1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/Support/raw_ostream.h"
23 class X86MCCodeEmitter : public MCCodeEmitter {
24 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
25 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
26 const TargetMachine &TM;
27 const TargetInstrInfo &TII;
30 X86MCCodeEmitter(TargetMachine &tm, bool is64Bit)
31 : TM(tm), TII(*TM.getInstrInfo()) {
32 Is64BitMode = is64Bit;
35 ~X86MCCodeEmitter() {}
37 unsigned getNumFixupKinds() const {
41 MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
42 static MCFixupKindInfo Infos[] = {
43 { "reloc_pcrel_word", 0, 4 * 8 },
44 { "reloc_picrel_word", 0, 4 * 8 },
45 { "reloc_absolute_word", 0, 4 * 8 },
46 { "reloc_absolute_word_sext", 0, 4 * 8 },
47 { "reloc_absolute_dword", 0, 8 * 8 }
50 assert(Kind >= FirstTargetFixupKind && Kind < MaxTargetFixupKind &&
52 return Infos[Kind - FirstTargetFixupKind];
55 static unsigned GetX86RegNum(const MCOperand &MO) {
56 return X86RegisterInfo::getX86RegNum(MO.getReg());
59 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
64 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
65 raw_ostream &OS) const {
66 // Output the constant in little endian byte order.
67 for (unsigned i = 0; i != Size; ++i) {
68 EmitByte(Val & 255, CurByte, OS);
73 void EmitDisplacementField(const MCOperand &Disp, int64_t Adj, bool IsPCRel,
74 unsigned &CurByte, raw_ostream &OS) const;
76 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
78 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
79 return RM | (RegOpcode << 3) | (Mod << 6);
82 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
83 unsigned &CurByte, raw_ostream &OS) const {
84 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
87 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
88 unsigned &CurByte, raw_ostream &OS) const {
89 // SIB byte is in the same format as the ModRMByte.
90 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
94 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
95 unsigned RegOpcodeField, intptr_t PCAdj,
96 unsigned &CurByte, raw_ostream &OS) const;
98 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
99 SmallVectorImpl<MCFixup> &Fixups) const;
103 } // end anonymous namespace
106 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
108 return new X86MCCodeEmitter(TM, false);
111 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
113 return new X86MCCodeEmitter(TM, true);
117 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
118 /// sign-extended field.
119 static bool isDisp8(int Value) {
120 return Value == (signed char)Value;
123 void X86MCCodeEmitter::
124 EmitDisplacementField(const MCOperand &DispOp, int64_t Adj, bool IsPCRel,
125 unsigned &CurByte, raw_ostream &OS) const {
126 // If this is a simple integer displacement that doesn't require a relocation,
128 if (DispOp.isImm()) {
129 EmitConstant(DispOp.getImm(), 4, CurByte, OS);
134 // Emit a symbolic constant as 4 0's and a Fixup.
135 EmitConstant(0, 4, CurByte, OS);
138 assert(0 && "Reloc not handled yet");
140 // Otherwise, this is something that requires a relocation. Emit it as such
142 unsigned RelocType = Is64BitMode ?
143 (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
144 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
145 if (RelocOp->isGlobal()) {
146 // In 64-bit static small code model, we could potentially emit absolute.
147 // But it's probably not beneficial. If the MCE supports using RIP directly
148 // do it, otherwise fallback to absolute (this is determined by IsPCRel).
149 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
150 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
151 bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM);
152 emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(),
154 } else if (RelocOp->isSymbol()) {
155 emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType);
156 } else if (RelocOp->isCPI()) {
157 emitConstPoolAddress(RelocOp->getIndex(), RelocType,
158 RelocOp->getOffset(), Adj);
160 assert(RelocOp->isJTI() && "Unexpected machine operand!");
161 emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj);
167 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
168 unsigned RegOpcodeField,
171 raw_ostream &OS) const {
172 const MCOperand &Disp = MI.getOperand(Op+3);
173 const MCOperand &Base = MI.getOperand(Op);
174 const MCOperand &Scale = MI.getOperand(Op+1);
175 const MCOperand &IndexReg = MI.getOperand(Op+2);
176 unsigned BaseReg = Base.getReg();
179 bool IsPCRel = false;
181 // Determine whether a SIB byte is needed.
182 // If no BaseReg, issue a RIP relative instruction only if the MCE can
183 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
184 // 2-7) and absolute references.
185 if (// The SIB byte must be used if there is an index register.
186 IndexReg.getReg() == 0 &&
187 // The SIB byte must be used if the base is ESP/RSP.
188 BaseReg != X86::ESP && BaseReg != X86::RSP &&
189 // If there is no base register and we're in 64-bit mode, we need a SIB
190 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
191 (!Is64BitMode || BaseReg != 0)) {
193 if (BaseReg == 0 || // [disp32] in X86-32 mode
194 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
195 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
196 EmitDisplacementField(Disp, PCAdj, true, CurByte, OS);
200 unsigned BaseRegNo = GetX86RegNum(Base);
202 // If the base is not EBP/ESP and there is no displacement, use simple
203 // indirect register encoding, this handles addresses like [EAX]. The
204 // encoding for [EBP] with no displacement means [disp32] so we handle it
205 // by emitting a displacement of 0 below.
206 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
207 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
211 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
212 if (Disp.isImm() && isDisp8(Disp.getImm())) {
213 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
214 EmitConstant(Disp.getImm(), 1, CurByte, OS);
218 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
219 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
220 EmitDisplacementField(Disp, PCAdj, IsPCRel, CurByte, OS);
224 // We need a SIB byte, so start by outputting the ModR/M byte first
225 assert(IndexReg.getReg() != X86::ESP &&
226 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
228 bool ForceDisp32 = false;
229 bool ForceDisp8 = false;
231 // If there is no base register, we emit the special case SIB byte with
232 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
233 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
235 } else if (!Disp.isImm()) {
236 // Emit the normal disp32 encoding.
237 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
239 } else if (Disp.getImm() == 0 && BaseReg != X86::EBP) {
240 // Emit no displacement ModR/M byte
241 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
242 } else if (isDisp8(Disp.getImm())) {
243 // Emit the disp8 encoding.
244 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
245 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
247 // Emit the normal disp32 encoding.
248 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
251 // Calculate what the SS field value should be...
252 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
253 unsigned SS = SSTable[Scale.getImm()];
256 // Handle the SIB byte for the case where there is no base, see Intel
257 // Manual 2A, table 2-7. The displacement has already been output.
259 if (IndexReg.getReg())
260 IndexRegNo = GetX86RegNum(IndexReg);
261 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
263 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
266 if (IndexReg.getReg())
267 IndexRegNo = GetX86RegNum(IndexReg);
269 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
270 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
273 // Do we need to output a displacement?
275 EmitConstant(Disp.getImm(), 1, CurByte, OS);
276 else if (ForceDisp32 || Disp.getImm() != 0)
277 EmitDisplacementField(Disp, PCAdj, IsPCRel, CurByte, OS);
280 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
281 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
282 /// size, and 3) use of X86-64 extended registers.
283 static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
284 const TargetInstrDesc &Desc) {
287 // Pseudo instructions do not need REX prefix byte.
288 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
290 if (TSFlags & X86II::REX_W)
293 if (MI.getNumOperands() == 0) return REX;
295 unsigned NumOps = MI.getNumOperands();
296 // FIXME: MCInst should explicitize the two-addrness.
297 bool isTwoAddr = NumOps > 1 &&
298 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
300 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
301 unsigned i = isTwoAddr ? 1 : 0;
302 for (; i != NumOps; ++i) {
303 const MCOperand &MO = MI.getOperand(i);
304 if (!MO.isReg()) continue;
305 unsigned Reg = MO.getReg();
306 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
307 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
308 // that returns non-zero.
313 switch (TSFlags & X86II::FormMask) {
314 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
315 case X86II::MRMSrcReg:
316 if (MI.getOperand(0).isReg() &&
317 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
319 i = isTwoAddr ? 2 : 1;
320 for (; i != NumOps; ++i) {
321 const MCOperand &MO = MI.getOperand(i);
322 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
326 case X86II::MRMSrcMem: {
327 if (MI.getOperand(0).isReg() &&
328 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
331 i = isTwoAddr ? 2 : 1;
332 for (; i != NumOps; ++i) {
333 const MCOperand &MO = MI.getOperand(i);
335 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
342 case X86II::MRM0m: case X86II::MRM1m:
343 case X86II::MRM2m: case X86II::MRM3m:
344 case X86II::MRM4m: case X86II::MRM5m:
345 case X86II::MRM6m: case X86II::MRM7m:
346 case X86II::MRMDestMem: {
347 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
348 i = isTwoAddr ? 1 : 0;
349 if (NumOps > e && MI.getOperand(e).isReg() &&
350 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
353 for (; i != e; ++i) {
354 const MCOperand &MO = MI.getOperand(i);
356 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
364 if (MI.getOperand(0).isReg() &&
365 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
367 i = isTwoAddr ? 2 : 1;
368 for (unsigned e = NumOps; i != e; ++i) {
369 const MCOperand &MO = MI.getOperand(i);
370 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
378 void X86MCCodeEmitter::
379 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
380 SmallVectorImpl<MCFixup> &Fixups) const {
381 unsigned Opcode = MI.getOpcode();
382 const TargetInstrDesc &Desc = TII.get(Opcode);
383 unsigned TSFlags = Desc.TSFlags;
385 // Keep track of the current byte being emitted.
386 unsigned CurByte = 0;
388 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
389 // in order to provide diffability.
391 // Emit the lock opcode prefix as needed.
392 if (TSFlags & X86II::LOCK)
393 EmitByte(0xF0, CurByte, OS);
395 // Emit segment override opcode prefix as needed.
396 switch (TSFlags & X86II::SegOvrMask) {
397 default: assert(0 && "Invalid segment!");
398 case 0: break; // No segment override!
400 EmitByte(0x64, CurByte, OS);
403 EmitByte(0x65, CurByte, OS);
407 // Emit the repeat opcode prefix as needed.
408 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
409 EmitByte(0xF3, CurByte, OS);
411 // Emit the operand size opcode prefix as needed.
412 if (TSFlags & X86II::OpSize)
413 EmitByte(0x66, CurByte, OS);
415 // Emit the address size opcode prefix as needed.
416 if (TSFlags & X86II::AdSize)
417 EmitByte(0x67, CurByte, OS);
419 bool Need0FPrefix = false;
420 switch (TSFlags & X86II::Op0Mask) {
421 default: assert(0 && "Invalid prefix!");
422 case 0: break; // No prefix!
423 case X86II::REP: break; // already handled.
424 case X86II::TB: // Two-byte opcode prefix
425 case X86II::T8: // 0F 38
426 case X86II::TA: // 0F 3A
429 case X86II::TF: // F2 0F 38
430 EmitByte(0xF2, CurByte, OS);
433 case X86II::XS: // F3 0F
434 EmitByte(0xF3, CurByte, OS);
437 case X86II::XD: // F2 0F
438 EmitByte(0xF2, CurByte, OS);
441 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
442 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
443 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
444 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
445 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
446 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
447 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
448 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
451 // Handle REX prefix.
452 // FIXME: Can this come before F2 etc to simplify emission?
454 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
455 EmitByte(0x40 | REX, CurByte, OS);
458 // 0x0F escape code must be emitted just before the opcode.
460 EmitByte(0x0F, CurByte, OS);
462 // FIXME: Pull this up into previous switch if REX can be moved earlier.
463 switch (TSFlags & X86II::Op0Mask) {
464 case X86II::TF: // F2 0F 38
465 case X86II::T8: // 0F 38
466 EmitByte(0x38, CurByte, OS);
468 case X86II::TA: // 0F 3A
469 EmitByte(0x3A, CurByte, OS);
473 // If this is a two-address instruction, skip one of the register operands.
474 unsigned NumOps = Desc.getNumOperands();
476 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
478 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
479 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
482 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
483 switch (TSFlags & X86II::FormMask) {
484 case X86II::MRMInitReg:
485 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
486 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
487 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
488 case X86II::RawFrm: {
489 EmitByte(BaseOpcode, CurByte, OS);
494 assert(0 && "Unimpl RawFrm expr");
498 case X86II::AddRegFrm: {
499 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
503 const MCOperand &MO1 = MI.getOperand(CurOp++);
505 unsigned Size = X86II::getSizeOfImm(TSFlags);
506 EmitConstant(MO1.getImm(), Size, CurByte, OS);
510 assert(0 && "Unimpl AddRegFrm expr");
514 case X86II::MRMDestReg:
515 EmitByte(BaseOpcode, CurByte, OS);
516 EmitRegModRMByte(MI.getOperand(CurOp),
517 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
520 EmitConstant(MI.getOperand(CurOp++).getImm(),
521 X86II::getSizeOfImm(TSFlags), CurByte, OS);
524 case X86II::MRMDestMem:
525 EmitByte(BaseOpcode, CurByte, OS);
526 EmitMemModRMByte(MI, CurOp,
527 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
529 CurOp += X86AddrNumOperands + 1;
531 EmitConstant(MI.getOperand(CurOp++).getImm(),
532 X86II::getSizeOfImm(TSFlags), CurByte, OS);
535 case X86II::MRMSrcReg:
536 EmitByte(BaseOpcode, CurByte, OS);
537 EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
541 EmitConstant(MI.getOperand(CurOp++).getImm(),
542 X86II::getSizeOfImm(TSFlags), CurByte, OS);
545 case X86II::MRMSrcMem: {
546 EmitByte(BaseOpcode, CurByte, OS);
548 // FIXME: Maybe lea should have its own form? This is a horrible hack.
550 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
551 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
552 AddrOperands = X86AddrNumOperands - 1; // No segment register
554 AddrOperands = X86AddrNumOperands;
556 // FIXME: What is this actually doing?
557 intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
558 X86II::getSizeOfImm(TSFlags) : 0;
560 EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
562 CurOp += AddrOperands + 1;
564 EmitConstant(MI.getOperand(CurOp++).getImm(),
565 X86II::getSizeOfImm(TSFlags), CurByte, OS);
569 case X86II::MRM0r: case X86II::MRM1r:
570 case X86II::MRM2r: case X86II::MRM3r:
571 case X86II::MRM4r: case X86II::MRM5r:
572 case X86II::MRM6r: case X86II::MRM7r: {
573 EmitByte(BaseOpcode, CurByte, OS);
575 // Special handling of lfence, mfence, monitor, and mwait.
576 // FIXME: This is terrible, they should get proper encoding bits in TSFlags.
577 if (Opcode == X86::LFENCE || Opcode == X86::MFENCE ||
578 Opcode == X86::MONITOR || Opcode == X86::MWAIT) {
579 EmitByte(ModRMByte(3, (TSFlags & X86II::FormMask)-X86II::MRM0r, 0),
584 case X86::MONITOR: EmitByte(0xC8, CurByte, OS); break;
585 case X86::MWAIT: EmitByte(0xC9, CurByte, OS); break;
588 EmitRegModRMByte(MI.getOperand(CurOp++),
589 (TSFlags & X86II::FormMask)-X86II::MRM0r,
596 const MCOperand &MO1 = MI.getOperand(CurOp++);
598 EmitConstant(MO1.getImm(), X86II::getSizeOfImm(TSFlags), CurByte, OS);
602 assert(0 && "relo unimpl");
604 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
605 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
606 if (Opcode == X86::MOV64ri32)
607 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
608 if (MO1.isGlobal()) {
609 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
610 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
612 } else if (MO1.isSymbol())
613 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
614 else if (MO1.isCPI())
615 emitConstPoolAddress(MO1.getIndex(), rt);
616 else if (MO1.isJTI())
617 emitJumpTableAddress(MO1.getIndex(), rt);
621 case X86II::MRM0m: case X86II::MRM1m:
622 case X86II::MRM2m: case X86II::MRM3m:
623 case X86II::MRM4m: case X86II::MRM5m:
624 case X86II::MRM6m: case X86II::MRM7m: {
626 if (CurOp + X86AddrNumOperands != NumOps) {
627 if (MI.getOperand(CurOp+X86AddrNumOperands).isImm())
628 PCAdj = X86II::getSizeOfImm(TSFlags);
633 EmitByte(BaseOpcode, CurByte, OS);
634 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
636 CurOp += X86AddrNumOperands;
641 const MCOperand &MO = MI.getOperand(CurOp++);
643 EmitConstant(MO.getImm(), X86II::getSizeOfImm(TSFlags), CurByte, OS);
647 assert(0 && "relo not handled");
649 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
650 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
651 if (Opcode == X86::MOV64mi32)
652 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
654 bool Indirect = gvNeedsNonLazyPtr(MO, TM);
655 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
657 } else if (MO.isSymbol())
658 emitExternalSymbolAddress(MO.getSymbolName(), rt);
660 emitConstPoolAddress(MO.getIndex(), rt);
662 emitJumpTableAddress(MO.getIndex(), rt);
670 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
671 errs() << "Cannot encode all operands of: ";