1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/Support/raw_ostream.h"
22 // FIXME: This should move to a header.
26 reloc_pcrel_word = FirstTargetFixupKind,
29 reloc_absolute_word_sext,
36 class X86MCCodeEmitter : public MCCodeEmitter {
37 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
38 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
39 const TargetMachine &TM;
40 const TargetInstrInfo &TII;
43 X86MCCodeEmitter(TargetMachine &tm, bool is64Bit)
44 : TM(tm), TII(*TM.getInstrInfo()) {
45 Is64BitMode = is64Bit;
48 ~X86MCCodeEmitter() {}
50 unsigned getNumFixupKinds() const {
54 MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
55 static MCFixupKindInfo Infos[] = {
56 { "reloc_pcrel_word", 0, 4 * 8 },
57 { "reloc_picrel_word", 0, 4 * 8 },
58 { "reloc_absolute_word", 0, 4 * 8 },
59 { "reloc_absolute_word_sext", 0, 4 * 8 },
60 { "reloc_absolute_dword", 0, 8 * 8 }
63 assert(Kind >= FirstTargetFixupKind && Kind < MaxTargetFixupKind &&
65 return Infos[Kind - FirstTargetFixupKind];
68 static unsigned GetX86RegNum(const MCOperand &MO) {
69 return X86RegisterInfo::getX86RegNum(MO.getReg());
72 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
77 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
78 raw_ostream &OS) const {
79 // Output the constant in little endian byte order.
80 for (unsigned i = 0; i != Size; ++i) {
81 EmitByte(Val & 255, CurByte, OS);
86 void EmitImmediate(const MCOperand &Disp, unsigned ImmSize,
87 unsigned &CurByte, raw_ostream &OS,
88 SmallVectorImpl<MCFixup> &Fixups) const;
90 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
92 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
93 return RM | (RegOpcode << 3) | (Mod << 6);
96 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
97 unsigned &CurByte, raw_ostream &OS) const {
98 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
101 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
102 unsigned &CurByte, raw_ostream &OS) const {
103 // SIB byte is in the same format as the ModRMByte.
104 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
108 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
109 unsigned RegOpcodeField,
110 unsigned &CurByte, raw_ostream &OS,
111 SmallVectorImpl<MCFixup> &Fixups) const;
113 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
114 SmallVectorImpl<MCFixup> &Fixups) const;
118 } // end anonymous namespace
121 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
123 return new X86MCCodeEmitter(TM, false);
126 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
128 return new X86MCCodeEmitter(TM, true);
132 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
133 /// sign-extended field.
134 static bool isDisp8(int Value) {
135 return Value == (signed char)Value;
138 void X86MCCodeEmitter::
139 EmitImmediate(const MCOperand &DispOp, unsigned Size,
140 unsigned &CurByte, raw_ostream &OS,
141 SmallVectorImpl<MCFixup> &Fixups) const {
142 // If this is a simple integer displacement that doesn't require a relocation,
144 if (DispOp.isImm()) {
145 EmitConstant(DispOp.getImm(), Size, CurByte, OS);
149 // FIXME: Pass in the relocation type.
151 unsigned RelocType = Is64BitMode ?
152 (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
153 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
156 // Emit a symbolic constant as a fixup and 4 zeros.
157 Fixups.push_back(MCFixup::Create(CurByte, DispOp.getExpr(),
158 MCFixupKind(X86::reloc_absolute_word)));
159 EmitConstant(0, Size, CurByte, OS);
163 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
164 unsigned RegOpcodeField,
167 SmallVectorImpl<MCFixup> &Fixups) const{
168 const MCOperand &Disp = MI.getOperand(Op+3);
169 const MCOperand &Base = MI.getOperand(Op);
170 const MCOperand &Scale = MI.getOperand(Op+1);
171 const MCOperand &IndexReg = MI.getOperand(Op+2);
172 unsigned BaseReg = Base.getReg();
174 // Determine whether a SIB byte is needed.
175 // If no BaseReg, issue a RIP relative instruction only if the MCE can
176 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
177 // 2-7) and absolute references.
178 if (// The SIB byte must be used if there is an index register.
179 IndexReg.getReg() == 0 &&
180 // The SIB byte must be used if the base is ESP/RSP.
181 BaseReg != X86::ESP && BaseReg != X86::RSP &&
182 // If there is no base register and we're in 64-bit mode, we need a SIB
183 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
184 (!Is64BitMode || BaseReg != 0)) {
186 if (BaseReg == 0 || // [disp32] in X86-32 mode
187 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
188 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
189 EmitImmediate(Disp, 4, CurByte, OS, Fixups);
193 unsigned BaseRegNo = GetX86RegNum(Base);
195 // If the base is not EBP/ESP and there is no displacement, use simple
196 // indirect register encoding, this handles addresses like [EAX]. The
197 // encoding for [EBP] with no displacement means [disp32] so we handle it
198 // by emitting a displacement of 0 below.
199 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
200 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
204 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
205 if (Disp.isImm() && isDisp8(Disp.getImm())) {
206 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
207 EmitConstant(Disp.getImm(), 1, CurByte, OS);
211 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
212 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
213 EmitImmediate(Disp, 4, CurByte, OS, Fixups);
217 // We need a SIB byte, so start by outputting the ModR/M byte first
218 assert(IndexReg.getReg() != X86::ESP &&
219 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
221 bool ForceDisp32 = false;
222 bool ForceDisp8 = false;
224 // If there is no base register, we emit the special case SIB byte with
225 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
226 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
228 } else if (!Disp.isImm()) {
229 // Emit the normal disp32 encoding.
230 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
232 } else if (Disp.getImm() == 0 && BaseReg != X86::EBP) {
233 // Emit no displacement ModR/M byte
234 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
235 } else if (isDisp8(Disp.getImm())) {
236 // Emit the disp8 encoding.
237 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
238 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
240 // Emit the normal disp32 encoding.
241 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
244 // Calculate what the SS field value should be...
245 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
246 unsigned SS = SSTable[Scale.getImm()];
249 // Handle the SIB byte for the case where there is no base, see Intel
250 // Manual 2A, table 2-7. The displacement has already been output.
252 if (IndexReg.getReg())
253 IndexRegNo = GetX86RegNum(IndexReg);
254 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
256 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
259 if (IndexReg.getReg())
260 IndexRegNo = GetX86RegNum(IndexReg);
262 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
263 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
266 // Do we need to output a displacement?
268 EmitImmediate(Disp, 1, CurByte, OS, Fixups);
269 else if (ForceDisp32 || Disp.getImm() != 0)
270 EmitImmediate(Disp, 4, CurByte, OS, Fixups);
273 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
274 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
275 /// size, and 3) use of X86-64 extended registers.
276 static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
277 const TargetInstrDesc &Desc) {
280 // Pseudo instructions do not need REX prefix byte.
281 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
283 if (TSFlags & X86II::REX_W)
286 if (MI.getNumOperands() == 0) return REX;
288 unsigned NumOps = MI.getNumOperands();
289 // FIXME: MCInst should explicitize the two-addrness.
290 bool isTwoAddr = NumOps > 1 &&
291 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
293 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
294 unsigned i = isTwoAddr ? 1 : 0;
295 for (; i != NumOps; ++i) {
296 const MCOperand &MO = MI.getOperand(i);
297 if (!MO.isReg()) continue;
298 unsigned Reg = MO.getReg();
299 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
300 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
301 // that returns non-zero.
306 switch (TSFlags & X86II::FormMask) {
307 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
308 case X86II::MRMSrcReg:
309 if (MI.getOperand(0).isReg() &&
310 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
312 i = isTwoAddr ? 2 : 1;
313 for (; i != NumOps; ++i) {
314 const MCOperand &MO = MI.getOperand(i);
315 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
319 case X86II::MRMSrcMem: {
320 if (MI.getOperand(0).isReg() &&
321 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
324 i = isTwoAddr ? 2 : 1;
325 for (; i != NumOps; ++i) {
326 const MCOperand &MO = MI.getOperand(i);
328 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
335 case X86II::MRM0m: case X86II::MRM1m:
336 case X86II::MRM2m: case X86II::MRM3m:
337 case X86II::MRM4m: case X86II::MRM5m:
338 case X86II::MRM6m: case X86II::MRM7m:
339 case X86II::MRMDestMem: {
340 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
341 i = isTwoAddr ? 1 : 0;
342 if (NumOps > e && MI.getOperand(e).isReg() &&
343 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
346 for (; i != e; ++i) {
347 const MCOperand &MO = MI.getOperand(i);
349 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
357 if (MI.getOperand(0).isReg() &&
358 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
360 i = isTwoAddr ? 2 : 1;
361 for (unsigned e = NumOps; i != e; ++i) {
362 const MCOperand &MO = MI.getOperand(i);
363 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
371 void X86MCCodeEmitter::
372 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
373 SmallVectorImpl<MCFixup> &Fixups) const {
374 unsigned Opcode = MI.getOpcode();
375 const TargetInstrDesc &Desc = TII.get(Opcode);
376 unsigned TSFlags = Desc.TSFlags;
378 // Keep track of the current byte being emitted.
379 unsigned CurByte = 0;
381 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
382 // in order to provide diffability.
384 // Emit the lock opcode prefix as needed.
385 if (TSFlags & X86II::LOCK)
386 EmitByte(0xF0, CurByte, OS);
388 // Emit segment override opcode prefix as needed.
389 switch (TSFlags & X86II::SegOvrMask) {
390 default: assert(0 && "Invalid segment!");
391 case 0: break; // No segment override!
393 EmitByte(0x64, CurByte, OS);
396 EmitByte(0x65, CurByte, OS);
400 // Emit the repeat opcode prefix as needed.
401 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
402 EmitByte(0xF3, CurByte, OS);
404 // Emit the operand size opcode prefix as needed.
405 if (TSFlags & X86II::OpSize)
406 EmitByte(0x66, CurByte, OS);
408 // Emit the address size opcode prefix as needed.
409 if (TSFlags & X86II::AdSize)
410 EmitByte(0x67, CurByte, OS);
412 bool Need0FPrefix = false;
413 switch (TSFlags & X86II::Op0Mask) {
414 default: assert(0 && "Invalid prefix!");
415 case 0: break; // No prefix!
416 case X86II::REP: break; // already handled.
417 case X86II::TB: // Two-byte opcode prefix
418 case X86II::T8: // 0F 38
419 case X86II::TA: // 0F 3A
422 case X86II::TF: // F2 0F 38
423 EmitByte(0xF2, CurByte, OS);
426 case X86II::XS: // F3 0F
427 EmitByte(0xF3, CurByte, OS);
430 case X86II::XD: // F2 0F
431 EmitByte(0xF2, CurByte, OS);
434 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
435 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
436 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
437 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
438 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
439 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
440 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
441 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
444 // Handle REX prefix.
445 // FIXME: Can this come before F2 etc to simplify emission?
447 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
448 EmitByte(0x40 | REX, CurByte, OS);
451 // 0x0F escape code must be emitted just before the opcode.
453 EmitByte(0x0F, CurByte, OS);
455 // FIXME: Pull this up into previous switch if REX can be moved earlier.
456 switch (TSFlags & X86II::Op0Mask) {
457 case X86II::TF: // F2 0F 38
458 case X86II::T8: // 0F 38
459 EmitByte(0x38, CurByte, OS);
461 case X86II::TA: // 0F 3A
462 EmitByte(0x3A, CurByte, OS);
466 // If this is a two-address instruction, skip one of the register operands.
467 unsigned NumOps = Desc.getNumOperands();
469 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
471 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
472 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
475 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
476 switch (TSFlags & X86II::FormMask) {
477 case X86II::MRMInitReg:
478 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
479 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
480 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
481 case X86II::RawFrm: {
482 EmitByte(BaseOpcode, CurByte, OS);
487 assert(0 && "Unimpl RawFrm expr");
491 case X86II::AddRegFrm: {
492 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
496 const MCOperand &MO1 = MI.getOperand(CurOp++);
498 unsigned Size = X86II::getSizeOfImm(TSFlags);
499 EmitConstant(MO1.getImm(), Size, CurByte, OS);
503 assert(0 && "Unimpl AddRegFrm expr");
507 case X86II::MRMDestReg:
508 EmitByte(BaseOpcode, CurByte, OS);
509 EmitRegModRMByte(MI.getOperand(CurOp),
510 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
513 EmitConstant(MI.getOperand(CurOp++).getImm(),
514 X86II::getSizeOfImm(TSFlags), CurByte, OS);
517 case X86II::MRMDestMem:
518 EmitByte(BaseOpcode, CurByte, OS);
519 EmitMemModRMByte(MI, CurOp,
520 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
521 CurByte, OS, Fixups);
522 CurOp += X86AddrNumOperands + 1;
524 EmitConstant(MI.getOperand(CurOp++).getImm(),
525 X86II::getSizeOfImm(TSFlags), CurByte, OS);
528 case X86II::MRMSrcReg:
529 EmitByte(BaseOpcode, CurByte, OS);
530 EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
534 EmitConstant(MI.getOperand(CurOp++).getImm(),
535 X86II::getSizeOfImm(TSFlags), CurByte, OS);
538 case X86II::MRMSrcMem: {
539 EmitByte(BaseOpcode, CurByte, OS);
541 // FIXME: Maybe lea should have its own form? This is a horrible hack.
543 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
544 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
545 AddrOperands = X86AddrNumOperands - 1; // No segment register
547 AddrOperands = X86AddrNumOperands;
549 EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
550 CurByte, OS, Fixups);
551 CurOp += AddrOperands + 1;
553 EmitConstant(MI.getOperand(CurOp++).getImm(),
554 X86II::getSizeOfImm(TSFlags), CurByte, OS);
558 case X86II::MRM0r: case X86II::MRM1r:
559 case X86II::MRM2r: case X86II::MRM3r:
560 case X86II::MRM4r: case X86II::MRM5r:
561 case X86II::MRM6r: case X86II::MRM7r: {
562 EmitByte(BaseOpcode, CurByte, OS);
564 // Special handling of lfence, mfence, monitor, and mwait.
565 // FIXME: This is terrible, they should get proper encoding bits in TSFlags.
566 if (Opcode == X86::LFENCE || Opcode == X86::MFENCE ||
567 Opcode == X86::MONITOR || Opcode == X86::MWAIT) {
568 EmitByte(ModRMByte(3, (TSFlags & X86II::FormMask)-X86II::MRM0r, 0),
573 case X86::MONITOR: EmitByte(0xC8, CurByte, OS); break;
574 case X86::MWAIT: EmitByte(0xC9, CurByte, OS); break;
577 EmitRegModRMByte(MI.getOperand(CurOp++),
578 (TSFlags & X86II::FormMask)-X86II::MRM0r,
585 const MCOperand &MO1 = MI.getOperand(CurOp++);
587 EmitConstant(MO1.getImm(), X86II::getSizeOfImm(TSFlags), CurByte, OS);
591 assert(0 && "relo unimpl");
593 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
594 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
595 if (Opcode == X86::MOV64ri32)
596 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
597 if (MO1.isGlobal()) {
598 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
599 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
601 } else if (MO1.isSymbol())
602 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
603 else if (MO1.isCPI())
604 emitConstPoolAddress(MO1.getIndex(), rt);
605 else if (MO1.isJTI())
606 emitJumpTableAddress(MO1.getIndex(), rt);
610 case X86II::MRM0m: case X86II::MRM1m:
611 case X86II::MRM2m: case X86II::MRM3m:
612 case X86II::MRM4m: case X86II::MRM5m:
613 case X86II::MRM6m: case X86II::MRM7m: {
614 EmitByte(BaseOpcode, CurByte, OS);
615 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
616 CurByte, OS, Fixups);
617 CurOp += X86AddrNumOperands;
622 const MCOperand &MO = MI.getOperand(CurOp++);
624 EmitConstant(MO.getImm(), X86II::getSizeOfImm(TSFlags), CurByte, OS);
628 assert(0 && "relo not handled");
630 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
631 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
632 if (Opcode == X86::MOV64mi32)
633 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
635 bool Indirect = gvNeedsNonLazyPtr(MO, TM);
636 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
638 } else if (MO.isSymbol())
639 emitExternalSymbolAddress(MO.getSymbolName(), rt);
641 emitConstPoolAddress(MO.getIndex(), rt);
643 emitJumpTableAddress(MO.getIndex(), rt);
651 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
652 errs() << "Cannot encode all operands of: ";