1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Support/raw_ostream.h"
23 // FIXME: This should move to a header.
27 reloc_pcrel_4byte = FirstTargetFixupKind, // 32-bit pcrel, e.g. a branch.
28 reloc_pcrel_1byte, // 8-bit pcrel, e.g. branch_1
29 reloc_riprel_4byte // 32-bit rip-relative
35 class X86MCCodeEmitter : public MCCodeEmitter {
36 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
37 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
38 const TargetMachine &TM;
39 const TargetInstrInfo &TII;
43 X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit)
44 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
45 Is64BitMode = is64Bit;
48 ~X86MCCodeEmitter() {}
50 unsigned getNumFixupKinds() const {
54 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
55 const static MCFixupKindInfo Infos[] = {
56 { "reloc_pcrel_4byte", 0, 4 * 8 },
57 { "reloc_pcrel_1byte", 0, 1 * 8 },
58 { "reloc_riprel_4byte", 0, 4 * 8 }
61 if (Kind < FirstTargetFixupKind)
62 return MCCodeEmitter::getFixupKindInfo(Kind);
64 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
66 return Infos[Kind - FirstTargetFixupKind];
69 static unsigned GetX86RegNum(const MCOperand &MO) {
70 return X86RegisterInfo::getX86RegNum(MO.getReg());
73 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
78 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
79 raw_ostream &OS) const {
80 // Output the constant in little endian byte order.
81 for (unsigned i = 0; i != Size; ++i) {
82 EmitByte(Val & 255, CurByte, OS);
87 void EmitImmediate(const MCOperand &Disp,
88 unsigned ImmSize, MCFixupKind FixupKind,
89 unsigned &CurByte, raw_ostream &OS,
90 SmallVectorImpl<MCFixup> &Fixups,
91 int ImmOffset = 0) const;
93 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
95 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
96 return RM | (RegOpcode << 3) | (Mod << 6);
99 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
100 unsigned &CurByte, raw_ostream &OS) const {
101 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
104 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
105 unsigned &CurByte, raw_ostream &OS) const {
106 // SIB byte is in the same format as the ModRMByte.
107 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
111 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
112 unsigned RegOpcodeField,
113 unsigned TSFlags, unsigned &CurByte, raw_ostream &OS,
114 SmallVectorImpl<MCFixup> &Fixups) const;
116 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
117 SmallVectorImpl<MCFixup> &Fixups) const;
121 } // end anonymous namespace
124 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
127 return new X86MCCodeEmitter(TM, Ctx, false);
130 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
133 return new X86MCCodeEmitter(TM, Ctx, true);
137 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
138 /// sign-extended field.
139 static bool isDisp8(int Value) {
140 return Value == (signed char)Value;
143 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
144 /// in an instruction with the specified TSFlags.
145 static MCFixupKind getImmFixupKind(unsigned TSFlags) {
146 unsigned Size = X86II::getSizeOfImm(TSFlags);
147 bool isPCRel = X86II::isImmPCRel(TSFlags);
150 default: assert(0 && "Unknown immediate size");
151 case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
152 case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
153 case 2: assert(!isPCRel); return FK_Data_2;
154 case 8: assert(!isPCRel); return FK_Data_8;
159 void X86MCCodeEmitter::
160 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
161 unsigned &CurByte, raw_ostream &OS,
162 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
163 // If this is a simple integer displacement that doesn't require a relocation,
165 if (DispOp.isImm()) {
166 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
170 // If we have an immoffset, add it to the expression.
171 const MCExpr *Expr = DispOp.getExpr();
173 Expr = MCBinaryExpr::CreateAdd(Expr,MCConstantExpr::Create(ImmOffset, Ctx),
176 // Emit a symbolic constant as a fixup and 4 zeros.
177 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
178 EmitConstant(0, Size, CurByte, OS);
182 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
183 unsigned RegOpcodeField,
184 unsigned TSFlags, unsigned &CurByte,
186 SmallVectorImpl<MCFixup> &Fixups) const{
187 const MCOperand &Disp = MI.getOperand(Op+3);
188 const MCOperand &Base = MI.getOperand(Op);
189 const MCOperand &Scale = MI.getOperand(Op+1);
190 const MCOperand &IndexReg = MI.getOperand(Op+2);
191 unsigned BaseReg = Base.getReg();
193 // Handle %rip relative addressing.
194 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
195 assert(IndexReg.getReg() == 0 && Is64BitMode &&
196 "Invalid rip-relative address");
197 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
199 // rip-relative addressing is actually relative to the *next* instruction.
200 // Since an immediate can follow the mod/rm byte for an instruction, this
201 // means that we need to bias the immediate field of the instruction with
202 // the size of the immediate field. If we have this case, add it into the
203 // expression to emit.
204 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
205 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_riprel_4byte),
206 CurByte, OS, Fixups, -ImmSize);
210 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
212 // Determine whether a SIB byte is needed.
213 // If no BaseReg, issue a RIP relative instruction only if the MCE can
214 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
215 // 2-7) and absolute references.
217 if (// The SIB byte must be used if there is an index register.
218 IndexReg.getReg() == 0 &&
219 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
220 // encode to an R/M value of 4, which indicates that a SIB byte is
222 BaseRegNo != N86::ESP &&
223 // If there is no base register and we're in 64-bit mode, we need a SIB
224 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
225 (!Is64BitMode || BaseReg != 0)) {
227 if (BaseReg == 0) { // [disp32] in X86-32 mode
228 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
229 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
233 // If the base is not EBP/ESP and there is no displacement, use simple
234 // indirect register encoding, this handles addresses like [EAX]. The
235 // encoding for [EBP] with no displacement means [disp32] so we handle it
236 // by emitting a displacement of 0 below.
237 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
238 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
242 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
243 if (Disp.isImm() && isDisp8(Disp.getImm())) {
244 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
245 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
249 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
250 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
251 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
255 // We need a SIB byte, so start by outputting the ModR/M byte first
256 assert(IndexReg.getReg() != X86::ESP &&
257 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
259 bool ForceDisp32 = false;
260 bool ForceDisp8 = false;
262 // If there is no base register, we emit the special case SIB byte with
263 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
264 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
266 } else if (!Disp.isImm()) {
267 // Emit the normal disp32 encoding.
268 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
270 } else if (Disp.getImm() == 0 && BaseReg != X86::EBP) {
271 // Emit no displacement ModR/M byte
272 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
273 } else if (isDisp8(Disp.getImm())) {
274 // Emit the disp8 encoding.
275 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
276 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
278 // Emit the normal disp32 encoding.
279 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
282 // Calculate what the SS field value should be...
283 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
284 unsigned SS = SSTable[Scale.getImm()];
287 // Handle the SIB byte for the case where there is no base, see Intel
288 // Manual 2A, table 2-7. The displacement has already been output.
290 if (IndexReg.getReg())
291 IndexRegNo = GetX86RegNum(IndexReg);
292 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
294 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
297 if (IndexReg.getReg())
298 IndexRegNo = GetX86RegNum(IndexReg);
300 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
301 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
304 // Do we need to output a displacement?
306 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
307 else if (ForceDisp32 || Disp.getImm() != 0)
308 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
311 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
312 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
313 /// size, and 3) use of X86-64 extended registers.
314 static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
315 const TargetInstrDesc &Desc) {
316 // Pseudo instructions shouldn't get here.
317 assert((TSFlags & X86II::FormMask) != X86II::Pseudo &&
318 "Can't encode pseudo instrs");
321 if (TSFlags & X86II::REX_W)
324 if (MI.getNumOperands() == 0) return REX;
326 unsigned NumOps = MI.getNumOperands();
327 // FIXME: MCInst should explicitize the two-addrness.
328 bool isTwoAddr = NumOps > 1 &&
329 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
331 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
332 unsigned i = isTwoAddr ? 1 : 0;
333 for (; i != NumOps; ++i) {
334 const MCOperand &MO = MI.getOperand(i);
335 if (!MO.isReg()) continue;
336 unsigned Reg = MO.getReg();
337 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
338 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
339 // that returns non-zero.
344 switch (TSFlags & X86II::FormMask) {
345 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
346 case X86II::MRMSrcReg:
347 if (MI.getOperand(0).isReg() &&
348 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
350 i = isTwoAddr ? 2 : 1;
351 for (; i != NumOps; ++i) {
352 const MCOperand &MO = MI.getOperand(i);
353 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
357 case X86II::MRMSrcMem: {
358 if (MI.getOperand(0).isReg() &&
359 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
362 i = isTwoAddr ? 2 : 1;
363 for (; i != NumOps; ++i) {
364 const MCOperand &MO = MI.getOperand(i);
366 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
373 case X86II::MRM0m: case X86II::MRM1m:
374 case X86II::MRM2m: case X86II::MRM3m:
375 case X86II::MRM4m: case X86II::MRM5m:
376 case X86II::MRM6m: case X86II::MRM7m:
377 case X86II::MRMDestMem: {
378 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
379 i = isTwoAddr ? 1 : 0;
380 if (NumOps > e && MI.getOperand(e).isReg() &&
381 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
384 for (; i != e; ++i) {
385 const MCOperand &MO = MI.getOperand(i);
387 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
395 if (MI.getOperand(0).isReg() &&
396 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
398 i = isTwoAddr ? 2 : 1;
399 for (unsigned e = NumOps; i != e; ++i) {
400 const MCOperand &MO = MI.getOperand(i);
401 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
409 void X86MCCodeEmitter::
410 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
411 SmallVectorImpl<MCFixup> &Fixups) const {
412 unsigned Opcode = MI.getOpcode();
413 const TargetInstrDesc &Desc = TII.get(Opcode);
414 unsigned TSFlags = Desc.TSFlags;
416 // Keep track of the current byte being emitted.
417 unsigned CurByte = 0;
419 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
420 // in order to provide diffability.
422 // Emit the lock opcode prefix as needed.
423 if (TSFlags & X86II::LOCK)
424 EmitByte(0xF0, CurByte, OS);
426 // Emit segment override opcode prefix as needed.
427 switch (TSFlags & X86II::SegOvrMask) {
428 default: assert(0 && "Invalid segment!");
429 case 0: break; // No segment override!
431 EmitByte(0x64, CurByte, OS);
434 EmitByte(0x65, CurByte, OS);
438 // Emit the repeat opcode prefix as needed.
439 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
440 EmitByte(0xF3, CurByte, OS);
442 // Emit the operand size opcode prefix as needed.
443 if (TSFlags & X86II::OpSize)
444 EmitByte(0x66, CurByte, OS);
446 // Emit the address size opcode prefix as needed.
447 if (TSFlags & X86II::AdSize)
448 EmitByte(0x67, CurByte, OS);
450 bool Need0FPrefix = false;
451 switch (TSFlags & X86II::Op0Mask) {
452 default: assert(0 && "Invalid prefix!");
453 case 0: break; // No prefix!
454 case X86II::REP: break; // already handled.
455 case X86II::TB: // Two-byte opcode prefix
456 case X86II::T8: // 0F 38
457 case X86II::TA: // 0F 3A
460 case X86II::TF: // F2 0F 38
461 EmitByte(0xF2, CurByte, OS);
464 case X86II::XS: // F3 0F
465 EmitByte(0xF3, CurByte, OS);
468 case X86II::XD: // F2 0F
469 EmitByte(0xF2, CurByte, OS);
472 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
473 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
474 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
475 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
476 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
477 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
478 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
479 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
482 // Handle REX prefix.
483 // FIXME: Can this come before F2 etc to simplify emission?
485 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
486 EmitByte(0x40 | REX, CurByte, OS);
489 // 0x0F escape code must be emitted just before the opcode.
491 EmitByte(0x0F, CurByte, OS);
493 // FIXME: Pull this up into previous switch if REX can be moved earlier.
494 switch (TSFlags & X86II::Op0Mask) {
495 case X86II::TF: // F2 0F 38
496 case X86II::T8: // 0F 38
497 EmitByte(0x38, CurByte, OS);
499 case X86II::TA: // 0F 3A
500 EmitByte(0x3A, CurByte, OS);
504 // If this is a two-address instruction, skip one of the register operands.
505 unsigned NumOps = Desc.getNumOperands();
507 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
509 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
510 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
513 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
514 switch (TSFlags & X86II::FormMask) {
515 case X86II::MRMInitReg:
516 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
517 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
518 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
520 EmitByte(BaseOpcode, CurByte, OS);
523 case X86II::AddRegFrm:
524 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
527 case X86II::MRMDestReg:
528 EmitByte(BaseOpcode, CurByte, OS);
529 EmitRegModRMByte(MI.getOperand(CurOp),
530 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
534 case X86II::MRMDestMem:
535 EmitByte(BaseOpcode, CurByte, OS);
536 EmitMemModRMByte(MI, CurOp,
537 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
538 TSFlags, CurByte, OS, Fixups);
539 CurOp += X86AddrNumOperands + 1;
542 case X86II::MRMSrcReg:
543 EmitByte(BaseOpcode, CurByte, OS);
544 EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
549 case X86II::MRMSrcMem: {
550 EmitByte(BaseOpcode, CurByte, OS);
552 // FIXME: Maybe lea should have its own form? This is a horrible hack.
554 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
555 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
556 AddrOperands = X86AddrNumOperands - 1; // No segment register
558 AddrOperands = X86AddrNumOperands;
560 EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
561 TSFlags, CurByte, OS, Fixups);
562 CurOp += AddrOperands + 1;
566 case X86II::MRM0r: case X86II::MRM1r:
567 case X86II::MRM2r: case X86II::MRM3r:
568 case X86II::MRM4r: case X86II::MRM5r:
569 case X86II::MRM6r: case X86II::MRM7r:
570 EmitByte(BaseOpcode, CurByte, OS);
572 // Special handling of lfence, mfence, monitor, and mwait.
573 // FIXME: This is terrible, they should get proper encoding bits in TSFlags.
574 if (Opcode == X86::LFENCE || Opcode == X86::MFENCE ||
575 Opcode == X86::MONITOR || Opcode == X86::MWAIT) {
576 EmitByte(ModRMByte(3, (TSFlags & X86II::FormMask)-X86II::MRM0r,
577 Opcode == X86::MWAIT),
580 EmitRegModRMByte(MI.getOperand(CurOp++),
581 (TSFlags & X86II::FormMask)-X86II::MRM0r,
585 case X86II::MRM0m: case X86II::MRM1m:
586 case X86II::MRM2m: case X86II::MRM3m:
587 case X86II::MRM4m: case X86II::MRM5m:
588 case X86II::MRM6m: case X86II::MRM7m:
589 EmitByte(BaseOpcode, CurByte, OS);
590 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
591 TSFlags, CurByte, OS, Fixups);
592 CurOp += X86AddrNumOperands;
595 EmitByte(BaseOpcode, CurByte, OS);
596 EmitByte(0xC1, CurByte, OS);
599 EmitByte(BaseOpcode, CurByte, OS);
600 EmitByte(0xC8, CurByte, OS);
603 EmitByte(BaseOpcode, CurByte, OS);
604 EmitByte(0xC9, CurByte, OS);
607 EmitByte(BaseOpcode, CurByte, OS);
608 EmitByte(0xE8, CurByte, OS);
611 EmitByte(BaseOpcode, CurByte, OS);
612 EmitByte(0xF0, CurByte, OS);
616 // If there is a remaining operand, it must be a trailing immediate. Emit it
617 // according to the right size for the instruction.
618 // FIXME: This should pass in whether the value is pc relative or not. This
619 // information should be aquired from TSFlags as well.
621 EmitImmediate(MI.getOperand(CurOp++),
622 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
623 CurByte, OS, Fixups);
627 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
628 errs() << "Cannot encode all operands of: ";