1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/Support/raw_ostream.h"
22 // FIXME: This should move to a header.
26 // FIXME: This is just a stub.
27 fixup_1byte_imm = FirstTargetFixupKind,
36 class X86MCCodeEmitter : public MCCodeEmitter {
37 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
38 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
39 const TargetMachine &TM;
40 const TargetInstrInfo &TII;
43 X86MCCodeEmitter(TargetMachine &tm, bool is64Bit)
44 : TM(tm), TII(*TM.getInstrInfo()) {
45 Is64BitMode = is64Bit;
48 ~X86MCCodeEmitter() {}
50 unsigned getNumFixupKinds() const {
54 MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
55 static MCFixupKindInfo Infos[] = {
56 { "fixup_1byte_imm", 0, 1 * 8 },
57 { "fixup_2byte_imm", 0, 2 * 8 },
58 { "fixup_4byte_imm", 0, 4 * 8 },
59 { "fixup_8byte_imm", 0, 8 * 8 }
62 assert(Kind >= FirstTargetFixupKind && Kind < MaxTargetFixupKind &&
64 return Infos[Kind - FirstTargetFixupKind];
67 static unsigned GetX86RegNum(const MCOperand &MO) {
68 return X86RegisterInfo::getX86RegNum(MO.getReg());
71 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
76 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
77 raw_ostream &OS) const {
78 // Output the constant in little endian byte order.
79 for (unsigned i = 0; i != Size; ++i) {
80 EmitByte(Val & 255, CurByte, OS);
85 void EmitImmediate(const MCOperand &Disp, unsigned ImmSize,
86 unsigned &CurByte, raw_ostream &OS,
87 SmallVectorImpl<MCFixup> &Fixups) const;
89 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
91 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
92 return RM | (RegOpcode << 3) | (Mod << 6);
95 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
96 unsigned &CurByte, raw_ostream &OS) const {
97 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
100 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
101 unsigned &CurByte, raw_ostream &OS) const {
102 // SIB byte is in the same format as the ModRMByte.
103 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
107 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
108 unsigned RegOpcodeField,
109 unsigned &CurByte, raw_ostream &OS,
110 SmallVectorImpl<MCFixup> &Fixups) const;
112 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
113 SmallVectorImpl<MCFixup> &Fixups) const;
117 } // end anonymous namespace
120 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
122 return new X86MCCodeEmitter(TM, false);
125 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
127 return new X86MCCodeEmitter(TM, true);
131 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
132 /// sign-extended field.
133 static bool isDisp8(int Value) {
134 return Value == (signed char)Value;
137 void X86MCCodeEmitter::
138 EmitImmediate(const MCOperand &DispOp, unsigned Size,
139 unsigned &CurByte, raw_ostream &OS,
140 SmallVectorImpl<MCFixup> &Fixups) const {
141 // If this is a simple integer displacement that doesn't require a relocation,
143 if (DispOp.isImm()) {
144 EmitConstant(DispOp.getImm(), Size, CurByte, OS);
148 // FIXME: Pass in the relocation type, this is just a hack..
151 FixupKind = X86::fixup_1byte_imm;
153 FixupKind = X86::fixup_2byte_imm;
155 FixupKind = X86::fixup_4byte_imm;
157 assert(Size == 8 && "Unknown immediate size");
158 FixupKind = X86::fixup_8byte_imm;
161 // Emit a symbolic constant as a fixup and 4 zeros.
162 Fixups.push_back(MCFixup::Create(CurByte, DispOp.getExpr(),
163 MCFixupKind(FixupKind)));
164 EmitConstant(0, Size, CurByte, OS);
168 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
169 unsigned RegOpcodeField,
172 SmallVectorImpl<MCFixup> &Fixups) const{
173 const MCOperand &Disp = MI.getOperand(Op+3);
174 const MCOperand &Base = MI.getOperand(Op);
175 const MCOperand &Scale = MI.getOperand(Op+1);
176 const MCOperand &IndexReg = MI.getOperand(Op+2);
177 unsigned BaseReg = Base.getReg();
178 unsigned BaseRegNo = -1U;
179 if (BaseReg != 0 && BaseReg != X86::RIP)
180 BaseRegNo = GetX86RegNum(Base);
182 // Determine whether a SIB byte is needed.
183 // If no BaseReg, issue a RIP relative instruction only if the MCE can
184 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
185 // 2-7) and absolute references.
187 if (// The SIB byte must be used if there is an index register.
188 IndexReg.getReg() == 0 &&
189 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
190 // encode to an R/M value of 4, which indicates that a SIB byte is
192 BaseRegNo != N86::ESP &&
193 // If there is no base register and we're in 64-bit mode, we need a SIB
194 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
195 (!Is64BitMode || BaseReg != 0)) {
197 if (BaseReg == 0 || // [disp32] in X86-32 mode
198 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
199 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
200 EmitImmediate(Disp, 4, CurByte, OS, Fixups);
204 // If the base is not EBP/ESP and there is no displacement, use simple
205 // indirect register encoding, this handles addresses like [EAX]. The
206 // encoding for [EBP] with no displacement means [disp32] so we handle it
207 // by emitting a displacement of 0 below.
208 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
209 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
213 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
214 if (Disp.isImm() && isDisp8(Disp.getImm())) {
215 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
216 EmitImmediate(Disp, 1, CurByte, OS, Fixups);
220 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
221 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
222 EmitImmediate(Disp, 4, CurByte, OS, Fixups);
226 // We need a SIB byte, so start by outputting the ModR/M byte first
227 assert(IndexReg.getReg() != X86::ESP &&
228 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
230 bool ForceDisp32 = false;
231 bool ForceDisp8 = false;
233 // If there is no base register, we emit the special case SIB byte with
234 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
235 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
237 } else if (!Disp.isImm()) {
238 // Emit the normal disp32 encoding.
239 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
241 } else if (Disp.getImm() == 0 && BaseReg != X86::EBP) {
242 // Emit no displacement ModR/M byte
243 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
244 } else if (isDisp8(Disp.getImm())) {
245 // Emit the disp8 encoding.
246 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
247 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
249 // Emit the normal disp32 encoding.
250 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
253 // Calculate what the SS field value should be...
254 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
255 unsigned SS = SSTable[Scale.getImm()];
258 // Handle the SIB byte for the case where there is no base, see Intel
259 // Manual 2A, table 2-7. The displacement has already been output.
261 if (IndexReg.getReg())
262 IndexRegNo = GetX86RegNum(IndexReg);
263 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
265 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
268 if (IndexReg.getReg())
269 IndexRegNo = GetX86RegNum(IndexReg);
271 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
272 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
275 // Do we need to output a displacement?
277 EmitImmediate(Disp, 1, CurByte, OS, Fixups);
278 else if (ForceDisp32 || Disp.getImm() != 0)
279 EmitImmediate(Disp, 4, CurByte, OS, Fixups);
282 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
283 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
284 /// size, and 3) use of X86-64 extended registers.
285 static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
286 const TargetInstrDesc &Desc) {
289 // Pseudo instructions do not need REX prefix byte.
290 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
292 if (TSFlags & X86II::REX_W)
295 if (MI.getNumOperands() == 0) return REX;
297 unsigned NumOps = MI.getNumOperands();
298 // FIXME: MCInst should explicitize the two-addrness.
299 bool isTwoAddr = NumOps > 1 &&
300 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
302 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
303 unsigned i = isTwoAddr ? 1 : 0;
304 for (; i != NumOps; ++i) {
305 const MCOperand &MO = MI.getOperand(i);
306 if (!MO.isReg()) continue;
307 unsigned Reg = MO.getReg();
308 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
309 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
310 // that returns non-zero.
315 switch (TSFlags & X86II::FormMask) {
316 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
317 case X86II::MRMSrcReg:
318 if (MI.getOperand(0).isReg() &&
319 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
321 i = isTwoAddr ? 2 : 1;
322 for (; i != NumOps; ++i) {
323 const MCOperand &MO = MI.getOperand(i);
324 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
328 case X86II::MRMSrcMem: {
329 if (MI.getOperand(0).isReg() &&
330 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
333 i = isTwoAddr ? 2 : 1;
334 for (; i != NumOps; ++i) {
335 const MCOperand &MO = MI.getOperand(i);
337 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
344 case X86II::MRM0m: case X86II::MRM1m:
345 case X86II::MRM2m: case X86II::MRM3m:
346 case X86II::MRM4m: case X86II::MRM5m:
347 case X86II::MRM6m: case X86II::MRM7m:
348 case X86II::MRMDestMem: {
349 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
350 i = isTwoAddr ? 1 : 0;
351 if (NumOps > e && MI.getOperand(e).isReg() &&
352 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
355 for (; i != e; ++i) {
356 const MCOperand &MO = MI.getOperand(i);
358 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
366 if (MI.getOperand(0).isReg() &&
367 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
369 i = isTwoAddr ? 2 : 1;
370 for (unsigned e = NumOps; i != e; ++i) {
371 const MCOperand &MO = MI.getOperand(i);
372 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
380 void X86MCCodeEmitter::
381 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
382 SmallVectorImpl<MCFixup> &Fixups) const {
383 unsigned Opcode = MI.getOpcode();
384 const TargetInstrDesc &Desc = TII.get(Opcode);
385 unsigned TSFlags = Desc.TSFlags;
387 // Keep track of the current byte being emitted.
388 unsigned CurByte = 0;
390 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
391 // in order to provide diffability.
393 // Emit the lock opcode prefix as needed.
394 if (TSFlags & X86II::LOCK)
395 EmitByte(0xF0, CurByte, OS);
397 // Emit segment override opcode prefix as needed.
398 switch (TSFlags & X86II::SegOvrMask) {
399 default: assert(0 && "Invalid segment!");
400 case 0: break; // No segment override!
402 EmitByte(0x64, CurByte, OS);
405 EmitByte(0x65, CurByte, OS);
409 // Emit the repeat opcode prefix as needed.
410 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
411 EmitByte(0xF3, CurByte, OS);
413 // Emit the operand size opcode prefix as needed.
414 if (TSFlags & X86II::OpSize)
415 EmitByte(0x66, CurByte, OS);
417 // Emit the address size opcode prefix as needed.
418 if (TSFlags & X86II::AdSize)
419 EmitByte(0x67, CurByte, OS);
421 bool Need0FPrefix = false;
422 switch (TSFlags & X86II::Op0Mask) {
423 default: assert(0 && "Invalid prefix!");
424 case 0: break; // No prefix!
425 case X86II::REP: break; // already handled.
426 case X86II::TB: // Two-byte opcode prefix
427 case X86II::T8: // 0F 38
428 case X86II::TA: // 0F 3A
431 case X86II::TF: // F2 0F 38
432 EmitByte(0xF2, CurByte, OS);
435 case X86II::XS: // F3 0F
436 EmitByte(0xF3, CurByte, OS);
439 case X86II::XD: // F2 0F
440 EmitByte(0xF2, CurByte, OS);
443 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
444 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
445 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
446 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
447 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
448 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
449 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
450 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
453 // Handle REX prefix.
454 // FIXME: Can this come before F2 etc to simplify emission?
456 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
457 EmitByte(0x40 | REX, CurByte, OS);
460 // 0x0F escape code must be emitted just before the opcode.
462 EmitByte(0x0F, CurByte, OS);
464 // FIXME: Pull this up into previous switch if REX can be moved earlier.
465 switch (TSFlags & X86II::Op0Mask) {
466 case X86II::TF: // F2 0F 38
467 case X86II::T8: // 0F 38
468 EmitByte(0x38, CurByte, OS);
470 case X86II::TA: // 0F 3A
471 EmitByte(0x3A, CurByte, OS);
475 // If this is a two-address instruction, skip one of the register operands.
476 unsigned NumOps = Desc.getNumOperands();
478 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
480 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
481 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
484 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
485 switch (TSFlags & X86II::FormMask) {
486 case X86II::MRMInitReg:
487 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
488 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
489 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
491 EmitByte(BaseOpcode, CurByte, OS);
494 case X86II::AddRegFrm:
495 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
498 case X86II::MRMDestReg:
499 EmitByte(BaseOpcode, CurByte, OS);
500 EmitRegModRMByte(MI.getOperand(CurOp),
501 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
505 case X86II::MRMDestMem:
506 EmitByte(BaseOpcode, CurByte, OS);
507 EmitMemModRMByte(MI, CurOp,
508 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
509 CurByte, OS, Fixups);
510 CurOp += X86AddrNumOperands + 1;
513 case X86II::MRMSrcReg:
514 EmitByte(BaseOpcode, CurByte, OS);
515 EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
520 case X86II::MRMSrcMem: {
521 EmitByte(BaseOpcode, CurByte, OS);
523 // FIXME: Maybe lea should have its own form? This is a horrible hack.
525 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
526 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
527 AddrOperands = X86AddrNumOperands - 1; // No segment register
529 AddrOperands = X86AddrNumOperands;
531 EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
532 CurByte, OS, Fixups);
533 CurOp += AddrOperands + 1;
537 case X86II::MRM0r: case X86II::MRM1r:
538 case X86II::MRM2r: case X86II::MRM3r:
539 case X86II::MRM4r: case X86II::MRM5r:
540 case X86II::MRM6r: case X86II::MRM7r:
541 EmitByte(BaseOpcode, CurByte, OS);
543 // Special handling of lfence, mfence, monitor, and mwait.
544 // FIXME: This is terrible, they should get proper encoding bits in TSFlags.
545 if (Opcode == X86::LFENCE || Opcode == X86::MFENCE ||
546 Opcode == X86::MONITOR || Opcode == X86::MWAIT) {
547 EmitByte(ModRMByte(3, (TSFlags & X86II::FormMask)-X86II::MRM0r, 0),
552 case X86::MONITOR: EmitByte(0xC8, CurByte, OS); break;
553 case X86::MWAIT: EmitByte(0xC9, CurByte, OS); break;
556 EmitRegModRMByte(MI.getOperand(CurOp++),
557 (TSFlags & X86II::FormMask)-X86II::MRM0r,
561 case X86II::MRM0m: case X86II::MRM1m:
562 case X86II::MRM2m: case X86II::MRM3m:
563 case X86II::MRM4m: case X86II::MRM5m:
564 case X86II::MRM6m: case X86II::MRM7m:
565 EmitByte(BaseOpcode, CurByte, OS);
566 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
567 CurByte, OS, Fixups);
568 CurOp += X86AddrNumOperands;
572 // If there is a remaining operand, it must be a trailing immediate. Emit it
573 // according to the right size for the instruction.
574 // FIXME: This should pass in whether the value is pc relative or not. This
575 // information should be aquired from TSFlags as well.
577 EmitImmediate(MI.getOperand(CurOp++), X86II::getSizeOfImm(TSFlags),
578 CurByte, OS, Fixups);
582 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
583 errs() << "Cannot encode all operands of: ";