1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/Support/raw_ostream.h"
25 class X86MCCodeEmitter : public MCCodeEmitter {
26 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
27 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
28 const TargetMachine &TM;
29 const TargetInstrInfo &TII;
33 X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit)
34 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
35 Is64BitMode = is64Bit;
38 ~X86MCCodeEmitter() {}
40 unsigned getNumFixupKinds() const {
44 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
45 const static MCFixupKindInfo Infos[] = {
46 { "reloc_pcrel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
47 { "reloc_pcrel_1byte", 0, 1 * 8, MCFixupKindInfo::FKF_IsPCRel },
48 { "reloc_pcrel_2byte", 0, 2 * 8, MCFixupKindInfo::FKF_IsPCRel },
49 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
50 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel }
53 if (Kind < FirstTargetFixupKind)
54 return MCCodeEmitter::getFixupKindInfo(Kind);
56 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
58 return Infos[Kind - FirstTargetFixupKind];
61 static unsigned GetX86RegNum(const MCOperand &MO) {
62 return X86RegisterInfo::getX86RegNum(MO.getReg());
65 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
66 // 0-7 and the difference between the 2 groups is given by the REX prefix.
67 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
68 // in 1's complement form, example:
70 // ModRM field => XMM9 => 1
71 // VEX.VVVV => XMM9 => ~9
73 // See table 4-35 of Intel AVX Programming Reference for details.
74 static unsigned char getVEXRegisterEncoding(const MCInst &MI,
76 unsigned SrcReg = MI.getOperand(OpNum).getReg();
77 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
78 if (SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15)
81 // The registers represented through VEX_VVVV should
82 // be encoded in 1's complement form.
83 return (~SrcRegNum) & 0xf;
86 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
91 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
92 raw_ostream &OS) const {
93 // Output the constant in little endian byte order.
94 for (unsigned i = 0; i != Size; ++i) {
95 EmitByte(Val & 255, CurByte, OS);
100 void EmitImmediate(const MCOperand &Disp,
101 unsigned ImmSize, MCFixupKind FixupKind,
102 unsigned &CurByte, raw_ostream &OS,
103 SmallVectorImpl<MCFixup> &Fixups,
104 int ImmOffset = 0) const;
106 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
108 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
109 return RM | (RegOpcode << 3) | (Mod << 6);
112 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
113 unsigned &CurByte, raw_ostream &OS) const {
114 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
117 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
118 unsigned &CurByte, raw_ostream &OS) const {
119 // SIB byte is in the same format as the ModRMByte.
120 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
124 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
125 unsigned RegOpcodeField,
126 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
127 SmallVectorImpl<MCFixup> &Fixups) const;
129 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
130 SmallVectorImpl<MCFixup> &Fixups) const;
132 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
133 const MCInst &MI, const TargetInstrDesc &Desc,
134 raw_ostream &OS) const;
136 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
137 const MCInst &MI, const TargetInstrDesc &Desc,
138 raw_ostream &OS) const;
141 } // end anonymous namespace
144 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
147 return new X86MCCodeEmitter(TM, Ctx, false);
150 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
153 return new X86MCCodeEmitter(TM, Ctx, true);
156 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
157 /// sign-extended field.
158 static bool isDisp8(int Value) {
159 return Value == (signed char)Value;
162 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
163 /// in an instruction with the specified TSFlags.
164 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
165 unsigned Size = X86II::getSizeOfImm(TSFlags);
166 bool isPCRel = X86II::isImmPCRel(TSFlags);
169 default: assert(0 && "Unknown immediate size");
170 case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
171 case 2: return isPCRel ? MCFixupKind(X86::reloc_pcrel_2byte) : FK_Data_2;
172 case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
173 case 8: assert(!isPCRel); return FK_Data_8;
178 void X86MCCodeEmitter::
179 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
180 unsigned &CurByte, raw_ostream &OS,
181 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
182 // If this is a simple integer displacement that doesn't require a relocation,
184 if (DispOp.isImm()) {
185 // FIXME: is this right for pc-rel encoding?? Probably need to emit this as
187 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
191 // If we have an immoffset, add it to the expression.
192 const MCExpr *Expr = DispOp.getExpr();
194 // If the fixup is pc-relative, we need to bias the value to be relative to
195 // the start of the field, not the end of the field.
196 if (FixupKind == MCFixupKind(X86::reloc_pcrel_4byte) ||
197 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
198 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
200 if (FixupKind == MCFixupKind(X86::reloc_pcrel_2byte))
202 if (FixupKind == MCFixupKind(X86::reloc_pcrel_1byte))
206 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
209 // Emit a symbolic constant as a fixup and 4 zeros.
210 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
211 EmitConstant(0, Size, CurByte, OS);
214 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
215 unsigned RegOpcodeField,
216 uint64_t TSFlags, unsigned &CurByte,
218 SmallVectorImpl<MCFixup> &Fixups) const{
219 const MCOperand &Disp = MI.getOperand(Op+3);
220 const MCOperand &Base = MI.getOperand(Op);
221 const MCOperand &Scale = MI.getOperand(Op+1);
222 const MCOperand &IndexReg = MI.getOperand(Op+2);
223 unsigned BaseReg = Base.getReg();
225 // Handle %rip relative addressing.
226 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
227 assert(Is64BitMode && "Rip-relative addressing requires 64-bit mode");
228 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
229 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
231 unsigned FixupKind = X86::reloc_riprel_4byte;
233 // movq loads are handled with a special relocation form which allows the
234 // linker to eliminate some loads for GOT references which end up in the
235 // same linkage unit.
236 if (MI.getOpcode() == X86::MOV64rm ||
237 MI.getOpcode() == X86::MOV64rm_TC)
238 FixupKind = X86::reloc_riprel_4byte_movq_load;
240 // rip-relative addressing is actually relative to the *next* instruction.
241 // Since an immediate can follow the mod/rm byte for an instruction, this
242 // means that we need to bias the immediate field of the instruction with
243 // the size of the immediate field. If we have this case, add it into the
244 // expression to emit.
245 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
247 EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
248 CurByte, OS, Fixups, -ImmSize);
252 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
254 // Determine whether a SIB byte is needed.
255 // If no BaseReg, issue a RIP relative instruction only if the MCE can
256 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
257 // 2-7) and absolute references.
259 if (// The SIB byte must be used if there is an index register.
260 IndexReg.getReg() == 0 &&
261 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
262 // encode to an R/M value of 4, which indicates that a SIB byte is
264 BaseRegNo != N86::ESP &&
265 // If there is no base register and we're in 64-bit mode, we need a SIB
266 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
267 (!Is64BitMode || BaseReg != 0)) {
269 if (BaseReg == 0) { // [disp32] in X86-32 mode
270 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
271 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
275 // If the base is not EBP/ESP and there is no displacement, use simple
276 // indirect register encoding, this handles addresses like [EAX]. The
277 // encoding for [EBP] with no displacement means [disp32] so we handle it
278 // by emitting a displacement of 0 below.
279 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
280 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
284 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
285 if (Disp.isImm() && isDisp8(Disp.getImm())) {
286 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
287 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
291 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
292 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
293 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
297 // We need a SIB byte, so start by outputting the ModR/M byte first
298 assert(IndexReg.getReg() != X86::ESP &&
299 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
301 bool ForceDisp32 = false;
302 bool ForceDisp8 = false;
304 // If there is no base register, we emit the special case SIB byte with
305 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
306 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
308 } else if (!Disp.isImm()) {
309 // Emit the normal disp32 encoding.
310 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
312 } else if (Disp.getImm() == 0 &&
313 // Base reg can't be anything that ends up with '5' as the base
314 // reg, it is the magic [*] nomenclature that indicates no base.
315 BaseRegNo != N86::EBP) {
316 // Emit no displacement ModR/M byte
317 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
318 } else if (isDisp8(Disp.getImm())) {
319 // Emit the disp8 encoding.
320 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
321 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
323 // Emit the normal disp32 encoding.
324 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
327 // Calculate what the SS field value should be...
328 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
329 unsigned SS = SSTable[Scale.getImm()];
332 // Handle the SIB byte for the case where there is no base, see Intel
333 // Manual 2A, table 2-7. The displacement has already been output.
335 if (IndexReg.getReg())
336 IndexRegNo = GetX86RegNum(IndexReg);
337 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
339 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
342 if (IndexReg.getReg())
343 IndexRegNo = GetX86RegNum(IndexReg);
345 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
346 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
349 // Do we need to output a displacement?
351 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
352 else if (ForceDisp32 || Disp.getImm() != 0)
353 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
356 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
358 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
359 const MCInst &MI, const TargetInstrDesc &Desc,
360 raw_ostream &OS) const {
362 // Pseudo instructions never have a VEX prefix.
363 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
366 bool HasVEX_4V = false;
367 if ((TSFlags >> 32) & X86II::VEX_4V)
370 // VEX_R: opcode externsion equivalent to REX.R in
371 // 1's complement (inverted) form
373 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
374 // 0: Same as REX_R=1 (64 bit mode only)
376 unsigned char VEX_R = 0x1;
378 // VEX_X: equivalent to REX.X, only used when a
379 // register is used for index in SIB Byte.
381 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
382 // 0: Same as REX.X=1 (64-bit mode only)
383 unsigned char VEX_X = 0x1;
387 // 1: Same as REX_B=0 (ignored in 32-bit mode)
388 // 0: Same as REX_B=1 (64 bit mode only)
390 unsigned char VEX_B = 0x1;
392 // VEX_W: opcode specific (use like REX.W, or used for
393 // opcode extension, or ignored, depending on the opcode byte)
394 unsigned char VEX_W = 0;
396 // VEX_5M (VEX m-mmmmm field):
398 // 0b00000: Reserved for future use
399 // 0b00001: implied 0F leading opcode
400 // 0b00010: implied 0F 38 leading opcode bytes
401 // 0b00011: implied 0F 3A leading opcode bytes
402 // 0b00100-0b11111: Reserved for future use
404 unsigned char VEX_5M = 0x1;
406 // VEX_4V (VEX vvvv field): a register specifier
407 // (in 1's complement form) or 1111 if unused.
408 unsigned char VEX_4V = 0xf;
410 // VEX_L (Vector Length):
412 // 0: scalar or 128-bit vector
415 unsigned char VEX_L = 0;
417 // VEX_PP: opcode extension providing equivalent
418 // functionality of a SIMD prefix
425 unsigned char VEX_PP = 0;
427 // Encode the operand size opcode prefix as needed.
428 if (TSFlags & X86II::OpSize)
431 if ((TSFlags >> 32) & X86II::VEX_W)
434 switch (TSFlags & X86II::Op0Mask) {
435 default: assert(0 && "Invalid prefix!");
436 case X86II::T8: // 0F 38
439 case X86II::TA: // 0F 3A
442 case X86II::TF: // F2 0F 38
446 case X86II::XS: // F3 0F
449 case X86II::XD: // F2 0F
452 case X86II::TB: // Bypass: Not used by VEX
457 unsigned NumOps = MI.getNumOperands();
460 switch (TSFlags & X86II::FormMask) {
461 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
462 case X86II::MRM0m: case X86II::MRM1m:
463 case X86II::MRM2m: case X86II::MRM3m:
464 case X86II::MRM4m: case X86II::MRM5m:
465 case X86II::MRM6m: case X86II::MRM7m:
466 case X86II::MRMDestMem:
467 NumOps = CurOp = X86::AddrNumOperands;
468 case X86II::MRMSrcMem:
469 case X86II::MRMSrcReg:
470 if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
471 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
474 // CurOp and NumOps are equal when VEX_R represents a register used
475 // to index a memory destination (which is the last operand)
476 CurOp = (CurOp == NumOps) ? 0 : CurOp+1;
479 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
483 // If the last register should be encoded in the immediate field
484 // do not use any bit from VEX prefix to this register, ignore it
485 if ((TSFlags >> 32) & X86II::VEX_I8IMM)
488 for (; CurOp != NumOps; ++CurOp) {
489 const MCOperand &MO = MI.getOperand(CurOp);
490 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
492 if (!VEX_B && MO.isReg() &&
493 ((TSFlags & X86II::FormMask) == X86II::MRMSrcMem) &&
494 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
498 default: // MRMDestReg, MRM0r-MRM7r
499 if (MI.getOperand(CurOp).isReg() &&
500 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
504 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
507 for (; CurOp != NumOps; ++CurOp) {
508 const MCOperand &MO = MI.getOperand(CurOp);
509 if (MO.isReg() && !HasVEX_4V &&
510 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
514 assert(0 && "Not implemented!");
517 // VEX opcode prefix can have 2 or 3 bytes
520 // +-----+ +--------------+ +-------------------+
521 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
522 // +-----+ +--------------+ +-------------------+
524 // +-----+ +-------------------+
525 // | C5h | | R | vvvv | L | pp |
526 // +-----+ +-------------------+
528 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
530 if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix
531 EmitByte(0xC5, CurByte, OS);
532 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
537 EmitByte(0xC4, CurByte, OS);
538 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
539 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
542 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
543 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
544 /// size, and 3) use of X86-64 extended registers.
545 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
546 const TargetInstrDesc &Desc) {
547 // Pseudo instructions never have a rex byte.
548 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
552 if (TSFlags & X86II::REX_W)
553 REX |= 1 << 3; // set REX.W
555 if (MI.getNumOperands() == 0) return REX;
557 unsigned NumOps = MI.getNumOperands();
558 // FIXME: MCInst should explicitize the two-addrness.
559 bool isTwoAddr = NumOps > 1 &&
560 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
562 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
563 unsigned i = isTwoAddr ? 1 : 0;
564 for (; i != NumOps; ++i) {
565 const MCOperand &MO = MI.getOperand(i);
566 if (!MO.isReg()) continue;
567 unsigned Reg = MO.getReg();
568 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
569 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
570 // that returns non-zero.
571 REX |= 0x40; // REX fixed encoding prefix
575 switch (TSFlags & X86II::FormMask) {
576 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
577 case X86II::MRMSrcReg:
578 if (MI.getOperand(0).isReg() &&
579 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
580 REX |= 1 << 2; // set REX.R
581 i = isTwoAddr ? 2 : 1;
582 for (; i != NumOps; ++i) {
583 const MCOperand &MO = MI.getOperand(i);
584 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
585 REX |= 1 << 0; // set REX.B
588 case X86II::MRMSrcMem: {
589 if (MI.getOperand(0).isReg() &&
590 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
591 REX |= 1 << 2; // set REX.R
593 i = isTwoAddr ? 2 : 1;
594 for (; i != NumOps; ++i) {
595 const MCOperand &MO = MI.getOperand(i);
597 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
598 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
604 case X86II::MRM0m: case X86II::MRM1m:
605 case X86II::MRM2m: case X86II::MRM3m:
606 case X86II::MRM4m: case X86II::MRM5m:
607 case X86II::MRM6m: case X86II::MRM7m:
608 case X86II::MRMDestMem: {
609 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
610 i = isTwoAddr ? 1 : 0;
611 if (NumOps > e && MI.getOperand(e).isReg() &&
612 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
613 REX |= 1 << 2; // set REX.R
615 for (; i != e; ++i) {
616 const MCOperand &MO = MI.getOperand(i);
618 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
619 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
626 if (MI.getOperand(0).isReg() &&
627 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
628 REX |= 1 << 0; // set REX.B
629 i = isTwoAddr ? 2 : 1;
630 for (unsigned e = NumOps; i != e; ++i) {
631 const MCOperand &MO = MI.getOperand(i);
632 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
633 REX |= 1 << 2; // set REX.R
640 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
642 /// MemOperand is the operand # of the start of a memory operand if present. If
643 /// Not present, it is -1.
644 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
645 int MemOperand, const MCInst &MI,
646 const TargetInstrDesc &Desc,
647 raw_ostream &OS) const {
649 // Emit the lock opcode prefix as needed.
650 if (TSFlags & X86II::LOCK)
651 EmitByte(0xF0, CurByte, OS);
653 // Emit segment override opcode prefix as needed.
654 switch (TSFlags & X86II::SegOvrMask) {
655 default: assert(0 && "Invalid segment!");
657 // No segment override, check for explicit one on memory operand.
658 if (MemOperand != -1) { // If the instruction has a memory operand.
659 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
660 default: assert(0 && "Unknown segment register!");
662 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
663 case X86::SS: EmitByte(0x36, CurByte, OS); break;
664 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
665 case X86::ES: EmitByte(0x26, CurByte, OS); break;
666 case X86::FS: EmitByte(0x64, CurByte, OS); break;
667 case X86::GS: EmitByte(0x65, CurByte, OS); break;
672 EmitByte(0x64, CurByte, OS);
675 EmitByte(0x65, CurByte, OS);
679 // Emit the repeat opcode prefix as needed.
680 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
681 EmitByte(0xF3, CurByte, OS);
683 // Emit the operand size opcode prefix as needed.
684 if (TSFlags & X86II::OpSize)
685 EmitByte(0x66, CurByte, OS);
687 // Emit the address size opcode prefix as needed.
688 if (TSFlags & X86II::AdSize)
689 EmitByte(0x67, CurByte, OS);
691 bool Need0FPrefix = false;
692 switch (TSFlags & X86II::Op0Mask) {
693 default: assert(0 && "Invalid prefix!");
694 case 0: break; // No prefix!
695 case X86II::REP: break; // already handled.
696 case X86II::TB: // Two-byte opcode prefix
697 case X86II::T8: // 0F 38
698 case X86II::TA: // 0F 3A
701 case X86II::TF: // F2 0F 38
702 EmitByte(0xF2, CurByte, OS);
705 case X86II::XS: // F3 0F
706 EmitByte(0xF3, CurByte, OS);
709 case X86II::XD: // F2 0F
710 EmitByte(0xF2, CurByte, OS);
713 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
714 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
715 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
716 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
717 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
718 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
719 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
720 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
723 // Handle REX prefix.
724 // FIXME: Can this come before F2 etc to simplify emission?
726 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
727 EmitByte(0x40 | REX, CurByte, OS);
730 // 0x0F escape code must be emitted just before the opcode.
732 EmitByte(0x0F, CurByte, OS);
734 // FIXME: Pull this up into previous switch if REX can be moved earlier.
735 switch (TSFlags & X86II::Op0Mask) {
736 case X86II::TF: // F2 0F 38
737 case X86II::T8: // 0F 38
738 EmitByte(0x38, CurByte, OS);
740 case X86II::TA: // 0F 3A
741 EmitByte(0x3A, CurByte, OS);
746 void X86MCCodeEmitter::
747 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
748 SmallVectorImpl<MCFixup> &Fixups) const {
749 unsigned Opcode = MI.getOpcode();
750 const TargetInstrDesc &Desc = TII.get(Opcode);
751 uint64_t TSFlags = Desc.TSFlags;
754 // If this is a two-address instruction, skip one of the register operands.
755 // FIXME: This should be handled during MCInst lowering.
756 unsigned NumOps = Desc.getNumOperands();
758 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
760 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
761 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
764 // Keep track of the current byte being emitted.
765 unsigned CurByte = 0;
767 // Is this instruction encoded using the AVX VEX prefix?
768 bool HasVEXPrefix = false;
770 // It uses the VEX.VVVV field?
771 bool HasVEX_4V = false;
773 if ((TSFlags >> 32) & X86II::VEX)
775 if ((TSFlags >> 32) & X86II::VEX_4V)
778 // Determine where the memory operand starts, if present.
779 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
780 if (MemoryOperand != -1) MemoryOperand += CurOp;
783 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
785 // FIXME: Segment overrides??
786 EmitVEXOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
788 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
789 unsigned SrcRegNum = 0;
790 switch (TSFlags & X86II::FormMask) {
791 case X86II::MRMInitReg:
792 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
793 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
794 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
795 case X86II::Pseudo: return; // Pseudo instructions encode to nothing.
797 EmitByte(BaseOpcode, CurByte, OS);
800 case X86II::AddRegFrm:
801 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
804 case X86II::MRMDestReg:
805 EmitByte(BaseOpcode, CurByte, OS);
806 EmitRegModRMByte(MI.getOperand(CurOp),
807 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
811 case X86II::MRMDestMem:
812 EmitByte(BaseOpcode, CurByte, OS);
813 EmitMemModRMByte(MI, CurOp,
814 GetX86RegNum(MI.getOperand(CurOp + X86::AddrNumOperands)),
815 TSFlags, CurByte, OS, Fixups);
816 CurOp += X86::AddrNumOperands + 1;
819 case X86II::MRMSrcReg:
820 EmitByte(BaseOpcode, CurByte, OS);
821 SrcRegNum = CurOp + 1;
823 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
826 EmitRegModRMByte(MI.getOperand(SrcRegNum),
827 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
828 CurOp = SrcRegNum + 1;
831 case X86II::MRMSrcMem: {
832 int AddrOperands = X86::AddrNumOperands;
833 unsigned FirstMemOp = CurOp+1;
836 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
839 EmitByte(BaseOpcode, CurByte, OS);
841 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
842 TSFlags, CurByte, OS, Fixups);
843 CurOp += AddrOperands + 1;
847 case X86II::MRM0r: case X86II::MRM1r:
848 case X86II::MRM2r: case X86II::MRM3r:
849 case X86II::MRM4r: case X86II::MRM5r:
850 case X86II::MRM6r: case X86II::MRM7r:
851 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
853 EmitByte(BaseOpcode, CurByte, OS);
854 EmitRegModRMByte(MI.getOperand(CurOp++),
855 (TSFlags & X86II::FormMask)-X86II::MRM0r,
858 case X86II::MRM0m: case X86II::MRM1m:
859 case X86II::MRM2m: case X86II::MRM3m:
860 case X86II::MRM4m: case X86II::MRM5m:
861 case X86II::MRM6m: case X86II::MRM7m:
862 EmitByte(BaseOpcode, CurByte, OS);
863 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
864 TSFlags, CurByte, OS, Fixups);
865 CurOp += X86::AddrNumOperands;
868 EmitByte(BaseOpcode, CurByte, OS);
869 EmitByte(0xC1, CurByte, OS);
872 EmitByte(BaseOpcode, CurByte, OS);
873 EmitByte(0xC2, CurByte, OS);
876 EmitByte(BaseOpcode, CurByte, OS);
877 EmitByte(0xC3, CurByte, OS);
880 EmitByte(BaseOpcode, CurByte, OS);
881 EmitByte(0xC4, CurByte, OS);
884 EmitByte(BaseOpcode, CurByte, OS);
885 EmitByte(0xC8, CurByte, OS);
888 EmitByte(BaseOpcode, CurByte, OS);
889 EmitByte(0xC9, CurByte, OS);
892 EmitByte(BaseOpcode, CurByte, OS);
893 EmitByte(0xE8, CurByte, OS);
896 EmitByte(BaseOpcode, CurByte, OS);
897 EmitByte(0xF0, CurByte, OS);
900 EmitByte(BaseOpcode, CurByte, OS);
901 EmitByte(0xF8, CurByte, OS);
904 EmitByte(BaseOpcode, CurByte, OS);
905 EmitByte(0xF9, CurByte, OS);
909 // If there is a remaining operand, it must be a trailing immediate. Emit it
910 // according to the right size for the instruction.
911 if (CurOp != NumOps) {
912 // The last source register of a 4 operand instruction in AVX is encoded
913 // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
914 if ((TSFlags >> 32) & X86II::VEX_I8IMM) {
915 const MCOperand &MO = MI.getOperand(CurOp++);
917 X86InstrInfo::isX86_64ExtendedReg(MO.getReg());
918 unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
919 RegNum |= GetX86RegNum(MO) << 4;
920 EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS,
923 EmitImmediate(MI.getOperand(CurOp++),
924 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
925 CurByte, OS, Fixups);
931 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
932 errs() << "Cannot encode all operands of: ";