1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/Support/raw_ostream.h"
25 class X86MCCodeEmitter : public MCCodeEmitter {
26 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
27 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
28 const TargetMachine &TM;
29 const TargetInstrInfo &TII;
33 X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit)
34 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
35 Is64BitMode = is64Bit;
38 ~X86MCCodeEmitter() {}
40 unsigned getNumFixupKinds() const {
44 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
45 const static MCFixupKindInfo Infos[] = {
46 { "reloc_pcrel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
47 { "reloc_pcrel_1byte", 0, 1 * 8, MCFixupKindInfo::FKF_IsPCRel },
48 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
49 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel }
52 if (Kind < FirstTargetFixupKind)
53 return MCCodeEmitter::getFixupKindInfo(Kind);
55 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
57 return Infos[Kind - FirstTargetFixupKind];
60 static unsigned GetX86RegNum(const MCOperand &MO) {
61 return X86RegisterInfo::getX86RegNum(MO.getReg());
64 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
69 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
70 raw_ostream &OS) const {
71 // Output the constant in little endian byte order.
72 for (unsigned i = 0; i != Size; ++i) {
73 EmitByte(Val & 255, CurByte, OS);
78 void EmitImmediate(const MCOperand &Disp,
79 unsigned ImmSize, MCFixupKind FixupKind,
80 unsigned &CurByte, raw_ostream &OS,
81 SmallVectorImpl<MCFixup> &Fixups,
82 int ImmOffset = 0) const;
84 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
86 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
87 return RM | (RegOpcode << 3) | (Mod << 6);
90 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
91 unsigned &CurByte, raw_ostream &OS) const {
92 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
95 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
96 unsigned &CurByte, raw_ostream &OS) const {
97 // SIB byte is in the same format as the ModRMByte.
98 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
102 void EmitSegmentOverridePrefix(const MCOperand &Op, unsigned TSFlags,
103 unsigned &CurByte, raw_ostream &OS) const;
105 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
106 unsigned RegOpcodeField,
107 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
108 SmallVectorImpl<MCFixup> &Fixups) const;
110 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
111 SmallVectorImpl<MCFixup> &Fixups) const;
113 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
114 const MCInst &MI, const TargetInstrDesc &Desc,
115 raw_ostream &OS) const;
117 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
118 const MCInst &MI, const TargetInstrDesc &Desc,
119 raw_ostream &OS) const;
122 } // end anonymous namespace
125 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
128 return new X86MCCodeEmitter(TM, Ctx, false);
131 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
134 return new X86MCCodeEmitter(TM, Ctx, true);
138 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
139 /// sign-extended field.
140 static bool isDisp8(int Value) {
141 return Value == (signed char)Value;
144 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
145 /// in an instruction with the specified TSFlags.
146 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
147 unsigned Size = X86II::getSizeOfImm(TSFlags);
148 bool isPCRel = X86II::isImmPCRel(TSFlags);
151 default: assert(0 && "Unknown immediate size");
152 case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
153 case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
154 case 2: assert(!isPCRel); return FK_Data_2;
155 case 8: assert(!isPCRel); return FK_Data_8;
160 void X86MCCodeEmitter::
161 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
162 unsigned &CurByte, raw_ostream &OS,
163 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
164 // If this is a simple integer displacement that doesn't require a relocation,
166 if (DispOp.isImm()) {
167 // FIXME: is this right for pc-rel encoding?? Probably need to emit this as
169 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
173 // If we have an immoffset, add it to the expression.
174 const MCExpr *Expr = DispOp.getExpr();
176 // If the fixup is pc-relative, we need to bias the value to be relative to
177 // the start of the field, not the end of the field.
178 if (FixupKind == MCFixupKind(X86::reloc_pcrel_4byte) ||
179 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
180 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
182 if (FixupKind == MCFixupKind(X86::reloc_pcrel_1byte))
186 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
189 // Emit a symbolic constant as a fixup and 4 zeros.
190 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
191 EmitConstant(0, Size, CurByte, OS);
194 void X86MCCodeEmitter::EmitSegmentOverridePrefix(const MCOperand &Op,
197 raw_ostream &OS) const {
198 // If no segment register is present, we don't need anything.
199 if (Op.getReg() == 0)
202 // Check if we need an override.
203 switch (Op.getReg()) {
204 case X86::CS: EmitByte(0x2E, CurByte, OS); return;
205 case X86::SS: EmitByte(0x36, CurByte, OS); return;
206 case X86::DS: EmitByte(0x3E, CurByte, OS); return;
207 case X86::ES: EmitByte(0x26, CurByte, OS); return;
208 case X86::FS: EmitByte(0x64, CurByte, OS); return;
209 case X86::GS: EmitByte(0x65, CurByte, OS); return;
212 assert(0 && "Invalid segment register!");
215 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
216 unsigned RegOpcodeField,
217 uint64_t TSFlags, unsigned &CurByte,
219 SmallVectorImpl<MCFixup> &Fixups) const{
220 const MCOperand &Disp = MI.getOperand(Op+3);
221 const MCOperand &Base = MI.getOperand(Op);
222 const MCOperand &Scale = MI.getOperand(Op+1);
223 const MCOperand &IndexReg = MI.getOperand(Op+2);
224 unsigned BaseReg = Base.getReg();
226 // Handle %rip relative addressing.
227 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
228 assert(Is64BitMode && "Rip-relative addressing requires 64-bit mode");
229 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
230 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
232 unsigned FixupKind = X86::reloc_riprel_4byte;
234 // movq loads are handled with a special relocation form which allows the
235 // linker to eliminate some loads for GOT references which end up in the
236 // same linkage unit.
237 if (MI.getOpcode() == X86::MOV64rm ||
238 MI.getOpcode() == X86::MOV64rm_TC)
239 FixupKind = X86::reloc_riprel_4byte_movq_load;
241 // rip-relative addressing is actually relative to the *next* instruction.
242 // Since an immediate can follow the mod/rm byte for an instruction, this
243 // means that we need to bias the immediate field of the instruction with
244 // the size of the immediate field. If we have this case, add it into the
245 // expression to emit.
246 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
248 EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
249 CurByte, OS, Fixups, -ImmSize);
253 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
255 // Determine whether a SIB byte is needed.
256 // If no BaseReg, issue a RIP relative instruction only if the MCE can
257 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
258 // 2-7) and absolute references.
260 if (// The SIB byte must be used if there is an index register.
261 IndexReg.getReg() == 0 &&
262 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
263 // encode to an R/M value of 4, which indicates that a SIB byte is
265 BaseRegNo != N86::ESP &&
266 // If there is no base register and we're in 64-bit mode, we need a SIB
267 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
268 (!Is64BitMode || BaseReg != 0)) {
270 if (BaseReg == 0) { // [disp32] in X86-32 mode
271 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
272 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
276 // If the base is not EBP/ESP and there is no displacement, use simple
277 // indirect register encoding, this handles addresses like [EAX]. The
278 // encoding for [EBP] with no displacement means [disp32] so we handle it
279 // by emitting a displacement of 0 below.
280 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
281 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
285 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
286 if (Disp.isImm() && isDisp8(Disp.getImm())) {
287 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
288 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
292 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
293 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
294 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
298 // We need a SIB byte, so start by outputting the ModR/M byte first
299 assert(IndexReg.getReg() != X86::ESP &&
300 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
302 bool ForceDisp32 = false;
303 bool ForceDisp8 = false;
305 // If there is no base register, we emit the special case SIB byte with
306 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
307 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
309 } else if (!Disp.isImm()) {
310 // Emit the normal disp32 encoding.
311 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
313 } else if (Disp.getImm() == 0 &&
314 // Base reg can't be anything that ends up with '5' as the base
315 // reg, it is the magic [*] nomenclature that indicates no base.
316 BaseRegNo != N86::EBP) {
317 // Emit no displacement ModR/M byte
318 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
319 } else if (isDisp8(Disp.getImm())) {
320 // Emit the disp8 encoding.
321 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
322 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
324 // Emit the normal disp32 encoding.
325 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
328 // Calculate what the SS field value should be...
329 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
330 unsigned SS = SSTable[Scale.getImm()];
333 // Handle the SIB byte for the case where there is no base, see Intel
334 // Manual 2A, table 2-7. The displacement has already been output.
336 if (IndexReg.getReg())
337 IndexRegNo = GetX86RegNum(IndexReg);
338 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
340 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
343 if (IndexReg.getReg())
344 IndexRegNo = GetX86RegNum(IndexReg);
346 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
347 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
350 // Do we need to output a displacement?
352 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
353 else if (ForceDisp32 || Disp.getImm() != 0)
354 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
357 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
359 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
360 const MCInst &MI, const TargetInstrDesc &Desc,
361 raw_ostream &OS) const {
363 // Pseudo instructions never have a VEX prefix.
364 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
367 // VEX_R: opcode externsion equivalent to REX.R in
368 // 1's complement (inverted) form
370 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
371 // 0: Same as REX_R=1 (64 bit mode only)
373 unsigned char VEX_R = 0x1;
375 // VEX_X: equivalent to REX.X, only used when a
376 // register is used for index in SIB Byte.
378 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
379 // 0: Same as REX.X=1 (64-bit mode only)
380 unsigned char VEX_X = 0x1;
384 // 1: Same as REX_B=0 (ignored in 32-bit mode)
385 // 0: Same as REX_B=1 (64 bit mode only)
387 unsigned char VEX_B = 0x1;
389 // VEX_W: opcode specific (use like REX.W, or used for
390 // opcode extension, or ignored, depending on the opcode byte)
391 unsigned char VEX_W = 0;
393 // VEX_5M (VEX m-mmmmm field):
395 // 0b00000: Reserved for future use
396 // 0b00001: implied 0F leading opcode
397 // 0b00010: implied 0F 38 leading opcode bytes
398 // 0b00011: implied 0F 3A leading opcode bytes
399 // 0b00100-0b11111: Reserved for future use
401 unsigned char VEX_5M = 0x1;
403 // VEX_4V (VEX vvvv field): a register specifier
404 // (in 1's complement form) or 1111 if unused.
405 unsigned char VEX_4V = 0xf;
407 // VEX_L (Vector Length):
409 // 0: scalar or 128-bit vector
412 unsigned char VEX_L = 0;
414 // VEX_PP: opcode extension providing equivalent
415 // functionality of a SIMD prefix
422 unsigned char VEX_PP = 0;
424 // Encode the operand size opcode prefix as needed.
425 if (TSFlags & X86II::OpSize)
428 switch (TSFlags & X86II::Op0Mask) {
429 default: assert(0 && "Invalid prefix!");
430 case 0: break; // No prefix!
431 case X86II::T8: // 0F 38
434 case X86II::TA: // 0F 3A
437 case X86II::TF: // F2 0F 38
441 case X86II::XS: // F3 0F
444 case X86II::XD: // F2 0F
449 unsigned NumOps = MI.getNumOperands();
451 unsigned SrcReg = 0, SrcRegNum = 0;
452 bool IsSrcMem = false;
454 switch (TSFlags & X86II::FormMask) {
455 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
456 case X86II::MRMSrcMem:
458 case X86II::MRMSrcReg:
459 if (MI.getOperand(0).isReg() &&
460 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
463 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the
464 // range 0-7 and the difference between the 2 groups is given by the
465 // REX prefix. In the VEX prefix, registers are seen sequencially
466 // from 0-15 and encoded in 1's complement form, example:
468 // ModRM field => XMM9 => 1
469 // VEX.VVVV => XMM9 => ~9
471 // See table 4-35 of Intel AVX Programming Reference for details.
472 SrcReg = MI.getOperand(1).getReg();
473 SrcRegNum = GetX86RegNum(MI.getOperand(1));
474 if (SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15)
477 // The registers represented through VEX_VVVV should
478 // be encoded in 1's complement form.
479 if ((TSFlags >> 32) & X86II::VEX_4V)
480 VEX_4V = (~SrcRegNum) & 0xf;
482 i = 2; // Skip the VEX.VVVV operand.
483 for (; i != NumOps; ++i) {
484 const MCOperand &MO = MI.getOperand(i);
485 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
487 if (!VEX_B && MO.isReg() && IsSrcMem &&
488 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
493 assert(0 && "Not implemented!");
496 // VEX opcode prefix can have 2 or 3 bytes
499 // +-----+ +--------------+ +-------------------+
500 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
501 // +-----+ +--------------+ +-------------------+
503 // +-----+ +-------------------+
504 // | C5h | | R | vvvv | L | pp |
505 // +-----+ +-------------------+
507 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
509 if (VEX_B && VEX_X) { // 2 byte VEX prefix
510 EmitByte(0xC5, CurByte, OS);
511 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
516 EmitByte(0xC4, CurByte, OS);
517 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_5M, CurByte, OS);
518 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
521 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
522 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
523 /// size, and 3) use of X86-64 extended registers.
524 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
525 const TargetInstrDesc &Desc) {
526 // Pseudo instructions never have a rex byte.
527 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
531 if (TSFlags & X86II::REX_W)
532 REX |= 1 << 3; // set REX.W
534 if (MI.getNumOperands() == 0) return REX;
536 unsigned NumOps = MI.getNumOperands();
537 // FIXME: MCInst should explicitize the two-addrness.
538 bool isTwoAddr = NumOps > 1 &&
539 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
541 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
542 unsigned i = isTwoAddr ? 1 : 0;
543 for (; i != NumOps; ++i) {
544 const MCOperand &MO = MI.getOperand(i);
545 if (!MO.isReg()) continue;
546 unsigned Reg = MO.getReg();
547 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
548 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
549 // that returns non-zero.
550 REX |= 0x40; // REX fixed encoding prefix
554 switch (TSFlags & X86II::FormMask) {
555 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
556 case X86II::MRMSrcReg:
557 if (MI.getOperand(0).isReg() &&
558 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
559 REX |= 1 << 2; // set REX.R
560 i = isTwoAddr ? 2 : 1;
561 for (; i != NumOps; ++i) {
562 const MCOperand &MO = MI.getOperand(i);
563 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
564 REX |= 1 << 0; // set REX.B
567 case X86II::MRMSrcMem: {
568 if (MI.getOperand(0).isReg() &&
569 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
570 REX |= 1 << 2; // set REX.R
572 i = isTwoAddr ? 2 : 1;
573 for (; i != NumOps; ++i) {
574 const MCOperand &MO = MI.getOperand(i);
576 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
577 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
583 case X86II::MRM0m: case X86II::MRM1m:
584 case X86II::MRM2m: case X86II::MRM3m:
585 case X86II::MRM4m: case X86II::MRM5m:
586 case X86II::MRM6m: case X86II::MRM7m:
587 case X86II::MRMDestMem: {
588 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
589 i = isTwoAddr ? 1 : 0;
590 if (NumOps > e && MI.getOperand(e).isReg() &&
591 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
592 REX |= 1 << 2; // set REX.R
594 for (; i != e; ++i) {
595 const MCOperand &MO = MI.getOperand(i);
597 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
598 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
605 if (MI.getOperand(0).isReg() &&
606 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
607 REX |= 1 << 0; // set REX.B
608 i = isTwoAddr ? 2 : 1;
609 for (unsigned e = NumOps; i != e; ++i) {
610 const MCOperand &MO = MI.getOperand(i);
611 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
612 REX |= 1 << 2; // set REX.R
619 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
620 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
621 const MCInst &MI, const TargetInstrDesc &Desc,
622 raw_ostream &OS) const {
624 // Emit the lock opcode prefix as needed.
625 if (TSFlags & X86II::LOCK)
626 EmitByte(0xF0, CurByte, OS);
628 // Emit segment override opcode prefix as needed.
629 switch (TSFlags & X86II::SegOvrMask) {
630 default: assert(0 && "Invalid segment!");
631 case 0: break; // No segment override!
633 EmitByte(0x64, CurByte, OS);
636 EmitByte(0x65, CurByte, OS);
640 // Emit the repeat opcode prefix as needed.
641 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
642 EmitByte(0xF3, CurByte, OS);
644 // Emit the operand size opcode prefix as needed.
645 if (TSFlags & X86II::OpSize)
646 EmitByte(0x66, CurByte, OS);
648 // Emit the address size opcode prefix as needed.
649 if (TSFlags & X86II::AdSize)
650 EmitByte(0x67, CurByte, OS);
652 bool Need0FPrefix = false;
653 switch (TSFlags & X86II::Op0Mask) {
654 default: assert(0 && "Invalid prefix!");
655 case 0: break; // No prefix!
656 case X86II::REP: break; // already handled.
657 case X86II::TB: // Two-byte opcode prefix
658 case X86II::T8: // 0F 38
659 case X86II::TA: // 0F 3A
662 case X86II::TF: // F2 0F 38
663 EmitByte(0xF2, CurByte, OS);
666 case X86II::XS: // F3 0F
667 EmitByte(0xF3, CurByte, OS);
670 case X86II::XD: // F2 0F
671 EmitByte(0xF2, CurByte, OS);
674 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
675 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
676 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
677 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
678 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
679 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
680 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
681 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
684 // Handle REX prefix.
685 // FIXME: Can this come before F2 etc to simplify emission?
687 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
688 EmitByte(0x40 | REX, CurByte, OS);
691 // 0x0F escape code must be emitted just before the opcode.
693 EmitByte(0x0F, CurByte, OS);
695 // FIXME: Pull this up into previous switch if REX can be moved earlier.
696 switch (TSFlags & X86II::Op0Mask) {
697 case X86II::TF: // F2 0F 38
698 case X86II::T8: // 0F 38
699 EmitByte(0x38, CurByte, OS);
701 case X86II::TA: // 0F 3A
702 EmitByte(0x3A, CurByte, OS);
707 void X86MCCodeEmitter::
708 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
709 SmallVectorImpl<MCFixup> &Fixups) const {
710 unsigned Opcode = MI.getOpcode();
711 const TargetInstrDesc &Desc = TII.get(Opcode);
712 uint64_t TSFlags = Desc.TSFlags;
714 // Keep track of the current byte being emitted.
715 unsigned CurByte = 0;
717 // Is this instruction encoded in AVX form?
718 bool IsAVXForm = false;
719 if ((TSFlags >> 32) & X86II::VEX_4V)
722 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
723 // in order to provide diffability.
726 EmitOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
728 EmitVEXOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
730 // If this is a two-address instruction, skip one of the register operands.
731 unsigned NumOps = Desc.getNumOperands();
733 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
735 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
736 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
739 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
740 unsigned SrcRegNum = 0;
741 switch (TSFlags & X86II::FormMask) {
742 case X86II::MRMInitReg:
743 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
744 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
745 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
746 case X86II::Pseudo: return; // Pseudo instructions encode to nothing.
748 EmitByte(BaseOpcode, CurByte, OS);
751 case X86II::AddRegFrm:
752 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
755 case X86II::MRMDestReg:
756 EmitByte(BaseOpcode, CurByte, OS);
757 EmitRegModRMByte(MI.getOperand(CurOp),
758 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
762 case X86II::MRMDestMem:
763 EmitSegmentOverridePrefix(MI.getOperand(CurOp + 4), TSFlags, CurByte, OS);
764 EmitByte(BaseOpcode, CurByte, OS);
765 EmitMemModRMByte(MI, CurOp,
766 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
767 TSFlags, CurByte, OS, Fixups);
768 CurOp += X86AddrNumOperands + 1;
771 case X86II::MRMSrcReg:
772 EmitByte(BaseOpcode, CurByte, OS);
773 SrcRegNum = CurOp + 1;
775 if (IsAVXForm) // Skip 1st src (which is encoded in VEX_VVVV)
778 EmitRegModRMByte(MI.getOperand(SrcRegNum),
779 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
780 CurOp = SrcRegNum + 1;
783 case X86II::MRMSrcMem: {
784 int AddrOperands = X86AddrNumOperands;
785 unsigned FirstMemOp = CurOp+1;
788 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
791 // FIXME: Maybe lea should have its own form? This is a horrible hack.
792 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
793 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
794 --AddrOperands; // No segment register
796 EmitSegmentOverridePrefix(MI.getOperand(FirstMemOp+4),
797 TSFlags, CurByte, OS);
799 EmitByte(BaseOpcode, CurByte, OS);
802 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
803 TSFlags, CurByte, OS, Fixups);
804 CurOp += AddrOperands + 1;
808 case X86II::MRM0r: case X86II::MRM1r:
809 case X86II::MRM2r: case X86II::MRM3r:
810 case X86II::MRM4r: case X86II::MRM5r:
811 case X86II::MRM6r: case X86II::MRM7r:
812 EmitByte(BaseOpcode, CurByte, OS);
813 EmitRegModRMByte(MI.getOperand(CurOp++),
814 (TSFlags & X86II::FormMask)-X86II::MRM0r,
817 case X86II::MRM0m: case X86II::MRM1m:
818 case X86II::MRM2m: case X86II::MRM3m:
819 case X86II::MRM4m: case X86II::MRM5m:
820 case X86II::MRM6m: case X86II::MRM7m:
821 EmitSegmentOverridePrefix(MI.getOperand(CurOp+4), TSFlags, CurByte, OS);
822 EmitByte(BaseOpcode, CurByte, OS);
823 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
824 TSFlags, CurByte, OS, Fixups);
825 CurOp += X86AddrNumOperands;
828 EmitByte(BaseOpcode, CurByte, OS);
829 EmitByte(0xC1, CurByte, OS);
832 EmitByte(BaseOpcode, CurByte, OS);
833 EmitByte(0xC2, CurByte, OS);
836 EmitByte(BaseOpcode, CurByte, OS);
837 EmitByte(0xC3, CurByte, OS);
840 EmitByte(BaseOpcode, CurByte, OS);
841 EmitByte(0xC4, CurByte, OS);
844 EmitByte(BaseOpcode, CurByte, OS);
845 EmitByte(0xC8, CurByte, OS);
848 EmitByte(BaseOpcode, CurByte, OS);
849 EmitByte(0xC9, CurByte, OS);
852 EmitByte(BaseOpcode, CurByte, OS);
853 EmitByte(0xE8, CurByte, OS);
856 EmitByte(BaseOpcode, CurByte, OS);
857 EmitByte(0xF0, CurByte, OS);
860 EmitByte(BaseOpcode, CurByte, OS);
861 EmitByte(0xF8, CurByte, OS);
864 EmitByte(BaseOpcode, CurByte, OS);
865 EmitByte(0xF9, CurByte, OS);
869 // If there is a remaining operand, it must be a trailing immediate. Emit it
870 // according to the right size for the instruction.
872 EmitImmediate(MI.getOperand(CurOp++),
873 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
874 CurByte, OS, Fixups);
878 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
879 errs() << "Cannot encode all operands of: ";