1 //====- X86InstrX86-64.td - Describe the X86 Instruction Set ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions...
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
22 // 64-bits but only 8 bits are significant.
23 def i64i8imm : Operand<i64>;
25 def lea64mem : Operand<i64> {
26 let PrintMethod = "printi64mem";
27 let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
30 def lea64_32mem : Operand<i32> {
31 let PrintMethod = "printlea64_32mem";
32 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
35 //===----------------------------------------------------------------------===//
36 // Complex Pattern Definitions...
38 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
39 [add, mul, shl, or, frameindex, X86Wrapper],
42 //===----------------------------------------------------------------------===//
43 // Instruction templates...
46 class RI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
47 : I<o, F, ops, asm, pattern>, REX_W;
48 class RIi8 <bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
49 : Ii8<o, F, ops, asm, pattern>, REX_W;
50 class RIi32 <bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
51 : Ii32<o, F, ops, asm, pattern>, REX_W;
53 class RIi64<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
54 : X86Inst<o, f, Imm64, ops, asm>, REX_W {
55 let Pattern = pattern;
59 class RSSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
60 : SSI<o, F, ops, asm, pattern>, REX_W;
61 class RSDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
62 : SDI<o, F, ops, asm, pattern>, REX_W;
63 class RPDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
64 : PDI<o, F, ops, asm, pattern>, REX_W;
66 //===----------------------------------------------------------------------===//
67 // Pattern fragments...
70 def i64immSExt32 : PatLeaf<(i64 imm), [{
71 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
72 // sign extended field.
73 return (int64_t)N->getValue() == (int32_t)N->getValue();
76 def i64immZExt32 : PatLeaf<(i64 imm), [{
77 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
78 // unsignedsign extended field.
79 return (uint64_t)N->getValue() == (uint32_t)N->getValue();
82 def i64immSExt8 : PatLeaf<(i64 imm), [{
83 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
84 // sign extended field.
85 return (int64_t)N->getValue() == (int8_t)N->getValue();
88 def sextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (sextloadi1 node:$ptr))>;
89 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
90 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
91 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
93 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
94 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
95 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
96 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
98 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
99 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
100 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
101 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
103 //===----------------------------------------------------------------------===//
104 // Instruction list...
107 def IMPLICIT_DEF_GR64 : I<0, Pseudo, (ops GR64:$dst),
108 "#IMPLICIT_DEF $dst",
109 [(set GR64:$dst, (undef))]>;
111 //===----------------------------------------------------------------------===//
112 // Call Instructions...
114 let isCall = 1, noResults = 1 in
115 // All calls clobber the non-callee saved registers...
116 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
117 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
118 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
119 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
120 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15] in {
121 def CALL64pcrel32 : I<0xE8, RawFrm, (ops i64imm:$dst, variable_ops),
122 "call ${dst:call}", []>;
123 def CALL64r : I<0xFF, MRM2r, (ops GR64:$dst, variable_ops),
124 "call {*}$dst", [(X86call GR64:$dst)]>;
125 def CALL64m : I<0xFF, MRM2m, (ops i64mem:$dst, variable_ops),
130 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in {
131 def JMP64r : I<0xFF, MRM4r, (ops GR64:$dst), "jmp{q} {*}$dst",
132 [(brind GR64:$dst)]>;
133 def JMP64m : I<0xFF, MRM4m, (ops i64mem:$dst), "jmp{q} {*}$dst",
134 [(brind (loadi64 addr:$dst))]>;
137 //===----------------------------------------------------------------------===//
138 // Miscellaneous Instructions...
140 def LEAVE64 : I<0xC9, RawFrm,
141 (ops), "leave", []>, Imp<[RBP,RSP],[RBP,RSP]>;
142 def POP64r : I<0x58, AddRegFrm,
143 (ops GR64:$reg), "pop{q} $reg", []>, Imp<[RSP],[RSP]>;
145 def LEA64_32r : I<0x8D, MRMSrcMem,
146 (ops GR32:$dst, lea64_32mem:$src),
147 "lea{l} {$src|$dst}, {$dst|$src}",
148 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
150 def LEA64r : RI<0x8D, MRMSrcMem, (ops GR64:$dst, lea64mem:$src),
151 "lea{q} {$src|$dst}, {$dst|$src}",
152 [(set GR64:$dst, lea64addr:$src)]>;
154 let isTwoAddress = 1 in
155 def BSWAP64r : RI<0xC8, AddRegFrm, (ops GR64:$dst, GR64:$src),
157 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
159 def XCHG64rr : RI<0x87, MRMDestReg, (ops GR64:$src1, GR64:$src2),
160 "xchg{q} {$src2|$src1}, {$src1|$src2}", []>;
161 def XCHG64mr : RI<0x87, MRMDestMem, (ops i64mem:$src1, GR64:$src2),
162 "xchg{q} {$src2|$src1}, {$src1|$src2}", []>;
163 def XCHG64rm : RI<0x87, MRMSrcMem, (ops GR64:$src1, i64mem:$src2),
164 "xchg{q} {$src2|$src1}, {$src1|$src2}", []>;
167 def REP_MOVSQ : RI<0xA5, RawFrm, (ops), "{rep;movsq|rep movsq}",
168 [(X86rep_movs i64)]>,
169 Imp<[RCX,RDI,RSI], [RCX,RDI,RSI]>, REP;
170 def REP_STOSQ : RI<0xAB, RawFrm, (ops), "{rep;stosq|rep stosq}",
171 [(X86rep_stos i64)]>,
172 Imp<[RAX,RCX,RDI], [RCX,RDI]>, REP;
174 //===----------------------------------------------------------------------===//
175 // Move Instructions...
178 def MOV64rr : RI<0x89, MRMDestReg, (ops GR64:$dst, GR64:$src),
179 "mov{q} {$src, $dst|$dst, $src}", []>;
181 def MOV64ri : RIi64<0xB8, AddRegFrm, (ops GR64:$dst, i64imm:$src),
182 "movabs{q} {$src, $dst|$dst, $src}",
183 [(set GR64:$dst, imm:$src)]>;
184 def MOV64ri32 : RIi32<0xC7, MRM0r, (ops GR64:$dst, i64i32imm:$src),
185 "mov{q} {$src, $dst|$dst, $src}",
186 [(set GR64:$dst, i64immSExt32:$src)]>;
188 def MOV64rm : RI<0x8B, MRMSrcMem, (ops GR64:$dst, i64mem:$src),
189 "mov{q} {$src, $dst|$dst, $src}",
190 [(set GR64:$dst, (load addr:$src))]>;
192 def MOV64mr : RI<0x89, MRMDestMem, (ops i64mem:$dst, GR64:$src),
193 "mov{q} {$src, $dst|$dst, $src}",
194 [(store GR64:$src, addr:$dst)]>;
195 def MOV64mi32 : RIi32<0xC7, MRM0m, (ops i64mem:$dst, i64i32imm:$src),
196 "mov{q} {$src, $dst|$dst, $src}",
197 [(store i64immSExt32:$src, addr:$dst)]>;
199 // Sign/Zero extenders
201 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (ops GR64:$dst, GR8 :$src),
202 "movs{bq|x} {$src, $dst|$dst, $src}",
203 [(set GR64:$dst, (sext GR8:$src))]>, TB;
204 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (ops GR64:$dst, i8mem :$src),
205 "movs{bq|x} {$src, $dst|$dst, $src}",
206 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
207 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (ops GR64:$dst, GR16:$src),
208 "movs{wq|x} {$src, $dst|$dst, $src}",
209 [(set GR64:$dst, (sext GR16:$src))]>, TB;
210 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (ops GR64:$dst, i16mem:$src),
211 "movs{wq|x} {$src, $dst|$dst, $src}",
212 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
213 def MOVSX64rr32: RI<0x63, MRMSrcReg, (ops GR64:$dst, GR32:$src),
214 "movs{lq|xd} {$src, $dst|$dst, $src}",
215 [(set GR64:$dst, (sext GR32:$src))]>;
216 def MOVSX64rm32: RI<0x63, MRMSrcMem, (ops GR64:$dst, i32mem:$src),
217 "movs{lq|xd} {$src, $dst|$dst, $src}",
218 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
220 def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (ops GR64:$dst, GR8 :$src),
221 "movz{bq|x} {$src, $dst|$dst, $src}",
222 [(set GR64:$dst, (zext GR8:$src))]>, TB;
223 def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (ops GR64:$dst, i8mem :$src),
224 "movz{bq|x} {$src, $dst|$dst, $src}",
225 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
226 def MOVZX64rr16: RI<0xB7, MRMSrcReg, (ops GR64:$dst, GR16:$src),
227 "movz{wq|x} {$src, $dst|$dst, $src}",
228 [(set GR64:$dst, (zext GR16:$src))]>, TB;
229 def MOVZX64rm16: RI<0xB7, MRMSrcMem, (ops GR64:$dst, i16mem:$src),
230 "movz{wq|x} {$src, $dst|$dst, $src}",
231 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
233 def CDQE : RI<0x98, RawFrm, (ops),
234 "{cltq|cdqe}", []>, Imp<[EAX],[RAX]>; // RAX = signext(EAX)
236 def CQO : RI<0x99, RawFrm, (ops),
237 "{cqto|cqo}", []>, Imp<[RAX],[RAX,RDX]>; // RDX:RAX = signext(RAX)
239 //===----------------------------------------------------------------------===//
240 // Arithmetic Instructions...
243 let isTwoAddress = 1 in {
244 let isConvertibleToThreeAddress = 1 in {
245 let isCommutable = 1 in
246 def ADD64rr : RI<0x01, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
247 "add{q} {$src2, $dst|$dst, $src2}",
248 [(set GR64:$dst, (add GR64:$src1, GR64:$src2))]>;
250 def ADD64ri32 : RIi32<0x81, MRM0r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
251 "add{q} {$src2, $dst|$dst, $src2}",
252 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2))]>;
253 def ADD64ri8 : RIi8<0x83, MRM0r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
254 "add{q} {$src2, $dst|$dst, $src2}",
255 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2))]>;
256 } // isConvertibleToThreeAddress
258 def ADD64rm : RI<0x03, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2),
259 "add{q} {$src2, $dst|$dst, $src2}",
260 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2)))]>;
263 def ADD64mr : RI<0x01, MRMDestMem, (ops i64mem:$dst, GR64:$src2),
264 "add{q} {$src2, $dst|$dst, $src2}",
265 [(store (add (load addr:$dst), GR64:$src2), addr:$dst)]>;
266 def ADD64mi32 : RIi32<0x81, MRM0m, (ops i64mem:$dst, i64i32imm :$src2),
267 "add{q} {$src2, $dst|$dst, $src2}",
268 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
269 def ADD64mi8 : RIi8<0x83, MRM0m, (ops i64mem:$dst, i64i8imm :$src2),
270 "add{q} {$src2, $dst|$dst, $src2}",
271 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
273 let isTwoAddress = 1 in {
274 let isCommutable = 1 in
275 def ADC64rr : RI<0x11, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
276 "adc{q} {$src2, $dst|$dst, $src2}",
277 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
279 def ADC64rm : RI<0x13, MRMSrcMem , (ops GR64:$dst, GR64:$src1, i64mem:$src2),
280 "adc{q} {$src2, $dst|$dst, $src2}",
281 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
283 def ADC64ri32 : RIi32<0x81, MRM2r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
284 "adc{q} {$src2, $dst|$dst, $src2}",
285 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
286 def ADC64ri8 : RIi8<0x83, MRM2r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
287 "adc{q} {$src2, $dst|$dst, $src2}",
288 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
291 def ADC64mr : RI<0x11, MRMDestMem, (ops i64mem:$dst, GR64:$src2),
292 "adc{q} {$src2, $dst|$dst, $src2}",
293 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
294 def ADC64mi32 : RIi32<0x81, MRM2m, (ops i64mem:$dst, i64i32imm:$src2),
295 "adc{q} {$src2, $dst|$dst, $src2}",
296 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
297 def ADC64mi8 : RIi8<0x83, MRM2m, (ops i64mem:$dst, i64i8imm :$src2),
298 "adc{q} {$src2, $dst|$dst, $src2}",
299 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
301 let isTwoAddress = 1 in {
302 def SUB64rr : RI<0x29, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
303 "sub{q} {$src2, $dst|$dst, $src2}",
304 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
306 def SUB64rm : RI<0x2B, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2),
307 "sub{q} {$src2, $dst|$dst, $src2}",
308 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2)))]>;
310 def SUB64ri32 : RIi32<0x81, MRM5r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
311 "sub{q} {$src2, $dst|$dst, $src2}",
312 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2))]>;
313 def SUB64ri8 : RIi8<0x83, MRM5r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
314 "sub{q} {$src2, $dst|$dst, $src2}",
315 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2))]>;
318 def SUB64mr : RI<0x29, MRMDestMem, (ops i64mem:$dst, GR64:$src2),
319 "sub{q} {$src2, $dst|$dst, $src2}",
320 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst)]>;
321 def SUB64mi32 : RIi32<0x81, MRM5m, (ops i64mem:$dst, i64i32imm:$src2),
322 "sub{q} {$src2, $dst|$dst, $src2}",
323 [(store (sub (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
324 def SUB64mi8 : RIi8<0x83, MRM5m, (ops i64mem:$dst, i64i8imm :$src2),
325 "sub{q} {$src2, $dst|$dst, $src2}",
326 [(store (sub (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
328 let isTwoAddress = 1 in {
329 def SBB64rr : RI<0x19, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
330 "sbb{q} {$src2, $dst|$dst, $src2}",
331 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
333 def SBB64rm : RI<0x1B, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2),
334 "sbb{q} {$src2, $dst|$dst, $src2}",
335 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
337 def SBB64ri32 : RIi32<0x81, MRM3r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
338 "sbb{q} {$src2, $dst|$dst, $src2}",
339 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
340 def SBB64ri8 : RIi8<0x83, MRM3r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
341 "sbb{q} {$src2, $dst|$dst, $src2}",
342 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
345 def SBB64mr : RI<0x19, MRMDestMem, (ops i64mem:$dst, GR64:$src2),
346 "sbb{q} {$src2, $dst|$dst, $src2}",
347 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
348 def SBB64mi32 : RIi32<0x81, MRM3m, (ops i64mem:$dst, i64i32imm:$src2),
349 "sbb{q} {$src2, $dst|$dst, $src2}",
350 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
351 def SBB64mi8 : RIi8<0x83, MRM3m, (ops i64mem:$dst, i64i8imm :$src2),
352 "sbb{q} {$src2, $dst|$dst, $src2}",
353 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
355 // Unsigned multiplication
356 def MUL64r : RI<0xF7, MRM4r, (ops GR64:$src),
358 Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*GR64
359 def MUL64m : RI<0xF7, MRM4m, (ops i64mem:$src),
361 Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*[mem64]
363 // Signed multiplication
364 def IMUL64r : RI<0xF7, MRM5r, (ops GR64:$src),
366 Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*GR64
367 def IMUL64m : RI<0xF7, MRM5m, (ops i64mem:$src),
369 Imp<[RAX],[RAX,RDX]>; // RAX,RDX = RAX*[mem64]
371 let isTwoAddress = 1 in {
372 let isCommutable = 1 in
373 def IMUL64rr : RI<0xAF, MRMSrcReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
374 "imul{q} {$src2, $dst|$dst, $src2}",
375 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>, TB;
377 def IMUL64rm : RI<0xAF, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2),
378 "imul{q} {$src2, $dst|$dst, $src2}",
379 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2)))]>, TB;
382 // Suprisingly enough, these are not two address instructions!
383 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
384 (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
385 "imul{q} {$src2, $src1, $dst|$dst, $src1, $src2}",
386 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>;
387 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
388 (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
389 "imul{q} {$src2, $src1, $dst|$dst, $src1, $src2}",
390 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2))]>;
391 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
392 (ops GR64:$dst, i64mem:$src1, i64i32imm:$src2),
393 "imul{q} {$src2, $src1, $dst|$dst, $src1, $src2}",
394 [(set GR64:$dst, (mul (load addr:$src1), i64immSExt32:$src2))]>;
395 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
396 (ops GR64:$dst, i64mem:$src1, i64i8imm: $src2),
397 "imul{q} {$src2, $src1, $dst|$dst, $src1, $src2}",
398 [(set GR64:$dst, (mul (load addr:$src1), i64immSExt8:$src2))]>;
400 // Unsigned division / remainder
401 def DIV64r : RI<0xF7, MRM6r, (ops GR64:$src), // RDX:RAX/r64 = RAX,RDX
402 "div{q} $src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
403 def DIV64m : RI<0xF7, MRM6m, (ops i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
404 "div{q} $src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
406 // Signed division / remainder
407 def IDIV64r: RI<0xF7, MRM7r, (ops GR64:$src), // RDX:RAX/r64 = RAX,RDX
408 "idiv{q} $src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
409 def IDIV64m: RI<0xF7, MRM7m, (ops i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
410 "idiv{q} $src", []>, Imp<[RAX,RDX],[RAX,RDX]>;
412 // Unary instructions
413 let CodeSize = 2 in {
414 let isTwoAddress = 1 in
415 def NEG64r : RI<0xF7, MRM3r, (ops GR64:$dst, GR64:$src), "neg{q} $dst",
416 [(set GR64:$dst, (ineg GR64:$src))]>;
417 def NEG64m : RI<0xF7, MRM3m, (ops i64mem:$dst), "neg{q} $dst",
418 [(store (ineg (loadi64 addr:$dst)), addr:$dst)]>;
420 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
421 def INC64r : RI<0xFF, MRM0r, (ops GR64:$dst, GR64:$src), "inc{q} $dst",
422 [(set GR64:$dst, (add GR64:$src, 1))]>;
423 def INC64m : RI<0xFF, MRM0m, (ops i64mem:$dst), "inc{q} $dst",
424 [(store (add (loadi64 addr:$dst), 1), addr:$dst)]>;
426 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
427 def DEC64r : RI<0xFF, MRM1r, (ops GR64:$dst, GR64:$src), "dec{q} $dst",
428 [(set GR64:$dst, (add GR64:$src, -1))]>;
429 def DEC64m : RI<0xFF, MRM1m, (ops i64mem:$dst), "dec{q} $dst",
430 [(store (add (loadi64 addr:$dst), -1), addr:$dst)]>;
432 // In 64-bit mode, single byte INC and DEC cannot be encoded.
433 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
434 // Can transform into LEA.
435 def INC64_16r : I<0xFF, MRM0r, (ops GR16:$dst, GR16:$src), "inc{w} $dst",
436 [(set GR16:$dst, (add GR16:$src, 1))]>,
437 OpSize, Requires<[In64BitMode]>;
438 def INC64_32r : I<0xFF, MRM0r, (ops GR32:$dst, GR32:$src), "inc{l} $dst",
439 [(set GR32:$dst, (add GR32:$src, 1))]>,
440 Requires<[In64BitMode]>;
441 def DEC64_16r : I<0xFF, MRM1r, (ops GR16:$dst, GR16:$src), "dec{w} $dst",
442 [(set GR16:$dst, (add GR16:$src, -1))]>,
443 OpSize, Requires<[In64BitMode]>;
444 def DEC64_32r : I<0xFF, MRM1r, (ops GR32:$dst, GR32:$src), "dec{l} $dst",
445 [(set GR32:$dst, (add GR32:$src, -1))]>,
446 Requires<[In64BitMode]>;
447 } // isConvertibleToThreeAddress
451 // Shift instructions
452 let isTwoAddress = 1 in {
453 def SHL64rCL : RI<0xD3, MRM4r, (ops GR64:$dst, GR64:$src),
454 "shl{q} {%cl, $dst|$dst, %CL}",
455 [(set GR64:$dst, (shl GR64:$src, CL))]>,
457 def SHL64ri : RIi8<0xC1, MRM4r, (ops GR64:$dst, GR64:$src1, i8imm:$src2),
458 "shl{q} {$src2, $dst|$dst, $src2}",
459 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
460 def SHL64r1 : RI<0xD1, MRM4r, (ops GR64:$dst, GR64:$src1),
464 def SHL64mCL : RI<0xD3, MRM4m, (ops i64mem:$dst),
465 "shl{q} {%cl, $dst|$dst, %CL}",
466 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>,
468 def SHL64mi : RIi8<0xC1, MRM4m, (ops i64mem:$dst, i8imm:$src),
469 "shl{q} {$src, $dst|$dst, $src}",
470 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
471 def SHL64m1 : RI<0xD1, MRM4m, (ops i64mem:$dst),
473 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
475 let isTwoAddress = 1 in {
476 def SHR64rCL : RI<0xD3, MRM5r, (ops GR64:$dst, GR64:$src),
477 "shr{q} {%cl, $dst|$dst, %CL}",
478 [(set GR64:$dst, (srl GR64:$src, CL))]>,
480 def SHR64ri : RIi8<0xC1, MRM5r, (ops GR64:$dst, GR64:$src1, i8imm:$src2),
481 "shr{q} {$src2, $dst|$dst, $src2}",
482 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
483 def SHR64r1 : RI<0xD1, MRM5r, (ops GR64:$dst, GR64:$src1),
485 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
488 def SHR64mCL : RI<0xD3, MRM5m, (ops i64mem:$dst),
489 "shr{q} {%cl, $dst|$dst, %CL}",
490 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>,
492 def SHR64mi : RIi8<0xC1, MRM5m, (ops i64mem:$dst, i8imm:$src),
493 "shr{q} {$src, $dst|$dst, $src}",
494 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
495 def SHR64m1 : RI<0xD1, MRM5m, (ops i64mem:$dst),
497 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
499 let isTwoAddress = 1 in {
500 def SAR64rCL : RI<0xD3, MRM7r, (ops GR64:$dst, GR64:$src),
501 "sar{q} {%cl, $dst|$dst, %CL}",
502 [(set GR64:$dst, (sra GR64:$src, CL))]>, Imp<[CL],[]>;
503 def SAR64ri : RIi8<0xC1, MRM7r, (ops GR64:$dst, GR64:$src1, i8imm:$src2),
504 "sar{q} {$src2, $dst|$dst, $src2}",
505 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
506 def SAR64r1 : RI<0xD1, MRM7r, (ops GR64:$dst, GR64:$src1),
508 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
511 def SAR64mCL : RI<0xD3, MRM7m, (ops i64mem:$dst),
512 "sar{q} {%cl, $dst|$dst, %CL}",
513 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>,
515 def SAR64mi : RIi8<0xC1, MRM7m, (ops i64mem:$dst, i8imm:$src),
516 "sar{q} {$src, $dst|$dst, $src}",
517 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
518 def SAR64m1 : RI<0xD1, MRM7m, (ops i64mem:$dst),
520 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
522 // Rotate instructions
523 let isTwoAddress = 1 in {
524 def ROL64rCL : RI<0xD3, MRM0r, (ops GR64:$dst, GR64:$src),
525 "rol{q} {%cl, $dst|$dst, %CL}",
526 [(set GR64:$dst, (rotl GR64:$src, CL))]>, Imp<[CL],[]>;
527 def ROL64ri : RIi8<0xC1, MRM0r, (ops GR64:$dst, GR64:$src1, i8imm:$src2),
528 "rol{q} {$src2, $dst|$dst, $src2}",
529 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
530 def ROL64r1 : RI<0xD1, MRM0r, (ops GR64:$dst, GR64:$src1),
532 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
535 def ROL64mCL : I<0xD3, MRM0m, (ops i64mem:$dst),
536 "rol{q} {%cl, $dst|$dst, %CL}",
537 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>,
539 def ROL64mi : RIi8<0xC1, MRM0m, (ops i64mem:$dst, i8imm:$src),
540 "rol{q} {$src, $dst|$dst, $src}",
541 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
542 def ROL64m1 : RI<0xD1, MRM0m, (ops i64mem:$dst),
544 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
546 let isTwoAddress = 1 in {
547 def ROR64rCL : RI<0xD3, MRM1r, (ops GR64:$dst, GR64:$src),
548 "ror{q} {%cl, $dst|$dst, %CL}",
549 [(set GR64:$dst, (rotr GR64:$src, CL))]>, Imp<[CL],[]>;
550 def ROR64ri : RIi8<0xC1, MRM1r, (ops GR64:$dst, GR64:$src1, i8imm:$src2),
551 "ror{q} {$src2, $dst|$dst, $src2}",
552 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
553 def ROR64r1 : RI<0xD1, MRM1r, (ops GR64:$dst, GR64:$src1),
555 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
558 def ROR64mCL : RI<0xD3, MRM1m, (ops i64mem:$dst),
559 "ror{q} {%cl, $dst|$dst, %CL}",
560 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>,
562 def ROR64mi : RIi8<0xC1, MRM1m, (ops i64mem:$dst, i8imm:$src),
563 "ror{q} {$src, $dst|$dst, $src}",
564 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
565 def ROR64m1 : RI<0xD1, MRM1m, (ops i64mem:$dst),
567 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
569 // Double shift instructions (generalizations of rotate)
570 let isTwoAddress = 1 in {
571 def SHLD64rrCL : RI<0xA5, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
572 "shld{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
574 def SHRD64rrCL : RI<0xAD, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
575 "shrd{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
578 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
579 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
580 (ops GR64:$dst, GR64:$src1, GR64:$src2, i8imm:$src3),
581 "shld{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
583 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
584 (ops GR64:$dst, GR64:$src1, GR64:$src2, i8imm:$src3),
585 "shrd{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
590 // Temporary hack: there is no patterns associated with these instructions
591 // so we have to tell tblgen that these do not produce results.
592 let noResults = 1 in {
593 def SHLD64mrCL : RI<0xA5, MRMDestMem, (ops i64mem:$dst, GR64:$src2),
594 "shld{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
596 def SHRD64mrCL : RI<0xAD, MRMDestMem, (ops i64mem:$dst, GR64:$src2),
597 "shrd{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
599 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
600 (ops i64mem:$dst, GR64:$src2, i8imm:$src3),
601 "shld{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
603 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
604 (ops i64mem:$dst, GR64:$src2, i8imm:$src3),
605 "shrd{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
609 //===----------------------------------------------------------------------===//
610 // Logical Instructions...
613 let isTwoAddress = 1 in
614 def NOT64r : RI<0xF7, MRM2r, (ops GR64:$dst, GR64:$src), "not{q} $dst",
615 [(set GR64:$dst, (not GR64:$src))]>;
616 def NOT64m : RI<0xF7, MRM2m, (ops i64mem:$dst), "not{q} $dst",
617 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
619 let isTwoAddress = 1 in {
620 let isCommutable = 1 in
621 def AND64rr : RI<0x21, MRMDestReg,
622 (ops GR64:$dst, GR64:$src1, GR64:$src2),
623 "and{q} {$src2, $dst|$dst, $src2}",
624 [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
625 def AND64rm : RI<0x23, MRMSrcMem,
626 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
627 "and{q} {$src2, $dst|$dst, $src2}",
628 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2)))]>;
629 def AND64ri32 : RIi32<0x81, MRM4r,
630 (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
631 "and{q} {$src2, $dst|$dst, $src2}",
632 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2))]>;
633 def AND64ri8 : RIi8<0x83, MRM4r,
634 (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
635 "and{q} {$src2, $dst|$dst, $src2}",
636 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2))]>;
639 def AND64mr : RI<0x21, MRMDestMem,
640 (ops i64mem:$dst, GR64:$src),
641 "and{q} {$src, $dst|$dst, $src}",
642 [(store (and (load addr:$dst), GR64:$src), addr:$dst)]>;
643 def AND64mi32 : RIi32<0x81, MRM4m,
644 (ops i64mem:$dst, i64i32imm:$src),
645 "and{q} {$src, $dst|$dst, $src}",
646 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
647 def AND64mi8 : RIi8<0x83, MRM4m,
648 (ops i64mem:$dst, i64i8imm :$src),
649 "and{q} {$src, $dst|$dst, $src}",
650 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
652 let isTwoAddress = 1 in {
653 let isCommutable = 1 in
654 def OR64rr : RI<0x09, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
655 "or{q} {$src2, $dst|$dst, $src2}",
656 [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
657 def OR64rm : RI<0x0B, MRMSrcMem , (ops GR64:$dst, GR64:$src1, i64mem:$src2),
658 "or{q} {$src2, $dst|$dst, $src2}",
659 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2)))]>;
660 def OR64ri32 : RIi32<0x81, MRM1r, (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
661 "or{q} {$src2, $dst|$dst, $src2}",
662 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2))]>;
663 def OR64ri8 : RIi8<0x83, MRM1r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
664 "or{q} {$src2, $dst|$dst, $src2}",
665 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2))]>;
668 def OR64mr : RI<0x09, MRMDestMem, (ops i64mem:$dst, GR64:$src),
669 "or{q} {$src, $dst|$dst, $src}",
670 [(store (or (load addr:$dst), GR64:$src), addr:$dst)]>;
671 def OR64mi32 : RIi32<0x81, MRM1m, (ops i64mem:$dst, i64i32imm:$src),
672 "or{q} {$src, $dst|$dst, $src}",
673 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
674 def OR64mi8 : RIi8<0x83, MRM1m, (ops i64mem:$dst, i64i8imm:$src),
675 "or{q} {$src, $dst|$dst, $src}",
676 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
678 let isTwoAddress = 1 in {
679 let isCommutable = 1 in
680 def XOR64rr : RI<0x31, MRMDestReg, (ops GR64:$dst, GR64:$src1, GR64:$src2),
681 "xor{q} {$src2, $dst|$dst, $src2}",
682 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
683 def XOR64rm : RI<0x33, MRMSrcMem, (ops GR64:$dst, GR64:$src1, i64mem:$src2),
684 "xor{q} {$src2, $dst|$dst, $src2}",
685 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2)))]>;
686 def XOR64ri32 : RIi32<0x81, MRM6r,
687 (ops GR64:$dst, GR64:$src1, i64i32imm:$src2),
688 "xor{q} {$src2, $dst|$dst, $src2}",
689 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2))]>;
690 def XOR64ri8 : RIi8<0x83, MRM6r, (ops GR64:$dst, GR64:$src1, i64i8imm:$src2),
691 "xor{q} {$src2, $dst|$dst, $src2}",
692 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2))]>;
695 def XOR64mr : RI<0x31, MRMDestMem, (ops i64mem:$dst, GR64:$src),
696 "xor{q} {$src, $dst|$dst, $src}",
697 [(store (xor (load addr:$dst), GR64:$src), addr:$dst)]>;
698 def XOR64mi32 : RIi32<0x81, MRM6m, (ops i64mem:$dst, i64i32imm:$src),
699 "xor{q} {$src, $dst|$dst, $src}",
700 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
701 def XOR64mi8 : RIi8<0x83, MRM6m, (ops i64mem:$dst, i64i8imm :$src),
702 "xor{q} {$src, $dst|$dst, $src}",
703 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
705 //===----------------------------------------------------------------------===//
706 // Comparison Instructions...
709 // Integer comparison
710 let isCommutable = 1 in
711 def TEST64rr : RI<0x85, MRMDestReg, (ops GR64:$src1, GR64:$src2),
712 "test{q} {$src2, $src1|$src1, $src2}",
713 [(X86cmp (and GR64:$src1, GR64:$src2), 0)]>;
714 def TEST64rm : RI<0x85, MRMSrcMem, (ops GR64:$src1, i64mem:$src2),
715 "test{q} {$src2, $src1|$src1, $src2}",
716 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0)]>;
717 def TEST64ri32 : RIi32<0xF7, MRM0r, (ops GR64:$src1, i64i32imm:$src2),
718 "test{q} {$src2, $src1|$src1, $src2}",
719 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0)]>;
720 def TEST64mi32 : RIi32<0xF7, MRM0m, (ops i64mem:$src1, i64i32imm:$src2),
721 "test{q} {$src2, $src1|$src1, $src2}",
722 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0)]>;
724 def CMP64rr : RI<0x39, MRMDestReg, (ops GR64:$src1, GR64:$src2),
725 "cmp{q} {$src2, $src1|$src1, $src2}",
726 [(X86cmp GR64:$src1, GR64:$src2)]>;
727 def CMP64mr : RI<0x39, MRMDestMem, (ops i64mem:$src1, GR64:$src2),
728 "cmp{q} {$src2, $src1|$src1, $src2}",
729 [(X86cmp (loadi64 addr:$src1), GR64:$src2)]>;
730 def CMP64rm : RI<0x3B, MRMSrcMem, (ops GR64:$src1, i64mem:$src2),
731 "cmp{q} {$src2, $src1|$src1, $src2}",
732 [(X86cmp GR64:$src1, (loadi64 addr:$src2))]>;
733 def CMP64ri32 : RIi32<0x81, MRM7r, (ops GR64:$src1, i64i32imm:$src2),
734 "cmp{q} {$src2, $src1|$src1, $src2}",
735 [(X86cmp GR64:$src1, i64immSExt32:$src2)]>;
736 def CMP64mi32 : RIi32<0x81, MRM7m, (ops i64mem:$src1, i64i32imm:$src2),
737 "cmp{q} {$src2, $src1|$src1, $src2}",
738 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2)]>;
739 def CMP64mi8 : RIi8<0x83, MRM7m, (ops i64mem:$src1, i64i8imm:$src2),
740 "cmp{q} {$src2, $src1|$src1, $src2}",
741 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2)]>;
742 def CMP64ri8 : RIi8<0x83, MRM7r, (ops GR64:$src1, i64i8imm:$src2),
743 "cmp{q} {$src2, $src1|$src1, $src2}",
744 [(X86cmp GR64:$src1, i64immSExt8:$src2)]>;
747 let isTwoAddress = 1 in {
748 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
749 (ops GR64:$dst, GR64:$src1, GR64:$src2),
750 "cmovb {$src2, $dst|$dst, $src2}",
751 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
753 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
754 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
755 "cmovb {$src2, $dst|$dst, $src2}",
756 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
758 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
759 (ops GR64:$dst, GR64:$src1, GR64:$src2),
760 "cmovae {$src2, $dst|$dst, $src2}",
761 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
763 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
764 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
765 "cmovae {$src2, $dst|$dst, $src2}",
766 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
768 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
769 (ops GR64:$dst, GR64:$src1, GR64:$src2),
770 "cmove {$src2, $dst|$dst, $src2}",
771 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
773 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
774 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
775 "cmove {$src2, $dst|$dst, $src2}",
776 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
778 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
779 (ops GR64:$dst, GR64:$src1, GR64:$src2),
780 "cmovne {$src2, $dst|$dst, $src2}",
781 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
783 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
784 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
785 "cmovne {$src2, $dst|$dst, $src2}",
786 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
788 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
789 (ops GR64:$dst, GR64:$src1, GR64:$src2),
790 "cmovbe {$src2, $dst|$dst, $src2}",
791 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
793 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
794 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
795 "cmovbe {$src2, $dst|$dst, $src2}",
796 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
798 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
799 (ops GR64:$dst, GR64:$src1, GR64:$src2),
800 "cmova {$src2, $dst|$dst, $src2}",
801 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
803 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
804 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
805 "cmova {$src2, $dst|$dst, $src2}",
806 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
808 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
809 (ops GR64:$dst, GR64:$src1, GR64:$src2),
810 "cmovl {$src2, $dst|$dst, $src2}",
811 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
813 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
814 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
815 "cmovl {$src2, $dst|$dst, $src2}",
816 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
818 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
819 (ops GR64:$dst, GR64:$src1, GR64:$src2),
820 "cmovge {$src2, $dst|$dst, $src2}",
821 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
823 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
824 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
825 "cmovge {$src2, $dst|$dst, $src2}",
826 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
828 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
829 (ops GR64:$dst, GR64:$src1, GR64:$src2),
830 "cmovle {$src2, $dst|$dst, $src2}",
831 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
833 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
834 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
835 "cmovle {$src2, $dst|$dst, $src2}",
836 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
838 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
839 (ops GR64:$dst, GR64:$src1, GR64:$src2),
840 "cmovg {$src2, $dst|$dst, $src2}",
841 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
843 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
844 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
845 "cmovg {$src2, $dst|$dst, $src2}",
846 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
848 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
849 (ops GR64:$dst, GR64:$src1, GR64:$src2),
850 "cmovs {$src2, $dst|$dst, $src2}",
851 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
853 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
854 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
855 "cmovs {$src2, $dst|$dst, $src2}",
856 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
858 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
859 (ops GR64:$dst, GR64:$src1, GR64:$src2),
860 "cmovns {$src2, $dst|$dst, $src2}",
861 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
863 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
864 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
865 "cmovns {$src2, $dst|$dst, $src2}",
866 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
868 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
869 (ops GR64:$dst, GR64:$src1, GR64:$src2),
870 "cmovp {$src2, $dst|$dst, $src2}",
871 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
873 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
874 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
875 "cmovp {$src2, $dst|$dst, $src2}",
876 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
878 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
879 (ops GR64:$dst, GR64:$src1, GR64:$src2),
880 "cmovnp {$src2, $dst|$dst, $src2}",
881 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
883 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
884 (ops GR64:$dst, GR64:$src1, i64mem:$src2),
885 "cmovnp {$src2, $dst|$dst, $src2}",
886 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
890 //===----------------------------------------------------------------------===//
891 // Conversion Instructions...
895 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (ops GR64:$dst, VR128:$src),
896 "cvtsd2si{q} {$src, $dst|$dst, $src}",
897 []>; // TODO: add intrinsic
898 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (ops GR64:$dst, f128mem:$src),
899 "cvtsd2si{q} {$src, $dst|$dst, $src}",
900 []>; // TODO: add intrinsic
901 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (ops GR64:$dst, FR64:$src),
902 "cvttsd2si{q} {$src, $dst|$dst, $src}",
903 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
904 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (ops GR64:$dst, f64mem:$src),
905 "cvttsd2si{q} {$src, $dst|$dst, $src}",
906 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
907 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (ops GR64:$dst, VR128:$src),
908 "cvttsd2si{q} {$src, $dst|$dst, $src}",
909 []>; // TODO: add intrinsic
910 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (ops GR64:$dst, f128mem:$src),
911 "cvttsd2si{q} {$src, $dst|$dst, $src}",
912 []>; // TODO: add intrinsic
915 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (ops FR64:$dst, GR64:$src),
916 "cvtsi2sd{q} {$src, $dst|$dst, $src}",
917 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
918 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (ops FR64:$dst, i64mem:$src),
919 "cvtsi2sd{q} {$src, $dst|$dst, $src}",
920 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
921 let isTwoAddress = 1 in {
922 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
923 (ops VR128:$dst, VR128:$src1, GR64:$src2),
924 "cvtsi2sd{q} {$src2, $dst|$dst, $src2}",
925 []>; // TODO: add intrinsic
926 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
927 (ops VR128:$dst, VR128:$src1, i64mem:$src2),
928 "cvtsi2sd{q} {$src2, $dst|$dst, $src2}",
929 []>; // TODO: add intrinsic
933 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (ops FR32:$dst, GR64:$src),
934 "cvtsi2ss{q} {$src, $dst|$dst, $src}",
935 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
936 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (ops FR32:$dst, i64mem:$src),
937 "cvtsi2ss{q} {$src, $dst|$dst, $src}",
938 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
939 let isTwoAddress = 1 in {
940 def Int_CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg,
941 (ops VR128:$dst, VR128:$src1, GR64:$src2),
942 "cvtsi2ss{q} {$src2, $dst|$dst, $src2}",
943 []>; // TODO: add intrinsic
944 def Int_CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem,
945 (ops VR128:$dst, VR128:$src1, i64mem:$src2),
946 "cvtsi2ss{q} {$src2, $dst|$dst, $src2}",
947 []>; // TODO: add intrinsic
951 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (ops GR64:$dst, VR128:$src),
952 "cvtss2si{q} {$src, $dst|$dst, $src}",
953 []>; // TODO: add intrinsic
954 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (ops GR64:$dst, f32mem:$src),
955 "cvtss2si{q} {$src, $dst|$dst, $src}",
956 []>; // TODO: add intrinsic
957 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (ops GR64:$dst, FR32:$src),
958 "cvttss2si{q} {$src, $dst|$dst, $src}",
959 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
960 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (ops GR64:$dst, f32mem:$src),
961 "cvttss2si{q} {$src, $dst|$dst, $src}",
962 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
963 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (ops GR64:$dst, VR128:$src),
964 "cvttss2si{q} {$src, $dst|$dst, $src}",
965 []>; // TODO: add intrinsic
966 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (ops GR64:$dst, f32mem:$src),
967 "cvttss2si{q} {$src, $dst|$dst, $src}",
968 []>; // TODO: add intrinsic
970 //===----------------------------------------------------------------------===//
971 // Alias Instructions
972 //===----------------------------------------------------------------------===//
975 // In 64-mode, each 64-bit and 32-bit registers has a low 8-bit sub-register.
976 def TRUNC_64to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR64:$src),
977 "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}",
978 [(set GR8:$dst, (trunc GR64:$src))]>;
979 def TRUNC_32to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR32:$src),
980 "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}",
981 [(set GR8:$dst, (trunc GR32:$src))]>,
982 Requires<[In64BitMode]>;
983 def TRUNC_16to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR16:$src),
984 "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}}",
985 [(set GR8:$dst, (trunc GR16:$src))]>,
986 Requires<[In64BitMode]>;
988 def TRUNC_64to16 : I<0x89, MRMDestReg, (ops GR16:$dst, GR64:$src),
989 "mov{w} {${src:subreg16}, $dst|$dst, ${src:subreg16}}",
990 [(set GR16:$dst, (trunc GR64:$src))]>;
992 def TRUNC_64to32 : I<0x89, MRMDestReg, (ops GR32:$dst, GR64:$src),
993 "mov{l} {${src:subreg32}, $dst|$dst, ${src:subreg32}}",
994 [(set GR32:$dst, (trunc GR64:$src))]>;
997 // TODO: Remove this after proper i32 -> i64 zext support.
998 def PsMOVZX64rr32: I<0x89, MRMDestReg, (ops GR64:$dst, GR32:$src),
999 "mov{l} {$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1000 [(set GR64:$dst, (zext GR32:$src))]>;
1001 def PsMOVZX64rm32: I<0x8B, MRMSrcMem, (ops GR64:$dst, i32mem:$src),
1002 "mov{l} {$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1003 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
1006 // Alias instructions that map movr0 to xor.
1007 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1008 // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove
1009 // when we have a better way to specify isel priority.
1010 let AddedComplexity = 1 in
1011 def MOV64r0 : RI<0x31, MRMInitReg, (ops GR64:$dst),
1012 "xor{q} $dst, $dst",
1013 [(set GR64:$dst, 0)]>;
1015 // Materialize i64 constant where top 32-bits are zero.
1016 let AddedComplexity = 1 in
1017 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (ops GR64:$dst, i64i32imm:$src),
1018 "mov{l} {$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1019 [(set GR64:$dst, i64immZExt32:$src)]>;
1021 //===----------------------------------------------------------------------===//
1022 // Non-Instruction Patterns
1023 //===----------------------------------------------------------------------===//
1025 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
1026 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1027 (MOV64ri tconstpool :$dst)>, Requires<[NotSmallCode]>;
1028 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1029 (MOV64ri tjumptable :$dst)>, Requires<[NotSmallCode]>;
1030 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1031 (MOV64ri tglobaladdr :$dst)>, Requires<[NotSmallCode]>;
1032 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1033 (MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>;
1035 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1036 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1037 Requires<[SmallCode, IsStatic]>;
1038 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1039 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1040 Requires<[SmallCode, IsStatic]>;
1041 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1042 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1043 Requires<[SmallCode, IsStatic]>;
1044 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1045 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1046 Requires<[SmallCode, IsStatic]>;
1049 // Direct PC relative function call for small code model. 32-bit displacement
1050 // sign extended to 64-bit.
1051 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1052 (CALL64pcrel32 tglobaladdr:$dst)>;
1053 def : Pat<(X86call (i64 texternalsym:$dst)),
1054 (CALL64pcrel32 texternalsym:$dst)>;
1056 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1057 (CALL64pcrel32 tglobaladdr:$dst)>;
1058 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1059 (CALL64pcrel32 texternalsym:$dst)>;
1061 def : Pat<(X86tailcall GR64:$dst),
1062 (CALL64r GR64:$dst)>;
1064 // {s|z}extload bool -> {s|z}extload byte
1065 def : Pat<(sextloadi64i1 addr:$src), (MOVSX64rm8 addr:$src)>;
1066 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1069 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1070 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1071 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1072 def : Pat<(extloadi64i32 addr:$src), (PsMOVZX64rm32 addr:$src)>;
1075 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1076 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16:$src)>;
1077 def : Pat<(i64 (anyext GR32:$src)), (PsMOVZX64rr32 GR32:$src)>;
1078 def : Pat<(i64 (anyext (loadi8 addr:$src))), (MOVZX64rm8 addr:$src)>;
1079 def : Pat<(i64 (anyext (loadi16 addr:$src))), (MOVZX64rm16 addr:$src)>;
1080 def : Pat<(i64 (anyext (loadi32 addr:$src))), (PsMOVZX64rm32 addr:$src)>;
1082 //===----------------------------------------------------------------------===//
1084 //===----------------------------------------------------------------------===//
1086 // (shl x, 1) ==> (add x, x)
1087 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1089 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1090 def : Pat<(or (srl GR64:$src1, CL:$amt),
1091 (shl GR64:$src2, (sub 64, CL:$amt))),
1092 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1094 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1095 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1096 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1098 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1099 def : Pat<(or (shl GR64:$src1, CL:$amt),
1100 (srl GR64:$src2, (sub 64, CL:$amt))),
1101 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1103 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1104 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1105 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1107 //===----------------------------------------------------------------------===//
1108 // X86-64 SSE Instructions
1109 //===----------------------------------------------------------------------===//
1111 // Move instructions...
1113 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR64:$src),
1114 "mov{d|q} {$src, $dst|$dst, $src}",
1116 (v2i64 (scalar_to_vector GR64:$src)))]>;
1117 def MOV64toPQIrm : RPDI<0x6E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1118 "mov{d|q} {$src, $dst|$dst, $src}",
1120 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>;
1122 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (ops GR64:$dst, VR128:$src),
1123 "mov{d|q} {$src, $dst|$dst, $src}",
1124 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
1126 def MOVPQIto64mr : RPDI<0x7E, MRMDestMem, (ops i64mem:$dst, VR128:$src),
1127 "mov{d|q} {$src, $dst|$dst, $src}",
1128 [(store (i64 (vector_extract (v2i64 VR128:$src),
1129 (iPTR 0))), addr:$dst)]>;
1131 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (ops FR64:$dst, GR64:$src),
1132 "mov{d|q} {$src, $dst|$dst, $src}",
1133 [(set FR64:$dst, (bitconvert GR64:$src))]>;
1134 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (ops FR64:$dst, i64mem:$src),
1135 "mov{d|q} {$src, $dst|$dst, $src}",
1136 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
1138 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (ops GR64:$dst, FR64:$src),
1139 "mov{d|q} {$src, $dst|$dst, $src}",
1140 [(set GR64:$dst, (bitconvert FR64:$src))]>;
1141 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (ops i64mem:$dst, FR64:$src),
1142 "mov{d|q} {$src, $dst|$dst, $src}",
1143 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;