1 //===- X86InstrSystem.td - System Instructions -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instructions that are generally used in
11 // privileged modes. These are not typically used by the compiler, but are
12 // supported for the assembler and disassembler.
14 //===----------------------------------------------------------------------===//
16 let Defs = [RAX, RDX] in
17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
20 let Defs = [RAX, RCX, RDX] in
21 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
23 // CPU flow control instructions
25 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
26 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
29 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
30 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
32 // Interrupt and SysCall Instructions.
33 let Uses = [EFLAGS] in
34 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
35 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
36 [(int_x86_int (i8 3))]>;
37 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
38 [(int_x86_int imm:$trap)]>;
40 def SYSCALL : I<0x05, RawFrm,
41 (outs), (ins), "syscall", []>, TB;
42 def SYSRETL : I<0x07, RawFrm,
43 (outs), (ins), "sysretl", []>, TB;
44 def SYSRETQ : RI<0x07, RawFrm,
45 (outs), (ins), "sysretq", []>, TB, Requires<[In64BitMode]>;
47 def SYSENTER : I<0x34, RawFrm,
48 (outs), (ins), "sysenter", []>, TB;
49 def SYSEXIT : I<0x35, RawFrm,
50 (outs), (ins), "sysexit", []>, TB, Requires<[In32BitMode]>;
52 def SYSEXIT64 : RI<0x35, RawFrm,
53 (outs), (ins), "sysexit", []>, TB, Requires<[In64BitMode]>;
55 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iretw", []>, OpSize;
56 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>;
57 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", []>,
58 Requires<[In64BitMode]>;
61 //===----------------------------------------------------------------------===//
62 // Input/Output Instructions.
64 let Defs = [AL], Uses = [DX] in
65 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
66 "in{b}\t{%dx, %al|%AL, %DX}", []>;
67 let Defs = [AX], Uses = [DX] in
68 def IN16rr : I<0xED, RawFrm, (outs), (ins),
69 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
70 let Defs = [EAX], Uses = [DX] in
71 def IN32rr : I<0xED, RawFrm, (outs), (ins),
72 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
75 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
76 "in{b}\t{$port, %al|%AL, $port}", []>;
78 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
79 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
81 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
82 "in{l}\t{$port, %eax|%EAX, $port}", []>;
84 let Uses = [DX, AL] in
85 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
86 "out{b}\t{%al, %dx|%DX, %AL}", []>;
87 let Uses = [DX, AX] in
88 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
89 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
90 let Uses = [DX, EAX] in
91 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
92 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
95 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
96 "out{b}\t{%al, $port|$port, %AL}", []>;
98 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
99 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
101 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
102 "out{l}\t{%eax, $port|$port, %EAX}", []>;
104 def IN8 : I<0x6C, RawFrm, (outs), (ins),
106 def IN16 : I<0x6D, RawFrm, (outs), (ins),
107 "ins{w}", []>, OpSize;
108 def IN32 : I<0x6D, RawFrm, (outs), (ins),
111 //===----------------------------------------------------------------------===//
112 // Segment override instruction prefixes
114 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
115 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
116 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
117 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
118 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
119 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
122 //===----------------------------------------------------------------------===//
123 // Segmentation support instructions.
125 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
126 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
127 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
128 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
130 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
131 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
132 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
133 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
134 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
136 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
137 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
138 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
139 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
140 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
141 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
142 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
143 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
145 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
147 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
148 "str{w}\t{$dst}", []>, TB;
149 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
150 "str{w}\t{$dst}", []>, TB;
151 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
152 "ltr{w}\t{$src}", []>, TB;
153 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
154 "ltr{w}\t{$src}", []>, TB;
156 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
157 "push{w}\t%cs", []>, Requires<[In32BitMode]>, OpSize;
158 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
159 "push{l}\t%cs", []>, Requires<[In32BitMode]>;
160 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
161 "push{w}\t%ss", []>, Requires<[In32BitMode]>, OpSize;
162 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
163 "push{l}\t%ss", []>, Requires<[In32BitMode]>;
164 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
165 "push{w}\t%ds", []>, Requires<[In32BitMode]>, OpSize;
166 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
167 "push{l}\t%ds", []>, Requires<[In32BitMode]>;
168 def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
169 "push{w}\t%es", []>, Requires<[In32BitMode]>, OpSize;
170 def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
171 "push{l}\t%es", []>, Requires<[In32BitMode]>;
173 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
174 "push{w}\t%fs", []>, OpSize, TB;
175 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
176 "push{l}\t%fs", []>, TB, Requires<[In32BitMode]>;
177 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
178 "push{w}\t%gs", []>, OpSize, TB;
179 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
180 "push{l}\t%gs", []>, TB, Requires<[In32BitMode]>;
182 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
183 "push{q}\t%fs", []>, TB;
184 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
185 "push{q}\t%gs", []>, TB;
187 // No "pop cs" instruction.
188 def POPSS16 : I<0x17, RawFrm, (outs), (ins),
189 "pop{w}\t%ss", []>, OpSize, Requires<[In32BitMode]>;
190 def POPSS32 : I<0x17, RawFrm, (outs), (ins),
191 "pop{l}\t%ss", []> , Requires<[In32BitMode]>;
192 def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
193 "pop{w}\t%ds", []>, OpSize, Requires<[In32BitMode]>;
194 def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
195 "pop{l}\t%ds", []> , Requires<[In32BitMode]>;
196 def POPES16 : I<0x07, RawFrm, (outs), (ins),
197 "pop{w}\t%es", []>, OpSize, Requires<[In32BitMode]>;
198 def POPES32 : I<0x07, RawFrm, (outs), (ins),
199 "pop{l}\t%es", []> , Requires<[In32BitMode]>;
200 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
201 "pop{w}\t%fs", []>, OpSize, TB;
202 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
203 "pop{l}\t%fs", []>, TB , Requires<[In32BitMode]>;
204 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
205 "pop{w}\t%gs", []>, OpSize, TB;
206 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
207 "pop{l}\t%gs", []>, TB , Requires<[In32BitMode]>;
208 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
209 "pop{q}\t%fs", []>, TB;
210 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
211 "pop{q}\t%gs", []>, TB;
214 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
215 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
216 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
217 "lds{l}\t{$src, $dst|$dst, $src}", []>;
218 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
219 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
220 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
221 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
222 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
223 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
224 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
225 "les{l}\t{$src, $dst|$dst, $src}", []>;
226 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
227 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
228 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
229 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
230 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
231 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
232 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
233 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
234 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
235 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
236 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
237 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
238 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
239 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
242 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
243 "verr\t$seg", []>, TB;
244 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
245 "verr\t$seg", []>, TB;
246 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
247 "verw\t$seg", []>, TB;
248 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
249 "verw\t$seg", []>, TB;
251 //===----------------------------------------------------------------------===//
252 // Descriptor-table support instructions
254 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
255 "sgdt\t$dst", []>, TB;
256 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
257 "sidt\t$dst", []>, TB;
258 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
259 "sldt{w}\t$dst", []>, TB, OpSize;
260 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
261 "sldt{w}\t$dst", []>, TB;
262 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
263 "sldt{l}\t$dst", []>, TB;
264 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
265 "lgdt\t$src", []>, TB;
266 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
267 "lidt\t$src", []>, TB;
268 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
269 "lldt{w}\t$src", []>, TB;
270 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
271 "lldt{w}\t$src", []>, TB;
273 //===----------------------------------------------------------------------===//
274 // Specialized register support
275 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
276 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
277 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
279 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
280 "smsw{w}\t$dst", []>, OpSize, TB;
281 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
282 "smsw{l}\t$dst", []>, TB;
284 // no m form encodable; use SMSW16m
285 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
286 "smsw{q}\t$dst", []>, TB;
288 // For memory operands, there is only a 16-bit form
289 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
290 "smsw{w}\t$dst", []>, TB;
292 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
293 "lmsw{w}\t$src", []>, TB;
294 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
295 "lmsw{w}\t$src", []>, TB;
297 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
299 //===----------------------------------------------------------------------===//
300 // Cache instructions
301 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
302 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;