1 //===- X86InstrShiftRotate.td - Shift and Rotate Instrs ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the shift and rotate instructions.
12 //===----------------------------------------------------------------------===//
14 // FIXME: Someone needs to smear multipattern goodness all over this file.
16 let Defs = [EFLAGS] in {
18 let Constraints = "$src1 = $dst" in {
20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
21 "shl{b}\t{%cl, $dst|$dst, CL}",
22 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
24 "shl{w}\t{%cl, $dst|$dst, CL}",
25 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
27 "shl{l}\t{%cl, $dst|$dst, CL}",
28 [(set GR32:$dst, (shl GR32:$src1, CL))]>;
31 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
32 "shl{b}\t{$src2, $dst|$dst, $src2}",
33 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
35 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
36 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
37 "shl{w}\t{$src2, $dst|$dst, $src2}",
38 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
39 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
40 "shl{l}\t{$src2, $dst|$dst, $src2}",
41 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
43 // NOTE: We don't include patterns for shifts of a register by one, because
44 // 'add reg,reg' is cheaper.
46 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
48 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
49 "shl{w}\t$dst", []>, OpSize;
50 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
52 } // isConvertibleToThreeAddress = 1
53 } // Constraints = "$src = $dst"
57 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
58 "shl{b}\t{%cl, $dst|$dst, CL}",
59 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
60 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
61 "shl{w}\t{%cl, $dst|$dst, CL}",
62 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
63 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
64 "shl{l}\t{%cl, $dst|$dst, CL}",
65 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
67 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
68 "shl{b}\t{$src, $dst|$dst, $src}",
69 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
70 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
71 "shl{w}\t{$src, $dst|$dst, $src}",
72 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
74 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
75 "shl{l}\t{$src, $dst|$dst, $src}",
76 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
79 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
81 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
82 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
84 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
86 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
88 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
90 let Constraints = "$src1 = $dst" in {
92 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
93 "shr{b}\t{%cl, $dst|$dst, CL}",
94 [(set GR8:$dst, (srl GR8:$src1, CL))]>;
95 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
96 "shr{w}\t{%cl, $dst|$dst, CL}",
97 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
98 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
99 "shr{l}\t{%cl, $dst|$dst, CL}",
100 [(set GR32:$dst, (srl GR32:$src1, CL))]>;
103 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
104 "shr{b}\t{$src2, $dst|$dst, $src2}",
105 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
106 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
107 "shr{w}\t{$src2, $dst|$dst, $src2}",
108 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
109 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
110 "shr{l}\t{$src2, $dst|$dst, $src2}",
111 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
114 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
116 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
117 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
119 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
120 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
122 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
123 } // Constraints = "$src = $dst"
127 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
128 "shr{b}\t{%cl, $dst|$dst, CL}",
129 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
130 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
131 "shr{w}\t{%cl, $dst|$dst, CL}",
132 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
134 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
135 "shr{l}\t{%cl, $dst|$dst, CL}",
136 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
138 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
139 "shr{b}\t{$src, $dst|$dst, $src}",
140 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
141 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
142 "shr{w}\t{$src, $dst|$dst, $src}",
143 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
145 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
146 "shr{l}\t{$src, $dst|$dst, $src}",
147 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
150 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
152 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
153 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
155 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
156 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
158 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
160 let Constraints = "$src1 = $dst" in {
162 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
163 "sar{b}\t{%cl, $dst|$dst, CL}",
164 [(set GR8:$dst, (sra GR8:$src1, CL))]>;
165 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
166 "sar{w}\t{%cl, $dst|$dst, CL}",
167 [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize;
168 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
169 "sar{l}\t{%cl, $dst|$dst, CL}",
170 [(set GR32:$dst, (sra GR32:$src1, CL))]>;
173 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
174 "sar{b}\t{$src2, $dst|$dst, $src2}",
175 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
176 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
177 "sar{w}\t{$src2, $dst|$dst, $src2}",
178 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
180 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
181 "sar{l}\t{$src2, $dst|$dst, $src2}",
182 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
185 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
187 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
188 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
190 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
191 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
193 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
194 } // Constraints = "$src = $dst"
198 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
199 "sar{b}\t{%cl, $dst|$dst, CL}",
200 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
201 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
202 "sar{w}\t{%cl, $dst|$dst, CL}",
203 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
204 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
205 "sar{l}\t{%cl, $dst|$dst, CL}",
206 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
208 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
209 "sar{b}\t{$src, $dst|$dst, $src}",
210 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
211 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
212 "sar{w}\t{$src, $dst|$dst, $src}",
213 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
215 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
216 "sar{l}\t{$src, $dst|$dst, $src}",
217 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
220 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
222 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
223 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
225 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
227 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
229 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
231 //===----------------------------------------------------------------------===//
232 // Rotate instructions
233 //===----------------------------------------------------------------------===//
235 let Constraints = "$src1 = $dst" in {
236 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
237 "rcl{b}\t{1, $dst|$dst, 1}", []>;
239 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
240 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
242 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
243 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
245 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
246 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
248 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
249 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
251 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
252 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
254 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
255 "rcl{l}\t{1, $dst|$dst, 1}", []>;
257 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
258 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
260 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
261 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
263 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
264 "rcr{b}\t{1, $dst|$dst, 1}", []>;
266 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
267 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
269 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
270 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
272 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
273 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
275 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
276 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
278 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
279 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
281 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
282 "rcr{l}\t{1, $dst|$dst, 1}", []>;
284 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
285 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
287 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
288 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
289 } // Constraints = "$src = $dst"
291 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
292 "rcl{b}\t{1, $dst|$dst, 1}", []>;
293 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
294 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
295 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
296 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
297 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
298 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
299 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
300 "rcl{l}\t{1, $dst|$dst, 1}", []>;
301 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
302 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
303 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
304 "rcr{b}\t{1, $dst|$dst, 1}", []>;
305 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
306 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
307 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
308 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
309 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
310 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
311 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
312 "rcr{l}\t{1, $dst|$dst, 1}", []>;
313 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
314 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
317 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
318 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
319 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
320 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
321 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
322 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
323 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
324 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
325 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
326 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
327 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
328 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
331 let Constraints = "$src1 = $dst" in {
332 // FIXME: provide shorter instructions when imm8 == 1
334 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
335 "rol{b}\t{%cl, $dst|$dst, CL}",
336 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
337 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
338 "rol{w}\t{%cl, $dst|$dst, CL}",
339 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize;
340 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
341 "rol{l}\t{%cl, $dst|$dst, CL}",
342 [(set GR32:$dst, (rotl GR32:$src1, CL))]>;
345 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
346 "rol{b}\t{$src2, $dst|$dst, $src2}",
347 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
348 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
349 "rol{w}\t{$src2, $dst|$dst, $src2}",
350 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
352 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
353 "rol{l}\t{$src2, $dst|$dst, $src2}",
354 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
357 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
359 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
360 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
362 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
363 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
365 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
366 } // Constraints = "$src = $dst"
369 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
370 "rol{b}\t{%cl, $dst|$dst, CL}",
371 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
372 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
373 "rol{w}\t{%cl, $dst|$dst, CL}",
374 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
375 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
376 "rol{l}\t{%cl, $dst|$dst, CL}",
377 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
379 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
380 "rol{b}\t{$src, $dst|$dst, $src}",
381 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
382 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
383 "rol{w}\t{$src, $dst|$dst, $src}",
384 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
386 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
387 "rol{l}\t{$src, $dst|$dst, $src}",
388 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
391 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
393 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
394 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
396 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
398 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
400 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
402 let Constraints = "$src1 = $dst" in {
404 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
405 "ror{b}\t{%cl, $dst|$dst, CL}",
406 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
407 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
408 "ror{w}\t{%cl, $dst|$dst, CL}",
409 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize;
410 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
411 "ror{l}\t{%cl, $dst|$dst, CL}",
412 [(set GR32:$dst, (rotr GR32:$src1, CL))]>;
415 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
416 "ror{b}\t{$src2, $dst|$dst, $src2}",
417 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
418 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
419 "ror{w}\t{$src2, $dst|$dst, $src2}",
420 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
422 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
423 "ror{l}\t{$src2, $dst|$dst, $src2}",
424 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
427 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
429 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
430 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
432 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
433 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
435 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
436 } // Constraints = "$src = $dst"
439 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
440 "ror{b}\t{%cl, $dst|$dst, CL}",
441 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
442 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
443 "ror{w}\t{%cl, $dst|$dst, CL}",
444 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
445 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
446 "ror{l}\t{%cl, $dst|$dst, CL}",
447 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
449 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
450 "ror{b}\t{$src, $dst|$dst, $src}",
451 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
452 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
453 "ror{w}\t{$src, $dst|$dst, $src}",
454 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
456 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
457 "ror{l}\t{$src, $dst|$dst, $src}",
458 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
461 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
463 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
464 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
466 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
468 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
470 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
473 //===----------------------------------------------------------------------===//
474 // Double shift instructions (generalizations of rotate)
475 //===----------------------------------------------------------------------===//
477 let Constraints = "$src1 = $dst" in {
480 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
481 (ins GR32:$src1, GR32:$src2),
482 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
483 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
484 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
485 (ins GR32:$src1, GR32:$src2),
486 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
487 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
488 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
489 (ins GR16:$src1, GR16:$src2),
490 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
491 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
493 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
494 (ins GR16:$src1, GR16:$src2),
495 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
496 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
500 let isCommutable = 1 in { // These instructions commute to each other.
501 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
503 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
504 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
505 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
508 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
510 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
511 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
512 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
515 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
517 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
518 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
519 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
522 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
524 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
525 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
526 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
530 } // Constraints = "$src = $dst"
533 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
534 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
535 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
537 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
538 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
539 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
542 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
543 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
544 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
545 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
546 (i8 imm:$src3)), addr:$dst)]>,
548 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
549 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
550 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
551 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
552 (i8 imm:$src3)), addr:$dst)]>,
556 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
557 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
558 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
559 addr:$dst)]>, TB, OpSize;
560 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
561 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
562 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
563 addr:$dst)]>, TB, OpSize;
565 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
566 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
567 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
568 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
569 (i8 imm:$src3)), addr:$dst)]>,
571 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
572 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
573 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
574 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
575 (i8 imm:$src3)), addr:$dst)]>,