1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
244 Domain d, OpndItins itins, bit Is2Addr = 1> {
245 let isCommutable = 1 in {
246 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
250 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr, d>,
251 Sched<[itins.Sched]>;
253 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
255 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
257 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm, d>,
258 Sched<[itins.Sched.Folded, ReadAfterLd]>;
261 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
262 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
263 string asm, string SSEVer, string FPSizeStr,
264 Operand memopr, ComplexPattern mem_cpat,
265 Domain d, OpndItins itins, bit Is2Addr = 1> {
266 let isCodeGenOnly = 1 in {
267 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
269 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
271 [(set RC:$dst, (!cast<Intrinsic>(
272 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
273 RC:$src1, RC:$src2))], itins.rr, d>,
274 Sched<[itins.Sched]>;
275 def rm_Int : SI_Int<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
277 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
278 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
279 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
280 SSEVer, "_", OpcodeStr, FPSizeStr))
281 RC:$src1, mem_cpat:$src2))], itins.rm, d>,
282 Sched<[itins.Sched.Folded, ReadAfterLd]>;
286 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
287 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
288 RegisterClass RC, ValueType vt,
289 X86MemOperand x86memop, PatFrag mem_frag,
290 Domain d, OpndItins itins, bit Is2Addr = 1> {
291 let isCommutable = 1 in
292 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
296 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
297 Sched<[itins.Sched]>;
299 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
301 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
302 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
303 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
305 Sched<[itins.Sched.Folded, ReadAfterLd]>;
308 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
309 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
310 string OpcodeStr, X86MemOperand x86memop,
311 list<dag> pat_rr, list<dag> pat_rm,
313 let isCommutable = 1, hasSideEffects = 0 in
314 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
316 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
318 pat_rr, NoItinerary, d>,
319 Sched<[WriteVecLogic]>;
320 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
324 pat_rm, NoItinerary, d>,
325 Sched<[WriteVecLogicLd, ReadAfterLd]>;
328 //===----------------------------------------------------------------------===//
329 // Non-instruction patterns
330 //===----------------------------------------------------------------------===//
332 // A vector extract of the first f32/f64 position is a subregister copy
333 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
335 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
338 // A 128-bit subvector extract from the first 256-bit vector position
339 // is a subregister copy that needs no instruction.
340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
341 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
343 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
346 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
348 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
351 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
353 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
355 // A 128-bit subvector insert to the first 256-bit vector position
356 // is a subregister copy that needs no instruction.
357 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
372 // Implicitly promote a 32-bit scalar to a vector.
373 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
374 (COPY_TO_REGCLASS FR32:$src, VR128)>;
375 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 // Implicitly promote a 64-bit scalar to a vector.
378 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
379 (COPY_TO_REGCLASS FR64:$src, VR128)>;
380 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
383 // Bitcasts between 128-bit vector types. Return the original type since
384 // no instruction is needed for the conversion
385 let Predicates = [HasSSE2] in {
386 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
387 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
388 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
392 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
397 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
402 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
407 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
412 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
418 // Bitcasts between 256-bit vector types. Return the original type since
419 // no instruction is needed for the conversion
420 let Predicates = [HasAVX] in {
421 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
422 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
423 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
427 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
432 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
437 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
442 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
447 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
453 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
454 // This is expanded by ExpandPostRAPseudos.
455 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
456 isPseudo = 1, SchedRW = [WriteZero] in {
457 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
458 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
459 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
460 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
463 //===----------------------------------------------------------------------===//
464 // AVX & SSE - Zero/One Vectors
465 //===----------------------------------------------------------------------===//
467 // Alias instruction that maps zero vector to pxor / xorp* for sse.
468 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
469 // swizzled by ExecutionDepsFix to pxor.
470 // We set canFoldAsLoad because this can be converted to a constant-pool
471 // load of an all-zeros value if folding it would be beneficial.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
473 isPseudo = 1, SchedRW = [WriteZero] in {
474 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
475 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
478 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
479 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
480 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
482 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
485 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
486 // and doesn't need it because on sandy bridge the register is set to zero
487 // at the rename stage without using any execution unit, so SET0PSY
488 // and SET0PDY can be used for vector int instructions without penalty
489 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
490 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
491 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
492 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
495 let Predicates = [HasAVX] in
496 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
498 let Predicates = [HasAVX2] in {
499 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
500 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
501 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
505 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
506 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
507 let Predicates = [HasAVX1Only] in {
508 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
509 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
510 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
512 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
513 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
514 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
516 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
517 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
518 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
520 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
521 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
522 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
525 // We set canFoldAsLoad because this can be converted to a constant-pool
526 // load of an all-ones value if folding it would be beneficial.
527 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
528 isPseudo = 1, SchedRW = [WriteZero] in {
529 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
530 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
531 let Predicates = [HasAVX2] in
532 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
533 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
537 //===----------------------------------------------------------------------===//
538 // SSE 1 & 2 - Move FP Scalar Instructions
540 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
541 // register copies because it's a partial register update; Register-to-register
542 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
543 // that the insert be implementable in terms of a copy, and just mentioned, we
544 // don't use movss/movsd for copies.
545 //===----------------------------------------------------------------------===//
547 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
548 X86MemOperand x86memop, string base_opc,
549 string asm_opr, Domain d = GenericDomain> {
550 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
551 (ins VR128:$src1, RC:$src2),
552 !strconcat(base_opc, asm_opr),
553 [(set VR128:$dst, (vt (OpNode VR128:$src1,
554 (scalar_to_vector RC:$src2))))],
555 IIC_SSE_MOV_S_RR, d>, Sched<[WriteFShuffle]>;
557 // For the disassembler
558 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
559 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
560 (ins VR128:$src1, RC:$src2),
561 !strconcat(base_opc, asm_opr),
562 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
565 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
566 X86MemOperand x86memop, string OpcodeStr,
567 Domain d = GenericDomain> {
569 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
570 "\t{$src2, $src1, $dst|$dst, $src1, $src2}", d>,
573 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
575 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
576 VEX, VEX_LIG, Sched<[WriteStore]>;
578 let Constraints = "$src1 = $dst" in {
579 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
580 "\t{$src2, $dst|$dst, $src2}", d>;
583 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
585 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
589 // Loading from memory automatically zeroing upper bits.
590 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
591 PatFrag mem_pat, string OpcodeStr,
592 Domain d = GenericDomain> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM, d>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM, d>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
604 SSEPackedSingle>, XS;
605 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd",
606 SSEPackedDouble>, XD;
608 let canFoldAsLoad = 1, isReMaterializable = 1 in {
609 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss",
610 SSEPackedSingle>, XS;
612 let AddedComplexity = 20 in
613 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd",
614 SSEPackedDouble>, XD;
618 let Predicates = [UseAVX] in {
619 let AddedComplexity = 20 in {
620 // MOVSSrm zeros the high parts of the register; represent this
621 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
622 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
624 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
625 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
626 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
627 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
629 // MOVSDrm zeros the high parts of the register; represent this
630 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
631 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
633 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
637 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
638 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
639 def : Pat<(v2f64 (X86vzload addr:$src)),
640 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
642 // Represent the same patterns above but in the form they appear for
644 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
645 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
646 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
647 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
648 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
649 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
652 // Extract and store.
653 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
655 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
656 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
658 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
660 // Shuffle with VMOVSS
661 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
662 (VMOVSSrr (v4i32 VR128:$src1),
663 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
664 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
665 (VMOVSSrr (v4f32 VR128:$src1),
666 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
669 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
670 (SUBREG_TO_REG (i32 0),
671 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
672 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
674 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
675 (SUBREG_TO_REG (i32 0),
676 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
677 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
680 // Shuffle with VMOVSD
681 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
682 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
683 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
691 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
694 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
696 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
697 (SUBREG_TO_REG (i32 0),
698 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
699 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
702 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
703 // is during lowering, where it's not possible to recognize the fold cause
704 // it has two uses through a bitcast. One use disappears at isel time and the
705 // fold opportunity reappears.
706 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
707 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
708 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
716 let Predicates = [UseSSE1] in {
717 let Predicates = [NoSSE41], AddedComplexity = 15 in {
718 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
719 // MOVSS to the lower bits.
720 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
721 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
722 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
723 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
728 let AddedComplexity = 20 in {
729 // MOVSSrm already zeros the high parts of the register.
730 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
731 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
732 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
738 // Extract and store.
739 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
741 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
743 // Shuffle with MOVSS
744 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
745 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
746 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
750 let Predicates = [UseSSE2] in {
751 let Predicates = [NoSSE41], AddedComplexity = 15 in {
752 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
753 // MOVSD to the lower bits.
754 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
755 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
758 let AddedComplexity = 20 in {
759 // MOVSDrm already zeros the high parts of the register.
760 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
761 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
762 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzload addr:$src)),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
772 // Extract and store.
773 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
775 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
777 // Shuffle with MOVSD
778 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
779 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
780 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
788 // is during lowering, where it's not possible to recognize the fold because
789 // it has two uses through a bitcast. One use disappears at isel time and the
790 // fold opportunity reappears.
791 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
793 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
801 //===----------------------------------------------------------------------===//
802 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
803 //===----------------------------------------------------------------------===//
805 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
806 X86MemOperand x86memop, PatFrag ld_frag,
807 string asm, Domain d,
809 bit IsReMaterializable = 1> {
810 let hasSideEffects = 0 in
811 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
812 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
813 Sched<[WriteFShuffle]>;
814 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
815 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
816 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
817 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
821 let Predicates = [HasAVX, NoVLX] in {
822 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
823 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
825 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
826 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
828 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
829 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
831 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
832 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
836 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
838 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
839 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
841 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
842 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
844 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
845 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
849 let Predicates = [UseSSE1] in {
850 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
851 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
853 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
854 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
857 let Predicates = [UseSSE2] in {
858 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
859 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
861 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
862 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
867 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
868 "movaps\t{$src, $dst|$dst, $src}",
869 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
870 IIC_SSE_MOVA_P_MR>, VEX;
871 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
872 "movapd\t{$src, $dst|$dst, $src}",
873 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
874 IIC_SSE_MOVA_P_MR>, VEX;
875 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
876 "movups\t{$src, $dst|$dst, $src}",
877 [(store (v4f32 VR128:$src), addr:$dst)],
878 IIC_SSE_MOVU_P_MR>, VEX;
879 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
880 "movupd\t{$src, $dst|$dst, $src}",
881 [(store (v2f64 VR128:$src), addr:$dst)],
882 IIC_SSE_MOVU_P_MR>, VEX;
883 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
884 "movaps\t{$src, $dst|$dst, $src}",
885 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
886 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
887 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
888 "movapd\t{$src, $dst|$dst, $src}",
889 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
890 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
891 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
892 "movups\t{$src, $dst|$dst, $src}",
893 [(store (v8f32 VR256:$src), addr:$dst)],
894 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
895 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
896 "movupd\t{$src, $dst|$dst, $src}",
897 [(store (v4f64 VR256:$src), addr:$dst)],
898 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
902 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
903 SchedRW = [WriteFShuffle] in {
904 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
906 "movaps\t{$src, $dst|$dst, $src}", [],
907 IIC_SSE_MOVA_P_RR>, VEX;
908 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
910 "movapd\t{$src, $dst|$dst, $src}", [],
911 IIC_SSE_MOVA_P_RR>, VEX;
912 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
914 "movups\t{$src, $dst|$dst, $src}", [],
915 IIC_SSE_MOVU_P_RR>, VEX;
916 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
918 "movupd\t{$src, $dst|$dst, $src}", [],
919 IIC_SSE_MOVU_P_RR>, VEX;
920 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
922 "movaps\t{$src, $dst|$dst, $src}", [],
923 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
924 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
926 "movapd\t{$src, $dst|$dst, $src}", [],
927 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
928 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
930 "movups\t{$src, $dst|$dst, $src}", [],
931 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
932 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
934 "movupd\t{$src, $dst|$dst, $src}", [],
935 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
938 let Predicates = [HasAVX] in {
939 def : Pat<(v8i32 (X86vzmovl
940 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v4i64 (X86vzmovl
943 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v8f32 (X86vzmovl
946 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
948 def : Pat<(v4f64 (X86vzmovl
949 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
950 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
954 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
955 (VMOVUPSYmr addr:$dst, VR256:$src)>;
956 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
957 (VMOVUPDYmr addr:$dst, VR256:$src)>;
959 let SchedRW = [WriteStore] in {
960 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movaps\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
964 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movapd\t{$src, $dst|$dst, $src}",
966 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
968 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movups\t{$src, $dst|$dst, $src}",
970 [(store (v4f32 VR128:$src), addr:$dst)],
972 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
973 "movupd\t{$src, $dst|$dst, $src}",
974 [(store (v2f64 VR128:$src), addr:$dst)],
979 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
980 SchedRW = [WriteFShuffle] in {
981 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movaps\t{$src, $dst|$dst, $src}", [],
984 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movapd\t{$src, $dst|$dst, $src}", [],
987 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
988 "movups\t{$src, $dst|$dst, $src}", [],
990 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
991 "movupd\t{$src, $dst|$dst, $src}", [],
995 let Predicates = [HasAVX] in {
996 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
997 (VMOVUPSmr addr:$dst, VR128:$src)>;
998 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
999 (VMOVUPDmr addr:$dst, VR128:$src)>;
1002 let Predicates = [UseSSE1] in
1003 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1004 (MOVUPSmr addr:$dst, VR128:$src)>;
1005 let Predicates = [UseSSE2] in
1006 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1007 (MOVUPDmr addr:$dst, VR128:$src)>;
1009 // Use vmovaps/vmovups for AVX integer load/store.
1010 let Predicates = [HasAVX, NoVLX] in {
1011 // 128-bit load/store
1012 def : Pat<(alignedloadv2i64 addr:$src),
1013 (VMOVAPSrm addr:$src)>;
1014 def : Pat<(loadv2i64 addr:$src),
1015 (VMOVUPSrm addr:$src)>;
1017 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1020 (VMOVAPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1022 (VMOVAPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1024 (VMOVAPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1028 (VMOVUPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1030 (VMOVUPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1032 (VMOVUPSmr addr:$dst, VR128:$src)>;
1034 // 256-bit load/store
1035 def : Pat<(alignedloadv4i64 addr:$src),
1036 (VMOVAPSYrm addr:$src)>;
1037 def : Pat<(loadv4i64 addr:$src),
1038 (VMOVUPSYrm addr:$src)>;
1039 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1042 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1044 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1046 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1050 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1052 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1054 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1056 // Special patterns for storing subvector extracts of lower 128-bits
1057 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1058 def : Pat<(alignedstore (v2f64 (extract_subvector
1059 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1061 def : Pat<(alignedstore (v4f32 (extract_subvector
1062 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1063 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 def : Pat<(alignedstore (v2i64 (extract_subvector
1065 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1066 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1067 def : Pat<(alignedstore (v4i32 (extract_subvector
1068 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1069 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1070 def : Pat<(alignedstore (v8i16 (extract_subvector
1071 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1072 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1073 def : Pat<(alignedstore (v16i8 (extract_subvector
1074 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1075 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1077 def : Pat<(store (v2f64 (extract_subvector
1078 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1079 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1080 def : Pat<(store (v4f32 (extract_subvector
1081 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1082 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1083 def : Pat<(store (v2i64 (extract_subvector
1084 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1085 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1086 def : Pat<(store (v4i32 (extract_subvector
1087 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1088 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1089 def : Pat<(store (v8i16 (extract_subvector
1090 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1091 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1092 def : Pat<(store (v16i8 (extract_subvector
1093 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1094 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1097 // Use movaps / movups for SSE integer load / store (one byte shorter).
1098 // The instructions selected below are then converted to MOVDQA/MOVDQU
1099 // during the SSE domain pass.
1100 let Predicates = [UseSSE1] in {
1101 def : Pat<(alignedloadv2i64 addr:$src),
1102 (MOVAPSrm addr:$src)>;
1103 def : Pat<(loadv2i64 addr:$src),
1104 (MOVUPSrm addr:$src)>;
1106 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1107 (MOVAPSmr addr:$dst, VR128:$src)>;
1108 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1109 (MOVAPSmr addr:$dst, VR128:$src)>;
1110 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1111 (MOVAPSmr addr:$dst, VR128:$src)>;
1112 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1113 (MOVAPSmr addr:$dst, VR128:$src)>;
1114 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1115 (MOVUPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1117 (MOVUPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1119 (MOVUPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1121 (MOVUPSmr addr:$dst, VR128:$src)>;
1124 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1125 // bits are disregarded. FIXME: Set encoding to pseudo!
1126 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1127 let isCodeGenOnly = 1 in {
1128 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1129 "movaps\t{$src, $dst|$dst, $src}",
1130 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1131 IIC_SSE_MOVA_P_RM>, VEX;
1132 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1133 "movapd\t{$src, $dst|$dst, $src}",
1134 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1135 IIC_SSE_MOVA_P_RM>, VEX;
1136 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1137 "movaps\t{$src, $dst|$dst, $src}",
1138 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1140 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1141 "movapd\t{$src, $dst|$dst, $src}",
1142 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1147 //===----------------------------------------------------------------------===//
1148 // SSE 1 & 2 - Move Low packed FP Instructions
1149 //===----------------------------------------------------------------------===//
1151 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1152 string base_opc, string asm_opr,
1153 InstrItinClass itin> {
1154 def PSrm : PI<opc, MRMSrcMem,
1155 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1156 !strconcat(base_opc, "s", asm_opr),
1158 (psnode VR128:$src1,
1159 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1160 itin, SSEPackedSingle>, PS,
1161 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1163 def PDrm : PI<opc, MRMSrcMem,
1164 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1165 !strconcat(base_opc, "d", asm_opr),
1166 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1167 (scalar_to_vector (loadf64 addr:$src2)))))],
1168 itin, SSEPackedDouble>, PD,
1169 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1173 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1174 string base_opc, InstrItinClass itin> {
1175 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1176 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1179 let Constraints = "$src1 = $dst" in
1180 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1181 "\t{$src2, $dst|$dst, $src2}",
1185 let AddedComplexity = 20 in {
1186 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1190 let SchedRW = [WriteStore] in {
1191 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1192 "movlps\t{$src, $dst|$dst, $src}",
1193 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1194 (iPTR 0))), addr:$dst)],
1195 IIC_SSE_MOV_LH>, VEX;
1196 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1197 "movlpd\t{$src, $dst|$dst, $src}",
1198 [(store (f64 (vector_extract (v2f64 VR128:$src),
1199 (iPTR 0))), addr:$dst)],
1200 IIC_SSE_MOV_LH>, VEX;
1201 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1202 "movlps\t{$src, $dst|$dst, $src}",
1203 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1204 (iPTR 0))), addr:$dst)],
1206 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1207 "movlpd\t{$src, $dst|$dst, $src}",
1208 [(store (f64 (vector_extract (v2f64 VR128:$src),
1209 (iPTR 0))), addr:$dst)],
1213 let Predicates = [HasAVX] in {
1214 // Shuffle with VMOVLPS
1215 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1216 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1218 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1220 // Shuffle with VMOVLPD
1221 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1222 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1223 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1224 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1226 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1227 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1232 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1233 def : Pat<(store (v4i32 (X86Movlps
1234 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1235 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1236 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1238 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1239 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1241 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1244 let Predicates = [UseSSE1] in {
1245 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1246 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1247 (iPTR 0))), addr:$src1),
1248 (MOVLPSmr addr:$src1, VR128:$src2)>;
1250 // Shuffle with MOVLPS
1251 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1252 (MOVLPSrm VR128:$src1, addr:$src2)>;
1253 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1254 (MOVLPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(X86Movlps VR128:$src1,
1256 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1257 (MOVLPSrm VR128:$src1, addr:$src2)>;
1260 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1262 (MOVLPSmr addr:$src1, VR128:$src2)>;
1263 def : Pat<(store (v4i32 (X86Movlps
1264 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1266 (MOVLPSmr addr:$src1, VR128:$src2)>;
1269 let Predicates = [UseSSE2] in {
1270 // Shuffle with MOVLPD
1271 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1272 (MOVLPDrm VR128:$src1, addr:$src2)>;
1273 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1274 (MOVLPDrm VR128:$src1, addr:$src2)>;
1275 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1276 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1277 (MOVLPDrm VR128:$src1, addr:$src2)>;
1280 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1282 (MOVLPDmr addr:$src1, VR128:$src2)>;
1283 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1285 (MOVLPDmr addr:$src1, VR128:$src2)>;
1288 //===----------------------------------------------------------------------===//
1289 // SSE 1 & 2 - Move Hi packed FP Instructions
1290 //===----------------------------------------------------------------------===//
1292 let AddedComplexity = 20 in {
1293 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1297 let SchedRW = [WriteStore] in {
1298 // v2f64 extract element 1 is always custom lowered to unpack high to low
1299 // and extract element 0 so the non-store version isn't too horrible.
1300 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1301 "movhps\t{$src, $dst|$dst, $src}",
1302 [(store (f64 (vector_extract
1303 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1304 (bc_v2f64 (v4f32 VR128:$src))),
1305 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1306 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1307 "movhpd\t{$src, $dst|$dst, $src}",
1308 [(store (f64 (vector_extract
1309 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1310 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1311 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1312 "movhps\t{$src, $dst|$dst, $src}",
1313 [(store (f64 (vector_extract
1314 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1315 (bc_v2f64 (v4f32 VR128:$src))),
1316 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1317 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1318 "movhpd\t{$src, $dst|$dst, $src}",
1319 [(store (f64 (vector_extract
1320 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1321 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1324 let Predicates = [HasAVX] in {
1326 def : Pat<(X86Movlhps VR128:$src1,
1327 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1328 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1329 def : Pat<(X86Movlhps VR128:$src1,
1330 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1331 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1335 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1336 // is during lowering, where it's not possible to recognize the load fold
1337 // cause it has two uses through a bitcast. One use disappears at isel time
1338 // and the fold opportunity reappears.
1339 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1340 (scalar_to_vector (loadf64 addr:$src2)))),
1341 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1342 // Also handle an i64 load because that may get selected as a faster way to
1344 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1345 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1346 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1348 def : Pat<(store (f64 (vector_extract
1349 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1350 (iPTR 0))), addr:$dst),
1351 (VMOVHPDmr addr:$dst, VR128:$src)>;
1354 let Predicates = [UseSSE1] in {
1356 def : Pat<(X86Movlhps VR128:$src1,
1357 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1358 (MOVHPSrm VR128:$src1, addr:$src2)>;
1359 def : Pat<(X86Movlhps VR128:$src1,
1360 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1361 (MOVHPSrm VR128:$src1, addr:$src2)>;
1364 let Predicates = [UseSSE2] in {
1367 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1368 // is during lowering, where it's not possible to recognize the load fold
1369 // cause it has two uses through a bitcast. One use disappears at isel time
1370 // and the fold opportunity reappears.
1371 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1372 (scalar_to_vector (loadf64 addr:$src2)))),
1373 (MOVHPDrm VR128:$src1, addr:$src2)>;
1374 // Also handle an i64 load because that may get selected as a faster way to
1376 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1377 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1378 (MOVHPDrm VR128:$src1, addr:$src2)>;
1380 def : Pat<(store (f64 (vector_extract
1381 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1382 (iPTR 0))), addr:$dst),
1383 (MOVHPDmr addr:$dst, VR128:$src)>;
1386 //===----------------------------------------------------------------------===//
1387 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1388 //===----------------------------------------------------------------------===//
1390 let AddedComplexity = 20, Predicates = [UseAVX] in {
1391 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1392 (ins VR128:$src1, VR128:$src2),
1393 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1395 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1397 VEX_4V, Sched<[WriteFShuffle]>;
1398 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1399 (ins VR128:$src1, VR128:$src2),
1400 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1402 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1404 VEX_4V, Sched<[WriteFShuffle]>;
1406 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1407 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1408 (ins VR128:$src1, VR128:$src2),
1409 "movlhps\t{$src2, $dst|$dst, $src2}",
1411 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1412 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1413 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1414 (ins VR128:$src1, VR128:$src2),
1415 "movhlps\t{$src2, $dst|$dst, $src2}",
1417 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1418 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1421 let Predicates = [UseAVX] in {
1423 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1424 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1425 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1426 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1429 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1430 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1433 let Predicates = [UseSSE1] in {
1435 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1436 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1437 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1438 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1441 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1442 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1445 //===----------------------------------------------------------------------===//
1446 // SSE 1 & 2 - Conversion Instructions
1447 //===----------------------------------------------------------------------===//
1449 def SSE_CVT_PD : OpndItins<
1450 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1453 let Sched = WriteCvtI2F in
1454 def SSE_CVT_PS : OpndItins<
1455 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1458 let Sched = WriteCvtI2F in
1459 def SSE_CVT_Scalar : OpndItins<
1460 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1463 let Sched = WriteCvtF2I in
1464 def SSE_CVT_SS2SI_32 : OpndItins<
1465 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1468 let Sched = WriteCvtF2I in
1469 def SSE_CVT_SS2SI_64 : OpndItins<
1470 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1473 let Sched = WriteCvtF2I in
1474 def SSE_CVT_SD2SI : OpndItins<
1475 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1478 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1479 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1480 string asm, OpndItins itins> {
1481 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1482 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1483 itins.rr>, Sched<[itins.Sched]>;
1484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1485 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1486 itins.rm>, Sched<[itins.Sched.Folded]>;
1489 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1490 X86MemOperand x86memop, string asm, Domain d,
1492 let hasSideEffects = 0 in {
1493 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1494 [], itins.rr, d>, Sched<[itins.Sched]>;
1496 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1497 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1501 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1502 X86MemOperand x86memop, string asm> {
1503 let hasSideEffects = 0, Predicates = [UseAVX] in {
1504 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1505 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1506 Sched<[WriteCvtI2F]>;
1508 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1509 (ins DstRC:$src1, x86memop:$src),
1510 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1511 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1512 } // hasSideEffects = 0
1515 let Predicates = [UseAVX] in {
1516 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1517 "cvttss2si\t{$src, $dst|$dst, $src}",
1520 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1521 "cvttss2si\t{$src, $dst|$dst, $src}",
1523 XS, VEX, VEX_W, VEX_LIG;
1524 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1525 "cvttsd2si\t{$src, $dst|$dst, $src}",
1528 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1529 "cvttsd2si\t{$src, $dst|$dst, $src}",
1531 XD, VEX, VEX_W, VEX_LIG;
1533 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1534 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1535 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1536 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1537 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1538 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1539 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1540 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1541 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1542 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1543 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1545 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1550 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1551 // register, but the same isn't true when only using memory operands,
1552 // provide other assembly "l" and "q" forms to address this explicitly
1553 // where appropriate to do so.
1554 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1555 XS, VEX_4V, VEX_LIG;
1556 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1557 XS, VEX_4V, VEX_W, VEX_LIG;
1558 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1559 XD, VEX_4V, VEX_LIG;
1560 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1561 XD, VEX_4V, VEX_W, VEX_LIG;
1563 let Predicates = [UseAVX] in {
1564 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1565 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1566 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1567 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1569 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1570 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1571 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1572 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1573 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1574 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1575 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1576 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1578 def : Pat<(f32 (sint_to_fp GR32:$src)),
1579 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1580 def : Pat<(f32 (sint_to_fp GR64:$src)),
1581 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1582 def : Pat<(f64 (sint_to_fp GR32:$src)),
1583 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1584 def : Pat<(f64 (sint_to_fp GR64:$src)),
1585 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1588 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1589 "cvttss2si\t{$src, $dst|$dst, $src}",
1590 SSE_CVT_SS2SI_32>, XS;
1591 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1592 "cvttss2si\t{$src, $dst|$dst, $src}",
1593 SSE_CVT_SS2SI_64>, XS, REX_W;
1594 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1595 "cvttsd2si\t{$src, $dst|$dst, $src}",
1597 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1598 "cvttsd2si\t{$src, $dst|$dst, $src}",
1599 SSE_CVT_SD2SI>, XD, REX_W;
1600 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1601 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1602 SSE_CVT_Scalar>, XS;
1603 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1604 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1605 SSE_CVT_Scalar>, XS, REX_W;
1606 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1607 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1608 SSE_CVT_Scalar>, XD;
1609 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1610 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1611 SSE_CVT_Scalar>, XD, REX_W;
1613 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1614 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1615 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1616 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1617 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1618 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1619 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1620 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1621 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1622 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1623 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1625 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1626 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1627 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1630 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1631 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1632 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1633 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1635 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1636 // and/or XMM operand(s).
1638 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1639 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1640 string asm, OpndItins itins> {
1641 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1642 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1643 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1644 Sched<[itins.Sched]>;
1645 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1646 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1647 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1648 Sched<[itins.Sched.Folded]>;
1651 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1652 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1653 PatFrag ld_frag, string asm, OpndItins itins,
1655 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1657 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1658 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1659 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1660 itins.rr>, Sched<[itins.Sched]>;
1661 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1662 (ins DstRC:$src1, x86memop:$src2),
1664 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1665 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1666 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1667 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1670 let Predicates = [UseAVX] in {
1671 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1672 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1673 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1674 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1675 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1676 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1678 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1679 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1680 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1681 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1684 let isCodeGenOnly = 1 in {
1685 let Predicates = [UseAVX] in {
1686 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1687 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1688 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1689 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1690 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1691 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1693 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1694 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1695 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1696 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1697 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1698 SSE_CVT_Scalar, 0>, XD,
1701 let Constraints = "$src1 = $dst" in {
1702 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1703 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1704 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1705 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1706 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1707 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1708 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1709 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1710 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1711 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1712 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1713 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1715 } // isCodeGenOnly = 1
1719 // Aliases for intrinsics
1720 let isCodeGenOnly = 1 in {
1721 let Predicates = [UseAVX] in {
1722 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1723 ssmem, sse_load_f32, "cvttss2si",
1724 SSE_CVT_SS2SI_32>, XS, VEX;
1725 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1726 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1727 "cvttss2si", SSE_CVT_SS2SI_64>,
1729 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1730 sdmem, sse_load_f64, "cvttsd2si",
1731 SSE_CVT_SD2SI>, XD, VEX;
1732 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1733 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1734 "cvttsd2si", SSE_CVT_SD2SI>,
1737 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1738 ssmem, sse_load_f32, "cvttss2si",
1739 SSE_CVT_SS2SI_32>, XS;
1740 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1741 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1742 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1743 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1744 sdmem, sse_load_f64, "cvttsd2si",
1746 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1747 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1748 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1749 } // isCodeGenOnly = 1
1751 let Predicates = [UseAVX] in {
1752 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1753 ssmem, sse_load_f32, "cvtss2si",
1754 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1755 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1756 ssmem, sse_load_f32, "cvtss2si",
1757 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1759 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1760 ssmem, sse_load_f32, "cvtss2si",
1761 SSE_CVT_SS2SI_32>, XS;
1762 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1763 ssmem, sse_load_f32, "cvtss2si",
1764 SSE_CVT_SS2SI_64>, XS, REX_W;
1766 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1767 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1768 SSEPackedSingle, SSE_CVT_PS>,
1769 PS, VEX, Requires<[HasAVX]>;
1770 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1771 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1772 SSEPackedSingle, SSE_CVT_PS>,
1773 PS, VEX, VEX_L, Requires<[HasAVX]>;
1775 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1776 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1777 SSEPackedSingle, SSE_CVT_PS>,
1778 PS, Requires<[UseSSE2]>;
1780 let Predicates = [UseAVX] in {
1781 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1782 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1783 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1784 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1785 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1786 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1787 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1788 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1789 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1790 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1791 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1793 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1794 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1799 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1800 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1801 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1802 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1803 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1804 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1805 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1806 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1807 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1808 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1809 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1811 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1812 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1813 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1818 // Convert scalar double to scalar single
1819 let hasSideEffects = 0, Predicates = [UseAVX] in {
1820 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1821 (ins FR64:$src1, FR64:$src2),
1822 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1823 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1824 Sched<[WriteCvtF2F]>;
1826 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1827 (ins FR64:$src1, f64mem:$src2),
1828 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1829 [], IIC_SSE_CVT_Scalar_RM>,
1830 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1831 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1834 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1837 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1838 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1839 [(set FR32:$dst, (fround FR64:$src))],
1840 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1841 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1842 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1843 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1844 IIC_SSE_CVT_Scalar_RM>,
1846 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1848 let isCodeGenOnly = 1 in {
1849 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1850 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1851 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1853 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1854 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,
1855 Sched<[WriteCvtF2F]>;
1856 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1857 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1858 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1859 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1860 VR128:$src1, sse_load_f64:$src2))],
1861 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>,
1862 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1864 let Constraints = "$src1 = $dst" in {
1865 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1866 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1867 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1869 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1870 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1871 Sched<[WriteCvtF2F]>;
1872 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1873 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1874 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1875 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1876 VR128:$src1, sse_load_f64:$src2))],
1877 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1878 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1880 } // isCodeGenOnly = 1
1882 // Convert scalar single to scalar double
1883 // SSE2 instructions with XS prefix
1884 let hasSideEffects = 0, Predicates = [UseAVX] in {
1885 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1886 (ins FR32:$src1, FR32:$src2),
1887 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1888 [], IIC_SSE_CVT_Scalar_RR>,
1889 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1890 Sched<[WriteCvtF2F]>;
1892 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1893 (ins FR32:$src1, f32mem:$src2),
1894 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1895 [], IIC_SSE_CVT_Scalar_RM>,
1896 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1897 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1900 def : Pat<(f64 (fextend FR32:$src)),
1901 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1902 def : Pat<(fextend (loadf32 addr:$src)),
1903 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1905 def : Pat<(extloadf32 addr:$src),
1906 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1907 Requires<[UseAVX, OptForSize]>;
1908 def : Pat<(extloadf32 addr:$src),
1909 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1910 Requires<[UseAVX, OptForSpeed]>;
1912 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1913 "cvtss2sd\t{$src, $dst|$dst, $src}",
1914 [(set FR64:$dst, (fextend FR32:$src))],
1915 IIC_SSE_CVT_Scalar_RR>, XS,
1916 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1917 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1918 "cvtss2sd\t{$src, $dst|$dst, $src}",
1919 [(set FR64:$dst, (extloadf32 addr:$src))],
1920 IIC_SSE_CVT_Scalar_RM>, XS,
1921 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1923 // extload f32 -> f64. This matches load+fextend because we have a hack in
1924 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1926 // Since these loads aren't folded into the fextend, we have to match it
1928 def : Pat<(fextend (loadf32 addr:$src)),
1929 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1930 def : Pat<(extloadf32 addr:$src),
1931 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1933 let isCodeGenOnly = 1 in {
1934 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1935 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1936 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1938 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1939 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>,
1940 Sched<[WriteCvtF2F]>;
1941 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1942 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1943 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1945 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1946 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>,
1947 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1948 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1949 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1950 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1951 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1953 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1954 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1955 Sched<[WriteCvtF2F]>;
1956 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1957 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1958 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1960 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1961 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1962 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1964 } // isCodeGenOnly = 1
1966 // Convert packed single/double fp to doubleword
1967 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1968 "cvtps2dq\t{$src, $dst|$dst, $src}",
1969 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1970 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1971 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1972 "cvtps2dq\t{$src, $dst|$dst, $src}",
1974 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1975 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1976 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1977 "cvtps2dq\t{$src, $dst|$dst, $src}",
1979 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1980 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1981 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1982 "cvtps2dq\t{$src, $dst|$dst, $src}",
1984 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1985 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1986 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 "cvtps2dq\t{$src, $dst|$dst, $src}",
1988 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1989 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1990 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1991 "cvtps2dq\t{$src, $dst|$dst, $src}",
1993 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1994 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1997 // Convert Packed Double FP to Packed DW Integers
1998 let Predicates = [HasAVX] in {
1999 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2000 // register, but the same isn't true when using memory operands instead.
2001 // Provide other assembly rr and rm forms to address this explicitly.
2002 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2003 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2004 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2005 VEX, Sched<[WriteCvtF2I]>;
2008 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2009 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2010 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2011 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2013 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2014 Sched<[WriteCvtF2ILd]>;
2017 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2018 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2020 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2021 Sched<[WriteCvtF2I]>;
2022 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2023 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2025 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2026 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2027 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2028 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2031 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2032 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2034 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2035 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2036 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2037 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2038 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2039 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2041 // Convert with truncation packed single/double fp to doubleword
2042 // SSE2 packed instructions with XS prefix
2043 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "cvttps2dq\t{$src, $dst|$dst, $src}",
2046 (int_x86_sse2_cvttps2dq VR128:$src))],
2047 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2048 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2049 "cvttps2dq\t{$src, $dst|$dst, $src}",
2050 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2051 (loadv4f32 addr:$src)))],
2052 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2053 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2054 "cvttps2dq\t{$src, $dst|$dst, $src}",
2056 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2057 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2058 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2059 "cvttps2dq\t{$src, $dst|$dst, $src}",
2060 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2061 (loadv8f32 addr:$src)))],
2062 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2063 Sched<[WriteCvtF2ILd]>;
2065 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2066 "cvttps2dq\t{$src, $dst|$dst, $src}",
2067 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2068 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2069 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2070 "cvttps2dq\t{$src, $dst|$dst, $src}",
2072 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2073 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2075 let Predicates = [HasAVX] in {
2076 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2077 (VCVTDQ2PSrr VR128:$src)>;
2078 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2079 (VCVTDQ2PSrm addr:$src)>;
2081 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2082 (VCVTDQ2PSrr VR128:$src)>;
2083 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2084 (VCVTDQ2PSrm addr:$src)>;
2086 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2087 (VCVTTPS2DQrr VR128:$src)>;
2088 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2089 (VCVTTPS2DQrm addr:$src)>;
2091 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2092 (VCVTDQ2PSYrr VR256:$src)>;
2093 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2094 (VCVTDQ2PSYrm addr:$src)>;
2096 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2097 (VCVTTPS2DQYrr VR256:$src)>;
2098 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2099 (VCVTTPS2DQYrm addr:$src)>;
2102 let Predicates = [UseSSE2] in {
2103 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2104 (CVTDQ2PSrr VR128:$src)>;
2105 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2106 (CVTDQ2PSrm addr:$src)>;
2108 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2109 (CVTDQ2PSrr VR128:$src)>;
2110 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2111 (CVTDQ2PSrm addr:$src)>;
2113 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2114 (CVTTPS2DQrr VR128:$src)>;
2115 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2116 (CVTTPS2DQrm addr:$src)>;
2119 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2120 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2122 (int_x86_sse2_cvttpd2dq VR128:$src))],
2123 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2125 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2126 // register, but the same isn't true when using memory operands instead.
2127 // Provide other assembly rr and rm forms to address this explicitly.
2130 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2131 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2132 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2133 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2134 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2135 (loadv2f64 addr:$src)))],
2136 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2139 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2140 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2142 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2143 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2144 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2145 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2147 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2148 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2149 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2150 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2152 let Predicates = [HasAVX] in {
2153 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2154 (VCVTTPD2DQYrr VR256:$src)>;
2155 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2156 (VCVTTPD2DQYrm addr:$src)>;
2157 } // Predicates = [HasAVX]
2159 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2160 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2161 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2162 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2163 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2164 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2165 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2166 (memopv2f64 addr:$src)))],
2168 Sched<[WriteCvtF2ILd]>;
2170 // Convert packed single to packed double
2171 let Predicates = [HasAVX] in {
2172 // SSE2 instructions without OpSize prefix
2173 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2174 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2175 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2176 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2177 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2178 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2179 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2180 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2181 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2182 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2184 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2185 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2186 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2187 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2189 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2190 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2193 let Predicates = [UseSSE2] in {
2194 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2195 "cvtps2pd\t{$src, $dst|$dst, $src}",
2196 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2197 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2198 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2199 "cvtps2pd\t{$src, $dst|$dst, $src}",
2200 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2201 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2204 // Convert Packed DW Integers to Packed Double FP
2205 let Predicates = [HasAVX] in {
2206 let hasSideEffects = 0, mayLoad = 1 in
2207 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2208 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2209 []>, VEX, Sched<[WriteCvtI2FLd]>;
2210 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2211 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2213 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2214 Sched<[WriteCvtI2F]>;
2215 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2216 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2218 (int_x86_avx_cvtdq2_pd_256
2219 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2220 Sched<[WriteCvtI2FLd]>;
2221 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2222 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2224 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2225 Sched<[WriteCvtI2F]>;
2228 let hasSideEffects = 0, mayLoad = 1 in
2229 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2230 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2231 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2232 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2233 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2234 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2235 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2237 // AVX 256-bit register conversion intrinsics
2238 let Predicates = [HasAVX] in {
2239 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2240 (VCVTDQ2PDYrr VR128:$src)>;
2241 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2242 (VCVTDQ2PDYrm addr:$src)>;
2243 } // Predicates = [HasAVX]
2245 // Convert packed double to packed single
2246 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2247 // register, but the same isn't true when using memory operands instead.
2248 // Provide other assembly rr and rm forms to address this explicitly.
2249 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2250 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2251 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2252 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2255 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2256 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2257 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2258 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2260 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2261 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2264 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2265 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2267 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2268 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2269 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2270 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2272 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2273 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2274 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2275 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2277 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2278 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2279 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2280 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2281 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2282 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2284 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2285 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2288 // AVX 256-bit register conversion intrinsics
2289 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2290 // whenever possible to avoid declaring two versions of each one.
2291 let Predicates = [HasAVX] in {
2292 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2293 (VCVTDQ2PSYrr VR256:$src)>;
2294 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2295 (VCVTDQ2PSYrm addr:$src)>;
2297 // Match fround and fextend for 128/256-bit conversions
2298 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2299 (VCVTPD2PSrr VR128:$src)>;
2300 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2301 (VCVTPD2PSXrm addr:$src)>;
2302 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2303 (VCVTPD2PSYrr VR256:$src)>;
2304 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2305 (VCVTPD2PSYrm addr:$src)>;
2307 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2308 (VCVTPS2PDrr VR128:$src)>;
2309 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2310 (VCVTPS2PDYrr VR128:$src)>;
2311 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2312 (VCVTPS2PDYrm addr:$src)>;
2315 let Predicates = [UseSSE2] in {
2316 // Match fround and fextend for 128 conversions
2317 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2318 (CVTPD2PSrr VR128:$src)>;
2319 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2320 (CVTPD2PSrm addr:$src)>;
2322 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2323 (CVTPS2PDrr VR128:$src)>;
2326 //===----------------------------------------------------------------------===//
2327 // SSE 1 & 2 - Compare Instructions
2328 //===----------------------------------------------------------------------===//
2330 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2331 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2332 Operand CC, SDNode OpNode, ValueType VT,
2333 PatFrag ld_frag, string asm, string asm_alt,
2334 OpndItins itins, ImmLeaf immLeaf> {
2335 def rr : SIi8<0xC2, MRMSrcReg,
2336 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2337 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))],
2338 itins.rr>, Sched<[itins.Sched]>;
2339 def rm : SIi8<0xC2, MRMSrcMem,
2340 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2341 [(set RC:$dst, (OpNode (VT RC:$src1),
2342 (ld_frag addr:$src2), immLeaf:$cc))],
2344 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2346 // Accept explicit immediate argument form instead of comparison code.
2347 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2348 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2349 (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, [],
2350 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2352 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2353 (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, [],
2354 IIC_SSE_ALU_F32S_RM>,
2355 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2359 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2360 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2361 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2362 SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG;
2363 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2364 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2365 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2366 SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare
2367 XD, VEX_4V, VEX_LIG;
2369 let Constraints = "$src1 = $dst" in {
2370 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2371 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2372 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S,
2374 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2375 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2376 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2377 SSE_ALU_F64S, i8immZExt3>, XD;
2380 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2381 Intrinsic Int, string asm, OpndItins itins,
2383 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2384 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2385 [(set VR128:$dst, (Int VR128:$src1,
2386 VR128:$src, immLeaf:$cc))],
2388 Sched<[itins.Sched]>;
2389 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2390 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2391 [(set VR128:$dst, (Int VR128:$src1,
2392 (load addr:$src), immLeaf:$cc))],
2394 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2397 let isCodeGenOnly = 1 in {
2398 // Aliases to match intrinsics which expect XMM operand(s).
2399 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2400 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2401 SSE_ALU_F32S, i8immZExt5>,
2403 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2404 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2405 SSE_ALU_F32S, i8immZExt5>, // same latency as f32
2407 let Constraints = "$src1 = $dst" in {
2408 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2409 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2410 SSE_ALU_F32S, i8immZExt3>, XS;
2411 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2412 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2413 SSE_ALU_F64S, i8immZExt3>,
2419 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2420 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2421 ValueType vt, X86MemOperand x86memop,
2422 PatFrag ld_frag, string OpcodeStr> {
2423 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2424 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2425 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2428 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2429 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2430 [(set EFLAGS, (OpNode (vt RC:$src1),
2431 (ld_frag addr:$src2)))],
2433 Sched<[WriteFAddLd, ReadAfterLd]>;
2436 let Defs = [EFLAGS] in {
2437 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2438 "ucomiss">, PS, VEX, VEX_LIG;
2439 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2440 "ucomisd">, PD, VEX, VEX_LIG;
2441 let Pattern = []<dag> in {
2442 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2443 "comiss">, PS, VEX, VEX_LIG;
2444 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2445 "comisd">, PD, VEX, VEX_LIG;
2448 let isCodeGenOnly = 1 in {
2449 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2450 load, "ucomiss">, PS, VEX;
2451 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2452 load, "ucomisd">, PD, VEX;
2454 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2455 load, "comiss">, PS, VEX;
2456 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2457 load, "comisd">, PD, VEX;
2459 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2461 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2464 let Pattern = []<dag> in {
2465 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2467 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2471 let isCodeGenOnly = 1 in {
2472 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2473 load, "ucomiss">, PS;
2474 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2475 load, "ucomisd">, PD;
2477 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2479 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2482 } // Defs = [EFLAGS]
2484 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2485 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2486 Operand CC, Intrinsic Int, string asm,
2487 string asm_alt, Domain d, ImmLeaf immLeaf,
2488 PatFrag ld_frag, OpndItins itins = SSE_ALU_F32P> {
2489 let isCommutable = 1 in
2490 def rri : PIi8<0xC2, MRMSrcReg,
2491 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2492 [(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
2495 def rmi : PIi8<0xC2, MRMSrcMem,
2496 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2497 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2), immLeaf:$cc))],
2499 Sched<[WriteFAddLd, ReadAfterLd]>;
2501 // Accept explicit immediate argument form instead of comparison code.
2502 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2503 def rri_alt : PIi8<0xC2, MRMSrcReg,
2504 (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
2505 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2507 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2508 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
2509 asm_alt, [], itins.rm, d>,
2510 Sched<[WriteFAddLd, ReadAfterLd]>;
2514 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2515 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2516 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2517 SSEPackedSingle, i8immZExt5, loadv4f32>, PS, VEX_4V;
2518 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2519 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2520 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2521 SSEPackedDouble, i8immZExt5, loadv2f64>, PD, VEX_4V;
2522 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2523 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2524 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2525 SSEPackedSingle, i8immZExt5, loadv8f32>, PS, VEX_4V, VEX_L;
2526 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2527 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2528 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2529 SSEPackedDouble, i8immZExt5, loadv4f64>, PD, VEX_4V, VEX_L;
2530 let Constraints = "$src1 = $dst" in {
2531 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2532 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2533 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2534 SSEPackedSingle, i8immZExt5, memopv4f32, SSE_ALU_F32P>, PS;
2535 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2536 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2537 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2538 SSEPackedDouble, i8immZExt5, memopv2f64, SSE_ALU_F64P>, PD;
2541 let Predicates = [HasAVX] in {
2542 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2543 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2544 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (loadv4f32 addr:$src2), imm:$cc)),
2545 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2546 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2547 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2548 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (loadv2f64 addr:$src2), imm:$cc)),
2549 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2551 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2552 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2553 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (loadv8f32 addr:$src2), imm:$cc)),
2554 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2555 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2556 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2557 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (loadv4f64 addr:$src2), imm:$cc)),
2558 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2561 let Predicates = [UseSSE1] in {
2562 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2563 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2564 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memopv4f32 addr:$src2), imm:$cc)),
2565 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2568 let Predicates = [UseSSE2] in {
2569 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2570 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2571 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memopv2f64 addr:$src2), imm:$cc)),
2572 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2575 //===----------------------------------------------------------------------===//
2576 // SSE 1 & 2 - Shuffle Instructions
2577 //===----------------------------------------------------------------------===//
2579 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2580 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2581 ValueType vt, string asm, PatFrag mem_frag,
2583 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2584 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2585 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2586 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2587 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2588 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2589 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2590 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2591 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2592 Sched<[WriteFShuffle]>;
2595 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2596 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2597 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2598 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2599 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2600 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2601 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2602 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2603 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2604 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2605 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2606 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2608 let Constraints = "$src1 = $dst" in {
2609 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2610 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2611 memopv4f32, SSEPackedSingle>, PS;
2612 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2613 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2614 memopv2f64, SSEPackedDouble>, PD;
2617 let Predicates = [HasAVX] in {
2618 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2619 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2620 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2621 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2622 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2624 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2625 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2626 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2627 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2628 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2631 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2632 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2633 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2634 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2635 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2637 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2638 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2639 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2640 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2641 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2644 let Predicates = [UseSSE1] in {
2645 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2646 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2647 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2648 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2649 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2652 let Predicates = [UseSSE2] in {
2653 // Generic SHUFPD patterns
2654 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2655 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2656 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2657 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2658 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2661 //===----------------------------------------------------------------------===//
2662 // SSE 1 & 2 - Unpack FP Instructions
2663 //===----------------------------------------------------------------------===//
2665 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2666 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2667 PatFrag mem_frag, RegisterClass RC,
2668 X86MemOperand x86memop, string asm,
2670 def rr : PI<opc, MRMSrcReg,
2671 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2673 (vt (OpNode RC:$src1, RC:$src2)))],
2674 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2675 def rm : PI<opc, MRMSrcMem,
2676 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2678 (vt (OpNode RC:$src1,
2679 (mem_frag addr:$src2))))],
2681 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2684 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2685 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2686 SSEPackedSingle>, PS, VEX_4V;
2687 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2688 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2689 SSEPackedDouble>, PD, VEX_4V;
2690 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2691 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2692 SSEPackedSingle>, PS, VEX_4V;
2693 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2694 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2695 SSEPackedDouble>, PD, VEX_4V;
2697 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2698 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2699 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2700 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2701 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2702 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2703 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2704 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2705 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2706 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2707 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2708 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2710 let Constraints = "$src1 = $dst" in {
2711 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2712 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2713 SSEPackedSingle>, PS;
2714 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2715 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2716 SSEPackedDouble>, PD;
2717 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2718 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2719 SSEPackedSingle>, PS;
2720 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2721 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2722 SSEPackedDouble>, PD;
2723 } // Constraints = "$src1 = $dst"
2725 let Predicates = [HasAVX1Only] in {
2726 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2727 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2728 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2729 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2730 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2731 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2732 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2733 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2735 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2736 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2737 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2738 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2739 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2740 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2741 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2742 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2745 //===----------------------------------------------------------------------===//
2746 // SSE 1 & 2 - Extract Floating-Point Sign mask
2747 //===----------------------------------------------------------------------===//
2749 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2750 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2752 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2753 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2754 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2755 Sched<[WriteVecLogic]>;
2758 let Predicates = [HasAVX] in {
2759 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2760 "movmskps", SSEPackedSingle>, PS, VEX;
2761 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2762 "movmskpd", SSEPackedDouble>, PD, VEX;
2763 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2764 "movmskps", SSEPackedSingle>, PS,
2766 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2767 "movmskpd", SSEPackedDouble>, PD,
2770 def : Pat<(i32 (X86fgetsign FR32:$src)),
2771 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2772 def : Pat<(i64 (X86fgetsign FR32:$src)),
2773 (SUBREG_TO_REG (i64 0),
2774 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2775 def : Pat<(i32 (X86fgetsign FR64:$src)),
2776 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2777 def : Pat<(i64 (X86fgetsign FR64:$src)),
2778 (SUBREG_TO_REG (i64 0),
2779 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2782 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2783 SSEPackedSingle>, PS;
2784 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2785 SSEPackedDouble>, PD;
2787 def : Pat<(i32 (X86fgetsign FR32:$src)),
2788 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2789 Requires<[UseSSE1]>;
2790 def : Pat<(i64 (X86fgetsign FR32:$src)),
2791 (SUBREG_TO_REG (i64 0),
2792 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2793 Requires<[UseSSE1]>;
2794 def : Pat<(i32 (X86fgetsign FR64:$src)),
2795 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2796 Requires<[UseSSE2]>;
2797 def : Pat<(i64 (X86fgetsign FR64:$src)),
2798 (SUBREG_TO_REG (i64 0),
2799 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2800 Requires<[UseSSE2]>;
2802 //===---------------------------------------------------------------------===//
2803 // SSE2 - Packed Integer Logical Instructions
2804 //===---------------------------------------------------------------------===//
2806 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2808 /// PDI_binop_rm - Simple SSE2 binary operator.
2809 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2810 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2811 X86MemOperand x86memop, OpndItins itins,
2812 bit IsCommutable, bit Is2Addr> {
2813 let isCommutable = IsCommutable in
2814 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2815 (ins RC:$src1, RC:$src2),
2817 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2818 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2819 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2820 Sched<[itins.Sched]>;
2821 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2822 (ins RC:$src1, x86memop:$src2),
2824 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2825 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2826 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2827 (bitconvert (memop_frag addr:$src2)))))],
2829 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2831 } // ExeDomain = SSEPackedInt
2833 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2834 ValueType OpVT128, ValueType OpVT256,
2835 OpndItins itins, bit IsCommutable = 0> {
2836 let Predicates = [HasAVX, NoVLX] in
2837 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2838 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2840 let Constraints = "$src1 = $dst" in
2841 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2842 memopv2i64, i128mem, itins, IsCommutable, 1>;
2844 let Predicates = [HasAVX2, NoVLX] in
2845 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2846 OpVT256, VR256, loadv4i64, i256mem, itins,
2847 IsCommutable, 0>, VEX_4V, VEX_L;
2850 // These are ordered here for pattern ordering requirements with the fp versions
2852 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2853 SSE_VEC_BIT_ITINS_P, 1>;
2854 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2855 SSE_VEC_BIT_ITINS_P, 1>;
2856 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2857 SSE_VEC_BIT_ITINS_P, 1>;
2858 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2859 SSE_VEC_BIT_ITINS_P, 0>;
2861 //===----------------------------------------------------------------------===//
2862 // SSE 1 & 2 - Logical Instructions
2863 //===----------------------------------------------------------------------===//
2865 // Multiclass for scalars using the X86 logical operation aliases for FP.
2866 multiclass sse12_fp_packed_scalar_logical_alias<
2867 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2868 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2869 FR32, f32, f128mem, loadf32_128, SSEPackedSingle, itins, 0>,
2872 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2873 FR64, f64, f128mem, loadf64_128, SSEPackedDouble, itins, 0>,
2876 let Constraints = "$src1 = $dst" in {
2877 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2878 f32, f128mem, memopfsf32_128, SSEPackedSingle, itins>, PS;
2880 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2881 f64, f128mem, memopfsf64_128, SSEPackedDouble, itins>, PD;
2885 let isCodeGenOnly = 1 in {
2886 defm FsAND : sse12_fp_packed_scalar_logical_alias<0x54, "and", X86fand,
2888 defm FsOR : sse12_fp_packed_scalar_logical_alias<0x56, "or", X86for,
2890 defm FsXOR : sse12_fp_packed_scalar_logical_alias<0x57, "xor", X86fxor,
2893 let isCommutable = 0 in
2894 defm FsANDN : sse12_fp_packed_scalar_logical_alias<0x55, "andn", X86fandn,
2898 // Multiclass for vectors using the X86 logical operation aliases for FP.
2899 multiclass sse12_fp_packed_vector_logical_alias<
2900 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2901 let Predicates = [HasAVX, NoVLX] in {
2902 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2903 VR128, v4f32, f128mem, loadv4f32, SSEPackedSingle, itins, 0>,
2906 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2907 VR128, v2f64, f128mem, loadv2f64, SSEPackedDouble, itins, 0>,
2911 let Constraints = "$src1 = $dst" in {
2912 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2913 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins>,
2916 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2917 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins>,
2922 let isCodeGenOnly = 1 in {
2923 defm FvAND : sse12_fp_packed_vector_logical_alias<0x54, "and", X86fand,
2925 defm FvOR : sse12_fp_packed_vector_logical_alias<0x56, "or", X86for,
2927 defm FvXOR : sse12_fp_packed_vector_logical_alias<0x57, "xor", X86fxor,
2930 let isCommutable = 0 in
2931 defm FvANDN : sse12_fp_packed_vector_logical_alias<0x55, "andn", X86fandn,
2935 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2937 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2939 let Predicates = [HasAVX, NoVLX] in {
2940 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2941 !strconcat(OpcodeStr, "ps"), f256mem,
2942 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2943 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2944 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2946 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2947 !strconcat(OpcodeStr, "pd"), f256mem,
2948 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2949 (bc_v4i64 (v4f64 VR256:$src2))))],
2950 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2951 (loadv4i64 addr:$src2)))], 0>,
2954 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2955 // are all promoted to v2i64, and the patterns are covered by the int
2956 // version. This is needed in SSE only, because v2i64 isn't supported on
2957 // SSE1, but only on SSE2.
2958 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2959 !strconcat(OpcodeStr, "ps"), f128mem, [],
2960 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2961 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2963 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2964 !strconcat(OpcodeStr, "pd"), f128mem,
2965 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2966 (bc_v2i64 (v2f64 VR128:$src2))))],
2967 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2968 (loadv2i64 addr:$src2)))], 0>,
2972 let Constraints = "$src1 = $dst" in {
2973 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2974 !strconcat(OpcodeStr, "ps"), f128mem,
2975 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2976 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2977 (memopv2i64 addr:$src2)))]>, PS;
2979 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2980 !strconcat(OpcodeStr, "pd"), f128mem,
2981 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2982 (bc_v2i64 (v2f64 VR128:$src2))))],
2983 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2984 (memopv2i64 addr:$src2)))]>, PD;
2988 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2989 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2990 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2991 let isCommutable = 0 in
2992 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2994 // AVX1 requires type coercions in order to fold loads directly into logical
2996 let Predicates = [HasAVX1Only] in {
2997 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
2998 (VANDPSYrm VR256:$src1, addr:$src2)>;
2999 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3000 (VORPSYrm VR256:$src1, addr:$src2)>;
3001 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3002 (VXORPSYrm VR256:$src1, addr:$src2)>;
3003 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3004 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3007 //===----------------------------------------------------------------------===//
3008 // SSE 1 & 2 - Arithmetic Instructions
3009 //===----------------------------------------------------------------------===//
3011 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3014 /// In addition, we also have a special variant of the scalar form here to
3015 /// represent the associated intrinsic operation. This form is unlike the
3016 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3017 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3019 /// These three forms can each be reg+reg or reg+mem.
3022 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3024 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3025 SDNode OpNode, SizeItins itins> {
3026 let Predicates = [HasAVX, NoVLX] in {
3027 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3028 VR128, v4f32, f128mem, loadv4f32,
3029 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3030 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3031 VR128, v2f64, f128mem, loadv2f64,
3032 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3034 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3035 OpNode, VR256, v8f32, f256mem, loadv8f32,
3036 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3037 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3038 OpNode, VR256, v4f64, f256mem, loadv4f64,
3039 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3042 let Constraints = "$src1 = $dst" in {
3043 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3044 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3046 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3047 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3052 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3054 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3055 OpNode, FR32, f32mem, SSEPackedSingle, itins.s, 0>,
3056 XS, VEX_4V, VEX_LIG;
3057 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3058 OpNode, FR64, f64mem, SSEPackedDouble, itins.d, 0>,
3059 XD, VEX_4V, VEX_LIG;
3061 let Constraints = "$src1 = $dst" in {
3062 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3063 OpNode, FR32, f32mem, SSEPackedSingle,
3065 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3066 OpNode, FR64, f64mem, SSEPackedDouble,
3071 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3073 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3074 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3075 SSEPackedSingle, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3076 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3077 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3078 SSEPackedDouble, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3080 let Constraints = "$src1 = $dst" in {
3081 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3082 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3083 SSEPackedSingle, itins.s>, XS;
3084 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3085 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3086 SSEPackedDouble, itins.d>, XD;
3090 // Binary Arithmetic instructions
3091 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3092 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3093 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3094 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3095 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3096 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3097 let isCommutable = 0 in {
3098 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3099 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3100 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3101 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3102 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3103 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3104 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3105 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3106 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3107 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3108 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3109 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3112 let isCodeGenOnly = 1 in {
3113 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3114 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3115 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3116 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3119 // Patterns used to select SSE scalar fp arithmetic instructions from
3122 // (1) a scalar fp operation followed by a blend
3124 // The effect is that the backend no longer emits unnecessary vector
3125 // insert instructions immediately after SSE scalar fp instructions
3126 // like addss or mulss.
3128 // For example, given the following code:
3129 // __m128 foo(__m128 A, __m128 B) {
3134 // Previously we generated:
3135 // addss %xmm0, %xmm1
3136 // movss %xmm1, %xmm0
3139 // addss %xmm1, %xmm0
3141 // (2) a vector packed single/double fp operation followed by a vector insert
3143 // The effect is that the backend converts the packed fp instruction
3144 // followed by a vector insert into a single SSE scalar fp instruction.
3146 // For example, given the following code:
3147 // __m128 foo(__m128 A, __m128 B) {
3148 // __m128 C = A + B;
3149 // return (__m128) {c[0], a[1], a[2], a[3]};
3152 // Previously we generated:
3153 // addps %xmm0, %xmm1
3154 // movss %xmm1, %xmm0
3157 // addss %xmm1, %xmm0
3159 // TODO: Some canonicalization in lowering would simplify the number of
3160 // patterns we have to try to match.
3161 multiclass scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {
3162 let Predicates = [UseSSE1] in {
3163 // extracted scalar math op with insert via movss
3164 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3165 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3167 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3168 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3170 // vector math op with insert via movss
3171 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3172 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3173 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3176 // With SSE 4.1, blendi is preferred to movsd, so match that too.
3177 let Predicates = [UseSSE41] in {
3178 // extracted scalar math op with insert via blend
3179 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3180 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3181 FR32:$src))), (i8 1))),
3182 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3183 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3185 // vector math op with insert via blend
3186 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3187 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3188 (!cast<I>(OpcPrefix#SSrr_Int)v4f32:$dst, v4f32:$src)>;
3192 // Repeat everything for AVX, except for the movss + scalar combo...
3193 // because that one shouldn't occur with AVX codegen?
3194 let Predicates = [HasAVX] in {
3195 // extracted scalar math op with insert via blend
3196 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3197 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3198 FR32:$src))), (i8 1))),
3199 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst,
3200 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3202 // vector math op with insert via movss
3203 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3204 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3205 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3207 // vector math op with insert via blend
3208 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3209 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3210 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3214 defm : scalar_math_f32_patterns<fadd, "ADD">;
3215 defm : scalar_math_f32_patterns<fsub, "SUB">;
3216 defm : scalar_math_f32_patterns<fmul, "MUL">;
3217 defm : scalar_math_f32_patterns<fdiv, "DIV">;
3219 multiclass scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {
3220 let Predicates = [UseSSE2] in {
3221 // extracted scalar math op with insert via movsd
3222 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3223 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3225 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3226 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3228 // vector math op with insert via movsd
3229 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3230 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3231 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3234 // With SSE 4.1, blendi is preferred to movsd, so match those too.
3235 let Predicates = [UseSSE41] in {
3236 // extracted scalar math op with insert via blend
3237 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3238 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3239 FR64:$src))), (i8 1))),
3240 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3241 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3243 // vector math op with insert via blend
3244 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3245 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3246 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3249 // Repeat everything for AVX.
3250 let Predicates = [HasAVX] in {
3251 // extracted scalar math op with insert via movsd
3252 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3253 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3255 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3256 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3258 // extracted scalar math op with insert via blend
3259 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3260 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3261 FR64:$src))), (i8 1))),
3262 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3263 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3265 // vector math op with insert via movsd
3266 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3267 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3268 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3270 // vector math op with insert via blend
3271 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3272 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3273 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3277 defm : scalar_math_f64_patterns<fadd, "ADD">;
3278 defm : scalar_math_f64_patterns<fsub, "SUB">;
3279 defm : scalar_math_f64_patterns<fmul, "MUL">;
3280 defm : scalar_math_f64_patterns<fdiv, "DIV">;
3284 /// In addition, we also have a special variant of the scalar form here to
3285 /// represent the associated intrinsic operation. This form is unlike the
3286 /// plain scalar form, in that it takes an entire vector (instead of a
3287 /// scalar) and leaves the top elements undefined.
3289 /// And, we have a special variant form for a full-vector intrinsic form.
3291 let Sched = WriteFSqrt in {
3292 def SSE_SQRTPS : OpndItins<
3293 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3296 def SSE_SQRTSS : OpndItins<
3297 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3300 def SSE_SQRTPD : OpndItins<
3301 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3304 def SSE_SQRTSD : OpndItins<
3305 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3309 let Sched = WriteFRsqrt in {
3310 def SSE_RSQRTPS : OpndItins<
3311 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3314 def SSE_RSQRTSS : OpndItins<
3315 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3319 let Sched = WriteFRcp in {
3320 def SSE_RCPP : OpndItins<
3321 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3324 def SSE_RCPS : OpndItins<
3325 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3329 /// sse_fp_unop_s - SSE1 unops in scalar form
3330 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3331 /// the HW instructions are 2 operand / destructive.
3332 multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3333 ValueType vt, ValueType ScalarVT,
3334 X86MemOperand x86memop, Operand vec_memop,
3335 ComplexPattern mem_cpat, Intrinsic Intr,
3336 SDNode OpNode, Domain d, OpndItins itins,
3337 Predicate target, string Suffix> {
3338 let hasSideEffects = 0 in {
3339 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
3340 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3341 [(set RC:$dst, (OpNode RC:$src1))], itins.rr, d>, Sched<[itins.Sched]>,
3344 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1),
3345 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3346 [(set RC:$dst, (OpNode (load addr:$src1)))], itins.rm, d>,
3347 Sched<[itins.Sched.Folded, ReadAfterLd]>,
3348 Requires<[target, OptForSize]>;
3350 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3351 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3352 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3353 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3355 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, vec_memop:$src2),
3356 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3357 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3361 let Predicates = [target] in {
3362 def : Pat<(vt (OpNode mem_cpat:$src)),
3363 (vt (COPY_TO_REGCLASS (vt (!cast<Instruction>(NAME#Suffix##m_Int)
3364 (vt (IMPLICIT_DEF)), mem_cpat:$src)), RC))>;
3365 // These are unary operations, but they are modeled as having 2 source operands
3366 // because the high elements of the destination are unchanged in SSE.
3367 def : Pat<(Intr VR128:$src),
3368 (!cast<Instruction>(NAME#Suffix##r_Int) VR128:$src, VR128:$src)>;
3369 def : Pat<(Intr (load addr:$src)),
3370 (vt (COPY_TO_REGCLASS(!cast<Instruction>(NAME#Suffix##m)
3371 addr:$src), VR128))>;
3372 def : Pat<(Intr mem_cpat:$src),
3373 (!cast<Instruction>(NAME#Suffix##m_Int)
3374 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3378 multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3379 ValueType vt, ValueType ScalarVT,
3380 X86MemOperand x86memop, Operand vec_memop,
3381 ComplexPattern mem_cpat,
3382 Intrinsic Intr, SDNode OpNode, Domain d,
3383 OpndItins itins, string Suffix> {
3384 let hasSideEffects = 0 in {
3385 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3386 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3387 [], itins.rr, d>, Sched<[itins.Sched]>;
3389 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3390 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3391 [], itins.rm, d>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3392 let isCodeGenOnly = 1 in {
3393 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
3394 (ins VR128:$src1, VR128:$src2),
3395 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3396 []>, Sched<[itins.Sched.Folded]>;
3398 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst),
3399 (ins VR128:$src1, vec_memop:$src2),
3400 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3401 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3405 let Predicates = [UseAVX] in {
3406 def : Pat<(OpNode RC:$src), (!cast<Instruction>("V"#NAME#Suffix##r)
3407 (ScalarVT (IMPLICIT_DEF)), RC:$src)>;
3409 def : Pat<(vt (OpNode mem_cpat:$src)),
3410 (!cast<Instruction>("V"#NAME#Suffix##m_Int) (vt (IMPLICIT_DEF)),
3414 let Predicates = [HasAVX] in {
3415 def : Pat<(Intr VR128:$src),
3416 (!cast<Instruction>("V"#NAME#Suffix##r_Int) (vt (IMPLICIT_DEF)),
3419 def : Pat<(Intr mem_cpat:$src),
3420 (!cast<Instruction>("V"#NAME#Suffix##m_Int)
3421 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3423 let Predicates = [UseAVX, OptForSize] in
3424 def : Pat<(ScalarVT (OpNode (load addr:$src))),
3425 (!cast<Instruction>("V"#NAME#Suffix##m) (ScalarVT (IMPLICIT_DEF)),
3429 /// sse1_fp_unop_p - SSE1 unops in packed form.
3430 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3432 let Predicates = [HasAVX] in {
3433 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3434 !strconcat("v", OpcodeStr,
3435 "ps\t{$src, $dst|$dst, $src}"),
3436 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3437 itins.rr>, VEX, Sched<[itins.Sched]>;
3438 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3439 !strconcat("v", OpcodeStr,
3440 "ps\t{$src, $dst|$dst, $src}"),
3441 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3442 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3443 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3444 !strconcat("v", OpcodeStr,
3445 "ps\t{$src, $dst|$dst, $src}"),
3446 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3447 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3448 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3449 !strconcat("v", OpcodeStr,
3450 "ps\t{$src, $dst|$dst, $src}"),
3451 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3452 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3455 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3456 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3457 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3458 Sched<[itins.Sched]>;
3459 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3460 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3461 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3462 Sched<[itins.Sched.Folded]>;
3465 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3466 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3467 SDNode OpNode, OpndItins itins> {
3468 let Predicates = [HasAVX] in {
3469 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3470 !strconcat("v", OpcodeStr,
3471 "pd\t{$src, $dst|$dst, $src}"),
3472 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3473 itins.rr>, VEX, Sched<[itins.Sched]>;
3474 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3475 !strconcat("v", OpcodeStr,
3476 "pd\t{$src, $dst|$dst, $src}"),
3477 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3478 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3479 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3480 !strconcat("v", OpcodeStr,
3481 "pd\t{$src, $dst|$dst, $src}"),
3482 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3483 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3484 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3485 !strconcat("v", OpcodeStr,
3486 "pd\t{$src, $dst|$dst, $src}"),
3487 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3488 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3491 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3492 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3493 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3494 Sched<[itins.Sched]>;
3495 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3496 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3497 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3498 Sched<[itins.Sched.Folded]>;
3501 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3503 defm SS : sse_fp_unop_s<opc, OpcodeStr##ss, FR32, v4f32, f32, f32mem,
3504 ssmem, sse_load_f32,
3505 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3506 SSEPackedSingle, itins, UseSSE1, "SS">, XS;
3507 defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr##ss, FR32, v4f32, f32,
3508 f32mem, ssmem, sse_load_f32,
3509 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3510 SSEPackedSingle, itins, "SS">, XS, VEX_4V, VEX_LIG;
3513 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3515 defm SD : sse_fp_unop_s<opc, OpcodeStr##sd, FR64, v2f64, f64, f64mem,
3516 sdmem, sse_load_f64,
3517 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3518 OpNode, SSEPackedDouble, itins, UseSSE2, "SD">, XD;
3519 defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr##sd, FR64, v2f64, f64,
3520 f64mem, sdmem, sse_load_f64,
3521 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3522 OpNode, SSEPackedDouble, itins, "SD">,
3523 XD, VEX_4V, VEX_LIG;
3527 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3528 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3529 sse2_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSD>,
3530 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3532 // Reciprocal approximations. Note that these typically require refinement
3533 // in order to obtain suitable precision.
3534 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3535 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>;
3536 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3537 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>;
3539 // There is no f64 version of the reciprocal approximation instructions.
3541 // TODO: We should add *scalar* op patterns for these just like we have for
3542 // the binops above. If the binop and unop patterns could all be unified
3543 // that would be even better.
3545 multiclass scalar_unary_math_patterns<Intrinsic Intr, string OpcPrefix,
3546 SDNode Move, ValueType VT,
3547 Predicate BasePredicate> {
3548 let Predicates = [BasePredicate] in {
3549 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3550 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3553 // With SSE 4.1, blendi is preferred to movs*, so match that too.
3554 let Predicates = [UseSSE41] in {
3555 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3556 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3559 // Repeat for AVX versions of the instructions.
3560 let Predicates = [HasAVX] in {
3561 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3562 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3564 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3565 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3569 defm : scalar_unary_math_patterns<int_x86_sse_rcp_ss, "RCPSS", X86Movss,
3571 defm : scalar_unary_math_patterns<int_x86_sse_rsqrt_ss, "RSQRTSS", X86Movss,
3573 defm : scalar_unary_math_patterns<int_x86_sse_sqrt_ss, "SQRTSS", X86Movss,
3575 defm : scalar_unary_math_patterns<int_x86_sse2_sqrt_sd, "SQRTSD", X86Movsd,
3579 //===----------------------------------------------------------------------===//
3580 // SSE 1 & 2 - Non-temporal stores
3581 //===----------------------------------------------------------------------===//
3583 let AddedComplexity = 400 in { // Prefer non-temporal versions
3584 let SchedRW = [WriteStore] in {
3585 let Predicates = [HasAVX, NoVLX] in {
3586 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3587 (ins f128mem:$dst, VR128:$src),
3588 "movntps\t{$src, $dst|$dst, $src}",
3589 [(alignednontemporalstore (v4f32 VR128:$src),
3591 IIC_SSE_MOVNT>, VEX;
3592 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3593 (ins f128mem:$dst, VR128:$src),
3594 "movntpd\t{$src, $dst|$dst, $src}",
3595 [(alignednontemporalstore (v2f64 VR128:$src),
3597 IIC_SSE_MOVNT>, VEX;
3599 let ExeDomain = SSEPackedInt in
3600 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3601 (ins f128mem:$dst, VR128:$src),
3602 "movntdq\t{$src, $dst|$dst, $src}",
3603 [(alignednontemporalstore (v2i64 VR128:$src),
3605 IIC_SSE_MOVNT>, VEX;
3607 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3608 (ins f256mem:$dst, VR256:$src),
3609 "movntps\t{$src, $dst|$dst, $src}",
3610 [(alignednontemporalstore (v8f32 VR256:$src),
3612 IIC_SSE_MOVNT>, VEX, VEX_L;
3613 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3614 (ins f256mem:$dst, VR256:$src),
3615 "movntpd\t{$src, $dst|$dst, $src}",
3616 [(alignednontemporalstore (v4f64 VR256:$src),
3618 IIC_SSE_MOVNT>, VEX, VEX_L;
3619 let ExeDomain = SSEPackedInt in
3620 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3621 (ins f256mem:$dst, VR256:$src),
3622 "movntdq\t{$src, $dst|$dst, $src}",
3623 [(alignednontemporalstore (v4i64 VR256:$src),
3625 IIC_SSE_MOVNT>, VEX, VEX_L;
3628 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3629 "movntps\t{$src, $dst|$dst, $src}",
3630 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3632 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3633 "movntpd\t{$src, $dst|$dst, $src}",
3634 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3637 let ExeDomain = SSEPackedInt in
3638 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3639 "movntdq\t{$src, $dst|$dst, $src}",
3640 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3643 // There is no AVX form for instructions below this point
3644 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3645 "movnti{l}\t{$src, $dst|$dst, $src}",
3646 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3648 PS, Requires<[HasSSE2]>;
3649 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3650 "movnti{q}\t{$src, $dst|$dst, $src}",
3651 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3653 PS, Requires<[HasSSE2]>;
3654 } // SchedRW = [WriteStore]
3656 let Predicates = [HasAVX2, NoVLX] in {
3657 def : Pat<(alignednontemporalstore (v8i32 VR256:$src), addr:$dst),
3658 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3659 def : Pat<(alignednontemporalstore (v16i16 VR256:$src), addr:$dst),
3660 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3661 def : Pat<(alignednontemporalstore (v32i8 VR256:$src), addr:$dst),
3662 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3665 let Predicates = [HasAVX, NoVLX] in {
3666 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3667 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3668 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3669 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3670 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3671 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3674 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3675 (MOVNTDQmr addr:$dst, VR128:$src)>;
3676 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3677 (MOVNTDQmr addr:$dst, VR128:$src)>;
3678 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3679 (MOVNTDQmr addr:$dst, VR128:$src)>;
3681 } // AddedComplexity
3683 //===----------------------------------------------------------------------===//
3684 // SSE 1 & 2 - Prefetch and memory fence
3685 //===----------------------------------------------------------------------===//
3687 // Prefetch intrinsic.
3688 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3689 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3690 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3691 IIC_SSE_PREFETCH>, TB;
3692 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3693 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3694 IIC_SSE_PREFETCH>, TB;
3695 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3696 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3697 IIC_SSE_PREFETCH>, TB;
3698 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3699 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3700 IIC_SSE_PREFETCH>, TB;
3703 // FIXME: How should flush instruction be modeled?
3704 let SchedRW = [WriteLoad] in {
3706 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3707 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3708 IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
3711 let SchedRW = [WriteNop] in {
3712 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3713 // was introduced with SSE2, it's backward compatible.
3714 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3715 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3716 OBXS, Requires<[HasSSE2]>;
3719 let SchedRW = [WriteFence] in {
3720 // Load, store, and memory fence
3721 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3722 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3723 PS, Requires<[HasSSE1]>;
3724 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3725 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3726 TB, Requires<[HasSSE2]>;
3727 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3728 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3729 TB, Requires<[HasSSE2]>;
3732 def : Pat<(X86SFence), (SFENCE)>;
3733 def : Pat<(X86LFence), (LFENCE)>;
3734 def : Pat<(X86MFence), (MFENCE)>;
3736 //===----------------------------------------------------------------------===//
3737 // SSE 1 & 2 - Load/Store XCSR register
3738 //===----------------------------------------------------------------------===//
3740 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3741 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3742 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3743 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3744 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3745 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3747 let Predicates = [UseSSE1] in {
3748 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
3749 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3750 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
3751 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3752 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3753 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
3756 //===---------------------------------------------------------------------===//
3757 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3758 //===---------------------------------------------------------------------===//
3760 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3762 let hasSideEffects = 0, SchedRW = [WriteMove] in {
3763 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3764 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3766 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3767 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3769 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3770 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3772 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3773 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3778 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3779 SchedRW = [WriteMove] in {
3780 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3781 "movdqa\t{$src, $dst|$dst, $src}", [],
3784 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3785 "movdqa\t{$src, $dst|$dst, $src}", [],
3786 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3787 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3788 "movdqu\t{$src, $dst|$dst, $src}", [],
3791 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3792 "movdqu\t{$src, $dst|$dst, $src}", [],
3793 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3796 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3797 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3798 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3799 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3801 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3802 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3804 let Predicates = [HasAVX] in {
3805 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3806 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3808 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3809 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3814 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3815 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3816 (ins i128mem:$dst, VR128:$src),
3817 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3819 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3820 (ins i256mem:$dst, VR256:$src),
3821 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3823 let Predicates = [HasAVX] in {
3824 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3825 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3827 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3828 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3833 let SchedRW = [WriteMove] in {
3834 let hasSideEffects = 0 in
3835 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3836 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3838 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3839 "movdqu\t{$src, $dst|$dst, $src}",
3840 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3843 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3844 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3845 "movdqa\t{$src, $dst|$dst, $src}", [],
3848 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3849 "movdqu\t{$src, $dst|$dst, $src}",
3850 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3854 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3855 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3856 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3857 "movdqa\t{$src, $dst|$dst, $src}",
3858 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3860 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3861 "movdqu\t{$src, $dst|$dst, $src}",
3862 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3864 XS, Requires<[UseSSE2]>;
3867 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3868 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3869 "movdqa\t{$src, $dst|$dst, $src}",
3870 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3872 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3873 "movdqu\t{$src, $dst|$dst, $src}",
3874 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3876 XS, Requires<[UseSSE2]>;
3879 } // ExeDomain = SSEPackedInt
3881 let Predicates = [HasAVX] in {
3882 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3883 (VMOVDQUmr addr:$dst, VR128:$src)>;
3884 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3885 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3887 let Predicates = [UseSSE2] in
3888 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3889 (MOVDQUmr addr:$dst, VR128:$src)>;
3891 //===---------------------------------------------------------------------===//
3892 // SSE2 - Packed Integer Arithmetic Instructions
3893 //===---------------------------------------------------------------------===//
3895 let Sched = WriteVecIMul in
3896 def SSE_PMADD : OpndItins<
3897 IIC_SSE_PMADD, IIC_SSE_PMADD
3900 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3902 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3903 RegisterClass RC, PatFrag memop_frag,
3904 X86MemOperand x86memop,
3906 bit IsCommutable = 0,
3908 let isCommutable = IsCommutable in
3909 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3910 (ins RC:$src1, RC:$src2),
3912 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3913 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3914 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3915 Sched<[itins.Sched]>;
3916 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3917 (ins RC:$src1, x86memop:$src2),
3919 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3920 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3921 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3922 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3925 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3926 Intrinsic IntId256, OpndItins itins,
3927 bit IsCommutable = 0> {
3928 let Predicates = [HasAVX] in
3929 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3930 VR128, loadv2i64, i128mem, itins,
3931 IsCommutable, 0>, VEX_4V;
3933 let Constraints = "$src1 = $dst" in
3934 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3935 i128mem, itins, IsCommutable, 1>;
3937 let Predicates = [HasAVX2] in
3938 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3939 VR256, loadv4i64, i256mem, itins,
3940 IsCommutable, 0>, VEX_4V, VEX_L;
3943 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3944 string OpcodeStr, SDNode OpNode,
3945 SDNode OpNode2, RegisterClass RC,
3946 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3947 PatFrag ld_frag, ShiftOpndItins itins,
3949 // src2 is always 128-bit
3950 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3951 (ins RC:$src1, VR128:$src2),
3953 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3954 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3955 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3956 itins.rr>, Sched<[WriteVecShift]>;
3957 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3958 (ins RC:$src1, i128mem:$src2),
3960 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3961 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3962 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3963 (bc_frag (ld_frag addr:$src2)))))], itins.rm>,
3964 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3965 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3966 (ins RC:$src1, u8imm:$src2),
3968 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3969 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3970 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3971 Sched<[WriteVecShift]>;
3974 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3975 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3976 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3977 PatFrag memop_frag, X86MemOperand x86memop,
3979 bit IsCommutable = 0, bit Is2Addr = 1> {
3980 let isCommutable = IsCommutable in
3981 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3982 (ins RC:$src1, RC:$src2),
3984 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3985 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3986 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
3987 Sched<[itins.Sched]>;
3988 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3989 (ins RC:$src1, x86memop:$src2),
3991 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3992 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3993 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3994 (bitconvert (memop_frag addr:$src2)))))]>,
3995 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3997 } // ExeDomain = SSEPackedInt
3999 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4000 SSE_INTALU_ITINS_P, 1>;
4001 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4002 SSE_INTALU_ITINS_P, 1>;
4003 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4004 SSE_INTALU_ITINS_P, 1>;
4005 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4006 SSE_INTALUQ_ITINS_P, 1>;
4007 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4008 SSE_INTMUL_ITINS_P, 1>;
4009 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4010 SSE_INTMUL_ITINS_P, 1>;
4011 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4012 SSE_INTMUL_ITINS_P, 1>;
4013 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4014 SSE_INTALU_ITINS_P, 0>;
4015 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4016 SSE_INTALU_ITINS_P, 0>;
4017 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4018 SSE_INTALU_ITINS_P, 0>;
4019 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4020 SSE_INTALUQ_ITINS_P, 0>;
4021 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4022 SSE_INTALU_ITINS_P, 0>;
4023 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4024 SSE_INTALU_ITINS_P, 0>;
4025 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4026 SSE_INTALU_ITINS_P, 1>;
4027 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4028 SSE_INTALU_ITINS_P, 1>;
4029 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4030 SSE_INTALU_ITINS_P, 1>;
4031 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4032 SSE_INTALU_ITINS_P, 1>;
4035 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4036 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4037 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4038 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4039 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4040 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4041 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4042 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4043 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4044 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4045 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4046 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4047 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4048 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4049 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4050 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4051 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4052 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4053 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4054 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4056 let Predicates = [HasAVX] in
4057 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4058 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4060 let Predicates = [HasAVX2] in
4061 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4062 VR256, loadv4i64, i256mem,
4063 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4064 let Constraints = "$src1 = $dst" in
4065 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4066 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4068 //===---------------------------------------------------------------------===//
4069 // SSE2 - Packed Integer Logical Instructions
4070 //===---------------------------------------------------------------------===//
4072 let Predicates = [HasAVX, NoVLX] in {
4073 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4074 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4075 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4076 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4077 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4078 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4079 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4080 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4081 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4083 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4084 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4085 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4086 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4087 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4088 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4089 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4090 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4091 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4093 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4094 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4095 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4096 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4097 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4098 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4100 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4101 // 128-bit logical shifts.
4102 def VPSLLDQri : PDIi8<0x73, MRM7r,
4103 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4104 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4106 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))]>,
4108 def VPSRLDQri : PDIi8<0x73, MRM3r,
4109 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4110 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4112 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))]>,
4114 // PSRADQri doesn't exist in SSE[1-3].
4116 } // Predicates = [HasAVX]
4118 let Predicates = [HasAVX2, NoVLX] in {
4119 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4120 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4121 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4122 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4123 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4124 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4125 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4126 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4127 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4129 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4130 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4131 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4132 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4133 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4134 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4135 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4136 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4137 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4139 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4140 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4141 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4142 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4143 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4144 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4146 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4147 // 256-bit logical shifts.
4148 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4149 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4150 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4152 (v4i64 (X86vshldq VR256:$src1, (i8 imm:$src2))))]>,
4154 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4155 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4156 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4158 (v4i64 (X86vshrdq VR256:$src1, (i8 imm:$src2))))]>,
4160 // PSRADQYri doesn't exist in SSE[1-3].
4162 } // Predicates = [HasAVX2]
4164 let Constraints = "$src1 = $dst" in {
4165 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4166 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4167 SSE_INTSHIFT_ITINS_P>;
4168 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4169 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4170 SSE_INTSHIFT_ITINS_P>;
4171 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4172 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4173 SSE_INTSHIFT_ITINS_P>;
4175 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4176 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4177 SSE_INTSHIFT_ITINS_P>;
4178 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4179 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4180 SSE_INTSHIFT_ITINS_P>;
4181 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4182 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4183 SSE_INTSHIFT_ITINS_P>;
4185 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4186 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4187 SSE_INTSHIFT_ITINS_P>;
4188 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4189 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4190 SSE_INTSHIFT_ITINS_P>;
4192 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4193 // 128-bit logical shifts.
4194 def PSLLDQri : PDIi8<0x73, MRM7r,
4195 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4196 "pslldq\t{$src2, $dst|$dst, $src2}",
4198 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))],
4199 IIC_SSE_INTSHDQ_P_RI>;
4200 def PSRLDQri : PDIi8<0x73, MRM3r,
4201 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4202 "psrldq\t{$src2, $dst|$dst, $src2}",
4204 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))],
4205 IIC_SSE_INTSHDQ_P_RI>;
4206 // PSRADQri doesn't exist in SSE[1-3].
4208 } // Constraints = "$src1 = $dst"
4210 let Predicates = [HasAVX] in {
4211 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4212 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4215 let Predicates = [UseSSE2] in {
4216 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4217 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4220 //===---------------------------------------------------------------------===//
4221 // SSE2 - Packed Integer Comparison Instructions
4222 //===---------------------------------------------------------------------===//
4224 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4225 SSE_INTALU_ITINS_P, 1>;
4226 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4227 SSE_INTALU_ITINS_P, 1>;
4228 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4229 SSE_INTALU_ITINS_P, 1>;
4230 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4231 SSE_INTALU_ITINS_P, 0>;
4232 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4233 SSE_INTALU_ITINS_P, 0>;
4234 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4235 SSE_INTALU_ITINS_P, 0>;
4237 //===---------------------------------------------------------------------===//
4238 // SSE2 - Packed Integer Shuffle Instructions
4239 //===---------------------------------------------------------------------===//
4241 let ExeDomain = SSEPackedInt in {
4242 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4244 let Predicates = [HasAVX] in {
4245 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4246 (ins VR128:$src1, u8imm:$src2),
4247 !strconcat("v", OpcodeStr,
4248 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4250 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4251 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4252 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4253 (ins i128mem:$src1, u8imm:$src2),
4254 !strconcat("v", OpcodeStr,
4255 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4257 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4258 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4259 Sched<[WriteShuffleLd]>;
4262 let Predicates = [HasAVX2] in {
4263 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4264 (ins VR256:$src1, u8imm:$src2),
4265 !strconcat("v", OpcodeStr,
4266 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4268 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4269 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4270 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4271 (ins i256mem:$src1, u8imm:$src2),
4272 !strconcat("v", OpcodeStr,
4273 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4275 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4276 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4277 Sched<[WriteShuffleLd]>;
4280 let Predicates = [UseSSE2] in {
4281 def ri : Ii8<0x70, MRMSrcReg,
4282 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4283 !strconcat(OpcodeStr,
4284 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4286 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4287 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4288 def mi : Ii8<0x70, MRMSrcMem,
4289 (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2),
4290 !strconcat(OpcodeStr,
4291 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4293 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4294 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4295 Sched<[WriteShuffleLd, ReadAfterLd]>;
4298 } // ExeDomain = SSEPackedInt
4300 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4301 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4302 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4304 let Predicates = [HasAVX] in {
4305 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4306 (VPSHUFDmi addr:$src1, imm:$imm)>;
4307 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4308 (VPSHUFDri VR128:$src1, imm:$imm)>;
4311 let Predicates = [UseSSE2] in {
4312 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4313 (PSHUFDmi addr:$src1, imm:$imm)>;
4314 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4315 (PSHUFDri VR128:$src1, imm:$imm)>;
4318 //===---------------------------------------------------------------------===//
4319 // Packed Integer Pack Instructions (SSE & AVX)
4320 //===---------------------------------------------------------------------===//
4322 let ExeDomain = SSEPackedInt in {
4323 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4324 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4325 PatFrag ld_frag, bit Is2Addr = 1> {
4326 def rr : PDI<opc, MRMSrcReg,
4327 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4329 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4330 !strconcat(OpcodeStr,
4331 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4333 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4334 Sched<[WriteShuffle]>;
4335 def rm : PDI<opc, MRMSrcMem,
4336 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4338 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4339 !strconcat(OpcodeStr,
4340 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4342 (OutVT (OpNode VR128:$src1,
4343 (bc_frag (ld_frag addr:$src2)))))]>,
4344 Sched<[WriteShuffleLd, ReadAfterLd]>;
4347 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4348 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4349 def Yrr : PDI<opc, MRMSrcReg,
4350 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4351 !strconcat(OpcodeStr,
4352 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4354 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4355 Sched<[WriteShuffle]>;
4356 def Yrm : PDI<opc, MRMSrcMem,
4357 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4358 !strconcat(OpcodeStr,
4359 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4361 (OutVT (OpNode VR256:$src1,
4362 (bc_frag (loadv4i64 addr:$src2)))))]>,
4363 Sched<[WriteShuffleLd, ReadAfterLd]>;
4366 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4367 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4368 PatFrag ld_frag, bit Is2Addr = 1> {
4369 def rr : SS48I<opc, MRMSrcReg,
4370 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4372 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4373 !strconcat(OpcodeStr,
4374 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4376 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4377 Sched<[WriteShuffle]>;
4378 def rm : SS48I<opc, MRMSrcMem,
4379 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4381 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4382 !strconcat(OpcodeStr,
4383 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4385 (OutVT (OpNode VR128:$src1,
4386 (bc_frag (ld_frag addr:$src2)))))]>,
4387 Sched<[WriteShuffleLd, ReadAfterLd]>;
4390 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4391 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4392 def Yrr : SS48I<opc, MRMSrcReg,
4393 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4394 !strconcat(OpcodeStr,
4395 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4397 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4398 Sched<[WriteShuffle]>;
4399 def Yrm : SS48I<opc, MRMSrcMem,
4400 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4401 !strconcat(OpcodeStr,
4402 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4404 (OutVT (OpNode VR256:$src1,
4405 (bc_frag (loadv4i64 addr:$src2)))))]>,
4406 Sched<[WriteShuffleLd, ReadAfterLd]>;
4409 let Predicates = [HasAVX] in {
4410 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4411 bc_v8i16, loadv2i64, 0>, VEX_4V;
4412 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4413 bc_v4i32, loadv2i64, 0>, VEX_4V;
4415 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4416 bc_v8i16, loadv2i64, 0>, VEX_4V;
4417 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4418 bc_v4i32, loadv2i64, 0>, VEX_4V;
4421 let Predicates = [HasAVX2] in {
4422 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4423 bc_v16i16>, VEX_4V, VEX_L;
4424 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4425 bc_v8i32>, VEX_4V, VEX_L;
4427 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4428 bc_v16i16>, VEX_4V, VEX_L;
4429 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4430 bc_v8i32>, VEX_4V, VEX_L;
4433 let Constraints = "$src1 = $dst" in {
4434 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4435 bc_v8i16, memopv2i64>;
4436 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4437 bc_v4i32, memopv2i64>;
4439 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4440 bc_v8i16, memopv2i64>;
4442 let Predicates = [HasSSE41] in
4443 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4444 bc_v4i32, memopv2i64>;
4446 } // ExeDomain = SSEPackedInt
4448 //===---------------------------------------------------------------------===//
4449 // SSE2 - Packed Integer Unpack Instructions
4450 //===---------------------------------------------------------------------===//
4452 let ExeDomain = SSEPackedInt in {
4453 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4454 SDNode OpNode, PatFrag bc_frag, PatFrag ld_frag,
4456 def rr : PDI<opc, MRMSrcReg,
4457 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4459 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4460 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4461 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4462 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4463 def rm : PDI<opc, MRMSrcMem,
4464 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4466 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4467 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4468 [(set VR128:$dst, (OpNode VR128:$src1,
4469 (bc_frag (ld_frag addr:$src2))))],
4471 Sched<[WriteShuffleLd, ReadAfterLd]>;
4474 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4475 SDNode OpNode, PatFrag bc_frag> {
4476 def Yrr : PDI<opc, MRMSrcReg,
4477 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4478 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4479 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4480 Sched<[WriteShuffle]>;
4481 def Yrm : PDI<opc, MRMSrcMem,
4482 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4483 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4484 [(set VR256:$dst, (OpNode VR256:$src1,
4485 (bc_frag (loadv4i64 addr:$src2))))]>,
4486 Sched<[WriteShuffleLd, ReadAfterLd]>;
4489 let Predicates = [HasAVX] in {
4490 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4491 bc_v16i8, loadv2i64, 0>, VEX_4V;
4492 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4493 bc_v8i16, loadv2i64, 0>, VEX_4V;
4494 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4495 bc_v4i32, loadv2i64, 0>, VEX_4V;
4496 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4497 bc_v2i64, loadv2i64, 0>, VEX_4V;
4499 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4500 bc_v16i8, loadv2i64, 0>, VEX_4V;
4501 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4502 bc_v8i16, loadv2i64, 0>, VEX_4V;
4503 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4504 bc_v4i32, loadv2i64, 0>, VEX_4V;
4505 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4506 bc_v2i64, loadv2i64, 0>, VEX_4V;
4509 let Predicates = [HasAVX2] in {
4510 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4511 bc_v32i8>, VEX_4V, VEX_L;
4512 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4513 bc_v16i16>, VEX_4V, VEX_L;
4514 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4515 bc_v8i32>, VEX_4V, VEX_L;
4516 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4517 bc_v4i64>, VEX_4V, VEX_L;
4519 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4520 bc_v32i8>, VEX_4V, VEX_L;
4521 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4522 bc_v16i16>, VEX_4V, VEX_L;
4523 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4524 bc_v8i32>, VEX_4V, VEX_L;
4525 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4526 bc_v4i64>, VEX_4V, VEX_L;
4529 let Constraints = "$src1 = $dst" in {
4530 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4531 bc_v16i8, memopv2i64>;
4532 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4533 bc_v8i16, memopv2i64>;
4534 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4535 bc_v4i32, memopv2i64>;
4536 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4537 bc_v2i64, memopv2i64>;
4539 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4540 bc_v16i8, memopv2i64>;
4541 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4542 bc_v8i16, memopv2i64>;
4543 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4544 bc_v4i32, memopv2i64>;
4545 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4546 bc_v2i64, memopv2i64>;
4548 } // ExeDomain = SSEPackedInt
4550 //===---------------------------------------------------------------------===//
4551 // SSE2 - Packed Integer Extract and Insert
4552 //===---------------------------------------------------------------------===//
4554 let ExeDomain = SSEPackedInt in {
4555 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4556 def rri : Ii8<0xC4, MRMSrcReg,
4557 (outs VR128:$dst), (ins VR128:$src1,
4558 GR32orGR64:$src2, u8imm:$src3),
4560 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4561 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4563 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4564 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4565 def rmi : Ii8<0xC4, MRMSrcMem,
4566 (outs VR128:$dst), (ins VR128:$src1,
4567 i16mem:$src2, u8imm:$src3),
4569 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4570 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4572 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4573 imm:$src3))], IIC_SSE_PINSRW>,
4574 Sched<[WriteShuffleLd, ReadAfterLd]>;
4578 let Predicates = [HasAVX] in
4579 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4580 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4581 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4582 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4583 imm:$src2))]>, PD, VEX,
4584 Sched<[WriteShuffle]>;
4585 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4586 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4587 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4588 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4589 imm:$src2))], IIC_SSE_PEXTRW>,
4590 Sched<[WriteShuffleLd, ReadAfterLd]>;
4593 let Predicates = [HasAVX] in
4594 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4596 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4597 defm PINSRW : sse2_pinsrw, PD;
4599 } // ExeDomain = SSEPackedInt
4601 //===---------------------------------------------------------------------===//
4602 // SSE2 - Packed Mask Creation
4603 //===---------------------------------------------------------------------===//
4605 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4607 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4609 "pmovmskb\t{$src, $dst|$dst, $src}",
4610 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4611 IIC_SSE_MOVMSK>, VEX;
4613 let Predicates = [HasAVX2] in {
4614 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4616 "pmovmskb\t{$src, $dst|$dst, $src}",
4617 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4621 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4622 "pmovmskb\t{$src, $dst|$dst, $src}",
4623 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4626 } // ExeDomain = SSEPackedInt
4628 //===---------------------------------------------------------------------===//
4629 // SSE2 - Conditional Store
4630 //===---------------------------------------------------------------------===//
4632 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4634 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4635 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4636 (ins VR128:$src, VR128:$mask),
4637 "maskmovdqu\t{$mask, $src|$src, $mask}",
4638 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4639 IIC_SSE_MASKMOV>, VEX;
4640 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4641 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4642 (ins VR128:$src, VR128:$mask),
4643 "maskmovdqu\t{$mask, $src|$src, $mask}",
4644 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4645 IIC_SSE_MASKMOV>, VEX;
4647 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4648 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4649 "maskmovdqu\t{$mask, $src|$src, $mask}",
4650 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4652 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4653 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4654 "maskmovdqu\t{$mask, $src|$src, $mask}",
4655 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4658 } // ExeDomain = SSEPackedInt
4660 //===---------------------------------------------------------------------===//
4661 // SSE2 - Move Doubleword
4662 //===---------------------------------------------------------------------===//
4664 //===---------------------------------------------------------------------===//
4665 // Move Int Doubleword to Packed Double Int
4667 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4668 "movd\t{$src, $dst|$dst, $src}",
4670 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4671 VEX, Sched<[WriteMove]>;
4672 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4673 "movd\t{$src, $dst|$dst, $src}",
4675 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4677 VEX, Sched<[WriteLoad]>;
4678 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4679 "movq\t{$src, $dst|$dst, $src}",
4681 (v2i64 (scalar_to_vector GR64:$src)))],
4682 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4683 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4684 def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4685 "movq\t{$src, $dst|$dst, $src}",
4686 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteLoad]>;
4687 let isCodeGenOnly = 1 in
4688 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4689 "movq\t{$src, $dst|$dst, $src}",
4690 [(set FR64:$dst, (bitconvert GR64:$src))],
4691 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4693 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4694 "movd\t{$src, $dst|$dst, $src}",
4696 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4698 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4699 "movd\t{$src, $dst|$dst, $src}",
4701 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4702 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4703 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4704 "mov{d|q}\t{$src, $dst|$dst, $src}",
4706 (v2i64 (scalar_to_vector GR64:$src)))],
4707 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4708 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4709 def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4710 "mov{d|q}\t{$src, $dst|$dst, $src}",
4711 [], IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4712 let isCodeGenOnly = 1 in
4713 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4714 "mov{d|q}\t{$src, $dst|$dst, $src}",
4715 [(set FR64:$dst, (bitconvert GR64:$src))],
4716 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4718 //===---------------------------------------------------------------------===//
4719 // Move Int Doubleword to Single Scalar
4721 let isCodeGenOnly = 1 in {
4722 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4723 "movd\t{$src, $dst|$dst, $src}",
4724 [(set FR32:$dst, (bitconvert GR32:$src))],
4725 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4727 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4728 "movd\t{$src, $dst|$dst, $src}",
4729 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4731 VEX, Sched<[WriteLoad]>;
4732 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4733 "movd\t{$src, $dst|$dst, $src}",
4734 [(set FR32:$dst, (bitconvert GR32:$src))],
4735 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4737 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4738 "movd\t{$src, $dst|$dst, $src}",
4739 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4740 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4743 //===---------------------------------------------------------------------===//
4744 // Move Packed Doubleword Int to Packed Double Int
4746 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4747 "movd\t{$src, $dst|$dst, $src}",
4748 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4749 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4751 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4752 (ins i32mem:$dst, VR128:$src),
4753 "movd\t{$src, $dst|$dst, $src}",
4754 [(store (i32 (vector_extract (v4i32 VR128:$src),
4755 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4756 VEX, Sched<[WriteStore]>;
4757 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4758 "movd\t{$src, $dst|$dst, $src}",
4759 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4760 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4762 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4763 "movd\t{$src, $dst|$dst, $src}",
4764 [(store (i32 (vector_extract (v4i32 VR128:$src),
4765 (iPTR 0))), addr:$dst)],
4766 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4768 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4769 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4771 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4772 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4774 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4775 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4777 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4778 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4780 //===---------------------------------------------------------------------===//
4781 // Move Packed Doubleword Int first element to Doubleword Int
4783 let SchedRW = [WriteMove] in {
4784 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4785 "movq\t{$src, $dst|$dst, $src}",
4786 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4791 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4792 "mov{d|q}\t{$src, $dst|$dst, $src}",
4793 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4798 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4799 def VMOVPQIto64rm : VRS2I<0x7E, MRMDestMem, (outs i64mem:$dst),
4800 (ins VR128:$src), "movq\t{$src, $dst|$dst, $src}",
4801 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4802 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4803 def MOVPQIto64rm : RS2I<0x7E, MRMDestMem, (outs i64mem:$dst), (ins VR128:$src),
4804 "mov{d|q}\t{$src, $dst|$dst, $src}",
4805 [], IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4807 //===---------------------------------------------------------------------===//
4808 // Bitcast FR64 <-> GR64
4810 let isCodeGenOnly = 1 in {
4811 let Predicates = [UseAVX] in
4812 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4813 "movq\t{$src, $dst|$dst, $src}",
4814 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4815 VEX, Sched<[WriteLoad]>;
4816 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4817 "movq\t{$src, $dst|$dst, $src}",
4818 [(set GR64:$dst, (bitconvert FR64:$src))],
4819 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4820 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4821 "movq\t{$src, $dst|$dst, $src}",
4822 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4823 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4825 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4826 "movq\t{$src, $dst|$dst, $src}",
4827 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4828 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4829 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4830 "mov{d|q}\t{$src, $dst|$dst, $src}",
4831 [(set GR64:$dst, (bitconvert FR64:$src))],
4832 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4833 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4834 "movq\t{$src, $dst|$dst, $src}",
4835 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4836 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4839 //===---------------------------------------------------------------------===//
4840 // Move Scalar Single to Double Int
4842 let isCodeGenOnly = 1 in {
4843 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4844 "movd\t{$src, $dst|$dst, $src}",
4845 [(set GR32:$dst, (bitconvert FR32:$src))],
4846 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4847 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4848 "movd\t{$src, $dst|$dst, $src}",
4849 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4850 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4851 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4852 "movd\t{$src, $dst|$dst, $src}",
4853 [(set GR32:$dst, (bitconvert FR32:$src))],
4854 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4855 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4856 "movd\t{$src, $dst|$dst, $src}",
4857 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4858 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4861 //===---------------------------------------------------------------------===//
4862 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4864 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4865 let AddedComplexity = 15 in {
4866 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4867 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4868 [(set VR128:$dst, (v2i64 (X86vzmovl
4869 (v2i64 (scalar_to_vector GR64:$src)))))],
4872 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4873 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4874 [(set VR128:$dst, (v2i64 (X86vzmovl
4875 (v2i64 (scalar_to_vector GR64:$src)))))],
4878 } // isCodeGenOnly, SchedRW
4880 let Predicates = [UseAVX] in {
4881 let AddedComplexity = 15 in
4882 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4883 (VMOVDI2PDIrr GR32:$src)>;
4885 // AVX 128-bit movd/movq instructions write zeros in the high 128-bit part.
4886 // These instructions also write zeros in the high part of a 256-bit register.
4887 let AddedComplexity = 20 in {
4888 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4889 (VMOVDI2PDIrm addr:$src)>;
4890 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4891 (VMOVDI2PDIrm addr:$src)>;
4892 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4893 (VMOVDI2PDIrm addr:$src)>;
4894 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4895 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
4896 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrm addr:$src), sub_xmm)>;
4898 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4899 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4900 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4901 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4902 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4903 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4904 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4907 let Predicates = [UseSSE2] in {
4908 let AddedComplexity = 15 in
4909 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4910 (MOVDI2PDIrr GR32:$src)>;
4912 let AddedComplexity = 20 in {
4913 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4914 (MOVDI2PDIrm addr:$src)>;
4915 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4916 (MOVDI2PDIrm addr:$src)>;
4917 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4918 (MOVDI2PDIrm addr:$src)>;
4922 // These are the correct encodings of the instructions so that we know how to
4923 // read correct assembly, even though we continue to emit the wrong ones for
4924 // compatibility with Darwin's buggy assembler.
4925 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4926 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4927 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4928 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4929 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4930 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4931 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4932 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4933 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4935 //===---------------------------------------------------------------------===//
4936 // SSE2 - Move Quadword
4937 //===---------------------------------------------------------------------===//
4939 //===---------------------------------------------------------------------===//
4940 // Move Quadword Int to Packed Quadword Int
4943 let ExeDomain = SSEPackedInt, SchedRW = [WriteLoad] in {
4944 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4945 "vmovq\t{$src, $dst|$dst, $src}",
4947 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4948 VEX, Requires<[UseAVX]>;
4949 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4950 "movq\t{$src, $dst|$dst, $src}",
4952 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4954 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4955 } // ExeDomain, SchedRW
4957 //===---------------------------------------------------------------------===//
4958 // Move Packed Quadword Int to Quadword Int
4960 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4961 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4962 "movq\t{$src, $dst|$dst, $src}",
4963 [(store (i64 (vector_extract (v2i64 VR128:$src),
4964 (iPTR 0))), addr:$dst)],
4965 IIC_SSE_MOVDQ>, VEX;
4966 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4967 "movq\t{$src, $dst|$dst, $src}",
4968 [(store (i64 (vector_extract (v2i64 VR128:$src),
4969 (iPTR 0))), addr:$dst)],
4971 } // ExeDomain, SchedRW
4973 // For disassembler only
4974 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4975 SchedRW = [WriteVecLogic] in {
4976 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4977 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
4978 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4979 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
4982 //===---------------------------------------------------------------------===//
4983 // Store / copy lower 64-bits of a XMM register.
4985 let Predicates = [HasAVX] in
4986 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
4987 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
4988 let Predicates = [UseSSE2] in
4989 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
4990 (MOVPQI2QImr addr:$dst, VR128:$src)>;
4992 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, AddedComplexity = 20 in {
4993 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4994 "vmovq\t{$src, $dst|$dst, $src}",
4996 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4997 (loadi64 addr:$src))))))],
4999 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5001 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5002 "movq\t{$src, $dst|$dst, $src}",
5004 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5005 (loadi64 addr:$src))))))],
5007 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5008 } // ExeDomain, isCodeGenOnly, AddedComplexity
5010 let Predicates = [UseAVX], AddedComplexity = 20 in {
5011 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5012 (VMOVZQI2PQIrm addr:$src)>;
5013 def : Pat<(v2i64 (X86vzload addr:$src)),
5014 (VMOVZQI2PQIrm addr:$src)>;
5015 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5016 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
5017 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
5020 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5021 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5022 (MOVZQI2PQIrm addr:$src)>;
5023 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5026 let Predicates = [HasAVX] in {
5027 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5028 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5029 def : Pat<(v4i64 (X86vzload addr:$src)),
5030 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5033 //===---------------------------------------------------------------------===//
5034 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5035 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5037 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
5038 let AddedComplexity = 15 in
5039 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5040 "vmovq\t{$src, $dst|$dst, $src}",
5041 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5043 XS, VEX, Requires<[UseAVX]>;
5044 let AddedComplexity = 15 in
5045 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5046 "movq\t{$src, $dst|$dst, $src}",
5047 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5049 XS, Requires<[UseSSE2]>;
5050 } // ExeDomain, SchedRW
5052 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5053 let AddedComplexity = 20 in
5054 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5055 "vmovq\t{$src, $dst|$dst, $src}",
5056 [(set VR128:$dst, (v2i64 (X86vzmovl
5057 (loadv2i64 addr:$src))))],
5059 XS, VEX, Requires<[UseAVX]>;
5060 let AddedComplexity = 20 in {
5061 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5062 "movq\t{$src, $dst|$dst, $src}",
5063 [(set VR128:$dst, (v2i64 (X86vzmovl
5064 (loadv2i64 addr:$src))))],
5066 XS, Requires<[UseSSE2]>;
5068 } // ExeDomain, isCodeGenOnly, SchedRW
5070 let AddedComplexity = 20 in {
5071 let Predicates = [UseAVX] in {
5072 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5073 (VMOVZPQILo2PQIrr VR128:$src)>;
5075 let Predicates = [UseSSE2] in {
5076 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5077 (MOVZPQILo2PQIrr VR128:$src)>;
5081 //===---------------------------------------------------------------------===//
5082 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5083 //===---------------------------------------------------------------------===//
5084 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5085 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5086 X86MemOperand x86memop> {
5087 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5088 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5089 [(set RC:$dst, (vt (OpNode RC:$src)))],
5090 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5091 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5092 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5093 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5094 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5097 let Predicates = [HasAVX] in {
5098 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5099 v4f32, VR128, loadv4f32, f128mem>, VEX;
5100 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5101 v4f32, VR128, loadv4f32, f128mem>, VEX;
5102 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5103 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5104 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5105 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5107 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5108 memopv4f32, f128mem>;
5109 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5110 memopv4f32, f128mem>;
5112 let Predicates = [HasAVX] in {
5113 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5114 (VMOVSHDUPrr VR128:$src)>;
5115 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5116 (VMOVSHDUPrm addr:$src)>;
5117 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5118 (VMOVSLDUPrr VR128:$src)>;
5119 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5120 (VMOVSLDUPrm addr:$src)>;
5121 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5122 (VMOVSHDUPYrr VR256:$src)>;
5123 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5124 (VMOVSHDUPYrm addr:$src)>;
5125 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5126 (VMOVSLDUPYrr VR256:$src)>;
5127 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5128 (VMOVSLDUPYrm addr:$src)>;
5131 let Predicates = [UseSSE3] in {
5132 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5133 (MOVSHDUPrr VR128:$src)>;
5134 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5135 (MOVSHDUPrm addr:$src)>;
5136 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5137 (MOVSLDUPrr VR128:$src)>;
5138 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5139 (MOVSLDUPrm addr:$src)>;
5142 //===---------------------------------------------------------------------===//
5143 // SSE3 - Replicate Double FP - MOVDDUP
5144 //===---------------------------------------------------------------------===//
5146 multiclass sse3_replicate_dfp<string OpcodeStr> {
5147 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5148 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5149 [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))],
5150 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5151 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5152 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5155 (scalar_to_vector (loadf64 addr:$src)))))],
5156 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5159 // FIXME: Merge with above classe when there're patterns for the ymm version
5160 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5161 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5162 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5163 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5164 Sched<[WriteFShuffle]>;
5165 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5166 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5169 (scalar_to_vector (loadf64 addr:$src)))))]>,
5173 let Predicates = [HasAVX] in {
5174 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5175 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5178 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5180 let Predicates = [HasAVX] in {
5181 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5182 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5183 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5184 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5185 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5186 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5187 def : Pat<(X86Movddup (bc_v2f64
5188 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5189 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5192 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5193 (VMOVDDUPYrm addr:$src)>;
5194 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5195 (VMOVDDUPYrm addr:$src)>;
5196 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5197 (VMOVDDUPYrm addr:$src)>;
5198 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5199 (VMOVDDUPYrr VR256:$src)>;
5202 let Predicates = [UseAVX, OptForSize] in {
5203 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5204 (VMOVDDUPrm addr:$src)>;
5205 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5206 (VMOVDDUPrm addr:$src)>;
5209 let Predicates = [UseSSE3] in {
5210 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5211 (MOVDDUPrm addr:$src)>;
5212 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5213 (MOVDDUPrm addr:$src)>;
5214 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5215 (MOVDDUPrm addr:$src)>;
5216 def : Pat<(X86Movddup (bc_v2f64
5217 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5218 (MOVDDUPrm addr:$src)>;
5221 //===---------------------------------------------------------------------===//
5222 // SSE3 - Move Unaligned Integer
5223 //===---------------------------------------------------------------------===//
5225 let SchedRW = [WriteLoad] in {
5226 let Predicates = [HasAVX] in {
5227 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5228 "vlddqu\t{$src, $dst|$dst, $src}",
5229 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5230 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5231 "vlddqu\t{$src, $dst|$dst, $src}",
5232 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5235 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5236 "lddqu\t{$src, $dst|$dst, $src}",
5237 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5241 //===---------------------------------------------------------------------===//
5242 // SSE3 - Arithmetic
5243 //===---------------------------------------------------------------------===//
5245 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5246 X86MemOperand x86memop, OpndItins itins,
5247 PatFrag ld_frag, bit Is2Addr = 1> {
5248 def rr : I<0xD0, MRMSrcReg,
5249 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5251 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5252 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5253 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5254 Sched<[itins.Sched]>;
5255 def rm : I<0xD0, MRMSrcMem,
5256 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5258 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5259 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5260 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))], itins.rr>,
5261 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5264 let Predicates = [HasAVX] in {
5265 let ExeDomain = SSEPackedSingle in {
5266 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5267 f128mem, SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V;
5268 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5269 f256mem, SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V, VEX_L;
5271 let ExeDomain = SSEPackedDouble in {
5272 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5273 f128mem, SSE_ALU_F64P, loadv2f64, 0>, PD, VEX_4V;
5274 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5275 f256mem, SSE_ALU_F64P, loadv4f64, 0>, PD, VEX_4V, VEX_L;
5278 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5279 let ExeDomain = SSEPackedSingle in
5280 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5281 f128mem, SSE_ALU_F32P, memopv4f32>, XD;
5282 let ExeDomain = SSEPackedDouble in
5283 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5284 f128mem, SSE_ALU_F64P, memopv2f64>, PD;
5287 // Patterns used to select 'addsub' instructions.
5288 let Predicates = [HasAVX] in {
5289 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5290 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5291 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (loadv4f32 addr:$rhs))),
5292 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5293 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5294 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5295 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (loadv2f64 addr:$rhs))),
5296 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5298 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5299 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5300 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (loadv8f32 addr:$rhs))),
5301 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5302 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5303 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5304 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (loadv4f64 addr:$rhs))),
5305 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5308 let Predicates = [UseSSE3] in {
5309 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5310 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5311 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (memopv4f32 addr:$rhs))),
5312 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5313 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5314 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5315 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (memopv2f64 addr:$rhs))),
5316 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5319 //===---------------------------------------------------------------------===//
5320 // SSE3 Instructions
5321 //===---------------------------------------------------------------------===//
5324 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5325 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5327 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5329 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5330 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5331 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5334 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5336 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5337 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5338 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5339 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5341 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5342 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5344 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5347 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5348 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5351 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5353 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5354 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5355 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5356 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5359 let Predicates = [HasAVX] in {
5360 let ExeDomain = SSEPackedSingle in {
5361 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5362 X86fhadd, loadv4f32, 0>, VEX_4V;
5363 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5364 X86fhsub, loadv4f32, 0>, VEX_4V;
5365 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5366 X86fhadd, loadv8f32, 0>, VEX_4V, VEX_L;
5367 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5368 X86fhsub, loadv8f32, 0>, VEX_4V, VEX_L;
5370 let ExeDomain = SSEPackedDouble in {
5371 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5372 X86fhadd, loadv2f64, 0>, VEX_4V;
5373 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5374 X86fhsub, loadv2f64, 0>, VEX_4V;
5375 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5376 X86fhadd, loadv4f64, 0>, VEX_4V, VEX_L;
5377 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5378 X86fhsub, loadv4f64, 0>, VEX_4V, VEX_L;
5382 let Constraints = "$src1 = $dst" in {
5383 let ExeDomain = SSEPackedSingle in {
5384 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd,
5386 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub,
5389 let ExeDomain = SSEPackedDouble in {
5390 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd,
5392 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub,
5397 //===---------------------------------------------------------------------===//
5398 // SSSE3 - Packed Absolute Instructions
5399 //===---------------------------------------------------------------------===//
5402 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5403 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
5405 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5407 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5408 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5409 Sched<[WriteVecALU]>;
5411 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5413 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5416 (bitconvert (ld_frag addr:$src))))], IIC_SSE_PABS_RM>,
5417 Sched<[WriteVecALULd]>;
5420 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5421 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5422 Intrinsic IntId256> {
5423 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5425 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5426 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5427 Sched<[WriteVecALU]>;
5429 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5431 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5434 (bitconvert (loadv4i64 addr:$src))))]>,
5435 Sched<[WriteVecALULd]>;
5438 // Helper fragments to match sext vXi1 to vXiY.
5439 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5441 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5442 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5443 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5445 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5446 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5448 let Predicates = [HasAVX] in {
5449 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", int_x86_ssse3_pabs_b_128,
5451 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", int_x86_ssse3_pabs_w_128,
5453 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", int_x86_ssse3_pabs_d_128,
5457 (bc_v2i64 (v16i1sextv16i8)),
5458 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5459 (VPABSBrr128 VR128:$src)>;
5461 (bc_v2i64 (v8i1sextv8i16)),
5462 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5463 (VPABSWrr128 VR128:$src)>;
5465 (bc_v2i64 (v4i1sextv4i32)),
5466 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5467 (VPABSDrr128 VR128:$src)>;
5470 let Predicates = [HasAVX2] in {
5471 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5472 int_x86_avx2_pabs_b>, VEX, VEX_L;
5473 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5474 int_x86_avx2_pabs_w>, VEX, VEX_L;
5475 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5476 int_x86_avx2_pabs_d>, VEX, VEX_L;
5479 (bc_v4i64 (v32i1sextv32i8)),
5480 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5481 (VPABSBrr256 VR256:$src)>;
5483 (bc_v4i64 (v16i1sextv16i16)),
5484 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5485 (VPABSWrr256 VR256:$src)>;
5487 (bc_v4i64 (v8i1sextv8i32)),
5488 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5489 (VPABSDrr256 VR256:$src)>;
5492 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", int_x86_ssse3_pabs_b_128,
5494 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", int_x86_ssse3_pabs_w_128,
5496 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", int_x86_ssse3_pabs_d_128,
5499 let Predicates = [HasSSSE3] in {
5501 (bc_v2i64 (v16i1sextv16i8)),
5502 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5503 (PABSBrr128 VR128:$src)>;
5505 (bc_v2i64 (v8i1sextv8i16)),
5506 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5507 (PABSWrr128 VR128:$src)>;
5509 (bc_v2i64 (v4i1sextv4i32)),
5510 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5511 (PABSDrr128 VR128:$src)>;
5514 //===---------------------------------------------------------------------===//
5515 // SSSE3 - Packed Binary Operator Instructions
5516 //===---------------------------------------------------------------------===//
5518 let Sched = WriteVecALU in {
5519 def SSE_PHADDSUBD : OpndItins<
5520 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5522 def SSE_PHADDSUBSW : OpndItins<
5523 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5525 def SSE_PHADDSUBW : OpndItins<
5526 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5529 let Sched = WriteShuffle in
5530 def SSE_PSHUFB : OpndItins<
5531 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5533 let Sched = WriteVecALU in
5534 def SSE_PSIGN : OpndItins<
5535 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5537 let Sched = WriteVecIMul in
5538 def SSE_PMULHRSW : OpndItins<
5539 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5542 /// SS3I_binop_rm - Simple SSSE3 bin op
5543 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5544 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5545 X86MemOperand x86memop, OpndItins itins,
5547 let isCommutable = 1 in
5548 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5549 (ins RC:$src1, RC:$src2),
5551 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5552 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5553 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5554 Sched<[itins.Sched]>;
5555 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5556 (ins RC:$src1, x86memop:$src2),
5558 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5559 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5561 (OpVT (OpNode RC:$src1,
5562 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5563 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5566 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5567 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5568 Intrinsic IntId128, OpndItins itins,
5569 PatFrag ld_frag, bit Is2Addr = 1> {
5570 let isCommutable = 1 in
5571 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5572 (ins VR128:$src1, VR128:$src2),
5574 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5575 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5576 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5577 Sched<[itins.Sched]>;
5578 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5579 (ins VR128:$src1, i128mem:$src2),
5581 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5582 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5584 (IntId128 VR128:$src1,
5585 (bitconvert (ld_frag addr:$src2))))]>,
5586 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5589 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5591 X86FoldableSchedWrite Sched> {
5592 let isCommutable = 1 in
5593 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5594 (ins VR256:$src1, VR256:$src2),
5595 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5596 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5598 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5599 (ins VR256:$src1, i256mem:$src2),
5600 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5602 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5603 Sched<[Sched.Folded, ReadAfterLd]>;
5606 let ImmT = NoImm, Predicates = [HasAVX] in {
5607 let isCommutable = 0 in {
5608 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5610 SSE_PHADDSUBW, 0>, VEX_4V;
5611 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5613 SSE_PHADDSUBD, 0>, VEX_4V;
5614 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5616 SSE_PHADDSUBW, 0>, VEX_4V;
5617 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5619 SSE_PHADDSUBD, 0>, VEX_4V;
5620 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5622 SSE_PSIGN, 0>, VEX_4V;
5623 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5625 SSE_PSIGN, 0>, VEX_4V;
5626 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5628 SSE_PSIGN, 0>, VEX_4V;
5629 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5631 SSE_PSHUFB, 0>, VEX_4V;
5632 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5633 int_x86_ssse3_phadd_sw_128,
5634 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5635 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5636 int_x86_ssse3_phsub_sw_128,
5637 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5638 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5639 int_x86_ssse3_pmadd_ub_sw_128,
5640 SSE_PMADD, loadv2i64, 0>, VEX_4V;
5642 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5643 int_x86_ssse3_pmul_hr_sw_128,
5644 SSE_PMULHRSW, loadv2i64, 0>, VEX_4V;
5647 let ImmT = NoImm, Predicates = [HasAVX2] in {
5648 let isCommutable = 0 in {
5649 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5651 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5652 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5654 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5655 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5657 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5658 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5660 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5661 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5663 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5664 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5666 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5667 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5669 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5670 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5672 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5673 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5674 int_x86_avx2_phadd_sw,
5675 WriteVecALU>, VEX_4V, VEX_L;
5676 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5677 int_x86_avx2_phsub_sw,
5678 WriteVecALU>, VEX_4V, VEX_L;
5679 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5680 int_x86_avx2_pmadd_ub_sw,
5681 WriteVecIMul>, VEX_4V, VEX_L;
5683 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5684 int_x86_avx2_pmul_hr_sw,
5685 WriteVecIMul>, VEX_4V, VEX_L;
5688 // None of these have i8 immediate fields.
5689 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5690 let isCommutable = 0 in {
5691 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5692 memopv2i64, i128mem, SSE_PHADDSUBW>;
5693 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5694 memopv2i64, i128mem, SSE_PHADDSUBD>;
5695 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5696 memopv2i64, i128mem, SSE_PHADDSUBW>;
5697 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5698 memopv2i64, i128mem, SSE_PHADDSUBD>;
5699 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5700 memopv2i64, i128mem, SSE_PSIGN>;
5701 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5702 memopv2i64, i128mem, SSE_PSIGN>;
5703 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5704 memopv2i64, i128mem, SSE_PSIGN>;
5705 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5706 memopv2i64, i128mem, SSE_PSHUFB>;
5707 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5708 int_x86_ssse3_phadd_sw_128,
5709 SSE_PHADDSUBSW, memopv2i64>;
5710 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5711 int_x86_ssse3_phsub_sw_128,
5712 SSE_PHADDSUBSW, memopv2i64>;
5713 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5714 int_x86_ssse3_pmadd_ub_sw_128,
5715 SSE_PMADD, memopv2i64>;
5717 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5718 int_x86_ssse3_pmul_hr_sw_128,
5719 SSE_PMULHRSW, memopv2i64>;
5722 //===---------------------------------------------------------------------===//
5723 // SSSE3 - Packed Align Instruction Patterns
5724 //===---------------------------------------------------------------------===//
5726 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5727 let hasSideEffects = 0 in {
5728 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5729 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
5731 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5733 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5734 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5736 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5737 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
5739 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5741 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5742 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5746 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5747 let hasSideEffects = 0 in {
5748 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5749 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
5751 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5752 []>, Sched<[WriteShuffle]>;
5754 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5755 (ins VR256:$src1, i256mem:$src2, u8imm:$src3),
5757 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5758 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5762 let Predicates = [HasAVX] in
5763 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5764 let Predicates = [HasAVX2] in
5765 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5766 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5767 defm PALIGN : ssse3_palignr<"palignr">;
5769 let Predicates = [HasAVX2] in {
5770 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5771 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5772 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5773 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5774 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5775 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5776 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5777 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5780 let Predicates = [HasAVX] in {
5781 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5782 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5783 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5784 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5785 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5786 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5787 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5788 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5791 let Predicates = [UseSSSE3] in {
5792 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5793 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5794 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5795 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5796 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5797 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5798 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5799 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5802 //===---------------------------------------------------------------------===//
5803 // SSSE3 - Thread synchronization
5804 //===---------------------------------------------------------------------===//
5806 let SchedRW = [WriteSystem] in {
5807 let usesCustomInserter = 1 in {
5808 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5809 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5810 Requires<[HasSSE3]>;
5813 let Uses = [EAX, ECX, EDX] in
5814 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5815 TB, Requires<[HasSSE3]>;
5816 let Uses = [ECX, EAX] in
5817 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5818 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5819 TB, Requires<[HasSSE3]>;
5822 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5823 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5825 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5826 Requires<[Not64BitMode]>;
5827 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5828 Requires<[In64BitMode]>;
5830 //===----------------------------------------------------------------------===//
5831 // SSE4.1 - Packed Move with Sign/Zero Extend
5832 //===----------------------------------------------------------------------===//
5834 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
5835 RegisterClass OutRC, RegisterClass InRC,
5837 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
5838 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5840 Sched<[itins.Sched]>;
5842 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
5843 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5845 itins.rm>, Sched<[itins.Sched.Folded]>;
5848 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
5849 X86MemOperand MemOp, X86MemOperand MemYOp,
5850 OpndItins SSEItins, OpndItins AVXItins,
5851 OpndItins AVX2Itins> {
5852 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
5853 let Predicates = [HasAVX] in
5854 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
5855 VR128, VR128, AVXItins>, VEX;
5856 let Predicates = [HasAVX2] in
5857 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
5858 VR256, VR128, AVX2Itins>, VEX, VEX_L;
5861 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
5862 X86MemOperand MemOp, X86MemOperand MemYOp> {
5863 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
5865 SSE_INTALU_ITINS_SHUFF_P,
5866 DEFAULT_ITINS_SHUFFLESCHED,
5867 DEFAULT_ITINS_SHUFFLESCHED>;
5868 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
5869 !strconcat("pmovzx", OpcodeStr),
5871 SSE_INTALU_ITINS_SHUFF_P,
5872 DEFAULT_ITINS_SHUFFLESCHED,
5873 DEFAULT_ITINS_SHUFFLESCHED>;
5876 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
5877 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
5878 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
5880 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
5881 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
5883 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
5886 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
5887 // Register-Register patterns
5888 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5889 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
5890 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
5891 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
5892 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
5893 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
5895 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5896 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
5897 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
5898 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
5900 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5901 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
5903 // On AVX2, we also support 256bit inputs.
5904 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
5905 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5906 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
5907 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5908 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
5909 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5911 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
5912 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5913 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
5914 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5916 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
5917 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5919 // Simple Register-Memory patterns
5920 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5921 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5922 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5923 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5924 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5925 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5927 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5928 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5929 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5930 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5932 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5933 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5935 // AVX2 Register-Memory patterns
5936 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5937 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5938 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5939 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5940 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5941 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5942 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5943 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5945 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5946 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5947 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5948 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5949 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5950 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5951 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5952 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5954 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
5955 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5956 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
5957 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5958 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5959 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5960 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5961 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5963 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5964 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5965 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5966 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5967 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5968 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5969 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5970 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5972 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5973 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5974 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5975 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5976 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5977 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5978 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5979 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5981 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
5982 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5983 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
5984 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5985 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
5986 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5987 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
5988 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5991 let Predicates = [HasAVX2] in {
5992 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
5993 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
5996 // SSE4.1/AVX patterns.
5997 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
5998 SDNode ExtOp, PatFrag ExtLoad16> {
5999 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6000 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6001 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6002 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6003 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6004 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6006 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6007 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6008 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6009 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6011 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6012 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6014 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6015 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6016 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6017 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6018 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6019 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6021 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6022 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6023 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6024 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6026 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6027 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6029 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6030 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6031 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6032 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6033 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6034 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6035 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6036 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6037 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6038 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6040 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6041 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6042 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6043 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6044 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6045 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6046 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6047 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6049 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6050 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6051 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6052 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6053 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6054 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6055 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6056 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6058 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6059 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6060 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6061 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6062 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6063 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6064 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6065 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6066 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6067 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6069 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6070 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6071 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6072 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6073 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6074 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6075 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6076 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6078 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6079 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6080 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6081 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6082 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6083 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6084 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6085 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6086 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6087 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6090 let Predicates = [HasAVX] in {
6091 defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
6092 defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
6095 let Predicates = [UseSSE41] in {
6096 defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
6097 defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
6100 //===----------------------------------------------------------------------===//
6101 // SSE4.1 - Extract Instructions
6102 //===----------------------------------------------------------------------===//
6104 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6105 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6106 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6107 (ins VR128:$src1, u8imm:$src2),
6108 !strconcat(OpcodeStr,
6109 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6110 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6112 Sched<[WriteShuffle]>;
6113 let hasSideEffects = 0, mayStore = 1,
6114 SchedRW = [WriteShuffleLd, WriteRMW] in
6115 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6116 (ins i8mem:$dst, VR128:$src1, u8imm:$src2),
6117 !strconcat(OpcodeStr,
6118 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6119 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6120 imm:$src2)))), addr:$dst)]>;
6123 let Predicates = [HasAVX] in
6124 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6126 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6129 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6130 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6131 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6132 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6133 (ins VR128:$src1, u8imm:$src2),
6134 !strconcat(OpcodeStr,
6135 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6136 []>, Sched<[WriteShuffle]>;
6138 let hasSideEffects = 0, mayStore = 1,
6139 SchedRW = [WriteShuffleLd, WriteRMW] in
6140 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6141 (ins i16mem:$dst, VR128:$src1, u8imm:$src2),
6142 !strconcat(OpcodeStr,
6143 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6144 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6145 imm:$src2)))), addr:$dst)]>;
6148 let Predicates = [HasAVX] in
6149 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6151 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6154 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6155 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6156 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6157 (ins VR128:$src1, u8imm:$src2),
6158 !strconcat(OpcodeStr,
6159 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6161 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6162 Sched<[WriteShuffle]>;
6163 let SchedRW = [WriteShuffleLd, WriteRMW] in
6164 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6165 (ins i32mem:$dst, VR128:$src1, u8imm:$src2),
6166 !strconcat(OpcodeStr,
6167 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6168 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6172 let Predicates = [HasAVX] in
6173 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6175 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6177 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6178 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6179 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6180 (ins VR128:$src1, u8imm:$src2),
6181 !strconcat(OpcodeStr,
6182 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6184 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6185 Sched<[WriteShuffle]>, REX_W;
6186 let SchedRW = [WriteShuffleLd, WriteRMW] in
6187 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6188 (ins i64mem:$dst, VR128:$src1, u8imm:$src2),
6189 !strconcat(OpcodeStr,
6190 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6191 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6192 addr:$dst)]>, REX_W;
6195 let Predicates = [HasAVX] in
6196 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6198 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6200 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6202 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6203 OpndItins itins = DEFAULT_ITINS> {
6204 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6205 (ins VR128:$src1, u8imm:$src2),
6206 !strconcat(OpcodeStr,
6207 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6208 [(set GR32orGR64:$dst,
6209 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6210 itins.rr>, Sched<[WriteFBlend]>;
6211 let SchedRW = [WriteFBlendLd, WriteRMW] in
6212 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6213 (ins f32mem:$dst, VR128:$src1, u8imm:$src2),
6214 !strconcat(OpcodeStr,
6215 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6216 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6217 addr:$dst)], itins.rm>;
6220 let ExeDomain = SSEPackedSingle in {
6221 let Predicates = [UseAVX] in
6222 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6223 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6226 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6227 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6230 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6232 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6235 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6236 Requires<[UseSSE41]>;
6238 //===----------------------------------------------------------------------===//
6239 // SSE4.1 - Insert Instructions
6240 //===----------------------------------------------------------------------===//
6242 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6243 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6244 (ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
6246 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6248 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6250 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6251 Sched<[WriteShuffle]>;
6252 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6253 (ins VR128:$src1, i8mem:$src2, u8imm:$src3),
6255 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6257 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6259 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6260 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6263 let Predicates = [HasAVX] in
6264 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6265 let Constraints = "$src1 = $dst" in
6266 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6268 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6269 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6270 (ins VR128:$src1, GR32:$src2, u8imm:$src3),
6272 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6274 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6276 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6277 Sched<[WriteShuffle]>;
6278 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6279 (ins VR128:$src1, i32mem:$src2, u8imm:$src3),
6281 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6283 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6285 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6286 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6289 let Predicates = [HasAVX] in
6290 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6291 let Constraints = "$src1 = $dst" in
6292 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6294 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6295 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6296 (ins VR128:$src1, GR64:$src2, u8imm:$src3),
6298 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6300 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6302 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6303 Sched<[WriteShuffle]>;
6304 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6305 (ins VR128:$src1, i64mem:$src2, u8imm:$src3),
6307 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6309 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6311 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6312 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6315 let Predicates = [HasAVX] in
6316 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6317 let Constraints = "$src1 = $dst" in
6318 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6320 // insertps has a few different modes, there's the first two here below which
6321 // are optimized inserts that won't zero arbitrary elements in the destination
6322 // vector. The next one matches the intrinsic and could zero arbitrary elements
6323 // in the target vector.
6324 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6325 OpndItins itins = DEFAULT_ITINS> {
6326 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6327 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
6329 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6331 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6333 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6334 Sched<[WriteFShuffle]>;
6335 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6336 (ins VR128:$src1, f32mem:$src2, u8imm:$src3),
6338 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6340 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6342 (X86insertps VR128:$src1,
6343 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6344 imm:$src3))], itins.rm>,
6345 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6348 let ExeDomain = SSEPackedSingle in {
6349 let Predicates = [UseAVX] in
6350 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6351 let Constraints = "$src1 = $dst" in
6352 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6355 let Predicates = [UseSSE41] in {
6356 // If we're inserting an element from a load or a null pshuf of a load,
6357 // fold the load into the insertps instruction.
6358 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6359 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6361 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6362 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6363 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6364 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6367 let Predicates = [UseAVX] in {
6368 // If we're inserting an element from a vbroadcast of a load, fold the
6369 // load into the X86insertps instruction.
6370 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6371 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6372 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6373 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6374 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6375 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6378 //===----------------------------------------------------------------------===//
6379 // SSE4.1 - Round Instructions
6380 //===----------------------------------------------------------------------===//
6382 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6383 X86MemOperand x86memop, RegisterClass RC,
6384 PatFrag mem_frag32, PatFrag mem_frag64,
6385 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6386 let ExeDomain = SSEPackedSingle in {
6387 // Intrinsic operation, reg.
6388 // Vector intrinsic operation, reg
6389 def PSr : SS4AIi8<opcps, MRMSrcReg,
6390 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6391 !strconcat(OpcodeStr,
6392 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6393 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6394 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6396 // Vector intrinsic operation, mem
6397 def PSm : SS4AIi8<opcps, MRMSrcMem,
6398 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6399 !strconcat(OpcodeStr,
6400 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6402 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6403 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6404 } // ExeDomain = SSEPackedSingle
6406 let ExeDomain = SSEPackedDouble in {
6407 // Vector intrinsic operation, reg
6408 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6409 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6410 !strconcat(OpcodeStr,
6411 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6412 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6413 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6415 // Vector intrinsic operation, mem
6416 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6417 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6418 !strconcat(OpcodeStr,
6419 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6421 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6422 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6423 } // ExeDomain = SSEPackedDouble
6426 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6429 Intrinsic F64Int, bit Is2Addr = 1> {
6430 let ExeDomain = GenericDomain in {
6432 let hasSideEffects = 0 in
6433 def SSr : SS4AIi8<opcss, MRMSrcReg,
6434 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3),
6436 !strconcat(OpcodeStr,
6437 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6438 !strconcat(OpcodeStr,
6439 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6440 []>, Sched<[WriteFAdd]>;
6442 // Intrinsic operation, reg.
6443 let isCodeGenOnly = 1 in
6444 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6445 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6447 !strconcat(OpcodeStr,
6448 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6449 !strconcat(OpcodeStr,
6450 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6451 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6454 // Intrinsic operation, mem.
6455 def SSm : SS4AIi8<opcss, MRMSrcMem,
6456 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32u8imm:$src3),
6458 !strconcat(OpcodeStr,
6459 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6460 !strconcat(OpcodeStr,
6461 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6463 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6464 Sched<[WriteFAddLd, ReadAfterLd]>;
6467 let hasSideEffects = 0 in
6468 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6469 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3),
6471 !strconcat(OpcodeStr,
6472 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6473 !strconcat(OpcodeStr,
6474 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6475 []>, Sched<[WriteFAdd]>;
6477 // Intrinsic operation, reg.
6478 let isCodeGenOnly = 1 in
6479 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6480 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6482 !strconcat(OpcodeStr,
6483 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6484 !strconcat(OpcodeStr,
6485 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6486 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6489 // Intrinsic operation, mem.
6490 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6491 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32u8imm:$src3),
6493 !strconcat(OpcodeStr,
6494 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6495 !strconcat(OpcodeStr,
6496 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6498 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6499 Sched<[WriteFAddLd, ReadAfterLd]>;
6500 } // ExeDomain = GenericDomain
6503 // FP round - roundss, roundps, roundsd, roundpd
6504 let Predicates = [HasAVX] in {
6506 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6507 loadv4f32, loadv2f64,
6508 int_x86_sse41_round_ps,
6509 int_x86_sse41_round_pd>, VEX;
6510 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6511 loadv8f32, loadv4f64,
6512 int_x86_avx_round_ps_256,
6513 int_x86_avx_round_pd_256>, VEX, VEX_L;
6514 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6515 int_x86_sse41_round_ss,
6516 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6519 let Predicates = [UseAVX] in {
6520 def : Pat<(ffloor FR32:$src),
6521 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6522 def : Pat<(f64 (ffloor FR64:$src)),
6523 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6524 def : Pat<(f32 (fnearbyint FR32:$src)),
6525 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6526 def : Pat<(f64 (fnearbyint FR64:$src)),
6527 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6528 def : Pat<(f32 (fceil FR32:$src)),
6529 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6530 def : Pat<(f64 (fceil FR64:$src)),
6531 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6532 def : Pat<(f32 (frint FR32:$src)),
6533 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6534 def : Pat<(f64 (frint FR64:$src)),
6535 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6536 def : Pat<(f32 (ftrunc FR32:$src)),
6537 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6538 def : Pat<(f64 (ftrunc FR64:$src)),
6539 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6542 let Predicates = [HasAVX] in {
6543 def : Pat<(v4f32 (ffloor VR128:$src)),
6544 (VROUNDPSr VR128:$src, (i32 0x1))>;
6545 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6546 (VROUNDPSr VR128:$src, (i32 0xC))>;
6547 def : Pat<(v4f32 (fceil VR128:$src)),
6548 (VROUNDPSr VR128:$src, (i32 0x2))>;
6549 def : Pat<(v4f32 (frint VR128:$src)),
6550 (VROUNDPSr VR128:$src, (i32 0x4))>;
6551 def : Pat<(v4f32 (ftrunc VR128:$src)),
6552 (VROUNDPSr VR128:$src, (i32 0x3))>;
6554 def : Pat<(v2f64 (ffloor VR128:$src)),
6555 (VROUNDPDr VR128:$src, (i32 0x1))>;
6556 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6557 (VROUNDPDr VR128:$src, (i32 0xC))>;
6558 def : Pat<(v2f64 (fceil VR128:$src)),
6559 (VROUNDPDr VR128:$src, (i32 0x2))>;
6560 def : Pat<(v2f64 (frint VR128:$src)),
6561 (VROUNDPDr VR128:$src, (i32 0x4))>;
6562 def : Pat<(v2f64 (ftrunc VR128:$src)),
6563 (VROUNDPDr VR128:$src, (i32 0x3))>;
6565 def : Pat<(v8f32 (ffloor VR256:$src)),
6566 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6567 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6568 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6569 def : Pat<(v8f32 (fceil VR256:$src)),
6570 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6571 def : Pat<(v8f32 (frint VR256:$src)),
6572 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6573 def : Pat<(v8f32 (ftrunc VR256:$src)),
6574 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6576 def : Pat<(v4f64 (ffloor VR256:$src)),
6577 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6578 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6579 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6580 def : Pat<(v4f64 (fceil VR256:$src)),
6581 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6582 def : Pat<(v4f64 (frint VR256:$src)),
6583 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6584 def : Pat<(v4f64 (ftrunc VR256:$src)),
6585 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6588 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6589 memopv4f32, memopv2f64,
6590 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6591 let Constraints = "$src1 = $dst" in
6592 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6593 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6595 let Predicates = [UseSSE41] in {
6596 def : Pat<(ffloor FR32:$src),
6597 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6598 def : Pat<(f64 (ffloor FR64:$src)),
6599 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6600 def : Pat<(f32 (fnearbyint FR32:$src)),
6601 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6602 def : Pat<(f64 (fnearbyint FR64:$src)),
6603 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6604 def : Pat<(f32 (fceil FR32:$src)),
6605 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6606 def : Pat<(f64 (fceil FR64:$src)),
6607 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6608 def : Pat<(f32 (frint FR32:$src)),
6609 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6610 def : Pat<(f64 (frint FR64:$src)),
6611 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6612 def : Pat<(f32 (ftrunc FR32:$src)),
6613 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6614 def : Pat<(f64 (ftrunc FR64:$src)),
6615 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6617 def : Pat<(v4f32 (ffloor VR128:$src)),
6618 (ROUNDPSr VR128:$src, (i32 0x1))>;
6619 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6620 (ROUNDPSr VR128:$src, (i32 0xC))>;
6621 def : Pat<(v4f32 (fceil VR128:$src)),
6622 (ROUNDPSr VR128:$src, (i32 0x2))>;
6623 def : Pat<(v4f32 (frint VR128:$src)),
6624 (ROUNDPSr VR128:$src, (i32 0x4))>;
6625 def : Pat<(v4f32 (ftrunc VR128:$src)),
6626 (ROUNDPSr VR128:$src, (i32 0x3))>;
6628 def : Pat<(v2f64 (ffloor VR128:$src)),
6629 (ROUNDPDr VR128:$src, (i32 0x1))>;
6630 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6631 (ROUNDPDr VR128:$src, (i32 0xC))>;
6632 def : Pat<(v2f64 (fceil VR128:$src)),
6633 (ROUNDPDr VR128:$src, (i32 0x2))>;
6634 def : Pat<(v2f64 (frint VR128:$src)),
6635 (ROUNDPDr VR128:$src, (i32 0x4))>;
6636 def : Pat<(v2f64 (ftrunc VR128:$src)),
6637 (ROUNDPDr VR128:$src, (i32 0x3))>;
6640 //===----------------------------------------------------------------------===//
6641 // SSE4.1 - Packed Bit Test
6642 //===----------------------------------------------------------------------===//
6644 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6645 // the intel intrinsic that corresponds to this.
6646 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6647 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6648 "vptest\t{$src2, $src1|$src1, $src2}",
6649 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6650 Sched<[WriteVecLogic]>, VEX;
6651 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6652 "vptest\t{$src2, $src1|$src1, $src2}",
6653 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6654 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6656 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6657 "vptest\t{$src2, $src1|$src1, $src2}",
6658 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6659 Sched<[WriteVecLogic]>, VEX, VEX_L;
6660 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6661 "vptest\t{$src2, $src1|$src1, $src2}",
6662 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6663 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6666 let Defs = [EFLAGS] in {
6667 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6668 "ptest\t{$src2, $src1|$src1, $src2}",
6669 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6670 Sched<[WriteVecLogic]>;
6671 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6672 "ptest\t{$src2, $src1|$src1, $src2}",
6673 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6674 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6677 // The bit test instructions below are AVX only
6678 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6679 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6680 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6681 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6682 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6683 Sched<[WriteVecLogic]>, VEX;
6684 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6685 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6686 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6687 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6690 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6691 let ExeDomain = SSEPackedSingle in {
6692 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6693 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6696 let ExeDomain = SSEPackedDouble in {
6697 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6698 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6703 //===----------------------------------------------------------------------===//
6704 // SSE4.1 - Misc Instructions
6705 //===----------------------------------------------------------------------===//
6707 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6708 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6709 "popcnt{w}\t{$src, $dst|$dst, $src}",
6710 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6711 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6713 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6714 "popcnt{w}\t{$src, $dst|$dst, $src}",
6715 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6716 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6717 Sched<[WriteFAddLd]>, OpSize16, XS;
6719 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6720 "popcnt{l}\t{$src, $dst|$dst, $src}",
6721 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6722 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6725 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6726 "popcnt{l}\t{$src, $dst|$dst, $src}",
6727 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6728 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6729 Sched<[WriteFAddLd]>, OpSize32, XS;
6731 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6732 "popcnt{q}\t{$src, $dst|$dst, $src}",
6733 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6734 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6735 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6736 "popcnt{q}\t{$src, $dst|$dst, $src}",
6737 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6738 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6739 Sched<[WriteFAddLd]>, XS;
6744 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6745 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6746 Intrinsic IntId128, PatFrag ld_frag,
6747 X86FoldableSchedWrite Sched> {
6748 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6750 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6751 [(set VR128:$dst, (IntId128 VR128:$src))]>,
6753 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6755 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6757 (IntId128 (bitconvert (ld_frag addr:$src))))]>,
6758 Sched<[Sched.Folded]>;
6761 // PHMIN has the same profile as PSAD, thus we use the same scheduling
6762 // model, although the naming is misleading.
6763 let Predicates = [HasAVX] in
6764 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6765 int_x86_sse41_phminposuw, loadv2i64,
6767 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6768 int_x86_sse41_phminposuw, memopv2i64,
6771 /// SS48I_binop_rm - Simple SSE41 binary operator.
6772 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6773 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6774 X86MemOperand x86memop, bit Is2Addr = 1,
6775 OpndItins itins = SSE_INTALU_ITINS_P> {
6776 let isCommutable = 1 in
6777 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6778 (ins RC:$src1, RC:$src2),
6780 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6781 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6782 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6783 Sched<[itins.Sched]>;
6784 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6785 (ins RC:$src1, x86memop:$src2),
6787 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6788 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6790 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
6791 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6794 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
6796 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
6797 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
6798 PatFrag memop_frag, X86MemOperand x86memop,
6800 bit IsCommutable = 0, bit Is2Addr = 1> {
6801 let isCommutable = IsCommutable in
6802 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6803 (ins RC:$src1, RC:$src2),
6805 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6806 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6807 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
6808 Sched<[itins.Sched]>;
6809 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6810 (ins RC:$src1, x86memop:$src2),
6812 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6813 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6814 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
6815 (bitconvert (memop_frag addr:$src2)))))]>,
6816 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6819 let Predicates = [HasAVX, NoVLX] in {
6820 let isCommutable = 0 in
6821 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6822 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6824 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6825 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6827 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6828 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6830 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6831 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6833 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6834 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6836 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6837 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6839 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6840 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6842 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6843 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6845 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
6846 VR128, loadv2i64, i128mem,
6847 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
6850 let Predicates = [HasAVX2, NoVLX] in {
6851 let isCommutable = 0 in
6852 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6853 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6855 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6856 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6858 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6859 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6861 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6862 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6864 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6865 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6867 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6868 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6870 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6871 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6873 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6874 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6876 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
6877 VR256, loadv4i64, i256mem,
6878 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
6881 let Constraints = "$src1 = $dst" in {
6882 let isCommutable = 0 in
6883 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6884 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6885 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6886 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6887 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6888 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6889 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6890 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6891 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6892 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6893 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6894 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6895 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6896 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6897 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6898 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6899 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
6900 VR128, memopv2i64, i128mem,
6901 SSE_INTMUL_ITINS_P, 1>;
6904 let Predicates = [HasAVX, NoVLX] in {
6905 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6906 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
6908 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6909 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6912 let Predicates = [HasAVX2] in {
6913 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6914 loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
6916 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6917 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6921 let Constraints = "$src1 = $dst" in {
6922 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6923 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6924 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6925 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6928 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6929 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6930 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6931 X86MemOperand x86memop, bit Is2Addr = 1,
6932 OpndItins itins = DEFAULT_ITINS> {
6933 let isCommutable = 1 in
6934 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6935 (ins RC:$src1, RC:$src2, u8imm:$src3),
6937 !strconcat(OpcodeStr,
6938 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6939 !strconcat(OpcodeStr,
6940 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6941 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6942 Sched<[itins.Sched]>;
6943 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6944 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6946 !strconcat(OpcodeStr,
6947 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6948 !strconcat(OpcodeStr,
6949 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6952 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6953 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6956 /// SS41I_binop_rmi - SSE 4.1 binary operator with 8-bit immediate
6957 multiclass SS41I_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
6958 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6959 X86MemOperand x86memop, bit Is2Addr = 1,
6960 OpndItins itins = DEFAULT_ITINS> {
6961 let isCommutable = 1 in
6962 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6963 (ins RC:$src1, RC:$src2, u8imm:$src3),
6965 !strconcat(OpcodeStr,
6966 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6967 !strconcat(OpcodeStr,
6968 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6969 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))],
6970 itins.rr>, Sched<[itins.Sched]>;
6971 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6972 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6974 !strconcat(OpcodeStr,
6975 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6976 !strconcat(OpcodeStr,
6977 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6979 (OpVT (OpNode RC:$src1,
6980 (bitconvert (memop_frag addr:$src2)), imm:$src3)))], itins.rm>,
6981 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6984 let Predicates = [HasAVX] in {
6985 let isCommutable = 0 in {
6986 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6987 VR128, loadv2i64, i128mem, 0,
6988 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
6991 let ExeDomain = SSEPackedSingle in {
6992 defm VBLENDPS : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v4f32,
6993 VR128, loadv4f32, f128mem, 0,
6994 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
6995 defm VBLENDPSY : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v8f32,
6996 VR256, loadv8f32, f256mem, 0,
6997 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
6999 let ExeDomain = SSEPackedDouble in {
7000 defm VBLENDPD : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v2f64,
7001 VR128, loadv2f64, f128mem, 0,
7002 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7003 defm VBLENDPDY : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v4f64,
7004 VR256, loadv4f64, f256mem, 0,
7005 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7007 defm VPBLENDW : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v8i16,
7008 VR128, loadv2i64, i128mem, 0,
7009 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7011 let ExeDomain = SSEPackedSingle in
7012 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7013 VR128, loadv4f32, f128mem, 0,
7014 SSE_DPPS_ITINS>, VEX_4V;
7015 let ExeDomain = SSEPackedDouble in
7016 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7017 VR128, loadv2f64, f128mem, 0,
7018 SSE_DPPS_ITINS>, VEX_4V;
7019 let ExeDomain = SSEPackedSingle in
7020 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7021 VR256, loadv8f32, i256mem, 0,
7022 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7025 let Predicates = [HasAVX2] in {
7026 let isCommutable = 0 in {
7027 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7028 VR256, loadv4i64, i256mem, 0,
7029 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7031 defm VPBLENDWY : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v16i16,
7032 VR256, loadv4i64, i256mem, 0,
7033 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7036 let Constraints = "$src1 = $dst" in {
7037 let isCommutable = 0 in {
7038 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7039 VR128, memopv2i64, i128mem,
7040 1, SSE_MPSADBW_ITINS>;
7042 let ExeDomain = SSEPackedSingle in
7043 defm BLENDPS : SS41I_binop_rmi<0x0C, "blendps", X86Blendi, v4f32,
7044 VR128, memopv4f32, f128mem,
7045 1, SSE_INTALU_ITINS_FBLEND_P>;
7046 let ExeDomain = SSEPackedDouble in
7047 defm BLENDPD : SS41I_binop_rmi<0x0D, "blendpd", X86Blendi, v2f64,
7048 VR128, memopv2f64, f128mem,
7049 1, SSE_INTALU_ITINS_FBLEND_P>;
7050 defm PBLENDW : SS41I_binop_rmi<0x0E, "pblendw", X86Blendi, v8i16,
7051 VR128, memopv2i64, i128mem,
7052 1, SSE_INTALU_ITINS_BLEND_P>;
7053 let ExeDomain = SSEPackedSingle in
7054 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7055 VR128, memopv4f32, f128mem, 1,
7057 let ExeDomain = SSEPackedDouble in
7058 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7059 VR128, memopv2f64, f128mem, 1,
7063 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7064 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7065 RegisterClass RC, X86MemOperand x86memop,
7066 PatFrag mem_frag, Intrinsic IntId,
7067 X86FoldableSchedWrite Sched> {
7068 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7069 (ins RC:$src1, RC:$src2, RC:$src3),
7070 !strconcat(OpcodeStr,
7071 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7072 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7073 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7076 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7077 (ins RC:$src1, x86memop:$src2, RC:$src3),
7078 !strconcat(OpcodeStr,
7079 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7081 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7083 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7084 Sched<[Sched.Folded, ReadAfterLd]>;
7087 let Predicates = [HasAVX] in {
7088 let ExeDomain = SSEPackedDouble in {
7089 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7090 loadv2f64, int_x86_sse41_blendvpd,
7092 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7093 loadv4f64, int_x86_avx_blendv_pd_256,
7094 WriteFVarBlend>, VEX_L;
7095 } // ExeDomain = SSEPackedDouble
7096 let ExeDomain = SSEPackedSingle in {
7097 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7098 loadv4f32, int_x86_sse41_blendvps,
7100 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7101 loadv8f32, int_x86_avx_blendv_ps_256,
7102 WriteFVarBlend>, VEX_L;
7103 } // ExeDomain = SSEPackedSingle
7104 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7105 loadv2i64, int_x86_sse41_pblendvb,
7109 let Predicates = [HasAVX2] in {
7110 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7111 loadv4i64, int_x86_avx2_pblendvb,
7112 WriteVarBlend>, VEX_L;
7115 let Predicates = [HasAVX] in {
7116 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7117 (v16i8 VR128:$src2))),
7118 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7119 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7120 (v4i32 VR128:$src2))),
7121 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7122 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7123 (v4f32 VR128:$src2))),
7124 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7125 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7126 (v2i64 VR128:$src2))),
7127 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7128 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7129 (v2f64 VR128:$src2))),
7130 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7131 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7132 (v8i32 VR256:$src2))),
7133 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7134 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7135 (v8f32 VR256:$src2))),
7136 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7137 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7138 (v4i64 VR256:$src2))),
7139 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7140 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7141 (v4f64 VR256:$src2))),
7142 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7145 let Predicates = [HasAVX2] in {
7146 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7147 (v32i8 VR256:$src2))),
7148 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7152 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7153 // on targets where they have equal performance. These were changed to use
7154 // blends because blends have better throughput on SandyBridge and Haswell, but
7155 // movs[s/d] are 1-2 byte shorter instructions.
7156 let Predicates = [UseAVX] in {
7157 let AddedComplexity = 15 in {
7158 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7159 // MOVS{S,D} to the lower bits.
7160 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7161 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7162 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7163 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7164 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7165 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7166 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7167 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7169 // Move low f32 and clear high bits.
7170 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7171 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7173 // Move low f64 and clear high bits.
7174 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7175 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7178 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7179 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7180 (SUBREG_TO_REG (i32 0),
7181 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7183 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7184 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7185 (SUBREG_TO_REG (i64 0),
7186 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7189 // These will incur an FP/int domain crossing penalty, but it may be the only
7190 // way without AVX2. Do not add any complexity because we may be able to match
7191 // more optimal patterns defined earlier in this file.
7192 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7193 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7194 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7195 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7198 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7199 // on targets where they have equal performance. These were changed to use
7200 // blends because blends have better throughput on SandyBridge and Haswell, but
7201 // movs[s/d] are 1-2 byte shorter instructions.
7202 let Predicates = [UseSSE41] in {
7203 // With SSE41 we can use blends for these patterns.
7204 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7205 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7206 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7207 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7208 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7209 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7213 /// SS41I_ternary_int - SSE 4.1 ternary operator
7214 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7215 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7216 X86MemOperand x86memop, Intrinsic IntId,
7217 OpndItins itins = DEFAULT_ITINS> {
7218 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7219 (ins VR128:$src1, VR128:$src2),
7220 !strconcat(OpcodeStr,
7221 "\t{$src2, $dst|$dst, $src2}"),
7222 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7223 itins.rr>, Sched<[itins.Sched]>;
7225 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7226 (ins VR128:$src1, x86memop:$src2),
7227 !strconcat(OpcodeStr,
7228 "\t{$src2, $dst|$dst, $src2}"),
7231 (bitconvert (mem_frag addr:$src2)), XMM0))],
7232 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7236 let ExeDomain = SSEPackedDouble in
7237 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7238 int_x86_sse41_blendvpd,
7239 DEFAULT_ITINS_FBLENDSCHED>;
7240 let ExeDomain = SSEPackedSingle in
7241 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7242 int_x86_sse41_blendvps,
7243 DEFAULT_ITINS_FBLENDSCHED>;
7244 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7245 int_x86_sse41_pblendvb,
7246 DEFAULT_ITINS_VARBLENDSCHED>;
7248 // Aliases with the implicit xmm0 argument
7249 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7250 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7251 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7252 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7253 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7254 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7255 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7256 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7257 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7258 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7259 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7260 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7262 let Predicates = [UseSSE41] in {
7263 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7264 (v16i8 VR128:$src2))),
7265 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7266 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7267 (v4i32 VR128:$src2))),
7268 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7269 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7270 (v4f32 VR128:$src2))),
7271 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7272 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7273 (v2i64 VR128:$src2))),
7274 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7275 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7276 (v2f64 VR128:$src2))),
7277 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7280 let SchedRW = [WriteLoad] in {
7281 let Predicates = [HasAVX] in
7282 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7283 "vmovntdqa\t{$src, $dst|$dst, $src}",
7284 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7286 let Predicates = [HasAVX2] in
7287 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7288 "vmovntdqa\t{$src, $dst|$dst, $src}",
7289 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7291 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7292 "movntdqa\t{$src, $dst|$dst, $src}",
7293 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7296 //===----------------------------------------------------------------------===//
7297 // SSE4.2 - Compare Instructions
7298 //===----------------------------------------------------------------------===//
7300 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7301 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7302 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7303 X86MemOperand x86memop, bit Is2Addr = 1> {
7304 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7305 (ins RC:$src1, RC:$src2),
7307 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7308 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7309 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7310 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7311 (ins RC:$src1, x86memop:$src2),
7313 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7314 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7316 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7319 let Predicates = [HasAVX] in
7320 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7321 loadv2i64, i128mem, 0>, VEX_4V;
7323 let Predicates = [HasAVX2] in
7324 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7325 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7327 let Constraints = "$src1 = $dst" in
7328 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7329 memopv2i64, i128mem>;
7331 //===----------------------------------------------------------------------===//
7332 // SSE4.2 - String/text Processing Instructions
7333 //===----------------------------------------------------------------------===//
7335 // Packed Compare Implicit Length Strings, Return Mask
7336 multiclass pseudo_pcmpistrm<string asm, PatFrag ld_frag> {
7337 def REG : PseudoI<(outs VR128:$dst),
7338 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7339 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7341 def MEM : PseudoI<(outs VR128:$dst),
7342 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7343 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7344 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7347 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7348 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128", loadv2i64>,
7350 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128", memopv2i64>,
7351 Requires<[UseSSE42]>;
7354 multiclass pcmpistrm_SS42AI<string asm> {
7355 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7356 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7357 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7358 []>, Sched<[WritePCmpIStrM]>;
7360 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7361 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7362 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7363 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7366 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7367 let Predicates = [HasAVX] in
7368 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7369 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7372 // Packed Compare Explicit Length Strings, Return Mask
7373 multiclass pseudo_pcmpestrm<string asm, PatFrag ld_frag> {
7374 def REG : PseudoI<(outs VR128:$dst),
7375 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7376 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7377 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7378 def MEM : PseudoI<(outs VR128:$dst),
7379 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7380 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7381 (bc_v16i8 (ld_frag addr:$src3)), EDX, imm:$src5))]>;
7384 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7385 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128", loadv2i64>,
7387 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128", memopv2i64>,
7388 Requires<[UseSSE42]>;
7391 multiclass SS42AI_pcmpestrm<string asm> {
7392 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7393 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7394 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7395 []>, Sched<[WritePCmpEStrM]>;
7397 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7398 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7399 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7400 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7403 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7404 let Predicates = [HasAVX] in
7405 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7406 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7409 // Packed Compare Implicit Length Strings, Return Index
7410 multiclass pseudo_pcmpistri<string asm, PatFrag ld_frag> {
7411 def REG : PseudoI<(outs GR32:$dst),
7412 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7413 [(set GR32:$dst, EFLAGS,
7414 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7415 def MEM : PseudoI<(outs GR32:$dst),
7416 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7417 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7418 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7421 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7422 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI", loadv2i64>,
7424 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI", memopv2i64>,
7425 Requires<[UseSSE42]>;
7428 multiclass SS42AI_pcmpistri<string asm> {
7429 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7430 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7431 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7432 []>, Sched<[WritePCmpIStrI]>;
7434 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7435 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7436 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7437 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7440 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7441 let Predicates = [HasAVX] in
7442 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7443 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7446 // Packed Compare Explicit Length Strings, Return Index
7447 multiclass pseudo_pcmpestri<string asm, PatFrag ld_frag> {
7448 def REG : PseudoI<(outs GR32:$dst),
7449 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7450 [(set GR32:$dst, EFLAGS,
7451 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7452 def MEM : PseudoI<(outs GR32:$dst),
7453 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7454 [(set GR32:$dst, EFLAGS,
7455 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (ld_frag addr:$src3)), EDX,
7459 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7460 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI", loadv2i64>,
7462 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI", memopv2i64>,
7463 Requires<[UseSSE42]>;
7466 multiclass SS42AI_pcmpestri<string asm> {
7467 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7468 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7469 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7470 []>, Sched<[WritePCmpEStrI]>;
7472 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7473 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7474 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7475 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7478 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7479 let Predicates = [HasAVX] in
7480 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7481 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7484 //===----------------------------------------------------------------------===//
7485 // SSE4.2 - CRC Instructions
7486 //===----------------------------------------------------------------------===//
7488 // No CRC instructions have AVX equivalents
7490 // crc intrinsic instruction
7491 // This set of instructions are only rm, the only difference is the size
7493 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7494 RegisterClass RCIn, SDPatternOperator Int> :
7495 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7496 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7497 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7500 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7501 X86MemOperand x86memop, SDPatternOperator Int> :
7502 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7503 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7504 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7505 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7507 let Constraints = "$src1 = $dst" in {
7508 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7509 int_x86_sse42_crc32_32_8>;
7510 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7511 int_x86_sse42_crc32_32_8>;
7512 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7513 int_x86_sse42_crc32_32_16>, OpSize16;
7514 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7515 int_x86_sse42_crc32_32_16>, OpSize16;
7516 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7517 int_x86_sse42_crc32_32_32>, OpSize32;
7518 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7519 int_x86_sse42_crc32_32_32>, OpSize32;
7520 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7521 int_x86_sse42_crc32_64_64>, REX_W;
7522 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7523 int_x86_sse42_crc32_64_64>, REX_W;
7524 let hasSideEffects = 0 in {
7526 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7528 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7533 //===----------------------------------------------------------------------===//
7534 // SHA-NI Instructions
7535 //===----------------------------------------------------------------------===//
7537 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7539 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7540 (ins VR128:$src1, VR128:$src2),
7541 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7543 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7544 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7546 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7547 (ins VR128:$src1, i128mem:$src2),
7548 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7550 (set VR128:$dst, (IntId VR128:$src1,
7551 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7552 (set VR128:$dst, (IntId VR128:$src1,
7553 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7556 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7557 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7558 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7559 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7561 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7562 (i8 imm:$src3)))]>, TA;
7563 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7564 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7565 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7567 (int_x86_sha1rnds4 VR128:$src1,
7568 (bc_v4i32 (memopv2i64 addr:$src2)),
7569 (i8 imm:$src3)))]>, TA;
7571 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7572 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7573 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7576 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7578 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7579 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7582 // Aliases with explicit %xmm0
7583 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7584 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7585 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7586 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7588 //===----------------------------------------------------------------------===//
7589 // AES-NI Instructions
7590 //===----------------------------------------------------------------------===//
7592 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
7593 PatFrag ld_frag, bit Is2Addr = 1> {
7594 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7595 (ins VR128:$src1, VR128:$src2),
7597 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7598 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7599 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7600 Sched<[WriteAESDecEnc]>;
7601 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7602 (ins VR128:$src1, i128mem:$src2),
7604 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7605 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7607 (IntId128 VR128:$src1, (ld_frag addr:$src2)))]>,
7608 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7611 // Perform One Round of an AES Encryption/Decryption Flow
7612 let Predicates = [HasAVX, HasAES] in {
7613 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7614 int_x86_aesni_aesenc, loadv2i64, 0>, VEX_4V;
7615 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7616 int_x86_aesni_aesenclast, loadv2i64, 0>, VEX_4V;
7617 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7618 int_x86_aesni_aesdec, loadv2i64, 0>, VEX_4V;
7619 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7620 int_x86_aesni_aesdeclast, loadv2i64, 0>, VEX_4V;
7623 let Constraints = "$src1 = $dst" in {
7624 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7625 int_x86_aesni_aesenc, memopv2i64>;
7626 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7627 int_x86_aesni_aesenclast, memopv2i64>;
7628 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7629 int_x86_aesni_aesdec, memopv2i64>;
7630 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7631 int_x86_aesni_aesdeclast, memopv2i64>;
7634 // Perform the AES InvMixColumn Transformation
7635 let Predicates = [HasAVX, HasAES] in {
7636 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7638 "vaesimc\t{$src1, $dst|$dst, $src1}",
7640 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7642 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7643 (ins i128mem:$src1),
7644 "vaesimc\t{$src1, $dst|$dst, $src1}",
7645 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7646 Sched<[WriteAESIMCLd]>, VEX;
7648 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7650 "aesimc\t{$src1, $dst|$dst, $src1}",
7652 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7653 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7654 (ins i128mem:$src1),
7655 "aesimc\t{$src1, $dst|$dst, $src1}",
7656 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7657 Sched<[WriteAESIMCLd]>;
7659 // AES Round Key Generation Assist
7660 let Predicates = [HasAVX, HasAES] in {
7661 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7662 (ins VR128:$src1, u8imm:$src2),
7663 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7665 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7666 Sched<[WriteAESKeyGen]>, VEX;
7667 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7668 (ins i128mem:$src1, u8imm:$src2),
7669 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7671 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7672 Sched<[WriteAESKeyGenLd]>, VEX;
7674 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7675 (ins VR128:$src1, u8imm:$src2),
7676 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7678 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7679 Sched<[WriteAESKeyGen]>;
7680 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7681 (ins i128mem:$src1, u8imm:$src2),
7682 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7684 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7685 Sched<[WriteAESKeyGenLd]>;
7687 //===----------------------------------------------------------------------===//
7688 // PCLMUL Instructions
7689 //===----------------------------------------------------------------------===//
7691 // AVX carry-less Multiplication instructions
7692 let isCommutable = 1 in
7693 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7694 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7695 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7697 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7698 Sched<[WriteCLMul]>;
7700 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7701 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7702 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7703 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7704 (loadv2i64 addr:$src2), imm:$src3))]>,
7705 Sched<[WriteCLMulLd, ReadAfterLd]>;
7707 // Carry-less Multiplication instructions
7708 let Constraints = "$src1 = $dst" in {
7709 let isCommutable = 1 in
7710 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7711 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7712 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7714 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7715 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
7717 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7718 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7719 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7720 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7721 (memopv2i64 addr:$src2), imm:$src3))],
7722 IIC_SSE_PCLMULQDQ_RM>,
7723 Sched<[WriteCLMulLd, ReadAfterLd]>;
7724 } // Constraints = "$src1 = $dst"
7727 multiclass pclmul_alias<string asm, int immop> {
7728 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7729 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
7731 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7732 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
7734 def : InstAlias<!strconcat("vpclmul", asm,
7735 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7736 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
7739 def : InstAlias<!strconcat("vpclmul", asm,
7740 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7741 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
7744 defm : pclmul_alias<"hqhq", 0x11>;
7745 defm : pclmul_alias<"hqlq", 0x01>;
7746 defm : pclmul_alias<"lqhq", 0x10>;
7747 defm : pclmul_alias<"lqlq", 0x00>;
7749 //===----------------------------------------------------------------------===//
7750 // SSE4A Instructions
7751 //===----------------------------------------------------------------------===//
7753 let Predicates = [HasSSE4A] in {
7755 let Constraints = "$src = $dst" in {
7756 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
7757 (ins VR128:$src, u8imm:$len, u8imm:$idx),
7758 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7759 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7761 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7762 (ins VR128:$src, VR128:$mask),
7763 "extrq\t{$mask, $src|$src, $mask}",
7764 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7765 VR128:$mask))]>, PD;
7767 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7768 (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
7769 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7770 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7771 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7772 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7773 (ins VR128:$src, VR128:$mask),
7774 "insertq\t{$mask, $src|$src, $mask}",
7775 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7776 VR128:$mask))]>, XD;
7779 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7780 "movntss\t{$src, $dst|$dst, $src}",
7781 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7783 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7784 "movntsd\t{$src, $dst|$dst, $src}",
7785 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7788 //===----------------------------------------------------------------------===//
7790 //===----------------------------------------------------------------------===//
7792 //===----------------------------------------------------------------------===//
7793 // VBROADCAST - Load from memory and broadcast to all elements of the
7794 // destination operand
7796 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7797 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
7798 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7799 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7800 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
7802 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
7803 X86MemOperand x86memop, ValueType VT,
7804 PatFrag ld_frag, SchedWrite Sched> :
7805 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7806 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7807 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
7808 Sched<[Sched]>, VEX {
7812 // AVX2 adds register forms
7813 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7814 Intrinsic Int, SchedWrite Sched> :
7815 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7816 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7817 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
7819 let ExeDomain = SSEPackedSingle in {
7820 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
7821 f32mem, v4f32, loadf32, WriteLoad>;
7822 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
7823 f32mem, v8f32, loadf32,
7824 WriteFShuffleLd>, VEX_L;
7826 let ExeDomain = SSEPackedDouble in
7827 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
7828 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
7829 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7830 int_x86_avx_vbroadcastf128_pd_256,
7831 WriteFShuffleLd>, VEX_L;
7833 let ExeDomain = SSEPackedSingle in {
7834 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7835 int_x86_avx2_vbroadcast_ss_ps,
7837 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7838 int_x86_avx2_vbroadcast_ss_ps_256,
7839 WriteFShuffle256>, VEX_L;
7841 let ExeDomain = SSEPackedDouble in
7842 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7843 int_x86_avx2_vbroadcast_sd_pd_256,
7844 WriteFShuffle256>, VEX_L;
7846 let Predicates = [HasAVX2] in
7847 def VBROADCASTI128 : avx_broadcast_no_int<0x5A, "vbroadcasti128", VR256,
7848 i128mem, v4i64, loadv2i64,
7851 let Predicates = [HasAVX] in
7852 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7853 (VBROADCASTF128 addr:$src)>;
7856 //===----------------------------------------------------------------------===//
7857 // VINSERTF128 - Insert packed floating-point values
7859 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7860 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7861 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
7862 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7863 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
7865 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7866 (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
7867 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7868 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
7871 let Predicates = [HasAVX] in {
7872 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7874 (VINSERTF128rr VR256:$src1, VR128:$src2,
7875 (INSERT_get_vinsert128_imm VR256:$ins))>;
7876 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7878 (VINSERTF128rr VR256:$src1, VR128:$src2,
7879 (INSERT_get_vinsert128_imm VR256:$ins))>;
7881 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7883 (VINSERTF128rm VR256:$src1, addr:$src2,
7884 (INSERT_get_vinsert128_imm VR256:$ins))>;
7885 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7887 (VINSERTF128rm VR256:$src1, addr:$src2,
7888 (INSERT_get_vinsert128_imm VR256:$ins))>;
7891 let Predicates = [HasAVX1Only] in {
7892 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7894 (VINSERTF128rr VR256:$src1, VR128:$src2,
7895 (INSERT_get_vinsert128_imm VR256:$ins))>;
7896 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7898 (VINSERTF128rr VR256:$src1, VR128:$src2,
7899 (INSERT_get_vinsert128_imm VR256:$ins))>;
7900 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7902 (VINSERTF128rr VR256:$src1, VR128:$src2,
7903 (INSERT_get_vinsert128_imm VR256:$ins))>;
7904 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7906 (VINSERTF128rr VR256:$src1, VR128:$src2,
7907 (INSERT_get_vinsert128_imm VR256:$ins))>;
7909 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7911 (VINSERTF128rm VR256:$src1, addr:$src2,
7912 (INSERT_get_vinsert128_imm VR256:$ins))>;
7913 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7914 (bc_v4i32 (loadv2i64 addr:$src2)),
7916 (VINSERTF128rm VR256:$src1, addr:$src2,
7917 (INSERT_get_vinsert128_imm VR256:$ins))>;
7918 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7919 (bc_v16i8 (loadv2i64 addr:$src2)),
7921 (VINSERTF128rm VR256:$src1, addr:$src2,
7922 (INSERT_get_vinsert128_imm VR256:$ins))>;
7923 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7924 (bc_v8i16 (loadv2i64 addr:$src2)),
7926 (VINSERTF128rm VR256:$src1, addr:$src2,
7927 (INSERT_get_vinsert128_imm VR256:$ins))>;
7930 //===----------------------------------------------------------------------===//
7931 // VEXTRACTF128 - Extract packed floating-point values
7933 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7934 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7935 (ins VR256:$src1, u8imm:$src2),
7936 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7937 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
7939 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7940 (ins f128mem:$dst, VR256:$src1, u8imm:$src2),
7941 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7942 []>, Sched<[WriteStore]>, VEX, VEX_L;
7946 let Predicates = [HasAVX] in {
7947 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7948 (v4f32 (VEXTRACTF128rr
7949 (v8f32 VR256:$src1),
7950 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7951 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7952 (v2f64 (VEXTRACTF128rr
7953 (v4f64 VR256:$src1),
7954 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7956 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7957 (iPTR imm))), addr:$dst),
7958 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7959 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7960 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7961 (iPTR imm))), addr:$dst),
7962 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7963 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7966 let Predicates = [HasAVX1Only] in {
7967 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7968 (v2i64 (VEXTRACTF128rr
7969 (v4i64 VR256:$src1),
7970 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7971 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7972 (v4i32 (VEXTRACTF128rr
7973 (v8i32 VR256:$src1),
7974 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7975 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7976 (v8i16 (VEXTRACTF128rr
7977 (v16i16 VR256:$src1),
7978 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7979 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7980 (v16i8 (VEXTRACTF128rr
7981 (v32i8 VR256:$src1),
7982 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7984 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
7985 (iPTR imm))), addr:$dst),
7986 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7987 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7988 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
7989 (iPTR imm))), addr:$dst),
7990 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7991 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7992 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
7993 (iPTR imm))), addr:$dst),
7994 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7995 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7996 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
7997 (iPTR imm))), addr:$dst),
7998 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7999 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8002 //===----------------------------------------------------------------------===//
8003 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8005 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8006 Intrinsic IntLd, Intrinsic IntLd256,
8007 Intrinsic IntSt, Intrinsic IntSt256> {
8008 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8009 (ins VR128:$src1, f128mem:$src2),
8010 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8011 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8013 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8014 (ins VR256:$src1, f256mem:$src2),
8015 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8016 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8018 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8019 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8020 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8021 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8022 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8023 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8024 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8025 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8028 let ExeDomain = SSEPackedSingle in
8029 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8030 int_x86_avx_maskload_ps,
8031 int_x86_avx_maskload_ps_256,
8032 int_x86_avx_maskstore_ps,
8033 int_x86_avx_maskstore_ps_256>;
8034 let ExeDomain = SSEPackedDouble in
8035 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8036 int_x86_avx_maskload_pd,
8037 int_x86_avx_maskload_pd_256,
8038 int_x86_avx_maskstore_pd,
8039 int_x86_avx_maskstore_pd_256>;
8041 //===----------------------------------------------------------------------===//
8042 // VPERMIL - Permute Single and Double Floating-Point Values
8044 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8045 RegisterClass RC, X86MemOperand x86memop_f,
8046 X86MemOperand x86memop_i, PatFrag i_frag,
8047 Intrinsic IntVar, ValueType vt> {
8048 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8049 (ins RC:$src1, RC:$src2),
8050 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8051 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8052 Sched<[WriteFShuffle]>;
8053 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8054 (ins RC:$src1, x86memop_i:$src2),
8055 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8056 [(set RC:$dst, (IntVar RC:$src1,
8057 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8058 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8060 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8061 (ins RC:$src1, u8imm:$src2),
8062 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8063 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8064 Sched<[WriteFShuffle]>;
8065 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8066 (ins x86memop_f:$src1, u8imm:$src2),
8067 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8069 (vt (X86VPermilpi (load addr:$src1), (i8 imm:$src2))))]>, VEX,
8070 Sched<[WriteFShuffleLd]>;
8073 let ExeDomain = SSEPackedSingle in {
8074 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8075 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8076 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8077 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8079 let ExeDomain = SSEPackedDouble in {
8080 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8081 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8082 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8083 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8086 let Predicates = [HasAVX] in {
8087 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8088 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8089 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8090 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8091 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8092 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8093 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8094 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8096 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8097 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8098 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8099 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8100 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8102 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8103 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8104 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8106 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8107 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8108 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8109 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8110 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8111 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8112 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8113 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8115 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8116 (VPERMILPDri VR128:$src1, imm:$imm)>;
8117 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8118 (VPERMILPDmi addr:$src1, imm:$imm)>;
8121 //===----------------------------------------------------------------------===//
8122 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8124 let ExeDomain = SSEPackedSingle in {
8125 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8126 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8127 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8128 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8129 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8130 Sched<[WriteFShuffle]>;
8131 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8132 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8133 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8134 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8135 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8136 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8139 let Predicates = [HasAVX] in {
8140 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8141 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8142 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8143 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8144 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8147 let Predicates = [HasAVX1Only] in {
8148 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8149 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8150 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8151 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8152 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8153 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8154 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8155 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8157 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8158 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8159 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8160 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8161 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8162 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8163 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8164 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8165 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8166 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8167 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8168 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8171 //===----------------------------------------------------------------------===//
8172 // VZERO - Zero YMM registers
8174 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8175 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8176 // Zero All YMM registers
8177 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8178 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8180 // Zero Upper bits of YMM registers
8181 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8182 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8185 //===----------------------------------------------------------------------===//
8186 // Half precision conversion instructions
8187 //===----------------------------------------------------------------------===//
8188 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8189 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8190 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8191 [(set RC:$dst, (Int VR128:$src))]>,
8192 T8PD, VEX, Sched<[WriteCvtF2F]>;
8193 let hasSideEffects = 0, mayLoad = 1 in
8194 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8195 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8196 Sched<[WriteCvtF2FLd]>;
8199 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8200 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8201 (ins RC:$src1, i32u8imm:$src2),
8202 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8203 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8204 TAPD, VEX, Sched<[WriteCvtF2F]>;
8205 let hasSideEffects = 0, mayStore = 1,
8206 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8207 def mr : Ii8<0x1D, MRMDestMem, (outs),
8208 (ins x86memop:$dst, RC:$src1, i32u8imm:$src2),
8209 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8213 let Predicates = [HasF16C] in {
8214 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8215 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8216 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8217 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8219 // Pattern match vcvtph2ps of a scalar i64 load.
8220 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8221 (VCVTPH2PSrm addr:$src)>;
8222 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8223 (VCVTPH2PSrm addr:$src)>;
8225 def : Pat<(store (f64 (vector_extract (bc_v2f64 (v8i16
8226 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8228 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8229 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v8i16
8230 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8232 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8233 def : Pat<(store (v8i16 (int_x86_vcvtps2ph_256 VR256:$src1, i32:$src2)),
8235 (VCVTPS2PHYmr addr:$dst, VR256:$src1, imm:$src2)>;
8238 // Patterns for matching conversions from float to half-float and vice versa.
8239 let Predicates = [HasF16C] in {
8240 def : Pat<(fp_to_f16 FR32:$src),
8241 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8242 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8244 def : Pat<(f16_to_fp GR16:$src),
8245 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8246 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8248 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8249 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8250 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8253 //===----------------------------------------------------------------------===//
8254 // AVX2 Instructions
8255 //===----------------------------------------------------------------------===//
8257 /// AVX2_binop_rmi - AVX2 binary operator with 8-bit immediate
8258 multiclass AVX2_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
8259 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
8260 X86MemOperand x86memop> {
8261 let isCommutable = 1 in
8262 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8263 (ins RC:$src1, RC:$src2, u8imm:$src3),
8264 !strconcat(OpcodeStr,
8265 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8266 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))]>,
8267 Sched<[WriteBlend]>, VEX_4V;
8268 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8269 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
8270 !strconcat(OpcodeStr,
8271 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8273 (OpVT (OpNode RC:$src1,
8274 (bitconvert (memop_frag addr:$src2)), imm:$src3)))]>,
8275 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8278 defm VPBLENDD : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v4i32,
8279 VR128, loadv2i64, i128mem>;
8280 defm VPBLENDDY : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v8i32,
8281 VR256, loadv4i64, i256mem>, VEX_L;
8283 //===----------------------------------------------------------------------===//
8284 // VPBROADCAST - Load from memory and broadcast to all elements of the
8285 // destination operand
8287 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8288 X86MemOperand x86memop, PatFrag ld_frag,
8289 Intrinsic Int128, Intrinsic Int256> {
8290 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8291 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8292 [(set VR128:$dst, (Int128 VR128:$src))]>,
8293 Sched<[WriteShuffle]>, VEX;
8294 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8295 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8297 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8298 Sched<[WriteLoad]>, VEX;
8299 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8300 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8301 [(set VR256:$dst, (Int256 VR128:$src))]>,
8302 Sched<[WriteShuffle256]>, VEX, VEX_L;
8303 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8304 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8306 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8307 Sched<[WriteLoad]>, VEX, VEX_L;
8310 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8311 int_x86_avx2_pbroadcastb_128,
8312 int_x86_avx2_pbroadcastb_256>;
8313 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8314 int_x86_avx2_pbroadcastw_128,
8315 int_x86_avx2_pbroadcastw_256>;
8316 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8317 int_x86_avx2_pbroadcastd_128,
8318 int_x86_avx2_pbroadcastd_256>;
8319 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8320 int_x86_avx2_pbroadcastq_128,
8321 int_x86_avx2_pbroadcastq_256>;
8323 let Predicates = [HasAVX2] in {
8324 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8325 (VPBROADCASTBrm addr:$src)>;
8326 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8327 (VPBROADCASTBYrm addr:$src)>;
8328 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8329 (VPBROADCASTWrm addr:$src)>;
8330 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8331 (VPBROADCASTWYrm addr:$src)>;
8332 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8333 (VPBROADCASTDrm addr:$src)>;
8334 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8335 (VPBROADCASTDYrm addr:$src)>;
8336 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8337 (VPBROADCASTQrm addr:$src)>;
8338 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8339 (VPBROADCASTQYrm addr:$src)>;
8341 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8342 (VPBROADCASTBrr VR128:$src)>;
8343 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8344 (VPBROADCASTBYrr VR128:$src)>;
8345 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8346 (VPBROADCASTWrr VR128:$src)>;
8347 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8348 (VPBROADCASTWYrr VR128:$src)>;
8349 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8350 (VPBROADCASTDrr VR128:$src)>;
8351 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8352 (VPBROADCASTDYrr VR128:$src)>;
8353 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8354 (VPBROADCASTQrr VR128:$src)>;
8355 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8356 (VPBROADCASTQYrr VR128:$src)>;
8357 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8358 (VBROADCASTSSrr VR128:$src)>;
8359 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8360 (VBROADCASTSSYrr VR128:$src)>;
8361 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8362 (VPBROADCASTQrr VR128:$src)>;
8363 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8364 (VBROADCASTSDYrr VR128:$src)>;
8366 // Provide aliases for broadcast from the same register class that
8367 // automatically does the extract.
8368 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8369 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8371 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8372 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8374 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8375 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8377 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8378 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8380 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8381 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8383 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8384 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8387 // Provide fallback in case the load node that is used in the patterns above
8388 // is used by additional users, which prevents the pattern selection.
8389 let AddedComplexity = 20 in {
8390 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8391 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8392 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8393 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8394 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8395 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8397 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8398 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8399 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8400 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8401 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8402 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8404 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8405 (VPBROADCASTBrr (COPY_TO_REGCLASS
8406 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8408 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8409 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8410 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8413 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8414 (VPBROADCASTWrr (COPY_TO_REGCLASS
8415 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8417 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8418 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8419 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8422 // The patterns for VPBROADCASTD are not needed because they would match
8423 // the exact same thing as VBROADCASTSS patterns.
8425 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8426 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8427 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8431 // AVX1 broadcast patterns
8432 let Predicates = [HasAVX1Only] in {
8433 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8434 (VBROADCASTSSYrm addr:$src)>;
8435 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8436 (VBROADCASTSDYrm addr:$src)>;
8437 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8438 (VBROADCASTSSrm addr:$src)>;
8441 let Predicates = [HasAVX] in {
8442 // Provide fallback in case the load node that is used in the patterns above
8443 // is used by additional users, which prevents the pattern selection.
8444 let AddedComplexity = 20 in {
8445 // 128bit broadcasts:
8446 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8447 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8448 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8449 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8450 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8451 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8452 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8453 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8454 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8455 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8457 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8458 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8459 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8460 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8461 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8462 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8463 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8464 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8465 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8466 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8469 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8470 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8471 def : Pat<(v2i64 (X86VBroadcast i64:$src)),
8472 (VMOVDDUPrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8475 //===----------------------------------------------------------------------===//
8476 // VPERM - Permute instructions
8479 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8480 ValueType OpVT, X86FoldableSchedWrite Sched> {
8481 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8482 (ins VR256:$src1, VR256:$src2),
8483 !strconcat(OpcodeStr,
8484 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8486 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8487 Sched<[Sched]>, VEX_4V, VEX_L;
8488 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8489 (ins VR256:$src1, i256mem:$src2),
8490 !strconcat(OpcodeStr,
8491 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8493 (OpVT (X86VPermv VR256:$src1,
8494 (bitconvert (mem_frag addr:$src2)))))]>,
8495 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8498 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8499 let ExeDomain = SSEPackedSingle in
8500 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8502 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8503 ValueType OpVT, X86FoldableSchedWrite Sched> {
8504 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8505 (ins VR256:$src1, u8imm:$src2),
8506 !strconcat(OpcodeStr,
8507 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8509 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8510 Sched<[Sched]>, VEX, VEX_L;
8511 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8512 (ins i256mem:$src1, u8imm:$src2),
8513 !strconcat(OpcodeStr,
8514 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8516 (OpVT (X86VPermi (mem_frag addr:$src1),
8517 (i8 imm:$src2))))]>,
8518 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8521 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8522 WriteShuffle256>, VEX_W;
8523 let ExeDomain = SSEPackedDouble in
8524 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8525 WriteFShuffle256>, VEX_W;
8527 //===----------------------------------------------------------------------===//
8528 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8530 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8531 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8532 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8533 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8534 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8536 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8537 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8538 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8539 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8541 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8543 let Predicates = [HasAVX2] in {
8544 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8545 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8546 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8547 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8548 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8549 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8551 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8553 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8554 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8555 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8556 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8557 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8559 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8563 //===----------------------------------------------------------------------===//
8564 // VINSERTI128 - Insert packed integer values
8566 let hasSideEffects = 0 in {
8567 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8568 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8569 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8570 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8572 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8573 (ins VR256:$src1, i128mem:$src2, u8imm:$src3),
8574 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8575 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8578 let Predicates = [HasAVX2] in {
8579 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8581 (VINSERTI128rr VR256:$src1, VR128:$src2,
8582 (INSERT_get_vinsert128_imm VR256:$ins))>;
8583 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8585 (VINSERTI128rr VR256:$src1, VR128:$src2,
8586 (INSERT_get_vinsert128_imm VR256:$ins))>;
8587 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8589 (VINSERTI128rr VR256:$src1, VR128:$src2,
8590 (INSERT_get_vinsert128_imm VR256:$ins))>;
8591 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8593 (VINSERTI128rr VR256:$src1, VR128:$src2,
8594 (INSERT_get_vinsert128_imm VR256:$ins))>;
8596 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8598 (VINSERTI128rm VR256:$src1, addr:$src2,
8599 (INSERT_get_vinsert128_imm VR256:$ins))>;
8600 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8601 (bc_v4i32 (loadv2i64 addr:$src2)),
8603 (VINSERTI128rm VR256:$src1, addr:$src2,
8604 (INSERT_get_vinsert128_imm VR256:$ins))>;
8605 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8606 (bc_v16i8 (loadv2i64 addr:$src2)),
8608 (VINSERTI128rm VR256:$src1, addr:$src2,
8609 (INSERT_get_vinsert128_imm VR256:$ins))>;
8610 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8611 (bc_v8i16 (loadv2i64 addr:$src2)),
8613 (VINSERTI128rm VR256:$src1, addr:$src2,
8614 (INSERT_get_vinsert128_imm VR256:$ins))>;
8617 //===----------------------------------------------------------------------===//
8618 // VEXTRACTI128 - Extract packed integer values
8620 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8621 (ins VR256:$src1, u8imm:$src2),
8622 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8623 Sched<[WriteShuffle256]>, VEX, VEX_L;
8624 let hasSideEffects = 0, mayStore = 1 in
8625 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8626 (ins i128mem:$dst, VR256:$src1, u8imm:$src2),
8627 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8628 Sched<[WriteStore]>, VEX, VEX_L;
8630 let Predicates = [HasAVX2] in {
8631 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8632 (v2i64 (VEXTRACTI128rr
8633 (v4i64 VR256:$src1),
8634 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8635 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8636 (v4i32 (VEXTRACTI128rr
8637 (v8i32 VR256:$src1),
8638 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8639 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8640 (v8i16 (VEXTRACTI128rr
8641 (v16i16 VR256:$src1),
8642 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8643 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8644 (v16i8 (VEXTRACTI128rr
8645 (v32i8 VR256:$src1),
8646 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8648 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8649 (iPTR imm))), addr:$dst),
8650 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8651 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8652 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8653 (iPTR imm))), addr:$dst),
8654 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8655 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8656 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8657 (iPTR imm))), addr:$dst),
8658 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8659 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8660 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8661 (iPTR imm))), addr:$dst),
8662 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8663 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8666 //===----------------------------------------------------------------------===//
8667 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8669 multiclass avx2_pmovmask<string OpcodeStr,
8670 Intrinsic IntLd128, Intrinsic IntLd256,
8671 Intrinsic IntSt128, Intrinsic IntSt256> {
8672 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8673 (ins VR128:$src1, i128mem:$src2),
8674 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8675 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8676 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8677 (ins VR256:$src1, i256mem:$src2),
8678 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8679 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8681 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8682 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8683 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8684 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8685 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8686 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8687 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8688 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8691 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8692 int_x86_avx2_maskload_d,
8693 int_x86_avx2_maskload_d_256,
8694 int_x86_avx2_maskstore_d,
8695 int_x86_avx2_maskstore_d_256>;
8696 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8697 int_x86_avx2_maskload_q,
8698 int_x86_avx2_maskload_q_256,
8699 int_x86_avx2_maskstore_q,
8700 int_x86_avx2_maskstore_q_256>, VEX_W;
8702 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8703 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8705 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8706 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8708 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8709 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
8711 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
8712 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8714 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8715 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8717 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
8718 (bc_v8f32 (v8i32 immAllZerosV)))),
8719 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8721 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
8722 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
8725 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8726 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8728 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
8729 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8731 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
8732 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
8735 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8736 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8738 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
8739 (bc_v4f32 (v4i32 immAllZerosV)))),
8740 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8742 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
8743 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
8746 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8747 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8749 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
8750 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8752 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
8753 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
8756 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
8757 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8759 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
8760 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8762 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8763 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8765 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8766 (v4f64 immAllZerosV))),
8767 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8769 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
8770 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
8773 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8774 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8776 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8777 (bc_v4i64 (v8i32 immAllZerosV)))),
8778 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8780 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
8781 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
8784 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
8785 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8787 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
8788 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
8790 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8791 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8793 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8794 (v2f64 immAllZerosV))),
8795 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8797 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
8798 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
8801 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8802 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8804 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8805 (bc_v2i64 (v4i32 immAllZerosV)))),
8806 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8808 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
8809 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
8812 //===----------------------------------------------------------------------===//
8813 // Variable Bit Shifts
8815 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8816 ValueType vt128, ValueType vt256> {
8817 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8818 (ins VR128:$src1, VR128:$src2),
8819 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8821 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8822 VEX_4V, Sched<[WriteVarVecShift]>;
8823 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8824 (ins VR128:$src1, i128mem:$src2),
8825 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8827 (vt128 (OpNode VR128:$src1,
8828 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8829 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8830 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8831 (ins VR256:$src1, VR256:$src2),
8832 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8834 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8835 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
8836 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8837 (ins VR256:$src1, i256mem:$src2),
8838 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8840 (vt256 (OpNode VR256:$src1,
8841 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8842 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8845 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8846 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8847 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8848 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8849 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8851 //===----------------------------------------------------------------------===//
8852 // VGATHER - GATHER Operations
8853 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8854 X86MemOperand memop128, X86MemOperand memop256> {
8855 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8856 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8857 !strconcat(OpcodeStr,
8858 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8860 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8861 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8862 !strconcat(OpcodeStr,
8863 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8864 []>, VEX_4VOp3, VEX_L;
8867 let mayLoad = 1, Constraints
8868 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8870 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8871 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8872 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8873 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
8875 let ExeDomain = SSEPackedDouble in {
8876 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8877 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8880 let ExeDomain = SSEPackedSingle in {
8881 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8882 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;