1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
244 Domain d, OpndItins itins, bit Is2Addr = 1> {
245 let isCommutable = 1 in {
246 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
250 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr, d>,
251 Sched<[itins.Sched]>;
253 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
255 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
257 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm, d>,
258 Sched<[itins.Sched.Folded, ReadAfterLd]>;
261 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
262 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
263 string asm, string SSEVer, string FPSizeStr,
264 Operand memopr, ComplexPattern mem_cpat,
265 Domain d, OpndItins itins, bit Is2Addr = 1> {
266 let isCodeGenOnly = 1 in {
267 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
269 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
271 [(set RC:$dst, (!cast<Intrinsic>(
272 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
273 RC:$src1, RC:$src2))], itins.rr, d>,
274 Sched<[itins.Sched]>;
275 def rm_Int : SI_Int<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
277 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
278 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
279 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
280 SSEVer, "_", OpcodeStr, FPSizeStr))
281 RC:$src1, mem_cpat:$src2))], itins.rm, d>,
282 Sched<[itins.Sched.Folded, ReadAfterLd]>;
286 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
287 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
288 RegisterClass RC, ValueType vt,
289 X86MemOperand x86memop, PatFrag mem_frag,
290 Domain d, OpndItins itins, bit Is2Addr = 1> {
291 let isCommutable = 1 in
292 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
296 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
297 Sched<[itins.Sched]>;
299 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
301 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
302 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
303 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
305 Sched<[itins.Sched.Folded, ReadAfterLd]>;
308 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
309 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
310 string OpcodeStr, X86MemOperand x86memop,
311 list<dag> pat_rr, list<dag> pat_rm,
313 let isCommutable = 1, hasSideEffects = 0 in
314 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
316 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
318 pat_rr, NoItinerary, d>,
319 Sched<[WriteVecLogic]>;
320 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
324 pat_rm, NoItinerary, d>,
325 Sched<[WriteVecLogicLd, ReadAfterLd]>;
328 //===----------------------------------------------------------------------===//
329 // Non-instruction patterns
330 //===----------------------------------------------------------------------===//
332 // A vector extract of the first f32/f64 position is a subregister copy
333 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
335 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
338 // A 128-bit subvector extract from the first 256-bit vector position
339 // is a subregister copy that needs no instruction.
340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
341 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
343 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
346 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
348 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
351 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
353 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
355 // A 128-bit subvector insert to the first 256-bit vector position
356 // is a subregister copy that needs no instruction.
357 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
372 // Implicitly promote a 32-bit scalar to a vector.
373 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
374 (COPY_TO_REGCLASS FR32:$src, VR128)>;
375 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 // Implicitly promote a 64-bit scalar to a vector.
378 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
379 (COPY_TO_REGCLASS FR64:$src, VR128)>;
380 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
383 // Bitcasts between 128-bit vector types. Return the original type since
384 // no instruction is needed for the conversion
385 let Predicates = [HasSSE2] in {
386 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
387 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
388 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
392 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
397 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
402 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
407 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
412 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
418 // Bitcasts between 256-bit vector types. Return the original type since
419 // no instruction is needed for the conversion
420 let Predicates = [HasAVX] in {
421 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
422 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
423 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
427 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
432 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
437 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
442 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
447 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
453 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
454 // This is expanded by ExpandPostRAPseudos.
455 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
456 isPseudo = 1, SchedRW = [WriteZero] in {
457 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
458 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
459 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
460 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
463 //===----------------------------------------------------------------------===//
464 // AVX & SSE - Zero/One Vectors
465 //===----------------------------------------------------------------------===//
467 // Alias instruction that maps zero vector to pxor / xorp* for sse.
468 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
469 // swizzled by ExecutionDepsFix to pxor.
470 // We set canFoldAsLoad because this can be converted to a constant-pool
471 // load of an all-zeros value if folding it would be beneficial.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
473 isPseudo = 1, SchedRW = [WriteZero] in {
474 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
475 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
478 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
479 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
480 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
482 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
485 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
486 // and doesn't need it because on sandy bridge the register is set to zero
487 // at the rename stage without using any execution unit, so SET0PSY
488 // and SET0PDY can be used for vector int instructions without penalty
489 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
490 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
491 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
492 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
495 let Predicates = [HasAVX] in
496 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
498 let Predicates = [HasAVX2] in {
499 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
500 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
501 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
505 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
506 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
507 let Predicates = [HasAVX1Only] in {
508 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
509 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
510 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
512 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
513 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
514 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
516 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
517 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
518 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
520 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
521 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
522 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
525 // We set canFoldAsLoad because this can be converted to a constant-pool
526 // load of an all-ones value if folding it would be beneficial.
527 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
528 isPseudo = 1, SchedRW = [WriteZero] in {
529 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
530 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
531 let Predicates = [HasAVX2] in
532 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
533 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
537 //===----------------------------------------------------------------------===//
538 // SSE 1 & 2 - Move FP Scalar Instructions
540 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
541 // register copies because it's a partial register update; Register-to-register
542 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
543 // that the insert be implementable in terms of a copy, and just mentioned, we
544 // don't use movss/movsd for copies.
545 //===----------------------------------------------------------------------===//
547 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
548 X86MemOperand x86memop, string base_opc,
549 string asm_opr, Domain d = GenericDomain> {
550 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
551 (ins VR128:$src1, RC:$src2),
552 !strconcat(base_opc, asm_opr),
553 [(set VR128:$dst, (vt (OpNode VR128:$src1,
554 (scalar_to_vector RC:$src2))))],
555 IIC_SSE_MOV_S_RR, d>, Sched<[WriteFShuffle]>;
557 // For the disassembler
558 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
559 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
560 (ins VR128:$src1, RC:$src2),
561 !strconcat(base_opc, asm_opr),
562 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
565 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
566 X86MemOperand x86memop, string OpcodeStr,
567 Domain d = GenericDomain> {
569 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
570 "\t{$src2, $src1, $dst|$dst, $src1, $src2}", d>,
573 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
575 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
576 VEX, VEX_LIG, Sched<[WriteStore]>;
578 let Constraints = "$src1 = $dst" in {
579 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
580 "\t{$src2, $dst|$dst, $src2}", d>;
583 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
585 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
589 // Loading from memory automatically zeroing upper bits.
590 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
591 PatFrag mem_pat, string OpcodeStr,
592 Domain d = GenericDomain> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM, d>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM, d>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
604 SSEPackedSingle>, XS;
605 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd",
606 SSEPackedDouble>, XD;
608 let canFoldAsLoad = 1, isReMaterializable = 1 in {
609 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss",
610 SSEPackedSingle>, XS;
612 let AddedComplexity = 20 in
613 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd",
614 SSEPackedDouble>, XD;
618 let Predicates = [UseAVX] in {
619 let AddedComplexity = 20 in {
620 // MOVSSrm zeros the high parts of the register; represent this
621 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
622 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
624 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
625 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
626 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
627 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
629 // MOVSDrm zeros the high parts of the register; represent this
630 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
631 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
633 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
637 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
638 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
639 def : Pat<(v2f64 (X86vzload addr:$src)),
640 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
642 // Represent the same patterns above but in the form they appear for
644 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
645 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
646 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
647 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
648 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
649 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
652 // Extract and store.
653 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
655 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
656 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
658 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
660 // Shuffle with VMOVSS
661 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
662 (VMOVSSrr (v4i32 VR128:$src1),
663 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
664 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
665 (VMOVSSrr (v4f32 VR128:$src1),
666 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
669 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
670 (SUBREG_TO_REG (i32 0),
671 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
672 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
674 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
675 (SUBREG_TO_REG (i32 0),
676 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
677 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
680 // Shuffle with VMOVSD
681 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
682 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
683 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
691 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
694 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
696 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
697 (SUBREG_TO_REG (i32 0),
698 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
699 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
702 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
703 // is during lowering, where it's not possible to recognize the fold cause
704 // it has two uses through a bitcast. One use disappears at isel time and the
705 // fold opportunity reappears.
706 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
707 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
708 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
716 let Predicates = [UseSSE1] in {
717 let Predicates = [NoSSE41], AddedComplexity = 15 in {
718 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
719 // MOVSS to the lower bits.
720 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
721 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
722 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
723 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
728 let AddedComplexity = 20 in {
729 // MOVSSrm already zeros the high parts of the register.
730 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
731 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
732 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
738 // Extract and store.
739 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
741 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
743 // Shuffle with MOVSS
744 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
745 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
746 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
750 let Predicates = [UseSSE2] in {
751 let Predicates = [NoSSE41], AddedComplexity = 15 in {
752 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
753 // MOVSD to the lower bits.
754 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
755 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
758 let AddedComplexity = 20 in {
759 // MOVSDrm already zeros the high parts of the register.
760 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
761 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
762 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzload addr:$src)),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
772 // Extract and store.
773 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
775 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
777 // Shuffle with MOVSD
778 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
779 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
780 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
788 // is during lowering, where it's not possible to recognize the fold because
789 // it has two uses through a bitcast. One use disappears at isel time and the
790 // fold opportunity reappears.
791 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
793 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
801 //===----------------------------------------------------------------------===//
802 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
803 //===----------------------------------------------------------------------===//
805 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
806 X86MemOperand x86memop, PatFrag ld_frag,
807 string asm, Domain d,
809 bit IsReMaterializable = 1> {
810 let hasSideEffects = 0 in
811 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
812 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
813 Sched<[WriteFShuffle]>;
814 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
815 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
816 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
817 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
821 let Predicates = [HasAVX, NoVLX] in {
822 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
823 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
825 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
826 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
828 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
829 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
831 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
832 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
836 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
838 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
839 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
841 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
842 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
844 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
845 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
849 let Predicates = [UseSSE1] in {
850 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
851 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
853 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
854 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
857 let Predicates = [UseSSE2] in {
858 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
859 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
861 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
862 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
867 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
868 "movaps\t{$src, $dst|$dst, $src}",
869 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
870 IIC_SSE_MOVA_P_MR>, VEX;
871 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
872 "movapd\t{$src, $dst|$dst, $src}",
873 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
874 IIC_SSE_MOVA_P_MR>, VEX;
875 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
876 "movups\t{$src, $dst|$dst, $src}",
877 [(store (v4f32 VR128:$src), addr:$dst)],
878 IIC_SSE_MOVU_P_MR>, VEX;
879 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
880 "movupd\t{$src, $dst|$dst, $src}",
881 [(store (v2f64 VR128:$src), addr:$dst)],
882 IIC_SSE_MOVU_P_MR>, VEX;
883 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
884 "movaps\t{$src, $dst|$dst, $src}",
885 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
886 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
887 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
888 "movapd\t{$src, $dst|$dst, $src}",
889 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
890 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
891 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
892 "movups\t{$src, $dst|$dst, $src}",
893 [(store (v8f32 VR256:$src), addr:$dst)],
894 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
895 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
896 "movupd\t{$src, $dst|$dst, $src}",
897 [(store (v4f64 VR256:$src), addr:$dst)],
898 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
902 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
903 SchedRW = [WriteFShuffle] in {
904 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
906 "movaps\t{$src, $dst|$dst, $src}", [],
907 IIC_SSE_MOVA_P_RR>, VEX;
908 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
910 "movapd\t{$src, $dst|$dst, $src}", [],
911 IIC_SSE_MOVA_P_RR>, VEX;
912 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
914 "movups\t{$src, $dst|$dst, $src}", [],
915 IIC_SSE_MOVU_P_RR>, VEX;
916 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
918 "movupd\t{$src, $dst|$dst, $src}", [],
919 IIC_SSE_MOVU_P_RR>, VEX;
920 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
922 "movaps\t{$src, $dst|$dst, $src}", [],
923 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
924 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
926 "movapd\t{$src, $dst|$dst, $src}", [],
927 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
928 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
930 "movups\t{$src, $dst|$dst, $src}", [],
931 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
932 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
934 "movupd\t{$src, $dst|$dst, $src}", [],
935 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
938 let Predicates = [HasAVX] in {
939 def : Pat<(v8i32 (X86vzmovl
940 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v4i64 (X86vzmovl
943 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v8f32 (X86vzmovl
946 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
948 def : Pat<(v4f64 (X86vzmovl
949 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
950 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
954 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
955 (VMOVUPSYmr addr:$dst, VR256:$src)>;
956 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
957 (VMOVUPDYmr addr:$dst, VR256:$src)>;
959 let SchedRW = [WriteStore] in {
960 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movaps\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
964 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movapd\t{$src, $dst|$dst, $src}",
966 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
968 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movups\t{$src, $dst|$dst, $src}",
970 [(store (v4f32 VR128:$src), addr:$dst)],
972 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
973 "movupd\t{$src, $dst|$dst, $src}",
974 [(store (v2f64 VR128:$src), addr:$dst)],
979 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
980 SchedRW = [WriteFShuffle] in {
981 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movaps\t{$src, $dst|$dst, $src}", [],
984 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movapd\t{$src, $dst|$dst, $src}", [],
987 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
988 "movups\t{$src, $dst|$dst, $src}", [],
990 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
991 "movupd\t{$src, $dst|$dst, $src}", [],
995 let Predicates = [HasAVX] in {
996 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
997 (VMOVUPSmr addr:$dst, VR128:$src)>;
998 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
999 (VMOVUPDmr addr:$dst, VR128:$src)>;
1002 let Predicates = [UseSSE1] in
1003 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1004 (MOVUPSmr addr:$dst, VR128:$src)>;
1005 let Predicates = [UseSSE2] in
1006 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1007 (MOVUPDmr addr:$dst, VR128:$src)>;
1009 // Use vmovaps/vmovups for AVX integer load/store.
1010 let Predicates = [HasAVX, NoVLX] in {
1011 // 128-bit load/store
1012 def : Pat<(alignedloadv2i64 addr:$src),
1013 (VMOVAPSrm addr:$src)>;
1014 def : Pat<(loadv2i64 addr:$src),
1015 (VMOVUPSrm addr:$src)>;
1017 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1020 (VMOVAPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1022 (VMOVAPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1024 (VMOVAPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1028 (VMOVUPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1030 (VMOVUPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1032 (VMOVUPSmr addr:$dst, VR128:$src)>;
1034 // 256-bit load/store
1035 def : Pat<(alignedloadv4i64 addr:$src),
1036 (VMOVAPSYrm addr:$src)>;
1037 def : Pat<(loadv4i64 addr:$src),
1038 (VMOVUPSYrm addr:$src)>;
1039 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1042 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1044 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1046 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1050 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1052 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1054 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1056 // Special patterns for storing subvector extracts of lower 128-bits
1057 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1058 def : Pat<(alignedstore (v2f64 (extract_subvector
1059 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1061 def : Pat<(alignedstore (v4f32 (extract_subvector
1062 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1063 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 def : Pat<(alignedstore (v2i64 (extract_subvector
1065 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1066 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1067 def : Pat<(alignedstore (v4i32 (extract_subvector
1068 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1069 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1070 def : Pat<(alignedstore (v8i16 (extract_subvector
1071 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1072 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1073 def : Pat<(alignedstore (v16i8 (extract_subvector
1074 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1075 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1077 def : Pat<(store (v2f64 (extract_subvector
1078 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1079 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1080 def : Pat<(store (v4f32 (extract_subvector
1081 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1082 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1083 def : Pat<(store (v2i64 (extract_subvector
1084 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1085 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1086 def : Pat<(store (v4i32 (extract_subvector
1087 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1088 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1089 def : Pat<(store (v8i16 (extract_subvector
1090 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1091 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1092 def : Pat<(store (v16i8 (extract_subvector
1093 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1094 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1097 // Use movaps / movups for SSE integer load / store (one byte shorter).
1098 // The instructions selected below are then converted to MOVDQA/MOVDQU
1099 // during the SSE domain pass.
1100 let Predicates = [UseSSE1] in {
1101 def : Pat<(alignedloadv2i64 addr:$src),
1102 (MOVAPSrm addr:$src)>;
1103 def : Pat<(loadv2i64 addr:$src),
1104 (MOVUPSrm addr:$src)>;
1106 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1107 (MOVAPSmr addr:$dst, VR128:$src)>;
1108 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1109 (MOVAPSmr addr:$dst, VR128:$src)>;
1110 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1111 (MOVAPSmr addr:$dst, VR128:$src)>;
1112 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1113 (MOVAPSmr addr:$dst, VR128:$src)>;
1114 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1115 (MOVUPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1117 (MOVUPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1119 (MOVUPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1121 (MOVUPSmr addr:$dst, VR128:$src)>;
1124 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1125 // bits are disregarded. FIXME: Set encoding to pseudo!
1126 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1127 let isCodeGenOnly = 1 in {
1128 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1129 "movaps\t{$src, $dst|$dst, $src}",
1130 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1131 IIC_SSE_MOVA_P_RM>, VEX;
1132 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1133 "movapd\t{$src, $dst|$dst, $src}",
1134 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1135 IIC_SSE_MOVA_P_RM>, VEX;
1136 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1137 "movaps\t{$src, $dst|$dst, $src}",
1138 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1140 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1141 "movapd\t{$src, $dst|$dst, $src}",
1142 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1147 //===----------------------------------------------------------------------===//
1148 // SSE 1 & 2 - Move Low packed FP Instructions
1149 //===----------------------------------------------------------------------===//
1151 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1152 string base_opc, string asm_opr,
1153 InstrItinClass itin> {
1154 def PSrm : PI<opc, MRMSrcMem,
1155 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1156 !strconcat(base_opc, "s", asm_opr),
1158 (psnode VR128:$src1,
1159 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1160 itin, SSEPackedSingle>, PS,
1161 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1163 def PDrm : PI<opc, MRMSrcMem,
1164 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1165 !strconcat(base_opc, "d", asm_opr),
1166 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1167 (scalar_to_vector (loadf64 addr:$src2)))))],
1168 itin, SSEPackedDouble>, PD,
1169 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1173 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1174 string base_opc, InstrItinClass itin> {
1175 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1176 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1179 let Constraints = "$src1 = $dst" in
1180 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1181 "\t{$src2, $dst|$dst, $src2}",
1185 let AddedComplexity = 20 in {
1186 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1190 let SchedRW = [WriteStore] in {
1191 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1192 "movlps\t{$src, $dst|$dst, $src}",
1193 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1194 (iPTR 0))), addr:$dst)],
1195 IIC_SSE_MOV_LH>, VEX;
1196 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1197 "movlpd\t{$src, $dst|$dst, $src}",
1198 [(store (f64 (vector_extract (v2f64 VR128:$src),
1199 (iPTR 0))), addr:$dst)],
1200 IIC_SSE_MOV_LH>, VEX;
1201 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1202 "movlps\t{$src, $dst|$dst, $src}",
1203 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1204 (iPTR 0))), addr:$dst)],
1206 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1207 "movlpd\t{$src, $dst|$dst, $src}",
1208 [(store (f64 (vector_extract (v2f64 VR128:$src),
1209 (iPTR 0))), addr:$dst)],
1213 let Predicates = [HasAVX] in {
1214 // Shuffle with VMOVLPS
1215 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1216 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1218 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1220 // Shuffle with VMOVLPD
1221 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1222 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1223 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1224 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1226 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1227 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1232 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1233 def : Pat<(store (v4i32 (X86Movlps
1234 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1235 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1236 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1238 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1239 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1241 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1244 let Predicates = [UseSSE1] in {
1245 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1246 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1247 (iPTR 0))), addr:$src1),
1248 (MOVLPSmr addr:$src1, VR128:$src2)>;
1250 // Shuffle with MOVLPS
1251 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1252 (MOVLPSrm VR128:$src1, addr:$src2)>;
1253 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1254 (MOVLPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(X86Movlps VR128:$src1,
1256 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1257 (MOVLPSrm VR128:$src1, addr:$src2)>;
1260 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1262 (MOVLPSmr addr:$src1, VR128:$src2)>;
1263 def : Pat<(store (v4i32 (X86Movlps
1264 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1266 (MOVLPSmr addr:$src1, VR128:$src2)>;
1269 let Predicates = [UseSSE2] in {
1270 // Shuffle with MOVLPD
1271 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1272 (MOVLPDrm VR128:$src1, addr:$src2)>;
1273 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1274 (MOVLPDrm VR128:$src1, addr:$src2)>;
1275 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1276 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1277 (MOVLPDrm VR128:$src1, addr:$src2)>;
1280 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1282 (MOVLPDmr addr:$src1, VR128:$src2)>;
1283 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1285 (MOVLPDmr addr:$src1, VR128:$src2)>;
1288 //===----------------------------------------------------------------------===//
1289 // SSE 1 & 2 - Move Hi packed FP Instructions
1290 //===----------------------------------------------------------------------===//
1292 let AddedComplexity = 20 in {
1293 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1297 let SchedRW = [WriteStore] in {
1298 // v2f64 extract element 1 is always custom lowered to unpack high to low
1299 // and extract element 0 so the non-store version isn't too horrible.
1300 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1301 "movhps\t{$src, $dst|$dst, $src}",
1302 [(store (f64 (vector_extract
1303 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1304 (bc_v2f64 (v4f32 VR128:$src))),
1305 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1306 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1307 "movhpd\t{$src, $dst|$dst, $src}",
1308 [(store (f64 (vector_extract
1309 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1310 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1311 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1312 "movhps\t{$src, $dst|$dst, $src}",
1313 [(store (f64 (vector_extract
1314 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1315 (bc_v2f64 (v4f32 VR128:$src))),
1316 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1317 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1318 "movhpd\t{$src, $dst|$dst, $src}",
1319 [(store (f64 (vector_extract
1320 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1321 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1324 let Predicates = [HasAVX] in {
1326 def : Pat<(X86Movlhps VR128:$src1,
1327 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1328 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1329 def : Pat<(X86Movlhps VR128:$src1,
1330 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1331 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1335 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1336 // is during lowering, where it's not possible to recognize the load fold
1337 // cause it has two uses through a bitcast. One use disappears at isel time
1338 // and the fold opportunity reappears.
1339 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1340 (scalar_to_vector (loadf64 addr:$src2)))),
1341 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1342 // Also handle an i64 load because that may get selected as a faster way to
1344 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1345 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1346 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1348 def : Pat<(store (f64 (vector_extract
1349 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1350 (iPTR 0))), addr:$dst),
1351 (VMOVHPDmr addr:$dst, VR128:$src)>;
1354 let Predicates = [UseSSE1] in {
1356 def : Pat<(X86Movlhps VR128:$src1,
1357 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1358 (MOVHPSrm VR128:$src1, addr:$src2)>;
1359 def : Pat<(X86Movlhps VR128:$src1,
1360 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1361 (MOVHPSrm VR128:$src1, addr:$src2)>;
1364 let Predicates = [UseSSE2] in {
1367 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1368 // is during lowering, where it's not possible to recognize the load fold
1369 // cause it has two uses through a bitcast. One use disappears at isel time
1370 // and the fold opportunity reappears.
1371 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1372 (scalar_to_vector (loadf64 addr:$src2)))),
1373 (MOVHPDrm VR128:$src1, addr:$src2)>;
1374 // Also handle an i64 load because that may get selected as a faster way to
1376 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1377 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1378 (MOVHPDrm VR128:$src1, addr:$src2)>;
1380 def : Pat<(store (f64 (vector_extract
1381 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1382 (iPTR 0))), addr:$dst),
1383 (MOVHPDmr addr:$dst, VR128:$src)>;
1386 //===----------------------------------------------------------------------===//
1387 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1388 //===----------------------------------------------------------------------===//
1390 let AddedComplexity = 20, Predicates = [UseAVX] in {
1391 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1392 (ins VR128:$src1, VR128:$src2),
1393 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1395 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1397 VEX_4V, Sched<[WriteFShuffle]>;
1398 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1399 (ins VR128:$src1, VR128:$src2),
1400 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1402 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1404 VEX_4V, Sched<[WriteFShuffle]>;
1406 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1407 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1408 (ins VR128:$src1, VR128:$src2),
1409 "movlhps\t{$src2, $dst|$dst, $src2}",
1411 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1412 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1413 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1414 (ins VR128:$src1, VR128:$src2),
1415 "movhlps\t{$src2, $dst|$dst, $src2}",
1417 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1418 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1421 let Predicates = [UseAVX] in {
1423 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1424 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1425 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1426 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1429 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1430 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1433 let Predicates = [UseSSE1] in {
1435 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1436 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1437 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1438 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1441 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1442 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1445 //===----------------------------------------------------------------------===//
1446 // SSE 1 & 2 - Conversion Instructions
1447 //===----------------------------------------------------------------------===//
1449 def SSE_CVT_PD : OpndItins<
1450 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1453 let Sched = WriteCvtI2F in
1454 def SSE_CVT_PS : OpndItins<
1455 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1458 let Sched = WriteCvtI2F in
1459 def SSE_CVT_Scalar : OpndItins<
1460 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1463 let Sched = WriteCvtF2I in
1464 def SSE_CVT_SS2SI_32 : OpndItins<
1465 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1468 let Sched = WriteCvtF2I in
1469 def SSE_CVT_SS2SI_64 : OpndItins<
1470 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1473 let Sched = WriteCvtF2I in
1474 def SSE_CVT_SD2SI : OpndItins<
1475 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1478 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1479 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1480 string asm, OpndItins itins> {
1481 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1482 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1483 itins.rr>, Sched<[itins.Sched]>;
1484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1485 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1486 itins.rm>, Sched<[itins.Sched.Folded]>;
1489 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1490 X86MemOperand x86memop, string asm, Domain d,
1492 let hasSideEffects = 0 in {
1493 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1494 [], itins.rr, d>, Sched<[itins.Sched]>;
1496 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1497 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1501 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1502 X86MemOperand x86memop, string asm> {
1503 let hasSideEffects = 0, Predicates = [UseAVX] in {
1504 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1505 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1506 Sched<[WriteCvtI2F]>;
1508 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1509 (ins DstRC:$src1, x86memop:$src),
1510 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1511 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1512 } // hasSideEffects = 0
1515 let Predicates = [UseAVX] in {
1516 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1517 "cvttss2si\t{$src, $dst|$dst, $src}",
1520 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1521 "cvttss2si\t{$src, $dst|$dst, $src}",
1523 XS, VEX, VEX_W, VEX_LIG;
1524 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1525 "cvttsd2si\t{$src, $dst|$dst, $src}",
1528 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1529 "cvttsd2si\t{$src, $dst|$dst, $src}",
1531 XD, VEX, VEX_W, VEX_LIG;
1533 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1534 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1535 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1536 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1537 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1538 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1539 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1540 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1541 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1542 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1543 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1545 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1550 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1551 // register, but the same isn't true when only using memory operands,
1552 // provide other assembly "l" and "q" forms to address this explicitly
1553 // where appropriate to do so.
1554 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1555 XS, VEX_4V, VEX_LIG;
1556 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1557 XS, VEX_4V, VEX_W, VEX_LIG;
1558 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1559 XD, VEX_4V, VEX_LIG;
1560 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1561 XD, VEX_4V, VEX_W, VEX_LIG;
1563 let Predicates = [UseAVX] in {
1564 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1565 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1566 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1567 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1569 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1570 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1571 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1572 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1573 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1574 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1575 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1576 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1578 def : Pat<(f32 (sint_to_fp GR32:$src)),
1579 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1580 def : Pat<(f32 (sint_to_fp GR64:$src)),
1581 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1582 def : Pat<(f64 (sint_to_fp GR32:$src)),
1583 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1584 def : Pat<(f64 (sint_to_fp GR64:$src)),
1585 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1588 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1589 "cvttss2si\t{$src, $dst|$dst, $src}",
1590 SSE_CVT_SS2SI_32>, XS;
1591 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1592 "cvttss2si\t{$src, $dst|$dst, $src}",
1593 SSE_CVT_SS2SI_64>, XS, REX_W;
1594 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1595 "cvttsd2si\t{$src, $dst|$dst, $src}",
1597 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1598 "cvttsd2si\t{$src, $dst|$dst, $src}",
1599 SSE_CVT_SD2SI>, XD, REX_W;
1600 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1601 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1602 SSE_CVT_Scalar>, XS;
1603 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1604 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1605 SSE_CVT_Scalar>, XS, REX_W;
1606 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1607 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1608 SSE_CVT_Scalar>, XD;
1609 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1610 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1611 SSE_CVT_Scalar>, XD, REX_W;
1613 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1614 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1615 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1616 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1617 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1618 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1619 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1620 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1621 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1622 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1623 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1625 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1626 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1627 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1630 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1631 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1632 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1633 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1635 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1636 // and/or XMM operand(s).
1638 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1639 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1640 string asm, OpndItins itins> {
1641 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1642 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1643 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1644 Sched<[itins.Sched]>;
1645 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1646 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1647 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1648 Sched<[itins.Sched.Folded]>;
1651 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1652 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1653 PatFrag ld_frag, string asm, OpndItins itins,
1655 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1657 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1658 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1659 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1660 itins.rr>, Sched<[itins.Sched]>;
1661 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1662 (ins DstRC:$src1, x86memop:$src2),
1664 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1665 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1666 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1667 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1670 let Predicates = [UseAVX] in {
1671 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1672 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1673 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1674 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1675 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1676 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1678 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1679 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1680 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1681 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1684 let isCodeGenOnly = 1 in {
1685 let Predicates = [UseAVX] in {
1686 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1687 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1688 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1689 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1690 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1691 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1693 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1694 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1695 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1696 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1697 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1698 SSE_CVT_Scalar, 0>, XD,
1701 let Constraints = "$src1 = $dst" in {
1702 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1703 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1704 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1705 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1706 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1707 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1708 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1709 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1710 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1711 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1712 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1713 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1715 } // isCodeGenOnly = 1
1719 // Aliases for intrinsics
1720 let isCodeGenOnly = 1 in {
1721 let Predicates = [UseAVX] in {
1722 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1723 ssmem, sse_load_f32, "cvttss2si",
1724 SSE_CVT_SS2SI_32>, XS, VEX;
1725 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1726 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1727 "cvttss2si", SSE_CVT_SS2SI_64>,
1729 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1730 sdmem, sse_load_f64, "cvttsd2si",
1731 SSE_CVT_SD2SI>, XD, VEX;
1732 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1733 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1734 "cvttsd2si", SSE_CVT_SD2SI>,
1737 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1738 ssmem, sse_load_f32, "cvttss2si",
1739 SSE_CVT_SS2SI_32>, XS;
1740 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1741 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1742 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1743 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1744 sdmem, sse_load_f64, "cvttsd2si",
1746 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1747 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1748 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1749 } // isCodeGenOnly = 1
1751 let Predicates = [UseAVX] in {
1752 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1753 ssmem, sse_load_f32, "cvtss2si",
1754 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1755 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1756 ssmem, sse_load_f32, "cvtss2si",
1757 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1759 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1760 ssmem, sse_load_f32, "cvtss2si",
1761 SSE_CVT_SS2SI_32>, XS;
1762 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1763 ssmem, sse_load_f32, "cvtss2si",
1764 SSE_CVT_SS2SI_64>, XS, REX_W;
1766 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1767 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1768 SSEPackedSingle, SSE_CVT_PS>,
1769 PS, VEX, Requires<[HasAVX]>;
1770 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1771 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1772 SSEPackedSingle, SSE_CVT_PS>,
1773 PS, VEX, VEX_L, Requires<[HasAVX]>;
1775 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1776 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1777 SSEPackedSingle, SSE_CVT_PS>,
1778 PS, Requires<[UseSSE2]>;
1780 let Predicates = [UseAVX] in {
1781 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1782 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1783 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1784 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1785 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1786 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1787 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1788 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1789 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1790 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1791 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1793 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1794 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1799 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1800 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1801 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1802 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1803 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1804 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1805 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1806 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1807 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1808 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1809 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1811 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1812 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1813 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1818 // Convert scalar double to scalar single
1819 let hasSideEffects = 0, Predicates = [UseAVX] in {
1820 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1821 (ins FR64:$src1, FR64:$src2),
1822 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1823 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1824 Sched<[WriteCvtF2F]>;
1826 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1827 (ins FR64:$src1, f64mem:$src2),
1828 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1829 [], IIC_SSE_CVT_Scalar_RM>,
1830 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1831 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1834 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1837 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1838 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1839 [(set FR32:$dst, (fround FR64:$src))],
1840 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1841 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1842 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1843 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1844 IIC_SSE_CVT_Scalar_RM>,
1846 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1848 let isCodeGenOnly = 1 in {
1849 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1850 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1851 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1853 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1854 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,
1855 Sched<[WriteCvtF2F]>;
1856 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1857 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1858 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1859 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1860 VR128:$src1, sse_load_f64:$src2))],
1861 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>,
1862 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1864 let Constraints = "$src1 = $dst" in {
1865 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1866 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1867 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1869 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1870 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1871 Sched<[WriteCvtF2F]>;
1872 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1873 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1874 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1875 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1876 VR128:$src1, sse_load_f64:$src2))],
1877 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1878 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1880 } // isCodeGenOnly = 1
1882 // Convert scalar single to scalar double
1883 // SSE2 instructions with XS prefix
1884 let hasSideEffects = 0, Predicates = [UseAVX] in {
1885 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1886 (ins FR32:$src1, FR32:$src2),
1887 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1888 [], IIC_SSE_CVT_Scalar_RR>,
1889 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1890 Sched<[WriteCvtF2F]>;
1892 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1893 (ins FR32:$src1, f32mem:$src2),
1894 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1895 [], IIC_SSE_CVT_Scalar_RM>,
1896 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1897 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1900 def : Pat<(f64 (fextend FR32:$src)),
1901 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1902 def : Pat<(fextend (loadf32 addr:$src)),
1903 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1905 def : Pat<(extloadf32 addr:$src),
1906 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1907 Requires<[UseAVX, OptForSize]>;
1908 def : Pat<(extloadf32 addr:$src),
1909 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1910 Requires<[UseAVX, OptForSpeed]>;
1912 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1913 "cvtss2sd\t{$src, $dst|$dst, $src}",
1914 [(set FR64:$dst, (fextend FR32:$src))],
1915 IIC_SSE_CVT_Scalar_RR>, XS,
1916 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1917 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1918 "cvtss2sd\t{$src, $dst|$dst, $src}",
1919 [(set FR64:$dst, (extloadf32 addr:$src))],
1920 IIC_SSE_CVT_Scalar_RM>, XS,
1921 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1923 // extload f32 -> f64. This matches load+fextend because we have a hack in
1924 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1926 // Since these loads aren't folded into the fextend, we have to match it
1928 def : Pat<(fextend (loadf32 addr:$src)),
1929 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1930 def : Pat<(extloadf32 addr:$src),
1931 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1933 let isCodeGenOnly = 1 in {
1934 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1935 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1936 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1938 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1939 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>,
1940 Sched<[WriteCvtF2F]>;
1941 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1942 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1943 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1945 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1946 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>,
1947 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1948 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1949 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1950 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1951 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1953 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1954 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1955 Sched<[WriteCvtF2F]>;
1956 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1957 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1958 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1960 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1961 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1962 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1964 } // isCodeGenOnly = 1
1966 // Convert packed single/double fp to doubleword
1967 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1968 "cvtps2dq\t{$src, $dst|$dst, $src}",
1969 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1970 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1971 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1972 "cvtps2dq\t{$src, $dst|$dst, $src}",
1974 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1975 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1976 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1977 "cvtps2dq\t{$src, $dst|$dst, $src}",
1979 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1980 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1981 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1982 "cvtps2dq\t{$src, $dst|$dst, $src}",
1984 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1985 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1986 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 "cvtps2dq\t{$src, $dst|$dst, $src}",
1988 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1989 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1990 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1991 "cvtps2dq\t{$src, $dst|$dst, $src}",
1993 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1994 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1997 // Convert Packed Double FP to Packed DW Integers
1998 let Predicates = [HasAVX] in {
1999 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2000 // register, but the same isn't true when using memory operands instead.
2001 // Provide other assembly rr and rm forms to address this explicitly.
2002 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2003 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2004 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2005 VEX, Sched<[WriteCvtF2I]>;
2008 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2009 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2010 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2011 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2013 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2014 Sched<[WriteCvtF2ILd]>;
2017 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2018 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2020 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2021 Sched<[WriteCvtF2I]>;
2022 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2023 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2025 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2026 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2027 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2028 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2031 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2032 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2034 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2035 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2036 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2037 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2038 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2039 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2041 // Convert with truncation packed single/double fp to doubleword
2042 // SSE2 packed instructions with XS prefix
2043 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "cvttps2dq\t{$src, $dst|$dst, $src}",
2046 (int_x86_sse2_cvttps2dq VR128:$src))],
2047 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2048 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2049 "cvttps2dq\t{$src, $dst|$dst, $src}",
2050 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2051 (loadv4f32 addr:$src)))],
2052 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2053 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2054 "cvttps2dq\t{$src, $dst|$dst, $src}",
2056 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2057 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2058 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2059 "cvttps2dq\t{$src, $dst|$dst, $src}",
2060 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2061 (loadv8f32 addr:$src)))],
2062 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2063 Sched<[WriteCvtF2ILd]>;
2065 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2066 "cvttps2dq\t{$src, $dst|$dst, $src}",
2067 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2068 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2069 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2070 "cvttps2dq\t{$src, $dst|$dst, $src}",
2072 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2073 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2075 let Predicates = [HasAVX] in {
2076 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2077 (VCVTDQ2PSrr VR128:$src)>;
2078 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2079 (VCVTDQ2PSrm addr:$src)>;
2082 let Predicates = [HasAVX, NoVLX] in {
2083 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2084 (VCVTDQ2PSrr VR128:$src)>;
2085 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2086 (VCVTDQ2PSrm addr:$src)>;
2088 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2089 (VCVTTPS2DQrr VR128:$src)>;
2090 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2091 (VCVTTPS2DQrm addr:$src)>;
2093 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2094 (VCVTDQ2PSYrr VR256:$src)>;
2095 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2096 (VCVTDQ2PSYrm addr:$src)>;
2098 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2099 (VCVTTPS2DQYrr VR256:$src)>;
2100 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2101 (VCVTTPS2DQYrm addr:$src)>;
2104 let Predicates = [UseSSE2] in {
2105 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2106 (CVTDQ2PSrr VR128:$src)>;
2107 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2108 (CVTDQ2PSrm addr:$src)>;
2110 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2111 (CVTDQ2PSrr VR128:$src)>;
2112 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2113 (CVTDQ2PSrm addr:$src)>;
2115 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2116 (CVTTPS2DQrr VR128:$src)>;
2117 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2118 (CVTTPS2DQrm addr:$src)>;
2121 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2122 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2124 (int_x86_sse2_cvttpd2dq VR128:$src))],
2125 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2127 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2128 // register, but the same isn't true when using memory operands instead.
2129 // Provide other assembly rr and rm forms to address this explicitly.
2132 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2133 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2134 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2135 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2136 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2137 (loadv2f64 addr:$src)))],
2138 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2141 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2142 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2144 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2145 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2146 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2147 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2149 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2150 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2151 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2152 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2154 let Predicates = [HasAVX, NoVLX] in {
2155 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2156 (VCVTTPD2DQYrr VR256:$src)>;
2157 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2158 (VCVTTPD2DQYrm addr:$src)>;
2159 } // Predicates = [HasAVX]
2161 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2162 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2163 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2164 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2165 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2166 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2167 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2168 (memopv2f64 addr:$src)))],
2170 Sched<[WriteCvtF2ILd]>;
2172 // Convert packed single to packed double
2173 let Predicates = [HasAVX] in {
2174 // SSE2 instructions without OpSize prefix
2175 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2176 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2177 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2178 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2179 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2180 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2181 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2182 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2183 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2184 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2186 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2187 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2188 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2189 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2191 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2192 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2195 let Predicates = [UseSSE2] in {
2196 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2197 "cvtps2pd\t{$src, $dst|$dst, $src}",
2198 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2199 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2200 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2201 "cvtps2pd\t{$src, $dst|$dst, $src}",
2202 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2203 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2206 // Convert Packed DW Integers to Packed Double FP
2207 let Predicates = [HasAVX] in {
2208 let hasSideEffects = 0, mayLoad = 1 in
2209 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2210 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2211 []>, VEX, Sched<[WriteCvtI2FLd]>;
2212 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2213 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2215 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2216 Sched<[WriteCvtI2F]>;
2217 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2218 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2220 (int_x86_avx_cvtdq2_pd_256
2221 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2222 Sched<[WriteCvtI2FLd]>;
2223 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2224 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2226 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2227 Sched<[WriteCvtI2F]>;
2230 let hasSideEffects = 0, mayLoad = 1 in
2231 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2232 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2233 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2234 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2235 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2236 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2237 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2239 // AVX register conversion intrinsics
2240 let Predicates = [HasAVX] in {
2241 def : Pat<(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))),
2242 (VCVTDQ2PDrr VR128:$src)>;
2243 def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))),
2244 (VCVTDQ2PDrm addr:$src)>;
2246 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2247 (VCVTDQ2PDYrr VR128:$src)>;
2248 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2249 (VCVTDQ2PDYrm addr:$src)>;
2250 } // Predicates = [HasAVX]
2252 // SSE2 register conversion intrinsics
2253 let Predicates = [HasSSE2] in {
2254 def : Pat<(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))),
2255 (CVTDQ2PDrr VR128:$src)>;
2256 def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))),
2257 (CVTDQ2PDrm addr:$src)>;
2258 } // Predicates = [HasSSE2]
2260 // Convert packed double to packed single
2261 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2262 // register, but the same isn't true when using memory operands instead.
2263 // Provide other assembly rr and rm forms to address this explicitly.
2264 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2265 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2266 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2267 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2270 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2271 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2272 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2273 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2275 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2276 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2279 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2280 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2282 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2283 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2284 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2285 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2287 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2288 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2289 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2290 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2292 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2293 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2294 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2295 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2296 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2297 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2299 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2300 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2303 // AVX 256-bit register conversion intrinsics
2304 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2305 // whenever possible to avoid declaring two versions of each one.
2306 let Predicates = [HasAVX] in {
2307 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2308 (VCVTDQ2PSYrr VR256:$src)>;
2309 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2310 (VCVTDQ2PSYrm addr:$src)>;
2313 let Predicates = [HasAVX, NoVLX] in {
2314 // Match fround and fextend for 128/256-bit conversions
2315 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2316 (VCVTPD2PSrr VR128:$src)>;
2317 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2318 (VCVTPD2PSXrm addr:$src)>;
2319 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2320 (VCVTPD2PSYrr VR256:$src)>;
2321 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2322 (VCVTPD2PSYrm addr:$src)>;
2324 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2325 (VCVTPS2PDrr VR128:$src)>;
2326 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2327 (VCVTPS2PDYrr VR128:$src)>;
2328 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2329 (VCVTPS2PDYrm addr:$src)>;
2332 let Predicates = [UseSSE2] in {
2333 // Match fround and fextend for 128 conversions
2334 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2335 (CVTPD2PSrr VR128:$src)>;
2336 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2337 (CVTPD2PSrm addr:$src)>;
2339 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2340 (CVTPS2PDrr VR128:$src)>;
2343 //===----------------------------------------------------------------------===//
2344 // SSE 1 & 2 - Compare Instructions
2345 //===----------------------------------------------------------------------===//
2347 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2348 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2349 Operand CC, SDNode OpNode, ValueType VT,
2350 PatFrag ld_frag, string asm, string asm_alt,
2351 OpndItins itins, ImmLeaf immLeaf> {
2352 def rr : SIi8<0xC2, MRMSrcReg,
2353 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2354 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))],
2355 itins.rr>, Sched<[itins.Sched]>;
2356 def rm : SIi8<0xC2, MRMSrcMem,
2357 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2358 [(set RC:$dst, (OpNode (VT RC:$src1),
2359 (ld_frag addr:$src2), immLeaf:$cc))],
2361 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2363 // Accept explicit immediate argument form instead of comparison code.
2364 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2365 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2366 (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, [],
2367 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2369 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2370 (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, [],
2371 IIC_SSE_ALU_F32S_RM>,
2372 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2376 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2377 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2378 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2379 SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG;
2380 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2381 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2382 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2383 SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare
2384 XD, VEX_4V, VEX_LIG;
2386 let Constraints = "$src1 = $dst" in {
2387 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2388 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2389 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S,
2391 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2392 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2393 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2394 SSE_ALU_F64S, i8immZExt3>, XD;
2397 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2398 Intrinsic Int, string asm, OpndItins itins,
2400 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2401 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2402 [(set VR128:$dst, (Int VR128:$src1,
2403 VR128:$src, immLeaf:$cc))],
2405 Sched<[itins.Sched]>;
2406 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2407 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2408 [(set VR128:$dst, (Int VR128:$src1,
2409 (load addr:$src), immLeaf:$cc))],
2411 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2414 let isCodeGenOnly = 1 in {
2415 // Aliases to match intrinsics which expect XMM operand(s).
2416 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2417 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2418 SSE_ALU_F32S, i8immZExt5>,
2420 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2421 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2422 SSE_ALU_F32S, i8immZExt5>, // same latency as f32
2424 let Constraints = "$src1 = $dst" in {
2425 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2426 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2427 SSE_ALU_F32S, i8immZExt3>, XS;
2428 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2429 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2430 SSE_ALU_F64S, i8immZExt3>,
2436 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2437 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2438 ValueType vt, X86MemOperand x86memop,
2439 PatFrag ld_frag, string OpcodeStr> {
2440 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2441 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2442 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2445 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2446 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2447 [(set EFLAGS, (OpNode (vt RC:$src1),
2448 (ld_frag addr:$src2)))],
2450 Sched<[WriteFAddLd, ReadAfterLd]>;
2453 let Defs = [EFLAGS] in {
2454 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2455 "ucomiss">, PS, VEX, VEX_LIG;
2456 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2457 "ucomisd">, PD, VEX, VEX_LIG;
2458 let Pattern = []<dag> in {
2459 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2460 "comiss">, PS, VEX, VEX_LIG;
2461 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2462 "comisd">, PD, VEX, VEX_LIG;
2465 let isCodeGenOnly = 1 in {
2466 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2467 load, "ucomiss">, PS, VEX;
2468 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2469 load, "ucomisd">, PD, VEX;
2471 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2472 load, "comiss">, PS, VEX;
2473 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2474 load, "comisd">, PD, VEX;
2476 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2478 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2481 let Pattern = []<dag> in {
2482 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2484 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2488 let isCodeGenOnly = 1 in {
2489 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2490 load, "ucomiss">, PS;
2491 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2492 load, "ucomisd">, PD;
2494 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2496 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2499 } // Defs = [EFLAGS]
2501 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2502 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2503 Operand CC, Intrinsic Int, string asm,
2504 string asm_alt, Domain d, ImmLeaf immLeaf,
2505 PatFrag ld_frag, OpndItins itins = SSE_ALU_F32P> {
2506 let isCommutable = 1 in
2507 def rri : PIi8<0xC2, MRMSrcReg,
2508 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2509 [(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
2512 def rmi : PIi8<0xC2, MRMSrcMem,
2513 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2514 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2), immLeaf:$cc))],
2516 Sched<[WriteFAddLd, ReadAfterLd]>;
2518 // Accept explicit immediate argument form instead of comparison code.
2519 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2520 def rri_alt : PIi8<0xC2, MRMSrcReg,
2521 (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
2522 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2524 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2525 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
2526 asm_alt, [], itins.rm, d>,
2527 Sched<[WriteFAddLd, ReadAfterLd]>;
2531 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2532 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2533 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2534 SSEPackedSingle, i8immZExt5, loadv4f32>, PS, VEX_4V;
2535 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2536 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2537 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2538 SSEPackedDouble, i8immZExt5, loadv2f64>, PD, VEX_4V;
2539 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2540 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2541 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2542 SSEPackedSingle, i8immZExt5, loadv8f32>, PS, VEX_4V, VEX_L;
2543 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2544 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2545 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2546 SSEPackedDouble, i8immZExt5, loadv4f64>, PD, VEX_4V, VEX_L;
2547 let Constraints = "$src1 = $dst" in {
2548 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2549 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2550 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2551 SSEPackedSingle, i8immZExt5, memopv4f32, SSE_ALU_F32P>, PS;
2552 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2553 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2554 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2555 SSEPackedDouble, i8immZExt5, memopv2f64, SSE_ALU_F64P>, PD;
2558 let Predicates = [HasAVX] in {
2559 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2560 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2561 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (loadv4f32 addr:$src2), imm:$cc)),
2562 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2563 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2564 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2565 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (loadv2f64 addr:$src2), imm:$cc)),
2566 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2568 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2569 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2570 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (loadv8f32 addr:$src2), imm:$cc)),
2571 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2572 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2573 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2574 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (loadv4f64 addr:$src2), imm:$cc)),
2575 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2578 let Predicates = [UseSSE1] in {
2579 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2580 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2581 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memopv4f32 addr:$src2), imm:$cc)),
2582 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2585 let Predicates = [UseSSE2] in {
2586 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2587 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2588 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memopv2f64 addr:$src2), imm:$cc)),
2589 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2592 //===----------------------------------------------------------------------===//
2593 // SSE 1 & 2 - Shuffle Instructions
2594 //===----------------------------------------------------------------------===//
2596 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2597 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2598 ValueType vt, string asm, PatFrag mem_frag,
2600 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2601 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2602 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2603 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2604 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2605 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2606 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2607 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2608 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2609 Sched<[WriteFShuffle]>;
2612 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2613 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2614 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2615 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2616 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2617 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2618 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2619 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2620 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2621 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2622 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2623 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2625 let Constraints = "$src1 = $dst" in {
2626 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2627 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2628 memopv4f32, SSEPackedSingle>, PS;
2629 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2630 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2631 memopv2f64, SSEPackedDouble>, PD;
2634 let Predicates = [HasAVX] in {
2635 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2636 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2637 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2638 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2639 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2641 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2642 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2643 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2644 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2645 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2648 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2649 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2650 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2651 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2652 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2654 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2655 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2656 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2657 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2658 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2661 let Predicates = [UseSSE1] in {
2662 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2663 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2664 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2665 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2666 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2669 let Predicates = [UseSSE2] in {
2670 // Generic SHUFPD patterns
2671 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2672 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2673 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2674 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2675 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2678 //===----------------------------------------------------------------------===//
2679 // SSE 1 & 2 - Unpack FP Instructions
2680 //===----------------------------------------------------------------------===//
2682 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2683 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2684 PatFrag mem_frag, RegisterClass RC,
2685 X86MemOperand x86memop, string asm,
2687 def rr : PI<opc, MRMSrcReg,
2688 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2690 (vt (OpNode RC:$src1, RC:$src2)))],
2691 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2692 def rm : PI<opc, MRMSrcMem,
2693 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2695 (vt (OpNode RC:$src1,
2696 (mem_frag addr:$src2))))],
2698 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2701 let Predicates = [HasAVX, NoVLX] in {
2702 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2703 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2704 SSEPackedSingle>, PS, VEX_4V;
2705 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2706 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2707 SSEPackedDouble>, PD, VEX_4V;
2708 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2709 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2710 SSEPackedSingle>, PS, VEX_4V;
2711 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2712 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2713 SSEPackedDouble>, PD, VEX_4V;
2715 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2716 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2717 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2718 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2719 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2720 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2721 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2722 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2723 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2724 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2725 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2726 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2727 }// Predicates = [HasAVX, NoVLX]
2728 let Constraints = "$src1 = $dst" in {
2729 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2730 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2731 SSEPackedSingle>, PS;
2732 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2733 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2734 SSEPackedDouble>, PD;
2735 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2736 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2737 SSEPackedSingle>, PS;
2738 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2739 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2740 SSEPackedDouble>, PD;
2741 } // Constraints = "$src1 = $dst"
2743 let Predicates = [HasAVX1Only] in {
2744 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2745 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2746 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2747 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2748 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2749 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2750 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2751 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2753 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2754 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2755 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2756 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2757 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2758 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2759 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2760 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2763 //===----------------------------------------------------------------------===//
2764 // SSE 1 & 2 - Extract Floating-Point Sign mask
2765 //===----------------------------------------------------------------------===//
2767 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2768 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2770 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2771 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2772 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2773 Sched<[WriteVecLogic]>;
2776 let Predicates = [HasAVX] in {
2777 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2778 "movmskps", SSEPackedSingle>, PS, VEX;
2779 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2780 "movmskpd", SSEPackedDouble>, PD, VEX;
2781 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2782 "movmskps", SSEPackedSingle>, PS,
2784 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2785 "movmskpd", SSEPackedDouble>, PD,
2788 def : Pat<(i32 (X86fgetsign FR32:$src)),
2789 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2790 def : Pat<(i64 (X86fgetsign FR32:$src)),
2791 (SUBREG_TO_REG (i64 0),
2792 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2793 def : Pat<(i32 (X86fgetsign FR64:$src)),
2794 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2795 def : Pat<(i64 (X86fgetsign FR64:$src)),
2796 (SUBREG_TO_REG (i64 0),
2797 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2800 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2801 SSEPackedSingle>, PS;
2802 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2803 SSEPackedDouble>, PD;
2805 def : Pat<(i32 (X86fgetsign FR32:$src)),
2806 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2807 Requires<[UseSSE1]>;
2808 def : Pat<(i64 (X86fgetsign FR32:$src)),
2809 (SUBREG_TO_REG (i64 0),
2810 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2811 Requires<[UseSSE1]>;
2812 def : Pat<(i32 (X86fgetsign FR64:$src)),
2813 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2814 Requires<[UseSSE2]>;
2815 def : Pat<(i64 (X86fgetsign FR64:$src)),
2816 (SUBREG_TO_REG (i64 0),
2817 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2818 Requires<[UseSSE2]>;
2820 //===---------------------------------------------------------------------===//
2821 // SSE2 - Packed Integer Logical Instructions
2822 //===---------------------------------------------------------------------===//
2824 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2826 /// PDI_binop_rm - Simple SSE2 binary operator.
2827 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2828 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2829 X86MemOperand x86memop, OpndItins itins,
2830 bit IsCommutable, bit Is2Addr> {
2831 let isCommutable = IsCommutable in
2832 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2833 (ins RC:$src1, RC:$src2),
2835 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2836 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2837 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2838 Sched<[itins.Sched]>;
2839 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2840 (ins RC:$src1, x86memop:$src2),
2842 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2843 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2844 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2845 (bitconvert (memop_frag addr:$src2)))))],
2847 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2849 } // ExeDomain = SSEPackedInt
2851 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2852 ValueType OpVT128, ValueType OpVT256,
2853 OpndItins itins, bit IsCommutable = 0, Predicate prd> {
2854 let Predicates = [HasAVX, prd] in
2855 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2856 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2858 let Constraints = "$src1 = $dst" in
2859 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2860 memopv2i64, i128mem, itins, IsCommutable, 1>;
2862 let Predicates = [HasAVX2, prd] in
2863 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2864 OpVT256, VR256, loadv4i64, i256mem, itins,
2865 IsCommutable, 0>, VEX_4V, VEX_L;
2868 // These are ordered here for pattern ordering requirements with the fp versions
2870 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2871 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2872 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2873 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2874 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2875 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2876 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2877 SSE_VEC_BIT_ITINS_P, 0, NoVLX>;
2879 //===----------------------------------------------------------------------===//
2880 // SSE 1 & 2 - Logical Instructions
2881 //===----------------------------------------------------------------------===//
2883 // Multiclass for scalars using the X86 logical operation aliases for FP.
2884 multiclass sse12_fp_packed_scalar_logical_alias<
2885 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2886 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2887 FR32, f32, f128mem, loadf32_128, SSEPackedSingle, itins, 0>,
2890 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2891 FR64, f64, f128mem, loadf64_128, SSEPackedDouble, itins, 0>,
2894 let Constraints = "$src1 = $dst" in {
2895 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2896 f32, f128mem, memopfsf32_128, SSEPackedSingle, itins>, PS;
2898 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2899 f64, f128mem, memopfsf64_128, SSEPackedDouble, itins>, PD;
2903 let isCodeGenOnly = 1 in {
2904 defm FsAND : sse12_fp_packed_scalar_logical_alias<0x54, "and", X86fand,
2906 defm FsOR : sse12_fp_packed_scalar_logical_alias<0x56, "or", X86for,
2908 defm FsXOR : sse12_fp_packed_scalar_logical_alias<0x57, "xor", X86fxor,
2911 let isCommutable = 0 in
2912 defm FsANDN : sse12_fp_packed_scalar_logical_alias<0x55, "andn", X86fandn,
2916 // Multiclass for vectors using the X86 logical operation aliases for FP.
2917 multiclass sse12_fp_packed_vector_logical_alias<
2918 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2919 let Predicates = [HasAVX, NoVLX] in {
2920 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2921 VR128, v4f32, f128mem, loadv4f32, SSEPackedSingle, itins, 0>,
2924 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2925 VR128, v2f64, f128mem, loadv2f64, SSEPackedDouble, itins, 0>,
2929 let Constraints = "$src1 = $dst" in {
2930 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2931 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins>,
2934 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2935 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins>,
2940 let isCodeGenOnly = 1 in {
2941 defm FvAND : sse12_fp_packed_vector_logical_alias<0x54, "and", X86fand,
2943 defm FvOR : sse12_fp_packed_vector_logical_alias<0x56, "or", X86for,
2945 defm FvXOR : sse12_fp_packed_vector_logical_alias<0x57, "xor", X86fxor,
2948 let isCommutable = 0 in
2949 defm FvANDN : sse12_fp_packed_vector_logical_alias<0x55, "andn", X86fandn,
2953 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2955 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2957 let Predicates = [HasAVX, NoVLX] in {
2958 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2959 !strconcat(OpcodeStr, "ps"), f256mem,
2960 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2961 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2962 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2964 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2965 !strconcat(OpcodeStr, "pd"), f256mem,
2966 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2967 (bc_v4i64 (v4f64 VR256:$src2))))],
2968 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2969 (loadv4i64 addr:$src2)))], 0>,
2972 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2973 // are all promoted to v2i64, and the patterns are covered by the int
2974 // version. This is needed in SSE only, because v2i64 isn't supported on
2975 // SSE1, but only on SSE2.
2976 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2977 !strconcat(OpcodeStr, "ps"), f128mem, [],
2978 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2979 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2981 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2982 !strconcat(OpcodeStr, "pd"), f128mem,
2983 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2984 (bc_v2i64 (v2f64 VR128:$src2))))],
2985 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2986 (loadv2i64 addr:$src2)))], 0>,
2990 let Constraints = "$src1 = $dst" in {
2991 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2992 !strconcat(OpcodeStr, "ps"), f128mem,
2993 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2994 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2995 (memopv2i64 addr:$src2)))]>, PS;
2997 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2998 !strconcat(OpcodeStr, "pd"), f128mem,
2999 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
3000 (bc_v2i64 (v2f64 VR128:$src2))))],
3001 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
3002 (memopv2i64 addr:$src2)))]>, PD;
3006 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
3007 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
3008 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
3009 let isCommutable = 0 in
3010 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
3012 // AVX1 requires type coercions in order to fold loads directly into logical
3014 let Predicates = [HasAVX1Only] in {
3015 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
3016 (VANDPSYrm VR256:$src1, addr:$src2)>;
3017 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3018 (VORPSYrm VR256:$src1, addr:$src2)>;
3019 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3020 (VXORPSYrm VR256:$src1, addr:$src2)>;
3021 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3022 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3025 //===----------------------------------------------------------------------===//
3026 // SSE 1 & 2 - Arithmetic Instructions
3027 //===----------------------------------------------------------------------===//
3029 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3032 /// In addition, we also have a special variant of the scalar form here to
3033 /// represent the associated intrinsic operation. This form is unlike the
3034 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3035 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3037 /// These three forms can each be reg+reg or reg+mem.
3040 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3042 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3043 SDNode OpNode, SizeItins itins> {
3044 let Predicates = [HasAVX, NoVLX] in {
3045 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3046 VR128, v4f32, f128mem, loadv4f32,
3047 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3048 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3049 VR128, v2f64, f128mem, loadv2f64,
3050 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3052 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3053 OpNode, VR256, v8f32, f256mem, loadv8f32,
3054 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3055 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3056 OpNode, VR256, v4f64, f256mem, loadv4f64,
3057 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3060 let Constraints = "$src1 = $dst" in {
3061 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3062 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3064 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3065 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3070 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3072 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3073 OpNode, FR32, f32mem, SSEPackedSingle, itins.s, 0>,
3074 XS, VEX_4V, VEX_LIG;
3075 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3076 OpNode, FR64, f64mem, SSEPackedDouble, itins.d, 0>,
3077 XD, VEX_4V, VEX_LIG;
3079 let Constraints = "$src1 = $dst" in {
3080 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3081 OpNode, FR32, f32mem, SSEPackedSingle,
3083 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3084 OpNode, FR64, f64mem, SSEPackedDouble,
3089 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3091 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3092 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3093 SSEPackedSingle, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3094 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3095 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3096 SSEPackedDouble, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3098 let Constraints = "$src1 = $dst" in {
3099 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3100 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3101 SSEPackedSingle, itins.s>, XS;
3102 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3103 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3104 SSEPackedDouble, itins.d>, XD;
3108 // Binary Arithmetic instructions
3109 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3110 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3111 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3112 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3113 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3114 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3115 let isCommutable = 0 in {
3116 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3117 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3118 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3119 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3120 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3121 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3122 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3123 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3124 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3125 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3126 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3127 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3130 let isCodeGenOnly = 1 in {
3131 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3132 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3133 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3134 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3137 // Patterns used to select SSE scalar fp arithmetic instructions from
3140 // (1) a scalar fp operation followed by a blend
3142 // The effect is that the backend no longer emits unnecessary vector
3143 // insert instructions immediately after SSE scalar fp instructions
3144 // like addss or mulss.
3146 // For example, given the following code:
3147 // __m128 foo(__m128 A, __m128 B) {
3152 // Previously we generated:
3153 // addss %xmm0, %xmm1
3154 // movss %xmm1, %xmm0
3157 // addss %xmm1, %xmm0
3159 // (2) a vector packed single/double fp operation followed by a vector insert
3161 // The effect is that the backend converts the packed fp instruction
3162 // followed by a vector insert into a single SSE scalar fp instruction.
3164 // For example, given the following code:
3165 // __m128 foo(__m128 A, __m128 B) {
3166 // __m128 C = A + B;
3167 // return (__m128) {c[0], a[1], a[2], a[3]};
3170 // Previously we generated:
3171 // addps %xmm0, %xmm1
3172 // movss %xmm1, %xmm0
3175 // addss %xmm1, %xmm0
3177 // TODO: Some canonicalization in lowering would simplify the number of
3178 // patterns we have to try to match.
3179 multiclass scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {
3180 let Predicates = [UseSSE1] in {
3181 // extracted scalar math op with insert via movss
3182 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3183 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3185 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3186 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3188 // vector math op with insert via movss
3189 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3190 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3191 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3194 // With SSE 4.1, blendi is preferred to movsd, so match that too.
3195 let Predicates = [UseSSE41] in {
3196 // extracted scalar math op with insert via blend
3197 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3198 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3199 FR32:$src))), (i8 1))),
3200 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3201 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3203 // vector math op with insert via blend
3204 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3205 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3206 (!cast<I>(OpcPrefix#SSrr_Int)v4f32:$dst, v4f32:$src)>;
3210 // Repeat everything for AVX, except for the movss + scalar combo...
3211 // because that one shouldn't occur with AVX codegen?
3212 let Predicates = [HasAVX] in {
3213 // extracted scalar math op with insert via blend
3214 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3215 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3216 FR32:$src))), (i8 1))),
3217 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst,
3218 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3220 // vector math op with insert via movss
3221 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3222 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3223 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3225 // vector math op with insert via blend
3226 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3227 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3228 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3232 defm : scalar_math_f32_patterns<fadd, "ADD">;
3233 defm : scalar_math_f32_patterns<fsub, "SUB">;
3234 defm : scalar_math_f32_patterns<fmul, "MUL">;
3235 defm : scalar_math_f32_patterns<fdiv, "DIV">;
3237 multiclass scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {
3238 let Predicates = [UseSSE2] in {
3239 // extracted scalar math op with insert via movsd
3240 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3241 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3243 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3244 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3246 // vector math op with insert via movsd
3247 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3248 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3249 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3252 // With SSE 4.1, blendi is preferred to movsd, so match those too.
3253 let Predicates = [UseSSE41] in {
3254 // extracted scalar math op with insert via blend
3255 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3256 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3257 FR64:$src))), (i8 1))),
3258 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3259 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3261 // vector math op with insert via blend
3262 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3263 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3264 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3267 // Repeat everything for AVX.
3268 let Predicates = [HasAVX] in {
3269 // extracted scalar math op with insert via movsd
3270 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3271 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3273 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3274 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3276 // extracted scalar math op with insert via blend
3277 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3278 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3279 FR64:$src))), (i8 1))),
3280 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3281 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3283 // vector math op with insert via movsd
3284 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3285 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3286 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3288 // vector math op with insert via blend
3289 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3290 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3291 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3295 defm : scalar_math_f64_patterns<fadd, "ADD">;
3296 defm : scalar_math_f64_patterns<fsub, "SUB">;
3297 defm : scalar_math_f64_patterns<fmul, "MUL">;
3298 defm : scalar_math_f64_patterns<fdiv, "DIV">;
3302 /// In addition, we also have a special variant of the scalar form here to
3303 /// represent the associated intrinsic operation. This form is unlike the
3304 /// plain scalar form, in that it takes an entire vector (instead of a
3305 /// scalar) and leaves the top elements undefined.
3307 /// And, we have a special variant form for a full-vector intrinsic form.
3309 let Sched = WriteFSqrt in {
3310 def SSE_SQRTPS : OpndItins<
3311 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3314 def SSE_SQRTSS : OpndItins<
3315 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3318 def SSE_SQRTPD : OpndItins<
3319 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3322 def SSE_SQRTSD : OpndItins<
3323 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3327 let Sched = WriteFRsqrt in {
3328 def SSE_RSQRTPS : OpndItins<
3329 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3332 def SSE_RSQRTSS : OpndItins<
3333 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3337 let Sched = WriteFRcp in {
3338 def SSE_RCPP : OpndItins<
3339 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3342 def SSE_RCPS : OpndItins<
3343 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3347 /// sse_fp_unop_s - SSE1 unops in scalar form
3348 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3349 /// the HW instructions are 2 operand / destructive.
3350 multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3351 ValueType vt, ValueType ScalarVT,
3352 X86MemOperand x86memop, Operand vec_memop,
3353 ComplexPattern mem_cpat, Intrinsic Intr,
3354 SDNode OpNode, Domain d, OpndItins itins,
3355 Predicate target, string Suffix> {
3356 let hasSideEffects = 0 in {
3357 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
3358 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3359 [(set RC:$dst, (OpNode RC:$src1))], itins.rr, d>, Sched<[itins.Sched]>,
3362 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1),
3363 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3364 [(set RC:$dst, (OpNode (load addr:$src1)))], itins.rm, d>,
3365 Sched<[itins.Sched.Folded, ReadAfterLd]>,
3366 Requires<[target, OptForSize]>;
3368 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3369 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3370 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3371 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3373 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, vec_memop:$src2),
3374 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3375 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3379 let Predicates = [target] in {
3380 def : Pat<(vt (OpNode mem_cpat:$src)),
3381 (vt (COPY_TO_REGCLASS (vt (!cast<Instruction>(NAME#Suffix##m_Int)
3382 (vt (IMPLICIT_DEF)), mem_cpat:$src)), RC))>;
3383 // These are unary operations, but they are modeled as having 2 source operands
3384 // because the high elements of the destination are unchanged in SSE.
3385 def : Pat<(Intr VR128:$src),
3386 (!cast<Instruction>(NAME#Suffix##r_Int) VR128:$src, VR128:$src)>;
3387 def : Pat<(Intr (load addr:$src)),
3388 (vt (COPY_TO_REGCLASS(!cast<Instruction>(NAME#Suffix##m)
3389 addr:$src), VR128))>;
3390 def : Pat<(Intr mem_cpat:$src),
3391 (!cast<Instruction>(NAME#Suffix##m_Int)
3392 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3396 multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3397 ValueType vt, ValueType ScalarVT,
3398 X86MemOperand x86memop, Operand vec_memop,
3399 ComplexPattern mem_cpat,
3400 Intrinsic Intr, SDNode OpNode, Domain d,
3401 OpndItins itins, string Suffix> {
3402 let hasSideEffects = 0 in {
3403 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3404 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3405 [], itins.rr, d>, Sched<[itins.Sched]>;
3407 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3408 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3409 [], itins.rm, d>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3410 let isCodeGenOnly = 1 in {
3411 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
3412 (ins VR128:$src1, VR128:$src2),
3413 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3414 []>, Sched<[itins.Sched.Folded]>;
3416 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst),
3417 (ins VR128:$src1, vec_memop:$src2),
3418 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3419 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3423 let Predicates = [UseAVX] in {
3424 def : Pat<(OpNode RC:$src), (!cast<Instruction>("V"#NAME#Suffix##r)
3425 (ScalarVT (IMPLICIT_DEF)), RC:$src)>;
3427 def : Pat<(vt (OpNode mem_cpat:$src)),
3428 (!cast<Instruction>("V"#NAME#Suffix##m_Int) (vt (IMPLICIT_DEF)),
3432 let Predicates = [HasAVX] in {
3433 def : Pat<(Intr VR128:$src),
3434 (!cast<Instruction>("V"#NAME#Suffix##r_Int) (vt (IMPLICIT_DEF)),
3437 def : Pat<(Intr mem_cpat:$src),
3438 (!cast<Instruction>("V"#NAME#Suffix##m_Int)
3439 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3441 let Predicates = [UseAVX, OptForSize] in
3442 def : Pat<(ScalarVT (OpNode (load addr:$src))),
3443 (!cast<Instruction>("V"#NAME#Suffix##m) (ScalarVT (IMPLICIT_DEF)),
3447 /// sse1_fp_unop_p - SSE1 unops in packed form.
3448 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3450 let Predicates = [HasAVX] in {
3451 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3452 !strconcat("v", OpcodeStr,
3453 "ps\t{$src, $dst|$dst, $src}"),
3454 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3455 itins.rr>, VEX, Sched<[itins.Sched]>;
3456 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3457 !strconcat("v", OpcodeStr,
3458 "ps\t{$src, $dst|$dst, $src}"),
3459 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3460 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3461 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3462 !strconcat("v", OpcodeStr,
3463 "ps\t{$src, $dst|$dst, $src}"),
3464 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3465 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3466 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3467 !strconcat("v", OpcodeStr,
3468 "ps\t{$src, $dst|$dst, $src}"),
3469 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3470 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3473 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3474 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3475 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3476 Sched<[itins.Sched]>;
3477 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3478 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3479 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3480 Sched<[itins.Sched.Folded]>;
3483 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3484 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3485 SDNode OpNode, OpndItins itins> {
3486 let Predicates = [HasAVX] in {
3487 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3488 !strconcat("v", OpcodeStr,
3489 "pd\t{$src, $dst|$dst, $src}"),
3490 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3491 itins.rr>, VEX, Sched<[itins.Sched]>;
3492 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3493 !strconcat("v", OpcodeStr,
3494 "pd\t{$src, $dst|$dst, $src}"),
3495 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3496 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3497 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3498 !strconcat("v", OpcodeStr,
3499 "pd\t{$src, $dst|$dst, $src}"),
3500 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3501 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3502 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3503 !strconcat("v", OpcodeStr,
3504 "pd\t{$src, $dst|$dst, $src}"),
3505 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3506 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3509 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3510 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3511 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3512 Sched<[itins.Sched]>;
3513 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3514 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3515 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3516 Sched<[itins.Sched.Folded]>;
3519 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3521 defm SS : sse_fp_unop_s<opc, OpcodeStr##ss, FR32, v4f32, f32, f32mem,
3522 ssmem, sse_load_f32,
3523 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3524 SSEPackedSingle, itins, UseSSE1, "SS">, XS;
3525 defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr##ss, FR32, v4f32, f32,
3526 f32mem, ssmem, sse_load_f32,
3527 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3528 SSEPackedSingle, itins, "SS">, XS, VEX_4V, VEX_LIG;
3531 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3533 defm SD : sse_fp_unop_s<opc, OpcodeStr##sd, FR64, v2f64, f64, f64mem,
3534 sdmem, sse_load_f64,
3535 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3536 OpNode, SSEPackedDouble, itins, UseSSE2, "SD">, XD;
3537 defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr##sd, FR64, v2f64, f64,
3538 f64mem, sdmem, sse_load_f64,
3539 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3540 OpNode, SSEPackedDouble, itins, "SD">,
3541 XD, VEX_4V, VEX_LIG;
3545 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3546 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3547 sse2_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSD>,
3548 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3550 // Reciprocal approximations. Note that these typically require refinement
3551 // in order to obtain suitable precision.
3552 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3553 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>;
3554 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3555 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>;
3557 // There is no f64 version of the reciprocal approximation instructions.
3559 // TODO: We should add *scalar* op patterns for these just like we have for
3560 // the binops above. If the binop and unop patterns could all be unified
3561 // that would be even better.
3563 multiclass scalar_unary_math_patterns<Intrinsic Intr, string OpcPrefix,
3564 SDNode Move, ValueType VT,
3565 Predicate BasePredicate> {
3566 let Predicates = [BasePredicate] in {
3567 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3568 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3571 // With SSE 4.1, blendi is preferred to movs*, so match that too.
3572 let Predicates = [UseSSE41] in {
3573 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3574 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3577 // Repeat for AVX versions of the instructions.
3578 let Predicates = [HasAVX] in {
3579 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3580 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3582 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3583 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3587 defm : scalar_unary_math_patterns<int_x86_sse_rcp_ss, "RCPSS", X86Movss,
3589 defm : scalar_unary_math_patterns<int_x86_sse_rsqrt_ss, "RSQRTSS", X86Movss,
3591 defm : scalar_unary_math_patterns<int_x86_sse_sqrt_ss, "SQRTSS", X86Movss,
3593 defm : scalar_unary_math_patterns<int_x86_sse2_sqrt_sd, "SQRTSD", X86Movsd,
3597 //===----------------------------------------------------------------------===//
3598 // SSE 1 & 2 - Non-temporal stores
3599 //===----------------------------------------------------------------------===//
3601 let AddedComplexity = 400 in { // Prefer non-temporal versions
3602 let SchedRW = [WriteStore] in {
3603 let Predicates = [HasAVX, NoVLX] in {
3604 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3605 (ins f128mem:$dst, VR128:$src),
3606 "movntps\t{$src, $dst|$dst, $src}",
3607 [(alignednontemporalstore (v4f32 VR128:$src),
3609 IIC_SSE_MOVNT>, VEX;
3610 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3611 (ins f128mem:$dst, VR128:$src),
3612 "movntpd\t{$src, $dst|$dst, $src}",
3613 [(alignednontemporalstore (v2f64 VR128:$src),
3615 IIC_SSE_MOVNT>, VEX;
3617 let ExeDomain = SSEPackedInt in
3618 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3619 (ins f128mem:$dst, VR128:$src),
3620 "movntdq\t{$src, $dst|$dst, $src}",
3621 [(alignednontemporalstore (v2i64 VR128:$src),
3623 IIC_SSE_MOVNT>, VEX;
3625 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3626 (ins f256mem:$dst, VR256:$src),
3627 "movntps\t{$src, $dst|$dst, $src}",
3628 [(alignednontemporalstore (v8f32 VR256:$src),
3630 IIC_SSE_MOVNT>, VEX, VEX_L;
3631 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3632 (ins f256mem:$dst, VR256:$src),
3633 "movntpd\t{$src, $dst|$dst, $src}",
3634 [(alignednontemporalstore (v4f64 VR256:$src),
3636 IIC_SSE_MOVNT>, VEX, VEX_L;
3637 let ExeDomain = SSEPackedInt in
3638 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3639 (ins f256mem:$dst, VR256:$src),
3640 "movntdq\t{$src, $dst|$dst, $src}",
3641 [(alignednontemporalstore (v4i64 VR256:$src),
3643 IIC_SSE_MOVNT>, VEX, VEX_L;
3646 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3647 "movntps\t{$src, $dst|$dst, $src}",
3648 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3650 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3651 "movntpd\t{$src, $dst|$dst, $src}",
3652 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3655 let ExeDomain = SSEPackedInt in
3656 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3657 "movntdq\t{$src, $dst|$dst, $src}",
3658 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3661 // There is no AVX form for instructions below this point
3662 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3663 "movnti{l}\t{$src, $dst|$dst, $src}",
3664 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3666 PS, Requires<[HasSSE2]>;
3667 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3668 "movnti{q}\t{$src, $dst|$dst, $src}",
3669 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3671 PS, Requires<[HasSSE2]>;
3672 } // SchedRW = [WriteStore]
3674 let Predicates = [HasAVX2, NoVLX] in {
3675 def : Pat<(alignednontemporalstore (v8i32 VR256:$src), addr:$dst),
3676 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3677 def : Pat<(alignednontemporalstore (v16i16 VR256:$src), addr:$dst),
3678 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3679 def : Pat<(alignednontemporalstore (v32i8 VR256:$src), addr:$dst),
3680 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3683 let Predicates = [HasAVX, NoVLX] in {
3684 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3685 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3686 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3687 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3688 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3689 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3692 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3693 (MOVNTDQmr addr:$dst, VR128:$src)>;
3694 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3695 (MOVNTDQmr addr:$dst, VR128:$src)>;
3696 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3697 (MOVNTDQmr addr:$dst, VR128:$src)>;
3699 } // AddedComplexity
3701 //===----------------------------------------------------------------------===//
3702 // SSE 1 & 2 - Prefetch and memory fence
3703 //===----------------------------------------------------------------------===//
3705 // Prefetch intrinsic.
3706 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3707 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3708 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3709 IIC_SSE_PREFETCH>, TB;
3710 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3711 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3712 IIC_SSE_PREFETCH>, TB;
3713 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3714 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3715 IIC_SSE_PREFETCH>, TB;
3716 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3717 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3718 IIC_SSE_PREFETCH>, TB;
3721 // FIXME: How should flush instruction be modeled?
3722 let SchedRW = [WriteLoad] in {
3724 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3725 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3726 IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
3729 let SchedRW = [WriteNop] in {
3730 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3731 // was introduced with SSE2, it's backward compatible.
3732 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3733 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3734 OBXS, Requires<[HasSSE2]>;
3737 let SchedRW = [WriteFence] in {
3738 // Load, store, and memory fence
3739 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3740 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3741 PS, Requires<[HasSSE1]>;
3742 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3743 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3744 TB, Requires<[HasSSE2]>;
3745 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3746 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3747 TB, Requires<[HasSSE2]>;
3750 def : Pat<(X86SFence), (SFENCE)>;
3751 def : Pat<(X86LFence), (LFENCE)>;
3752 def : Pat<(X86MFence), (MFENCE)>;
3754 //===----------------------------------------------------------------------===//
3755 // SSE 1 & 2 - Load/Store XCSR register
3756 //===----------------------------------------------------------------------===//
3758 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3759 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3760 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3761 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3762 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3763 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3765 let Predicates = [UseSSE1] in {
3766 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
3767 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3768 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
3769 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3770 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3771 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
3774 //===---------------------------------------------------------------------===//
3775 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3776 //===---------------------------------------------------------------------===//
3778 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3780 let hasSideEffects = 0, SchedRW = [WriteMove] in {
3781 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3782 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3784 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3785 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3787 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3788 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3790 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3791 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3796 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3797 SchedRW = [WriteMove] in {
3798 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3799 "movdqa\t{$src, $dst|$dst, $src}", [],
3802 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3803 "movdqa\t{$src, $dst|$dst, $src}", [],
3804 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3805 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3806 "movdqu\t{$src, $dst|$dst, $src}", [],
3809 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3810 "movdqu\t{$src, $dst|$dst, $src}", [],
3811 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3814 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3815 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3816 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3817 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3819 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3820 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3822 let Predicates = [HasAVX] in {
3823 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3824 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3826 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3827 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3832 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3833 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3834 (ins i128mem:$dst, VR128:$src),
3835 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3837 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3838 (ins i256mem:$dst, VR256:$src),
3839 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3841 let Predicates = [HasAVX] in {
3842 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3843 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3845 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3846 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3851 let SchedRW = [WriteMove] in {
3852 let hasSideEffects = 0 in
3853 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3854 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3856 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3857 "movdqu\t{$src, $dst|$dst, $src}",
3858 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3861 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3862 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3863 "movdqa\t{$src, $dst|$dst, $src}", [],
3866 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3867 "movdqu\t{$src, $dst|$dst, $src}",
3868 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3872 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3873 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3874 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3875 "movdqa\t{$src, $dst|$dst, $src}",
3876 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3878 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3879 "movdqu\t{$src, $dst|$dst, $src}",
3880 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3882 XS, Requires<[UseSSE2]>;
3885 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3886 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3887 "movdqa\t{$src, $dst|$dst, $src}",
3888 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3890 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3891 "movdqu\t{$src, $dst|$dst, $src}",
3892 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3894 XS, Requires<[UseSSE2]>;
3897 } // ExeDomain = SSEPackedInt
3899 let Predicates = [HasAVX] in {
3900 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3901 (VMOVDQUmr addr:$dst, VR128:$src)>;
3902 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3903 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3905 let Predicates = [UseSSE2] in
3906 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3907 (MOVDQUmr addr:$dst, VR128:$src)>;
3909 //===---------------------------------------------------------------------===//
3910 // SSE2 - Packed Integer Arithmetic Instructions
3911 //===---------------------------------------------------------------------===//
3913 let Sched = WriteVecIMul in
3914 def SSE_PMADD : OpndItins<
3915 IIC_SSE_PMADD, IIC_SSE_PMADD
3918 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3920 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3921 RegisterClass RC, PatFrag memop_frag,
3922 X86MemOperand x86memop,
3924 bit IsCommutable = 0,
3926 let isCommutable = IsCommutable in
3927 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3928 (ins RC:$src1, RC:$src2),
3930 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3931 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3932 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3933 Sched<[itins.Sched]>;
3934 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3935 (ins RC:$src1, x86memop:$src2),
3937 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3938 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3939 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3940 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3943 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3944 Intrinsic IntId256, OpndItins itins,
3945 bit IsCommutable = 0> {
3946 let Predicates = [HasAVX] in
3947 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3948 VR128, loadv2i64, i128mem, itins,
3949 IsCommutable, 0>, VEX_4V;
3951 let Constraints = "$src1 = $dst" in
3952 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3953 i128mem, itins, IsCommutable, 1>;
3955 let Predicates = [HasAVX2] in
3956 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3957 VR256, loadv4i64, i256mem, itins,
3958 IsCommutable, 0>, VEX_4V, VEX_L;
3961 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3962 string OpcodeStr, SDNode OpNode,
3963 SDNode OpNode2, RegisterClass RC,
3964 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3965 PatFrag ld_frag, ShiftOpndItins itins,
3967 // src2 is always 128-bit
3968 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3969 (ins RC:$src1, VR128:$src2),
3971 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3972 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3973 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3974 itins.rr>, Sched<[WriteVecShift]>;
3975 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3976 (ins RC:$src1, i128mem:$src2),
3978 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3979 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3980 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3981 (bc_frag (ld_frag addr:$src2)))))], itins.rm>,
3982 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3983 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3984 (ins RC:$src1, u8imm:$src2),
3986 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3987 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3988 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3989 Sched<[WriteVecShift]>;
3992 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3993 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3994 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3995 PatFrag memop_frag, X86MemOperand x86memop,
3997 bit IsCommutable = 0, bit Is2Addr = 1> {
3998 let isCommutable = IsCommutable in
3999 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4000 (ins RC:$src1, RC:$src2),
4002 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4003 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4004 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4005 Sched<[itins.Sched]>;
4006 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4007 (ins RC:$src1, x86memop:$src2),
4009 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4010 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4011 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4012 (bitconvert (memop_frag addr:$src2)))))]>,
4013 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4015 } // ExeDomain = SSEPackedInt
4017 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4018 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4019 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4020 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4021 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4022 SSE_INTALU_ITINS_P, 1, NoVLX>;
4023 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4024 SSE_INTALUQ_ITINS_P, 1, NoVLX>;
4025 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4026 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4027 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4028 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4029 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4030 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4031 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4032 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4033 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4034 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4035 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4036 SSE_INTALU_ITINS_P, 0, NoVLX>;
4037 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4038 SSE_INTALUQ_ITINS_P, 0, NoVLX>;
4039 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4040 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4041 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4042 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4043 defm PMINUB : PDI_binop_all<0xDA, "pminub", umin, v16i8, v32i8,
4044 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4045 defm PMINSW : PDI_binop_all<0xEA, "pminsw", smin, v8i16, v16i16,
4046 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4047 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", umax, v16i8, v32i8,
4048 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4049 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", smax, v8i16, v16i16,
4050 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4053 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4054 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4055 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4056 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4057 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4058 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4059 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4060 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4061 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4062 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4063 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4064 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4065 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4066 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4067 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4068 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4069 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4070 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4071 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4072 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4074 let Predicates = [HasAVX2] in
4075 def : Pat<(v32i8 (X86psadbw (v32i8 VR256:$src1),
4076 (v32i8 VR256:$src2))),
4077 (VPSADBWYrr VR256:$src2, VR256:$src1)>;
4079 let Predicates = [HasAVX] in
4080 def : Pat<(v16i8 (X86psadbw (v16i8 VR128:$src1),
4081 (v16i8 VR128:$src2))),
4082 (VPSADBWrr VR128:$src2, VR128:$src1)>;
4084 def : Pat<(v16i8 (X86psadbw (v16i8 VR128:$src1),
4085 (v16i8 VR128:$src2))),
4086 (PSADBWrr VR128:$src2, VR128:$src1)>;
4088 let Predicates = [HasAVX] in
4089 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4090 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4092 let Predicates = [HasAVX2] in
4093 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4094 VR256, loadv4i64, i256mem,
4095 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4096 let Constraints = "$src1 = $dst" in
4097 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4098 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4100 //===---------------------------------------------------------------------===//
4101 // SSE2 - Packed Integer Logical Instructions
4102 //===---------------------------------------------------------------------===//
4104 let Predicates = [HasAVX, NoVLX] in {
4105 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4106 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4107 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4108 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4109 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4110 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4111 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4112 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4113 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4115 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4116 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4117 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4118 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4119 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4120 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4121 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4122 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4123 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4125 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4126 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4127 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4128 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4129 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4130 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4132 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4133 // 128-bit logical shifts.
4134 def VPSLLDQri : PDIi8<0x73, MRM7r,
4135 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4136 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4138 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))]>,
4140 def VPSRLDQri : PDIi8<0x73, MRM3r,
4141 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4142 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4144 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))]>,
4146 // PSRADQri doesn't exist in SSE[1-3].
4148 } // Predicates = [HasAVX]
4150 let Predicates = [HasAVX2, NoVLX] in {
4151 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4152 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4153 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4154 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4155 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4156 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4157 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4158 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4159 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4161 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4162 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4163 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4164 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4165 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4166 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4167 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4168 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4169 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4171 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4172 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4173 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4174 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4175 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4176 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4178 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4179 // 256-bit logical shifts.
4180 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4181 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4182 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4184 (v4i64 (X86vshldq VR256:$src1, (i8 imm:$src2))))]>,
4186 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4187 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4188 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4190 (v4i64 (X86vshrdq VR256:$src1, (i8 imm:$src2))))]>,
4192 // PSRADQYri doesn't exist in SSE[1-3].
4194 } // Predicates = [HasAVX2]
4196 let Constraints = "$src1 = $dst" in {
4197 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4198 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4199 SSE_INTSHIFT_ITINS_P>;
4200 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4201 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4202 SSE_INTSHIFT_ITINS_P>;
4203 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4204 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4205 SSE_INTSHIFT_ITINS_P>;
4207 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4208 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4209 SSE_INTSHIFT_ITINS_P>;
4210 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4211 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4212 SSE_INTSHIFT_ITINS_P>;
4213 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4214 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4215 SSE_INTSHIFT_ITINS_P>;
4217 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4218 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4219 SSE_INTSHIFT_ITINS_P>;
4220 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4221 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4222 SSE_INTSHIFT_ITINS_P>;
4224 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4225 // 128-bit logical shifts.
4226 def PSLLDQri : PDIi8<0x73, MRM7r,
4227 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4228 "pslldq\t{$src2, $dst|$dst, $src2}",
4230 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))],
4231 IIC_SSE_INTSHDQ_P_RI>;
4232 def PSRLDQri : PDIi8<0x73, MRM3r,
4233 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4234 "psrldq\t{$src2, $dst|$dst, $src2}",
4236 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))],
4237 IIC_SSE_INTSHDQ_P_RI>;
4238 // PSRADQri doesn't exist in SSE[1-3].
4240 } // Constraints = "$src1 = $dst"
4242 //===---------------------------------------------------------------------===//
4243 // SSE2 - Packed Integer Comparison Instructions
4244 //===---------------------------------------------------------------------===//
4246 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4247 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4248 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4249 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4250 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4251 SSE_INTALU_ITINS_P, 1, NoVLX>;
4252 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4253 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4254 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4255 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4256 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4257 SSE_INTALU_ITINS_P, 0, NoVLX>;
4259 //===---------------------------------------------------------------------===//
4260 // SSE2 - Packed Integer Shuffle Instructions
4261 //===---------------------------------------------------------------------===//
4263 let ExeDomain = SSEPackedInt in {
4264 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4266 let Predicates = [HasAVX] in {
4267 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4268 (ins VR128:$src1, u8imm:$src2),
4269 !strconcat("v", OpcodeStr,
4270 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4272 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4273 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4274 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4275 (ins i128mem:$src1, u8imm:$src2),
4276 !strconcat("v", OpcodeStr,
4277 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4279 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4280 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4281 Sched<[WriteShuffleLd]>;
4284 let Predicates = [HasAVX2] in {
4285 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4286 (ins VR256:$src1, u8imm:$src2),
4287 !strconcat("v", OpcodeStr,
4288 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4290 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4291 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4292 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4293 (ins i256mem:$src1, u8imm:$src2),
4294 !strconcat("v", OpcodeStr,
4295 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4297 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4298 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4299 Sched<[WriteShuffleLd]>;
4302 let Predicates = [UseSSE2] in {
4303 def ri : Ii8<0x70, MRMSrcReg,
4304 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4305 !strconcat(OpcodeStr,
4306 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4308 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4309 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4310 def mi : Ii8<0x70, MRMSrcMem,
4311 (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2),
4312 !strconcat(OpcodeStr,
4313 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4315 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4316 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4317 Sched<[WriteShuffleLd, ReadAfterLd]>;
4320 } // ExeDomain = SSEPackedInt
4322 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4323 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4324 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4326 let Predicates = [HasAVX] in {
4327 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4328 (VPSHUFDmi addr:$src1, imm:$imm)>;
4329 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4330 (VPSHUFDri VR128:$src1, imm:$imm)>;
4333 let Predicates = [UseSSE2] in {
4334 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4335 (PSHUFDmi addr:$src1, imm:$imm)>;
4336 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4337 (PSHUFDri VR128:$src1, imm:$imm)>;
4340 //===---------------------------------------------------------------------===//
4341 // Packed Integer Pack Instructions (SSE & AVX)
4342 //===---------------------------------------------------------------------===//
4344 let ExeDomain = SSEPackedInt in {
4345 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4346 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4347 PatFrag ld_frag, bit Is2Addr = 1> {
4348 def rr : PDI<opc, MRMSrcReg,
4349 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4351 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4352 !strconcat(OpcodeStr,
4353 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4355 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4356 Sched<[WriteShuffle]>;
4357 def rm : PDI<opc, MRMSrcMem,
4358 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4360 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4361 !strconcat(OpcodeStr,
4362 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4364 (OutVT (OpNode VR128:$src1,
4365 (bc_frag (ld_frag addr:$src2)))))]>,
4366 Sched<[WriteShuffleLd, ReadAfterLd]>;
4369 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4370 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4371 def Yrr : PDI<opc, MRMSrcReg,
4372 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4373 !strconcat(OpcodeStr,
4374 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4376 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4377 Sched<[WriteShuffle]>;
4378 def Yrm : PDI<opc, MRMSrcMem,
4379 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4380 !strconcat(OpcodeStr,
4381 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4383 (OutVT (OpNode VR256:$src1,
4384 (bc_frag (loadv4i64 addr:$src2)))))]>,
4385 Sched<[WriteShuffleLd, ReadAfterLd]>;
4388 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4389 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4390 PatFrag ld_frag, bit Is2Addr = 1> {
4391 def rr : SS48I<opc, MRMSrcReg,
4392 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4394 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4395 !strconcat(OpcodeStr,
4396 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4398 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4399 Sched<[WriteShuffle]>;
4400 def rm : SS48I<opc, MRMSrcMem,
4401 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4403 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4404 !strconcat(OpcodeStr,
4405 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4407 (OutVT (OpNode VR128:$src1,
4408 (bc_frag (ld_frag addr:$src2)))))]>,
4409 Sched<[WriteShuffleLd, ReadAfterLd]>;
4412 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4413 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4414 def Yrr : SS48I<opc, MRMSrcReg,
4415 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4416 !strconcat(OpcodeStr,
4417 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4419 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4420 Sched<[WriteShuffle]>;
4421 def Yrm : SS48I<opc, MRMSrcMem,
4422 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4423 !strconcat(OpcodeStr,
4424 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4426 (OutVT (OpNode VR256:$src1,
4427 (bc_frag (loadv4i64 addr:$src2)))))]>,
4428 Sched<[WriteShuffleLd, ReadAfterLd]>;
4431 let Predicates = [HasAVX] in {
4432 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4433 bc_v8i16, loadv2i64, 0>, VEX_4V;
4434 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4435 bc_v4i32, loadv2i64, 0>, VEX_4V;
4437 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4438 bc_v8i16, loadv2i64, 0>, VEX_4V;
4439 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4440 bc_v4i32, loadv2i64, 0>, VEX_4V;
4443 let Predicates = [HasAVX2] in {
4444 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4445 bc_v16i16>, VEX_4V, VEX_L;
4446 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4447 bc_v8i32>, VEX_4V, VEX_L;
4449 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4450 bc_v16i16>, VEX_4V, VEX_L;
4451 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4452 bc_v8i32>, VEX_4V, VEX_L;
4455 let Constraints = "$src1 = $dst" in {
4456 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4457 bc_v8i16, memopv2i64>;
4458 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4459 bc_v4i32, memopv2i64>;
4461 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4462 bc_v8i16, memopv2i64>;
4464 let Predicates = [HasSSE41] in
4465 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4466 bc_v4i32, memopv2i64>;
4468 } // ExeDomain = SSEPackedInt
4470 //===---------------------------------------------------------------------===//
4471 // SSE2 - Packed Integer Unpack Instructions
4472 //===---------------------------------------------------------------------===//
4474 let ExeDomain = SSEPackedInt in {
4475 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4476 SDNode OpNode, PatFrag bc_frag, PatFrag ld_frag,
4478 def rr : PDI<opc, MRMSrcReg,
4479 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4481 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4482 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4483 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4484 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4485 def rm : PDI<opc, MRMSrcMem,
4486 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4488 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4489 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4490 [(set VR128:$dst, (OpNode VR128:$src1,
4491 (bc_frag (ld_frag addr:$src2))))],
4493 Sched<[WriteShuffleLd, ReadAfterLd]>;
4496 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4497 SDNode OpNode, PatFrag bc_frag> {
4498 def Yrr : PDI<opc, MRMSrcReg,
4499 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4500 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4501 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4502 Sched<[WriteShuffle]>;
4503 def Yrm : PDI<opc, MRMSrcMem,
4504 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4505 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4506 [(set VR256:$dst, (OpNode VR256:$src1,
4507 (bc_frag (loadv4i64 addr:$src2))))]>,
4508 Sched<[WriteShuffleLd, ReadAfterLd]>;
4512 let Predicates = [HasAVX, NoVLX_Or_NoBWI] in {
4513 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4514 bc_v16i8, loadv2i64, 0>, VEX_4V;
4515 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4516 bc_v8i16, loadv2i64, 0>, VEX_4V;
4517 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4518 bc_v16i8, loadv2i64, 0>, VEX_4V;
4519 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4520 bc_v8i16, loadv2i64, 0>, VEX_4V;
4522 let Predicates = [HasAVX, NoVLX] in {
4523 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4524 bc_v4i32, loadv2i64, 0>, VEX_4V;
4525 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4526 bc_v2i64, loadv2i64, 0>, VEX_4V;
4527 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4528 bc_v4i32, loadv2i64, 0>, VEX_4V;
4529 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4530 bc_v2i64, loadv2i64, 0>, VEX_4V;
4533 let Predicates = [HasAVX2, NoVLX_Or_NoBWI] in {
4534 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4535 bc_v32i8>, VEX_4V, VEX_L;
4536 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4537 bc_v16i16>, VEX_4V, VEX_L;
4538 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4539 bc_v32i8>, VEX_4V, VEX_L;
4540 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4541 bc_v16i16>, VEX_4V, VEX_L;
4543 let Predicates = [HasAVX2, NoVLX] in {
4544 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4545 bc_v8i32>, VEX_4V, VEX_L;
4546 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4547 bc_v4i64>, VEX_4V, VEX_L;
4548 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4549 bc_v8i32>, VEX_4V, VEX_L;
4550 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4551 bc_v4i64>, VEX_4V, VEX_L;
4554 let Constraints = "$src1 = $dst" in {
4555 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4556 bc_v16i8, memopv2i64>;
4557 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4558 bc_v8i16, memopv2i64>;
4559 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4560 bc_v4i32, memopv2i64>;
4561 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4562 bc_v2i64, memopv2i64>;
4564 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4565 bc_v16i8, memopv2i64>;
4566 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4567 bc_v8i16, memopv2i64>;
4568 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4569 bc_v4i32, memopv2i64>;
4570 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4571 bc_v2i64, memopv2i64>;
4573 } // ExeDomain = SSEPackedInt
4575 //===---------------------------------------------------------------------===//
4576 // SSE2 - Packed Integer Extract and Insert
4577 //===---------------------------------------------------------------------===//
4579 let ExeDomain = SSEPackedInt in {
4580 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4581 def rri : Ii8<0xC4, MRMSrcReg,
4582 (outs VR128:$dst), (ins VR128:$src1,
4583 GR32orGR64:$src2, u8imm:$src3),
4585 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4586 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4588 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4589 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4590 def rmi : Ii8<0xC4, MRMSrcMem,
4591 (outs VR128:$dst), (ins VR128:$src1,
4592 i16mem:$src2, u8imm:$src3),
4594 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4595 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4597 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4598 imm:$src3))], IIC_SSE_PINSRW>,
4599 Sched<[WriteShuffleLd, ReadAfterLd]>;
4603 let Predicates = [HasAVX] in
4604 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4605 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4606 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4607 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4608 imm:$src2))]>, PD, VEX,
4609 Sched<[WriteShuffle]>;
4610 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4611 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4612 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4613 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4614 imm:$src2))], IIC_SSE_PEXTRW>,
4615 Sched<[WriteShuffleLd, ReadAfterLd]>;
4618 let Predicates = [HasAVX] in
4619 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4621 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4622 defm PINSRW : sse2_pinsrw, PD;
4624 } // ExeDomain = SSEPackedInt
4626 //===---------------------------------------------------------------------===//
4627 // SSE2 - Packed Mask Creation
4628 //===---------------------------------------------------------------------===//
4630 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4632 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4634 "pmovmskb\t{$src, $dst|$dst, $src}",
4635 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4636 IIC_SSE_MOVMSK>, VEX;
4638 let Predicates = [HasAVX2] in {
4639 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4641 "pmovmskb\t{$src, $dst|$dst, $src}",
4642 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4646 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4647 "pmovmskb\t{$src, $dst|$dst, $src}",
4648 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4651 } // ExeDomain = SSEPackedInt
4653 //===---------------------------------------------------------------------===//
4654 // SSE2 - Conditional Store
4655 //===---------------------------------------------------------------------===//
4657 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4659 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4660 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4661 (ins VR128:$src, VR128:$mask),
4662 "maskmovdqu\t{$mask, $src|$src, $mask}",
4663 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4664 IIC_SSE_MASKMOV>, VEX;
4665 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4666 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4667 (ins VR128:$src, VR128:$mask),
4668 "maskmovdqu\t{$mask, $src|$src, $mask}",
4669 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4670 IIC_SSE_MASKMOV>, VEX;
4672 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4673 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4674 "maskmovdqu\t{$mask, $src|$src, $mask}",
4675 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4677 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4678 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4679 "maskmovdqu\t{$mask, $src|$src, $mask}",
4680 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4683 } // ExeDomain = SSEPackedInt
4685 //===---------------------------------------------------------------------===//
4686 // SSE2 - Move Doubleword
4687 //===---------------------------------------------------------------------===//
4689 //===---------------------------------------------------------------------===//
4690 // Move Int Doubleword to Packed Double Int
4692 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4693 "movd\t{$src, $dst|$dst, $src}",
4695 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4696 VEX, Sched<[WriteMove]>;
4697 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4698 "movd\t{$src, $dst|$dst, $src}",
4700 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4702 VEX, Sched<[WriteLoad]>;
4703 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4704 "movq\t{$src, $dst|$dst, $src}",
4706 (v2i64 (scalar_to_vector GR64:$src)))],
4707 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4708 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4709 def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4710 "movq\t{$src, $dst|$dst, $src}",
4711 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteLoad]>;
4712 let isCodeGenOnly = 1 in
4713 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4714 "movq\t{$src, $dst|$dst, $src}",
4715 [(set FR64:$dst, (bitconvert GR64:$src))],
4716 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4718 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4719 "movd\t{$src, $dst|$dst, $src}",
4721 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4723 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4724 "movd\t{$src, $dst|$dst, $src}",
4726 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4727 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4728 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4729 "mov{d|q}\t{$src, $dst|$dst, $src}",
4731 (v2i64 (scalar_to_vector GR64:$src)))],
4732 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4733 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4734 def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4735 "mov{d|q}\t{$src, $dst|$dst, $src}",
4736 [], IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4737 let isCodeGenOnly = 1 in
4738 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4739 "mov{d|q}\t{$src, $dst|$dst, $src}",
4740 [(set FR64:$dst, (bitconvert GR64:$src))],
4741 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4743 //===---------------------------------------------------------------------===//
4744 // Move Int Doubleword to Single Scalar
4746 let isCodeGenOnly = 1 in {
4747 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4748 "movd\t{$src, $dst|$dst, $src}",
4749 [(set FR32:$dst, (bitconvert GR32:$src))],
4750 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4752 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4753 "movd\t{$src, $dst|$dst, $src}",
4754 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4756 VEX, Sched<[WriteLoad]>;
4757 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4758 "movd\t{$src, $dst|$dst, $src}",
4759 [(set FR32:$dst, (bitconvert GR32:$src))],
4760 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4762 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4763 "movd\t{$src, $dst|$dst, $src}",
4764 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4765 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4768 //===---------------------------------------------------------------------===//
4769 // Move Packed Doubleword Int to Packed Double Int
4771 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4772 "movd\t{$src, $dst|$dst, $src}",
4773 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4774 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4776 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4777 (ins i32mem:$dst, VR128:$src),
4778 "movd\t{$src, $dst|$dst, $src}",
4779 [(store (i32 (vector_extract (v4i32 VR128:$src),
4780 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4781 VEX, Sched<[WriteStore]>;
4782 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4783 "movd\t{$src, $dst|$dst, $src}",
4784 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4785 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4787 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4788 "movd\t{$src, $dst|$dst, $src}",
4789 [(store (i32 (vector_extract (v4i32 VR128:$src),
4790 (iPTR 0))), addr:$dst)],
4791 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4793 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4794 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4796 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4797 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4799 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4800 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4802 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4803 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4805 //===---------------------------------------------------------------------===//
4806 // Move Packed Doubleword Int first element to Doubleword Int
4808 let SchedRW = [WriteMove] in {
4809 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4810 "movq\t{$src, $dst|$dst, $src}",
4811 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4816 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4817 "mov{d|q}\t{$src, $dst|$dst, $src}",
4818 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4823 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4824 def VMOVPQIto64rm : VRS2I<0x7E, MRMDestMem, (outs i64mem:$dst),
4825 (ins VR128:$src), "movq\t{$src, $dst|$dst, $src}",
4826 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4827 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4828 def MOVPQIto64rm : RS2I<0x7E, MRMDestMem, (outs i64mem:$dst), (ins VR128:$src),
4829 "mov{d|q}\t{$src, $dst|$dst, $src}",
4830 [], IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4832 //===---------------------------------------------------------------------===//
4833 // Bitcast FR64 <-> GR64
4835 let isCodeGenOnly = 1 in {
4836 let Predicates = [UseAVX] in
4837 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4838 "movq\t{$src, $dst|$dst, $src}",
4839 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4840 VEX, Sched<[WriteLoad]>;
4841 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4842 "movq\t{$src, $dst|$dst, $src}",
4843 [(set GR64:$dst, (bitconvert FR64:$src))],
4844 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4845 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4846 "movq\t{$src, $dst|$dst, $src}",
4847 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4848 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4850 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4851 "movq\t{$src, $dst|$dst, $src}",
4852 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4853 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4854 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4855 "mov{d|q}\t{$src, $dst|$dst, $src}",
4856 [(set GR64:$dst, (bitconvert FR64:$src))],
4857 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4858 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4859 "movq\t{$src, $dst|$dst, $src}",
4860 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4861 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4864 //===---------------------------------------------------------------------===//
4865 // Move Scalar Single to Double Int
4867 let isCodeGenOnly = 1 in {
4868 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4869 "movd\t{$src, $dst|$dst, $src}",
4870 [(set GR32:$dst, (bitconvert FR32:$src))],
4871 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4872 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4873 "movd\t{$src, $dst|$dst, $src}",
4874 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4875 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4876 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4877 "movd\t{$src, $dst|$dst, $src}",
4878 [(set GR32:$dst, (bitconvert FR32:$src))],
4879 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4880 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4881 "movd\t{$src, $dst|$dst, $src}",
4882 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4883 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4886 //===---------------------------------------------------------------------===//
4887 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4889 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4890 let AddedComplexity = 15 in {
4891 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4892 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4893 [(set VR128:$dst, (v2i64 (X86vzmovl
4894 (v2i64 (scalar_to_vector GR64:$src)))))],
4897 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4898 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4899 [(set VR128:$dst, (v2i64 (X86vzmovl
4900 (v2i64 (scalar_to_vector GR64:$src)))))],
4903 } // isCodeGenOnly, SchedRW
4905 let Predicates = [UseAVX] in {
4906 let AddedComplexity = 15 in
4907 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4908 (VMOVDI2PDIrr GR32:$src)>;
4910 // AVX 128-bit movd/movq instructions write zeros in the high 128-bit part.
4911 // These instructions also write zeros in the high part of a 256-bit register.
4912 let AddedComplexity = 20 in {
4913 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4914 (VMOVDI2PDIrm addr:$src)>;
4915 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4916 (VMOVDI2PDIrm addr:$src)>;
4917 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4918 (VMOVDI2PDIrm addr:$src)>;
4919 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4920 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
4921 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrm addr:$src), sub_xmm)>;
4923 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4924 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4925 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4926 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4927 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4928 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4929 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4932 let Predicates = [UseSSE2] in {
4933 let AddedComplexity = 15 in
4934 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4935 (MOVDI2PDIrr GR32:$src)>;
4937 let AddedComplexity = 20 in {
4938 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4939 (MOVDI2PDIrm addr:$src)>;
4940 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4941 (MOVDI2PDIrm addr:$src)>;
4942 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4943 (MOVDI2PDIrm addr:$src)>;
4947 // These are the correct encodings of the instructions so that we know how to
4948 // read correct assembly, even though we continue to emit the wrong ones for
4949 // compatibility with Darwin's buggy assembler.
4950 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4951 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4952 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4953 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4954 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4955 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4956 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4957 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4958 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4960 //===---------------------------------------------------------------------===//
4961 // SSE2 - Move Quadword
4962 //===---------------------------------------------------------------------===//
4964 //===---------------------------------------------------------------------===//
4965 // Move Quadword Int to Packed Quadword Int
4968 let ExeDomain = SSEPackedInt, SchedRW = [WriteLoad] in {
4969 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4970 "vmovq\t{$src, $dst|$dst, $src}",
4972 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4973 VEX, Requires<[UseAVX]>;
4974 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4975 "movq\t{$src, $dst|$dst, $src}",
4977 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4979 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4980 } // ExeDomain, SchedRW
4982 //===---------------------------------------------------------------------===//
4983 // Move Packed Quadword Int to Quadword Int
4985 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4986 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4987 "movq\t{$src, $dst|$dst, $src}",
4988 [(store (i64 (vector_extract (v2i64 VR128:$src),
4989 (iPTR 0))), addr:$dst)],
4990 IIC_SSE_MOVDQ>, VEX;
4991 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4992 "movq\t{$src, $dst|$dst, $src}",
4993 [(store (i64 (vector_extract (v2i64 VR128:$src),
4994 (iPTR 0))), addr:$dst)],
4996 } // ExeDomain, SchedRW
4998 // For disassembler only
4999 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
5000 SchedRW = [WriteVecLogic] in {
5001 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5002 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
5003 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5004 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
5007 //===---------------------------------------------------------------------===//
5008 // Store / copy lower 64-bits of a XMM register.
5010 let Predicates = [HasAVX] in
5011 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5012 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5013 let Predicates = [UseSSE2] in
5014 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5015 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5017 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, AddedComplexity = 20 in {
5018 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5019 "vmovq\t{$src, $dst|$dst, $src}",
5021 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5022 (loadi64 addr:$src))))))],
5024 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5026 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5027 "movq\t{$src, $dst|$dst, $src}",
5029 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5030 (loadi64 addr:$src))))))],
5032 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5033 } // ExeDomain, isCodeGenOnly, AddedComplexity
5035 let Predicates = [UseAVX], AddedComplexity = 20 in {
5036 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5037 (VMOVZQI2PQIrm addr:$src)>;
5038 def : Pat<(v2i64 (X86vzload addr:$src)),
5039 (VMOVZQI2PQIrm addr:$src)>;
5040 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5041 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
5042 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
5045 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5046 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5047 (MOVZQI2PQIrm addr:$src)>;
5048 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5051 let Predicates = [HasAVX] in {
5052 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5053 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5054 def : Pat<(v4i64 (X86vzload addr:$src)),
5055 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5058 //===---------------------------------------------------------------------===//
5059 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5060 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5062 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
5063 let AddedComplexity = 15 in
5064 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5065 "vmovq\t{$src, $dst|$dst, $src}",
5066 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5068 XS, VEX, Requires<[UseAVX]>;
5069 let AddedComplexity = 15 in
5070 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5071 "movq\t{$src, $dst|$dst, $src}",
5072 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5074 XS, Requires<[UseSSE2]>;
5075 } // ExeDomain, SchedRW
5077 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5078 let AddedComplexity = 20 in
5079 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5080 "vmovq\t{$src, $dst|$dst, $src}",
5081 [(set VR128:$dst, (v2i64 (X86vzmovl
5082 (loadv2i64 addr:$src))))],
5084 XS, VEX, Requires<[UseAVX]>;
5085 let AddedComplexity = 20 in {
5086 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5087 "movq\t{$src, $dst|$dst, $src}",
5088 [(set VR128:$dst, (v2i64 (X86vzmovl
5089 (loadv2i64 addr:$src))))],
5091 XS, Requires<[UseSSE2]>;
5093 } // ExeDomain, isCodeGenOnly, SchedRW
5095 let AddedComplexity = 20 in {
5096 let Predicates = [UseAVX] in {
5097 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5098 (VMOVZPQILo2PQIrr VR128:$src)>;
5100 let Predicates = [UseSSE2] in {
5101 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5102 (MOVZPQILo2PQIrr VR128:$src)>;
5106 //===---------------------------------------------------------------------===//
5107 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5108 //===---------------------------------------------------------------------===//
5109 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5110 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5111 X86MemOperand x86memop> {
5112 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5113 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5114 [(set RC:$dst, (vt (OpNode RC:$src)))],
5115 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5116 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5117 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5118 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5119 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5122 let Predicates = [HasAVX] in {
5123 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5124 v4f32, VR128, loadv4f32, f128mem>, VEX;
5125 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5126 v4f32, VR128, loadv4f32, f128mem>, VEX;
5127 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5128 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5129 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5130 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5132 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5133 memopv4f32, f128mem>;
5134 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5135 memopv4f32, f128mem>;
5137 let Predicates = [HasAVX] in {
5138 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5139 (VMOVSHDUPrr VR128:$src)>;
5140 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5141 (VMOVSHDUPrm addr:$src)>;
5142 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5143 (VMOVSLDUPrr VR128:$src)>;
5144 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5145 (VMOVSLDUPrm addr:$src)>;
5146 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5147 (VMOVSHDUPYrr VR256:$src)>;
5148 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5149 (VMOVSHDUPYrm addr:$src)>;
5150 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5151 (VMOVSLDUPYrr VR256:$src)>;
5152 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5153 (VMOVSLDUPYrm addr:$src)>;
5156 let Predicates = [UseSSE3] in {
5157 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5158 (MOVSHDUPrr VR128:$src)>;
5159 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5160 (MOVSHDUPrm addr:$src)>;
5161 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5162 (MOVSLDUPrr VR128:$src)>;
5163 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5164 (MOVSLDUPrm addr:$src)>;
5167 //===---------------------------------------------------------------------===//
5168 // SSE3 - Replicate Double FP - MOVDDUP
5169 //===---------------------------------------------------------------------===//
5171 multiclass sse3_replicate_dfp<string OpcodeStr> {
5172 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5173 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5174 [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))],
5175 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5176 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5177 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5180 (scalar_to_vector (loadf64 addr:$src)))))],
5181 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5184 // FIXME: Merge with above classe when there're patterns for the ymm version
5185 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5186 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5187 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5188 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5189 Sched<[WriteFShuffle]>;
5190 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5191 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5194 (scalar_to_vector (loadf64 addr:$src)))))]>,
5198 let Predicates = [HasAVX] in {
5199 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5200 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5203 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5205 let Predicates = [HasAVX] in {
5206 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5207 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5208 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5209 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5210 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5211 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5212 def : Pat<(X86Movddup (bc_v2f64
5213 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5214 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5217 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5218 (VMOVDDUPYrm addr:$src)>;
5219 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5220 (VMOVDDUPYrm addr:$src)>;
5221 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5222 (VMOVDDUPYrm addr:$src)>;
5223 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5224 (VMOVDDUPYrr VR256:$src)>;
5227 let Predicates = [UseAVX, OptForSize] in {
5228 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5229 (VMOVDDUPrm addr:$src)>;
5230 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5231 (VMOVDDUPrm addr:$src)>;
5234 let Predicates = [UseSSE3] in {
5235 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5236 (MOVDDUPrm addr:$src)>;
5237 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5238 (MOVDDUPrm addr:$src)>;
5239 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5240 (MOVDDUPrm addr:$src)>;
5241 def : Pat<(X86Movddup (bc_v2f64
5242 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5243 (MOVDDUPrm addr:$src)>;
5246 //===---------------------------------------------------------------------===//
5247 // SSE3 - Move Unaligned Integer
5248 //===---------------------------------------------------------------------===//
5250 let SchedRW = [WriteLoad] in {
5251 let Predicates = [HasAVX] in {
5252 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5253 "vlddqu\t{$src, $dst|$dst, $src}",
5254 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5255 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5256 "vlddqu\t{$src, $dst|$dst, $src}",
5257 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5260 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5261 "lddqu\t{$src, $dst|$dst, $src}",
5262 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5266 //===---------------------------------------------------------------------===//
5267 // SSE3 - Arithmetic
5268 //===---------------------------------------------------------------------===//
5270 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5271 X86MemOperand x86memop, OpndItins itins,
5272 PatFrag ld_frag, bit Is2Addr = 1> {
5273 def rr : I<0xD0, MRMSrcReg,
5274 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5276 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5277 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5278 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5279 Sched<[itins.Sched]>;
5280 def rm : I<0xD0, MRMSrcMem,
5281 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5283 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5284 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5285 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))], itins.rr>,
5286 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5289 let Predicates = [HasAVX] in {
5290 let ExeDomain = SSEPackedSingle in {
5291 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5292 f128mem, SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V;
5293 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5294 f256mem, SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V, VEX_L;
5296 let ExeDomain = SSEPackedDouble in {
5297 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5298 f128mem, SSE_ALU_F64P, loadv2f64, 0>, PD, VEX_4V;
5299 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5300 f256mem, SSE_ALU_F64P, loadv4f64, 0>, PD, VEX_4V, VEX_L;
5303 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5304 let ExeDomain = SSEPackedSingle in
5305 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5306 f128mem, SSE_ALU_F32P, memopv4f32>, XD;
5307 let ExeDomain = SSEPackedDouble in
5308 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5309 f128mem, SSE_ALU_F64P, memopv2f64>, PD;
5312 // Patterns used to select 'addsub' instructions.
5313 let Predicates = [HasAVX] in {
5314 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5315 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5316 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (loadv4f32 addr:$rhs))),
5317 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5318 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5319 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5320 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (loadv2f64 addr:$rhs))),
5321 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5323 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5324 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5325 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (loadv8f32 addr:$rhs))),
5326 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5327 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5328 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5329 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (loadv4f64 addr:$rhs))),
5330 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5333 let Predicates = [UseSSE3] in {
5334 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5335 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5336 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (memopv4f32 addr:$rhs))),
5337 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5338 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5339 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5340 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (memopv2f64 addr:$rhs))),
5341 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5344 //===---------------------------------------------------------------------===//
5345 // SSE3 Instructions
5346 //===---------------------------------------------------------------------===//
5349 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5350 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5352 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5354 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5355 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5356 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5359 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5361 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5362 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5363 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5364 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5366 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5367 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5369 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5371 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5372 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5373 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5376 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5378 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5379 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5380 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5381 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5384 let Predicates = [HasAVX] in {
5385 let ExeDomain = SSEPackedSingle in {
5386 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5387 X86fhadd, loadv4f32, 0>, VEX_4V;
5388 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5389 X86fhsub, loadv4f32, 0>, VEX_4V;
5390 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5391 X86fhadd, loadv8f32, 0>, VEX_4V, VEX_L;
5392 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5393 X86fhsub, loadv8f32, 0>, VEX_4V, VEX_L;
5395 let ExeDomain = SSEPackedDouble in {
5396 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5397 X86fhadd, loadv2f64, 0>, VEX_4V;
5398 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5399 X86fhsub, loadv2f64, 0>, VEX_4V;
5400 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5401 X86fhadd, loadv4f64, 0>, VEX_4V, VEX_L;
5402 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5403 X86fhsub, loadv4f64, 0>, VEX_4V, VEX_L;
5407 let Constraints = "$src1 = $dst" in {
5408 let ExeDomain = SSEPackedSingle in {
5409 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd,
5411 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub,
5414 let ExeDomain = SSEPackedDouble in {
5415 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd,
5417 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub,
5422 //===---------------------------------------------------------------------===//
5423 // SSSE3 - Packed Absolute Instructions
5424 //===---------------------------------------------------------------------===//
5427 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5428 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
5430 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5432 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5433 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5434 Sched<[WriteVecALU]>;
5436 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5438 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5441 (bitconvert (ld_frag addr:$src))))], IIC_SSE_PABS_RM>,
5442 Sched<[WriteVecALULd]>;
5445 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5446 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5447 Intrinsic IntId256> {
5448 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5450 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5451 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5452 Sched<[WriteVecALU]>;
5454 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5456 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5459 (bitconvert (loadv4i64 addr:$src))))]>,
5460 Sched<[WriteVecALULd]>;
5463 // Helper fragments to match sext vXi1 to vXiY.
5464 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5466 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5467 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5468 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5470 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5471 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5473 let Predicates = [HasAVX] in {
5474 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", int_x86_ssse3_pabs_b_128,
5476 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", int_x86_ssse3_pabs_w_128,
5478 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", int_x86_ssse3_pabs_d_128,
5482 (bc_v2i64 (v16i1sextv16i8)),
5483 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5484 (VPABSBrr128 VR128:$src)>;
5486 (bc_v2i64 (v8i1sextv8i16)),
5487 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5488 (VPABSWrr128 VR128:$src)>;
5490 (bc_v2i64 (v4i1sextv4i32)),
5491 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5492 (VPABSDrr128 VR128:$src)>;
5495 let Predicates = [HasAVX2] in {
5496 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5497 int_x86_avx2_pabs_b>, VEX, VEX_L;
5498 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5499 int_x86_avx2_pabs_w>, VEX, VEX_L;
5500 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5501 int_x86_avx2_pabs_d>, VEX, VEX_L;
5504 (bc_v4i64 (v32i1sextv32i8)),
5505 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5506 (VPABSBrr256 VR256:$src)>;
5508 (bc_v4i64 (v16i1sextv16i16)),
5509 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5510 (VPABSWrr256 VR256:$src)>;
5512 (bc_v4i64 (v8i1sextv8i32)),
5513 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5514 (VPABSDrr256 VR256:$src)>;
5517 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", int_x86_ssse3_pabs_b_128,
5519 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", int_x86_ssse3_pabs_w_128,
5521 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", int_x86_ssse3_pabs_d_128,
5524 let Predicates = [HasSSSE3] in {
5526 (bc_v2i64 (v16i1sextv16i8)),
5527 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5528 (PABSBrr128 VR128:$src)>;
5530 (bc_v2i64 (v8i1sextv8i16)),
5531 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5532 (PABSWrr128 VR128:$src)>;
5534 (bc_v2i64 (v4i1sextv4i32)),
5535 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5536 (PABSDrr128 VR128:$src)>;
5539 //===---------------------------------------------------------------------===//
5540 // SSSE3 - Packed Binary Operator Instructions
5541 //===---------------------------------------------------------------------===//
5543 let Sched = WriteVecALU in {
5544 def SSE_PHADDSUBD : OpndItins<
5545 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5547 def SSE_PHADDSUBSW : OpndItins<
5548 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5550 def SSE_PHADDSUBW : OpndItins<
5551 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5554 let Sched = WriteShuffle in
5555 def SSE_PSHUFB : OpndItins<
5556 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5558 let Sched = WriteVecALU in
5559 def SSE_PSIGN : OpndItins<
5560 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5562 let Sched = WriteVecIMul in
5563 def SSE_PMULHRSW : OpndItins<
5564 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5567 /// SS3I_binop_rm - Simple SSSE3 bin op
5568 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5569 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5570 X86MemOperand x86memop, OpndItins itins,
5572 let isCommutable = 1 in
5573 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5574 (ins RC:$src1, RC:$src2),
5576 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5577 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5578 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5579 Sched<[itins.Sched]>;
5580 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5581 (ins RC:$src1, x86memop:$src2),
5583 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5584 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5586 (OpVT (OpNode RC:$src1,
5587 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5588 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5591 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5592 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5593 Intrinsic IntId128, OpndItins itins,
5594 PatFrag ld_frag, bit Is2Addr = 1> {
5595 let isCommutable = 1 in
5596 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5597 (ins VR128:$src1, VR128:$src2),
5599 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5600 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5601 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5602 Sched<[itins.Sched]>;
5603 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5604 (ins VR128:$src1, i128mem:$src2),
5606 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5607 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5609 (IntId128 VR128:$src1,
5610 (bitconvert (ld_frag addr:$src2))))]>,
5611 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5614 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5616 X86FoldableSchedWrite Sched> {
5617 let isCommutable = 1 in
5618 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5619 (ins VR256:$src1, VR256:$src2),
5620 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5621 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5623 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5624 (ins VR256:$src1, i256mem:$src2),
5625 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5627 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5628 Sched<[Sched.Folded, ReadAfterLd]>;
5631 let ImmT = NoImm, Predicates = [HasAVX] in {
5632 let isCommutable = 0 in {
5633 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5635 SSE_PHADDSUBW, 0>, VEX_4V;
5636 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5638 SSE_PHADDSUBD, 0>, VEX_4V;
5639 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5641 SSE_PHADDSUBW, 0>, VEX_4V;
5642 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5644 SSE_PHADDSUBD, 0>, VEX_4V;
5645 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5647 SSE_PSIGN, 0>, VEX_4V;
5648 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5650 SSE_PSIGN, 0>, VEX_4V;
5651 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5653 SSE_PSIGN, 0>, VEX_4V;
5654 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5656 SSE_PSHUFB, 0>, VEX_4V;
5657 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5658 int_x86_ssse3_phadd_sw_128,
5659 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5660 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5661 int_x86_ssse3_phsub_sw_128,
5662 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5663 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5664 int_x86_ssse3_pmadd_ub_sw_128,
5665 SSE_PMADD, loadv2i64, 0>, VEX_4V;
5667 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5668 int_x86_ssse3_pmul_hr_sw_128,
5669 SSE_PMULHRSW, loadv2i64, 0>, VEX_4V;
5672 let ImmT = NoImm, Predicates = [HasAVX2] in {
5673 let isCommutable = 0 in {
5674 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5676 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5677 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5679 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5680 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5682 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5683 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5685 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5686 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5688 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5689 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5691 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5692 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5694 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5695 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5697 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5698 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5699 int_x86_avx2_phadd_sw,
5700 WriteVecALU>, VEX_4V, VEX_L;
5701 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5702 int_x86_avx2_phsub_sw,
5703 WriteVecALU>, VEX_4V, VEX_L;
5704 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5705 int_x86_avx2_pmadd_ub_sw,
5706 WriteVecIMul>, VEX_4V, VEX_L;
5708 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5709 int_x86_avx2_pmul_hr_sw,
5710 WriteVecIMul>, VEX_4V, VEX_L;
5713 // None of these have i8 immediate fields.
5714 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5715 let isCommutable = 0 in {
5716 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5717 memopv2i64, i128mem, SSE_PHADDSUBW>;
5718 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5719 memopv2i64, i128mem, SSE_PHADDSUBD>;
5720 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5721 memopv2i64, i128mem, SSE_PHADDSUBW>;
5722 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5723 memopv2i64, i128mem, SSE_PHADDSUBD>;
5724 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5725 memopv2i64, i128mem, SSE_PSIGN>;
5726 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5727 memopv2i64, i128mem, SSE_PSIGN>;
5728 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5729 memopv2i64, i128mem, SSE_PSIGN>;
5730 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5731 memopv2i64, i128mem, SSE_PSHUFB>;
5732 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5733 int_x86_ssse3_phadd_sw_128,
5734 SSE_PHADDSUBSW, memopv2i64>;
5735 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5736 int_x86_ssse3_phsub_sw_128,
5737 SSE_PHADDSUBSW, memopv2i64>;
5738 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5739 int_x86_ssse3_pmadd_ub_sw_128,
5740 SSE_PMADD, memopv2i64>;
5742 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5743 int_x86_ssse3_pmul_hr_sw_128,
5744 SSE_PMULHRSW, memopv2i64>;
5747 //===---------------------------------------------------------------------===//
5748 // SSSE3 - Packed Align Instruction Patterns
5749 //===---------------------------------------------------------------------===//
5751 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5752 let hasSideEffects = 0 in {
5753 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5754 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
5756 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5758 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5759 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5761 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5762 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
5764 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5766 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5767 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5771 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5772 let hasSideEffects = 0 in {
5773 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5774 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
5776 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5777 []>, Sched<[WriteShuffle]>;
5779 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5780 (ins VR256:$src1, i256mem:$src2, u8imm:$src3),
5782 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5783 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5787 let Predicates = [HasAVX] in
5788 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5789 let Predicates = [HasAVX2] in
5790 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5791 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5792 defm PALIGN : ssse3_palignr<"palignr">;
5794 let Predicates = [HasAVX2] in {
5795 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5796 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5797 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5798 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5799 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5800 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5801 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5802 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5805 let Predicates = [HasAVX] in {
5806 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5807 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5808 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5809 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5810 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5811 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5812 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5813 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5816 let Predicates = [UseSSSE3] in {
5817 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5818 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5819 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5820 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5821 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5822 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5823 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5824 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5827 //===---------------------------------------------------------------------===//
5828 // SSSE3 - Thread synchronization
5829 //===---------------------------------------------------------------------===//
5831 let SchedRW = [WriteSystem] in {
5832 let usesCustomInserter = 1 in {
5833 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5834 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5835 Requires<[HasSSE3]>;
5838 let Uses = [EAX, ECX, EDX] in
5839 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5840 TB, Requires<[HasSSE3]>;
5841 let Uses = [ECX, EAX] in
5842 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5843 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5844 TB, Requires<[HasSSE3]>;
5847 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5848 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5850 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5851 Requires<[Not64BitMode]>;
5852 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5853 Requires<[In64BitMode]>;
5855 //===----------------------------------------------------------------------===//
5856 // SSE4.1 - Packed Move with Sign/Zero Extend
5857 //===----------------------------------------------------------------------===//
5859 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
5860 RegisterClass OutRC, RegisterClass InRC,
5862 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
5863 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5865 Sched<[itins.Sched]>;
5867 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
5868 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5870 itins.rm>, Sched<[itins.Sched.Folded]>;
5873 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
5874 X86MemOperand MemOp, X86MemOperand MemYOp,
5875 OpndItins SSEItins, OpndItins AVXItins,
5876 OpndItins AVX2Itins> {
5877 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
5878 let Predicates = [HasAVX, NoVLX] in
5879 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
5880 VR128, VR128, AVXItins>, VEX;
5881 let Predicates = [HasAVX2, NoVLX] in
5882 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
5883 VR256, VR128, AVX2Itins>, VEX, VEX_L;
5886 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
5887 X86MemOperand MemOp, X86MemOperand MemYOp> {
5888 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
5890 SSE_INTALU_ITINS_SHUFF_P,
5891 DEFAULT_ITINS_SHUFFLESCHED,
5892 DEFAULT_ITINS_SHUFFLESCHED>;
5893 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
5894 !strconcat("pmovzx", OpcodeStr),
5896 SSE_INTALU_ITINS_SHUFF_P,
5897 DEFAULT_ITINS_SHUFFLESCHED,
5898 DEFAULT_ITINS_SHUFFLESCHED>;
5901 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
5902 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
5903 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
5905 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
5906 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
5908 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
5911 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
5912 // Register-Register patterns
5913 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5914 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
5915 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
5916 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
5917 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
5918 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
5920 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5921 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
5922 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
5923 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
5925 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5926 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
5928 // On AVX2, we also support 256bit inputs.
5929 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
5930 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5931 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
5932 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5933 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
5934 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5936 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
5937 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5938 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
5939 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5941 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
5942 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5944 // Simple Register-Memory patterns
5945 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5946 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5947 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5948 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5949 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5950 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5952 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5953 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5954 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5955 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5957 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5958 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5960 // AVX2 Register-Memory patterns
5961 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5962 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5963 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5964 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5965 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5966 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5967 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5968 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5970 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5971 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5972 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5973 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5974 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5975 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5976 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5977 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5979 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
5980 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5981 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
5982 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5983 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5984 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5985 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5986 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5988 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5989 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5990 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5991 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5992 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5993 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5994 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5995 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5997 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5998 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5999 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6000 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6001 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6002 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6003 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6004 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6006 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6007 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6008 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6009 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6010 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6011 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6012 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6013 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6016 let Predicates = [HasAVX2, NoVLX] in {
6017 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
6018 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
6021 // SSE4.1/AVX patterns.
6022 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
6023 SDNode ExtOp, PatFrag ExtLoad16> {
6024 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6025 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6026 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6027 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6028 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6029 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6031 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6032 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6033 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6034 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6036 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6037 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6039 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6040 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6041 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6042 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6043 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6044 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6046 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6047 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6048 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6049 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6051 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6052 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6054 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6055 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6056 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6057 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6058 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6059 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6060 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6061 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6062 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6063 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6065 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6066 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6067 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6068 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6069 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6070 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6071 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6072 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6074 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6075 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6076 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6077 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6078 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6079 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6080 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6081 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6083 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6084 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6085 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6086 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6087 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6088 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6089 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6090 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6091 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6092 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6094 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6095 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6096 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6097 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6098 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6099 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6100 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6101 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6103 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6104 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6105 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6106 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6107 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6108 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6109 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6110 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6111 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6112 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6115 let Predicates = [HasAVX, NoVLX] in {
6116 defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
6117 defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
6120 let Predicates = [UseSSE41] in {
6121 defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
6122 defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
6125 //===----------------------------------------------------------------------===//
6126 // SSE4.1 - Extract Instructions
6127 //===----------------------------------------------------------------------===//
6129 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6130 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6131 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6132 (ins VR128:$src1, u8imm:$src2),
6133 !strconcat(OpcodeStr,
6134 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6135 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6137 Sched<[WriteShuffle]>;
6138 let hasSideEffects = 0, mayStore = 1,
6139 SchedRW = [WriteShuffleLd, WriteRMW] in
6140 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6141 (ins i8mem:$dst, VR128:$src1, u8imm:$src2),
6142 !strconcat(OpcodeStr,
6143 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6144 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6145 imm:$src2)))), addr:$dst)]>;
6148 let Predicates = [HasAVX] in
6149 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6151 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6154 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6155 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6156 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6157 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6158 (ins VR128:$src1, u8imm:$src2),
6159 !strconcat(OpcodeStr,
6160 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6161 []>, Sched<[WriteShuffle]>;
6163 let hasSideEffects = 0, mayStore = 1,
6164 SchedRW = [WriteShuffleLd, WriteRMW] in
6165 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6166 (ins i16mem:$dst, VR128:$src1, u8imm:$src2),
6167 !strconcat(OpcodeStr,
6168 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6169 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6170 imm:$src2)))), addr:$dst)]>;
6173 let Predicates = [HasAVX] in
6174 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6176 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6179 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6180 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6181 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6182 (ins VR128:$src1, u8imm:$src2),
6183 !strconcat(OpcodeStr,
6184 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6186 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6187 Sched<[WriteShuffle]>;
6188 let SchedRW = [WriteShuffleLd, WriteRMW] in
6189 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6190 (ins i32mem:$dst, VR128:$src1, u8imm:$src2),
6191 !strconcat(OpcodeStr,
6192 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6193 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6197 let Predicates = [HasAVX] in
6198 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6200 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6202 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6203 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6204 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6205 (ins VR128:$src1, u8imm:$src2),
6206 !strconcat(OpcodeStr,
6207 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6209 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6210 Sched<[WriteShuffle]>, REX_W;
6211 let SchedRW = [WriteShuffleLd, WriteRMW] in
6212 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6213 (ins i64mem:$dst, VR128:$src1, u8imm:$src2),
6214 !strconcat(OpcodeStr,
6215 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6216 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6217 addr:$dst)]>, REX_W;
6220 let Predicates = [HasAVX] in
6221 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6223 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6225 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6227 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6228 OpndItins itins = DEFAULT_ITINS> {
6229 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6230 (ins VR128:$src1, u8imm:$src2),
6231 !strconcat(OpcodeStr,
6232 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6233 [(set GR32orGR64:$dst,
6234 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6235 itins.rr>, Sched<[WriteFBlend]>;
6236 let SchedRW = [WriteFBlendLd, WriteRMW] in
6237 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6238 (ins f32mem:$dst, VR128:$src1, u8imm:$src2),
6239 !strconcat(OpcodeStr,
6240 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6241 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6242 addr:$dst)], itins.rm>;
6245 let ExeDomain = SSEPackedSingle in {
6246 let Predicates = [UseAVX] in
6247 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6248 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6251 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6252 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6255 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6257 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6260 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6261 Requires<[UseSSE41]>;
6263 //===----------------------------------------------------------------------===//
6264 // SSE4.1 - Insert Instructions
6265 //===----------------------------------------------------------------------===//
6267 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6268 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6269 (ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
6271 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6273 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6275 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6276 Sched<[WriteShuffle]>;
6277 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6278 (ins VR128:$src1, i8mem:$src2, u8imm:$src3),
6280 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6282 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6284 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6285 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6288 let Predicates = [HasAVX] in
6289 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6290 let Constraints = "$src1 = $dst" in
6291 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6293 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6294 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6295 (ins VR128:$src1, GR32:$src2, u8imm:$src3),
6297 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6299 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6301 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6302 Sched<[WriteShuffle]>;
6303 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6304 (ins VR128:$src1, i32mem:$src2, u8imm:$src3),
6306 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6308 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6310 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6311 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6314 let Predicates = [HasAVX] in
6315 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6316 let Constraints = "$src1 = $dst" in
6317 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6319 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6320 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6321 (ins VR128:$src1, GR64:$src2, u8imm:$src3),
6323 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6325 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6327 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6328 Sched<[WriteShuffle]>;
6329 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6330 (ins VR128:$src1, i64mem:$src2, u8imm:$src3),
6332 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6334 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6336 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6337 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6340 let Predicates = [HasAVX] in
6341 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6342 let Constraints = "$src1 = $dst" in
6343 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6345 // insertps has a few different modes, there's the first two here below which
6346 // are optimized inserts that won't zero arbitrary elements in the destination
6347 // vector. The next one matches the intrinsic and could zero arbitrary elements
6348 // in the target vector.
6349 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6350 OpndItins itins = DEFAULT_ITINS> {
6351 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6352 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
6354 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6356 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6358 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6359 Sched<[WriteFShuffle]>;
6360 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6361 (ins VR128:$src1, f32mem:$src2, u8imm:$src3),
6363 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6365 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6367 (X86insertps VR128:$src1,
6368 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6369 imm:$src3))], itins.rm>,
6370 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6373 let ExeDomain = SSEPackedSingle in {
6374 let Predicates = [UseAVX] in
6375 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6376 let Constraints = "$src1 = $dst" in
6377 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6380 let Predicates = [UseSSE41] in {
6381 // If we're inserting an element from a load or a null pshuf of a load,
6382 // fold the load into the insertps instruction.
6383 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6384 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6386 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6387 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6388 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6389 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6392 let Predicates = [UseAVX] in {
6393 // If we're inserting an element from a vbroadcast of a load, fold the
6394 // load into the X86insertps instruction.
6395 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6396 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6397 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6398 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6399 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6400 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6403 //===----------------------------------------------------------------------===//
6404 // SSE4.1 - Round Instructions
6405 //===----------------------------------------------------------------------===//
6407 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6408 X86MemOperand x86memop, RegisterClass RC,
6409 PatFrag mem_frag32, PatFrag mem_frag64,
6410 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6411 let ExeDomain = SSEPackedSingle in {
6412 // Intrinsic operation, reg.
6413 // Vector intrinsic operation, reg
6414 def PSr : SS4AIi8<opcps, MRMSrcReg,
6415 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6416 !strconcat(OpcodeStr,
6417 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6418 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6419 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6421 // Vector intrinsic operation, mem
6422 def PSm : SS4AIi8<opcps, MRMSrcMem,
6423 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6424 !strconcat(OpcodeStr,
6425 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6427 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6428 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6429 } // ExeDomain = SSEPackedSingle
6431 let ExeDomain = SSEPackedDouble in {
6432 // Vector intrinsic operation, reg
6433 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6434 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6435 !strconcat(OpcodeStr,
6436 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6437 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6438 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6440 // Vector intrinsic operation, mem
6441 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6442 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6443 !strconcat(OpcodeStr,
6444 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6446 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6447 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6448 } // ExeDomain = SSEPackedDouble
6451 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6454 Intrinsic F64Int, bit Is2Addr = 1> {
6455 let ExeDomain = GenericDomain in {
6457 let hasSideEffects = 0 in
6458 def SSr : SS4AIi8<opcss, MRMSrcReg,
6459 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3),
6461 !strconcat(OpcodeStr,
6462 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6463 !strconcat(OpcodeStr,
6464 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6465 []>, Sched<[WriteFAdd]>;
6467 // Intrinsic operation, reg.
6468 let isCodeGenOnly = 1 in
6469 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6470 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6472 !strconcat(OpcodeStr,
6473 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6474 !strconcat(OpcodeStr,
6475 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6476 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6479 // Intrinsic operation, mem.
6480 def SSm : SS4AIi8<opcss, MRMSrcMem,
6481 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32u8imm:$src3),
6483 !strconcat(OpcodeStr,
6484 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6485 !strconcat(OpcodeStr,
6486 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6488 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6489 Sched<[WriteFAddLd, ReadAfterLd]>;
6492 let hasSideEffects = 0 in
6493 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6494 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3),
6496 !strconcat(OpcodeStr,
6497 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6498 !strconcat(OpcodeStr,
6499 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6500 []>, Sched<[WriteFAdd]>;
6502 // Intrinsic operation, reg.
6503 let isCodeGenOnly = 1 in
6504 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6505 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6507 !strconcat(OpcodeStr,
6508 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6509 !strconcat(OpcodeStr,
6510 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6511 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6514 // Intrinsic operation, mem.
6515 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6516 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32u8imm:$src3),
6518 !strconcat(OpcodeStr,
6519 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6520 !strconcat(OpcodeStr,
6521 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6523 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6524 Sched<[WriteFAddLd, ReadAfterLd]>;
6525 } // ExeDomain = GenericDomain
6528 // FP round - roundss, roundps, roundsd, roundpd
6529 let Predicates = [HasAVX] in {
6531 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6532 loadv4f32, loadv2f64,
6533 int_x86_sse41_round_ps,
6534 int_x86_sse41_round_pd>, VEX;
6535 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6536 loadv8f32, loadv4f64,
6537 int_x86_avx_round_ps_256,
6538 int_x86_avx_round_pd_256>, VEX, VEX_L;
6539 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6540 int_x86_sse41_round_ss,
6541 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6544 let Predicates = [UseAVX] in {
6545 def : Pat<(ffloor FR32:$src),
6546 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6547 def : Pat<(f64 (ffloor FR64:$src)),
6548 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6549 def : Pat<(f32 (fnearbyint FR32:$src)),
6550 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6551 def : Pat<(f64 (fnearbyint FR64:$src)),
6552 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6553 def : Pat<(f32 (fceil FR32:$src)),
6554 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6555 def : Pat<(f64 (fceil FR64:$src)),
6556 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6557 def : Pat<(f32 (frint FR32:$src)),
6558 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6559 def : Pat<(f64 (frint FR64:$src)),
6560 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6561 def : Pat<(f32 (ftrunc FR32:$src)),
6562 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6563 def : Pat<(f64 (ftrunc FR64:$src)),
6564 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6567 let Predicates = [HasAVX] in {
6568 def : Pat<(v4f32 (ffloor VR128:$src)),
6569 (VROUNDPSr VR128:$src, (i32 0x1))>;
6570 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6571 (VROUNDPSr VR128:$src, (i32 0xC))>;
6572 def : Pat<(v4f32 (fceil VR128:$src)),
6573 (VROUNDPSr VR128:$src, (i32 0x2))>;
6574 def : Pat<(v4f32 (frint VR128:$src)),
6575 (VROUNDPSr VR128:$src, (i32 0x4))>;
6576 def : Pat<(v4f32 (ftrunc VR128:$src)),
6577 (VROUNDPSr VR128:$src, (i32 0x3))>;
6579 def : Pat<(v2f64 (ffloor VR128:$src)),
6580 (VROUNDPDr VR128:$src, (i32 0x1))>;
6581 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6582 (VROUNDPDr VR128:$src, (i32 0xC))>;
6583 def : Pat<(v2f64 (fceil VR128:$src)),
6584 (VROUNDPDr VR128:$src, (i32 0x2))>;
6585 def : Pat<(v2f64 (frint VR128:$src)),
6586 (VROUNDPDr VR128:$src, (i32 0x4))>;
6587 def : Pat<(v2f64 (ftrunc VR128:$src)),
6588 (VROUNDPDr VR128:$src, (i32 0x3))>;
6590 def : Pat<(v8f32 (ffloor VR256:$src)),
6591 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6592 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6593 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6594 def : Pat<(v8f32 (fceil VR256:$src)),
6595 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6596 def : Pat<(v8f32 (frint VR256:$src)),
6597 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6598 def : Pat<(v8f32 (ftrunc VR256:$src)),
6599 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6601 def : Pat<(v4f64 (ffloor VR256:$src)),
6602 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6603 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6604 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6605 def : Pat<(v4f64 (fceil VR256:$src)),
6606 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6607 def : Pat<(v4f64 (frint VR256:$src)),
6608 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6609 def : Pat<(v4f64 (ftrunc VR256:$src)),
6610 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6613 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6614 memopv4f32, memopv2f64,
6615 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6616 let Constraints = "$src1 = $dst" in
6617 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6618 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6620 let Predicates = [UseSSE41] in {
6621 def : Pat<(ffloor FR32:$src),
6622 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6623 def : Pat<(f64 (ffloor FR64:$src)),
6624 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6625 def : Pat<(f32 (fnearbyint FR32:$src)),
6626 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6627 def : Pat<(f64 (fnearbyint FR64:$src)),
6628 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6629 def : Pat<(f32 (fceil FR32:$src)),
6630 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6631 def : Pat<(f64 (fceil FR64:$src)),
6632 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6633 def : Pat<(f32 (frint FR32:$src)),
6634 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6635 def : Pat<(f64 (frint FR64:$src)),
6636 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6637 def : Pat<(f32 (ftrunc FR32:$src)),
6638 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6639 def : Pat<(f64 (ftrunc FR64:$src)),
6640 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6642 def : Pat<(v4f32 (ffloor VR128:$src)),
6643 (ROUNDPSr VR128:$src, (i32 0x1))>;
6644 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6645 (ROUNDPSr VR128:$src, (i32 0xC))>;
6646 def : Pat<(v4f32 (fceil VR128:$src)),
6647 (ROUNDPSr VR128:$src, (i32 0x2))>;
6648 def : Pat<(v4f32 (frint VR128:$src)),
6649 (ROUNDPSr VR128:$src, (i32 0x4))>;
6650 def : Pat<(v4f32 (ftrunc VR128:$src)),
6651 (ROUNDPSr VR128:$src, (i32 0x3))>;
6653 def : Pat<(v2f64 (ffloor VR128:$src)),
6654 (ROUNDPDr VR128:$src, (i32 0x1))>;
6655 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6656 (ROUNDPDr VR128:$src, (i32 0xC))>;
6657 def : Pat<(v2f64 (fceil VR128:$src)),
6658 (ROUNDPDr VR128:$src, (i32 0x2))>;
6659 def : Pat<(v2f64 (frint VR128:$src)),
6660 (ROUNDPDr VR128:$src, (i32 0x4))>;
6661 def : Pat<(v2f64 (ftrunc VR128:$src)),
6662 (ROUNDPDr VR128:$src, (i32 0x3))>;
6665 //===----------------------------------------------------------------------===//
6666 // SSE4.1 - Packed Bit Test
6667 //===----------------------------------------------------------------------===//
6669 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6670 // the intel intrinsic that corresponds to this.
6671 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6672 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6673 "vptest\t{$src2, $src1|$src1, $src2}",
6674 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6675 Sched<[WriteVecLogic]>, VEX;
6676 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6677 "vptest\t{$src2, $src1|$src1, $src2}",
6678 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6679 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6681 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6682 "vptest\t{$src2, $src1|$src1, $src2}",
6683 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6684 Sched<[WriteVecLogic]>, VEX, VEX_L;
6685 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6686 "vptest\t{$src2, $src1|$src1, $src2}",
6687 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6688 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6691 let Defs = [EFLAGS] in {
6692 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6693 "ptest\t{$src2, $src1|$src1, $src2}",
6694 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6695 Sched<[WriteVecLogic]>;
6696 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6697 "ptest\t{$src2, $src1|$src1, $src2}",
6698 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6699 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6702 // The bit test instructions below are AVX only
6703 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6704 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6705 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6706 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6707 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6708 Sched<[WriteVecLogic]>, VEX;
6709 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6710 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6711 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6712 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6715 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6716 let ExeDomain = SSEPackedSingle in {
6717 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6718 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6721 let ExeDomain = SSEPackedDouble in {
6722 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6723 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6728 //===----------------------------------------------------------------------===//
6729 // SSE4.1 - Misc Instructions
6730 //===----------------------------------------------------------------------===//
6732 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6733 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6734 "popcnt{w}\t{$src, $dst|$dst, $src}",
6735 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6736 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6738 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6739 "popcnt{w}\t{$src, $dst|$dst, $src}",
6740 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6741 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6742 Sched<[WriteFAddLd]>, OpSize16, XS;
6744 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6745 "popcnt{l}\t{$src, $dst|$dst, $src}",
6746 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6747 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6750 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6751 "popcnt{l}\t{$src, $dst|$dst, $src}",
6752 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6753 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6754 Sched<[WriteFAddLd]>, OpSize32, XS;
6756 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6757 "popcnt{q}\t{$src, $dst|$dst, $src}",
6758 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6759 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6760 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6761 "popcnt{q}\t{$src, $dst|$dst, $src}",
6762 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6763 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6764 Sched<[WriteFAddLd]>, XS;
6769 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6770 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6771 Intrinsic IntId128, PatFrag ld_frag,
6772 X86FoldableSchedWrite Sched> {
6773 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6775 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6776 [(set VR128:$dst, (IntId128 VR128:$src))]>,
6778 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6780 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6782 (IntId128 (bitconvert (ld_frag addr:$src))))]>,
6783 Sched<[Sched.Folded]>;
6786 // PHMIN has the same profile as PSAD, thus we use the same scheduling
6787 // model, although the naming is misleading.
6788 let Predicates = [HasAVX] in
6789 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6790 int_x86_sse41_phminposuw, loadv2i64,
6792 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6793 int_x86_sse41_phminposuw, memopv2i64,
6796 /// SS48I_binop_rm - Simple SSE41 binary operator.
6797 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6798 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6799 X86MemOperand x86memop, bit Is2Addr = 1,
6800 OpndItins itins = SSE_INTALU_ITINS_P> {
6801 let isCommutable = 1 in
6802 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6803 (ins RC:$src1, RC:$src2),
6805 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6806 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6807 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6808 Sched<[itins.Sched]>;
6809 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6810 (ins RC:$src1, x86memop:$src2),
6812 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6813 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6815 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
6816 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6819 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
6821 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
6822 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
6823 PatFrag memop_frag, X86MemOperand x86memop,
6825 bit IsCommutable = 0, bit Is2Addr = 1> {
6826 let isCommutable = IsCommutable in
6827 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6828 (ins RC:$src1, RC:$src2),
6830 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6831 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6832 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
6833 Sched<[itins.Sched]>;
6834 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6835 (ins RC:$src1, x86memop:$src2),
6837 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6838 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6839 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
6840 (bitconvert (memop_frag addr:$src2)))))]>,
6841 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6844 let Predicates = [HasAVX, NoVLX] in {
6845 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", smin, v16i8, VR128,
6846 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6848 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", smin, v4i32, VR128,
6849 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6851 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", umin, v4i32, VR128,
6852 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6854 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", umin, v8i16, VR128,
6855 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6857 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v16i8, VR128,
6858 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6860 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v4i32, VR128,
6861 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6863 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", umax, v4i32, VR128,
6864 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6866 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v8i16, VR128,
6867 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6869 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
6870 VR128, loadv2i64, i128mem,
6871 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
6874 let Predicates = [HasAVX2, NoVLX] in {
6875 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", smin, v32i8, VR256,
6876 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6878 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", smin, v8i32, VR256,
6879 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6881 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", umin, v8i32, VR256,
6882 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6884 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", umin, v16i16, VR256,
6885 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6887 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v32i8, VR256,
6888 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6890 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v8i32, VR256,
6891 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6893 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", umax, v8i32, VR256,
6894 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6896 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v16i16, VR256,
6897 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6899 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
6900 VR256, loadv4i64, i256mem,
6901 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
6904 let Constraints = "$src1 = $dst" in {
6905 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", smin, v16i8, VR128,
6906 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6907 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", smin, v4i32, VR128,
6908 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6909 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", umin, v4i32, VR128,
6910 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6911 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", umin, v8i16, VR128,
6912 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6913 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", smax, v16i8, VR128,
6914 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6915 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", smax, v4i32, VR128,
6916 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6917 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", umax, v4i32, VR128,
6918 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6919 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", umax, v8i16, VR128,
6920 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6921 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
6922 VR128, memopv2i64, i128mem,
6923 SSE_INTMUL_ITINS_P, 1>;
6926 let Predicates = [HasAVX, NoVLX] in {
6927 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6928 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
6930 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6931 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6934 let Predicates = [HasAVX2] in {
6935 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6936 loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
6938 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6939 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6943 let Constraints = "$src1 = $dst" in {
6944 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6945 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6946 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6947 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6950 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6951 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6952 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6953 X86MemOperand x86memop, bit Is2Addr = 1,
6954 OpndItins itins = DEFAULT_ITINS> {
6955 let isCommutable = 1 in
6956 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6957 (ins RC:$src1, RC:$src2, u8imm:$src3),
6959 !strconcat(OpcodeStr,
6960 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6961 !strconcat(OpcodeStr,
6962 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6963 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6964 Sched<[itins.Sched]>;
6965 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6966 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6968 !strconcat(OpcodeStr,
6969 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6970 !strconcat(OpcodeStr,
6971 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6974 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6975 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6978 /// SS41I_binop_rmi - SSE 4.1 binary operator with 8-bit immediate
6979 multiclass SS41I_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
6980 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6981 X86MemOperand x86memop, bit Is2Addr = 1,
6982 OpndItins itins = DEFAULT_ITINS> {
6983 let isCommutable = 1 in
6984 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6985 (ins RC:$src1, RC:$src2, u8imm:$src3),
6987 !strconcat(OpcodeStr,
6988 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6989 !strconcat(OpcodeStr,
6990 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6991 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))],
6992 itins.rr>, Sched<[itins.Sched]>;
6993 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6994 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6996 !strconcat(OpcodeStr,
6997 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6998 !strconcat(OpcodeStr,
6999 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7001 (OpVT (OpNode RC:$src1,
7002 (bitconvert (memop_frag addr:$src2)), imm:$src3)))], itins.rm>,
7003 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7006 let Predicates = [HasAVX] in {
7007 let isCommutable = 0 in {
7008 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7009 VR128, loadv2i64, i128mem, 0,
7010 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7013 let ExeDomain = SSEPackedSingle in {
7014 defm VBLENDPS : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v4f32,
7015 VR128, loadv4f32, f128mem, 0,
7016 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7017 defm VBLENDPSY : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v8f32,
7018 VR256, loadv8f32, f256mem, 0,
7019 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7021 let ExeDomain = SSEPackedDouble in {
7022 defm VBLENDPD : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v2f64,
7023 VR128, loadv2f64, f128mem, 0,
7024 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7025 defm VBLENDPDY : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v4f64,
7026 VR256, loadv4f64, f256mem, 0,
7027 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7029 defm VPBLENDW : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v8i16,
7030 VR128, loadv2i64, i128mem, 0,
7031 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7033 let ExeDomain = SSEPackedSingle in
7034 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7035 VR128, loadv4f32, f128mem, 0,
7036 SSE_DPPS_ITINS>, VEX_4V;
7037 let ExeDomain = SSEPackedDouble in
7038 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7039 VR128, loadv2f64, f128mem, 0,
7040 SSE_DPPS_ITINS>, VEX_4V;
7041 let ExeDomain = SSEPackedSingle in
7042 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7043 VR256, loadv8f32, i256mem, 0,
7044 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7047 let Predicates = [HasAVX2] in {
7048 let isCommutable = 0 in {
7049 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7050 VR256, loadv4i64, i256mem, 0,
7051 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7053 defm VPBLENDWY : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v16i16,
7054 VR256, loadv4i64, i256mem, 0,
7055 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7058 let Constraints = "$src1 = $dst" in {
7059 let isCommutable = 0 in {
7060 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7061 VR128, memopv2i64, i128mem,
7062 1, SSE_MPSADBW_ITINS>;
7064 let ExeDomain = SSEPackedSingle in
7065 defm BLENDPS : SS41I_binop_rmi<0x0C, "blendps", X86Blendi, v4f32,
7066 VR128, memopv4f32, f128mem,
7067 1, SSE_INTALU_ITINS_FBLEND_P>;
7068 let ExeDomain = SSEPackedDouble in
7069 defm BLENDPD : SS41I_binop_rmi<0x0D, "blendpd", X86Blendi, v2f64,
7070 VR128, memopv2f64, f128mem,
7071 1, SSE_INTALU_ITINS_FBLEND_P>;
7072 defm PBLENDW : SS41I_binop_rmi<0x0E, "pblendw", X86Blendi, v8i16,
7073 VR128, memopv2i64, i128mem,
7074 1, SSE_INTALU_ITINS_BLEND_P>;
7075 let ExeDomain = SSEPackedSingle in
7076 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7077 VR128, memopv4f32, f128mem, 1,
7079 let ExeDomain = SSEPackedDouble in
7080 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7081 VR128, memopv2f64, f128mem, 1,
7085 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7086 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7087 RegisterClass RC, X86MemOperand x86memop,
7088 PatFrag mem_frag, Intrinsic IntId,
7089 X86FoldableSchedWrite Sched> {
7090 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7091 (ins RC:$src1, RC:$src2, RC:$src3),
7092 !strconcat(OpcodeStr,
7093 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7094 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7095 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7098 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7099 (ins RC:$src1, x86memop:$src2, RC:$src3),
7100 !strconcat(OpcodeStr,
7101 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7103 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7105 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7106 Sched<[Sched.Folded, ReadAfterLd]>;
7109 let Predicates = [HasAVX] in {
7110 let ExeDomain = SSEPackedDouble in {
7111 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7112 loadv2f64, int_x86_sse41_blendvpd,
7114 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7115 loadv4f64, int_x86_avx_blendv_pd_256,
7116 WriteFVarBlend>, VEX_L;
7117 } // ExeDomain = SSEPackedDouble
7118 let ExeDomain = SSEPackedSingle in {
7119 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7120 loadv4f32, int_x86_sse41_blendvps,
7122 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7123 loadv8f32, int_x86_avx_blendv_ps_256,
7124 WriteFVarBlend>, VEX_L;
7125 } // ExeDomain = SSEPackedSingle
7126 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7127 loadv2i64, int_x86_sse41_pblendvb,
7131 let Predicates = [HasAVX2] in {
7132 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7133 loadv4i64, int_x86_avx2_pblendvb,
7134 WriteVarBlend>, VEX_L;
7137 let Predicates = [HasAVX] in {
7138 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7139 (v16i8 VR128:$src2))),
7140 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7141 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7142 (v4i32 VR128:$src2))),
7143 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7144 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7145 (v4f32 VR128:$src2))),
7146 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7147 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7148 (v2i64 VR128:$src2))),
7149 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7150 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7151 (v2f64 VR128:$src2))),
7152 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7153 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7154 (v8i32 VR256:$src2))),
7155 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7156 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7157 (v8f32 VR256:$src2))),
7158 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7159 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7160 (v4i64 VR256:$src2))),
7161 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7162 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7163 (v4f64 VR256:$src2))),
7164 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7167 let Predicates = [HasAVX2] in {
7168 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7169 (v32i8 VR256:$src2))),
7170 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7174 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7175 // on targets where they have equal performance. These were changed to use
7176 // blends because blends have better throughput on SandyBridge and Haswell, but
7177 // movs[s/d] are 1-2 byte shorter instructions.
7178 let Predicates = [UseAVX] in {
7179 let AddedComplexity = 15 in {
7180 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7181 // MOVS{S,D} to the lower bits.
7182 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7183 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7184 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7185 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7186 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7187 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7188 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7189 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7191 // Move low f32 and clear high bits.
7192 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7193 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7195 // Move low f64 and clear high bits.
7196 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7197 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7200 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7201 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7202 (SUBREG_TO_REG (i32 0),
7203 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7205 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7206 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7207 (SUBREG_TO_REG (i64 0),
7208 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7211 // These will incur an FP/int domain crossing penalty, but it may be the only
7212 // way without AVX2. Do not add any complexity because we may be able to match
7213 // more optimal patterns defined earlier in this file.
7214 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7215 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7216 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7217 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7220 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7221 // on targets where they have equal performance. These were changed to use
7222 // blends because blends have better throughput on SandyBridge and Haswell, but
7223 // movs[s/d] are 1-2 byte shorter instructions.
7224 let Predicates = [UseSSE41] in {
7225 // With SSE41 we can use blends for these patterns.
7226 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7227 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7228 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7229 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7230 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7231 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7235 /// SS41I_ternary_int - SSE 4.1 ternary operator
7236 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7237 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7238 X86MemOperand x86memop, Intrinsic IntId,
7239 OpndItins itins = DEFAULT_ITINS> {
7240 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7241 (ins VR128:$src1, VR128:$src2),
7242 !strconcat(OpcodeStr,
7243 "\t{$src2, $dst|$dst, $src2}"),
7244 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7245 itins.rr>, Sched<[itins.Sched]>;
7247 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7248 (ins VR128:$src1, x86memop:$src2),
7249 !strconcat(OpcodeStr,
7250 "\t{$src2, $dst|$dst, $src2}"),
7253 (bitconvert (mem_frag addr:$src2)), XMM0))],
7254 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7258 let ExeDomain = SSEPackedDouble in
7259 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7260 int_x86_sse41_blendvpd,
7261 DEFAULT_ITINS_FBLENDSCHED>;
7262 let ExeDomain = SSEPackedSingle in
7263 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7264 int_x86_sse41_blendvps,
7265 DEFAULT_ITINS_FBLENDSCHED>;
7266 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7267 int_x86_sse41_pblendvb,
7268 DEFAULT_ITINS_VARBLENDSCHED>;
7270 // Aliases with the implicit xmm0 argument
7271 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7272 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7273 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7274 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7275 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7276 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7277 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7278 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7279 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7280 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7281 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7282 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7284 let Predicates = [UseSSE41] in {
7285 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7286 (v16i8 VR128:$src2))),
7287 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7288 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7289 (v4i32 VR128:$src2))),
7290 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7291 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7292 (v4f32 VR128:$src2))),
7293 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7294 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7295 (v2i64 VR128:$src2))),
7296 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7297 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7298 (v2f64 VR128:$src2))),
7299 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7302 let SchedRW = [WriteLoad] in {
7303 let Predicates = [HasAVX] in
7304 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7305 "vmovntdqa\t{$src, $dst|$dst, $src}",
7306 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7308 let Predicates = [HasAVX2] in
7309 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7310 "vmovntdqa\t{$src, $dst|$dst, $src}",
7311 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7313 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7314 "movntdqa\t{$src, $dst|$dst, $src}",
7315 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7318 //===----------------------------------------------------------------------===//
7319 // SSE4.2 - Compare Instructions
7320 //===----------------------------------------------------------------------===//
7322 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7323 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7324 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7325 X86MemOperand x86memop, bit Is2Addr = 1> {
7326 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7327 (ins RC:$src1, RC:$src2),
7329 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7330 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7331 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7332 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7333 (ins RC:$src1, x86memop:$src2),
7335 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7336 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7338 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7341 let Predicates = [HasAVX] in
7342 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7343 loadv2i64, i128mem, 0>, VEX_4V;
7345 let Predicates = [HasAVX2] in
7346 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7347 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7349 let Constraints = "$src1 = $dst" in
7350 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7351 memopv2i64, i128mem>;
7353 //===----------------------------------------------------------------------===//
7354 // SSE4.2 - String/text Processing Instructions
7355 //===----------------------------------------------------------------------===//
7357 // Packed Compare Implicit Length Strings, Return Mask
7358 multiclass pseudo_pcmpistrm<string asm, PatFrag ld_frag> {
7359 def REG : PseudoI<(outs VR128:$dst),
7360 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7361 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7363 def MEM : PseudoI<(outs VR128:$dst),
7364 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7365 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7366 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7369 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7370 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128", loadv2i64>,
7372 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128", memopv2i64>,
7373 Requires<[UseSSE42]>;
7376 multiclass pcmpistrm_SS42AI<string asm> {
7377 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7378 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7379 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7380 []>, Sched<[WritePCmpIStrM]>;
7382 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7383 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7384 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7385 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7388 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7389 let Predicates = [HasAVX] in
7390 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7391 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7394 // Packed Compare Explicit Length Strings, Return Mask
7395 multiclass pseudo_pcmpestrm<string asm, PatFrag ld_frag> {
7396 def REG : PseudoI<(outs VR128:$dst),
7397 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7398 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7399 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7400 def MEM : PseudoI<(outs VR128:$dst),
7401 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7402 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7403 (bc_v16i8 (ld_frag addr:$src3)), EDX, imm:$src5))]>;
7406 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7407 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128", loadv2i64>,
7409 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128", memopv2i64>,
7410 Requires<[UseSSE42]>;
7413 multiclass SS42AI_pcmpestrm<string asm> {
7414 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7415 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7416 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7417 []>, Sched<[WritePCmpEStrM]>;
7419 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7420 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7421 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7422 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7425 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7426 let Predicates = [HasAVX] in
7427 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7428 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7431 // Packed Compare Implicit Length Strings, Return Index
7432 multiclass pseudo_pcmpistri<string asm, PatFrag ld_frag> {
7433 def REG : PseudoI<(outs GR32:$dst),
7434 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7435 [(set GR32:$dst, EFLAGS,
7436 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7437 def MEM : PseudoI<(outs GR32:$dst),
7438 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7439 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7440 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7443 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7444 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI", loadv2i64>,
7446 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI", memopv2i64>,
7447 Requires<[UseSSE42]>;
7450 multiclass SS42AI_pcmpistri<string asm> {
7451 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7452 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7453 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7454 []>, Sched<[WritePCmpIStrI]>;
7456 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7457 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7458 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7459 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7462 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7463 let Predicates = [HasAVX] in
7464 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7465 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7468 // Packed Compare Explicit Length Strings, Return Index
7469 multiclass pseudo_pcmpestri<string asm, PatFrag ld_frag> {
7470 def REG : PseudoI<(outs GR32:$dst),
7471 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7472 [(set GR32:$dst, EFLAGS,
7473 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7474 def MEM : PseudoI<(outs GR32:$dst),
7475 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7476 [(set GR32:$dst, EFLAGS,
7477 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (ld_frag addr:$src3)), EDX,
7481 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7482 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI", loadv2i64>,
7484 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI", memopv2i64>,
7485 Requires<[UseSSE42]>;
7488 multiclass SS42AI_pcmpestri<string asm> {
7489 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7490 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7491 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7492 []>, Sched<[WritePCmpEStrI]>;
7494 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7495 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7496 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7497 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7500 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7501 let Predicates = [HasAVX] in
7502 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7503 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7506 //===----------------------------------------------------------------------===//
7507 // SSE4.2 - CRC Instructions
7508 //===----------------------------------------------------------------------===//
7510 // No CRC instructions have AVX equivalents
7512 // crc intrinsic instruction
7513 // This set of instructions are only rm, the only difference is the size
7515 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7516 RegisterClass RCIn, SDPatternOperator Int> :
7517 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7518 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7519 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7522 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7523 X86MemOperand x86memop, SDPatternOperator Int> :
7524 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7525 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7526 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7527 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7529 let Constraints = "$src1 = $dst" in {
7530 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7531 int_x86_sse42_crc32_32_8>;
7532 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7533 int_x86_sse42_crc32_32_8>;
7534 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7535 int_x86_sse42_crc32_32_16>, OpSize16;
7536 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7537 int_x86_sse42_crc32_32_16>, OpSize16;
7538 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7539 int_x86_sse42_crc32_32_32>, OpSize32;
7540 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7541 int_x86_sse42_crc32_32_32>, OpSize32;
7542 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7543 int_x86_sse42_crc32_64_64>, REX_W;
7544 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7545 int_x86_sse42_crc32_64_64>, REX_W;
7546 let hasSideEffects = 0 in {
7548 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7550 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7555 //===----------------------------------------------------------------------===//
7556 // SHA-NI Instructions
7557 //===----------------------------------------------------------------------===//
7559 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7561 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7562 (ins VR128:$src1, VR128:$src2),
7563 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7565 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7566 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7568 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7569 (ins VR128:$src1, i128mem:$src2),
7570 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7572 (set VR128:$dst, (IntId VR128:$src1,
7573 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7574 (set VR128:$dst, (IntId VR128:$src1,
7575 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7578 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7579 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7580 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7581 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7583 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7584 (i8 imm:$src3)))]>, TA;
7585 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7586 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7587 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7589 (int_x86_sha1rnds4 VR128:$src1,
7590 (bc_v4i32 (memopv2i64 addr:$src2)),
7591 (i8 imm:$src3)))]>, TA;
7593 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7594 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7595 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7598 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7600 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7601 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7604 // Aliases with explicit %xmm0
7605 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7606 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7607 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7608 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7610 //===----------------------------------------------------------------------===//
7611 // AES-NI Instructions
7612 //===----------------------------------------------------------------------===//
7614 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
7615 PatFrag ld_frag, bit Is2Addr = 1> {
7616 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7617 (ins VR128:$src1, VR128:$src2),
7619 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7620 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7621 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7622 Sched<[WriteAESDecEnc]>;
7623 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7624 (ins VR128:$src1, i128mem:$src2),
7626 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7627 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7629 (IntId128 VR128:$src1, (ld_frag addr:$src2)))]>,
7630 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7633 // Perform One Round of an AES Encryption/Decryption Flow
7634 let Predicates = [HasAVX, HasAES] in {
7635 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7636 int_x86_aesni_aesenc, loadv2i64, 0>, VEX_4V;
7637 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7638 int_x86_aesni_aesenclast, loadv2i64, 0>, VEX_4V;
7639 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7640 int_x86_aesni_aesdec, loadv2i64, 0>, VEX_4V;
7641 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7642 int_x86_aesni_aesdeclast, loadv2i64, 0>, VEX_4V;
7645 let Constraints = "$src1 = $dst" in {
7646 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7647 int_x86_aesni_aesenc, memopv2i64>;
7648 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7649 int_x86_aesni_aesenclast, memopv2i64>;
7650 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7651 int_x86_aesni_aesdec, memopv2i64>;
7652 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7653 int_x86_aesni_aesdeclast, memopv2i64>;
7656 // Perform the AES InvMixColumn Transformation
7657 let Predicates = [HasAVX, HasAES] in {
7658 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7660 "vaesimc\t{$src1, $dst|$dst, $src1}",
7662 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7664 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7665 (ins i128mem:$src1),
7666 "vaesimc\t{$src1, $dst|$dst, $src1}",
7667 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7668 Sched<[WriteAESIMCLd]>, VEX;
7670 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7672 "aesimc\t{$src1, $dst|$dst, $src1}",
7674 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7675 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7676 (ins i128mem:$src1),
7677 "aesimc\t{$src1, $dst|$dst, $src1}",
7678 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7679 Sched<[WriteAESIMCLd]>;
7681 // AES Round Key Generation Assist
7682 let Predicates = [HasAVX, HasAES] in {
7683 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7684 (ins VR128:$src1, u8imm:$src2),
7685 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7687 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7688 Sched<[WriteAESKeyGen]>, VEX;
7689 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7690 (ins i128mem:$src1, u8imm:$src2),
7691 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7693 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7694 Sched<[WriteAESKeyGenLd]>, VEX;
7696 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7697 (ins VR128:$src1, u8imm:$src2),
7698 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7700 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7701 Sched<[WriteAESKeyGen]>;
7702 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7703 (ins i128mem:$src1, u8imm:$src2),
7704 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7706 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7707 Sched<[WriteAESKeyGenLd]>;
7709 //===----------------------------------------------------------------------===//
7710 // PCLMUL Instructions
7711 //===----------------------------------------------------------------------===//
7713 // AVX carry-less Multiplication instructions
7714 let isCommutable = 1 in
7715 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7716 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7717 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7719 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7720 Sched<[WriteCLMul]>;
7722 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7723 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7724 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7725 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7726 (loadv2i64 addr:$src2), imm:$src3))]>,
7727 Sched<[WriteCLMulLd, ReadAfterLd]>;
7729 // Carry-less Multiplication instructions
7730 let Constraints = "$src1 = $dst" in {
7731 let isCommutable = 1 in
7732 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7733 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7734 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7736 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7737 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
7739 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7740 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7741 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7742 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7743 (memopv2i64 addr:$src2), imm:$src3))],
7744 IIC_SSE_PCLMULQDQ_RM>,
7745 Sched<[WriteCLMulLd, ReadAfterLd]>;
7746 } // Constraints = "$src1 = $dst"
7749 multiclass pclmul_alias<string asm, int immop> {
7750 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7751 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
7753 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7754 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
7756 def : InstAlias<!strconcat("vpclmul", asm,
7757 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7758 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
7761 def : InstAlias<!strconcat("vpclmul", asm,
7762 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7763 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
7766 defm : pclmul_alias<"hqhq", 0x11>;
7767 defm : pclmul_alias<"hqlq", 0x01>;
7768 defm : pclmul_alias<"lqhq", 0x10>;
7769 defm : pclmul_alias<"lqlq", 0x00>;
7771 //===----------------------------------------------------------------------===//
7772 // SSE4A Instructions
7773 //===----------------------------------------------------------------------===//
7775 let Predicates = [HasSSE4A] in {
7777 let Constraints = "$src = $dst" in {
7778 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
7779 (ins VR128:$src, u8imm:$len, u8imm:$idx),
7780 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7781 [(set VR128:$dst, (X86extrqi VR128:$src, imm:$len,
7783 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7784 (ins VR128:$src, VR128:$mask),
7785 "extrq\t{$mask, $src|$src, $mask}",
7786 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7787 VR128:$mask))]>, PD;
7789 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7790 (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
7791 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7792 [(set VR128:$dst, (X86insertqi VR128:$src, VR128:$src2,
7793 imm:$len, imm:$idx))]>, XD;
7794 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7795 (ins VR128:$src, VR128:$mask),
7796 "insertq\t{$mask, $src|$src, $mask}",
7797 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7798 VR128:$mask))]>, XD;
7801 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7802 "movntss\t{$src, $dst|$dst, $src}",
7803 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7805 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7806 "movntsd\t{$src, $dst|$dst, $src}",
7807 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7810 //===----------------------------------------------------------------------===//
7812 //===----------------------------------------------------------------------===//
7814 //===----------------------------------------------------------------------===//
7815 // VBROADCAST - Load from memory and broadcast to all elements of the
7816 // destination operand
7818 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7819 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
7820 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7821 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7822 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
7824 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
7825 X86MemOperand x86memop, ValueType VT,
7826 PatFrag ld_frag, SchedWrite Sched> :
7827 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7828 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7829 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
7830 Sched<[Sched]>, VEX {
7834 // AVX2 adds register forms
7835 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7836 Intrinsic Int, SchedWrite Sched> :
7837 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7838 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7839 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
7841 let ExeDomain = SSEPackedSingle in {
7842 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
7843 f32mem, v4f32, loadf32, WriteLoad>;
7844 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
7845 f32mem, v8f32, loadf32,
7846 WriteFShuffleLd>, VEX_L;
7848 let ExeDomain = SSEPackedDouble in
7849 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
7850 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
7851 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7852 int_x86_avx_vbroadcastf128_pd_256,
7853 WriteFShuffleLd>, VEX_L;
7855 let ExeDomain = SSEPackedSingle in {
7856 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7857 int_x86_avx2_vbroadcast_ss_ps,
7859 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7860 int_x86_avx2_vbroadcast_ss_ps_256,
7861 WriteFShuffle256>, VEX_L;
7863 let ExeDomain = SSEPackedDouble in
7864 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7865 int_x86_avx2_vbroadcast_sd_pd_256,
7866 WriteFShuffle256>, VEX_L;
7868 let mayLoad = 1, Predicates = [HasAVX2] in
7869 def VBROADCASTI128 : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
7871 "vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
7872 Sched<[WriteLoad]>, VEX, VEX_L;
7874 let Predicates = [HasAVX] in
7875 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7876 (VBROADCASTF128 addr:$src)>;
7879 //===----------------------------------------------------------------------===//
7880 // VINSERTF128 - Insert packed floating-point values
7882 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7883 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7884 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
7885 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7886 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
7888 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7889 (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
7890 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7891 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
7894 let Predicates = [HasAVX] in {
7895 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7897 (VINSERTF128rr VR256:$src1, VR128:$src2,
7898 (INSERT_get_vinsert128_imm VR256:$ins))>;
7899 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7901 (VINSERTF128rr VR256:$src1, VR128:$src2,
7902 (INSERT_get_vinsert128_imm VR256:$ins))>;
7904 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7906 (VINSERTF128rm VR256:$src1, addr:$src2,
7907 (INSERT_get_vinsert128_imm VR256:$ins))>;
7908 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7910 (VINSERTF128rm VR256:$src1, addr:$src2,
7911 (INSERT_get_vinsert128_imm VR256:$ins))>;
7914 let Predicates = [HasAVX1Only] in {
7915 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7917 (VINSERTF128rr VR256:$src1, VR128:$src2,
7918 (INSERT_get_vinsert128_imm VR256:$ins))>;
7919 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7921 (VINSERTF128rr VR256:$src1, VR128:$src2,
7922 (INSERT_get_vinsert128_imm VR256:$ins))>;
7923 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7925 (VINSERTF128rr VR256:$src1, VR128:$src2,
7926 (INSERT_get_vinsert128_imm VR256:$ins))>;
7927 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7929 (VINSERTF128rr VR256:$src1, VR128:$src2,
7930 (INSERT_get_vinsert128_imm VR256:$ins))>;
7932 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7934 (VINSERTF128rm VR256:$src1, addr:$src2,
7935 (INSERT_get_vinsert128_imm VR256:$ins))>;
7936 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7937 (bc_v4i32 (loadv2i64 addr:$src2)),
7939 (VINSERTF128rm VR256:$src1, addr:$src2,
7940 (INSERT_get_vinsert128_imm VR256:$ins))>;
7941 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7942 (bc_v16i8 (loadv2i64 addr:$src2)),
7944 (VINSERTF128rm VR256:$src1, addr:$src2,
7945 (INSERT_get_vinsert128_imm VR256:$ins))>;
7946 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7947 (bc_v8i16 (loadv2i64 addr:$src2)),
7949 (VINSERTF128rm VR256:$src1, addr:$src2,
7950 (INSERT_get_vinsert128_imm VR256:$ins))>;
7953 //===----------------------------------------------------------------------===//
7954 // VEXTRACTF128 - Extract packed floating-point values
7956 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7957 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7958 (ins VR256:$src1, u8imm:$src2),
7959 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7960 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
7962 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7963 (ins f128mem:$dst, VR256:$src1, u8imm:$src2),
7964 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7965 []>, Sched<[WriteStore]>, VEX, VEX_L;
7969 let Predicates = [HasAVX] in {
7970 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7971 (v4f32 (VEXTRACTF128rr
7972 (v8f32 VR256:$src1),
7973 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7974 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7975 (v2f64 (VEXTRACTF128rr
7976 (v4f64 VR256:$src1),
7977 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7979 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7980 (iPTR imm))), addr:$dst),
7981 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7982 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7983 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7984 (iPTR imm))), addr:$dst),
7985 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7986 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7989 let Predicates = [HasAVX1Only] in {
7990 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7991 (v2i64 (VEXTRACTF128rr
7992 (v4i64 VR256:$src1),
7993 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7994 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7995 (v4i32 (VEXTRACTF128rr
7996 (v8i32 VR256:$src1),
7997 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7998 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7999 (v8i16 (VEXTRACTF128rr
8000 (v16i16 VR256:$src1),
8001 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8002 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8003 (v16i8 (VEXTRACTF128rr
8004 (v32i8 VR256:$src1),
8005 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8007 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8008 (iPTR imm))), addr:$dst),
8009 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8010 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8011 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8012 (iPTR imm))), addr:$dst),
8013 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8014 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8015 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8016 (iPTR imm))), addr:$dst),
8017 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8018 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8019 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8020 (iPTR imm))), addr:$dst),
8021 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8022 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8025 //===----------------------------------------------------------------------===//
8026 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8028 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8029 Intrinsic IntLd, Intrinsic IntLd256,
8030 Intrinsic IntSt, Intrinsic IntSt256> {
8031 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8032 (ins VR128:$src1, f128mem:$src2),
8033 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8034 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8036 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8037 (ins VR256:$src1, f256mem:$src2),
8038 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8039 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8041 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8042 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8043 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8044 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8045 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8046 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8047 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8048 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8051 let ExeDomain = SSEPackedSingle in
8052 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8053 int_x86_avx_maskload_ps,
8054 int_x86_avx_maskload_ps_256,
8055 int_x86_avx_maskstore_ps,
8056 int_x86_avx_maskstore_ps_256>;
8057 let ExeDomain = SSEPackedDouble in
8058 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8059 int_x86_avx_maskload_pd,
8060 int_x86_avx_maskload_pd_256,
8061 int_x86_avx_maskstore_pd,
8062 int_x86_avx_maskstore_pd_256>;
8064 //===----------------------------------------------------------------------===//
8065 // VPERMIL - Permute Single and Double Floating-Point Values
8067 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8068 RegisterClass RC, X86MemOperand x86memop_f,
8069 X86MemOperand x86memop_i, PatFrag i_frag,
8070 Intrinsic IntVar, ValueType vt> {
8071 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8072 (ins RC:$src1, RC:$src2),
8073 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8074 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8075 Sched<[WriteFShuffle]>;
8076 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8077 (ins RC:$src1, x86memop_i:$src2),
8078 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8079 [(set RC:$dst, (IntVar RC:$src1,
8080 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8081 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8083 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8084 (ins RC:$src1, u8imm:$src2),
8085 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8086 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8087 Sched<[WriteFShuffle]>;
8088 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8089 (ins x86memop_f:$src1, u8imm:$src2),
8090 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8092 (vt (X86VPermilpi (load addr:$src1), (i8 imm:$src2))))]>, VEX,
8093 Sched<[WriteFShuffleLd]>;
8096 let ExeDomain = SSEPackedSingle in {
8097 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8098 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8099 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8100 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8102 let ExeDomain = SSEPackedDouble in {
8103 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8104 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8105 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8106 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8109 let Predicates = [HasAVX] in {
8110 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8111 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8112 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8113 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8114 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8115 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8116 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8117 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8119 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8120 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8121 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8122 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8123 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8125 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8126 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8127 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8129 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8130 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8131 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8132 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8133 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8134 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8135 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8136 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8138 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8139 (VPERMILPDri VR128:$src1, imm:$imm)>;
8140 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8141 (VPERMILPDmi addr:$src1, imm:$imm)>;
8144 //===----------------------------------------------------------------------===//
8145 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8147 let ExeDomain = SSEPackedSingle in {
8148 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8149 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8150 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8151 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8152 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8153 Sched<[WriteFShuffle]>;
8154 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8155 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8156 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8157 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8158 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8159 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8162 let Predicates = [HasAVX] in {
8163 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8164 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8165 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8166 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8167 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8170 let Predicates = [HasAVX1Only] in {
8171 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8172 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8173 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8174 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8175 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8176 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8177 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8178 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8180 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8181 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8182 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8183 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8184 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8185 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8186 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8187 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8188 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8189 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8190 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8191 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8194 //===----------------------------------------------------------------------===//
8195 // VZERO - Zero YMM registers
8197 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8198 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8199 // Zero All YMM registers
8200 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8201 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8203 // Zero Upper bits of YMM registers
8204 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8205 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8208 //===----------------------------------------------------------------------===//
8209 // Half precision conversion instructions
8210 //===----------------------------------------------------------------------===//
8211 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8212 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8213 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8214 [(set RC:$dst, (Int VR128:$src))]>,
8215 T8PD, VEX, Sched<[WriteCvtF2F]>;
8216 let hasSideEffects = 0, mayLoad = 1 in
8217 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8218 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8219 Sched<[WriteCvtF2FLd]>;
8222 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8223 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8224 (ins RC:$src1, i32u8imm:$src2),
8225 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8226 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8227 TAPD, VEX, Sched<[WriteCvtF2F]>;
8228 let hasSideEffects = 0, mayStore = 1,
8229 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8230 def mr : Ii8<0x1D, MRMDestMem, (outs),
8231 (ins x86memop:$dst, RC:$src1, i32u8imm:$src2),
8232 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8236 let Predicates = [HasF16C] in {
8237 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8238 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8239 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8240 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8242 // Pattern match vcvtph2ps of a scalar i64 load.
8243 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8244 (VCVTPH2PSrm addr:$src)>;
8245 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8246 (VCVTPH2PSrm addr:$src)>;
8248 def : Pat<(store (f64 (vector_extract (bc_v2f64 (v8i16
8249 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8251 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8252 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v8i16
8253 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8255 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8256 def : Pat<(store (v8i16 (int_x86_vcvtps2ph_256 VR256:$src1, i32:$src2)),
8258 (VCVTPS2PHYmr addr:$dst, VR256:$src1, imm:$src2)>;
8261 // Patterns for matching conversions from float to half-float and vice versa.
8262 let Predicates = [HasF16C] in {
8263 def : Pat<(fp_to_f16 FR32:$src),
8264 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8265 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8267 def : Pat<(f16_to_fp GR16:$src),
8268 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8269 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8271 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8272 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8273 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8276 //===----------------------------------------------------------------------===//
8277 // AVX2 Instructions
8278 //===----------------------------------------------------------------------===//
8280 /// AVX2_binop_rmi - AVX2 binary operator with 8-bit immediate
8281 multiclass AVX2_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
8282 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
8283 X86MemOperand x86memop> {
8284 let isCommutable = 1 in
8285 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8286 (ins RC:$src1, RC:$src2, u8imm:$src3),
8287 !strconcat(OpcodeStr,
8288 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8289 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))]>,
8290 Sched<[WriteBlend]>, VEX_4V;
8291 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8292 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
8293 !strconcat(OpcodeStr,
8294 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8296 (OpVT (OpNode RC:$src1,
8297 (bitconvert (memop_frag addr:$src2)), imm:$src3)))]>,
8298 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8301 defm VPBLENDD : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v4i32,
8302 VR128, loadv2i64, i128mem>;
8303 defm VPBLENDDY : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v8i32,
8304 VR256, loadv4i64, i256mem>, VEX_L;
8306 //===----------------------------------------------------------------------===//
8307 // VPBROADCAST - Load from memory and broadcast to all elements of the
8308 // destination operand
8310 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8311 X86MemOperand x86memop, PatFrag ld_frag,
8312 Intrinsic Int128, Intrinsic Int256> {
8313 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8314 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8315 [(set VR128:$dst, (Int128 VR128:$src))]>,
8316 Sched<[WriteShuffle]>, VEX;
8317 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8318 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8320 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8321 Sched<[WriteLoad]>, VEX;
8322 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8323 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8324 [(set VR256:$dst, (Int256 VR128:$src))]>,
8325 Sched<[WriteShuffle256]>, VEX, VEX_L;
8326 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8327 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8329 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8330 Sched<[WriteLoad]>, VEX, VEX_L;
8333 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8334 int_x86_avx2_pbroadcastb_128,
8335 int_x86_avx2_pbroadcastb_256>;
8336 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8337 int_x86_avx2_pbroadcastw_128,
8338 int_x86_avx2_pbroadcastw_256>;
8339 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8340 int_x86_avx2_pbroadcastd_128,
8341 int_x86_avx2_pbroadcastd_256>;
8342 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8343 int_x86_avx2_pbroadcastq_128,
8344 int_x86_avx2_pbroadcastq_256>;
8346 let Predicates = [HasAVX2] in {
8347 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8348 (VPBROADCASTBrm addr:$src)>;
8349 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8350 (VPBROADCASTBYrm addr:$src)>;
8351 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8352 (VPBROADCASTWrm addr:$src)>;
8353 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8354 (VPBROADCASTWYrm addr:$src)>;
8355 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8356 (VPBROADCASTDrm addr:$src)>;
8357 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8358 (VPBROADCASTDYrm addr:$src)>;
8359 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8360 (VPBROADCASTQrm addr:$src)>;
8361 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8362 (VPBROADCASTQYrm addr:$src)>;
8364 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8365 (VPBROADCASTBrr VR128:$src)>;
8366 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8367 (VPBROADCASTBYrr VR128:$src)>;
8368 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8369 (VPBROADCASTWrr VR128:$src)>;
8370 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8371 (VPBROADCASTWYrr VR128:$src)>;
8372 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8373 (VPBROADCASTDrr VR128:$src)>;
8374 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8375 (VPBROADCASTDYrr VR128:$src)>;
8376 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8377 (VPBROADCASTQrr VR128:$src)>;
8378 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8379 (VPBROADCASTQYrr VR128:$src)>;
8380 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8381 (VBROADCASTSSrr VR128:$src)>;
8382 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8383 (VBROADCASTSSYrr VR128:$src)>;
8384 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8385 (VPBROADCASTQrr VR128:$src)>;
8386 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8387 (VBROADCASTSDYrr VR128:$src)>;
8389 // Provide aliases for broadcast from the same register class that
8390 // automatically does the extract.
8391 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8392 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8394 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8395 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8397 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8398 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8400 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8401 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8403 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8404 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8406 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8407 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8410 // Provide fallback in case the load node that is used in the patterns above
8411 // is used by additional users, which prevents the pattern selection.
8412 let AddedComplexity = 20 in {
8413 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8414 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8415 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8416 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8417 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8418 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8420 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8421 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8422 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8423 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8424 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8425 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8427 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8428 (VPBROADCASTBrr (COPY_TO_REGCLASS
8429 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8431 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8432 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8433 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8436 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8437 (VPBROADCASTWrr (COPY_TO_REGCLASS
8438 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8440 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8441 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8442 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8445 // The patterns for VPBROADCASTD are not needed because they would match
8446 // the exact same thing as VBROADCASTSS patterns.
8448 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8449 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8450 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8454 // AVX1 broadcast patterns
8455 let Predicates = [HasAVX1Only] in {
8456 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8457 (VBROADCASTSSYrm addr:$src)>;
8458 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8459 (VBROADCASTSDYrm addr:$src)>;
8460 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8461 (VBROADCASTSSrm addr:$src)>;
8464 let Predicates = [HasAVX] in {
8465 // Provide fallback in case the load node that is used in the patterns above
8466 // is used by additional users, which prevents the pattern selection.
8467 let AddedComplexity = 20 in {
8468 // 128bit broadcasts:
8469 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8470 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8471 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8472 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8473 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8474 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8475 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8476 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8477 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8478 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8480 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8481 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8482 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8483 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8484 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8485 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8486 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8487 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8488 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8489 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8492 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8493 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8494 def : Pat<(v2i64 (X86VBroadcast i64:$src)),
8495 (VMOVDDUPrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8498 //===----------------------------------------------------------------------===//
8499 // VPERM - Permute instructions
8502 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8503 ValueType OpVT, X86FoldableSchedWrite Sched> {
8504 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8505 (ins VR256:$src1, VR256:$src2),
8506 !strconcat(OpcodeStr,
8507 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8509 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8510 Sched<[Sched]>, VEX_4V, VEX_L;
8511 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8512 (ins VR256:$src1, i256mem:$src2),
8513 !strconcat(OpcodeStr,
8514 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8516 (OpVT (X86VPermv VR256:$src1,
8517 (bitconvert (mem_frag addr:$src2)))))]>,
8518 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8521 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8522 let ExeDomain = SSEPackedSingle in
8523 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8525 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8526 ValueType OpVT, X86FoldableSchedWrite Sched> {
8527 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8528 (ins VR256:$src1, u8imm:$src2),
8529 !strconcat(OpcodeStr,
8530 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8532 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8533 Sched<[Sched]>, VEX, VEX_L;
8534 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8535 (ins i256mem:$src1, u8imm:$src2),
8536 !strconcat(OpcodeStr,
8537 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8539 (OpVT (X86VPermi (mem_frag addr:$src1),
8540 (i8 imm:$src2))))]>,
8541 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8544 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8545 WriteShuffle256>, VEX_W;
8546 let ExeDomain = SSEPackedDouble in
8547 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8548 WriteFShuffle256>, VEX_W;
8550 //===----------------------------------------------------------------------===//
8551 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8553 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8554 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8555 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8556 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8557 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8559 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8560 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8561 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8562 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8564 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8566 let Predicates = [HasAVX2] in {
8567 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8568 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8569 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8570 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8571 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8572 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8574 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8576 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8577 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8578 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8579 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8580 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8582 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8586 //===----------------------------------------------------------------------===//
8587 // VINSERTI128 - Insert packed integer values
8589 let hasSideEffects = 0 in {
8590 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8591 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8592 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8593 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8595 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8596 (ins VR256:$src1, i128mem:$src2, u8imm:$src3),
8597 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8598 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8601 let Predicates = [HasAVX2] in {
8602 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8604 (VINSERTI128rr VR256:$src1, VR128:$src2,
8605 (INSERT_get_vinsert128_imm VR256:$ins))>;
8606 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8608 (VINSERTI128rr VR256:$src1, VR128:$src2,
8609 (INSERT_get_vinsert128_imm VR256:$ins))>;
8610 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8612 (VINSERTI128rr VR256:$src1, VR128:$src2,
8613 (INSERT_get_vinsert128_imm VR256:$ins))>;
8614 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8616 (VINSERTI128rr VR256:$src1, VR128:$src2,
8617 (INSERT_get_vinsert128_imm VR256:$ins))>;
8619 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8621 (VINSERTI128rm VR256:$src1, addr:$src2,
8622 (INSERT_get_vinsert128_imm VR256:$ins))>;
8623 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8624 (bc_v4i32 (loadv2i64 addr:$src2)),
8626 (VINSERTI128rm VR256:$src1, addr:$src2,
8627 (INSERT_get_vinsert128_imm VR256:$ins))>;
8628 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8629 (bc_v16i8 (loadv2i64 addr:$src2)),
8631 (VINSERTI128rm VR256:$src1, addr:$src2,
8632 (INSERT_get_vinsert128_imm VR256:$ins))>;
8633 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8634 (bc_v8i16 (loadv2i64 addr:$src2)),
8636 (VINSERTI128rm VR256:$src1, addr:$src2,
8637 (INSERT_get_vinsert128_imm VR256:$ins))>;
8640 //===----------------------------------------------------------------------===//
8641 // VEXTRACTI128 - Extract packed integer values
8643 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8644 (ins VR256:$src1, u8imm:$src2),
8645 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8646 Sched<[WriteShuffle256]>, VEX, VEX_L;
8647 let hasSideEffects = 0, mayStore = 1 in
8648 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8649 (ins i128mem:$dst, VR256:$src1, u8imm:$src2),
8650 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8651 Sched<[WriteStore]>, VEX, VEX_L;
8653 let Predicates = [HasAVX2] in {
8654 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8655 (v2i64 (VEXTRACTI128rr
8656 (v4i64 VR256:$src1),
8657 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8658 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8659 (v4i32 (VEXTRACTI128rr
8660 (v8i32 VR256:$src1),
8661 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8662 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8663 (v8i16 (VEXTRACTI128rr
8664 (v16i16 VR256:$src1),
8665 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8666 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8667 (v16i8 (VEXTRACTI128rr
8668 (v32i8 VR256:$src1),
8669 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8671 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8672 (iPTR imm))), addr:$dst),
8673 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8674 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8675 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8676 (iPTR imm))), addr:$dst),
8677 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8678 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8679 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8680 (iPTR imm))), addr:$dst),
8681 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8682 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8683 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8684 (iPTR imm))), addr:$dst),
8685 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8686 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8689 //===----------------------------------------------------------------------===//
8690 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8692 multiclass avx2_pmovmask<string OpcodeStr,
8693 Intrinsic IntLd128, Intrinsic IntLd256,
8694 Intrinsic IntSt128, Intrinsic IntSt256> {
8695 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8696 (ins VR128:$src1, i128mem:$src2),
8697 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8698 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8699 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8700 (ins VR256:$src1, i256mem:$src2),
8701 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8702 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8704 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8705 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8706 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8707 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8708 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8709 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8710 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8711 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8714 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8715 int_x86_avx2_maskload_d,
8716 int_x86_avx2_maskload_d_256,
8717 int_x86_avx2_maskstore_d,
8718 int_x86_avx2_maskstore_d_256>;
8719 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8720 int_x86_avx2_maskload_q,
8721 int_x86_avx2_maskload_q_256,
8722 int_x86_avx2_maskstore_q,
8723 int_x86_avx2_maskstore_q_256>, VEX_W;
8725 def: Pat<(X86mstore addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8726 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8728 def: Pat<(X86mstore addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8729 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8731 def: Pat<(X86mstore addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8732 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
8734 def: Pat<(X86mstore addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
8735 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8737 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8738 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8740 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
8741 (bc_v8f32 (v8i32 immAllZerosV)))),
8742 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8744 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
8745 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
8748 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8749 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8751 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
8752 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8754 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
8755 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
8758 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8759 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8761 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
8762 (bc_v4f32 (v4i32 immAllZerosV)))),
8763 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8765 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
8766 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
8769 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8770 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8772 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
8773 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8775 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
8776 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
8779 def: Pat<(X86mstore addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
8780 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8782 def: Pat<(X86mstore addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
8783 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8785 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8786 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8788 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8789 (v4f64 immAllZerosV))),
8790 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8792 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
8793 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
8796 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8797 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8799 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8800 (bc_v4i64 (v8i32 immAllZerosV)))),
8801 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8803 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
8804 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
8807 def: Pat<(X86mstore addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
8808 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8810 def: Pat<(X86mstore addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
8811 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
8813 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8814 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8816 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8817 (v2f64 immAllZerosV))),
8818 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8820 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
8821 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
8824 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8825 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8827 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8828 (bc_v2i64 (v4i32 immAllZerosV)))),
8829 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8831 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
8832 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
8835 //===----------------------------------------------------------------------===//
8836 // Variable Bit Shifts
8838 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8839 ValueType vt128, ValueType vt256> {
8840 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8841 (ins VR128:$src1, VR128:$src2),
8842 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8844 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8845 VEX_4V, Sched<[WriteVarVecShift]>;
8846 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8847 (ins VR128:$src1, i128mem:$src2),
8848 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8850 (vt128 (OpNode VR128:$src1,
8851 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8852 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8853 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8854 (ins VR256:$src1, VR256:$src2),
8855 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8857 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8858 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
8859 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8860 (ins VR256:$src1, i256mem:$src2),
8861 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8863 (vt256 (OpNode VR256:$src1,
8864 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8865 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8868 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8869 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8870 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8871 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8872 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8874 //===----------------------------------------------------------------------===//
8875 // VGATHER - GATHER Operations
8876 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8877 X86MemOperand memop128, X86MemOperand memop256> {
8878 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8879 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8880 !strconcat(OpcodeStr,
8881 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8883 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8884 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8885 !strconcat(OpcodeStr,
8886 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8887 []>, VEX_4VOp3, VEX_L;
8890 let mayLoad = 1, Constraints
8891 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8893 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8894 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8895 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8896 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
8898 let ExeDomain = SSEPackedDouble in {
8899 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8900 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8903 let ExeDomain = SSEPackedSingle in {
8904 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8905 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;