1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE scalar FP Instructions
19 //===----------------------------------------------------------------------===//
21 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
22 // instruction selection into a branch sequence.
23 let Uses = [EFLAGS], usesCustomInserter = 1 in {
24 def CMOV_FR32 : I<0, Pseudo,
25 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
27 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
29 def CMOV_FR64 : I<0, Pseudo,
30 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
32 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
34 def CMOV_V4F32 : I<0, Pseudo,
35 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
36 "#CMOV_V4F32 PSEUDO!",
38 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
40 def CMOV_V2F64 : I<0, Pseudo,
41 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
42 "#CMOV_V2F64 PSEUDO!",
44 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
46 def CMOV_V2I64 : I<0, Pseudo,
47 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
48 "#CMOV_V2I64 PSEUDO!",
50 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
54 //===----------------------------------------------------------------------===//
55 // SSE 1 & 2 Instructions Classes
56 //===----------------------------------------------------------------------===//
58 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
59 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
60 RegisterClass RC, X86MemOperand x86memop,
62 let isCommutable = 1 in {
63 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
65 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
66 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
67 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
69 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
71 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
72 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
73 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
76 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
77 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
78 string asm, string SSEVer, string FPSizeStr,
79 Operand memopr, ComplexPattern mem_cpat,
81 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
83 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
84 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
85 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
86 !strconcat(SSEVer, !strconcat("_",
87 !strconcat(OpcodeStr, FPSizeStr))))
88 RC:$src1, RC:$src2))]>;
89 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
91 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
92 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
93 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
94 !strconcat(SSEVer, !strconcat("_",
95 !strconcat(OpcodeStr, FPSizeStr))))
96 RC:$src1, mem_cpat:$src2))]>;
99 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
100 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
101 RegisterClass RC, ValueType vt,
102 X86MemOperand x86memop, PatFrag mem_frag,
103 Domain d, bit Is2Addr = 1> {
104 let isCommutable = 1 in
105 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
108 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
109 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
111 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
113 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
114 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
115 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
118 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
119 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
120 string OpcodeStr, X86MemOperand x86memop,
121 list<dag> pat_rr, list<dag> pat_rm,
123 let isCommutable = 1 in
124 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
126 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
127 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
129 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
131 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
132 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
136 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
137 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
138 string asm, string SSEVer, string FPSizeStr,
139 X86MemOperand x86memop, PatFrag mem_frag,
140 Domain d, bit Is2Addr = 1> {
141 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
143 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
144 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
145 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_",
146 !strconcat(SSEVer, !strconcat("_",
147 !strconcat(OpcodeStr, FPSizeStr))))
148 RC:$src1, RC:$src2))], d>;
149 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
151 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
152 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
153 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_",
154 !strconcat(SSEVer, !strconcat("_",
155 !strconcat(OpcodeStr, FPSizeStr))))
156 RC:$src1, (mem_frag addr:$src2)))], d>;
159 //===----------------------------------------------------------------------===//
160 // SSE 1 & 2 - Move Instructions
161 //===----------------------------------------------------------------------===//
163 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
164 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
165 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
167 // Loading from memory automatically zeroing upper bits.
168 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
169 PatFrag mem_pat, string OpcodeStr> :
170 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
171 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
172 [(set RC:$dst, (mem_pat addr:$src))]>;
174 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
175 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
176 // is used instead. Register-to-register movss/movsd is not modeled as an
177 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
178 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
179 let isAsmParserOnly = 1 in {
180 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
181 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
182 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
183 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
185 let canFoldAsLoad = 1, isReMaterializable = 1 in {
186 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
188 let AddedComplexity = 20 in
189 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
193 let Constraints = "$src1 = $dst" in {
194 def MOVSSrr : sse12_move_rr<FR32, v4f32,
195 "movss\t{$src2, $dst|$dst, $src2}">, XS;
196 def MOVSDrr : sse12_move_rr<FR64, v2f64,
197 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
200 let canFoldAsLoad = 1, isReMaterializable = 1 in {
201 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
203 let AddedComplexity = 20 in
204 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
207 let AddedComplexity = 15 in {
208 // Extract the low 32-bit value from one vector and insert it into another.
209 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
210 (MOVSSrr (v4f32 VR128:$src1),
211 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
212 // Extract the low 64-bit value from one vector and insert it into another.
213 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
214 (MOVSDrr (v2f64 VR128:$src1),
215 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
218 // Implicitly promote a 32-bit scalar to a vector.
219 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
220 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
221 // Implicitly promote a 64-bit scalar to a vector.
222 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
223 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
225 let AddedComplexity = 20 in {
226 // MOVSSrm zeros the high parts of the register; represent this
227 // with SUBREG_TO_REG.
228 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
229 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
230 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
231 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
232 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
233 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
234 // MOVSDrm zeros the high parts of the register; represent this
235 // with SUBREG_TO_REG.
236 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
237 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
238 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
239 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
240 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
241 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
242 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
243 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
244 def : Pat<(v2f64 (X86vzload addr:$src)),
245 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
248 // Store scalar value to memory.
249 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
250 "movss\t{$src, $dst|$dst, $src}",
251 [(store FR32:$src, addr:$dst)]>;
252 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
253 "movsd\t{$src, $dst|$dst, $src}",
254 [(store FR64:$src, addr:$dst)]>;
256 let isAsmParserOnly = 1 in {
257 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
258 "movss\t{$src, $dst|$dst, $src}",
259 [(store FR32:$src, addr:$dst)]>, XS, VEX;
260 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
261 "movsd\t{$src, $dst|$dst, $src}",
262 [(store FR64:$src, addr:$dst)]>, XD, VEX;
265 // Extract and store.
266 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
269 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
270 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
273 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
275 // Move Aligned/Unaligned floating point values
276 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
277 X86MemOperand x86memop, PatFrag ld_frag,
278 string asm, Domain d,
279 bit IsReMaterializable = 1> {
280 let neverHasSideEffects = 1 in
281 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
282 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
283 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
284 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
285 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
286 [(set RC:$dst, (ld_frag addr:$src))], d>;
289 let isAsmParserOnly = 1 in {
290 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
291 "movaps", SSEPackedSingle>, VEX;
292 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
293 "movapd", SSEPackedDouble>, OpSize, VEX;
294 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
295 "movups", SSEPackedSingle>, VEX;
296 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
297 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
299 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
300 "movaps", SSEPackedSingle>, VEX;
301 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
302 "movapd", SSEPackedDouble>, OpSize, VEX;
303 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
304 "movups", SSEPackedSingle>, VEX;
305 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
306 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
308 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
309 "movaps", SSEPackedSingle>, TB;
310 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
311 "movapd", SSEPackedDouble>, TB, OpSize;
312 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
313 "movups", SSEPackedSingle>, TB;
314 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
315 "movupd", SSEPackedDouble, 0>, TB, OpSize;
317 let isAsmParserOnly = 1 in {
318 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
319 "movaps\t{$src, $dst|$dst, $src}",
320 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
321 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
322 "movapd\t{$src, $dst|$dst, $src}",
323 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
324 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
325 "movups\t{$src, $dst|$dst, $src}",
326 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
327 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
328 "movupd\t{$src, $dst|$dst, $src}",
329 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
330 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
331 "movaps\t{$src, $dst|$dst, $src}",
332 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
333 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
334 "movapd\t{$src, $dst|$dst, $src}",
335 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
336 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
337 "movups\t{$src, $dst|$dst, $src}",
338 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
339 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
340 "movupd\t{$src, $dst|$dst, $src}",
341 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
344 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
345 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
346 (VMOVUPSYmr addr:$dst, VR256:$src)>;
348 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
349 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
350 (VMOVUPDYmr addr:$dst, VR256:$src)>;
352 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
353 "movaps\t{$src, $dst|$dst, $src}",
354 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
355 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
356 "movapd\t{$src, $dst|$dst, $src}",
357 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
358 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
359 "movups\t{$src, $dst|$dst, $src}",
360 [(store (v4f32 VR128:$src), addr:$dst)]>;
361 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
362 "movupd\t{$src, $dst|$dst, $src}",
363 [(store (v2f64 VR128:$src), addr:$dst)]>;
365 // Intrinsic forms of MOVUPS/D load and store
366 let isAsmParserOnly = 1 in {
367 let canFoldAsLoad = 1, isReMaterializable = 1 in
368 def VMOVUPSrm_Int : VPSI<0x10, MRMSrcMem, (outs VR128:$dst),
370 "movups\t{$src, $dst|$dst, $src}",
371 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>, VEX;
372 def VMOVUPDrm_Int : VPDI<0x10, MRMSrcMem, (outs VR128:$dst),
374 "movupd\t{$src, $dst|$dst, $src}",
375 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>, VEX;
376 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
377 (ins f128mem:$dst, VR128:$src),
378 "movups\t{$src, $dst|$dst, $src}",
379 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
380 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
381 (ins f128mem:$dst, VR128:$src),
382 "movupd\t{$src, $dst|$dst, $src}",
383 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
385 let canFoldAsLoad = 1, isReMaterializable = 1 in
386 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
387 "movups\t{$src, $dst|$dst, $src}",
388 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
389 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
390 "movupd\t{$src, $dst|$dst, $src}",
391 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
393 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
394 "movups\t{$src, $dst|$dst, $src}",
395 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
396 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
397 "movupd\t{$src, $dst|$dst, $src}",
398 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
400 // Move Low/High packed floating point values
401 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
402 PatFrag mov_frag, string base_opc,
404 def PSrm : PI<opc, MRMSrcMem,
405 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
406 !strconcat(!strconcat(base_opc,"s"), asm_opr),
409 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
410 SSEPackedSingle>, TB;
412 def PDrm : PI<opc, MRMSrcMem,
413 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
414 !strconcat(!strconcat(base_opc,"d"), asm_opr),
415 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
416 (scalar_to_vector (loadf64 addr:$src2)))))],
417 SSEPackedDouble>, TB, OpSize;
420 let isAsmParserOnly = 1, AddedComplexity = 20 in {
421 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
422 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
423 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
424 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
426 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
427 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
428 "\t{$src2, $dst|$dst, $src2}">;
429 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
430 "\t{$src2, $dst|$dst, $src2}">;
433 let isAsmParserOnly = 1 in {
434 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
435 "movlps\t{$src, $dst|$dst, $src}",
436 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
437 (iPTR 0))), addr:$dst)]>, VEX;
438 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
439 "movlpd\t{$src, $dst|$dst, $src}",
440 [(store (f64 (vector_extract (v2f64 VR128:$src),
441 (iPTR 0))), addr:$dst)]>, VEX;
443 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
444 "movlps\t{$src, $dst|$dst, $src}",
445 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
446 (iPTR 0))), addr:$dst)]>;
447 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
448 "movlpd\t{$src, $dst|$dst, $src}",
449 [(store (f64 (vector_extract (v2f64 VR128:$src),
450 (iPTR 0))), addr:$dst)]>;
452 // v2f64 extract element 1 is always custom lowered to unpack high to low
453 // and extract element 0 so the non-store version isn't too horrible.
454 let isAsmParserOnly = 1 in {
455 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
456 "movhps\t{$src, $dst|$dst, $src}",
457 [(store (f64 (vector_extract
458 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
459 (undef)), (iPTR 0))), addr:$dst)]>,
461 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
462 "movhpd\t{$src, $dst|$dst, $src}",
463 [(store (f64 (vector_extract
464 (v2f64 (unpckh VR128:$src, (undef))),
465 (iPTR 0))), addr:$dst)]>,
468 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
469 "movhps\t{$src, $dst|$dst, $src}",
470 [(store (f64 (vector_extract
471 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
472 (undef)), (iPTR 0))), addr:$dst)]>;
473 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
474 "movhpd\t{$src, $dst|$dst, $src}",
475 [(store (f64 (vector_extract
476 (v2f64 (unpckh VR128:$src, (undef))),
477 (iPTR 0))), addr:$dst)]>;
479 let isAsmParserOnly = 1, AddedComplexity = 20 in {
480 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
481 (ins VR128:$src1, VR128:$src2),
482 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
484 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
486 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
487 (ins VR128:$src1, VR128:$src2),
488 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
490 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
493 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
494 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
495 (ins VR128:$src1, VR128:$src2),
496 "movlhps\t{$src2, $dst|$dst, $src2}",
498 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
499 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
500 (ins VR128:$src1, VR128:$src2),
501 "movhlps\t{$src2, $dst|$dst, $src2}",
503 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
506 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
507 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
508 let AddedComplexity = 20 in {
509 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
510 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
511 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
512 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
515 //===----------------------------------------------------------------------===//
516 // SSE 1 & 2 - Conversion Instructions
517 //===----------------------------------------------------------------------===//
519 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
520 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
522 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
523 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
524 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
525 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
528 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
529 X86MemOperand x86memop, string asm> {
530 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
532 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
536 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
537 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
538 string asm, Domain d> {
539 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
540 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
541 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
542 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
545 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
546 X86MemOperand x86memop, string asm> {
547 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
548 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
549 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
550 (ins DstRC:$src1, x86memop:$src),
551 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
554 let isAsmParserOnly = 1 in {
555 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
556 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
557 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
558 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
560 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
561 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
562 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
563 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
566 // The assembler can recognize rr 64-bit instructions by seeing a rxx
567 // register, but the same isn't true when only using memory operands,
568 // provide other assembly "l" and "q" forms to address this explicitly
569 // where appropriate to do so.
570 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
572 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
574 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
576 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
578 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
582 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
583 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
584 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
585 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
586 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
587 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
588 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
589 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
590 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
591 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
592 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
593 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
594 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
595 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
596 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
597 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
599 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
600 // and/or XMM operand(s).
601 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
602 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
603 string asm, Domain d> {
604 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
605 [(set DstRC:$dst, (Int SrcRC:$src))], d>;
606 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
607 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
610 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
611 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
613 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
614 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
615 [(set DstRC:$dst, (Int SrcRC:$src))]>;
616 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
617 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
618 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
621 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
622 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
623 PatFrag ld_frag, string asm, Domain d> {
624 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
625 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
626 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
627 (ins DstRC:$src1, x86memop:$src2), asm,
628 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>;
631 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
632 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
633 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
634 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
636 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
637 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
638 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
639 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
640 (ins DstRC:$src1, x86memop:$src2),
642 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
643 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
644 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
647 let isAsmParserOnly = 1 in {
648 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
649 f32mem, load, "cvtss2si">, XS, VEX;
650 defm Int_VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
651 int_x86_sse_cvtss2si64, f32mem, load, "cvtss2si">,
653 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
654 f128mem, load, "cvtsd2si">, XD, VEX;
655 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
656 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
659 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
660 // Get rid of this hack or rename the intrinsics, there are several
661 // intructions that only match with the intrinsic form, why create duplicates
662 // to let them be recognized by the assembler?
663 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
664 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
665 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
666 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
668 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
669 f32mem, load, "cvtss2si">, XS;
670 defm Int_CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
671 f32mem, load, "cvtss2si{q}">, XS, REX_W;
672 defm Int_CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
673 f128mem, load, "cvtsd2si">, XD;
674 defm Int_CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
675 f128mem, load, "cvtsd2si">, XD, REX_W;
677 defm CVTSD2SI64 : sse12_cvt_s_np<0x2D, VR128, GR64, f64mem, "cvtsd2si{q}">, XD,
680 let isAsmParserOnly = 1 in {
681 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
682 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
683 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
684 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
686 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
687 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
688 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
689 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
693 let Constraints = "$src1 = $dst" in {
694 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
695 int_x86_sse_cvtsi2ss, i32mem, loadi32,
697 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
698 int_x86_sse_cvtsi642ss, i64mem, loadi64,
699 "cvtsi2ss{q}">, XS, REX_W;
700 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
701 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
703 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
704 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
705 "cvtsi2sd">, XD, REX_W;
708 // Instructions below don't have an AVX form.
709 defm Int_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
710 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
711 SSEPackedSingle>, TB;
712 defm Int_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
713 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
714 SSEPackedDouble>, TB, OpSize;
715 defm Int_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
716 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
717 SSEPackedSingle>, TB;
718 defm Int_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
719 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
720 SSEPackedDouble>, TB, OpSize;
721 defm Int_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
722 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
723 SSEPackedDouble>, TB, OpSize;
724 let Constraints = "$src1 = $dst" in {
725 defm Int_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
726 int_x86_sse_cvtpi2ps,
727 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
728 SSEPackedSingle>, TB;
733 // Aliases for intrinsics
734 let isAsmParserOnly = 1 in {
735 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
736 f32mem, load, "cvttss2si">, XS, VEX;
737 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
738 int_x86_sse_cvttss2si64, f32mem, load,
739 "cvttss2si">, XS, VEX, VEX_W;
740 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
741 f128mem, load, "cvttss2si">, XD, VEX;
742 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
743 int_x86_sse2_cvttsd2si64, f128mem, load,
744 "cvttss2si">, XD, VEX, VEX_W;
746 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
747 f32mem, load, "cvttss2si">, XS;
748 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
749 int_x86_sse_cvttss2si64, f32mem, load,
750 "cvttss2si{q}">, XS, REX_W;
751 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
752 f128mem, load, "cvttss2si">, XD;
753 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
754 int_x86_sse2_cvttsd2si64, f128mem, load,
755 "cvttss2si{q}">, XD, REX_W;
757 let isAsmParserOnly = 1, Pattern = []<dag> in {
758 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
759 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
760 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
761 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
763 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
764 "cvtdq2ps\t{$src, $dst|$dst, $src}",
765 SSEPackedSingle>, TB, VEX;
766 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
767 "cvtdq2ps\t{$src, $dst|$dst, $src}",
768 SSEPackedSingle>, TB, VEX;
770 let Pattern = []<dag> in {
771 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
772 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
773 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
774 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
775 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
776 "cvtdq2ps\t{$src, $dst|$dst, $src}",
777 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
782 // Convert scalar double to scalar single
783 let isAsmParserOnly = 1 in {
784 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
785 (ins FR64:$src1, FR64:$src2),
786 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
788 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
789 (ins FR64:$src1, f64mem:$src2),
790 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
791 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
793 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
794 "cvtsd2ss\t{$src, $dst|$dst, $src}",
795 [(set FR32:$dst, (fround FR64:$src))]>;
796 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
797 "cvtsd2ss\t{$src, $dst|$dst, $src}",
798 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
799 Requires<[HasSSE2, OptForSize]>;
801 let isAsmParserOnly = 1 in
802 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
803 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
805 let Constraints = "$src1 = $dst" in
806 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
807 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
809 // Convert scalar single to scalar double
810 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
811 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
812 (ins FR32:$src1, FR32:$src2),
813 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
814 []>, XS, Requires<[HasAVX]>, VEX_4V;
815 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
816 (ins FR32:$src1, f32mem:$src2),
817 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
818 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
820 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
821 "cvtss2sd\t{$src, $dst|$dst, $src}",
822 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
824 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
825 "cvtss2sd\t{$src, $dst|$dst, $src}",
826 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
827 Requires<[HasSSE2, OptForSize]>;
829 let isAsmParserOnly = 1 in {
830 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
831 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
832 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
833 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
834 VR128:$src2))]>, XS, VEX_4V,
836 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
837 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
838 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
839 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
840 (load addr:$src2)))]>, XS, VEX_4V,
843 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
844 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
845 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
846 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
847 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
850 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
851 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
852 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
853 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
854 (load addr:$src2)))]>, XS,
858 def : Pat<(extloadf32 addr:$src),
859 (CVTSS2SDrr (MOVSSrm addr:$src))>,
860 Requires<[HasSSE2, OptForSpeed]>;
862 // Convert doubleword to packed single/double fp
863 let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
864 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
865 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
866 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
867 TB, VEX, Requires<[HasAVX]>;
868 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
869 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
870 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
871 (bitconvert (memopv2i64 addr:$src))))]>,
872 TB, VEX, Requires<[HasAVX]>;
874 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
875 "cvtdq2ps\t{$src, $dst|$dst, $src}",
876 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
877 TB, Requires<[HasSSE2]>;
878 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
879 "cvtdq2ps\t{$src, $dst|$dst, $src}",
880 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
881 (bitconvert (memopv2i64 addr:$src))))]>,
882 TB, Requires<[HasSSE2]>;
884 // FIXME: why the non-intrinsic version is described as SSE3?
885 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
886 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
887 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
888 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
889 XS, VEX, Requires<[HasAVX]>;
890 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
891 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
892 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
893 (bitconvert (memopv2i64 addr:$src))))]>,
894 XS, VEX, Requires<[HasAVX]>;
896 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
897 "cvtdq2pd\t{$src, $dst|$dst, $src}",
898 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
899 XS, Requires<[HasSSE2]>;
900 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
901 "cvtdq2pd\t{$src, $dst|$dst, $src}",
902 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
903 (bitconvert (memopv2i64 addr:$src))))]>,
904 XS, Requires<[HasSSE2]>;
907 // Convert packed single/double fp to doubleword
908 let isAsmParserOnly = 1 in {
909 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
910 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
911 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
912 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
913 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
914 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
915 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
916 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
918 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
919 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
920 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
921 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
923 let isAsmParserOnly = 1 in {
924 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
925 "cvtps2dq\t{$src, $dst|$dst, $src}",
926 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
928 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
930 "cvtps2dq\t{$src, $dst|$dst, $src}",
931 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
932 (memop addr:$src)))]>, VEX;
934 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
935 "cvtps2dq\t{$src, $dst|$dst, $src}",
936 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
937 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
938 "cvtps2dq\t{$src, $dst|$dst, $src}",
939 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
940 (memop addr:$src)))]>;
942 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XD prefix
943 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
944 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
945 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
946 XD, VEX, Requires<[HasAVX]>;
947 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
948 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
949 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
950 (memop addr:$src)))]>,
951 XD, VEX, Requires<[HasAVX]>;
953 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
954 "cvtpd2dq\t{$src, $dst|$dst, $src}",
955 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
956 XD, Requires<[HasSSE2]>;
957 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
958 "cvtpd2dq\t{$src, $dst|$dst, $src}",
959 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
960 (memop addr:$src)))]>,
961 XD, Requires<[HasSSE2]>;
964 // Convert with truncation packed single/double fp to doubleword
965 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XS prefix
966 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
967 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
968 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
969 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
970 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
971 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
972 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
973 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
975 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
976 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
977 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
978 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
981 let isAsmParserOnly = 1 in {
982 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
983 "vcvttps2dq\t{$src, $dst|$dst, $src}",
985 (int_x86_sse2_cvttps2dq VR128:$src))]>,
986 XS, VEX, Requires<[HasAVX]>;
987 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
988 "vcvttps2dq\t{$src, $dst|$dst, $src}",
989 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
990 (memop addr:$src)))]>,
991 XS, VEX, Requires<[HasAVX]>;
993 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
994 "cvttps2dq\t{$src, $dst|$dst, $src}",
996 (int_x86_sse2_cvttps2dq VR128:$src))]>,
997 XS, Requires<[HasSSE2]>;
998 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
999 "cvttps2dq\t{$src, $dst|$dst, $src}",
1000 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1001 (memop addr:$src)))]>,
1002 XS, Requires<[HasSSE2]>;
1004 let isAsmParserOnly = 1 in {
1005 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
1007 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1008 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
1010 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
1012 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1013 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1014 (memop addr:$src)))]>, VEX;
1016 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1017 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1018 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1019 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1020 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1021 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1022 (memop addr:$src)))]>;
1024 let isAsmParserOnly = 1 in {
1025 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1026 // register, but the same isn't true when using memory operands instead.
1027 // Provide other assembly rr and rm forms to address this explicitly.
1028 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1029 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1030 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1031 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1034 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1035 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1036 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1037 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1040 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1041 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1042 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1043 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1046 // Convert packed single to packed double
1047 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
1048 // SSE2 instructions without OpSize prefix
1049 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1050 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1051 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1052 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1053 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1054 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1055 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1056 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1058 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1059 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1060 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1061 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1063 let isAsmParserOnly = 1 in {
1064 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1065 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1066 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1067 VEX, Requires<[HasAVX]>;
1068 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1069 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1070 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1071 (load addr:$src)))]>,
1072 VEX, Requires<[HasAVX]>;
1074 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1075 "cvtps2pd\t{$src, $dst|$dst, $src}",
1076 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1077 TB, Requires<[HasSSE2]>;
1078 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1079 "cvtps2pd\t{$src, $dst|$dst, $src}",
1080 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1081 (load addr:$src)))]>,
1082 TB, Requires<[HasSSE2]>;
1084 // Convert packed double to packed single
1085 let isAsmParserOnly = 1 in {
1086 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1087 // register, but the same isn't true when using memory operands instead.
1088 // Provide other assembly rr and rm forms to address this explicitly.
1089 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1090 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1091 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1092 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1095 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1096 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1097 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1098 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1101 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1102 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1103 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1104 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1106 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1107 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1108 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1109 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1112 let isAsmParserOnly = 1 in {
1113 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1114 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1115 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1116 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1118 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1119 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1120 (memop addr:$src)))]>;
1122 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1123 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1124 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1125 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1126 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1127 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1128 (memop addr:$src)))]>;
1130 // AVX 256-bit register conversion intrinsics
1131 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1132 // whenever possible to avoid declaring two versions of each one.
1133 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1134 (VCVTDQ2PSYrr VR256:$src)>;
1135 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1136 (VCVTDQ2PSYrm addr:$src)>;
1138 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1139 (VCVTPD2PSYrr VR256:$src)>;
1140 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1141 (VCVTPD2PSYrm addr:$src)>;
1143 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1144 (VCVTPS2DQYrr VR256:$src)>;
1145 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1146 (VCVTPS2DQYrm addr:$src)>;
1148 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1149 (VCVTPS2PDYrr VR128:$src)>;
1150 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1151 (VCVTPS2PDYrm addr:$src)>;
1153 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1154 (VCVTTPD2DQYrr VR256:$src)>;
1155 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1156 (VCVTTPD2DQYrm addr:$src)>;
1158 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1159 (VCVTTPS2DQYrr VR256:$src)>;
1160 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1161 (VCVTTPS2DQYrm addr:$src)>;
1163 //===----------------------------------------------------------------------===//
1164 // SSE 1 & 2 - Compare Instructions
1165 //===----------------------------------------------------------------------===//
1167 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1168 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1169 string asm, string asm_alt> {
1170 def rr : SIi8<0xC2, MRMSrcReg,
1171 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1174 def rm : SIi8<0xC2, MRMSrcMem,
1175 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1177 // Accept explicit immediate argument form instead of comparison code.
1178 let isAsmParserOnly = 1 in {
1179 def rr_alt : SIi8<0xC2, MRMSrcReg,
1180 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1183 def rm_alt : SIi8<0xC2, MRMSrcMem,
1184 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1189 let neverHasSideEffects = 1, isAsmParserOnly = 1 in {
1190 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1191 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1192 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1194 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1195 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1196 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1200 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1201 defm CMPSS : sse12_cmp_scalar<FR32, f32mem,
1202 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
1203 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
1204 defm CMPSD : sse12_cmp_scalar<FR64, f64mem,
1205 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1206 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
1209 multiclass sse12_cmp_scalar_int<RegisterClass RC, Operand memopr,
1210 ComplexPattern mem_cpat, Intrinsic Int, string asm> {
1211 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1212 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1213 [(set VR128:$dst, (Int VR128:$src1,
1214 VR128:$src, imm:$cc))]>;
1215 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1216 (ins VR128:$src1, memopr:$src, SSECC:$cc), asm,
1217 [(set VR128:$dst, (Int VR128:$src1,
1218 mem_cpat:$src, imm:$cc))]>;
1221 // Aliases to match intrinsics which expect XMM operand(s).
1223 let isAsmParserOnly = 1 in {
1224 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, ssmem, sse_load_f32,
1226 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1228 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, sdmem, sse_load_f64,
1229 int_x86_sse2_cmp_sd,
1230 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1233 let Constraints = "$src1 = $dst" in {
1234 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, ssmem, sse_load_f32,
1236 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1237 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, sdmem, sse_load_f64,
1238 int_x86_sse2_cmp_sd,
1239 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1243 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1244 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1245 ValueType vt, X86MemOperand x86memop,
1246 PatFrag ld_frag, string OpcodeStr, Domain d> {
1247 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1248 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1249 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1250 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1251 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1252 [(set EFLAGS, (OpNode (vt RC:$src1),
1253 (ld_frag addr:$src2)))], d>;
1256 let Defs = [EFLAGS] in {
1257 let isAsmParserOnly = 1 in {
1258 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1259 "ucomiss", SSEPackedSingle>, VEX;
1260 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1261 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1262 let Pattern = []<dag> in {
1263 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1264 "comiss", SSEPackedSingle>, VEX;
1265 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1266 "comisd", SSEPackedDouble>, OpSize, VEX;
1269 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1270 load, "ucomiss", SSEPackedSingle>, VEX;
1271 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1272 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1274 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1275 load, "comiss", SSEPackedSingle>, VEX;
1276 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1277 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1279 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1280 "ucomiss", SSEPackedSingle>, TB;
1281 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1282 "ucomisd", SSEPackedDouble>, TB, OpSize;
1284 let Pattern = []<dag> in {
1285 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1286 "comiss", SSEPackedSingle>, TB;
1287 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1288 "comisd", SSEPackedDouble>, TB, OpSize;
1291 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1292 load, "ucomiss", SSEPackedSingle>, TB;
1293 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1294 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1296 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1297 "comiss", SSEPackedSingle>, TB;
1298 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1299 "comisd", SSEPackedDouble>, TB, OpSize;
1300 } // Defs = [EFLAGS]
1302 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1303 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1304 Intrinsic Int, string asm, string asm_alt,
1306 def rri : PIi8<0xC2, MRMSrcReg,
1307 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1308 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1309 def rmi : PIi8<0xC2, MRMSrcMem,
1310 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1311 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1312 // Accept explicit immediate argument form instead of comparison code.
1313 let isAsmParserOnly = 1 in {
1314 def rri_alt : PIi8<0xC2, MRMSrcReg,
1315 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1317 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1318 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1323 let isAsmParserOnly = 1 in {
1324 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1325 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1326 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1327 SSEPackedSingle>, VEX_4V;
1328 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1329 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1330 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1331 SSEPackedDouble>, OpSize, VEX_4V;
1332 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1333 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1334 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1335 SSEPackedSingle>, VEX_4V;
1336 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1337 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1338 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1339 SSEPackedDouble>, OpSize, VEX_4V;
1341 let Constraints = "$src1 = $dst" in {
1342 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1343 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1344 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1345 SSEPackedSingle>, TB;
1346 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1347 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1348 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1349 SSEPackedDouble>, TB, OpSize;
1352 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1353 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1354 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1355 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1356 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1357 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1358 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1359 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1361 //===----------------------------------------------------------------------===//
1362 // SSE 1 & 2 - Shuffle Instructions
1363 //===----------------------------------------------------------------------===//
1365 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1366 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1367 ValueType vt, string asm, PatFrag mem_frag,
1368 Domain d, bit IsConvertibleToThreeAddress = 0> {
1369 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1370 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1371 [(set RC:$dst, (vt (shufp:$src3
1372 RC:$src1, (mem_frag addr:$src2))))], d>;
1373 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1374 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1375 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1377 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1380 let isAsmParserOnly = 1 in {
1381 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1382 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1383 memopv4f32, SSEPackedSingle>, VEX_4V;
1384 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1385 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1386 memopv8f32, SSEPackedSingle>, VEX_4V;
1387 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1388 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1389 memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
1390 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1391 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1392 memopv4f64, SSEPackedDouble>, OpSize, VEX_4V;
1395 let Constraints = "$src1 = $dst" in {
1396 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1397 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1398 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1400 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1401 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1402 memopv2f64, SSEPackedDouble>, TB, OpSize;
1405 //===----------------------------------------------------------------------===//
1406 // SSE 1 & 2 - Unpack Instructions
1407 //===----------------------------------------------------------------------===//
1409 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1410 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1411 PatFrag mem_frag, RegisterClass RC,
1412 X86MemOperand x86memop, string asm,
1414 def rr : PI<opc, MRMSrcReg,
1415 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1417 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1418 def rm : PI<opc, MRMSrcMem,
1419 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1421 (vt (OpNode RC:$src1,
1422 (mem_frag addr:$src2))))], d>;
1425 let AddedComplexity = 10 in {
1426 let isAsmParserOnly = 1 in {
1427 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1428 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1429 SSEPackedSingle>, VEX_4V;
1430 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1431 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1432 SSEPackedDouble>, OpSize, VEX_4V;
1433 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1434 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1435 SSEPackedSingle>, VEX_4V;
1436 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1437 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1438 SSEPackedDouble>, OpSize, VEX_4V;
1440 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1441 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1442 SSEPackedSingle>, VEX_4V;
1443 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1444 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1445 SSEPackedDouble>, OpSize, VEX_4V;
1446 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1447 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1448 SSEPackedSingle>, VEX_4V;
1449 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1450 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1451 SSEPackedDouble>, OpSize, VEX_4V;
1454 let Constraints = "$src1 = $dst" in {
1455 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1456 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1457 SSEPackedSingle>, TB;
1458 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1459 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1460 SSEPackedDouble>, TB, OpSize;
1461 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1462 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1463 SSEPackedSingle>, TB;
1464 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1465 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1466 SSEPackedDouble>, TB, OpSize;
1467 } // Constraints = "$src1 = $dst"
1468 } // AddedComplexity
1470 //===----------------------------------------------------------------------===//
1471 // SSE 1 & 2 - Extract Floating-Point Sign mask
1472 //===----------------------------------------------------------------------===//
1474 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1475 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1477 def rr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1478 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1479 [(set GR32:$dst, (Int RC:$src))], d>;
1483 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1484 SSEPackedSingle>, TB;
1485 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1486 SSEPackedDouble>, TB, OpSize;
1488 let isAsmParserOnly = 1 in {
1489 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1490 "movmskps", SSEPackedSingle>, VEX;
1491 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1492 "movmskpd", SSEPackedDouble>, OpSize,
1494 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1495 "movmskps", SSEPackedSingle>, VEX;
1496 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1497 "movmskpd", SSEPackedDouble>, OpSize,
1501 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1502 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1503 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1504 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1506 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1507 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1508 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1509 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1513 //===----------------------------------------------------------------------===//
1514 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1515 //===----------------------------------------------------------------------===//
1517 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1518 // names that start with 'Fs'.
1520 // Alias instructions that map fld0 to pxor for sse.
1521 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1522 canFoldAsLoad = 1 in {
1523 // FIXME: Set encoding to pseudo!
1524 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1525 [(set FR32:$dst, fp32imm0)]>,
1526 Requires<[HasSSE1]>, TB, OpSize;
1527 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1528 [(set FR64:$dst, fpimm0)]>,
1529 Requires<[HasSSE2]>, TB, OpSize;
1532 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1533 // bits are disregarded.
1534 let neverHasSideEffects = 1 in {
1535 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1536 "movaps\t{$src, $dst|$dst, $src}", []>;
1537 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1538 "movapd\t{$src, $dst|$dst, $src}", []>;
1541 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1542 // bits are disregarded.
1543 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1544 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1545 "movaps\t{$src, $dst|$dst, $src}",
1546 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1547 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1548 "movapd\t{$src, $dst|$dst, $src}",
1549 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1552 //===----------------------------------------------------------------------===//
1553 // SSE 1 & 2 - Logical Instructions
1554 //===----------------------------------------------------------------------===//
1556 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1558 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1560 let isAsmParserOnly = 1 in {
1561 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1562 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1564 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1565 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1568 let Constraints = "$src1 = $dst" in {
1569 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1570 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1572 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1573 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1577 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1578 let mayLoad = 0 in {
1579 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1580 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1581 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1584 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1585 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1587 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1589 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1590 SDNode OpNode, int HasPat = 0,
1591 list<list<dag>> Pattern = []> {
1592 let isAsmParserOnly = 1, Pattern = []<dag> in {
1593 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1594 !strconcat(OpcodeStr, "ps"), f128mem,
1595 !if(HasPat, Pattern[0], // rr
1596 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1598 !if(HasPat, Pattern[2], // rm
1599 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1600 (memopv2i64 addr:$src2)))]), 0>,
1603 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1604 !strconcat(OpcodeStr, "pd"), f128mem,
1605 !if(HasPat, Pattern[1], // rr
1606 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1609 !if(HasPat, Pattern[3], // rm
1610 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1611 (memopv2i64 addr:$src2)))]), 0>,
1614 let Constraints = "$src1 = $dst" in {
1615 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1616 !strconcat(OpcodeStr, "ps"), f128mem,
1617 !if(HasPat, Pattern[0], // rr
1618 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1620 !if(HasPat, Pattern[2], // rm
1621 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1622 (memopv2i64 addr:$src2)))])>, TB;
1624 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1625 !strconcat(OpcodeStr, "pd"), f128mem,
1626 !if(HasPat, Pattern[1], // rr
1627 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1630 !if(HasPat, Pattern[3], // rm
1631 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1632 (memopv2i64 addr:$src2)))])>,
1637 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1639 let isAsmParserOnly = 1 in {
1640 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr> {
1641 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1642 !strconcat(OpcodeStr, "ps"), f256mem, [], [], 0>, VEX_4V;
1644 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1645 !strconcat(OpcodeStr, "pd"), f256mem, [], [], 0>, OpSize, VEX_4V;
1649 // AVX 256-bit packed logical ops forms
1650 defm VAND : sse12_fp_packed_logical_y<0x54, "and">;
1651 defm VOR : sse12_fp_packed_logical_y<0x56, "or">;
1652 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor">;
1653 let isCommutable = 0 in
1654 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn">;
1656 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1657 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1658 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1659 let isCommutable = 0 in
1660 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1662 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1663 (bc_v2i64 (v4i32 immAllOnesV))),
1666 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1667 (bc_v2i64 (v2f64 VR128:$src2))))],
1669 [(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1670 (bc_v2i64 (v4i32 immAllOnesV))),
1671 (memopv2i64 addr:$src2))))],
1673 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1674 (memopv2i64 addr:$src2)))]]>;
1676 //===----------------------------------------------------------------------===//
1677 // SSE 1 & 2 - Arithmetic Instructions
1678 //===----------------------------------------------------------------------===//
1680 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1683 /// In addition, we also have a special variant of the scalar form here to
1684 /// represent the associated intrinsic operation. This form is unlike the
1685 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1686 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1688 /// These three forms can each be reg+reg or reg+mem.
1691 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1693 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1695 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1696 OpNode, FR32, f32mem, Is2Addr>, XS;
1697 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1698 OpNode, FR64, f64mem, Is2Addr>, XD;
1701 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1703 let mayLoad = 0 in {
1704 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1705 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1706 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1707 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1711 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1713 let mayLoad = 0 in {
1714 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1715 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1716 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1717 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1721 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1723 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1724 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1725 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1726 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1729 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1731 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1732 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1733 SSEPackedSingle, Is2Addr>, TB;
1735 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1736 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1737 SSEPackedDouble, Is2Addr>, TB, OpSize;
1740 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1741 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1742 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1743 SSEPackedSingle, 0>, TB;
1745 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1746 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1747 SSEPackedDouble, 0>, TB, OpSize;
1750 // Binary Arithmetic instructions
1751 let isAsmParserOnly = 1 in {
1752 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1753 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1754 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1755 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1756 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1757 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1758 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1759 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1761 let isCommutable = 0 in {
1762 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1763 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1764 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1765 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1766 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1767 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1768 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1769 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1770 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1771 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1772 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1773 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1774 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1775 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1776 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1777 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1778 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1779 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1780 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1781 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1785 let Constraints = "$src1 = $dst" in {
1786 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1787 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1788 basic_sse12_fp_binop_s_int<0x58, "add">;
1789 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1790 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1791 basic_sse12_fp_binop_s_int<0x59, "mul">;
1793 let isCommutable = 0 in {
1794 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1795 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1796 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1797 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1798 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1799 basic_sse12_fp_binop_s_int<0x5E, "div">;
1800 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1801 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1802 basic_sse12_fp_binop_s_int<0x5F, "max">,
1803 basic_sse12_fp_binop_p_int<0x5F, "max">;
1804 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1805 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1806 basic_sse12_fp_binop_s_int<0x5D, "min">,
1807 basic_sse12_fp_binop_p_int<0x5D, "min">;
1812 /// In addition, we also have a special variant of the scalar form here to
1813 /// represent the associated intrinsic operation. This form is unlike the
1814 /// plain scalar form, in that it takes an entire vector (instead of a
1815 /// scalar) and leaves the top elements undefined.
1817 /// And, we have a special variant form for a full-vector intrinsic form.
1819 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1820 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1821 SDNode OpNode, Intrinsic F32Int> {
1822 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1823 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1824 [(set FR32:$dst, (OpNode FR32:$src))]>;
1825 // For scalar unary operations, fold a load into the operation
1826 // only in OptForSize mode. It eliminates an instruction, but it also
1827 // eliminates a whole-register clobber (the load), so it introduces a
1828 // partial register update condition.
1829 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1830 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1831 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1832 Requires<[HasSSE1, OptForSize]>;
1833 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1834 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1835 [(set VR128:$dst, (F32Int VR128:$src))]>;
1836 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1837 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1838 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1841 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1842 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1843 SDNode OpNode, Intrinsic F32Int> {
1844 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1845 !strconcat(OpcodeStr,
1846 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1847 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1848 !strconcat(OpcodeStr,
1849 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1850 []>, XS, Requires<[HasAVX, OptForSize]>;
1851 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1852 !strconcat(OpcodeStr,
1853 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1854 [(set VR128:$dst, (F32Int VR128:$src))]>;
1855 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1856 !strconcat(OpcodeStr,
1857 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1858 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1861 /// sse1_fp_unop_p - SSE1 unops in packed form.
1862 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1863 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1864 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1865 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1866 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1867 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1868 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1871 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1872 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1873 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1874 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1875 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1876 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1877 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1878 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1881 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1882 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1883 Intrinsic V4F32Int> {
1884 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1885 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1886 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1887 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1888 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1889 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1892 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1893 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1894 Intrinsic V4F32Int> {
1895 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1896 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1897 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1898 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1899 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1900 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1903 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1904 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1905 SDNode OpNode, Intrinsic F64Int> {
1906 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1907 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1908 [(set FR64:$dst, (OpNode FR64:$src))]>;
1909 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1910 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1911 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1912 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1913 Requires<[HasSSE2, OptForSize]>;
1914 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1915 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1916 [(set VR128:$dst, (F64Int VR128:$src))]>;
1917 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1918 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1919 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1922 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1923 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1924 SDNode OpNode, Intrinsic F64Int> {
1925 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1926 !strconcat(OpcodeStr,
1927 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1928 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1929 (ins FR64:$src1, f64mem:$src2),
1930 !strconcat(OpcodeStr,
1931 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1932 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1933 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1934 [(set VR128:$dst, (F64Int VR128:$src))]>;
1935 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1936 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1937 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1940 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1941 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1943 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1944 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1945 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1946 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1947 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1948 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1951 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1952 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1953 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1954 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1955 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1956 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1957 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1958 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1961 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1962 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1963 Intrinsic V2F64Int> {
1964 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1965 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1966 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1967 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1968 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1969 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1972 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
1973 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1974 Intrinsic V2F64Int> {
1975 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1976 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1977 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1978 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1979 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1980 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1983 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
1985 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
1986 sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1989 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1990 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1991 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1992 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1993 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
1994 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
1995 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
1996 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
1999 // Reciprocal approximations. Note that these typically require refinement
2000 // in order to obtain suitable precision.
2001 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
2002 int_x86_sse_rsqrt_ss>, VEX_4V;
2003 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
2004 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
2005 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
2006 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
2008 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
2010 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
2011 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
2012 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
2013 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
2017 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
2018 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
2019 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
2020 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
2021 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
2022 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
2024 // Reciprocal approximations. Note that these typically require refinement
2025 // in order to obtain suitable precision.
2026 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
2027 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
2028 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
2029 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2030 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
2031 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
2033 // There is no f64 version of the reciprocal approximation instructions.
2035 //===----------------------------------------------------------------------===//
2036 // SSE 1 & 2 - Non-temporal stores
2037 //===----------------------------------------------------------------------===//
2039 let isAsmParserOnly = 1 in {
2040 def VMOVNTPSmr_Int : VPSI<0x2B, MRMDestMem, (outs),
2041 (ins i128mem:$dst, VR128:$src),
2042 "movntps\t{$src, $dst|$dst, $src}",
2043 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>, VEX;
2044 def VMOVNTPDmr_Int : VPDI<0x2B, MRMDestMem, (outs),
2045 (ins i128mem:$dst, VR128:$src),
2046 "movntpd\t{$src, $dst|$dst, $src}",
2047 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>, VEX;
2049 let ExeDomain = SSEPackedInt in
2050 def VMOVNTDQmr_Int : VPDI<0xE7, MRMDestMem, (outs),
2051 (ins f128mem:$dst, VR128:$src),
2052 "movntdq\t{$src, $dst|$dst, $src}",
2053 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>, VEX;
2055 let AddedComplexity = 400 in { // Prefer non-temporal versions
2056 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
2057 (ins f128mem:$dst, VR128:$src),
2058 "movntps\t{$src, $dst|$dst, $src}",
2059 [(alignednontemporalstore (v4f32 VR128:$src),
2061 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
2062 (ins f128mem:$dst, VR128:$src),
2063 "movntpd\t{$src, $dst|$dst, $src}",
2064 [(alignednontemporalstore (v2f64 VR128:$src),
2066 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
2067 (ins f128mem:$dst, VR128:$src),
2068 "movntdq\t{$src, $dst|$dst, $src}",
2069 [(alignednontemporalstore (v2f64 VR128:$src),
2071 let ExeDomain = SSEPackedInt in
2072 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
2073 (ins f128mem:$dst, VR128:$src),
2074 "movntdq\t{$src, $dst|$dst, $src}",
2075 [(alignednontemporalstore (v4f32 VR128:$src),
2078 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
2079 (ins f256mem:$dst, VR256:$src),
2080 "movntps\t{$src, $dst|$dst, $src}",
2081 [(alignednontemporalstore (v8f32 VR256:$src),
2083 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
2084 (ins f256mem:$dst, VR256:$src),
2085 "movntpd\t{$src, $dst|$dst, $src}",
2086 [(alignednontemporalstore (v4f64 VR256:$src),
2088 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
2089 (ins f256mem:$dst, VR256:$src),
2090 "movntdq\t{$src, $dst|$dst, $src}",
2091 [(alignednontemporalstore (v4f64 VR256:$src),
2093 let ExeDomain = SSEPackedInt in
2094 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
2095 (ins f256mem:$dst, VR256:$src),
2096 "movntdq\t{$src, $dst|$dst, $src}",
2097 [(alignednontemporalstore (v8f32 VR256:$src),
2102 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
2103 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
2104 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
2105 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
2106 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
2107 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
2109 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2110 "movntps\t{$src, $dst|$dst, $src}",
2111 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
2112 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2113 "movntpd\t{$src, $dst|$dst, $src}",
2114 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2116 let ExeDomain = SSEPackedInt in
2117 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2118 "movntdq\t{$src, $dst|$dst, $src}",
2119 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2121 let AddedComplexity = 400 in { // Prefer non-temporal versions
2122 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2123 "movntps\t{$src, $dst|$dst, $src}",
2124 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2125 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2126 "movntpd\t{$src, $dst|$dst, $src}",
2127 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2129 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2130 "movntdq\t{$src, $dst|$dst, $src}",
2131 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2133 let ExeDomain = SSEPackedInt in
2134 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2135 "movntdq\t{$src, $dst|$dst, $src}",
2136 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2138 // There is no AVX form for instructions below this point
2139 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2140 "movnti\t{$src, $dst|$dst, $src}",
2141 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2142 TB, Requires<[HasSSE2]>;
2144 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2145 "movnti\t{$src, $dst|$dst, $src}",
2146 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2147 TB, Requires<[HasSSE2]>;
2150 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2151 "movnti\t{$src, $dst|$dst, $src}",
2152 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2153 TB, Requires<[HasSSE2]>;
2155 //===----------------------------------------------------------------------===//
2156 // SSE 1 & 2 - Misc Instructions (No AVX form)
2157 //===----------------------------------------------------------------------===//
2159 // Prefetch intrinsic.
2160 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2161 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
2162 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2163 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
2164 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2165 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
2166 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2167 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
2169 // Load, store, and memory fence
2170 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2171 TB, Requires<[HasSSE1]>;
2172 def : Pat<(X86SFence), (SFENCE)>;
2174 // Alias instructions that map zero vector to pxor / xorp* for sse.
2175 // We set canFoldAsLoad because this can be converted to a constant-pool
2176 // load of an all-zeros value if folding it would be beneficial.
2177 // FIXME: Change encoding to pseudo!
2178 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2179 isCodeGenOnly = 1 in {
2180 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2181 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2182 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2183 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2184 let ExeDomain = SSEPackedInt in
2185 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2186 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2189 // The same as done above but for AVX. The 128-bit versions are the
2190 // same, but re-encoded. The 256-bit does not support PI version.
2191 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2192 isCodeGenOnly = 1, Predicates = [HasAVX] in {
2193 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2194 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
2195 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2196 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
2197 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2198 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
2199 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2200 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
2201 let ExeDomain = SSEPackedInt in
2202 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2203 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2206 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2207 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2208 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2210 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2211 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2213 //===----------------------------------------------------------------------===//
2214 // SSE 1 & 2 - Load/Store XCSR register
2215 //===----------------------------------------------------------------------===//
2217 let isAsmParserOnly = 1 in {
2218 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2219 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2220 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2221 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2224 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2225 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2226 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2227 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2229 //===---------------------------------------------------------------------===//
2230 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2231 //===---------------------------------------------------------------------===//
2233 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2235 let isAsmParserOnly = 1 in {
2236 let neverHasSideEffects = 1 in {
2237 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2238 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2239 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2240 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2242 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2243 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2244 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2245 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2247 let canFoldAsLoad = 1, mayLoad = 1 in {
2248 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2249 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2250 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2251 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2252 let Predicates = [HasAVX] in {
2253 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2254 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2255 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2256 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2260 let mayStore = 1 in {
2261 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2262 (ins i128mem:$dst, VR128:$src),
2263 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2264 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2265 (ins i256mem:$dst, VR256:$src),
2266 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2267 let Predicates = [HasAVX] in {
2268 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2269 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2270 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2271 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2276 let neverHasSideEffects = 1 in
2277 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2278 "movdqa\t{$src, $dst|$dst, $src}", []>;
2280 let canFoldAsLoad = 1, mayLoad = 1 in {
2281 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2282 "movdqa\t{$src, $dst|$dst, $src}",
2283 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2284 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2285 "movdqu\t{$src, $dst|$dst, $src}",
2286 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2287 XS, Requires<[HasSSE2]>;
2290 let mayStore = 1 in {
2291 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2292 "movdqa\t{$src, $dst|$dst, $src}",
2293 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2294 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2295 "movdqu\t{$src, $dst|$dst, $src}",
2296 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2297 XS, Requires<[HasSSE2]>;
2300 // Intrinsic forms of MOVDQU load and store
2301 let isAsmParserOnly = 1 in {
2302 let canFoldAsLoad = 1 in
2303 def VMOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2304 "vmovdqu\t{$src, $dst|$dst, $src}",
2305 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2306 XS, VEX, Requires<[HasAVX]>;
2307 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2308 "vmovdqu\t{$src, $dst|$dst, $src}",
2309 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2310 XS, VEX, Requires<[HasAVX]>;
2313 let canFoldAsLoad = 1 in
2314 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2315 "movdqu\t{$src, $dst|$dst, $src}",
2316 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2317 XS, Requires<[HasSSE2]>;
2318 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2319 "movdqu\t{$src, $dst|$dst, $src}",
2320 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2321 XS, Requires<[HasSSE2]>;
2323 } // ExeDomain = SSEPackedInt
2325 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2326 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2327 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2329 //===---------------------------------------------------------------------===//
2330 // SSE2 - Packed Integer Arithmetic Instructions
2331 //===---------------------------------------------------------------------===//
2333 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2335 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2336 bit IsCommutable = 0, bit Is2Addr = 1> {
2337 let isCommutable = IsCommutable in
2338 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2339 (ins VR128:$src1, VR128:$src2),
2341 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2342 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2343 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2344 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2345 (ins VR128:$src1, i128mem:$src2),
2347 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2348 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2349 [(set VR128:$dst, (IntId VR128:$src1,
2350 (bitconvert (memopv2i64 addr:$src2))))]>;
2353 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2354 string OpcodeStr, Intrinsic IntId,
2355 Intrinsic IntId2, bit Is2Addr = 1> {
2356 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2357 (ins VR128:$src1, VR128:$src2),
2359 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2360 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2361 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2362 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2363 (ins VR128:$src1, i128mem:$src2),
2365 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2366 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2367 [(set VR128:$dst, (IntId VR128:$src1,
2368 (bitconvert (memopv2i64 addr:$src2))))]>;
2369 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2370 (ins VR128:$src1, i32i8imm:$src2),
2372 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2373 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2374 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2377 /// PDI_binop_rm - Simple SSE2 binary operator.
2378 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2379 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2380 let isCommutable = IsCommutable in
2381 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2382 (ins VR128:$src1, VR128:$src2),
2384 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2385 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2386 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2387 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2388 (ins VR128:$src1, i128mem:$src2),
2390 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2391 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2392 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2393 (bitconvert (memopv2i64 addr:$src2)))))]>;
2396 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2398 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2399 /// to collapse (bitconvert VT to VT) into its operand.
2401 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2402 bit IsCommutable = 0, bit Is2Addr = 1> {
2403 let isCommutable = IsCommutable in
2404 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2405 (ins VR128:$src1, VR128:$src2),
2407 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2408 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2409 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2410 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2411 (ins VR128:$src1, i128mem:$src2),
2413 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2414 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2415 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2418 } // ExeDomain = SSEPackedInt
2420 // 128-bit Integer Arithmetic
2422 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2423 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2424 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2425 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2426 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2427 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2428 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2429 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2430 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2431 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2434 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2436 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2438 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2440 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2442 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2444 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2446 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2448 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2450 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2452 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2454 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2456 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2458 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2460 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2462 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2464 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2466 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2468 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2470 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2474 let Constraints = "$src1 = $dst" in {
2475 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2476 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2477 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2478 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2479 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2480 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2481 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2482 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2483 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2486 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2487 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2488 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2489 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2490 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2491 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2492 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2493 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2494 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2495 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2496 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2497 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2498 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2499 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2500 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2501 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2502 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2503 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2504 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2506 } // Constraints = "$src1 = $dst"
2508 //===---------------------------------------------------------------------===//
2509 // SSE2 - Packed Integer Logical Instructions
2510 //===---------------------------------------------------------------------===//
2512 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2513 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2514 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2516 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2517 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2519 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2520 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2523 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2524 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2526 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2527 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2529 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2530 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2533 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2534 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2536 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2537 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2540 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2541 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2542 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2544 let ExeDomain = SSEPackedInt in {
2545 let neverHasSideEffects = 1 in {
2546 // 128-bit logical shifts.
2547 def VPSLLDQri : PDIi8<0x73, MRM7r,
2548 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2549 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2551 def VPSRLDQri : PDIi8<0x73, MRM3r,
2552 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2553 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2555 // PSRADQri doesn't exist in SSE[1-3].
2557 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2558 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2559 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2560 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2561 VR128:$src2)))]>, VEX_4V;
2563 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2564 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2565 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2566 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2567 (memopv2i64 addr:$src2))))]>,
2572 let Constraints = "$src1 = $dst" in {
2573 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2574 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2575 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2576 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2577 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2578 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2580 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2581 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2582 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2583 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2584 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2585 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2587 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2588 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2589 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2590 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2592 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2593 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2594 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2596 let ExeDomain = SSEPackedInt in {
2597 let neverHasSideEffects = 1 in {
2598 // 128-bit logical shifts.
2599 def PSLLDQri : PDIi8<0x73, MRM7r,
2600 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2601 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2602 def PSRLDQri : PDIi8<0x73, MRM3r,
2603 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2604 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2605 // PSRADQri doesn't exist in SSE[1-3].
2607 def PANDNrr : PDI<0xDF, MRMSrcReg,
2608 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2609 "pandn\t{$src2, $dst|$dst, $src2}",
2610 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2613 def PANDNrm : PDI<0xDF, MRMSrcMem,
2614 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2615 "pandn\t{$src2, $dst|$dst, $src2}",
2616 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2617 (memopv2i64 addr:$src2))))]>;
2619 } // Constraints = "$src1 = $dst"
2621 let Predicates = [HasAVX] in {
2622 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2623 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2624 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2625 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2626 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2627 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2628 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2629 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2630 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2631 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2633 // Shift up / down and insert zero's.
2634 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2635 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2636 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2637 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2640 let Predicates = [HasSSE2] in {
2641 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2642 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2643 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2644 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2645 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2646 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2647 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2648 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2649 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2650 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2652 // Shift up / down and insert zero's.
2653 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2654 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2655 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2656 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2659 //===---------------------------------------------------------------------===//
2660 // SSE2 - Packed Integer Comparison Instructions
2661 //===---------------------------------------------------------------------===//
2663 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2664 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2666 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2668 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2670 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2672 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2674 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2678 let Constraints = "$src1 = $dst" in {
2679 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2680 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2681 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2682 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2683 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2684 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2685 } // Constraints = "$src1 = $dst"
2687 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2688 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2689 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2690 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2691 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2692 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2693 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2694 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2695 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2696 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2697 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2698 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2700 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2701 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2702 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2703 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2704 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2705 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2706 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2707 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2708 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2709 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2710 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2711 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2713 //===---------------------------------------------------------------------===//
2714 // SSE2 - Packed Integer Pack Instructions
2715 //===---------------------------------------------------------------------===//
2717 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2718 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2720 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2722 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2726 let Constraints = "$src1 = $dst" in {
2727 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2728 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2729 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2730 } // Constraints = "$src1 = $dst"
2732 //===---------------------------------------------------------------------===//
2733 // SSE2 - Packed Integer Shuffle Instructions
2734 //===---------------------------------------------------------------------===//
2736 let ExeDomain = SSEPackedInt in {
2737 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2739 def ri : Ii8<0x70, MRMSrcReg,
2740 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2741 !strconcat(OpcodeStr,
2742 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2743 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2745 def mi : Ii8<0x70, MRMSrcMem,
2746 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2747 !strconcat(OpcodeStr,
2748 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2749 [(set VR128:$dst, (vt (pshuf_frag:$src2
2750 (bc_frag (memopv2i64 addr:$src1)),
2753 } // ExeDomain = SSEPackedInt
2755 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2756 let AddedComplexity = 5 in
2757 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2760 // SSE2 with ImmT == Imm8 and XS prefix.
2761 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2764 // SSE2 with ImmT == Imm8 and XD prefix.
2765 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2769 let Predicates = [HasSSE2] in {
2770 let AddedComplexity = 5 in
2771 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2773 // SSE2 with ImmT == Imm8 and XS prefix.
2774 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2776 // SSE2 with ImmT == Imm8 and XD prefix.
2777 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2780 //===---------------------------------------------------------------------===//
2781 // SSE2 - Packed Integer Unpack Instructions
2782 //===---------------------------------------------------------------------===//
2784 let ExeDomain = SSEPackedInt in {
2785 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2786 PatFrag unp_frag, PatFrag bc_frag, bit Is2Addr = 1> {
2787 def rr : PDI<opc, MRMSrcReg,
2788 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2790 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2791 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2792 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2793 def rm : PDI<opc, MRMSrcMem,
2794 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2796 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2797 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2798 [(set VR128:$dst, (unp_frag VR128:$src1,
2799 (bc_frag (memopv2i64
2803 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2804 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8,
2806 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16,
2808 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, unpckl, bc_v4i32,
2811 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2812 /// knew to collapse (bitconvert VT to VT) into its operand.
2813 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2814 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2815 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2817 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>, VEX_4V;
2818 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2819 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2820 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2822 (v2i64 (unpckl VR128:$src1,
2823 (memopv2i64 addr:$src2))))]>, VEX_4V;
2825 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, unpckh, bc_v16i8,
2827 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, unpckh, bc_v8i16,
2829 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, unpckh, bc_v4i32,
2832 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2833 /// knew to collapse (bitconvert VT to VT) into its operand.
2834 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2835 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2836 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2838 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>, VEX_4V;
2839 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2840 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2841 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2843 (v2i64 (unpckh VR128:$src1,
2844 (memopv2i64 addr:$src2))))]>, VEX_4V;
2847 let Constraints = "$src1 = $dst" in {
2848 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2849 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2850 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2852 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2853 /// knew to collapse (bitconvert VT to VT) into its operand.
2854 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2855 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2856 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2858 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2859 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2860 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2861 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2863 (v2i64 (unpckl VR128:$src1,
2864 (memopv2i64 addr:$src2))))]>;
2866 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2867 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2868 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2870 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2871 /// knew to collapse (bitconvert VT to VT) into its operand.
2872 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2873 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2874 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2876 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2877 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2878 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2879 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2881 (v2i64 (unpckh VR128:$src1,
2882 (memopv2i64 addr:$src2))))]>;
2885 } // ExeDomain = SSEPackedInt
2887 //===---------------------------------------------------------------------===//
2888 // SSE2 - Packed Integer Extract and Insert
2889 //===---------------------------------------------------------------------===//
2891 let ExeDomain = SSEPackedInt in {
2892 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2893 def rri : Ii8<0xC4, MRMSrcReg,
2894 (outs VR128:$dst), (ins VR128:$src1,
2895 GR32:$src2, i32i8imm:$src3),
2897 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2898 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2900 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2901 def rmi : Ii8<0xC4, MRMSrcMem,
2902 (outs VR128:$dst), (ins VR128:$src1,
2903 i16mem:$src2, i32i8imm:$src3),
2905 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2906 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2908 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2913 let isAsmParserOnly = 1, Predicates = [HasAVX] in
2914 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2915 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2916 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2917 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2918 imm:$src2))]>, OpSize, VEX;
2919 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2920 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2921 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2922 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2926 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2927 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2928 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2929 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2930 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2931 []>, OpSize, VEX_4V;
2934 let Constraints = "$src1 = $dst" in
2935 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
2937 } // ExeDomain = SSEPackedInt
2939 //===---------------------------------------------------------------------===//
2940 // SSE2 - Packed Mask Creation
2941 //===---------------------------------------------------------------------===//
2943 let ExeDomain = SSEPackedInt in {
2945 let isAsmParserOnly = 1 in {
2946 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2947 "pmovmskb\t{$src, $dst|$dst, $src}",
2948 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2949 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2950 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2952 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2953 "pmovmskb\t{$src, $dst|$dst, $src}",
2954 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2956 } // ExeDomain = SSEPackedInt
2958 //===---------------------------------------------------------------------===//
2959 // SSE2 - Conditional Store
2960 //===---------------------------------------------------------------------===//
2962 let ExeDomain = SSEPackedInt in {
2964 let isAsmParserOnly = 1 in {
2966 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2967 (ins VR128:$src, VR128:$mask),
2968 "maskmovdqu\t{$mask, $src|$src, $mask}",
2969 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2971 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2972 (ins VR128:$src, VR128:$mask),
2973 "maskmovdqu\t{$mask, $src|$src, $mask}",
2974 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2978 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2979 "maskmovdqu\t{$mask, $src|$src, $mask}",
2980 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2982 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2983 "maskmovdqu\t{$mask, $src|$src, $mask}",
2984 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2986 } // ExeDomain = SSEPackedInt
2988 //===---------------------------------------------------------------------===//
2989 // SSE2 - Move Doubleword
2990 //===---------------------------------------------------------------------===//
2992 // Move Int Doubleword to Packed Double Int
2993 let isAsmParserOnly = 1 in {
2994 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2995 "movd\t{$src, $dst|$dst, $src}",
2997 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2998 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2999 "movd\t{$src, $dst|$dst, $src}",
3001 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
3004 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3005 "movd\t{$src, $dst|$dst, $src}",
3007 (v4i32 (scalar_to_vector GR32:$src)))]>;
3008 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3009 "movd\t{$src, $dst|$dst, $src}",
3011 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
3014 // Move Int Doubleword to Single Scalar
3015 let isAsmParserOnly = 1 in {
3016 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
3017 "movd\t{$src, $dst|$dst, $src}",
3018 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
3020 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
3021 "movd\t{$src, $dst|$dst, $src}",
3022 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
3025 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
3026 "movd\t{$src, $dst|$dst, $src}",
3027 [(set FR32:$dst, (bitconvert GR32:$src))]>;
3029 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
3030 "movd\t{$src, $dst|$dst, $src}",
3031 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
3033 // Move Packed Doubleword Int to Packed Double Int
3034 let isAsmParserOnly = 1 in {
3035 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3036 "movd\t{$src, $dst|$dst, $src}",
3037 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3039 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
3040 (ins i32mem:$dst, VR128:$src),
3041 "movd\t{$src, $dst|$dst, $src}",
3042 [(store (i32 (vector_extract (v4i32 VR128:$src),
3043 (iPTR 0))), addr:$dst)]>, VEX;
3045 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3046 "movd\t{$src, $dst|$dst, $src}",
3047 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3049 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
3050 "movd\t{$src, $dst|$dst, $src}",
3051 [(store (i32 (vector_extract (v4i32 VR128:$src),
3052 (iPTR 0))), addr:$dst)]>;
3054 // Move Scalar Single to Double Int
3055 let isAsmParserOnly = 1 in {
3056 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3057 "movd\t{$src, $dst|$dst, $src}",
3058 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
3059 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3060 "movd\t{$src, $dst|$dst, $src}",
3061 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
3063 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3064 "movd\t{$src, $dst|$dst, $src}",
3065 [(set GR32:$dst, (bitconvert FR32:$src))]>;
3066 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3067 "movd\t{$src, $dst|$dst, $src}",
3068 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
3070 // movd / movq to XMM register zero-extends
3071 let AddedComplexity = 15, isAsmParserOnly = 1 in {
3072 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3073 "movd\t{$src, $dst|$dst, $src}",
3074 [(set VR128:$dst, (v4i32 (X86vzmovl
3075 (v4i32 (scalar_to_vector GR32:$src)))))]>,
3077 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3078 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3079 [(set VR128:$dst, (v2i64 (X86vzmovl
3080 (v2i64 (scalar_to_vector GR64:$src)))))]>,
3083 let AddedComplexity = 15 in {
3084 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3085 "movd\t{$src, $dst|$dst, $src}",
3086 [(set VR128:$dst, (v4i32 (X86vzmovl
3087 (v4i32 (scalar_to_vector GR32:$src)))))]>;
3088 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3089 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3090 [(set VR128:$dst, (v2i64 (X86vzmovl
3091 (v2i64 (scalar_to_vector GR64:$src)))))]>;
3094 let AddedComplexity = 20 in {
3095 let isAsmParserOnly = 1 in
3096 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3097 "movd\t{$src, $dst|$dst, $src}",
3099 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3100 (loadi32 addr:$src))))))]>,
3102 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3103 "movd\t{$src, $dst|$dst, $src}",
3105 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3106 (loadi32 addr:$src))))))]>;
3108 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
3109 (MOVZDI2PDIrm addr:$src)>;
3110 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3111 (MOVZDI2PDIrm addr:$src)>;
3112 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3113 (MOVZDI2PDIrm addr:$src)>;
3116 //===---------------------------------------------------------------------===//
3117 // SSE2 - Move Quadword
3118 //===---------------------------------------------------------------------===//
3120 // Move Quadword Int to Packed Quadword Int
3121 let isAsmParserOnly = 1 in
3122 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3123 "vmovq\t{$src, $dst|$dst, $src}",
3125 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3126 VEX, Requires<[HasAVX]>;
3127 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3128 "movq\t{$src, $dst|$dst, $src}",
3130 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3131 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3133 // Move Packed Quadword Int to Quadword Int
3134 let isAsmParserOnly = 1 in
3135 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3136 "movq\t{$src, $dst|$dst, $src}",
3137 [(store (i64 (vector_extract (v2i64 VR128:$src),
3138 (iPTR 0))), addr:$dst)]>, VEX;
3139 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3140 "movq\t{$src, $dst|$dst, $src}",
3141 [(store (i64 (vector_extract (v2i64 VR128:$src),
3142 (iPTR 0))), addr:$dst)]>;
3144 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3145 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3147 // Store / copy lower 64-bits of a XMM register.
3148 let isAsmParserOnly = 1 in
3149 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3150 "movq\t{$src, $dst|$dst, $src}",
3151 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3152 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3153 "movq\t{$src, $dst|$dst, $src}",
3154 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3156 let AddedComplexity = 20, isAsmParserOnly = 1 in
3157 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3158 "vmovq\t{$src, $dst|$dst, $src}",
3160 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3161 (loadi64 addr:$src))))))]>,
3162 XS, VEX, Requires<[HasAVX]>;
3164 let AddedComplexity = 20 in {
3165 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3166 "movq\t{$src, $dst|$dst, $src}",
3168 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3169 (loadi64 addr:$src))))))]>,
3170 XS, Requires<[HasSSE2]>;
3172 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3173 (MOVZQI2PQIrm addr:$src)>;
3174 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3175 (MOVZQI2PQIrm addr:$src)>;
3176 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3179 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3180 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3181 let isAsmParserOnly = 1, AddedComplexity = 15 in
3182 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3183 "vmovq\t{$src, $dst|$dst, $src}",
3184 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3185 XS, VEX, Requires<[HasAVX]>;
3186 let AddedComplexity = 15 in
3187 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3188 "movq\t{$src, $dst|$dst, $src}",
3189 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3190 XS, Requires<[HasSSE2]>;
3192 let AddedComplexity = 20, isAsmParserOnly = 1 in
3193 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3194 "vmovq\t{$src, $dst|$dst, $src}",
3195 [(set VR128:$dst, (v2i64 (X86vzmovl
3196 (loadv2i64 addr:$src))))]>,
3197 XS, VEX, Requires<[HasAVX]>;
3198 let AddedComplexity = 20 in {
3199 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3200 "movq\t{$src, $dst|$dst, $src}",
3201 [(set VR128:$dst, (v2i64 (X86vzmovl
3202 (loadv2i64 addr:$src))))]>,
3203 XS, Requires<[HasSSE2]>;
3205 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3206 (MOVZPQILo2PQIrm addr:$src)>;
3209 // Instructions to match in the assembler
3210 let isAsmParserOnly = 1 in {
3211 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3212 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3213 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3214 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3215 // Recognize "movd" with GR64 destination, but encode as a "movq"
3216 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3217 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3220 // Instructions for the disassembler
3221 // xr = XMM register
3224 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3225 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3226 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3227 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3228 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3230 //===---------------------------------------------------------------------===//
3231 // SSE2 - Misc Instructions
3232 //===---------------------------------------------------------------------===//
3235 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3236 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3237 TB, Requires<[HasSSE2]>;
3239 // Load, store, and memory fence
3240 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3241 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3242 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3243 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3244 def : Pat<(X86LFence), (LFENCE)>;
3245 def : Pat<(X86MFence), (MFENCE)>;
3248 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3249 // was introduced with SSE2, it's backward compatible.
3250 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3252 // Alias instructions that map zero vector to pxor / xorp* for sse.
3253 // We set canFoldAsLoad because this can be converted to a constant-pool
3254 // load of an all-ones value if folding it would be beneficial.
3255 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3256 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3257 // FIXME: Change encoding to pseudo.
3258 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3259 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3261 //===---------------------------------------------------------------------===//
3262 // SSE3 - Conversion Instructions
3263 //===---------------------------------------------------------------------===//
3265 // Convert Packed Double FP to Packed DW Integers
3266 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3267 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3268 // register, but the same isn't true when using memory operands instead.
3269 // Provide other assembly rr and rm forms to address this explicitly.
3270 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3271 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3272 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3273 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3276 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3277 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3278 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3279 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3282 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3283 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3284 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3285 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3288 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3289 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3290 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3291 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3293 // Convert Packed DW Integers to Packed Double FP
3294 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3295 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3296 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3297 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3298 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3299 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3300 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3301 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3302 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3305 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3306 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3307 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3308 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3310 // AVX 256-bit register conversion intrinsics
3311 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3312 (VCVTDQ2PDYrr VR128:$src)>;
3313 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3314 (VCVTDQ2PDYrm addr:$src)>;
3316 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3317 (VCVTPD2DQYrr VR256:$src)>;
3318 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3319 (VCVTPD2DQYrm addr:$src)>;
3321 //===---------------------------------------------------------------------===//
3322 // SSE3 - Move Instructions
3323 //===---------------------------------------------------------------------===//
3325 // Replicate Single FP
3326 multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
3327 def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3328 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3329 [(set VR128:$dst, (v4f32 (rep_frag
3330 VR128:$src, (undef))))]>;
3331 def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3332 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3333 [(set VR128:$dst, (rep_frag
3334 (memopv4f32 addr:$src), (undef)))]>;
3337 multiclass sse3_replicate_sfp_y<bits<8> op, PatFrag rep_frag,
3339 def rr : S3SI<op, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3340 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3341 def rm : S3SI<op, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3342 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3345 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3346 // FIXME: Merge above classes when we have patterns for the ymm version
3347 defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
3348 defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
3349 defm VMOVSHDUPY : sse3_replicate_sfp_y<0x16, movshdup, "vmovshdup">, VEX;
3350 defm VMOVSLDUPY : sse3_replicate_sfp_y<0x12, movsldup, "vmovsldup">, VEX;
3352 defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
3353 defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
3355 // Replicate Double FP
3356 multiclass sse3_replicate_dfp<string OpcodeStr> {
3357 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3358 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3359 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3360 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3361 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3363 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3367 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3368 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3369 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3371 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3376 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3377 // FIXME: Merge above classes when we have patterns for the ymm version
3378 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3379 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3381 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3383 // Move Unaligned Integer
3384 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3385 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3386 "vlddqu\t{$src, $dst|$dst, $src}",
3387 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3388 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3389 "vlddqu\t{$src, $dst|$dst, $src}",
3390 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
3392 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3393 "lddqu\t{$src, $dst|$dst, $src}",
3394 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3396 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3398 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3400 // Several Move patterns
3401 let AddedComplexity = 5 in {
3402 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3403 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3404 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3405 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3406 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3407 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3408 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3409 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3412 // vector_shuffle v1, <undef> <1, 1, 3, 3>
3413 let AddedComplexity = 15 in
3414 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
3415 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3416 let AddedComplexity = 20 in
3417 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3418 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
3420 // vector_shuffle v1, <undef> <0, 0, 2, 2>
3421 let AddedComplexity = 15 in
3422 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
3423 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3424 let AddedComplexity = 20 in
3425 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3426 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
3428 //===---------------------------------------------------------------------===//
3429 // SSE3 - Arithmetic
3430 //===---------------------------------------------------------------------===//
3432 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3433 X86MemOperand x86memop, bit Is2Addr = 1> {
3434 def rr : I<0xD0, MRMSrcReg,
3435 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3437 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3438 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3439 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3440 def rm : I<0xD0, MRMSrcMem,
3441 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3443 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3444 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3445 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3448 let isAsmParserOnly = 1, Predicates = [HasAVX],
3449 ExeDomain = SSEPackedDouble in {
3450 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3451 f128mem, 0>, XD, VEX_4V;
3452 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3453 f128mem, 0>, OpSize, VEX_4V;
3454 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3455 f256mem, 0>, XD, VEX_4V;
3456 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3457 f256mem, 0>, OpSize, VEX_4V;
3459 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3460 ExeDomain = SSEPackedDouble in {
3461 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3463 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3464 f128mem>, TB, OpSize;
3467 //===---------------------------------------------------------------------===//
3468 // SSE3 Instructions
3469 //===---------------------------------------------------------------------===//
3472 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3473 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3474 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3476 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3477 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3478 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3480 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3482 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3483 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3484 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3486 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3487 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3488 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3490 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3491 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3492 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3494 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3496 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3497 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3498 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3501 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3502 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3503 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3504 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3505 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3506 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3507 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3508 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3509 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3510 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3511 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3512 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3513 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3514 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3515 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3516 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3517 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3520 let Constraints = "$src1 = $dst" in {
3521 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3522 int_x86_sse3_hadd_ps>;
3523 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3524 int_x86_sse3_hadd_pd>;
3525 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3526 int_x86_sse3_hsub_ps>;
3527 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3528 int_x86_sse3_hsub_pd>;
3531 //===---------------------------------------------------------------------===//
3532 // SSSE3 - Packed Absolute Instructions
3533 //===---------------------------------------------------------------------===//
3535 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3536 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3537 PatFrag mem_frag64, PatFrag mem_frag128,
3538 Intrinsic IntId64, Intrinsic IntId128> {
3539 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
3540 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3541 [(set VR64:$dst, (IntId64 VR64:$src))]>;
3543 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
3544 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3546 (IntId64 (bitconvert (mem_frag64 addr:$src))))]>;
3548 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3550 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3551 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3554 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3556 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3559 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3562 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3563 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv8i8, memopv16i8,
3564 int_x86_ssse3_pabs_b,
3565 int_x86_ssse3_pabs_b_128>, VEX;
3566 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv4i16, memopv8i16,
3567 int_x86_ssse3_pabs_w,
3568 int_x86_ssse3_pabs_w_128>, VEX;
3569 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv2i32, memopv4i32,
3570 int_x86_ssse3_pabs_d,
3571 int_x86_ssse3_pabs_d_128>, VEX;
3574 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv8i8, memopv16i8,
3575 int_x86_ssse3_pabs_b,
3576 int_x86_ssse3_pabs_b_128>;
3577 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv4i16, memopv8i16,
3578 int_x86_ssse3_pabs_w,
3579 int_x86_ssse3_pabs_w_128>;
3580 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv2i32, memopv4i32,
3581 int_x86_ssse3_pabs_d,
3582 int_x86_ssse3_pabs_d_128>;
3584 //===---------------------------------------------------------------------===//
3585 // SSSE3 - Packed Binary Operator Instructions
3586 //===---------------------------------------------------------------------===//
3588 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3589 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3590 PatFrag mem_frag64, PatFrag mem_frag128,
3591 Intrinsic IntId64, Intrinsic IntId128,
3593 let isCommutable = 1 in
3594 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3595 (ins VR64:$src1, VR64:$src2),
3597 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3598 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3599 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
3600 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3601 (ins VR64:$src1, i64mem:$src2),
3603 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3604 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3606 (IntId64 VR64:$src1,
3607 (bitconvert (memopv8i8 addr:$src2))))]>;
3609 let isCommutable = 1 in
3610 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3611 (ins VR128:$src1, VR128:$src2),
3613 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3614 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3615 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3617 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3618 (ins VR128:$src1, i128mem:$src2),
3620 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3621 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3623 (IntId128 VR128:$src1,
3624 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3627 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3628 let isCommutable = 0 in {
3629 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv4i16, memopv8i16,
3630 int_x86_ssse3_phadd_w,
3631 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3632 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv2i32, memopv4i32,
3633 int_x86_ssse3_phadd_d,
3634 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3635 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv4i16, memopv8i16,
3636 int_x86_ssse3_phadd_sw,
3637 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3638 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv4i16, memopv8i16,
3639 int_x86_ssse3_phsub_w,
3640 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3641 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv2i32, memopv4i32,
3642 int_x86_ssse3_phsub_d,
3643 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3644 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv4i16, memopv8i16,
3645 int_x86_ssse3_phsub_sw,
3646 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3647 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv8i8, memopv16i8,
3648 int_x86_ssse3_pmadd_ub_sw,
3649 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3650 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv8i8, memopv16i8,
3651 int_x86_ssse3_pshuf_b,
3652 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3653 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv8i8, memopv16i8,
3654 int_x86_ssse3_psign_b,
3655 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3656 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv4i16, memopv8i16,
3657 int_x86_ssse3_psign_w,
3658 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3659 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv2i32, memopv4i32,
3660 int_x86_ssse3_psign_d,
3661 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3663 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv4i16, memopv8i16,
3664 int_x86_ssse3_pmul_hr_sw,
3665 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3668 // None of these have i8 immediate fields.
3669 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3670 let isCommutable = 0 in {
3671 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv4i16, memopv8i16,
3672 int_x86_ssse3_phadd_w,
3673 int_x86_ssse3_phadd_w_128>;
3674 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv2i32, memopv4i32,
3675 int_x86_ssse3_phadd_d,
3676 int_x86_ssse3_phadd_d_128>;
3677 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv4i16, memopv8i16,
3678 int_x86_ssse3_phadd_sw,
3679 int_x86_ssse3_phadd_sw_128>;
3680 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv4i16, memopv8i16,
3681 int_x86_ssse3_phsub_w,
3682 int_x86_ssse3_phsub_w_128>;
3683 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv2i32, memopv4i32,
3684 int_x86_ssse3_phsub_d,
3685 int_x86_ssse3_phsub_d_128>;
3686 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv4i16, memopv8i16,
3687 int_x86_ssse3_phsub_sw,
3688 int_x86_ssse3_phsub_sw_128>;
3689 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv8i8, memopv16i8,
3690 int_x86_ssse3_pmadd_ub_sw,
3691 int_x86_ssse3_pmadd_ub_sw_128>;
3692 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, memopv16i8,
3693 int_x86_ssse3_pshuf_b,
3694 int_x86_ssse3_pshuf_b_128>;
3695 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv8i8, memopv16i8,
3696 int_x86_ssse3_psign_b,
3697 int_x86_ssse3_psign_b_128>;
3698 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv4i16, memopv8i16,
3699 int_x86_ssse3_psign_w,
3700 int_x86_ssse3_psign_w_128>;
3701 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv2i32, memopv4i32,
3702 int_x86_ssse3_psign_d,
3703 int_x86_ssse3_psign_d_128>;
3705 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv4i16, memopv8i16,
3706 int_x86_ssse3_pmul_hr_sw,
3707 int_x86_ssse3_pmul_hr_sw_128>;
3710 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3711 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3712 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3713 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3715 //===---------------------------------------------------------------------===//
3716 // SSSE3 - Packed Align Instruction Patterns
3717 //===---------------------------------------------------------------------===//
3719 multiclass sse3_palign<string asm, bit Is2Addr = 1> {
3720 def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
3721 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
3723 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3725 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3727 def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
3728 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
3730 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3732 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3735 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3736 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3738 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3740 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3742 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3743 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3745 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3747 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3751 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3752 defm VPALIGN : sse3_palign<"vpalignr", 0>, VEX_4V;
3753 let Constraints = "$src1 = $dst" in
3754 defm PALIGN : sse3_palign<"palignr">;
3756 let AddedComplexity = 5 in {
3758 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
3759 (PALIGNR64rr VR64:$src2, VR64:$src1,
3760 (SHUFFLE_get_palign_imm VR64:$src3))>,
3761 Requires<[HasSSSE3]>;
3762 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
3763 (PALIGNR64rr VR64:$src2, VR64:$src1,
3764 (SHUFFLE_get_palign_imm VR64:$src3))>,
3765 Requires<[HasSSSE3]>;
3766 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
3767 (PALIGNR64rr VR64:$src2, VR64:$src1,
3768 (SHUFFLE_get_palign_imm VR64:$src3))>,
3769 Requires<[HasSSSE3]>;
3770 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
3771 (PALIGNR64rr VR64:$src2, VR64:$src1,
3772 (SHUFFLE_get_palign_imm VR64:$src3))>,
3773 Requires<[HasSSSE3]>;
3775 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3776 (PALIGNR128rr VR128:$src2, VR128:$src1,
3777 (SHUFFLE_get_palign_imm VR128:$src3))>,
3778 Requires<[HasSSSE3]>;
3779 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3780 (PALIGNR128rr VR128:$src2, VR128:$src1,
3781 (SHUFFLE_get_palign_imm VR128:$src3))>,
3782 Requires<[HasSSSE3]>;
3783 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3784 (PALIGNR128rr VR128:$src2, VR128:$src1,
3785 (SHUFFLE_get_palign_imm VR128:$src3))>,
3786 Requires<[HasSSSE3]>;
3787 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3788 (PALIGNR128rr VR128:$src2, VR128:$src1,
3789 (SHUFFLE_get_palign_imm VR128:$src3))>,
3790 Requires<[HasSSSE3]>;
3793 //===---------------------------------------------------------------------===//
3794 // SSSE3 Misc Instructions
3795 //===---------------------------------------------------------------------===//
3797 // Thread synchronization
3798 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
3799 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
3800 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
3801 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
3803 //===---------------------------------------------------------------------===//
3804 // Non-Instruction Patterns
3805 //===---------------------------------------------------------------------===//
3807 // extload f32 -> f64. This matches load+fextend because we have a hack in
3808 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3810 // Since these loads aren't folded into the fextend, we have to match it
3812 let Predicates = [HasSSE2] in
3813 def : Pat<(fextend (loadf32 addr:$src)),
3814 (CVTSS2SDrm addr:$src)>;
3817 let Predicates = [HasSSE2] in {
3818 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3819 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3820 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3821 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3822 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3823 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3824 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3825 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3826 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3827 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3828 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3829 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3830 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3831 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3832 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3833 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3834 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3835 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3836 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3837 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3838 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3839 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3840 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3841 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3842 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3843 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3844 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3845 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3846 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3847 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3850 // Move scalar to XMM zero-extended
3851 // movd to XMM register zero-extends
3852 let AddedComplexity = 15 in {
3853 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3854 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3855 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3856 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3857 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3858 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3859 (MOVSSrr (v4f32 (V_SET0PS)),
3860 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3861 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3862 (MOVSSrr (v4i32 (V_SET0PI)),
3863 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3866 // Splat v2f64 / v2i64
3867 let AddedComplexity = 10 in {
3868 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3869 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3870 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3871 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3872 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3873 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3874 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3875 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3878 // Special unary SHUFPSrri case.
3879 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3880 (SHUFPSrri VR128:$src1, VR128:$src1,
3881 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3882 let AddedComplexity = 5 in
3883 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3884 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3885 Requires<[HasSSE2]>;
3886 // Special unary SHUFPDrri case.
3887 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3888 (SHUFPDrri VR128:$src1, VR128:$src1,
3889 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3890 Requires<[HasSSE2]>;
3891 // Special unary SHUFPDrri case.
3892 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3893 (SHUFPDrri VR128:$src1, VR128:$src1,
3894 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3895 Requires<[HasSSE2]>;
3896 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3897 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3898 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3899 Requires<[HasSSE2]>;
3901 // Special binary v4i32 shuffle cases with SHUFPS.
3902 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3903 (SHUFPSrri VR128:$src1, VR128:$src2,
3904 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3905 Requires<[HasSSE2]>;
3906 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3907 (SHUFPSrmi VR128:$src1, addr:$src2,
3908 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3909 Requires<[HasSSE2]>;
3910 // Special binary v2i64 shuffle cases using SHUFPDrri.
3911 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3912 (SHUFPDrri VR128:$src1, VR128:$src2,
3913 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3914 Requires<[HasSSE2]>;
3916 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3917 let AddedComplexity = 15 in {
3918 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3919 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3920 Requires<[OptForSpeed, HasSSE2]>;
3921 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3922 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3923 Requires<[OptForSpeed, HasSSE2]>;
3925 let AddedComplexity = 10 in {
3926 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3927 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3928 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3929 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3930 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3931 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3932 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3933 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3936 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3937 let AddedComplexity = 15 in {
3938 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3939 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3940 Requires<[OptForSpeed, HasSSE2]>;
3941 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3942 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3943 Requires<[OptForSpeed, HasSSE2]>;
3945 let AddedComplexity = 10 in {
3946 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3947 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3948 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3949 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3950 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3951 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3952 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3953 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3956 let AddedComplexity = 20 in {
3957 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3958 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3959 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3961 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3962 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3963 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3965 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3966 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3967 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3968 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3969 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3972 let AddedComplexity = 20 in {
3973 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3974 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3975 (MOVLPSrm VR128:$src1, addr:$src2)>;
3976 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3977 (MOVLPDrm VR128:$src1, addr:$src2)>;
3978 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3979 (MOVLPSrm VR128:$src1, addr:$src2)>;
3980 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3981 (MOVLPDrm VR128:$src1, addr:$src2)>;
3984 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3985 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3986 (MOVLPSmr addr:$src1, VR128:$src2)>;
3987 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3988 (MOVLPDmr addr:$src1, VR128:$src2)>;
3989 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3991 (MOVLPSmr addr:$src1, VR128:$src2)>;
3992 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3993 (MOVLPDmr addr:$src1, VR128:$src2)>;
3995 let AddedComplexity = 15 in {
3996 // Setting the lowest element in the vector.
3997 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3998 (MOVSSrr (v4i32 VR128:$src1),
3999 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
4000 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
4001 (MOVSDrr (v2i64 VR128:$src1),
4002 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
4004 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
4005 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
4006 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
4007 Requires<[HasSSE2]>;
4008 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
4009 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
4010 Requires<[HasSSE2]>;
4013 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
4014 // fall back to this for SSE1)
4015 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
4016 (SHUFPSrri VR128:$src2, VR128:$src1,
4017 (SHUFFLE_get_shuf_imm VR128:$src3))>;
4019 // Set lowest element and zero upper elements.
4020 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4021 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
4023 // Some special case pandn patterns.
4024 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
4026 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
4027 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
4029 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
4030 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
4032 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
4034 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
4035 (memop addr:$src2))),
4036 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
4037 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
4038 (memop addr:$src2))),
4039 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
4040 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
4041 (memop addr:$src2))),
4042 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
4044 // vector -> vector casts
4045 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
4046 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
4047 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
4048 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
4049 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
4050 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
4051 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
4052 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
4054 // Use movaps / movups for SSE integer load / store (one byte shorter).
4055 def : Pat<(alignedloadv4i32 addr:$src),
4056 (MOVAPSrm addr:$src)>;
4057 def : Pat<(loadv4i32 addr:$src),
4058 (MOVUPSrm addr:$src)>;
4059 def : Pat<(alignedloadv2i64 addr:$src),
4060 (MOVAPSrm addr:$src)>;
4061 def : Pat<(loadv2i64 addr:$src),
4062 (MOVUPSrm addr:$src)>;
4064 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4065 (MOVAPSmr addr:$dst, VR128:$src)>;
4066 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4067 (MOVAPSmr addr:$dst, VR128:$src)>;
4068 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4069 (MOVAPSmr addr:$dst, VR128:$src)>;
4070 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4071 (MOVAPSmr addr:$dst, VR128:$src)>;
4072 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4073 (MOVUPSmr addr:$dst, VR128:$src)>;
4074 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4075 (MOVUPSmr addr:$dst, VR128:$src)>;
4076 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4077 (MOVUPSmr addr:$dst, VR128:$src)>;
4078 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4079 (MOVUPSmr addr:$dst, VR128:$src)>;
4081 //===----------------------------------------------------------------------===//
4082 // SSE4.1 - Packed Move with Sign/Zero Extend
4083 //===----------------------------------------------------------------------===//
4085 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4086 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4087 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4088 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4090 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4091 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4093 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
4097 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4098 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
4100 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
4102 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
4104 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
4106 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
4108 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
4112 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4113 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4114 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4115 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4116 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4117 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4119 // Common patterns involving scalar load.
4120 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4121 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4122 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4123 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4125 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4126 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4127 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4128 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4130 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4131 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4132 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4133 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4135 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4136 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4137 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4138 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4140 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4141 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4142 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4143 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4145 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4146 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4147 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4148 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4151 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4152 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4153 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4154 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4156 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4157 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4159 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4163 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4164 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
4166 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
4168 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
4170 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
4174 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4175 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4176 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4177 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4179 // Common patterns involving scalar load
4180 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4181 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4182 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4183 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4185 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4186 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4187 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4188 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4191 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4192 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4193 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4194 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4196 // Expecting a i16 load any extended to i32 value.
4197 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4198 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4199 [(set VR128:$dst, (IntId (bitconvert
4200 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4204 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4205 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4207 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4210 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4211 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4213 // Common patterns involving scalar load
4214 def : Pat<(int_x86_sse41_pmovsxbq
4215 (bitconvert (v4i32 (X86vzmovl
4216 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4217 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4219 def : Pat<(int_x86_sse41_pmovzxbq
4220 (bitconvert (v4i32 (X86vzmovl
4221 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4222 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4224 //===----------------------------------------------------------------------===//
4225 // SSE4.1 - Extract Instructions
4226 //===----------------------------------------------------------------------===//
4228 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4229 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4230 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4231 (ins VR128:$src1, i32i8imm:$src2),
4232 !strconcat(OpcodeStr,
4233 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4234 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4236 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4237 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4238 !strconcat(OpcodeStr,
4239 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4242 // There's an AssertZext in the way of writing the store pattern
4243 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4246 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4247 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4248 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4249 (ins VR128:$src1, i32i8imm:$src2),
4250 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4253 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4256 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4257 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4258 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4259 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4260 !strconcat(OpcodeStr,
4261 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4264 // There's an AssertZext in the way of writing the store pattern
4265 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4268 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4269 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4271 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4274 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4275 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4276 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4277 (ins VR128:$src1, i32i8imm:$src2),
4278 !strconcat(OpcodeStr,
4279 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4281 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4282 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4283 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4284 !strconcat(OpcodeStr,
4285 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4286 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4287 addr:$dst)]>, OpSize;
4290 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4291 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4293 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4295 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4296 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4297 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4298 (ins VR128:$src1, i32i8imm:$src2),
4299 !strconcat(OpcodeStr,
4300 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4302 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4303 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4304 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4305 !strconcat(OpcodeStr,
4306 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4307 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4308 addr:$dst)]>, OpSize, REX_W;
4311 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4312 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4314 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4316 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4318 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4319 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4320 (ins VR128:$src1, i32i8imm:$src2),
4321 !strconcat(OpcodeStr,
4322 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4324 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4326 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4327 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4328 !strconcat(OpcodeStr,
4329 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4330 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4331 addr:$dst)]>, OpSize;
4334 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4335 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4336 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4337 (ins VR128:$src1, i32i8imm:$src2),
4338 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4341 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4343 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4344 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4347 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4348 Requires<[HasSSE41]>;
4350 //===----------------------------------------------------------------------===//
4351 // SSE4.1 - Insert Instructions
4352 //===----------------------------------------------------------------------===//
4354 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4355 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4356 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4358 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4360 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4362 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4363 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4364 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4366 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4368 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4370 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4371 imm:$src3))]>, OpSize;
4374 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4375 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4376 let Constraints = "$src1 = $dst" in
4377 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4379 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4380 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4381 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4383 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4385 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4387 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4389 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4390 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4392 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4394 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4396 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4397 imm:$src3)))]>, OpSize;
4400 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4401 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4402 let Constraints = "$src1 = $dst" in
4403 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4405 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4406 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4407 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4409 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4411 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4413 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4415 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4416 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4418 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4420 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4422 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4423 imm:$src3)))]>, OpSize;
4426 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4427 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4428 let Constraints = "$src1 = $dst" in
4429 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4431 // insertps has a few different modes, there's the first two here below which
4432 // are optimized inserts that won't zero arbitrary elements in the destination
4433 // vector. The next one matches the intrinsic and could zero arbitrary elements
4434 // in the target vector.
4435 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4436 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4437 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4439 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4441 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4443 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4445 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4446 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
4448 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4450 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4452 (X86insrtps VR128:$src1,
4453 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4454 imm:$src3))]>, OpSize;
4457 let Constraints = "$src1 = $dst" in
4458 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4459 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4460 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4462 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4463 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4465 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4466 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4467 Requires<[HasSSE41]>;
4469 //===----------------------------------------------------------------------===//
4470 // SSE4.1 - Round Instructions
4471 //===----------------------------------------------------------------------===//
4473 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4474 X86MemOperand x86memop, RegisterClass RC,
4475 PatFrag mem_frag32, PatFrag mem_frag64,
4476 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4477 // Intrinsic operation, reg.
4478 // Vector intrinsic operation, reg
4479 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
4480 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4481 !strconcat(OpcodeStr,
4482 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4483 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4486 // Vector intrinsic operation, mem
4487 def PSm_Int : Ii8<opcps, MRMSrcMem,
4488 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4489 !strconcat(OpcodeStr,
4490 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4492 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4494 Requires<[HasSSE41]>;
4496 // Vector intrinsic operation, reg
4497 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
4498 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4499 !strconcat(OpcodeStr,
4500 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4501 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4504 // Vector intrinsic operation, mem
4505 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
4506 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4507 !strconcat(OpcodeStr,
4508 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4510 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4514 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4515 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4516 // Intrinsic operation, reg.
4517 // Vector intrinsic operation, reg
4518 def PSr : SS4AIi8<opcps, MRMSrcReg,
4519 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4520 !strconcat(OpcodeStr,
4521 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4524 // Vector intrinsic operation, mem
4525 def PSm : Ii8<opcps, MRMSrcMem,
4526 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4527 !strconcat(OpcodeStr,
4528 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4529 []>, TA, OpSize, Requires<[HasSSE41]>;
4531 // Vector intrinsic operation, reg
4532 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4533 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4534 !strconcat(OpcodeStr,
4535 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4538 // Vector intrinsic operation, mem
4539 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4540 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4541 !strconcat(OpcodeStr,
4542 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4546 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4549 Intrinsic F64Int, bit Is2Addr = 1> {
4550 // Intrinsic operation, reg.
4551 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
4552 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4554 !strconcat(OpcodeStr,
4555 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4556 !strconcat(OpcodeStr,
4557 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4558 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4561 // Intrinsic operation, mem.
4562 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
4563 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4565 !strconcat(OpcodeStr,
4566 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4567 !strconcat(OpcodeStr,
4568 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4570 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4573 // Intrinsic operation, reg.
4574 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
4575 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4577 !strconcat(OpcodeStr,
4578 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4579 !strconcat(OpcodeStr,
4580 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4581 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4584 // Intrinsic operation, mem.
4585 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
4586 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4588 !strconcat(OpcodeStr,
4589 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4590 !strconcat(OpcodeStr,
4591 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4593 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4597 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4599 // Intrinsic operation, reg.
4600 def SSr : SS4AIi8<opcss, MRMSrcReg,
4601 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4602 !strconcat(OpcodeStr,
4603 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4606 // Intrinsic operation, mem.
4607 def SSm : SS4AIi8<opcss, MRMSrcMem,
4608 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4609 !strconcat(OpcodeStr,
4610 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4613 // Intrinsic operation, reg.
4614 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4615 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4616 !strconcat(OpcodeStr,
4617 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4620 // Intrinsic operation, mem.
4621 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4622 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4623 !strconcat(OpcodeStr,
4624 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4628 // FP round - roundss, roundps, roundsd, roundpd
4629 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4631 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4632 memopv4f32, memopv2f64,
4633 int_x86_sse41_round_ps,
4634 int_x86_sse41_round_pd>, VEX;
4635 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4636 memopv8f32, memopv4f64,
4637 int_x86_avx_round_ps_256,
4638 int_x86_avx_round_pd_256>, VEX;
4639 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4640 int_x86_sse41_round_ss,
4641 int_x86_sse41_round_sd, 0>, VEX_4V;
4643 // Instructions for the assembler
4644 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4646 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4648 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4651 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4652 memopv4f32, memopv2f64,
4653 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4654 let Constraints = "$src1 = $dst" in
4655 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4656 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4658 //===----------------------------------------------------------------------===//
4659 // SSE4.1 - Packed Bit Test
4660 //===----------------------------------------------------------------------===//
4662 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4663 // the intel intrinsic that corresponds to this.
4664 let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
4665 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4666 "vptest\t{$src2, $src1|$src1, $src2}",
4667 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4669 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4670 "vptest\t{$src2, $src1|$src1, $src2}",
4671 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4674 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4675 "vptest\t{$src2, $src1|$src1, $src2}",
4676 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
4678 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4679 "vptest\t{$src2, $src1|$src1, $src2}",
4680 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
4684 let Defs = [EFLAGS] in {
4685 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4686 "ptest \t{$src2, $src1|$src1, $src2}",
4687 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4689 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4690 "ptest \t{$src2, $src1|$src1, $src2}",
4691 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4695 // The bit test instructions below are AVX only
4696 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4697 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
4698 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
4699 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4700 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
4701 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
4702 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4703 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
4707 let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
4708 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
4709 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
4710 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
4711 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
4714 //===----------------------------------------------------------------------===//
4715 // SSE4.1 - Misc Instructions
4716 //===----------------------------------------------------------------------===//
4718 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4719 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4720 Intrinsic IntId128> {
4721 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4723 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4724 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4725 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4727 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4730 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4733 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4734 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4735 int_x86_sse41_phminposuw>, VEX;
4736 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4737 int_x86_sse41_phminposuw>;
4739 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4740 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4741 Intrinsic IntId128, bit Is2Addr = 1> {
4742 let isCommutable = 1 in
4743 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4744 (ins VR128:$src1, VR128:$src2),
4746 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4747 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4748 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4749 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4750 (ins VR128:$src1, i128mem:$src2),
4752 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4753 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4755 (IntId128 VR128:$src1,
4756 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4759 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4760 let isCommutable = 0 in
4761 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4763 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4765 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4767 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4769 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4771 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4773 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4775 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4777 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4779 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4781 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4785 let Constraints = "$src1 = $dst" in {
4786 let isCommutable = 0 in
4787 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4788 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4789 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4790 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4791 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4792 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4793 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4794 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4795 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4796 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4797 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4800 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4801 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4802 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4803 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4805 /// SS48I_binop_rm - Simple SSE41 binary operator.
4806 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4807 ValueType OpVT, bit Is2Addr = 1> {
4808 let isCommutable = 1 in
4809 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4810 (ins VR128:$src1, VR128:$src2),
4812 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4813 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4814 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4816 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4817 (ins VR128:$src1, i128mem:$src2),
4819 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4820 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4821 [(set VR128:$dst, (OpNode VR128:$src1,
4822 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4826 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4827 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4828 let Constraints = "$src1 = $dst" in
4829 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4831 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4832 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4833 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4834 X86MemOperand x86memop, bit Is2Addr = 1> {
4835 let isCommutable = 1 in
4836 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4837 (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4839 !strconcat(OpcodeStr,
4840 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4841 !strconcat(OpcodeStr,
4842 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4843 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4845 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4846 (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4848 !strconcat(OpcodeStr,
4849 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4850 !strconcat(OpcodeStr,
4851 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4854 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4858 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4859 let isCommutable = 0 in {
4860 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4861 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4862 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4863 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4864 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
4865 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4866 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
4867 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4868 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4869 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4870 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4871 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4873 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4874 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4875 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4876 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4877 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
4878 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4881 let Constraints = "$src1 = $dst" in {
4882 let isCommutable = 0 in {
4883 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4884 VR128, memopv16i8, i128mem>;
4885 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4886 VR128, memopv16i8, i128mem>;
4887 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4888 VR128, memopv16i8, i128mem>;
4889 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4890 VR128, memopv16i8, i128mem>;
4892 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4893 VR128, memopv16i8, i128mem>;
4894 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4895 VR128, memopv16i8, i128mem>;
4898 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4899 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4900 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4901 RegisterClass RC, X86MemOperand x86memop,
4902 PatFrag mem_frag, Intrinsic IntId> {
4903 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4904 (ins RC:$src1, RC:$src2, RC:$src3),
4905 !strconcat(OpcodeStr,
4906 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4907 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4908 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4910 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4911 (ins RC:$src1, x86memop:$src2, RC:$src3),
4912 !strconcat(OpcodeStr,
4913 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4915 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
4917 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4921 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
4922 memopv16i8, int_x86_sse41_blendvpd>;
4923 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
4924 memopv16i8, int_x86_sse41_blendvps>;
4925 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
4926 memopv16i8, int_x86_sse41_pblendvb>;
4927 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
4928 memopv32i8, int_x86_avx_blendv_pd_256>;
4929 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
4930 memopv32i8, int_x86_avx_blendv_ps_256>;
4932 /// SS41I_ternary_int - SSE 4.1 ternary operator
4933 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4934 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4935 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4936 (ins VR128:$src1, VR128:$src2),
4937 !strconcat(OpcodeStr,
4938 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
4939 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4942 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4943 (ins VR128:$src1, i128mem:$src2),
4944 !strconcat(OpcodeStr,
4945 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
4948 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4952 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4953 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4954 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4956 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4957 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4958 "vmovntdqa\t{$src, $dst|$dst, $src}",
4959 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4961 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4962 "movntdqa\t{$src, $dst|$dst, $src}",
4963 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4966 //===----------------------------------------------------------------------===//
4967 // SSE4.2 - Compare Instructions
4968 //===----------------------------------------------------------------------===//
4970 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4971 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4972 Intrinsic IntId128, bit Is2Addr = 1> {
4973 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4974 (ins VR128:$src1, VR128:$src2),
4976 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4977 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4978 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4980 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4981 (ins VR128:$src1, i128mem:$src2),
4983 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4984 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4986 (IntId128 VR128:$src1,
4987 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4990 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4991 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
4993 let Constraints = "$src1 = $dst" in
4994 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4996 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4997 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4998 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4999 (PCMPGTQrm VR128:$src1, addr:$src2)>;
5001 //===----------------------------------------------------------------------===//
5002 // SSE4.2 - String/text Processing Instructions
5003 //===----------------------------------------------------------------------===//
5005 // Packed Compare Implicit Length Strings, Return Mask
5006 multiclass pseudo_pcmpistrm<string asm> {
5007 def REG : Ii8<0, Pseudo, (outs VR128:$dst),
5008 (ins VR128:$src1, VR128:$src2, i8imm:$src3), !strconcat(asm, "rr PSEUDO"),
5009 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
5011 def MEM : Ii8<0, Pseudo, (outs VR128:$dst),
5012 (ins VR128:$src1, i128mem:$src2, i8imm:$src3), !strconcat(asm, "rm PSEUDO"),
5013 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
5014 VR128:$src1, (load addr:$src2), imm:$src3))]>;
5017 let Defs = [EFLAGS], usesCustomInserter = 1 in {
5018 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
5019 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
5022 let Defs = [XMM0, EFLAGS], isAsmParserOnly = 1,
5023 Predicates = [HasAVX] in {
5024 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5025 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5026 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5027 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5028 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5029 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5032 let Defs = [XMM0, EFLAGS] in {
5033 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5034 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5035 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5036 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5037 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5038 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5041 // Packed Compare Explicit Length Strings, Return Mask
5042 multiclass pseudo_pcmpestrm<string asm> {
5043 def REG : Ii8<0, Pseudo, (outs VR128:$dst),
5044 (ins VR128:$src1, VR128:$src3, i8imm:$src5), !strconcat(asm, "rr PSEUDO"),
5045 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5046 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
5047 def MEM : Ii8<0, Pseudo, (outs VR128:$dst),
5048 (ins VR128:$src1, i128mem:$src3, i8imm:$src5), !strconcat(asm, "rm PSEUDO"),
5049 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5050 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
5053 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
5054 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
5055 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
5058 let isAsmParserOnly = 1, Predicates = [HasAVX],
5059 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5060 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5061 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5062 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5063 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5064 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5065 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5068 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5069 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5070 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5071 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5072 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5073 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5074 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5077 // Packed Compare Implicit Length Strings, Return Index
5078 let Defs = [ECX, EFLAGS] in {
5079 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
5080 def rr : SS42AI<0x63, MRMSrcReg, (outs),
5081 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5082 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5083 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
5084 (implicit EFLAGS)]>, OpSize;
5085 def rm : SS42AI<0x63, MRMSrcMem, (outs),
5086 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5087 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5088 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
5089 (implicit EFLAGS)]>, OpSize;
5093 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
5094 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
5096 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
5098 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
5100 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
5102 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
5104 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
5108 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
5109 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
5110 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
5111 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
5112 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
5113 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
5115 // Packed Compare Explicit Length Strings, Return Index
5116 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
5117 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
5118 def rr : SS42AI<0x61, MRMSrcReg, (outs),
5119 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5120 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5121 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
5122 (implicit EFLAGS)]>, OpSize;
5123 def rm : SS42AI<0x61, MRMSrcMem, (outs),
5124 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5125 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5127 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
5128 (implicit EFLAGS)]>, OpSize;
5132 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
5133 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
5135 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
5137 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
5139 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
5141 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
5143 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
5147 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
5148 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
5149 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
5150 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
5151 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
5152 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
5154 //===----------------------------------------------------------------------===//
5155 // SSE4.2 - CRC Instructions
5156 //===----------------------------------------------------------------------===//
5158 // No CRC instructions have AVX equivalents
5160 // crc intrinsic instruction
5161 // This set of instructions are only rm, the only difference is the size
5163 let Constraints = "$src1 = $dst" in {
5164 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5165 (ins GR32:$src1, i8mem:$src2),
5166 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5168 (int_x86_sse42_crc32_8 GR32:$src1,
5169 (load addr:$src2)))]>;
5170 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5171 (ins GR32:$src1, GR8:$src2),
5172 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5174 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
5175 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5176 (ins GR32:$src1, i16mem:$src2),
5177 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5179 (int_x86_sse42_crc32_16 GR32:$src1,
5180 (load addr:$src2)))]>,
5182 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5183 (ins GR32:$src1, GR16:$src2),
5184 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5186 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
5188 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5189 (ins GR32:$src1, i32mem:$src2),
5190 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5192 (int_x86_sse42_crc32_32 GR32:$src1,
5193 (load addr:$src2)))]>;
5194 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5195 (ins GR32:$src1, GR32:$src2),
5196 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5198 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
5199 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5200 (ins GR64:$src1, i8mem:$src2),
5201 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5203 (int_x86_sse42_crc64_8 GR64:$src1,
5204 (load addr:$src2)))]>,
5206 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5207 (ins GR64:$src1, GR8:$src2),
5208 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5210 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
5212 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5213 (ins GR64:$src1, i64mem:$src2),
5214 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5216 (int_x86_sse42_crc64_64 GR64:$src1,
5217 (load addr:$src2)))]>,
5219 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5220 (ins GR64:$src1, GR64:$src2),
5221 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5223 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
5227 //===----------------------------------------------------------------------===//
5228 // AES-NI Instructions
5229 //===----------------------------------------------------------------------===//
5231 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5232 Intrinsic IntId128, bit Is2Addr = 1> {
5233 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5234 (ins VR128:$src1, VR128:$src2),
5236 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5237 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5238 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5240 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5241 (ins VR128:$src1, i128mem:$src2),
5243 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5244 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5246 (IntId128 VR128:$src1,
5247 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5250 // Perform One Round of an AES Encryption/Decryption Flow
5251 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
5252 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5253 int_x86_aesni_aesenc, 0>, VEX_4V;
5254 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5255 int_x86_aesni_aesenclast, 0>, VEX_4V;
5256 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5257 int_x86_aesni_aesdec, 0>, VEX_4V;
5258 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5259 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5262 let Constraints = "$src1 = $dst" in {
5263 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5264 int_x86_aesni_aesenc>;
5265 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5266 int_x86_aesni_aesenclast>;
5267 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5268 int_x86_aesni_aesdec>;
5269 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5270 int_x86_aesni_aesdeclast>;
5273 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5274 (AESENCrr VR128:$src1, VR128:$src2)>;
5275 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5276 (AESENCrm VR128:$src1, addr:$src2)>;
5277 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5278 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5279 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5280 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5281 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5282 (AESDECrr VR128:$src1, VR128:$src2)>;
5283 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5284 (AESDECrm VR128:$src1, addr:$src2)>;
5285 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5286 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5287 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5288 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5290 // Perform the AES InvMixColumn Transformation
5291 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
5292 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5294 "vaesimc\t{$src1, $dst|$dst, $src1}",
5296 (int_x86_aesni_aesimc VR128:$src1))]>,
5298 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5299 (ins i128mem:$src1),
5300 "vaesimc\t{$src1, $dst|$dst, $src1}",
5302 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5305 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5307 "aesimc\t{$src1, $dst|$dst, $src1}",
5309 (int_x86_aesni_aesimc VR128:$src1))]>,
5311 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5312 (ins i128mem:$src1),
5313 "aesimc\t{$src1, $dst|$dst, $src1}",
5315 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5318 // AES Round Key Generation Assist
5319 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
5320 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5321 (ins VR128:$src1, i8imm:$src2),
5322 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5324 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5326 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5327 (ins i128mem:$src1, i8imm:$src2),
5328 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5330 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5334 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5335 (ins VR128:$src1, i8imm:$src2),
5336 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5338 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5340 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5341 (ins i128mem:$src1, i8imm:$src2),
5342 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5344 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5348 //===----------------------------------------------------------------------===//
5349 // CLMUL Instructions
5350 //===----------------------------------------------------------------------===//
5352 // Only the AVX version of CLMUL instructions are described here.
5354 // Carry-less Multiplication instructions
5355 let isAsmParserOnly = 1 in {
5356 def VPCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5357 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5358 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5361 def VPCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5362 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5363 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5367 multiclass avx_vpclmul<string asm> {
5368 def rr : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
5369 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5372 def rm : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
5373 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5376 defm VPCLMULHQHQDQ : avx_vpclmul<"vpclmulhqhqdq">;
5377 defm VPCLMULHQLQDQ : avx_vpclmul<"vpclmulhqlqdq">;
5378 defm VPCLMULLQHQDQ : avx_vpclmul<"vpclmullqhqdq">;
5379 defm VPCLMULLQLQDQ : avx_vpclmul<"vpclmullqlqdq">;
5381 } // isAsmParserOnly
5383 //===----------------------------------------------------------------------===//
5385 //===----------------------------------------------------------------------===//
5387 let isAsmParserOnly = 1 in {
5389 // Load from memory and broadcast to all elements of the destination operand
5390 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5391 X86MemOperand x86memop, Intrinsic Int> :
5392 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5393 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5394 [(set RC:$dst, (Int addr:$src))]>, VEX;
5396 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5397 int_x86_avx_vbroadcastss>;
5398 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5399 int_x86_avx_vbroadcastss_256>;
5400 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5401 int_x86_avx_vbroadcast_sd_256>;
5402 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5403 int_x86_avx_vbroadcastf128_pd_256>;
5405 // Insert packed floating-point values
5406 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5407 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5408 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5410 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5411 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5412 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5415 // Extract packed floating-point values
5416 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5417 (ins VR256:$src1, i8imm:$src2),
5418 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5420 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5421 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5422 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5425 // Conditional SIMD Packed Loads and Stores
5426 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
5427 Intrinsic IntLd, Intrinsic IntLd256,
5428 Intrinsic IntSt, Intrinsic IntSt256,
5429 PatFrag pf128, PatFrag pf256> {
5430 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5431 (ins VR128:$src1, f128mem:$src2),
5432 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5433 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
5435 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5436 (ins VR256:$src1, f256mem:$src2),
5437 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5438 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
5440 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5441 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5442 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5443 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
5444 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5445 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5446 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5447 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
5450 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
5451 int_x86_avx_maskload_ps,
5452 int_x86_avx_maskload_ps_256,
5453 int_x86_avx_maskstore_ps,
5454 int_x86_avx_maskstore_ps_256,
5455 memopv4f32, memopv8f32>;
5456 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
5457 int_x86_avx_maskload_pd,
5458 int_x86_avx_maskload_pd_256,
5459 int_x86_avx_maskstore_pd,
5460 int_x86_avx_maskstore_pd_256,
5461 memopv2f64, memopv4f64>;
5463 // Permute Floating-Point Values
5464 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5465 RegisterClass RC, X86MemOperand x86memop_f,
5466 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5467 Intrinsic IntVar, Intrinsic IntImm> {
5468 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5469 (ins RC:$src1, RC:$src2),
5470 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5471 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5472 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5473 (ins RC:$src1, x86memop_i:$src2),
5474 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5475 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5477 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5478 (ins RC:$src1, i8imm:$src2),
5479 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5480 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5481 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5482 (ins x86memop_f:$src1, i8imm:$src2),
5483 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5484 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5487 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5488 memopv4f32, memopv4i32,
5489 int_x86_avx_vpermilvar_ps,
5490 int_x86_avx_vpermil_ps>;
5491 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5492 memopv8f32, memopv8i32,
5493 int_x86_avx_vpermilvar_ps_256,
5494 int_x86_avx_vpermil_ps_256>;
5495 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5496 memopv2f64, memopv2i64,
5497 int_x86_avx_vpermilvar_pd,
5498 int_x86_avx_vpermil_pd>;
5499 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5500 memopv4f64, memopv4i64,
5501 int_x86_avx_vpermilvar_pd_256,
5502 int_x86_avx_vpermil_pd_256>;
5504 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5505 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5506 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5508 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5509 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5510 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5513 // Zero All YMM registers
5514 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
5515 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
5517 // Zero Upper bits of YMM registers
5518 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
5519 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
5521 } // isAsmParserOnly
5523 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5524 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5525 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5526 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5527 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5528 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5530 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
5531 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5532 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
5533 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5534 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
5535 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5537 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5538 (VBROADCASTF128 addr:$src)>;
5540 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5541 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5542 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5543 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5544 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5545 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5547 def : Pat<(int_x86_avx_vperm2f128_ps_256
5548 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5549 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5550 def : Pat<(int_x86_avx_vperm2f128_pd_256
5551 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5552 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5553 def : Pat<(int_x86_avx_vperm2f128_si_256
5554 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5555 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;