1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
246 let isCommutable = 1 in {
247 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
249 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
251 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
252 Sched<[itins.Sched]>;
254 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
256 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
257 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
258 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
259 Sched<[itins.Sched.Folded, ReadAfterLd]>;
262 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
263 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
264 string asm, string SSEVer, string FPSizeStr,
265 Operand memopr, ComplexPattern mem_cpat,
268 let isCodeGenOnly = 1 in {
269 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
271 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
272 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
273 [(set RC:$dst, (!cast<Intrinsic>(
274 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
275 RC:$src1, RC:$src2))], itins.rr>,
276 Sched<[itins.Sched]>;
277 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
279 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
280 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
281 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
282 SSEVer, "_", OpcodeStr, FPSizeStr))
283 RC:$src1, mem_cpat:$src2))], itins.rm>,
284 Sched<[itins.Sched.Folded, ReadAfterLd]>;
288 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
289 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
290 RegisterClass RC, ValueType vt,
291 X86MemOperand x86memop, PatFrag mem_frag,
292 Domain d, OpndItins itins, bit Is2Addr = 1> {
293 let isCommutable = 1 in
294 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
296 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
297 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
298 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
299 Sched<[itins.Sched]>;
301 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
305 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
307 Sched<[itins.Sched.Folded, ReadAfterLd]>;
310 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
311 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
312 string OpcodeStr, X86MemOperand x86memop,
313 list<dag> pat_rr, list<dag> pat_rm,
315 let isCommutable = 1, hasSideEffects = 0 in
316 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
320 pat_rr, NoItinerary, d>,
321 Sched<[WriteVecLogic]>;
322 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
324 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
325 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
326 pat_rm, NoItinerary, d>,
327 Sched<[WriteVecLogicLd, ReadAfterLd]>;
330 //===----------------------------------------------------------------------===//
331 // Non-instruction patterns
332 //===----------------------------------------------------------------------===//
334 // A vector extract of the first f32/f64 position is a subregister copy
335 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
337 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
338 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
340 // A 128-bit subvector extract from the first 256-bit vector position
341 // is a subregister copy that needs no instruction.
342 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
343 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
344 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
347 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
348 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
349 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
350 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
352 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
353 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
354 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
355 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
357 // A 128-bit subvector insert to the first 256-bit vector position
358 // is a subregister copy that needs no instruction.
359 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
360 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
370 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
371 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
374 // Implicitly promote a 32-bit scalar to a vector.
375 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
378 (COPY_TO_REGCLASS FR32:$src, VR128)>;
379 // Implicitly promote a 64-bit scalar to a vector.
380 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
382 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
383 (COPY_TO_REGCLASS FR64:$src, VR128)>;
385 // Bitcasts between 128-bit vector types. Return the original type since
386 // no instruction is needed for the conversion
387 let Predicates = [HasSSE2] in {
388 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
397 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
402 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
407 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
416 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
417 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
420 // Bitcasts between 256-bit vector types. Return the original type since
421 // no instruction is needed for the conversion
422 let Predicates = [HasAVX] in {
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
455 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
456 // This is expanded by ExpandPostRAPseudos.
457 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
458 isPseudo = 1, SchedRW = [WriteZero] in {
459 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
460 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
461 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
462 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
465 //===----------------------------------------------------------------------===//
466 // AVX & SSE - Zero/One Vectors
467 //===----------------------------------------------------------------------===//
469 // Alias instruction that maps zero vector to pxor / xorp* for sse.
470 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
471 // swizzled by ExecutionDepsFix to pxor.
472 // We set canFoldAsLoad because this can be converted to a constant-pool
473 // load of an all-zeros value if folding it would be beneficial.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
475 isPseudo = 1, SchedRW = [WriteZero] in {
476 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
477 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
480 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
482 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
483 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
484 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
487 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
488 // and doesn't need it because on sandy bridge the register is set to zero
489 // at the rename stage without using any execution unit, so SET0PSY
490 // and SET0PDY can be used for vector int instructions without penalty
491 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
492 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
493 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
494 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
497 let Predicates = [HasAVX] in
498 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
500 let Predicates = [HasAVX2] in {
501 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
503 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
504 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
507 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
508 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
509 let Predicates = [HasAVX1Only] in {
510 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
511 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
512 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
514 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
515 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
516 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
518 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
519 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
520 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
522 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
523 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
524 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
527 // We set canFoldAsLoad because this can be converted to a constant-pool
528 // load of an all-ones value if folding it would be beneficial.
529 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
530 isPseudo = 1, SchedRW = [WriteZero] in {
531 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
532 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
533 let Predicates = [HasAVX2] in
534 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
535 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
539 //===----------------------------------------------------------------------===//
540 // SSE 1 & 2 - Move FP Scalar Instructions
542 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
543 // register copies because it's a partial register update; Register-to-register
544 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
545 // that the insert be implementable in terms of a copy, and just mentioned, we
546 // don't use movss/movsd for copies.
547 //===----------------------------------------------------------------------===//
549 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
550 X86MemOperand x86memop, string base_opc,
551 string asm_opr, Domain d = GenericDomain> {
552 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
553 (ins VR128:$src1, RC:$src2),
554 !strconcat(base_opc, asm_opr),
555 [(set VR128:$dst, (vt (OpNode VR128:$src1,
556 (scalar_to_vector RC:$src2))))],
557 IIC_SSE_MOV_S_RR, d>, Sched<[WriteFShuffle]>;
559 // For the disassembler
560 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
561 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
562 (ins VR128:$src1, RC:$src2),
563 !strconcat(base_opc, asm_opr),
564 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
567 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
568 X86MemOperand x86memop, string OpcodeStr,
569 Domain d = GenericDomain> {
571 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
572 "\t{$src2, $src1, $dst|$dst, $src1, $src2}", d>,
575 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
576 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
577 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
578 VEX, VEX_LIG, Sched<[WriteStore]>;
580 let Constraints = "$src1 = $dst" in {
581 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
582 "\t{$src2, $dst|$dst, $src2}", d>;
585 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
586 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
587 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
591 // Loading from memory automatically zeroing upper bits.
592 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
593 PatFrag mem_pat, string OpcodeStr,
594 Domain d = GenericDomain> {
595 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
596 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
597 [(set RC:$dst, (mem_pat addr:$src))],
598 IIC_SSE_MOV_S_RM, d>, VEX, VEX_LIG, Sched<[WriteLoad]>;
599 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
600 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
601 [(set RC:$dst, (mem_pat addr:$src))],
602 IIC_SSE_MOV_S_RM, d>, Sched<[WriteLoad]>;
605 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
606 SSEPackedSingle>, XS;
607 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd",
608 SSEPackedDouble>, XD;
610 let canFoldAsLoad = 1, isReMaterializable = 1 in {
611 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss",
612 SSEPackedSingle>, XS;
614 let AddedComplexity = 20 in
615 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd",
616 SSEPackedDouble>, XD;
620 let Predicates = [UseAVX] in {
621 let AddedComplexity = 20 in {
622 // MOVSSrm zeros the high parts of the register; represent this
623 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
624 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
625 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
626 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
627 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
628 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
629 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
631 // MOVSDrm zeros the high parts of the register; represent this
632 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
633 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
637 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
638 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
639 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
640 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
641 def : Pat<(v2f64 (X86vzload addr:$src)),
642 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
644 // Represent the same patterns above but in the form they appear for
646 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
647 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
648 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
649 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
650 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
651 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
652 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
653 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
654 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
656 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
657 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
658 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
660 // Extract and store.
661 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
663 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
664 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
666 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
668 // Shuffle with VMOVSS
669 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
670 (VMOVSSrr (v4i32 VR128:$src1),
671 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
672 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
673 (VMOVSSrr (v4f32 VR128:$src1),
674 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
677 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
678 (SUBREG_TO_REG (i32 0),
679 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
680 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
682 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
683 (SUBREG_TO_REG (i32 0),
684 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
685 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
688 // Shuffle with VMOVSD
689 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
690 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
691 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
692 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
693 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
694 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
695 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
696 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
699 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
700 (SUBREG_TO_REG (i32 0),
701 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
702 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
704 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
705 (SUBREG_TO_REG (i32 0),
706 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
707 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
710 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
711 // is during lowering, where it's not possible to recognize the fold cause
712 // it has two uses through a bitcast. One use disappears at isel time and the
713 // fold opportunity reappears.
714 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
715 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
716 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
717 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
718 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
719 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
720 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
721 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
724 let Predicates = [UseSSE1] in {
725 let Predicates = [NoSSE41], AddedComplexity = 15 in {
726 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
727 // MOVSS to the lower bits.
728 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
729 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
730 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
731 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
732 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
733 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
736 let AddedComplexity = 20 in {
737 // MOVSSrm already zeros the high parts of the register.
738 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
739 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
740 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
741 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
742 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
743 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
746 // Extract and store.
747 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
749 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
751 // Shuffle with MOVSS
752 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
753 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
754 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
755 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
758 let Predicates = [UseSSE2] in {
759 let Predicates = [NoSSE41], AddedComplexity = 15 in {
760 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
761 // MOVSD to the lower bits.
762 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
763 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
766 let AddedComplexity = 20 in {
767 // MOVSDrm already zeros the high parts of the register.
768 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
770 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
771 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
772 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
773 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
774 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
775 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
776 def : Pat<(v2f64 (X86vzload addr:$src)),
777 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
780 // Extract and store.
781 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
783 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
785 // Shuffle with MOVSD
786 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
787 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
788 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
789 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
790 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
791 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
792 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
793 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
796 // is during lowering, where it's not possible to recognize the fold cause
797 // it has two uses through a bitcast. One use disappears at isel time and the
798 // fold opportunity reappears.
799 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
800 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
801 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
802 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
803 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
804 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
805 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
806 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
809 //===----------------------------------------------------------------------===//
810 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
811 //===----------------------------------------------------------------------===//
813 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
814 X86MemOperand x86memop, PatFrag ld_frag,
815 string asm, Domain d,
817 bit IsReMaterializable = 1> {
818 let hasSideEffects = 0 in
819 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
820 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
821 Sched<[WriteFShuffle]>;
822 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
823 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
824 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
825 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
829 let Predicates = [HasAVX, NoVLX] in {
830 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
831 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
833 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
834 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
836 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
837 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
839 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
840 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
843 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
844 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
846 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
847 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
849 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
850 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
852 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
853 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
857 let Predicates = [UseSSE1] in {
858 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
859 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
861 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
862 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
865 let Predicates = [UseSSE2] in {
866 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
867 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
869 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
870 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
874 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
875 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
876 "movaps\t{$src, $dst|$dst, $src}",
877 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
878 IIC_SSE_MOVA_P_MR>, VEX;
879 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
880 "movapd\t{$src, $dst|$dst, $src}",
881 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
882 IIC_SSE_MOVA_P_MR>, VEX;
883 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
884 "movups\t{$src, $dst|$dst, $src}",
885 [(store (v4f32 VR128:$src), addr:$dst)],
886 IIC_SSE_MOVU_P_MR>, VEX;
887 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
888 "movupd\t{$src, $dst|$dst, $src}",
889 [(store (v2f64 VR128:$src), addr:$dst)],
890 IIC_SSE_MOVU_P_MR>, VEX;
891 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
892 "movaps\t{$src, $dst|$dst, $src}",
893 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
894 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
895 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
896 "movapd\t{$src, $dst|$dst, $src}",
897 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
898 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
899 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
900 "movups\t{$src, $dst|$dst, $src}",
901 [(store (v8f32 VR256:$src), addr:$dst)],
902 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
903 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
904 "movupd\t{$src, $dst|$dst, $src}",
905 [(store (v4f64 VR256:$src), addr:$dst)],
906 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
910 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
911 SchedRW = [WriteFShuffle] in {
912 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
914 "movaps\t{$src, $dst|$dst, $src}", [],
915 IIC_SSE_MOVA_P_RR>, VEX;
916 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
918 "movapd\t{$src, $dst|$dst, $src}", [],
919 IIC_SSE_MOVA_P_RR>, VEX;
920 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
922 "movups\t{$src, $dst|$dst, $src}", [],
923 IIC_SSE_MOVU_P_RR>, VEX;
924 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
926 "movupd\t{$src, $dst|$dst, $src}", [],
927 IIC_SSE_MOVU_P_RR>, VEX;
928 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
930 "movaps\t{$src, $dst|$dst, $src}", [],
931 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
932 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
934 "movapd\t{$src, $dst|$dst, $src}", [],
935 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
936 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
938 "movups\t{$src, $dst|$dst, $src}", [],
939 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
940 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
942 "movupd\t{$src, $dst|$dst, $src}", [],
943 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
946 let Predicates = [HasAVX] in {
947 def : Pat<(v8i32 (X86vzmovl
948 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
949 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
950 def : Pat<(v4i64 (X86vzmovl
951 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
952 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
953 def : Pat<(v8f32 (X86vzmovl
954 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
955 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
956 def : Pat<(v4f64 (X86vzmovl
957 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
958 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
962 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
963 (VMOVUPSYmr addr:$dst, VR256:$src)>;
964 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
965 (VMOVUPDYmr addr:$dst, VR256:$src)>;
967 let SchedRW = [WriteStore] in {
968 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movaps\t{$src, $dst|$dst, $src}",
970 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
972 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
973 "movapd\t{$src, $dst|$dst, $src}",
974 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
976 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
977 "movups\t{$src, $dst|$dst, $src}",
978 [(store (v4f32 VR128:$src), addr:$dst)],
980 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
981 "movupd\t{$src, $dst|$dst, $src}",
982 [(store (v2f64 VR128:$src), addr:$dst)],
987 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
988 SchedRW = [WriteFShuffle] in {
989 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
990 "movaps\t{$src, $dst|$dst, $src}", [],
992 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
993 "movapd\t{$src, $dst|$dst, $src}", [],
995 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
996 "movups\t{$src, $dst|$dst, $src}", [],
998 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
999 "movupd\t{$src, $dst|$dst, $src}", [],
1003 let Predicates = [HasAVX] in {
1004 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1005 (VMOVUPSmr addr:$dst, VR128:$src)>;
1006 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1007 (VMOVUPDmr addr:$dst, VR128:$src)>;
1010 let Predicates = [UseSSE1] in
1011 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1012 (MOVUPSmr addr:$dst, VR128:$src)>;
1013 let Predicates = [UseSSE2] in
1014 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1015 (MOVUPDmr addr:$dst, VR128:$src)>;
1017 // Use vmovaps/vmovups for AVX integer load/store.
1018 let Predicates = [HasAVX, NoVLX] in {
1019 // 128-bit load/store
1020 def : Pat<(alignedloadv2i64 addr:$src),
1021 (VMOVAPSrm addr:$src)>;
1022 def : Pat<(loadv2i64 addr:$src),
1023 (VMOVUPSrm addr:$src)>;
1025 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1026 (VMOVAPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1028 (VMOVAPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1030 (VMOVAPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1032 (VMOVAPSmr addr:$dst, VR128:$src)>;
1033 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1034 (VMOVUPSmr addr:$dst, VR128:$src)>;
1035 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1036 (VMOVUPSmr addr:$dst, VR128:$src)>;
1037 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1038 (VMOVUPSmr addr:$dst, VR128:$src)>;
1039 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1040 (VMOVUPSmr addr:$dst, VR128:$src)>;
1042 // 256-bit load/store
1043 def : Pat<(alignedloadv4i64 addr:$src),
1044 (VMOVAPSYrm addr:$src)>;
1045 def : Pat<(loadv4i64 addr:$src),
1046 (VMOVUPSYrm addr:$src)>;
1047 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1048 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1050 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1052 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1054 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1055 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1056 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1057 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1058 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1059 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1060 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1061 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1062 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1064 // Special patterns for storing subvector extracts of lower 128-bits
1065 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1066 def : Pat<(alignedstore (v2f64 (extract_subvector
1067 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1068 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1069 def : Pat<(alignedstore (v4f32 (extract_subvector
1070 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1071 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1072 def : Pat<(alignedstore (v2i64 (extract_subvector
1073 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1074 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1075 def : Pat<(alignedstore (v4i32 (extract_subvector
1076 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1077 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1078 def : Pat<(alignedstore (v8i16 (extract_subvector
1079 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1080 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1081 def : Pat<(alignedstore (v16i8 (extract_subvector
1082 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1083 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1085 def : Pat<(store (v2f64 (extract_subvector
1086 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1087 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1088 def : Pat<(store (v4f32 (extract_subvector
1089 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1090 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1091 def : Pat<(store (v2i64 (extract_subvector
1092 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1093 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1094 def : Pat<(store (v4i32 (extract_subvector
1095 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1096 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1097 def : Pat<(store (v8i16 (extract_subvector
1098 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1099 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1100 def : Pat<(store (v16i8 (extract_subvector
1101 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1102 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1105 // Use movaps / movups for SSE integer load / store (one byte shorter).
1106 // The instructions selected below are then converted to MOVDQA/MOVDQU
1107 // during the SSE domain pass.
1108 let Predicates = [UseSSE1] in {
1109 def : Pat<(alignedloadv2i64 addr:$src),
1110 (MOVAPSrm addr:$src)>;
1111 def : Pat<(loadv2i64 addr:$src),
1112 (MOVUPSrm addr:$src)>;
1114 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1115 (MOVAPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1117 (MOVAPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1119 (MOVAPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1121 (MOVAPSmr addr:$dst, VR128:$src)>;
1122 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1123 (MOVUPSmr addr:$dst, VR128:$src)>;
1124 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1125 (MOVUPSmr addr:$dst, VR128:$src)>;
1126 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1127 (MOVUPSmr addr:$dst, VR128:$src)>;
1128 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1129 (MOVUPSmr addr:$dst, VR128:$src)>;
1132 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1133 // bits are disregarded. FIXME: Set encoding to pseudo!
1134 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1135 let isCodeGenOnly = 1 in {
1136 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1137 "movaps\t{$src, $dst|$dst, $src}",
1138 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1139 IIC_SSE_MOVA_P_RM>, VEX;
1140 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1141 "movapd\t{$src, $dst|$dst, $src}",
1142 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1143 IIC_SSE_MOVA_P_RM>, VEX;
1144 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1145 "movaps\t{$src, $dst|$dst, $src}",
1146 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1148 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1149 "movapd\t{$src, $dst|$dst, $src}",
1150 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1155 //===----------------------------------------------------------------------===//
1156 // SSE 1 & 2 - Move Low packed FP Instructions
1157 //===----------------------------------------------------------------------===//
1159 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1160 string base_opc, string asm_opr,
1161 InstrItinClass itin> {
1162 def PSrm : PI<opc, MRMSrcMem,
1163 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1164 !strconcat(base_opc, "s", asm_opr),
1166 (psnode VR128:$src1,
1167 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1168 itin, SSEPackedSingle>, PS,
1169 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1171 def PDrm : PI<opc, MRMSrcMem,
1172 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1173 !strconcat(base_opc, "d", asm_opr),
1174 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1175 (scalar_to_vector (loadf64 addr:$src2)))))],
1176 itin, SSEPackedDouble>, PD,
1177 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1181 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1182 string base_opc, InstrItinClass itin> {
1183 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1184 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1187 let Constraints = "$src1 = $dst" in
1188 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1189 "\t{$src2, $dst|$dst, $src2}",
1193 let AddedComplexity = 20 in {
1194 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1198 let SchedRW = [WriteStore] in {
1199 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1200 "movlps\t{$src, $dst|$dst, $src}",
1201 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1202 (iPTR 0))), addr:$dst)],
1203 IIC_SSE_MOV_LH>, VEX;
1204 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1205 "movlpd\t{$src, $dst|$dst, $src}",
1206 [(store (f64 (vector_extract (v2f64 VR128:$src),
1207 (iPTR 0))), addr:$dst)],
1208 IIC_SSE_MOV_LH>, VEX;
1209 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1210 "movlps\t{$src, $dst|$dst, $src}",
1211 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1212 (iPTR 0))), addr:$dst)],
1214 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1215 "movlpd\t{$src, $dst|$dst, $src}",
1216 [(store (f64 (vector_extract (v2f64 VR128:$src),
1217 (iPTR 0))), addr:$dst)],
1221 let Predicates = [HasAVX] in {
1222 // Shuffle with VMOVLPS
1223 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1224 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1226 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1228 // Shuffle with VMOVLPD
1229 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1230 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1231 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1232 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1233 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1234 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1235 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1238 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1240 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1241 def : Pat<(store (v4i32 (X86Movlps
1242 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1243 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1244 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1246 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1247 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1249 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1252 let Predicates = [UseSSE1] in {
1253 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1254 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1255 (iPTR 0))), addr:$src1),
1256 (MOVLPSmr addr:$src1, VR128:$src2)>;
1258 // Shuffle with MOVLPS
1259 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1260 (MOVLPSrm VR128:$src1, addr:$src2)>;
1261 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1262 (MOVLPSrm VR128:$src1, addr:$src2)>;
1263 def : Pat<(X86Movlps VR128:$src1,
1264 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1265 (MOVLPSrm VR128:$src1, addr:$src2)>;
1268 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1270 (MOVLPSmr addr:$src1, VR128:$src2)>;
1271 def : Pat<(store (v4i32 (X86Movlps
1272 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1274 (MOVLPSmr addr:$src1, VR128:$src2)>;
1277 let Predicates = [UseSSE2] in {
1278 // Shuffle with MOVLPD
1279 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1280 (MOVLPDrm VR128:$src1, addr:$src2)>;
1281 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1282 (MOVLPDrm VR128:$src1, addr:$src2)>;
1283 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1284 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1285 (MOVLPDrm VR128:$src1, addr:$src2)>;
1288 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1290 (MOVLPDmr addr:$src1, VR128:$src2)>;
1291 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1293 (MOVLPDmr addr:$src1, VR128:$src2)>;
1296 //===----------------------------------------------------------------------===//
1297 // SSE 1 & 2 - Move Hi packed FP Instructions
1298 //===----------------------------------------------------------------------===//
1300 let AddedComplexity = 20 in {
1301 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1305 let SchedRW = [WriteStore] in {
1306 // v2f64 extract element 1 is always custom lowered to unpack high to low
1307 // and extract element 0 so the non-store version isn't too horrible.
1308 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1309 "movhps\t{$src, $dst|$dst, $src}",
1310 [(store (f64 (vector_extract
1311 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1312 (bc_v2f64 (v4f32 VR128:$src))),
1313 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1314 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1315 "movhpd\t{$src, $dst|$dst, $src}",
1316 [(store (f64 (vector_extract
1317 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1318 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1319 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1320 "movhps\t{$src, $dst|$dst, $src}",
1321 [(store (f64 (vector_extract
1322 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1323 (bc_v2f64 (v4f32 VR128:$src))),
1324 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1325 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1326 "movhpd\t{$src, $dst|$dst, $src}",
1327 [(store (f64 (vector_extract
1328 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1329 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1332 let Predicates = [HasAVX] in {
1334 def : Pat<(X86Movlhps VR128:$src1,
1335 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1336 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1337 def : Pat<(X86Movlhps VR128:$src1,
1338 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1339 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1343 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1344 // is during lowering, where it's not possible to recognize the load fold
1345 // cause it has two uses through a bitcast. One use disappears at isel time
1346 // and the fold opportunity reappears.
1347 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1348 (scalar_to_vector (loadf64 addr:$src2)))),
1349 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1350 // Also handle an i64 load because that may get selected as a faster way to
1352 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1353 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1354 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1356 def : Pat<(store (f64 (vector_extract
1357 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1358 (iPTR 0))), addr:$dst),
1359 (VMOVHPDmr addr:$dst, VR128:$src)>;
1362 let Predicates = [UseSSE1] in {
1364 def : Pat<(X86Movlhps VR128:$src1,
1365 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1366 (MOVHPSrm VR128:$src1, addr:$src2)>;
1367 def : Pat<(X86Movlhps VR128:$src1,
1368 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1369 (MOVHPSrm VR128:$src1, addr:$src2)>;
1372 let Predicates = [UseSSE2] in {
1375 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1376 // is during lowering, where it's not possible to recognize the load fold
1377 // cause it has two uses through a bitcast. One use disappears at isel time
1378 // and the fold opportunity reappears.
1379 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1380 (scalar_to_vector (loadf64 addr:$src2)))),
1381 (MOVHPDrm VR128:$src1, addr:$src2)>;
1382 // Also handle an i64 load because that may get selected as a faster way to
1384 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1385 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1386 (MOVHPDrm VR128:$src1, addr:$src2)>;
1388 def : Pat<(store (f64 (vector_extract
1389 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1390 (iPTR 0))), addr:$dst),
1391 (MOVHPDmr addr:$dst, VR128:$src)>;
1394 //===----------------------------------------------------------------------===//
1395 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1396 //===----------------------------------------------------------------------===//
1398 let AddedComplexity = 20, Predicates = [UseAVX] in {
1399 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1400 (ins VR128:$src1, VR128:$src2),
1401 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1403 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1405 VEX_4V, Sched<[WriteFShuffle]>;
1406 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1407 (ins VR128:$src1, VR128:$src2),
1408 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1410 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1412 VEX_4V, Sched<[WriteFShuffle]>;
1414 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1415 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1416 (ins VR128:$src1, VR128:$src2),
1417 "movlhps\t{$src2, $dst|$dst, $src2}",
1419 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1420 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1421 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1422 (ins VR128:$src1, VR128:$src2),
1423 "movhlps\t{$src2, $dst|$dst, $src2}",
1425 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1426 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1429 let Predicates = [UseAVX] in {
1431 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1432 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1433 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1434 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1437 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1438 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1441 let Predicates = [UseSSE1] in {
1443 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1444 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1445 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1446 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1449 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1450 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1453 //===----------------------------------------------------------------------===//
1454 // SSE 1 & 2 - Conversion Instructions
1455 //===----------------------------------------------------------------------===//
1457 def SSE_CVT_PD : OpndItins<
1458 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1461 let Sched = WriteCvtI2F in
1462 def SSE_CVT_PS : OpndItins<
1463 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1466 let Sched = WriteCvtI2F in
1467 def SSE_CVT_Scalar : OpndItins<
1468 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1471 let Sched = WriteCvtF2I in
1472 def SSE_CVT_SS2SI_32 : OpndItins<
1473 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1476 let Sched = WriteCvtF2I in
1477 def SSE_CVT_SS2SI_64 : OpndItins<
1478 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1481 let Sched = WriteCvtF2I in
1482 def SSE_CVT_SD2SI : OpndItins<
1483 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1486 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1487 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1488 string asm, OpndItins itins> {
1489 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1490 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1491 itins.rr>, Sched<[itins.Sched]>;
1492 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1493 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1494 itins.rm>, Sched<[itins.Sched.Folded]>;
1497 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1498 X86MemOperand x86memop, string asm, Domain d,
1500 let hasSideEffects = 0 in {
1501 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1502 [], itins.rr, d>, Sched<[itins.Sched]>;
1504 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1505 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1509 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1510 X86MemOperand x86memop, string asm> {
1511 let hasSideEffects = 0, Predicates = [UseAVX] in {
1512 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1513 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1514 Sched<[WriteCvtI2F]>;
1516 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1517 (ins DstRC:$src1, x86memop:$src),
1518 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1519 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1520 } // hasSideEffects = 0
1523 let Predicates = [UseAVX] in {
1524 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1525 "cvttss2si\t{$src, $dst|$dst, $src}",
1528 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1529 "cvttss2si\t{$src, $dst|$dst, $src}",
1531 XS, VEX, VEX_W, VEX_LIG;
1532 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1533 "cvttsd2si\t{$src, $dst|$dst, $src}",
1536 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1537 "cvttsd2si\t{$src, $dst|$dst, $src}",
1539 XD, VEX, VEX_W, VEX_LIG;
1541 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1542 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1543 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1545 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1549 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1550 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1551 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1552 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1553 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1554 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1555 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1556 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1558 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1559 // register, but the same isn't true when only using memory operands,
1560 // provide other assembly "l" and "q" forms to address this explicitly
1561 // where appropriate to do so.
1562 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1563 XS, VEX_4V, VEX_LIG;
1564 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1565 XS, VEX_4V, VEX_W, VEX_LIG;
1566 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1567 XD, VEX_4V, VEX_LIG;
1568 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1569 XD, VEX_4V, VEX_W, VEX_LIG;
1571 let Predicates = [UseAVX] in {
1572 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1573 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1574 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1575 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1577 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1578 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1579 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1580 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1581 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1582 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1583 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1584 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1586 def : Pat<(f32 (sint_to_fp GR32:$src)),
1587 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1588 def : Pat<(f32 (sint_to_fp GR64:$src)),
1589 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1590 def : Pat<(f64 (sint_to_fp GR32:$src)),
1591 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1592 def : Pat<(f64 (sint_to_fp GR64:$src)),
1593 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1596 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1597 "cvttss2si\t{$src, $dst|$dst, $src}",
1598 SSE_CVT_SS2SI_32>, XS;
1599 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1600 "cvttss2si\t{$src, $dst|$dst, $src}",
1601 SSE_CVT_SS2SI_64>, XS, REX_W;
1602 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1603 "cvttsd2si\t{$src, $dst|$dst, $src}",
1605 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1606 "cvttsd2si\t{$src, $dst|$dst, $src}",
1607 SSE_CVT_SD2SI>, XD, REX_W;
1608 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1609 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1610 SSE_CVT_Scalar>, XS;
1611 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1612 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1613 SSE_CVT_Scalar>, XS, REX_W;
1614 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1615 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1616 SSE_CVT_Scalar>, XD;
1617 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1618 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1619 SSE_CVT_Scalar>, XD, REX_W;
1621 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1622 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1623 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1625 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1626 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1627 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1629 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1630 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1631 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1632 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1633 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1634 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1635 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1636 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1638 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1639 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1640 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1641 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1643 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1644 // and/or XMM operand(s).
1646 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1647 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1648 string asm, OpndItins itins> {
1649 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1650 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1651 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1652 Sched<[itins.Sched]>;
1653 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1654 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1655 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1656 Sched<[itins.Sched.Folded]>;
1659 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1660 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1661 PatFrag ld_frag, string asm, OpndItins itins,
1663 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1665 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1666 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1667 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1668 itins.rr>, Sched<[itins.Sched]>;
1669 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1670 (ins DstRC:$src1, x86memop:$src2),
1672 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1673 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1674 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1675 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1678 let Predicates = [UseAVX] in {
1679 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1680 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1681 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1682 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1683 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1684 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1686 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1687 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1688 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1689 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1692 let isCodeGenOnly = 1 in {
1693 let Predicates = [UseAVX] in {
1694 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1695 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1696 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1697 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1698 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1699 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1701 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1702 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1703 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1704 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1705 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1706 SSE_CVT_Scalar, 0>, XD,
1709 let Constraints = "$src1 = $dst" in {
1710 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1711 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1712 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1713 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1714 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1715 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1716 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1717 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1718 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1719 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1720 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1721 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1723 } // isCodeGenOnly = 1
1727 // Aliases for intrinsics
1728 let isCodeGenOnly = 1 in {
1729 let Predicates = [UseAVX] in {
1730 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1731 ssmem, sse_load_f32, "cvttss2si",
1732 SSE_CVT_SS2SI_32>, XS, VEX;
1733 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1734 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1735 "cvttss2si", SSE_CVT_SS2SI_64>,
1737 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1738 sdmem, sse_load_f64, "cvttsd2si",
1739 SSE_CVT_SD2SI>, XD, VEX;
1740 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1741 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1742 "cvttsd2si", SSE_CVT_SD2SI>,
1745 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1746 ssmem, sse_load_f32, "cvttss2si",
1747 SSE_CVT_SS2SI_32>, XS;
1748 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1749 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1750 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1751 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1752 sdmem, sse_load_f64, "cvttsd2si",
1754 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1755 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1756 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1757 } // isCodeGenOnly = 1
1759 let Predicates = [UseAVX] in {
1760 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1761 ssmem, sse_load_f32, "cvtss2si",
1762 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1763 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1764 ssmem, sse_load_f32, "cvtss2si",
1765 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1767 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1768 ssmem, sse_load_f32, "cvtss2si",
1769 SSE_CVT_SS2SI_32>, XS;
1770 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1771 ssmem, sse_load_f32, "cvtss2si",
1772 SSE_CVT_SS2SI_64>, XS, REX_W;
1774 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1775 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1776 SSEPackedSingle, SSE_CVT_PS>,
1777 PS, VEX, Requires<[HasAVX]>;
1778 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1779 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1780 SSEPackedSingle, SSE_CVT_PS>,
1781 PS, VEX, VEX_L, Requires<[HasAVX]>;
1783 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1784 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1785 SSEPackedSingle, SSE_CVT_PS>,
1786 PS, Requires<[UseSSE2]>;
1788 let Predicates = [UseAVX] in {
1789 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1790 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1791 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1793 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1794 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1797 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1798 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1799 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1800 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1801 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1802 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1803 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1804 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1807 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1808 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1809 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1811 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1812 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1813 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1815 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1816 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1817 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1818 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1819 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1820 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1821 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1822 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1826 // Convert scalar double to scalar single
1827 let hasSideEffects = 0, Predicates = [UseAVX] in {
1828 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1829 (ins FR64:$src1, FR64:$src2),
1830 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1831 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1832 Sched<[WriteCvtF2F]>;
1834 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1835 (ins FR64:$src1, f64mem:$src2),
1836 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1837 [], IIC_SSE_CVT_Scalar_RM>,
1838 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1839 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1842 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1845 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1846 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1847 [(set FR32:$dst, (fround FR64:$src))],
1848 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1849 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1850 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1851 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1852 IIC_SSE_CVT_Scalar_RM>,
1854 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1856 let isCodeGenOnly = 1 in {
1857 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1858 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1859 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1861 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1862 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1863 Sched<[WriteCvtF2F]>;
1864 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1865 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1866 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1867 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1868 VR128:$src1, sse_load_f64:$src2))],
1869 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1870 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1872 let Constraints = "$src1 = $dst" in {
1873 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1874 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1875 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1877 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1878 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1879 Sched<[WriteCvtF2F]>;
1880 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1881 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1882 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1883 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1884 VR128:$src1, sse_load_f64:$src2))],
1885 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1886 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1888 } // isCodeGenOnly = 1
1890 // Convert scalar single to scalar double
1891 // SSE2 instructions with XS prefix
1892 let hasSideEffects = 0, Predicates = [UseAVX] in {
1893 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1894 (ins FR32:$src1, FR32:$src2),
1895 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1896 [], IIC_SSE_CVT_Scalar_RR>,
1897 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1898 Sched<[WriteCvtF2F]>;
1900 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1901 (ins FR32:$src1, f32mem:$src2),
1902 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1903 [], IIC_SSE_CVT_Scalar_RM>,
1904 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1905 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1908 def : Pat<(f64 (fextend FR32:$src)),
1909 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1910 def : Pat<(fextend (loadf32 addr:$src)),
1911 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1913 def : Pat<(extloadf32 addr:$src),
1914 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1915 Requires<[UseAVX, OptForSize]>;
1916 def : Pat<(extloadf32 addr:$src),
1917 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1918 Requires<[UseAVX, OptForSpeed]>;
1920 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1921 "cvtss2sd\t{$src, $dst|$dst, $src}",
1922 [(set FR64:$dst, (fextend FR32:$src))],
1923 IIC_SSE_CVT_Scalar_RR>, XS,
1924 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1925 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1926 "cvtss2sd\t{$src, $dst|$dst, $src}",
1927 [(set FR64:$dst, (extloadf32 addr:$src))],
1928 IIC_SSE_CVT_Scalar_RM>, XS,
1929 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1931 // extload f32 -> f64. This matches load+fextend because we have a hack in
1932 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1934 // Since these loads aren't folded into the fextend, we have to match it
1936 def : Pat<(fextend (loadf32 addr:$src)),
1937 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1938 def : Pat<(extloadf32 addr:$src),
1939 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1941 let isCodeGenOnly = 1 in {
1942 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1943 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1944 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1946 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1947 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1948 Sched<[WriteCvtF2F]>;
1949 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1950 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1951 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1953 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1954 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1955 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1956 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1957 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1958 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1959 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1961 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1962 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1963 Sched<[WriteCvtF2F]>;
1964 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1965 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1966 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1968 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1969 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1970 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1972 } // isCodeGenOnly = 1
1974 // Convert packed single/double fp to doubleword
1975 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1976 "cvtps2dq\t{$src, $dst|$dst, $src}",
1977 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1978 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1979 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1980 "cvtps2dq\t{$src, $dst|$dst, $src}",
1982 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1983 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1984 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1985 "cvtps2dq\t{$src, $dst|$dst, $src}",
1987 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1988 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1989 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1990 "cvtps2dq\t{$src, $dst|$dst, $src}",
1992 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1993 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1994 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1995 "cvtps2dq\t{$src, $dst|$dst, $src}",
1996 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1997 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1998 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1999 "cvtps2dq\t{$src, $dst|$dst, $src}",
2001 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
2002 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2005 // Convert Packed Double FP to Packed DW Integers
2006 let Predicates = [HasAVX] in {
2007 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2008 // register, but the same isn't true when using memory operands instead.
2009 // Provide other assembly rr and rm forms to address this explicitly.
2010 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2011 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2012 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2013 VEX, Sched<[WriteCvtF2I]>;
2016 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2017 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2018 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2019 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2021 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2022 Sched<[WriteCvtF2ILd]>;
2025 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2026 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2028 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2029 Sched<[WriteCvtF2I]>;
2030 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2031 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2033 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2034 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2035 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2036 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2039 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2040 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2042 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2043 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2044 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2045 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2046 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2047 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2049 // Convert with truncation packed single/double fp to doubleword
2050 // SSE2 packed instructions with XS prefix
2051 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2052 "cvttps2dq\t{$src, $dst|$dst, $src}",
2054 (int_x86_sse2_cvttps2dq VR128:$src))],
2055 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2056 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2057 "cvttps2dq\t{$src, $dst|$dst, $src}",
2058 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2059 (loadv4f32 addr:$src)))],
2060 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2061 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2062 "cvttps2dq\t{$src, $dst|$dst, $src}",
2064 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2065 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2066 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2067 "cvttps2dq\t{$src, $dst|$dst, $src}",
2068 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2069 (loadv8f32 addr:$src)))],
2070 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2071 Sched<[WriteCvtF2ILd]>;
2073 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2074 "cvttps2dq\t{$src, $dst|$dst, $src}",
2075 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2076 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2077 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2078 "cvttps2dq\t{$src, $dst|$dst, $src}",
2080 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2081 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2083 let Predicates = [HasAVX] in {
2084 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2085 (VCVTDQ2PSrr VR128:$src)>;
2086 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2087 (VCVTDQ2PSrm addr:$src)>;
2089 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2090 (VCVTDQ2PSrr VR128:$src)>;
2091 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2092 (VCVTDQ2PSrm addr:$src)>;
2094 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2095 (VCVTTPS2DQrr VR128:$src)>;
2096 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2097 (VCVTTPS2DQrm addr:$src)>;
2099 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2100 (VCVTDQ2PSYrr VR256:$src)>;
2101 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2102 (VCVTDQ2PSYrm addr:$src)>;
2104 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2105 (VCVTTPS2DQYrr VR256:$src)>;
2106 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2107 (VCVTTPS2DQYrm addr:$src)>;
2110 let Predicates = [UseSSE2] in {
2111 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2112 (CVTDQ2PSrr VR128:$src)>;
2113 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2114 (CVTDQ2PSrm addr:$src)>;
2116 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2117 (CVTDQ2PSrr VR128:$src)>;
2118 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2119 (CVTDQ2PSrm addr:$src)>;
2121 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2122 (CVTTPS2DQrr VR128:$src)>;
2123 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2124 (CVTTPS2DQrm addr:$src)>;
2127 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2128 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2130 (int_x86_sse2_cvttpd2dq VR128:$src))],
2131 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2133 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2134 // register, but the same isn't true when using memory operands instead.
2135 // Provide other assembly rr and rm forms to address this explicitly.
2138 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2139 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2140 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2141 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2142 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2143 (loadv2f64 addr:$src)))],
2144 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2147 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2148 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2150 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2151 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2152 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2153 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2155 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2156 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2157 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2158 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2160 let Predicates = [HasAVX] in {
2161 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2162 (VCVTTPD2DQYrr VR256:$src)>;
2163 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2164 (VCVTTPD2DQYrm addr:$src)>;
2165 } // Predicates = [HasAVX]
2167 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2168 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2169 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2170 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2171 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2172 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2173 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2174 (memopv2f64 addr:$src)))],
2176 Sched<[WriteCvtF2ILd]>;
2178 // Convert packed single to packed double
2179 let Predicates = [HasAVX] in {
2180 // SSE2 instructions without OpSize prefix
2181 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2182 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2183 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2184 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2185 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2186 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2187 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2188 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2189 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2190 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2192 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2193 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2194 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2195 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2197 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2198 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2201 let Predicates = [UseSSE2] in {
2202 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2203 "cvtps2pd\t{$src, $dst|$dst, $src}",
2204 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2205 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2206 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2207 "cvtps2pd\t{$src, $dst|$dst, $src}",
2208 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2209 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2212 // Convert Packed DW Integers to Packed Double FP
2213 let Predicates = [HasAVX] in {
2214 let hasSideEffects = 0, mayLoad = 1 in
2215 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2216 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2217 []>, VEX, Sched<[WriteCvtI2FLd]>;
2218 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2219 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2221 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2222 Sched<[WriteCvtI2F]>;
2223 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2224 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2226 (int_x86_avx_cvtdq2_pd_256
2227 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2228 Sched<[WriteCvtI2FLd]>;
2229 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2230 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2232 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2233 Sched<[WriteCvtI2F]>;
2236 let hasSideEffects = 0, mayLoad = 1 in
2237 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2238 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2239 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2240 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2241 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2242 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2243 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2245 // AVX 256-bit register conversion intrinsics
2246 let Predicates = [HasAVX] in {
2247 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2248 (VCVTDQ2PDYrr VR128:$src)>;
2249 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2250 (VCVTDQ2PDYrm addr:$src)>;
2251 } // Predicates = [HasAVX]
2253 // Convert packed double to packed single
2254 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2255 // register, but the same isn't true when using memory operands instead.
2256 // Provide other assembly rr and rm forms to address this explicitly.
2257 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2258 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2259 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2260 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2263 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2264 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2265 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2266 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2268 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2269 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2272 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2273 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2275 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2276 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2277 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2278 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2280 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2281 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2282 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2283 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2285 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2286 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2287 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2288 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2289 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2290 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2292 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2293 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2296 // AVX 256-bit register conversion intrinsics
2297 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2298 // whenever possible to avoid declaring two versions of each one.
2299 let Predicates = [HasAVX] in {
2300 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2301 (VCVTDQ2PSYrr VR256:$src)>;
2302 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2303 (VCVTDQ2PSYrm addr:$src)>;
2305 // Match fround and fextend for 128/256-bit conversions
2306 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2307 (VCVTPD2PSrr VR128:$src)>;
2308 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2309 (VCVTPD2PSXrm addr:$src)>;
2310 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2311 (VCVTPD2PSYrr VR256:$src)>;
2312 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2313 (VCVTPD2PSYrm addr:$src)>;
2315 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2316 (VCVTPS2PDrr VR128:$src)>;
2317 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2318 (VCVTPS2PDYrr VR128:$src)>;
2319 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2320 (VCVTPS2PDYrm addr:$src)>;
2323 let Predicates = [UseSSE2] in {
2324 // Match fround and fextend for 128 conversions
2325 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2326 (CVTPD2PSrr VR128:$src)>;
2327 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2328 (CVTPD2PSrm addr:$src)>;
2330 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2331 (CVTPS2PDrr VR128:$src)>;
2334 //===----------------------------------------------------------------------===//
2335 // SSE 1 & 2 - Compare Instructions
2336 //===----------------------------------------------------------------------===//
2338 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2339 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2340 Operand CC, SDNode OpNode, ValueType VT,
2341 PatFrag ld_frag, string asm, string asm_alt,
2342 OpndItins itins, ImmLeaf immLeaf> {
2343 def rr : SIi8<0xC2, MRMSrcReg,
2344 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2345 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))],
2346 itins.rr>, Sched<[itins.Sched]>;
2347 def rm : SIi8<0xC2, MRMSrcMem,
2348 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2349 [(set RC:$dst, (OpNode (VT RC:$src1),
2350 (ld_frag addr:$src2), immLeaf:$cc))],
2352 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2354 // Accept explicit immediate argument form instead of comparison code.
2355 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2356 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2357 (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, [],
2358 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2360 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2361 (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, [],
2362 IIC_SSE_ALU_F32S_RM>,
2363 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2367 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2368 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2369 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2370 SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG;
2371 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2372 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2373 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2374 SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare
2375 XD, VEX_4V, VEX_LIG;
2377 let Constraints = "$src1 = $dst" in {
2378 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2379 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2380 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S,
2382 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2383 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2384 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2385 SSE_ALU_F64S, i8immZExt3>, XD;
2388 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2389 Intrinsic Int, string asm, OpndItins itins,
2391 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2392 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2393 [(set VR128:$dst, (Int VR128:$src1,
2394 VR128:$src, immLeaf:$cc))],
2396 Sched<[itins.Sched]>;
2397 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2398 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2399 [(set VR128:$dst, (Int VR128:$src1,
2400 (load addr:$src), immLeaf:$cc))],
2402 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2405 let isCodeGenOnly = 1 in {
2406 // Aliases to match intrinsics which expect XMM operand(s).
2407 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2408 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2409 SSE_ALU_F32S, i8immZExt5>,
2411 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2412 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2413 SSE_ALU_F32S, i8immZExt5>, // same latency as f32
2415 let Constraints = "$src1 = $dst" in {
2416 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2417 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2418 SSE_ALU_F32S, i8immZExt3>, XS;
2419 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2420 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2421 SSE_ALU_F64S, i8immZExt3>,
2427 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2428 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2429 ValueType vt, X86MemOperand x86memop,
2430 PatFrag ld_frag, string OpcodeStr> {
2431 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2432 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2433 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2436 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2437 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2438 [(set EFLAGS, (OpNode (vt RC:$src1),
2439 (ld_frag addr:$src2)))],
2441 Sched<[WriteFAddLd, ReadAfterLd]>;
2444 let Defs = [EFLAGS] in {
2445 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2446 "ucomiss">, PS, VEX, VEX_LIG;
2447 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2448 "ucomisd">, PD, VEX, VEX_LIG;
2449 let Pattern = []<dag> in {
2450 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2451 "comiss">, PS, VEX, VEX_LIG;
2452 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2453 "comisd">, PD, VEX, VEX_LIG;
2456 let isCodeGenOnly = 1 in {
2457 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2458 load, "ucomiss">, PS, VEX;
2459 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2460 load, "ucomisd">, PD, VEX;
2462 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2463 load, "comiss">, PS, VEX;
2464 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2465 load, "comisd">, PD, VEX;
2467 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2469 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2472 let Pattern = []<dag> in {
2473 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2475 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2479 let isCodeGenOnly = 1 in {
2480 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2481 load, "ucomiss">, PS;
2482 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2483 load, "ucomisd">, PD;
2485 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2487 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2490 } // Defs = [EFLAGS]
2492 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2493 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2494 Operand CC, Intrinsic Int, string asm,
2495 string asm_alt, Domain d, ImmLeaf immLeaf,
2496 PatFrag ld_frag, OpndItins itins = SSE_ALU_F32P> {
2497 let isCommutable = 1 in
2498 def rri : PIi8<0xC2, MRMSrcReg,
2499 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2500 [(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
2503 def rmi : PIi8<0xC2, MRMSrcMem,
2504 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2505 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2), immLeaf:$cc))],
2507 Sched<[WriteFAddLd, ReadAfterLd]>;
2509 // Accept explicit immediate argument form instead of comparison code.
2510 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2511 def rri_alt : PIi8<0xC2, MRMSrcReg,
2512 (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
2513 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2515 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2516 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
2517 asm_alt, [], itins.rm, d>,
2518 Sched<[WriteFAddLd, ReadAfterLd]>;
2522 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2523 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2524 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2525 SSEPackedSingle, i8immZExt5, loadv4f32>, PS, VEX_4V;
2526 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2527 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2528 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2529 SSEPackedDouble, i8immZExt5, loadv2f64>, PD, VEX_4V;
2530 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2531 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2532 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2533 SSEPackedSingle, i8immZExt5, loadv8f32>, PS, VEX_4V, VEX_L;
2534 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2535 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2536 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2537 SSEPackedDouble, i8immZExt5, loadv4f64>, PD, VEX_4V, VEX_L;
2538 let Constraints = "$src1 = $dst" in {
2539 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2540 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2541 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2542 SSEPackedSingle, i8immZExt5, memopv4f32, SSE_ALU_F32P>, PS;
2543 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2544 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2545 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2546 SSEPackedDouble, i8immZExt5, memopv2f64, SSE_ALU_F64P>, PD;
2549 let Predicates = [HasAVX] in {
2550 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2551 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2552 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (loadv4f32 addr:$src2), imm:$cc)),
2553 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2554 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2555 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2556 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (loadv2f64 addr:$src2), imm:$cc)),
2557 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2559 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2560 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2561 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (loadv8f32 addr:$src2), imm:$cc)),
2562 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2563 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2564 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2565 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (loadv4f64 addr:$src2), imm:$cc)),
2566 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2569 let Predicates = [UseSSE1] in {
2570 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2571 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2572 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memopv4f32 addr:$src2), imm:$cc)),
2573 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2576 let Predicates = [UseSSE2] in {
2577 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2578 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2579 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memopv2f64 addr:$src2), imm:$cc)),
2580 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2583 //===----------------------------------------------------------------------===//
2584 // SSE 1 & 2 - Shuffle Instructions
2585 //===----------------------------------------------------------------------===//
2587 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2588 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2589 ValueType vt, string asm, PatFrag mem_frag,
2591 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2592 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2593 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2594 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2595 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2596 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2597 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2598 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2599 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2600 Sched<[WriteFShuffle]>;
2603 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2604 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2605 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2606 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2607 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2608 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2609 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2610 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2611 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2612 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2613 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2614 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2616 let Constraints = "$src1 = $dst" in {
2617 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2618 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2619 memopv4f32, SSEPackedSingle>, PS;
2620 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2621 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2622 memopv2f64, SSEPackedDouble>, PD;
2625 let Predicates = [HasAVX] in {
2626 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2627 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2628 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2629 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2630 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2632 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2633 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2634 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2635 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2636 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2639 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2640 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2641 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2642 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2643 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2645 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2646 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2647 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2648 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2649 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2652 let Predicates = [UseSSE1] in {
2653 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2654 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2655 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2656 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2657 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2660 let Predicates = [UseSSE2] in {
2661 // Generic SHUFPD patterns
2662 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2663 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2664 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2665 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2666 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2669 //===----------------------------------------------------------------------===//
2670 // SSE 1 & 2 - Unpack FP Instructions
2671 //===----------------------------------------------------------------------===//
2673 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2674 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2675 PatFrag mem_frag, RegisterClass RC,
2676 X86MemOperand x86memop, string asm,
2678 def rr : PI<opc, MRMSrcReg,
2679 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2681 (vt (OpNode RC:$src1, RC:$src2)))],
2682 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2683 def rm : PI<opc, MRMSrcMem,
2684 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2686 (vt (OpNode RC:$src1,
2687 (mem_frag addr:$src2))))],
2689 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2692 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2693 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2694 SSEPackedSingle>, PS, VEX_4V;
2695 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2696 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2697 SSEPackedDouble>, PD, VEX_4V;
2698 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2699 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2700 SSEPackedSingle>, PS, VEX_4V;
2701 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2702 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2703 SSEPackedDouble>, PD, VEX_4V;
2705 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2706 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2707 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2708 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2709 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2710 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2711 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2712 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2713 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2714 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2715 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2716 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2718 let Constraints = "$src1 = $dst" in {
2719 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2720 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2721 SSEPackedSingle>, PS;
2722 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2723 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2724 SSEPackedDouble>, PD;
2725 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2726 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2727 SSEPackedSingle>, PS;
2728 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2729 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2730 SSEPackedDouble>, PD;
2731 } // Constraints = "$src1 = $dst"
2733 let Predicates = [HasAVX1Only] in {
2734 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2735 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2736 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2737 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2738 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2739 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2740 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2741 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2743 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2744 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2745 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2746 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2747 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2748 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2749 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2750 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2753 //===----------------------------------------------------------------------===//
2754 // SSE 1 & 2 - Extract Floating-Point Sign mask
2755 //===----------------------------------------------------------------------===//
2757 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2758 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2760 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2761 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2762 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2763 Sched<[WriteVecLogic]>;
2766 let Predicates = [HasAVX] in {
2767 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2768 "movmskps", SSEPackedSingle>, PS, VEX;
2769 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2770 "movmskpd", SSEPackedDouble>, PD, VEX;
2771 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2772 "movmskps", SSEPackedSingle>, PS,
2774 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2775 "movmskpd", SSEPackedDouble>, PD,
2778 def : Pat<(i32 (X86fgetsign FR32:$src)),
2779 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2780 def : Pat<(i64 (X86fgetsign FR32:$src)),
2781 (SUBREG_TO_REG (i64 0),
2782 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2783 def : Pat<(i32 (X86fgetsign FR64:$src)),
2784 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2785 def : Pat<(i64 (X86fgetsign FR64:$src)),
2786 (SUBREG_TO_REG (i64 0),
2787 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2790 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2791 SSEPackedSingle>, PS;
2792 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2793 SSEPackedDouble>, PD;
2795 def : Pat<(i32 (X86fgetsign FR32:$src)),
2796 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2797 Requires<[UseSSE1]>;
2798 def : Pat<(i64 (X86fgetsign FR32:$src)),
2799 (SUBREG_TO_REG (i64 0),
2800 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2801 Requires<[UseSSE1]>;
2802 def : Pat<(i32 (X86fgetsign FR64:$src)),
2803 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2804 Requires<[UseSSE2]>;
2805 def : Pat<(i64 (X86fgetsign FR64:$src)),
2806 (SUBREG_TO_REG (i64 0),
2807 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2808 Requires<[UseSSE2]>;
2810 //===---------------------------------------------------------------------===//
2811 // SSE2 - Packed Integer Logical Instructions
2812 //===---------------------------------------------------------------------===//
2814 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2816 /// PDI_binop_rm - Simple SSE2 binary operator.
2817 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2818 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2819 X86MemOperand x86memop, OpndItins itins,
2820 bit IsCommutable, bit Is2Addr> {
2821 let isCommutable = IsCommutable in
2822 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2823 (ins RC:$src1, RC:$src2),
2825 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2826 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2827 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2828 Sched<[itins.Sched]>;
2829 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2830 (ins RC:$src1, x86memop:$src2),
2832 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2833 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2834 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2835 (bitconvert (memop_frag addr:$src2)))))],
2837 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2839 } // ExeDomain = SSEPackedInt
2841 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2842 ValueType OpVT128, ValueType OpVT256,
2843 OpndItins itins, bit IsCommutable = 0> {
2844 let Predicates = [HasAVX, NoVLX] in
2845 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2846 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2848 let Constraints = "$src1 = $dst" in
2849 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2850 memopv2i64, i128mem, itins, IsCommutable, 1>;
2852 let Predicates = [HasAVX2, NoVLX] in
2853 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2854 OpVT256, VR256, loadv4i64, i256mem, itins,
2855 IsCommutable, 0>, VEX_4V, VEX_L;
2858 // These are ordered here for pattern ordering requirements with the fp versions
2860 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2861 SSE_VEC_BIT_ITINS_P, 1>;
2862 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2863 SSE_VEC_BIT_ITINS_P, 1>;
2864 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2865 SSE_VEC_BIT_ITINS_P, 1>;
2866 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2867 SSE_VEC_BIT_ITINS_P, 0>;
2869 //===----------------------------------------------------------------------===//
2870 // SSE 1 & 2 - Logical Instructions
2871 //===----------------------------------------------------------------------===//
2873 // Multiclass for scalars using the X86 logical operation aliases for FP.
2874 multiclass sse12_fp_packed_scalar_logical_alias<
2875 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2876 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2877 FR32, f32, f128mem, loadf32_128, SSEPackedSingle, itins, 0>,
2880 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2881 FR64, f64, f128mem, loadf64_128, SSEPackedDouble, itins, 0>,
2884 let Constraints = "$src1 = $dst" in {
2885 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2886 f32, f128mem, memopfsf32_128, SSEPackedSingle, itins>, PS;
2888 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2889 f64, f128mem, memopfsf64_128, SSEPackedDouble, itins>, PD;
2893 let isCodeGenOnly = 1 in {
2894 defm FsAND : sse12_fp_packed_scalar_logical_alias<0x54, "and", X86fand,
2896 defm FsOR : sse12_fp_packed_scalar_logical_alias<0x56, "or", X86for,
2898 defm FsXOR : sse12_fp_packed_scalar_logical_alias<0x57, "xor", X86fxor,
2901 let isCommutable = 0 in
2902 defm FsANDN : sse12_fp_packed_scalar_logical_alias<0x55, "andn", X86fandn,
2906 // Multiclass for vectors using the X86 logical operation aliases for FP.
2907 multiclass sse12_fp_packed_vector_logical_alias<
2908 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2909 let Predicates = [HasAVX, NoVLX] in {
2910 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2911 VR128, v4f32, f128mem, loadv4f32, SSEPackedSingle, itins, 0>,
2914 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2915 VR128, v2f64, f128mem, loadv2f64, SSEPackedDouble, itins, 0>,
2919 let Constraints = "$src1 = $dst" in {
2920 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2921 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins>,
2924 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2925 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins>,
2930 let isCodeGenOnly = 1 in {
2931 defm FvAND : sse12_fp_packed_vector_logical_alias<0x54, "and", X86fand,
2933 defm FvOR : sse12_fp_packed_vector_logical_alias<0x56, "or", X86for,
2935 defm FvXOR : sse12_fp_packed_vector_logical_alias<0x57, "xor", X86fxor,
2938 let isCommutable = 0 in
2939 defm FvANDN : sse12_fp_packed_vector_logical_alias<0x55, "andn", X86fandn,
2943 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2945 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2947 let Predicates = [HasAVX, NoVLX] in {
2948 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2949 !strconcat(OpcodeStr, "ps"), f256mem,
2950 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2951 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2952 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2954 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2955 !strconcat(OpcodeStr, "pd"), f256mem,
2956 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2957 (bc_v4i64 (v4f64 VR256:$src2))))],
2958 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2959 (loadv4i64 addr:$src2)))], 0>,
2962 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2963 // are all promoted to v2i64, and the patterns are covered by the int
2964 // version. This is needed in SSE only, because v2i64 isn't supported on
2965 // SSE1, but only on SSE2.
2966 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2967 !strconcat(OpcodeStr, "ps"), f128mem, [],
2968 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2969 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2971 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2972 !strconcat(OpcodeStr, "pd"), f128mem,
2973 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2974 (bc_v2i64 (v2f64 VR128:$src2))))],
2975 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2976 (loadv2i64 addr:$src2)))], 0>,
2980 let Constraints = "$src1 = $dst" in {
2981 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2982 !strconcat(OpcodeStr, "ps"), f128mem,
2983 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2984 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2985 (memopv2i64 addr:$src2)))]>, PS;
2987 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2988 !strconcat(OpcodeStr, "pd"), f128mem,
2989 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2990 (bc_v2i64 (v2f64 VR128:$src2))))],
2991 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2992 (memopv2i64 addr:$src2)))]>, PD;
2996 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2997 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2998 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2999 let isCommutable = 0 in
3000 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
3002 // AVX1 requires type coercions in order to fold loads directly into logical
3004 let Predicates = [HasAVX1Only] in {
3005 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
3006 (VANDPSYrm VR256:$src1, addr:$src2)>;
3007 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3008 (VORPSYrm VR256:$src1, addr:$src2)>;
3009 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3010 (VXORPSYrm VR256:$src1, addr:$src2)>;
3011 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3012 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3015 //===----------------------------------------------------------------------===//
3016 // SSE 1 & 2 - Arithmetic Instructions
3017 //===----------------------------------------------------------------------===//
3019 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3022 /// In addition, we also have a special variant of the scalar form here to
3023 /// represent the associated intrinsic operation. This form is unlike the
3024 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3025 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3027 /// These three forms can each be reg+reg or reg+mem.
3030 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3032 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3033 SDNode OpNode, SizeItins itins> {
3034 let Predicates = [HasAVX, NoVLX] in {
3035 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3036 VR128, v4f32, f128mem, loadv4f32,
3037 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3038 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3039 VR128, v2f64, f128mem, loadv2f64,
3040 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3042 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3043 OpNode, VR256, v8f32, f256mem, loadv8f32,
3044 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3045 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3046 OpNode, VR256, v4f64, f256mem, loadv4f64,
3047 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3050 let Constraints = "$src1 = $dst" in {
3051 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3052 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3054 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3055 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3060 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3062 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3063 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3064 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3065 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3067 let Constraints = "$src1 = $dst" in {
3068 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3069 OpNode, FR32, f32mem, itins.s>, XS;
3070 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3071 OpNode, FR64, f64mem, itins.d>, XD;
3075 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3077 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3078 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3079 itins.s, 0>, XS, VEX_4V, VEX_LIG;
3080 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3081 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3082 itins.d, 0>, XD, VEX_4V, VEX_LIG;
3084 let Constraints = "$src1 = $dst" in {
3085 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3086 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3088 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3089 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3094 // Binary Arithmetic instructions
3095 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3096 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3097 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3098 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3099 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3100 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3101 let isCommutable = 0 in {
3102 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3103 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3104 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3105 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3106 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3107 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3108 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3109 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3110 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3111 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3112 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3113 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3116 let isCodeGenOnly = 1 in {
3117 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3118 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3119 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3120 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3123 // Patterns used to select SSE scalar fp arithmetic instructions from
3126 // (1) a scalar fp operation followed by a blend
3128 // The effect is that the backend no longer emits unnecessary vector
3129 // insert instructions immediately after SSE scalar fp instructions
3130 // like addss or mulss.
3132 // For example, given the following code:
3133 // __m128 foo(__m128 A, __m128 B) {
3138 // Previously we generated:
3139 // addss %xmm0, %xmm1
3140 // movss %xmm1, %xmm0
3143 // addss %xmm1, %xmm0
3145 // (2) a vector packed single/double fp operation followed by a vector insert
3147 // The effect is that the backend converts the packed fp instruction
3148 // followed by a vector insert into a single SSE scalar fp instruction.
3150 // For example, given the following code:
3151 // __m128 foo(__m128 A, __m128 B) {
3152 // __m128 C = A + B;
3153 // return (__m128) {c[0], a[1], a[2], a[3]};
3156 // Previously we generated:
3157 // addps %xmm0, %xmm1
3158 // movss %xmm1, %xmm0
3161 // addss %xmm1, %xmm0
3163 // TODO: Some canonicalization in lowering would simplify the number of
3164 // patterns we have to try to match.
3165 multiclass scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {
3166 let Predicates = [UseSSE1] in {
3167 // extracted scalar math op with insert via movss
3168 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3169 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3171 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3172 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3174 // vector math op with insert via movss
3175 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3176 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3177 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3180 // With SSE 4.1, insertps/blendi are preferred to movsd, so match those too.
3181 let Predicates = [UseSSE41] in {
3182 // extracted scalar math op with insert via insertps
3183 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3184 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3185 FR32:$src))), (iPTR 0))),
3186 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3187 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3189 // extracted scalar math op with insert via blend
3190 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3191 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3192 FR32:$src))), (i8 1))),
3193 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3194 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3196 // vector math op with insert via blend
3197 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3198 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3199 (!cast<I>(OpcPrefix#SSrr_Int)v4f32:$dst, v4f32:$src)>;
3203 // Repeat everything for AVX, except for the movss + scalar combo...
3204 // because that one shouldn't occur with AVX codegen?
3205 let Predicates = [HasAVX] in {
3206 // extracted scalar math op with insert via insertps
3207 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3208 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3209 FR32:$src))), (iPTR 0))),
3210 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst,
3211 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3213 // extracted scalar math op with insert via blend
3214 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3215 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3216 FR32:$src))), (i8 1))),
3217 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst,
3218 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3220 // vector math op with insert via movss
3221 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3222 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3223 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3225 // vector math op with insert via blend
3226 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3227 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3228 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3232 defm : scalar_math_f32_patterns<fadd, "ADD">;
3233 defm : scalar_math_f32_patterns<fsub, "SUB">;
3234 defm : scalar_math_f32_patterns<fmul, "MUL">;
3235 defm : scalar_math_f32_patterns<fdiv, "DIV">;
3237 multiclass scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {
3238 let Predicates = [UseSSE2] in {
3239 // extracted scalar math op with insert via movsd
3240 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3241 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3243 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3244 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3246 // vector math op with insert via movsd
3247 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3248 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3249 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3252 // With SSE 4.1, blendi is preferred to movsd, so match those too.
3253 let Predicates = [UseSSE41] in {
3254 // extracted scalar math op with insert via blend
3255 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3256 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3257 FR64:$src))), (i8 1))),
3258 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3259 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3261 // vector math op with insert via blend
3262 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3263 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3264 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3267 // Repeat everything for AVX.
3268 let Predicates = [HasAVX] in {
3269 // extracted scalar math op with insert via movsd
3270 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3271 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3273 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3274 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3276 // extracted scalar math op with insert via blend
3277 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3278 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3279 FR64:$src))), (i8 1))),
3280 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3281 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3283 // vector math op with insert via movsd
3284 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3285 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3286 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3288 // vector math op with insert via blend
3289 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3290 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3291 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3295 defm : scalar_math_f64_patterns<fadd, "ADD">;
3296 defm : scalar_math_f64_patterns<fsub, "SUB">;
3297 defm : scalar_math_f64_patterns<fmul, "MUL">;
3298 defm : scalar_math_f64_patterns<fdiv, "DIV">;
3302 /// In addition, we also have a special variant of the scalar form here to
3303 /// represent the associated intrinsic operation. This form is unlike the
3304 /// plain scalar form, in that it takes an entire vector (instead of a
3305 /// scalar) and leaves the top elements undefined.
3307 /// And, we have a special variant form for a full-vector intrinsic form.
3309 let Sched = WriteFSqrt in {
3310 def SSE_SQRTPS : OpndItins<
3311 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3314 def SSE_SQRTSS : OpndItins<
3315 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3318 def SSE_SQRTPD : OpndItins<
3319 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3322 def SSE_SQRTSD : OpndItins<
3323 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3327 let Sched = WriteFRsqrt in {
3328 def SSE_RSQRTPS : OpndItins<
3329 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3332 def SSE_RSQRTSS : OpndItins<
3333 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3337 let Sched = WriteFRcp in {
3338 def SSE_RCPP : OpndItins<
3339 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3342 def SSE_RCPS : OpndItins<
3343 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3347 /// sse_fp_unop_s - SSE1 unops in scalar form
3348 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3349 /// the HW instructions are 2 operand / destructive.
3350 multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3351 ValueType vt, ValueType ScalarVT,
3352 X86MemOperand x86memop, Operand vec_memop,
3353 ComplexPattern mem_cpat, Intrinsic Intr,
3354 SDNode OpNode, OpndItins itins, Predicate target,
3356 let hasSideEffects = 0 in {
3357 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
3358 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3359 [(set RC:$dst, (OpNode RC:$src1))], itins.rr>, Sched<[itins.Sched]>,
3362 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1),
3363 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3364 [(set RC:$dst, (OpNode (load addr:$src1)))], itins.rm>,
3365 Sched<[itins.Sched.Folded, ReadAfterLd]>,
3366 Requires<[target, OptForSize]>;
3368 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3369 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3370 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3371 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3373 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, vec_memop:$src2),
3374 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3375 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3379 let Predicates = [target] in {
3380 def : Pat<(vt (OpNode mem_cpat:$src)),
3381 (vt (COPY_TO_REGCLASS (vt (!cast<Instruction>(NAME#Suffix##m_Int)
3382 (vt (IMPLICIT_DEF)), mem_cpat:$src)), RC))>;
3383 // These are unary operations, but they are modeled as having 2 source operands
3384 // because the high elements of the destination are unchanged in SSE.
3385 def : Pat<(Intr VR128:$src),
3386 (!cast<Instruction>(NAME#Suffix##r_Int) VR128:$src, VR128:$src)>;
3387 def : Pat<(Intr (load addr:$src)),
3388 (vt (COPY_TO_REGCLASS(!cast<Instruction>(NAME#Suffix##m)
3389 addr:$src), VR128))>;
3390 def : Pat<(Intr mem_cpat:$src),
3391 (!cast<Instruction>(NAME#Suffix##m_Int)
3392 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3396 multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3397 ValueType vt, ValueType ScalarVT,
3398 X86MemOperand x86memop, Operand vec_memop,
3399 ComplexPattern mem_cpat,
3400 Intrinsic Intr, SDNode OpNode, OpndItins itins,
3401 Predicate target, string Suffix> {
3402 let hasSideEffects = 0 in {
3403 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3404 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3405 [], itins.rr>, Sched<[itins.Sched]>;
3407 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3408 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3409 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3410 let isCodeGenOnly = 1 in {
3411 // todo: uncomment when all r_Int forms will be added to X86InstrInfo.cpp
3412 //def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
3413 // (ins VR128:$src1, VR128:$src2),
3414 // !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3415 // []>, Sched<[itins.Sched.Folded]>;
3417 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst),
3418 (ins VR128:$src1, vec_memop:$src2),
3419 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3420 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3424 let Predicates = [target] in {
3425 def : Pat<(OpNode RC:$src), (!cast<Instruction>("V"#NAME#Suffix##r)
3426 (ScalarVT (IMPLICIT_DEF)), RC:$src)>;
3428 def : Pat<(vt (OpNode mem_cpat:$src)),
3429 (!cast<Instruction>("V"#NAME#Suffix##m_Int) (vt (IMPLICIT_DEF)),
3432 // todo: use r_Int form when it will be ready
3433 //def : Pat<(Intr VR128:$src), (!cast<Instruction>("V"#NAME#Suffix##r_Int)
3434 // (VT (IMPLICIT_DEF)), VR128:$src)>;
3435 def : Pat<(Intr VR128:$src),
3436 (vt (COPY_TO_REGCLASS(
3437 !cast<Instruction>("V"#NAME#Suffix##r) (ScalarVT (IMPLICIT_DEF)),
3438 (ScalarVT (COPY_TO_REGCLASS VR128:$src, RC))), VR128))>;
3439 def : Pat<(Intr mem_cpat:$src),
3440 (!cast<Instruction>("V"#NAME#Suffix##m_Int)
3441 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3443 let Predicates = [target, OptForSize] in
3444 def : Pat<(ScalarVT (OpNode (load addr:$src))),
3445 (!cast<Instruction>("V"#NAME#Suffix##m) (ScalarVT (IMPLICIT_DEF)),
3449 /// sse1_fp_unop_p - SSE1 unops in packed form.
3450 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3452 let Predicates = [HasAVX] in {
3453 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3454 !strconcat("v", OpcodeStr,
3455 "ps\t{$src, $dst|$dst, $src}"),
3456 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3457 itins.rr>, VEX, Sched<[itins.Sched]>;
3458 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3459 !strconcat("v", OpcodeStr,
3460 "ps\t{$src, $dst|$dst, $src}"),
3461 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3462 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3463 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3464 !strconcat("v", OpcodeStr,
3465 "ps\t{$src, $dst|$dst, $src}"),
3466 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3467 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3468 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3469 !strconcat("v", OpcodeStr,
3470 "ps\t{$src, $dst|$dst, $src}"),
3471 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3472 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3475 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3476 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3477 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3478 Sched<[itins.Sched]>;
3479 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3480 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3481 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3482 Sched<[itins.Sched.Folded]>;
3485 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3486 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3487 Intrinsic V4F32Int, Intrinsic V8F32Int,
3489 let isCodeGenOnly = 1 in {
3490 let Predicates = [HasAVX] in {
3491 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3492 !strconcat("v", OpcodeStr,
3493 "ps\t{$src, $dst|$dst, $src}"),
3494 [(set VR128:$dst, (V4F32Int VR128:$src))],
3495 itins.rr>, VEX, Sched<[itins.Sched]>;
3496 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3497 !strconcat("v", OpcodeStr,
3498 "ps\t{$src, $dst|$dst, $src}"),
3499 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3500 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3501 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3502 !strconcat("v", OpcodeStr,
3503 "ps\t{$src, $dst|$dst, $src}"),
3504 [(set VR256:$dst, (V8F32Int VR256:$src))],
3505 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3506 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3508 !strconcat("v", OpcodeStr,
3509 "ps\t{$src, $dst|$dst, $src}"),
3510 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3511 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3514 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3515 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3516 [(set VR128:$dst, (V4F32Int VR128:$src))],
3517 itins.rr>, Sched<[itins.Sched]>;
3518 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3519 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3520 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3521 itins.rm>, Sched<[itins.Sched.Folded]>;
3522 } // isCodeGenOnly = 1
3525 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3526 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3527 SDNode OpNode, OpndItins itins> {
3528 let Predicates = [HasAVX] in {
3529 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3530 !strconcat("v", OpcodeStr,
3531 "pd\t{$src, $dst|$dst, $src}"),
3532 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3533 itins.rr>, VEX, Sched<[itins.Sched]>;
3534 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3535 !strconcat("v", OpcodeStr,
3536 "pd\t{$src, $dst|$dst, $src}"),
3537 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3538 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3539 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3540 !strconcat("v", OpcodeStr,
3541 "pd\t{$src, $dst|$dst, $src}"),
3542 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3543 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3544 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3545 !strconcat("v", OpcodeStr,
3546 "pd\t{$src, $dst|$dst, $src}"),
3547 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3548 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3551 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3552 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3553 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3554 Sched<[itins.Sched]>;
3555 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3556 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3557 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3558 Sched<[itins.Sched.Folded]>;
3561 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3563 defm SS : sse_fp_unop_s<opc, OpcodeStr##ss, FR32, v4f32, f32, f32mem,
3564 ssmem, sse_load_f32,
3565 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3566 itins, UseSSE1, "SS">, XS;
3567 defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr##ss, FR32, v4f32, f32,
3568 f32mem, ssmem, sse_load_f32,
3569 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3570 itins, UseAVX, "SS">, XS, VEX_4V, VEX_LIG;
3573 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3575 defm SD : sse_fp_unop_s<opc, OpcodeStr##sd, FR64, v2f64, f64, f64mem,
3576 sdmem, sse_load_f64,
3577 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3578 OpNode, itins, UseSSE2, "SD">, XD;
3579 defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr##sd, FR64, v2f64, f64,
3580 f64mem, sdmem, sse_load_f64,
3581 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3582 OpNode, itins, UseAVX, "SD">, XD, VEX_4V, VEX_LIG;
3586 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3587 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3588 sse2_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSD>,
3589 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3591 // Reciprocal approximations. Note that these typically require refinement
3592 // in order to obtain suitable precision.
3593 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3594 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>,
3595 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3596 int_x86_avx_rsqrt_ps_256, SSE_RSQRTPS>;
3597 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3598 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3599 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3600 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3602 // There is no f64 version of the reciprocal approximation instructions.
3604 //===----------------------------------------------------------------------===//
3605 // SSE 1 & 2 - Non-temporal stores
3606 //===----------------------------------------------------------------------===//
3608 let AddedComplexity = 400 in { // Prefer non-temporal versions
3609 let SchedRW = [WriteStore] in {
3610 let Predicates = [HasAVX, NoVLX] in {
3611 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3612 (ins f128mem:$dst, VR128:$src),
3613 "movntps\t{$src, $dst|$dst, $src}",
3614 [(alignednontemporalstore (v4f32 VR128:$src),
3616 IIC_SSE_MOVNT>, VEX;
3617 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3618 (ins f128mem:$dst, VR128:$src),
3619 "movntpd\t{$src, $dst|$dst, $src}",
3620 [(alignednontemporalstore (v2f64 VR128:$src),
3622 IIC_SSE_MOVNT>, VEX;
3624 let ExeDomain = SSEPackedInt in
3625 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3626 (ins f128mem:$dst, VR128:$src),
3627 "movntdq\t{$src, $dst|$dst, $src}",
3628 [(alignednontemporalstore (v2i64 VR128:$src),
3630 IIC_SSE_MOVNT>, VEX;
3632 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3633 (ins f256mem:$dst, VR256:$src),
3634 "movntps\t{$src, $dst|$dst, $src}",
3635 [(alignednontemporalstore (v8f32 VR256:$src),
3637 IIC_SSE_MOVNT>, VEX, VEX_L;
3638 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3639 (ins f256mem:$dst, VR256:$src),
3640 "movntpd\t{$src, $dst|$dst, $src}",
3641 [(alignednontemporalstore (v4f64 VR256:$src),
3643 IIC_SSE_MOVNT>, VEX, VEX_L;
3644 let ExeDomain = SSEPackedInt in
3645 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3646 (ins f256mem:$dst, VR256:$src),
3647 "movntdq\t{$src, $dst|$dst, $src}",
3648 [(alignednontemporalstore (v4i64 VR256:$src),
3650 IIC_SSE_MOVNT>, VEX, VEX_L;
3653 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3654 "movntps\t{$src, $dst|$dst, $src}",
3655 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3657 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3658 "movntpd\t{$src, $dst|$dst, $src}",
3659 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3662 let ExeDomain = SSEPackedInt in
3663 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3664 "movntdq\t{$src, $dst|$dst, $src}",
3665 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3668 // There is no AVX form for instructions below this point
3669 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3670 "movnti{l}\t{$src, $dst|$dst, $src}",
3671 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3673 PS, Requires<[HasSSE2]>;
3674 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3675 "movnti{q}\t{$src, $dst|$dst, $src}",
3676 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3678 PS, Requires<[HasSSE2]>;
3679 } // SchedRW = [WriteStore]
3681 let Predicates = [HasAVX, NoVLX] in {
3682 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3683 (VMOVNTPSmr addr:$dst, VR128:$src)>;
3686 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3687 (MOVNTPSmr addr:$dst, VR128:$src)>;
3689 } // AddedComplexity
3691 //===----------------------------------------------------------------------===//
3692 // SSE 1 & 2 - Prefetch and memory fence
3693 //===----------------------------------------------------------------------===//
3695 // Prefetch intrinsic.
3696 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3697 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3698 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3699 IIC_SSE_PREFETCH>, TB;
3700 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3701 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3702 IIC_SSE_PREFETCH>, TB;
3703 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3704 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3705 IIC_SSE_PREFETCH>, TB;
3706 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3707 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3708 IIC_SSE_PREFETCH>, TB;
3711 // FIXME: How should flush instruction be modeled?
3712 let SchedRW = [WriteLoad] in {
3714 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3715 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3716 IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
3719 let SchedRW = [WriteNop] in {
3720 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3721 // was introduced with SSE2, it's backward compatible.
3722 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3723 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3724 OBXS, Requires<[HasSSE2]>;
3727 let SchedRW = [WriteFence] in {
3728 // Load, store, and memory fence
3729 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3730 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3731 PS, Requires<[HasSSE1]>;
3732 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3733 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3734 TB, Requires<[HasSSE2]>;
3735 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3736 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3737 TB, Requires<[HasSSE2]>;
3740 def : Pat<(X86SFence), (SFENCE)>;
3741 def : Pat<(X86LFence), (LFENCE)>;
3742 def : Pat<(X86MFence), (MFENCE)>;
3744 //===----------------------------------------------------------------------===//
3745 // SSE 1 & 2 - Load/Store XCSR register
3746 //===----------------------------------------------------------------------===//
3748 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3749 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3750 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3751 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3752 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3753 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3755 let Predicates = [UseSSE1] in {
3756 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
3757 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3758 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
3759 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3760 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3761 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
3764 //===---------------------------------------------------------------------===//
3765 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3766 //===---------------------------------------------------------------------===//
3768 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3770 let hasSideEffects = 0, SchedRW = [WriteMove] in {
3771 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3772 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3774 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3775 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3777 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3778 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3780 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3781 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3786 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3787 SchedRW = [WriteMove] in {
3788 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3789 "movdqa\t{$src, $dst|$dst, $src}", [],
3792 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3793 "movdqa\t{$src, $dst|$dst, $src}", [],
3794 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3795 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3796 "movdqu\t{$src, $dst|$dst, $src}", [],
3799 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3800 "movdqu\t{$src, $dst|$dst, $src}", [],
3801 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3804 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3805 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3806 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3807 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3809 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3810 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3812 let Predicates = [HasAVX] in {
3813 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3814 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3816 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3817 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3822 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3823 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3824 (ins i128mem:$dst, VR128:$src),
3825 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3827 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3828 (ins i256mem:$dst, VR256:$src),
3829 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3831 let Predicates = [HasAVX] in {
3832 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3833 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3835 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3836 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3841 let SchedRW = [WriteMove] in {
3842 let hasSideEffects = 0 in
3843 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3844 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3846 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3847 "movdqu\t{$src, $dst|$dst, $src}",
3848 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3851 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3852 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3853 "movdqa\t{$src, $dst|$dst, $src}", [],
3856 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3857 "movdqu\t{$src, $dst|$dst, $src}",
3858 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3862 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3863 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3864 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3865 "movdqa\t{$src, $dst|$dst, $src}",
3866 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3868 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3869 "movdqu\t{$src, $dst|$dst, $src}",
3870 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3872 XS, Requires<[UseSSE2]>;
3875 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3876 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3877 "movdqa\t{$src, $dst|$dst, $src}",
3878 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3880 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3881 "movdqu\t{$src, $dst|$dst, $src}",
3882 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3884 XS, Requires<[UseSSE2]>;
3887 } // ExeDomain = SSEPackedInt
3889 let Predicates = [HasAVX] in {
3890 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3891 (VMOVDQUmr addr:$dst, VR128:$src)>;
3892 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3893 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3895 let Predicates = [UseSSE2] in
3896 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3897 (MOVDQUmr addr:$dst, VR128:$src)>;
3899 //===---------------------------------------------------------------------===//
3900 // SSE2 - Packed Integer Arithmetic Instructions
3901 //===---------------------------------------------------------------------===//
3903 let Sched = WriteVecIMul in
3904 def SSE_PMADD : OpndItins<
3905 IIC_SSE_PMADD, IIC_SSE_PMADD
3908 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3910 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3911 RegisterClass RC, PatFrag memop_frag,
3912 X86MemOperand x86memop,
3914 bit IsCommutable = 0,
3916 let isCommutable = IsCommutable in
3917 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3918 (ins RC:$src1, RC:$src2),
3920 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3921 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3922 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3923 Sched<[itins.Sched]>;
3924 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3925 (ins RC:$src1, x86memop:$src2),
3927 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3928 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3929 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3930 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3933 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3934 Intrinsic IntId256, OpndItins itins,
3935 bit IsCommutable = 0> {
3936 let Predicates = [HasAVX] in
3937 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3938 VR128, loadv2i64, i128mem, itins,
3939 IsCommutable, 0>, VEX_4V;
3941 let Constraints = "$src1 = $dst" in
3942 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3943 i128mem, itins, IsCommutable, 1>;
3945 let Predicates = [HasAVX2] in
3946 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3947 VR256, loadv4i64, i256mem, itins,
3948 IsCommutable, 0>, VEX_4V, VEX_L;
3951 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3952 string OpcodeStr, SDNode OpNode,
3953 SDNode OpNode2, RegisterClass RC,
3954 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3955 PatFrag ld_frag, ShiftOpndItins itins,
3957 // src2 is always 128-bit
3958 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3959 (ins RC:$src1, VR128:$src2),
3961 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3962 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3963 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3964 itins.rr>, Sched<[WriteVecShift]>;
3965 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3966 (ins RC:$src1, i128mem:$src2),
3968 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3969 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3970 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3971 (bc_frag (ld_frag addr:$src2)))))], itins.rm>,
3972 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3973 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3974 (ins RC:$src1, u8imm:$src2),
3976 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3977 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3978 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3979 Sched<[WriteVecShift]>;
3982 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3983 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3984 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3985 PatFrag memop_frag, X86MemOperand x86memop,
3987 bit IsCommutable = 0, bit Is2Addr = 1> {
3988 let isCommutable = IsCommutable in
3989 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3990 (ins RC:$src1, RC:$src2),
3992 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3993 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3994 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
3995 Sched<[itins.Sched]>;
3996 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3997 (ins RC:$src1, x86memop:$src2),
3999 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4000 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4001 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4002 (bitconvert (memop_frag addr:$src2)))))]>,
4003 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4005 } // ExeDomain = SSEPackedInt
4007 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4008 SSE_INTALU_ITINS_P, 1>;
4009 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4010 SSE_INTALU_ITINS_P, 1>;
4011 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4012 SSE_INTALU_ITINS_P, 1>;
4013 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4014 SSE_INTALUQ_ITINS_P, 1>;
4015 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4016 SSE_INTMUL_ITINS_P, 1>;
4017 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4018 SSE_INTMUL_ITINS_P, 1>;
4019 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4020 SSE_INTMUL_ITINS_P, 1>;
4021 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4022 SSE_INTALU_ITINS_P, 0>;
4023 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4024 SSE_INTALU_ITINS_P, 0>;
4025 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4026 SSE_INTALU_ITINS_P, 0>;
4027 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4028 SSE_INTALUQ_ITINS_P, 0>;
4029 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4030 SSE_INTALU_ITINS_P, 0>;
4031 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4032 SSE_INTALU_ITINS_P, 0>;
4033 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4034 SSE_INTALU_ITINS_P, 1>;
4035 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4036 SSE_INTALU_ITINS_P, 1>;
4037 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4038 SSE_INTALU_ITINS_P, 1>;
4039 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4040 SSE_INTALU_ITINS_P, 1>;
4043 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4044 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4045 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4046 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4047 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4048 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4049 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4050 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4051 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4052 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4053 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4054 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4055 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4056 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4057 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4058 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4059 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4060 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4061 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4062 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4064 let Predicates = [HasAVX] in
4065 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4066 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4068 let Predicates = [HasAVX2] in
4069 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4070 VR256, loadv4i64, i256mem,
4071 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4072 let Constraints = "$src1 = $dst" in
4073 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4074 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4076 //===---------------------------------------------------------------------===//
4077 // SSE2 - Packed Integer Logical Instructions
4078 //===---------------------------------------------------------------------===//
4080 let Predicates = [HasAVX] in {
4081 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4082 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4083 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4084 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4085 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4086 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4087 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4088 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4089 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4091 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4092 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4093 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4094 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4095 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4096 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4097 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4098 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4099 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4101 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4102 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4103 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4104 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4105 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4106 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4108 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4109 // 128-bit logical shifts.
4110 def VPSLLDQri : PDIi8<0x73, MRM7r,
4111 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4112 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4114 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))]>,
4116 def VPSRLDQri : PDIi8<0x73, MRM3r,
4117 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4118 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4120 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))]>,
4122 // PSRADQri doesn't exist in SSE[1-3].
4124 } // Predicates = [HasAVX]
4126 let Predicates = [HasAVX2] in {
4127 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4128 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4129 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4130 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4131 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4132 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4133 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4134 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4135 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4137 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4138 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4139 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4140 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4141 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4142 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4143 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4144 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4145 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4147 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4148 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4149 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4150 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4151 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4152 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4154 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4155 // 256-bit logical shifts.
4156 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4157 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4158 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4160 (v4i64 (X86vshldq VR256:$src1, (i8 imm:$src2))))]>,
4162 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4163 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4164 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4166 (v4i64 (X86vshrdq VR256:$src1, (i8 imm:$src2))))]>,
4168 // PSRADQYri doesn't exist in SSE[1-3].
4170 } // Predicates = [HasAVX2]
4172 let Constraints = "$src1 = $dst" in {
4173 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4174 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4175 SSE_INTSHIFT_ITINS_P>;
4176 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4177 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4178 SSE_INTSHIFT_ITINS_P>;
4179 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4180 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4181 SSE_INTSHIFT_ITINS_P>;
4183 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4184 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4185 SSE_INTSHIFT_ITINS_P>;
4186 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4187 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4188 SSE_INTSHIFT_ITINS_P>;
4189 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4190 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4191 SSE_INTSHIFT_ITINS_P>;
4193 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4194 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4195 SSE_INTSHIFT_ITINS_P>;
4196 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4197 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4198 SSE_INTSHIFT_ITINS_P>;
4200 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4201 // 128-bit logical shifts.
4202 def PSLLDQri : PDIi8<0x73, MRM7r,
4203 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4204 "pslldq\t{$src2, $dst|$dst, $src2}",
4206 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))],
4207 IIC_SSE_INTSHDQ_P_RI>;
4208 def PSRLDQri : PDIi8<0x73, MRM3r,
4209 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4210 "psrldq\t{$src2, $dst|$dst, $src2}",
4212 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))],
4213 IIC_SSE_INTSHDQ_P_RI>;
4214 // PSRADQri doesn't exist in SSE[1-3].
4216 } // Constraints = "$src1 = $dst"
4218 let Predicates = [HasAVX] in {
4219 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4220 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4223 let Predicates = [UseSSE2] in {
4224 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4225 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4228 //===---------------------------------------------------------------------===//
4229 // SSE2 - Packed Integer Comparison Instructions
4230 //===---------------------------------------------------------------------===//
4232 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4233 SSE_INTALU_ITINS_P, 1>;
4234 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4235 SSE_INTALU_ITINS_P, 1>;
4236 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4237 SSE_INTALU_ITINS_P, 1>;
4238 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4239 SSE_INTALU_ITINS_P, 0>;
4240 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4241 SSE_INTALU_ITINS_P, 0>;
4242 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4243 SSE_INTALU_ITINS_P, 0>;
4245 //===---------------------------------------------------------------------===//
4246 // SSE2 - Packed Integer Shuffle Instructions
4247 //===---------------------------------------------------------------------===//
4249 let ExeDomain = SSEPackedInt in {
4250 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4252 let Predicates = [HasAVX] in {
4253 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4254 (ins VR128:$src1, u8imm:$src2),
4255 !strconcat("v", OpcodeStr,
4256 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4258 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4259 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4260 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4261 (ins i128mem:$src1, u8imm:$src2),
4262 !strconcat("v", OpcodeStr,
4263 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4265 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4266 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4267 Sched<[WriteShuffleLd]>;
4270 let Predicates = [HasAVX2] in {
4271 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4272 (ins VR256:$src1, u8imm:$src2),
4273 !strconcat("v", OpcodeStr,
4274 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4276 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4277 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4278 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4279 (ins i256mem:$src1, u8imm:$src2),
4280 !strconcat("v", OpcodeStr,
4281 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4283 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4284 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4285 Sched<[WriteShuffleLd]>;
4288 let Predicates = [UseSSE2] in {
4289 def ri : Ii8<0x70, MRMSrcReg,
4290 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4291 !strconcat(OpcodeStr,
4292 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4294 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4295 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4296 def mi : Ii8<0x70, MRMSrcMem,
4297 (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2),
4298 !strconcat(OpcodeStr,
4299 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4301 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4302 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4303 Sched<[WriteShuffleLd, ReadAfterLd]>;
4306 } // ExeDomain = SSEPackedInt
4308 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4309 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4310 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4312 let Predicates = [HasAVX] in {
4313 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4314 (VPSHUFDmi addr:$src1, imm:$imm)>;
4315 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4316 (VPSHUFDri VR128:$src1, imm:$imm)>;
4319 let Predicates = [UseSSE2] in {
4320 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4321 (PSHUFDmi addr:$src1, imm:$imm)>;
4322 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4323 (PSHUFDri VR128:$src1, imm:$imm)>;
4326 //===---------------------------------------------------------------------===//
4327 // Packed Integer Pack Instructions (SSE & AVX)
4328 //===---------------------------------------------------------------------===//
4330 let ExeDomain = SSEPackedInt in {
4331 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4332 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4333 PatFrag ld_frag, bit Is2Addr = 1> {
4334 def rr : PDI<opc, MRMSrcReg,
4335 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4337 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4338 !strconcat(OpcodeStr,
4339 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4341 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4342 Sched<[WriteShuffle]>;
4343 def rm : PDI<opc, MRMSrcMem,
4344 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4347 !strconcat(OpcodeStr,
4348 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4350 (OutVT (OpNode VR128:$src1,
4351 (bc_frag (ld_frag addr:$src2)))))]>,
4352 Sched<[WriteShuffleLd, ReadAfterLd]>;
4355 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4356 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4357 def Yrr : PDI<opc, MRMSrcReg,
4358 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4359 !strconcat(OpcodeStr,
4360 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4362 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4363 Sched<[WriteShuffle]>;
4364 def Yrm : PDI<opc, MRMSrcMem,
4365 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4366 !strconcat(OpcodeStr,
4367 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4369 (OutVT (OpNode VR256:$src1,
4370 (bc_frag (loadv4i64 addr:$src2)))))]>,
4371 Sched<[WriteShuffleLd, ReadAfterLd]>;
4374 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4375 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4376 PatFrag ld_frag, bit Is2Addr = 1> {
4377 def rr : SS48I<opc, MRMSrcReg,
4378 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4380 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4381 !strconcat(OpcodeStr,
4382 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4384 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4385 Sched<[WriteShuffle]>;
4386 def rm : SS48I<opc, MRMSrcMem,
4387 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4389 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4390 !strconcat(OpcodeStr,
4391 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4393 (OutVT (OpNode VR128:$src1,
4394 (bc_frag (ld_frag addr:$src2)))))]>,
4395 Sched<[WriteShuffleLd, ReadAfterLd]>;
4398 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4399 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4400 def Yrr : SS48I<opc, MRMSrcReg,
4401 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4402 !strconcat(OpcodeStr,
4403 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4405 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4406 Sched<[WriteShuffle]>;
4407 def Yrm : SS48I<opc, MRMSrcMem,
4408 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4409 !strconcat(OpcodeStr,
4410 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4412 (OutVT (OpNode VR256:$src1,
4413 (bc_frag (loadv4i64 addr:$src2)))))]>,
4414 Sched<[WriteShuffleLd, ReadAfterLd]>;
4417 let Predicates = [HasAVX] in {
4418 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4419 bc_v8i16, loadv2i64, 0>, VEX_4V;
4420 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4421 bc_v4i32, loadv2i64, 0>, VEX_4V;
4423 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4424 bc_v8i16, loadv2i64, 0>, VEX_4V;
4425 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4426 bc_v4i32, loadv2i64, 0>, VEX_4V;
4429 let Predicates = [HasAVX2] in {
4430 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4431 bc_v16i16>, VEX_4V, VEX_L;
4432 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4433 bc_v8i32>, VEX_4V, VEX_L;
4435 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4436 bc_v16i16>, VEX_4V, VEX_L;
4437 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4438 bc_v8i32>, VEX_4V, VEX_L;
4441 let Constraints = "$src1 = $dst" in {
4442 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4443 bc_v8i16, memopv2i64>;
4444 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4445 bc_v4i32, memopv2i64>;
4447 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4448 bc_v8i16, memopv2i64>;
4450 let Predicates = [HasSSE41] in
4451 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4452 bc_v4i32, memopv2i64>;
4454 } // ExeDomain = SSEPackedInt
4456 //===---------------------------------------------------------------------===//
4457 // SSE2 - Packed Integer Unpack Instructions
4458 //===---------------------------------------------------------------------===//
4460 let ExeDomain = SSEPackedInt in {
4461 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4462 SDNode OpNode, PatFrag bc_frag, PatFrag ld_frag,
4464 def rr : PDI<opc, MRMSrcReg,
4465 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4467 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4468 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4469 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4470 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4471 def rm : PDI<opc, MRMSrcMem,
4472 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4474 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4475 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4476 [(set VR128:$dst, (OpNode VR128:$src1,
4477 (bc_frag (ld_frag addr:$src2))))],
4479 Sched<[WriteShuffleLd, ReadAfterLd]>;
4482 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4483 SDNode OpNode, PatFrag bc_frag> {
4484 def Yrr : PDI<opc, MRMSrcReg,
4485 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4486 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4487 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4488 Sched<[WriteShuffle]>;
4489 def Yrm : PDI<opc, MRMSrcMem,
4490 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4491 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4492 [(set VR256:$dst, (OpNode VR256:$src1,
4493 (bc_frag (loadv4i64 addr:$src2))))]>,
4494 Sched<[WriteShuffleLd, ReadAfterLd]>;
4497 let Predicates = [HasAVX] in {
4498 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4499 bc_v16i8, loadv2i64, 0>, VEX_4V;
4500 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4501 bc_v8i16, loadv2i64, 0>, VEX_4V;
4502 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4503 bc_v4i32, loadv2i64, 0>, VEX_4V;
4504 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4505 bc_v2i64, loadv2i64, 0>, VEX_4V;
4507 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4508 bc_v16i8, loadv2i64, 0>, VEX_4V;
4509 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4510 bc_v8i16, loadv2i64, 0>, VEX_4V;
4511 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4512 bc_v4i32, loadv2i64, 0>, VEX_4V;
4513 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4514 bc_v2i64, loadv2i64, 0>, VEX_4V;
4517 let Predicates = [HasAVX2] in {
4518 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4519 bc_v32i8>, VEX_4V, VEX_L;
4520 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4521 bc_v16i16>, VEX_4V, VEX_L;
4522 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4523 bc_v8i32>, VEX_4V, VEX_L;
4524 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4525 bc_v4i64>, VEX_4V, VEX_L;
4527 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4528 bc_v32i8>, VEX_4V, VEX_L;
4529 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4530 bc_v16i16>, VEX_4V, VEX_L;
4531 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4532 bc_v8i32>, VEX_4V, VEX_L;
4533 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4534 bc_v4i64>, VEX_4V, VEX_L;
4537 let Constraints = "$src1 = $dst" in {
4538 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4539 bc_v16i8, memopv2i64>;
4540 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4541 bc_v8i16, memopv2i64>;
4542 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4543 bc_v4i32, memopv2i64>;
4544 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4545 bc_v2i64, memopv2i64>;
4547 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4548 bc_v16i8, memopv2i64>;
4549 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4550 bc_v8i16, memopv2i64>;
4551 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4552 bc_v4i32, memopv2i64>;
4553 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4554 bc_v2i64, memopv2i64>;
4556 } // ExeDomain = SSEPackedInt
4558 //===---------------------------------------------------------------------===//
4559 // SSE2 - Packed Integer Extract and Insert
4560 //===---------------------------------------------------------------------===//
4562 let ExeDomain = SSEPackedInt in {
4563 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4564 def rri : Ii8<0xC4, MRMSrcReg,
4565 (outs VR128:$dst), (ins VR128:$src1,
4566 GR32orGR64:$src2, u8imm:$src3),
4568 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4569 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4571 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4572 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4573 def rmi : Ii8<0xC4, MRMSrcMem,
4574 (outs VR128:$dst), (ins VR128:$src1,
4575 i16mem:$src2, u8imm:$src3),
4577 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4578 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4580 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4581 imm:$src3))], IIC_SSE_PINSRW>,
4582 Sched<[WriteShuffleLd, ReadAfterLd]>;
4586 let Predicates = [HasAVX] in
4587 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4588 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4589 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4590 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4591 imm:$src2))]>, PD, VEX,
4592 Sched<[WriteShuffle]>;
4593 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4594 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4595 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4596 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4597 imm:$src2))], IIC_SSE_PEXTRW>,
4598 Sched<[WriteShuffleLd, ReadAfterLd]>;
4601 let Predicates = [HasAVX] in
4602 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4604 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4605 defm PINSRW : sse2_pinsrw, PD;
4607 } // ExeDomain = SSEPackedInt
4609 //===---------------------------------------------------------------------===//
4610 // SSE2 - Packed Mask Creation
4611 //===---------------------------------------------------------------------===//
4613 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4615 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4617 "pmovmskb\t{$src, $dst|$dst, $src}",
4618 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4619 IIC_SSE_MOVMSK>, VEX;
4621 let Predicates = [HasAVX2] in {
4622 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4624 "pmovmskb\t{$src, $dst|$dst, $src}",
4625 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4629 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4630 "pmovmskb\t{$src, $dst|$dst, $src}",
4631 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4634 } // ExeDomain = SSEPackedInt
4636 //===---------------------------------------------------------------------===//
4637 // SSE2 - Conditional Store
4638 //===---------------------------------------------------------------------===//
4640 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4642 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4643 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4644 (ins VR128:$src, VR128:$mask),
4645 "maskmovdqu\t{$mask, $src|$src, $mask}",
4646 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4647 IIC_SSE_MASKMOV>, VEX;
4648 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4649 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4650 (ins VR128:$src, VR128:$mask),
4651 "maskmovdqu\t{$mask, $src|$src, $mask}",
4652 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4653 IIC_SSE_MASKMOV>, VEX;
4655 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4656 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4657 "maskmovdqu\t{$mask, $src|$src, $mask}",
4658 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4660 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4661 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4662 "maskmovdqu\t{$mask, $src|$src, $mask}",
4663 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4666 } // ExeDomain = SSEPackedInt
4668 //===---------------------------------------------------------------------===//
4669 // SSE2 - Move Doubleword
4670 //===---------------------------------------------------------------------===//
4672 //===---------------------------------------------------------------------===//
4673 // Move Int Doubleword to Packed Double Int
4675 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4676 "movd\t{$src, $dst|$dst, $src}",
4678 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4679 VEX, Sched<[WriteMove]>;
4680 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4681 "movd\t{$src, $dst|$dst, $src}",
4683 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4685 VEX, Sched<[WriteLoad]>;
4686 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4687 "movq\t{$src, $dst|$dst, $src}",
4689 (v2i64 (scalar_to_vector GR64:$src)))],
4690 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4691 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4692 def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4693 "movq\t{$src, $dst|$dst, $src}",
4694 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteLoad]>;
4695 let isCodeGenOnly = 1 in
4696 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4697 "movq\t{$src, $dst|$dst, $src}",
4698 [(set FR64:$dst, (bitconvert GR64:$src))],
4699 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4701 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4702 "movd\t{$src, $dst|$dst, $src}",
4704 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4706 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4707 "movd\t{$src, $dst|$dst, $src}",
4709 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4710 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4711 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4712 "mov{d|q}\t{$src, $dst|$dst, $src}",
4714 (v2i64 (scalar_to_vector GR64:$src)))],
4715 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4716 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4717 def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4718 "mov{d|q}\t{$src, $dst|$dst, $src}",
4719 [], IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4720 let isCodeGenOnly = 1 in
4721 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4722 "mov{d|q}\t{$src, $dst|$dst, $src}",
4723 [(set FR64:$dst, (bitconvert GR64:$src))],
4724 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4726 //===---------------------------------------------------------------------===//
4727 // Move Int Doubleword to Single Scalar
4729 let isCodeGenOnly = 1 in {
4730 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4731 "movd\t{$src, $dst|$dst, $src}",
4732 [(set FR32:$dst, (bitconvert GR32:$src))],
4733 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4735 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4736 "movd\t{$src, $dst|$dst, $src}",
4737 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4739 VEX, Sched<[WriteLoad]>;
4740 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4741 "movd\t{$src, $dst|$dst, $src}",
4742 [(set FR32:$dst, (bitconvert GR32:$src))],
4743 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4745 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4746 "movd\t{$src, $dst|$dst, $src}",
4747 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4748 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4751 //===---------------------------------------------------------------------===//
4752 // Move Packed Doubleword Int to Packed Double Int
4754 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4755 "movd\t{$src, $dst|$dst, $src}",
4756 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4757 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4759 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4760 (ins i32mem:$dst, VR128:$src),
4761 "movd\t{$src, $dst|$dst, $src}",
4762 [(store (i32 (vector_extract (v4i32 VR128:$src),
4763 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4764 VEX, Sched<[WriteStore]>;
4765 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4766 "movd\t{$src, $dst|$dst, $src}",
4767 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4768 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4770 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4771 "movd\t{$src, $dst|$dst, $src}",
4772 [(store (i32 (vector_extract (v4i32 VR128:$src),
4773 (iPTR 0))), addr:$dst)],
4774 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4776 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4777 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4779 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4780 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4782 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4783 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4785 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4786 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4788 //===---------------------------------------------------------------------===//
4789 // Move Packed Doubleword Int first element to Doubleword Int
4791 let SchedRW = [WriteMove] in {
4792 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4793 "movq\t{$src, $dst|$dst, $src}",
4794 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4799 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4800 "mov{d|q}\t{$src, $dst|$dst, $src}",
4801 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4806 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4807 def VMOVPQIto64rm : VRS2I<0x7E, MRMDestMem, (outs i64mem:$dst),
4808 (ins VR128:$src), "movq\t{$src, $dst|$dst, $src}",
4809 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4810 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4811 def MOVPQIto64rm : RS2I<0x7E, MRMDestMem, (outs i64mem:$dst), (ins VR128:$src),
4812 "mov{d|q}\t{$src, $dst|$dst, $src}",
4813 [], IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4815 //===---------------------------------------------------------------------===//
4816 // Bitcast FR64 <-> GR64
4818 let isCodeGenOnly = 1 in {
4819 let Predicates = [UseAVX] in
4820 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4821 "movq\t{$src, $dst|$dst, $src}",
4822 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4823 VEX, Sched<[WriteLoad]>;
4824 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4825 "movq\t{$src, $dst|$dst, $src}",
4826 [(set GR64:$dst, (bitconvert FR64:$src))],
4827 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4828 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4829 "movq\t{$src, $dst|$dst, $src}",
4830 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4831 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4833 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4834 "movq\t{$src, $dst|$dst, $src}",
4835 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4836 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4837 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4838 "mov{d|q}\t{$src, $dst|$dst, $src}",
4839 [(set GR64:$dst, (bitconvert FR64:$src))],
4840 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4841 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4842 "movq\t{$src, $dst|$dst, $src}",
4843 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4844 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4847 //===---------------------------------------------------------------------===//
4848 // Move Scalar Single to Double Int
4850 let isCodeGenOnly = 1 in {
4851 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4852 "movd\t{$src, $dst|$dst, $src}",
4853 [(set GR32:$dst, (bitconvert FR32:$src))],
4854 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4855 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4856 "movd\t{$src, $dst|$dst, $src}",
4857 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4858 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4859 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4860 "movd\t{$src, $dst|$dst, $src}",
4861 [(set GR32:$dst, (bitconvert FR32:$src))],
4862 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4863 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4864 "movd\t{$src, $dst|$dst, $src}",
4865 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4866 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4869 //===---------------------------------------------------------------------===//
4870 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4872 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4873 let AddedComplexity = 15 in {
4874 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4875 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4876 [(set VR128:$dst, (v2i64 (X86vzmovl
4877 (v2i64 (scalar_to_vector GR64:$src)))))],
4880 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4881 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4882 [(set VR128:$dst, (v2i64 (X86vzmovl
4883 (v2i64 (scalar_to_vector GR64:$src)))))],
4886 } // isCodeGenOnly, SchedRW
4888 let Predicates = [UseAVX] in {
4889 let AddedComplexity = 15 in
4890 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4891 (VMOVDI2PDIrr GR32:$src)>;
4893 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4894 let AddedComplexity = 20 in {
4895 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4896 (VMOVDI2PDIrm addr:$src)>;
4897 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4898 (VMOVDI2PDIrm addr:$src)>;
4899 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4900 (VMOVDI2PDIrm addr:$src)>;
4902 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4903 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4904 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4905 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4906 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4907 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4908 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4911 let Predicates = [UseSSE2] in {
4912 let AddedComplexity = 15 in
4913 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4914 (MOVDI2PDIrr GR32:$src)>;
4916 let AddedComplexity = 20 in {
4917 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4918 (MOVDI2PDIrm addr:$src)>;
4919 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4920 (MOVDI2PDIrm addr:$src)>;
4921 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4922 (MOVDI2PDIrm addr:$src)>;
4926 // These are the correct encodings of the instructions so that we know how to
4927 // read correct assembly, even though we continue to emit the wrong ones for
4928 // compatibility with Darwin's buggy assembler.
4929 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4930 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4931 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4932 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4933 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4934 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4935 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4936 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4937 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4939 //===---------------------------------------------------------------------===//
4940 // SSE2 - Move Quadword
4941 //===---------------------------------------------------------------------===//
4943 //===---------------------------------------------------------------------===//
4944 // Move Quadword Int to Packed Quadword Int
4947 let ExeDomain = SSEPackedInt, SchedRW = [WriteLoad] in {
4948 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4949 "vmovq\t{$src, $dst|$dst, $src}",
4951 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4952 VEX, Requires<[UseAVX]>;
4953 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4954 "movq\t{$src, $dst|$dst, $src}",
4956 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4958 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4959 } // ExeDomain, SchedRW
4961 //===---------------------------------------------------------------------===//
4962 // Move Packed Quadword Int to Quadword Int
4964 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4965 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4966 "movq\t{$src, $dst|$dst, $src}",
4967 [(store (i64 (vector_extract (v2i64 VR128:$src),
4968 (iPTR 0))), addr:$dst)],
4969 IIC_SSE_MOVDQ>, VEX;
4970 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4971 "movq\t{$src, $dst|$dst, $src}",
4972 [(store (i64 (vector_extract (v2i64 VR128:$src),
4973 (iPTR 0))), addr:$dst)],
4975 } // ExeDomain, SchedRW
4977 // For disassembler only
4978 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4979 SchedRW = [WriteVecLogic] in {
4980 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4981 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
4982 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4983 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
4986 //===---------------------------------------------------------------------===//
4987 // Store / copy lower 64-bits of a XMM register.
4989 let Predicates = [UseAVX] in
4990 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
4991 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
4992 let Predicates = [UseSSE2] in
4993 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
4994 (MOVPQI2QImr addr:$dst, VR128:$src)>;
4996 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, AddedComplexity = 20 in {
4997 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4998 "vmovq\t{$src, $dst|$dst, $src}",
5000 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5001 (loadi64 addr:$src))))))],
5003 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5005 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5006 "movq\t{$src, $dst|$dst, $src}",
5008 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5009 (loadi64 addr:$src))))))],
5011 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5012 } // ExeDomain, isCodeGenOnly, AddedComplexity
5014 let Predicates = [UseAVX], AddedComplexity = 20 in {
5015 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5016 (VMOVZQI2PQIrm addr:$src)>;
5017 def : Pat<(v2i64 (X86vzload addr:$src)),
5018 (VMOVZQI2PQIrm addr:$src)>;
5021 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5022 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5023 (MOVZQI2PQIrm addr:$src)>;
5024 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5027 let Predicates = [HasAVX] in {
5028 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5029 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5030 def : Pat<(v4i64 (X86vzload addr:$src)),
5031 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5034 //===---------------------------------------------------------------------===//
5035 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5036 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5038 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
5039 let AddedComplexity = 15 in
5040 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5041 "vmovq\t{$src, $dst|$dst, $src}",
5042 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5044 XS, VEX, Requires<[UseAVX]>;
5045 let AddedComplexity = 15 in
5046 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5047 "movq\t{$src, $dst|$dst, $src}",
5048 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5050 XS, Requires<[UseSSE2]>;
5051 } // ExeDomain, SchedRW
5053 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5054 let AddedComplexity = 20 in
5055 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5056 "vmovq\t{$src, $dst|$dst, $src}",
5057 [(set VR128:$dst, (v2i64 (X86vzmovl
5058 (loadv2i64 addr:$src))))],
5060 XS, VEX, Requires<[UseAVX]>;
5061 let AddedComplexity = 20 in {
5062 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5063 "movq\t{$src, $dst|$dst, $src}",
5064 [(set VR128:$dst, (v2i64 (X86vzmovl
5065 (loadv2i64 addr:$src))))],
5067 XS, Requires<[UseSSE2]>;
5069 } // ExeDomain, isCodeGenOnly, SchedRW
5071 let AddedComplexity = 20 in {
5072 let Predicates = [UseAVX] in {
5073 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5074 (VMOVZPQILo2PQIrr VR128:$src)>;
5076 let Predicates = [UseSSE2] in {
5077 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5078 (MOVZPQILo2PQIrr VR128:$src)>;
5082 //===---------------------------------------------------------------------===//
5083 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5084 //===---------------------------------------------------------------------===//
5085 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5086 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5087 X86MemOperand x86memop> {
5088 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5089 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5090 [(set RC:$dst, (vt (OpNode RC:$src)))],
5091 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5092 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5093 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5094 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5095 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5098 let Predicates = [HasAVX] in {
5099 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5100 v4f32, VR128, loadv4f32, f128mem>, VEX;
5101 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5102 v4f32, VR128, loadv4f32, f128mem>, VEX;
5103 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5104 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5105 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5106 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5108 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5109 memopv4f32, f128mem>;
5110 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5111 memopv4f32, f128mem>;
5113 let Predicates = [HasAVX] in {
5114 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5115 (VMOVSHDUPrr VR128:$src)>;
5116 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5117 (VMOVSHDUPrm addr:$src)>;
5118 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5119 (VMOVSLDUPrr VR128:$src)>;
5120 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5121 (VMOVSLDUPrm addr:$src)>;
5122 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5123 (VMOVSHDUPYrr VR256:$src)>;
5124 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5125 (VMOVSHDUPYrm addr:$src)>;
5126 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5127 (VMOVSLDUPYrr VR256:$src)>;
5128 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5129 (VMOVSLDUPYrm addr:$src)>;
5132 let Predicates = [UseSSE3] in {
5133 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5134 (MOVSHDUPrr VR128:$src)>;
5135 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5136 (MOVSHDUPrm addr:$src)>;
5137 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5138 (MOVSLDUPrr VR128:$src)>;
5139 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5140 (MOVSLDUPrm addr:$src)>;
5143 //===---------------------------------------------------------------------===//
5144 // SSE3 - Replicate Double FP - MOVDDUP
5145 //===---------------------------------------------------------------------===//
5147 multiclass sse3_replicate_dfp<string OpcodeStr> {
5148 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5149 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5150 [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))],
5151 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5152 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5153 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5156 (scalar_to_vector (loadf64 addr:$src)))))],
5157 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5160 // FIXME: Merge with above classe when there're patterns for the ymm version
5161 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5162 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5163 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5164 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5165 Sched<[WriteFShuffle]>;
5166 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5167 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5170 (scalar_to_vector (loadf64 addr:$src)))))]>,
5174 let Predicates = [HasAVX] in {
5175 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5176 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5179 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5181 let Predicates = [HasAVX] in {
5182 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5183 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5184 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5185 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5186 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5187 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5188 def : Pat<(X86Movddup (bc_v2f64
5189 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5190 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5193 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5194 (VMOVDDUPYrm addr:$src)>;
5195 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5196 (VMOVDDUPYrm addr:$src)>;
5197 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5198 (VMOVDDUPYrm addr:$src)>;
5199 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5200 (VMOVDDUPYrr VR256:$src)>;
5203 let Predicates = [UseAVX, OptForSize] in {
5204 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5205 (VMOVDDUPrm addr:$src)>;
5206 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5207 (VMOVDDUPrm addr:$src)>;
5210 let Predicates = [UseSSE3] in {
5211 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5212 (MOVDDUPrm addr:$src)>;
5213 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5214 (MOVDDUPrm addr:$src)>;
5215 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5216 (MOVDDUPrm addr:$src)>;
5217 def : Pat<(X86Movddup (bc_v2f64
5218 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5219 (MOVDDUPrm addr:$src)>;
5222 //===---------------------------------------------------------------------===//
5223 // SSE3 - Move Unaligned Integer
5224 //===---------------------------------------------------------------------===//
5226 let SchedRW = [WriteLoad] in {
5227 let Predicates = [HasAVX] in {
5228 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5229 "vlddqu\t{$src, $dst|$dst, $src}",
5230 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5231 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5232 "vlddqu\t{$src, $dst|$dst, $src}",
5233 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5236 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5237 "lddqu\t{$src, $dst|$dst, $src}",
5238 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5242 //===---------------------------------------------------------------------===//
5243 // SSE3 - Arithmetic
5244 //===---------------------------------------------------------------------===//
5246 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5247 X86MemOperand x86memop, OpndItins itins,
5248 PatFrag ld_frag, bit Is2Addr = 1> {
5249 def rr : I<0xD0, MRMSrcReg,
5250 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5252 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5253 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5254 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5255 Sched<[itins.Sched]>;
5256 def rm : I<0xD0, MRMSrcMem,
5257 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5259 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5260 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5261 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))], itins.rr>,
5262 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5265 let Predicates = [HasAVX] in {
5266 let ExeDomain = SSEPackedSingle in {
5267 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5268 f128mem, SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V;
5269 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5270 f256mem, SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V, VEX_L;
5272 let ExeDomain = SSEPackedDouble in {
5273 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5274 f128mem, SSE_ALU_F64P, loadv2f64, 0>, PD, VEX_4V;
5275 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5276 f256mem, SSE_ALU_F64P, loadv4f64, 0>, PD, VEX_4V, VEX_L;
5279 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5280 let ExeDomain = SSEPackedSingle in
5281 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5282 f128mem, SSE_ALU_F32P, memopv4f32>, XD;
5283 let ExeDomain = SSEPackedDouble in
5284 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5285 f128mem, SSE_ALU_F64P, memopv2f64>, PD;
5288 // Patterns used to select 'addsub' instructions.
5289 let Predicates = [HasAVX] in {
5290 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5291 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5292 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (loadv4f32 addr:$rhs))),
5293 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5294 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5295 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5296 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (loadv2f64 addr:$rhs))),
5297 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5299 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5300 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5301 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (loadv8f32 addr:$rhs))),
5302 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5303 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5304 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5305 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (loadv4f64 addr:$rhs))),
5306 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5309 let Predicates = [UseSSE3] in {
5310 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5311 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5312 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (memopv4f32 addr:$rhs))),
5313 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5314 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5315 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5316 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (memopv2f64 addr:$rhs))),
5317 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5320 //===---------------------------------------------------------------------===//
5321 // SSE3 Instructions
5322 //===---------------------------------------------------------------------===//
5325 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5326 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5328 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5330 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5331 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5332 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5335 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5337 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5338 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5339 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5340 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5342 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5343 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5345 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5347 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5348 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5349 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5352 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5354 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5355 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5356 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5357 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5360 let Predicates = [HasAVX] in {
5361 let ExeDomain = SSEPackedSingle in {
5362 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5363 X86fhadd, loadv4f32, 0>, VEX_4V;
5364 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5365 X86fhsub, loadv4f32, 0>, VEX_4V;
5366 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5367 X86fhadd, loadv8f32, 0>, VEX_4V, VEX_L;
5368 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5369 X86fhsub, loadv8f32, 0>, VEX_4V, VEX_L;
5371 let ExeDomain = SSEPackedDouble in {
5372 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5373 X86fhadd, loadv2f64, 0>, VEX_4V;
5374 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5375 X86fhsub, loadv2f64, 0>, VEX_4V;
5376 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5377 X86fhadd, loadv4f64, 0>, VEX_4V, VEX_L;
5378 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5379 X86fhsub, loadv4f64, 0>, VEX_4V, VEX_L;
5383 let Constraints = "$src1 = $dst" in {
5384 let ExeDomain = SSEPackedSingle in {
5385 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd,
5387 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub,
5390 let ExeDomain = SSEPackedDouble in {
5391 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd,
5393 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub,
5398 //===---------------------------------------------------------------------===//
5399 // SSSE3 - Packed Absolute Instructions
5400 //===---------------------------------------------------------------------===//
5403 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5404 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
5406 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5408 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5409 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5410 Sched<[WriteVecALU]>;
5412 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5414 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5417 (bitconvert (ld_frag addr:$src))))], IIC_SSE_PABS_RM>,
5418 Sched<[WriteVecALULd]>;
5421 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5422 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5423 Intrinsic IntId256> {
5424 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5426 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5427 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5428 Sched<[WriteVecALU]>;
5430 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5432 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5435 (bitconvert (loadv4i64 addr:$src))))]>,
5436 Sched<[WriteVecALULd]>;
5439 // Helper fragments to match sext vXi1 to vXiY.
5440 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5442 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5443 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5444 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5446 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5447 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5449 let Predicates = [HasAVX] in {
5450 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", int_x86_ssse3_pabs_b_128,
5452 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", int_x86_ssse3_pabs_w_128,
5454 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", int_x86_ssse3_pabs_d_128,
5458 (bc_v2i64 (v16i1sextv16i8)),
5459 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5460 (VPABSBrr128 VR128:$src)>;
5462 (bc_v2i64 (v8i1sextv8i16)),
5463 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5464 (VPABSWrr128 VR128:$src)>;
5466 (bc_v2i64 (v4i1sextv4i32)),
5467 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5468 (VPABSDrr128 VR128:$src)>;
5471 let Predicates = [HasAVX2] in {
5472 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5473 int_x86_avx2_pabs_b>, VEX, VEX_L;
5474 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5475 int_x86_avx2_pabs_w>, VEX, VEX_L;
5476 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5477 int_x86_avx2_pabs_d>, VEX, VEX_L;
5480 (bc_v4i64 (v32i1sextv32i8)),
5481 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5482 (VPABSBrr256 VR256:$src)>;
5484 (bc_v4i64 (v16i1sextv16i16)),
5485 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5486 (VPABSWrr256 VR256:$src)>;
5488 (bc_v4i64 (v8i1sextv8i32)),
5489 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5490 (VPABSDrr256 VR256:$src)>;
5493 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", int_x86_ssse3_pabs_b_128,
5495 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", int_x86_ssse3_pabs_w_128,
5497 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", int_x86_ssse3_pabs_d_128,
5500 let Predicates = [HasSSSE3] in {
5502 (bc_v2i64 (v16i1sextv16i8)),
5503 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5504 (PABSBrr128 VR128:$src)>;
5506 (bc_v2i64 (v8i1sextv8i16)),
5507 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5508 (PABSWrr128 VR128:$src)>;
5510 (bc_v2i64 (v4i1sextv4i32)),
5511 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5512 (PABSDrr128 VR128:$src)>;
5515 //===---------------------------------------------------------------------===//
5516 // SSSE3 - Packed Binary Operator Instructions
5517 //===---------------------------------------------------------------------===//
5519 let Sched = WriteVecALU in {
5520 def SSE_PHADDSUBD : OpndItins<
5521 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5523 def SSE_PHADDSUBSW : OpndItins<
5524 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5526 def SSE_PHADDSUBW : OpndItins<
5527 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5530 let Sched = WriteShuffle in
5531 def SSE_PSHUFB : OpndItins<
5532 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5534 let Sched = WriteVecALU in
5535 def SSE_PSIGN : OpndItins<
5536 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5538 let Sched = WriteVecIMul in
5539 def SSE_PMULHRSW : OpndItins<
5540 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5543 /// SS3I_binop_rm - Simple SSSE3 bin op
5544 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5545 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5546 X86MemOperand x86memop, OpndItins itins,
5548 let isCommutable = 1 in
5549 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5550 (ins RC:$src1, RC:$src2),
5552 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5553 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5554 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5555 Sched<[itins.Sched]>;
5556 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5557 (ins RC:$src1, x86memop:$src2),
5559 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5560 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5562 (OpVT (OpNode RC:$src1,
5563 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5564 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5567 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5568 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5569 Intrinsic IntId128, OpndItins itins,
5570 PatFrag ld_frag, bit Is2Addr = 1> {
5571 let isCommutable = 1 in
5572 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5573 (ins VR128:$src1, VR128:$src2),
5575 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5576 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5577 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5578 Sched<[itins.Sched]>;
5579 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5580 (ins VR128:$src1, i128mem:$src2),
5582 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5583 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5585 (IntId128 VR128:$src1,
5586 (bitconvert (ld_frag addr:$src2))))]>,
5587 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5590 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5592 X86FoldableSchedWrite Sched> {
5593 let isCommutable = 1 in
5594 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5595 (ins VR256:$src1, VR256:$src2),
5596 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5597 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5599 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5600 (ins VR256:$src1, i256mem:$src2),
5601 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5603 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5604 Sched<[Sched.Folded, ReadAfterLd]>;
5607 let ImmT = NoImm, Predicates = [HasAVX] in {
5608 let isCommutable = 0 in {
5609 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5611 SSE_PHADDSUBW, 0>, VEX_4V;
5612 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5614 SSE_PHADDSUBD, 0>, VEX_4V;
5615 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5617 SSE_PHADDSUBW, 0>, VEX_4V;
5618 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5620 SSE_PHADDSUBD, 0>, VEX_4V;
5621 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5623 SSE_PSIGN, 0>, VEX_4V;
5624 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5626 SSE_PSIGN, 0>, VEX_4V;
5627 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5629 SSE_PSIGN, 0>, VEX_4V;
5630 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5632 SSE_PSHUFB, 0>, VEX_4V;
5633 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5634 int_x86_ssse3_phadd_sw_128,
5635 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5636 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5637 int_x86_ssse3_phsub_sw_128,
5638 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5639 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5640 int_x86_ssse3_pmadd_ub_sw_128,
5641 SSE_PMADD, loadv2i64, 0>, VEX_4V;
5643 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5644 int_x86_ssse3_pmul_hr_sw_128,
5645 SSE_PMULHRSW, loadv2i64, 0>, VEX_4V;
5648 let ImmT = NoImm, Predicates = [HasAVX2] in {
5649 let isCommutable = 0 in {
5650 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5652 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5653 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5655 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5656 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5658 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5659 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5661 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5662 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5664 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5665 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5667 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5668 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5670 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5671 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5673 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5674 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5675 int_x86_avx2_phadd_sw,
5676 WriteVecALU>, VEX_4V, VEX_L;
5677 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5678 int_x86_avx2_phsub_sw,
5679 WriteVecALU>, VEX_4V, VEX_L;
5680 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5681 int_x86_avx2_pmadd_ub_sw,
5682 WriteVecIMul>, VEX_4V, VEX_L;
5684 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5685 int_x86_avx2_pmul_hr_sw,
5686 WriteVecIMul>, VEX_4V, VEX_L;
5689 // None of these have i8 immediate fields.
5690 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5691 let isCommutable = 0 in {
5692 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5693 memopv2i64, i128mem, SSE_PHADDSUBW>;
5694 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5695 memopv2i64, i128mem, SSE_PHADDSUBD>;
5696 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5697 memopv2i64, i128mem, SSE_PHADDSUBW>;
5698 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5699 memopv2i64, i128mem, SSE_PHADDSUBD>;
5700 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5701 memopv2i64, i128mem, SSE_PSIGN>;
5702 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5703 memopv2i64, i128mem, SSE_PSIGN>;
5704 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5705 memopv2i64, i128mem, SSE_PSIGN>;
5706 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5707 memopv2i64, i128mem, SSE_PSHUFB>;
5708 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5709 int_x86_ssse3_phadd_sw_128,
5710 SSE_PHADDSUBSW, memopv2i64>;
5711 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5712 int_x86_ssse3_phsub_sw_128,
5713 SSE_PHADDSUBSW, memopv2i64>;
5714 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5715 int_x86_ssse3_pmadd_ub_sw_128,
5716 SSE_PMADD, memopv2i64>;
5718 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5719 int_x86_ssse3_pmul_hr_sw_128,
5720 SSE_PMULHRSW, memopv2i64>;
5723 //===---------------------------------------------------------------------===//
5724 // SSSE3 - Packed Align Instruction Patterns
5725 //===---------------------------------------------------------------------===//
5727 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5728 let hasSideEffects = 0 in {
5729 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5730 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
5732 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5734 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5735 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5737 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5738 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
5740 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5742 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5743 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5747 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5748 let hasSideEffects = 0 in {
5749 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5750 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
5752 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5753 []>, Sched<[WriteShuffle]>;
5755 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5756 (ins VR256:$src1, i256mem:$src2, u8imm:$src3),
5758 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5759 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5763 let Predicates = [HasAVX] in
5764 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5765 let Predicates = [HasAVX2] in
5766 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5767 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5768 defm PALIGN : ssse3_palignr<"palignr">;
5770 let Predicates = [HasAVX2] in {
5771 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5772 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5773 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5774 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5775 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5776 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5777 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5778 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5781 let Predicates = [HasAVX] in {
5782 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5783 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5784 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5785 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5786 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5787 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5788 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5789 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5792 let Predicates = [UseSSSE3] in {
5793 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5794 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5795 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5796 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5797 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5798 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5799 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5800 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5803 //===---------------------------------------------------------------------===//
5804 // SSSE3 - Thread synchronization
5805 //===---------------------------------------------------------------------===//
5807 let SchedRW = [WriteSystem] in {
5808 let usesCustomInserter = 1 in {
5809 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5810 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5811 Requires<[HasSSE3]>;
5814 let Uses = [EAX, ECX, EDX] in
5815 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5816 TB, Requires<[HasSSE3]>;
5817 let Uses = [ECX, EAX] in
5818 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5819 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5820 TB, Requires<[HasSSE3]>;
5823 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5824 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5826 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5827 Requires<[Not64BitMode]>;
5828 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5829 Requires<[In64BitMode]>;
5831 //===----------------------------------------------------------------------===//
5832 // SSE4.1 - Packed Move with Sign/Zero Extend
5833 //===----------------------------------------------------------------------===//
5835 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
5836 RegisterClass OutRC, RegisterClass InRC,
5838 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
5839 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5841 Sched<[itins.Sched]>;
5843 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
5844 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5846 itins.rm>, Sched<[itins.Sched.Folded]>;
5849 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
5850 X86MemOperand MemOp, X86MemOperand MemYOp,
5851 OpndItins SSEItins, OpndItins AVXItins,
5852 OpndItins AVX2Itins> {
5853 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
5854 let Predicates = [HasAVX] in
5855 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
5856 VR128, VR128, AVXItins>, VEX;
5857 let Predicates = [HasAVX2] in
5858 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
5859 VR256, VR128, AVX2Itins>, VEX, VEX_L;
5862 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
5863 X86MemOperand MemOp, X86MemOperand MemYOp> {
5864 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
5866 SSE_INTALU_ITINS_SHUFF_P,
5867 DEFAULT_ITINS_SHUFFLESCHED,
5868 DEFAULT_ITINS_SHUFFLESCHED>;
5869 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
5870 !strconcat("pmovzx", OpcodeStr),
5872 SSE_INTALU_ITINS_SHUFF_P,
5873 DEFAULT_ITINS_SHUFFLESCHED,
5874 DEFAULT_ITINS_SHUFFLESCHED>;
5877 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
5878 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
5879 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
5881 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
5882 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
5884 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
5887 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
5888 // Register-Register patterns
5889 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5890 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
5891 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
5892 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
5893 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
5894 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
5896 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5897 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
5898 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
5899 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
5901 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5902 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
5904 // On AVX2, we also support 256bit inputs.
5905 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
5906 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5907 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
5908 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5909 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
5910 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5912 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
5913 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5914 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
5915 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5917 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
5918 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5920 // Simple Register-Memory patterns
5921 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5922 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5923 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5924 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5925 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5926 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5928 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5929 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5930 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5931 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5933 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5934 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5936 // AVX2 Register-Memory patterns
5937 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5938 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5939 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5940 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5941 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5942 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5943 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5944 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5946 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5947 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5948 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5949 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5950 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5951 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5952 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5953 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5955 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
5956 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5957 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
5958 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5959 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5960 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5961 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5962 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5964 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5965 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5966 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5967 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5968 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5969 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5970 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5971 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5973 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5974 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5975 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5976 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5977 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5978 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5979 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5980 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5982 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
5983 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5984 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
5985 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5986 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
5987 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5988 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
5989 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5992 let Predicates = [HasAVX2] in {
5993 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
5994 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
5997 // SSE4.1/AVX patterns.
5998 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
5999 SDNode ExtOp, PatFrag ExtLoad16> {
6000 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6001 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6002 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6003 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6004 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6005 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6007 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6008 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6009 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6010 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6012 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6013 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6015 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6016 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6017 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6018 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6019 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6020 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6022 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6023 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6024 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6025 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6027 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6028 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6030 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6031 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6032 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6033 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6034 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6035 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6036 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6037 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6038 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6039 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6041 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6042 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6043 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6044 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6045 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6046 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6047 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6048 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6050 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6051 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6052 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6053 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6054 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6055 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6056 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6057 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6059 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6060 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6061 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6062 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6063 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6064 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6065 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6066 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6067 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6068 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6070 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6071 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6072 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6073 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6074 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6075 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6076 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6077 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6079 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6080 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6081 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6082 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6083 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6084 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6085 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6086 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6087 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6088 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6091 let Predicates = [HasAVX] in {
6092 defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
6093 defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
6096 let Predicates = [UseSSE41] in {
6097 defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
6098 defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
6101 //===----------------------------------------------------------------------===//
6102 // SSE4.1 - Extract Instructions
6103 //===----------------------------------------------------------------------===//
6105 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6106 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6107 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6108 (ins VR128:$src1, u8imm:$src2),
6109 !strconcat(OpcodeStr,
6110 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6111 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6113 Sched<[WriteShuffle]>;
6114 let hasSideEffects = 0, mayStore = 1,
6115 SchedRW = [WriteShuffleLd, WriteRMW] in
6116 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6117 (ins i8mem:$dst, VR128:$src1, u8imm:$src2),
6118 !strconcat(OpcodeStr,
6119 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6120 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6121 imm:$src2)))), addr:$dst)]>;
6124 let Predicates = [HasAVX] in
6125 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6127 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6130 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6131 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6132 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6133 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6134 (ins VR128:$src1, u8imm:$src2),
6135 !strconcat(OpcodeStr,
6136 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6137 []>, Sched<[WriteShuffle]>;
6139 let hasSideEffects = 0, mayStore = 1,
6140 SchedRW = [WriteShuffleLd, WriteRMW] in
6141 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6142 (ins i16mem:$dst, VR128:$src1, u8imm:$src2),
6143 !strconcat(OpcodeStr,
6144 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6145 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6146 imm:$src2)))), addr:$dst)]>;
6149 let Predicates = [HasAVX] in
6150 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6152 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6155 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6156 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6157 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6158 (ins VR128:$src1, u8imm:$src2),
6159 !strconcat(OpcodeStr,
6160 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6162 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6163 Sched<[WriteShuffle]>;
6164 let SchedRW = [WriteShuffleLd, WriteRMW] in
6165 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6166 (ins i32mem:$dst, VR128:$src1, u8imm:$src2),
6167 !strconcat(OpcodeStr,
6168 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6169 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6173 let Predicates = [HasAVX] in
6174 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6176 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6178 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6179 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6180 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6181 (ins VR128:$src1, u8imm:$src2),
6182 !strconcat(OpcodeStr,
6183 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6185 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6186 Sched<[WriteShuffle]>, REX_W;
6187 let SchedRW = [WriteShuffleLd, WriteRMW] in
6188 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6189 (ins i64mem:$dst, VR128:$src1, u8imm:$src2),
6190 !strconcat(OpcodeStr,
6191 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6192 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6193 addr:$dst)]>, REX_W;
6196 let Predicates = [HasAVX] in
6197 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6199 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6201 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6203 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6204 OpndItins itins = DEFAULT_ITINS> {
6205 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6206 (ins VR128:$src1, u8imm:$src2),
6207 !strconcat(OpcodeStr,
6208 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6209 [(set GR32orGR64:$dst,
6210 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6211 itins.rr>, Sched<[WriteFBlend]>;
6212 let SchedRW = [WriteFBlendLd, WriteRMW] in
6213 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6214 (ins f32mem:$dst, VR128:$src1, u8imm:$src2),
6215 !strconcat(OpcodeStr,
6216 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6217 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6218 addr:$dst)], itins.rm>;
6221 let ExeDomain = SSEPackedSingle in {
6222 let Predicates = [UseAVX] in
6223 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6224 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6227 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6228 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6231 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6233 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6236 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6237 Requires<[UseSSE41]>;
6239 //===----------------------------------------------------------------------===//
6240 // SSE4.1 - Insert Instructions
6241 //===----------------------------------------------------------------------===//
6243 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6244 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6245 (ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
6247 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6249 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6251 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6252 Sched<[WriteShuffle]>;
6253 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6254 (ins VR128:$src1, i8mem:$src2, u8imm:$src3),
6256 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6258 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6260 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6261 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6264 let Predicates = [HasAVX] in
6265 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6266 let Constraints = "$src1 = $dst" in
6267 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6269 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6270 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6271 (ins VR128:$src1, GR32:$src2, u8imm:$src3),
6273 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6275 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6277 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6278 Sched<[WriteShuffle]>;
6279 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6280 (ins VR128:$src1, i32mem:$src2, u8imm:$src3),
6282 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6284 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6286 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6287 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6290 let Predicates = [HasAVX] in
6291 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6292 let Constraints = "$src1 = $dst" in
6293 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6295 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6296 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6297 (ins VR128:$src1, GR64:$src2, u8imm:$src3),
6299 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6301 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6303 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6304 Sched<[WriteShuffle]>;
6305 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6306 (ins VR128:$src1, i64mem:$src2, u8imm:$src3),
6308 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6310 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6312 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6313 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6316 let Predicates = [HasAVX] in
6317 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6318 let Constraints = "$src1 = $dst" in
6319 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6321 // insertps has a few different modes, there's the first two here below which
6322 // are optimized inserts that won't zero arbitrary elements in the destination
6323 // vector. The next one matches the intrinsic and could zero arbitrary elements
6324 // in the target vector.
6325 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6326 OpndItins itins = DEFAULT_ITINS> {
6327 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6328 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
6330 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6332 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6334 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6335 Sched<[WriteFShuffle]>;
6336 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6337 (ins VR128:$src1, f32mem:$src2, u8imm:$src3),
6339 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6341 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6343 (X86insertps VR128:$src1,
6344 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6345 imm:$src3))], itins.rm>,
6346 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6349 let ExeDomain = SSEPackedSingle in {
6350 let Predicates = [UseAVX] in
6351 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6352 let Constraints = "$src1 = $dst" in
6353 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6356 let Predicates = [UseSSE41] in {
6357 // If we're inserting an element from a load or a null pshuf of a load,
6358 // fold the load into the insertps instruction.
6359 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6360 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6362 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6363 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6364 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6365 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6368 let Predicates = [UseAVX] in {
6369 // If we're inserting an element from a vbroadcast of a load, fold the
6370 // load into the X86insertps instruction.
6371 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6372 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6373 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6374 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6375 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6376 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6379 //===----------------------------------------------------------------------===//
6380 // SSE4.1 - Round Instructions
6381 //===----------------------------------------------------------------------===//
6383 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6384 X86MemOperand x86memop, RegisterClass RC,
6385 PatFrag mem_frag32, PatFrag mem_frag64,
6386 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6387 let ExeDomain = SSEPackedSingle in {
6388 // Intrinsic operation, reg.
6389 // Vector intrinsic operation, reg
6390 def PSr : SS4AIi8<opcps, MRMSrcReg,
6391 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6392 !strconcat(OpcodeStr,
6393 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6394 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6395 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6397 // Vector intrinsic operation, mem
6398 def PSm : SS4AIi8<opcps, MRMSrcMem,
6399 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6400 !strconcat(OpcodeStr,
6401 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6403 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6404 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6405 } // ExeDomain = SSEPackedSingle
6407 let ExeDomain = SSEPackedDouble in {
6408 // Vector intrinsic operation, reg
6409 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6410 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6411 !strconcat(OpcodeStr,
6412 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6413 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6414 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6416 // Vector intrinsic operation, mem
6417 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6418 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6419 !strconcat(OpcodeStr,
6420 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6422 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6423 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6424 } // ExeDomain = SSEPackedDouble
6427 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6430 Intrinsic F64Int, bit Is2Addr = 1> {
6431 let ExeDomain = GenericDomain in {
6433 let hasSideEffects = 0 in
6434 def SSr : SS4AIi8<opcss, MRMSrcReg,
6435 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3),
6437 !strconcat(OpcodeStr,
6438 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6439 !strconcat(OpcodeStr,
6440 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6441 []>, Sched<[WriteFAdd]>;
6443 // Intrinsic operation, reg.
6444 let isCodeGenOnly = 1 in
6445 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6446 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6448 !strconcat(OpcodeStr,
6449 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6450 !strconcat(OpcodeStr,
6451 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6452 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6455 // Intrinsic operation, mem.
6456 def SSm : SS4AIi8<opcss, MRMSrcMem,
6457 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32u8imm:$src3),
6459 !strconcat(OpcodeStr,
6460 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6461 !strconcat(OpcodeStr,
6462 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6464 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6465 Sched<[WriteFAddLd, ReadAfterLd]>;
6468 let hasSideEffects = 0 in
6469 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6470 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3),
6472 !strconcat(OpcodeStr,
6473 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6474 !strconcat(OpcodeStr,
6475 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6476 []>, Sched<[WriteFAdd]>;
6478 // Intrinsic operation, reg.
6479 let isCodeGenOnly = 1 in
6480 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6481 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6483 !strconcat(OpcodeStr,
6484 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6485 !strconcat(OpcodeStr,
6486 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6487 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6490 // Intrinsic operation, mem.
6491 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6492 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32u8imm:$src3),
6494 !strconcat(OpcodeStr,
6495 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6496 !strconcat(OpcodeStr,
6497 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6499 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6500 Sched<[WriteFAddLd, ReadAfterLd]>;
6501 } // ExeDomain = GenericDomain
6504 // FP round - roundss, roundps, roundsd, roundpd
6505 let Predicates = [HasAVX] in {
6507 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6508 loadv4f32, loadv2f64,
6509 int_x86_sse41_round_ps,
6510 int_x86_sse41_round_pd>, VEX;
6511 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6512 loadv8f32, loadv4f64,
6513 int_x86_avx_round_ps_256,
6514 int_x86_avx_round_pd_256>, VEX, VEX_L;
6515 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6516 int_x86_sse41_round_ss,
6517 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6520 let Predicates = [UseAVX] in {
6521 def : Pat<(ffloor FR32:$src),
6522 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6523 def : Pat<(f64 (ffloor FR64:$src)),
6524 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6525 def : Pat<(f32 (fnearbyint FR32:$src)),
6526 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6527 def : Pat<(f64 (fnearbyint FR64:$src)),
6528 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6529 def : Pat<(f32 (fceil FR32:$src)),
6530 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6531 def : Pat<(f64 (fceil FR64:$src)),
6532 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6533 def : Pat<(f32 (frint FR32:$src)),
6534 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6535 def : Pat<(f64 (frint FR64:$src)),
6536 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6537 def : Pat<(f32 (ftrunc FR32:$src)),
6538 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6539 def : Pat<(f64 (ftrunc FR64:$src)),
6540 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6543 let Predicates = [HasAVX] in {
6544 def : Pat<(v4f32 (ffloor VR128:$src)),
6545 (VROUNDPSr VR128:$src, (i32 0x1))>;
6546 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6547 (VROUNDPSr VR128:$src, (i32 0xC))>;
6548 def : Pat<(v4f32 (fceil VR128:$src)),
6549 (VROUNDPSr VR128:$src, (i32 0x2))>;
6550 def : Pat<(v4f32 (frint VR128:$src)),
6551 (VROUNDPSr VR128:$src, (i32 0x4))>;
6552 def : Pat<(v4f32 (ftrunc VR128:$src)),
6553 (VROUNDPSr VR128:$src, (i32 0x3))>;
6555 def : Pat<(v2f64 (ffloor VR128:$src)),
6556 (VROUNDPDr VR128:$src, (i32 0x1))>;
6557 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6558 (VROUNDPDr VR128:$src, (i32 0xC))>;
6559 def : Pat<(v2f64 (fceil VR128:$src)),
6560 (VROUNDPDr VR128:$src, (i32 0x2))>;
6561 def : Pat<(v2f64 (frint VR128:$src)),
6562 (VROUNDPDr VR128:$src, (i32 0x4))>;
6563 def : Pat<(v2f64 (ftrunc VR128:$src)),
6564 (VROUNDPDr VR128:$src, (i32 0x3))>;
6566 def : Pat<(v8f32 (ffloor VR256:$src)),
6567 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6568 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6569 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6570 def : Pat<(v8f32 (fceil VR256:$src)),
6571 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6572 def : Pat<(v8f32 (frint VR256:$src)),
6573 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6574 def : Pat<(v8f32 (ftrunc VR256:$src)),
6575 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6577 def : Pat<(v4f64 (ffloor VR256:$src)),
6578 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6579 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6580 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6581 def : Pat<(v4f64 (fceil VR256:$src)),
6582 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6583 def : Pat<(v4f64 (frint VR256:$src)),
6584 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6585 def : Pat<(v4f64 (ftrunc VR256:$src)),
6586 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6589 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6590 memopv4f32, memopv2f64,
6591 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6592 let Constraints = "$src1 = $dst" in
6593 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6594 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6596 let Predicates = [UseSSE41] in {
6597 def : Pat<(ffloor FR32:$src),
6598 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6599 def : Pat<(f64 (ffloor FR64:$src)),
6600 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6601 def : Pat<(f32 (fnearbyint FR32:$src)),
6602 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6603 def : Pat<(f64 (fnearbyint FR64:$src)),
6604 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6605 def : Pat<(f32 (fceil FR32:$src)),
6606 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6607 def : Pat<(f64 (fceil FR64:$src)),
6608 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6609 def : Pat<(f32 (frint FR32:$src)),
6610 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6611 def : Pat<(f64 (frint FR64:$src)),
6612 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6613 def : Pat<(f32 (ftrunc FR32:$src)),
6614 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6615 def : Pat<(f64 (ftrunc FR64:$src)),
6616 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6618 def : Pat<(v4f32 (ffloor VR128:$src)),
6619 (ROUNDPSr VR128:$src, (i32 0x1))>;
6620 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6621 (ROUNDPSr VR128:$src, (i32 0xC))>;
6622 def : Pat<(v4f32 (fceil VR128:$src)),
6623 (ROUNDPSr VR128:$src, (i32 0x2))>;
6624 def : Pat<(v4f32 (frint VR128:$src)),
6625 (ROUNDPSr VR128:$src, (i32 0x4))>;
6626 def : Pat<(v4f32 (ftrunc VR128:$src)),
6627 (ROUNDPSr VR128:$src, (i32 0x3))>;
6629 def : Pat<(v2f64 (ffloor VR128:$src)),
6630 (ROUNDPDr VR128:$src, (i32 0x1))>;
6631 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6632 (ROUNDPDr VR128:$src, (i32 0xC))>;
6633 def : Pat<(v2f64 (fceil VR128:$src)),
6634 (ROUNDPDr VR128:$src, (i32 0x2))>;
6635 def : Pat<(v2f64 (frint VR128:$src)),
6636 (ROUNDPDr VR128:$src, (i32 0x4))>;
6637 def : Pat<(v2f64 (ftrunc VR128:$src)),
6638 (ROUNDPDr VR128:$src, (i32 0x3))>;
6641 //===----------------------------------------------------------------------===//
6642 // SSE4.1 - Packed Bit Test
6643 //===----------------------------------------------------------------------===//
6645 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6646 // the intel intrinsic that corresponds to this.
6647 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6648 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6649 "vptest\t{$src2, $src1|$src1, $src2}",
6650 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6651 Sched<[WriteVecLogic]>, VEX;
6652 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6653 "vptest\t{$src2, $src1|$src1, $src2}",
6654 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6655 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6657 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6658 "vptest\t{$src2, $src1|$src1, $src2}",
6659 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6660 Sched<[WriteVecLogic]>, VEX, VEX_L;
6661 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6662 "vptest\t{$src2, $src1|$src1, $src2}",
6663 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6664 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6667 let Defs = [EFLAGS] in {
6668 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6669 "ptest\t{$src2, $src1|$src1, $src2}",
6670 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6671 Sched<[WriteVecLogic]>;
6672 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6673 "ptest\t{$src2, $src1|$src1, $src2}",
6674 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6675 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6678 // The bit test instructions below are AVX only
6679 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6680 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6681 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6682 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6683 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6684 Sched<[WriteVecLogic]>, VEX;
6685 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6686 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6687 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6688 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6691 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6692 let ExeDomain = SSEPackedSingle in {
6693 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6694 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6697 let ExeDomain = SSEPackedDouble in {
6698 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6699 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6704 //===----------------------------------------------------------------------===//
6705 // SSE4.1 - Misc Instructions
6706 //===----------------------------------------------------------------------===//
6708 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6709 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6710 "popcnt{w}\t{$src, $dst|$dst, $src}",
6711 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6712 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6714 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6715 "popcnt{w}\t{$src, $dst|$dst, $src}",
6716 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6717 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6718 Sched<[WriteFAddLd]>, OpSize16, XS;
6720 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6721 "popcnt{l}\t{$src, $dst|$dst, $src}",
6722 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6723 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6726 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6727 "popcnt{l}\t{$src, $dst|$dst, $src}",
6728 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6729 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6730 Sched<[WriteFAddLd]>, OpSize32, XS;
6732 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6733 "popcnt{q}\t{$src, $dst|$dst, $src}",
6734 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6735 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6736 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6737 "popcnt{q}\t{$src, $dst|$dst, $src}",
6738 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6739 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6740 Sched<[WriteFAddLd]>, XS;
6745 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6746 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6747 Intrinsic IntId128, PatFrag ld_frag,
6748 X86FoldableSchedWrite Sched> {
6749 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6751 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6752 [(set VR128:$dst, (IntId128 VR128:$src))]>,
6754 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6756 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6758 (IntId128 (bitconvert (ld_frag addr:$src))))]>,
6759 Sched<[Sched.Folded]>;
6762 // PHMIN has the same profile as PSAD, thus we use the same scheduling
6763 // model, although the naming is misleading.
6764 let Predicates = [HasAVX] in
6765 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6766 int_x86_sse41_phminposuw, loadv2i64,
6768 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6769 int_x86_sse41_phminposuw, memopv2i64,
6772 /// SS48I_binop_rm - Simple SSE41 binary operator.
6773 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6774 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6775 X86MemOperand x86memop, bit Is2Addr = 1,
6776 OpndItins itins = SSE_INTALU_ITINS_P> {
6777 let isCommutable = 1 in
6778 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6779 (ins RC:$src1, RC:$src2),
6781 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6782 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6783 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6784 Sched<[itins.Sched]>;
6785 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6786 (ins RC:$src1, x86memop:$src2),
6788 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6789 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6791 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
6792 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6795 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
6797 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
6798 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
6799 PatFrag memop_frag, X86MemOperand x86memop,
6801 bit IsCommutable = 0, bit Is2Addr = 1> {
6802 let isCommutable = IsCommutable in
6803 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6804 (ins RC:$src1, RC:$src2),
6806 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6807 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6808 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
6809 Sched<[itins.Sched]>;
6810 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6811 (ins RC:$src1, x86memop:$src2),
6813 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6814 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6815 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
6816 (bitconvert (memop_frag addr:$src2)))))]>,
6817 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6820 let Predicates = [HasAVX, NoVLX] in {
6821 let isCommutable = 0 in
6822 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6823 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6825 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6826 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6828 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6829 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6831 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6832 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6834 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6835 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6837 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6838 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6840 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6841 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6843 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6844 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6846 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
6847 VR128, loadv2i64, i128mem,
6848 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
6851 let Predicates = [HasAVX2, NoVLX] in {
6852 let isCommutable = 0 in
6853 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6854 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6856 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6857 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6859 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6860 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6862 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6863 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6865 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6866 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6868 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6869 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6871 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6872 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6874 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6875 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6877 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
6878 VR256, loadv4i64, i256mem,
6879 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
6882 let Constraints = "$src1 = $dst" in {
6883 let isCommutable = 0 in
6884 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6885 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6886 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6887 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6888 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6889 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6890 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6891 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6892 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6893 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6894 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6895 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6896 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6897 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6898 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6899 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6900 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
6901 VR128, memopv2i64, i128mem,
6902 SSE_INTMUL_ITINS_P, 1>;
6905 let Predicates = [HasAVX, NoVLX] in {
6906 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6907 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
6909 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6910 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6913 let Predicates = [HasAVX2] in {
6914 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6915 loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
6917 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6918 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6922 let Constraints = "$src1 = $dst" in {
6923 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6924 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6925 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6926 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6929 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6930 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6931 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6932 X86MemOperand x86memop, bit Is2Addr = 1,
6933 OpndItins itins = DEFAULT_ITINS> {
6934 let isCommutable = 1 in
6935 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6936 (ins RC:$src1, RC:$src2, u8imm:$src3),
6938 !strconcat(OpcodeStr,
6939 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6940 !strconcat(OpcodeStr,
6941 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6942 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6943 Sched<[itins.Sched]>;
6944 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6945 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6947 !strconcat(OpcodeStr,
6948 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6949 !strconcat(OpcodeStr,
6950 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6953 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6954 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6957 /// SS41I_binop_rmi - SSE 4.1 binary operator with 8-bit immediate
6958 multiclass SS41I_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
6959 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6960 X86MemOperand x86memop, bit Is2Addr = 1,
6961 OpndItins itins = DEFAULT_ITINS> {
6962 let isCommutable = 1 in
6963 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6964 (ins RC:$src1, RC:$src2, u8imm:$src3),
6966 !strconcat(OpcodeStr,
6967 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6968 !strconcat(OpcodeStr,
6969 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6970 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))],
6971 itins.rr>, Sched<[itins.Sched]>;
6972 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6973 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6975 !strconcat(OpcodeStr,
6976 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6977 !strconcat(OpcodeStr,
6978 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6980 (OpVT (OpNode RC:$src1,
6981 (bitconvert (memop_frag addr:$src2)), imm:$src3)))], itins.rm>,
6982 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6985 let Predicates = [HasAVX] in {
6986 let isCommutable = 0 in {
6987 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6988 VR128, loadv2i64, i128mem, 0,
6989 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
6992 let ExeDomain = SSEPackedSingle in {
6993 defm VBLENDPS : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v4f32,
6994 VR128, loadv4f32, f128mem, 0,
6995 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
6996 defm VBLENDPSY : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v8f32,
6997 VR256, loadv8f32, f256mem, 0,
6998 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7000 let ExeDomain = SSEPackedDouble in {
7001 defm VBLENDPD : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v2f64,
7002 VR128, loadv2f64, f128mem, 0,
7003 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7004 defm VBLENDPDY : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v4f64,
7005 VR256, loadv4f64, f256mem, 0,
7006 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7008 defm VPBLENDW : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v8i16,
7009 VR128, loadv2i64, i128mem, 0,
7010 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7012 let ExeDomain = SSEPackedSingle in
7013 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7014 VR128, loadv4f32, f128mem, 0,
7015 SSE_DPPS_ITINS>, VEX_4V;
7016 let ExeDomain = SSEPackedDouble in
7017 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7018 VR128, loadv2f64, f128mem, 0,
7019 SSE_DPPS_ITINS>, VEX_4V;
7020 let ExeDomain = SSEPackedSingle in
7021 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7022 VR256, loadv8f32, i256mem, 0,
7023 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7026 let Predicates = [HasAVX2] in {
7027 let isCommutable = 0 in {
7028 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7029 VR256, loadv4i64, i256mem, 0,
7030 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7032 defm VPBLENDWY : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v16i16,
7033 VR256, loadv4i64, i256mem, 0,
7034 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7037 let Constraints = "$src1 = $dst" in {
7038 let isCommutable = 0 in {
7039 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7040 VR128, memopv2i64, i128mem,
7041 1, SSE_MPSADBW_ITINS>;
7043 let ExeDomain = SSEPackedSingle in
7044 defm BLENDPS : SS41I_binop_rmi<0x0C, "blendps", X86Blendi, v4f32,
7045 VR128, memopv4f32, f128mem,
7046 1, SSE_INTALU_ITINS_FBLEND_P>;
7047 let ExeDomain = SSEPackedDouble in
7048 defm BLENDPD : SS41I_binop_rmi<0x0D, "blendpd", X86Blendi, v2f64,
7049 VR128, memopv2f64, f128mem,
7050 1, SSE_INTALU_ITINS_FBLEND_P>;
7051 defm PBLENDW : SS41I_binop_rmi<0x0E, "pblendw", X86Blendi, v8i16,
7052 VR128, memopv2i64, i128mem,
7053 1, SSE_INTALU_ITINS_BLEND_P>;
7054 let ExeDomain = SSEPackedSingle in
7055 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7056 VR128, memopv4f32, f128mem, 1,
7058 let ExeDomain = SSEPackedDouble in
7059 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7060 VR128, memopv2f64, f128mem, 1,
7064 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7065 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7066 RegisterClass RC, X86MemOperand x86memop,
7067 PatFrag mem_frag, Intrinsic IntId,
7068 X86FoldableSchedWrite Sched> {
7069 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7070 (ins RC:$src1, RC:$src2, RC:$src3),
7071 !strconcat(OpcodeStr,
7072 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7073 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7074 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7077 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7078 (ins RC:$src1, x86memop:$src2, RC:$src3),
7079 !strconcat(OpcodeStr,
7080 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7082 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7084 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7085 Sched<[Sched.Folded, ReadAfterLd]>;
7088 let Predicates = [HasAVX] in {
7089 let ExeDomain = SSEPackedDouble in {
7090 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7091 loadv2f64, int_x86_sse41_blendvpd,
7093 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7094 loadv4f64, int_x86_avx_blendv_pd_256,
7095 WriteFVarBlend>, VEX_L;
7096 } // ExeDomain = SSEPackedDouble
7097 let ExeDomain = SSEPackedSingle in {
7098 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7099 loadv4f32, int_x86_sse41_blendvps,
7101 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7102 loadv8f32, int_x86_avx_blendv_ps_256,
7103 WriteFVarBlend>, VEX_L;
7104 } // ExeDomain = SSEPackedSingle
7105 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7106 loadv2i64, int_x86_sse41_pblendvb,
7110 let Predicates = [HasAVX2] in {
7111 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7112 loadv4i64, int_x86_avx2_pblendvb,
7113 WriteVarBlend>, VEX_L;
7116 let Predicates = [HasAVX] in {
7117 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7118 (v16i8 VR128:$src2))),
7119 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7120 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7121 (v4i32 VR128:$src2))),
7122 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7123 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7124 (v4f32 VR128:$src2))),
7125 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7126 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7127 (v2i64 VR128:$src2))),
7128 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7129 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7130 (v2f64 VR128:$src2))),
7131 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7132 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7133 (v8i32 VR256:$src2))),
7134 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7135 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7136 (v8f32 VR256:$src2))),
7137 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7138 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7139 (v4i64 VR256:$src2))),
7140 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7141 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7142 (v4f64 VR256:$src2))),
7143 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7146 let Predicates = [HasAVX2] in {
7147 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7148 (v32i8 VR256:$src2))),
7149 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7153 let Predicates = [UseAVX] in {
7154 let AddedComplexity = 15 in {
7155 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7156 // MOVS{S,D} to the lower bits.
7157 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7158 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7159 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7160 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7161 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7162 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7163 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7164 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7166 // Move low f32 and clear high bits.
7167 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7168 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7169 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7170 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7173 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7174 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7175 (SUBREG_TO_REG (i32 0),
7176 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7178 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7179 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7180 (SUBREG_TO_REG (i64 0),
7181 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7184 // Move low f64 and clear high bits.
7185 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7186 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7188 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7189 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7192 let Predicates = [UseSSE41] in {
7193 // With SSE41 we can use blends for these patterns.
7194 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7195 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7196 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7197 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7198 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7199 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7203 /// SS41I_ternary_int - SSE 4.1 ternary operator
7204 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7205 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7206 X86MemOperand x86memop, Intrinsic IntId,
7207 OpndItins itins = DEFAULT_ITINS> {
7208 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7209 (ins VR128:$src1, VR128:$src2),
7210 !strconcat(OpcodeStr,
7211 "\t{$src2, $dst|$dst, $src2}"),
7212 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7213 itins.rr>, Sched<[itins.Sched]>;
7215 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7216 (ins VR128:$src1, x86memop:$src2),
7217 !strconcat(OpcodeStr,
7218 "\t{$src2, $dst|$dst, $src2}"),
7221 (bitconvert (mem_frag addr:$src2)), XMM0))],
7222 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7226 let ExeDomain = SSEPackedDouble in
7227 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7228 int_x86_sse41_blendvpd,
7229 DEFAULT_ITINS_FBLENDSCHED>;
7230 let ExeDomain = SSEPackedSingle in
7231 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7232 int_x86_sse41_blendvps,
7233 DEFAULT_ITINS_FBLENDSCHED>;
7234 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7235 int_x86_sse41_pblendvb,
7236 DEFAULT_ITINS_VARBLENDSCHED>;
7238 // Aliases with the implicit xmm0 argument
7239 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7240 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7241 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7242 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7243 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7244 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7245 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7246 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7247 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7248 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7249 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7250 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7252 let Predicates = [UseSSE41] in {
7253 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7254 (v16i8 VR128:$src2))),
7255 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7256 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7257 (v4i32 VR128:$src2))),
7258 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7259 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7260 (v4f32 VR128:$src2))),
7261 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7262 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7263 (v2i64 VR128:$src2))),
7264 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7265 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7266 (v2f64 VR128:$src2))),
7267 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7270 let SchedRW = [WriteLoad] in {
7271 let Predicates = [HasAVX] in
7272 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7273 "vmovntdqa\t{$src, $dst|$dst, $src}",
7274 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7276 let Predicates = [HasAVX2] in
7277 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7278 "vmovntdqa\t{$src, $dst|$dst, $src}",
7279 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7281 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7282 "movntdqa\t{$src, $dst|$dst, $src}",
7283 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7286 //===----------------------------------------------------------------------===//
7287 // SSE4.2 - Compare Instructions
7288 //===----------------------------------------------------------------------===//
7290 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7291 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7292 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7293 X86MemOperand x86memop, bit Is2Addr = 1> {
7294 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7295 (ins RC:$src1, RC:$src2),
7297 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7298 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7299 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7300 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7301 (ins RC:$src1, x86memop:$src2),
7303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7306 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7309 let Predicates = [HasAVX] in
7310 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7311 loadv2i64, i128mem, 0>, VEX_4V;
7313 let Predicates = [HasAVX2] in
7314 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7315 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7317 let Constraints = "$src1 = $dst" in
7318 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7319 memopv2i64, i128mem>;
7321 //===----------------------------------------------------------------------===//
7322 // SSE4.2 - String/text Processing Instructions
7323 //===----------------------------------------------------------------------===//
7325 // Packed Compare Implicit Length Strings, Return Mask
7326 multiclass pseudo_pcmpistrm<string asm, PatFrag ld_frag> {
7327 def REG : PseudoI<(outs VR128:$dst),
7328 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7329 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7331 def MEM : PseudoI<(outs VR128:$dst),
7332 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7333 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7334 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7337 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7338 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128", loadv2i64>,
7340 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128", memopv2i64>,
7341 Requires<[UseSSE42]>;
7344 multiclass pcmpistrm_SS42AI<string asm> {
7345 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7346 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7347 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7348 []>, Sched<[WritePCmpIStrM]>;
7350 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7351 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7352 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7353 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7356 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7357 let Predicates = [HasAVX] in
7358 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7359 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7362 // Packed Compare Explicit Length Strings, Return Mask
7363 multiclass pseudo_pcmpestrm<string asm, PatFrag ld_frag> {
7364 def REG : PseudoI<(outs VR128:$dst),
7365 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7366 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7367 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7368 def MEM : PseudoI<(outs VR128:$dst),
7369 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7370 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7371 (bc_v16i8 (ld_frag addr:$src3)), EDX, imm:$src5))]>;
7374 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7375 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128", loadv2i64>,
7377 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128", memopv2i64>,
7378 Requires<[UseSSE42]>;
7381 multiclass SS42AI_pcmpestrm<string asm> {
7382 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7383 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7384 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7385 []>, Sched<[WritePCmpEStrM]>;
7387 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7388 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7389 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7390 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7393 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7394 let Predicates = [HasAVX] in
7395 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7396 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7399 // Packed Compare Implicit Length Strings, Return Index
7400 multiclass pseudo_pcmpistri<string asm, PatFrag ld_frag> {
7401 def REG : PseudoI<(outs GR32:$dst),
7402 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7403 [(set GR32:$dst, EFLAGS,
7404 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7405 def MEM : PseudoI<(outs GR32:$dst),
7406 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7407 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7408 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7411 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7412 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI", loadv2i64>,
7414 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI", memopv2i64>,
7415 Requires<[UseSSE42]>;
7418 multiclass SS42AI_pcmpistri<string asm> {
7419 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7420 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7421 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7422 []>, Sched<[WritePCmpIStrI]>;
7424 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7425 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7426 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7427 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7430 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7431 let Predicates = [HasAVX] in
7432 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7433 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7436 // Packed Compare Explicit Length Strings, Return Index
7437 multiclass pseudo_pcmpestri<string asm, PatFrag ld_frag> {
7438 def REG : PseudoI<(outs GR32:$dst),
7439 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7440 [(set GR32:$dst, EFLAGS,
7441 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7442 def MEM : PseudoI<(outs GR32:$dst),
7443 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7444 [(set GR32:$dst, EFLAGS,
7445 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (ld_frag addr:$src3)), EDX,
7449 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7450 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI", loadv2i64>,
7452 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI", memopv2i64>,
7453 Requires<[UseSSE42]>;
7456 multiclass SS42AI_pcmpestri<string asm> {
7457 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7458 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7459 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7460 []>, Sched<[WritePCmpEStrI]>;
7462 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7463 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7464 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7465 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7468 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7469 let Predicates = [HasAVX] in
7470 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7471 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7474 //===----------------------------------------------------------------------===//
7475 // SSE4.2 - CRC Instructions
7476 //===----------------------------------------------------------------------===//
7478 // No CRC instructions have AVX equivalents
7480 // crc intrinsic instruction
7481 // This set of instructions are only rm, the only difference is the size
7483 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7484 RegisterClass RCIn, SDPatternOperator Int> :
7485 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7486 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7487 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7490 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7491 X86MemOperand x86memop, SDPatternOperator Int> :
7492 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7493 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7494 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7495 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7497 let Constraints = "$src1 = $dst" in {
7498 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7499 int_x86_sse42_crc32_32_8>;
7500 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7501 int_x86_sse42_crc32_32_8>;
7502 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7503 int_x86_sse42_crc32_32_16>, OpSize16;
7504 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7505 int_x86_sse42_crc32_32_16>, OpSize16;
7506 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7507 int_x86_sse42_crc32_32_32>, OpSize32;
7508 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7509 int_x86_sse42_crc32_32_32>, OpSize32;
7510 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7511 int_x86_sse42_crc32_64_64>, REX_W;
7512 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7513 int_x86_sse42_crc32_64_64>, REX_W;
7514 let hasSideEffects = 0 in {
7516 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7518 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7523 //===----------------------------------------------------------------------===//
7524 // SHA-NI Instructions
7525 //===----------------------------------------------------------------------===//
7527 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7529 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7530 (ins VR128:$src1, VR128:$src2),
7531 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7533 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7534 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7536 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7537 (ins VR128:$src1, i128mem:$src2),
7538 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7540 (set VR128:$dst, (IntId VR128:$src1,
7541 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7542 (set VR128:$dst, (IntId VR128:$src1,
7543 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7546 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7547 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7548 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7549 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7551 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7552 (i8 imm:$src3)))]>, TA;
7553 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7554 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7555 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7557 (int_x86_sha1rnds4 VR128:$src1,
7558 (bc_v4i32 (memopv2i64 addr:$src2)),
7559 (i8 imm:$src3)))]>, TA;
7561 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7562 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7563 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7566 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7568 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7569 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7572 // Aliases with explicit %xmm0
7573 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7574 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7575 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7576 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7578 //===----------------------------------------------------------------------===//
7579 // AES-NI Instructions
7580 //===----------------------------------------------------------------------===//
7582 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
7583 PatFrag ld_frag, bit Is2Addr = 1> {
7584 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7585 (ins VR128:$src1, VR128:$src2),
7587 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7588 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7589 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7590 Sched<[WriteAESDecEnc]>;
7591 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7592 (ins VR128:$src1, i128mem:$src2),
7594 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7595 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7597 (IntId128 VR128:$src1, (ld_frag addr:$src2)))]>,
7598 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7601 // Perform One Round of an AES Encryption/Decryption Flow
7602 let Predicates = [HasAVX, HasAES] in {
7603 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7604 int_x86_aesni_aesenc, loadv2i64, 0>, VEX_4V;
7605 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7606 int_x86_aesni_aesenclast, loadv2i64, 0>, VEX_4V;
7607 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7608 int_x86_aesni_aesdec, loadv2i64, 0>, VEX_4V;
7609 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7610 int_x86_aesni_aesdeclast, loadv2i64, 0>, VEX_4V;
7613 let Constraints = "$src1 = $dst" in {
7614 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7615 int_x86_aesni_aesenc, memopv2i64>;
7616 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7617 int_x86_aesni_aesenclast, memopv2i64>;
7618 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7619 int_x86_aesni_aesdec, memopv2i64>;
7620 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7621 int_x86_aesni_aesdeclast, memopv2i64>;
7624 // Perform the AES InvMixColumn Transformation
7625 let Predicates = [HasAVX, HasAES] in {
7626 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7628 "vaesimc\t{$src1, $dst|$dst, $src1}",
7630 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7632 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7633 (ins i128mem:$src1),
7634 "vaesimc\t{$src1, $dst|$dst, $src1}",
7635 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7636 Sched<[WriteAESIMCLd]>, VEX;
7638 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7640 "aesimc\t{$src1, $dst|$dst, $src1}",
7642 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7643 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7644 (ins i128mem:$src1),
7645 "aesimc\t{$src1, $dst|$dst, $src1}",
7646 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7647 Sched<[WriteAESIMCLd]>;
7649 // AES Round Key Generation Assist
7650 let Predicates = [HasAVX, HasAES] in {
7651 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7652 (ins VR128:$src1, u8imm:$src2),
7653 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7655 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7656 Sched<[WriteAESKeyGen]>, VEX;
7657 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7658 (ins i128mem:$src1, u8imm:$src2),
7659 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7661 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7662 Sched<[WriteAESKeyGenLd]>, VEX;
7664 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7665 (ins VR128:$src1, u8imm:$src2),
7666 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7668 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7669 Sched<[WriteAESKeyGen]>;
7670 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7671 (ins i128mem:$src1, u8imm:$src2),
7672 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7674 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7675 Sched<[WriteAESKeyGenLd]>;
7677 //===----------------------------------------------------------------------===//
7678 // PCLMUL Instructions
7679 //===----------------------------------------------------------------------===//
7681 // AVX carry-less Multiplication instructions
7682 let isCommutable = 1 in
7683 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7684 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7685 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7687 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7688 Sched<[WriteCLMul]>;
7690 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7691 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7692 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7693 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7694 (loadv2i64 addr:$src2), imm:$src3))]>,
7695 Sched<[WriteCLMulLd, ReadAfterLd]>;
7697 // Carry-less Multiplication instructions
7698 let Constraints = "$src1 = $dst" in {
7699 let isCommutable = 1 in
7700 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7701 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7702 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7704 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7705 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
7707 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7708 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7709 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7710 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7711 (memopv2i64 addr:$src2), imm:$src3))],
7712 IIC_SSE_PCLMULQDQ_RM>,
7713 Sched<[WriteCLMulLd, ReadAfterLd]>;
7714 } // Constraints = "$src1 = $dst"
7717 multiclass pclmul_alias<string asm, int immop> {
7718 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7719 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
7721 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7722 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
7724 def : InstAlias<!strconcat("vpclmul", asm,
7725 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7726 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
7729 def : InstAlias<!strconcat("vpclmul", asm,
7730 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7731 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
7734 defm : pclmul_alias<"hqhq", 0x11>;
7735 defm : pclmul_alias<"hqlq", 0x01>;
7736 defm : pclmul_alias<"lqhq", 0x10>;
7737 defm : pclmul_alias<"lqlq", 0x00>;
7739 //===----------------------------------------------------------------------===//
7740 // SSE4A Instructions
7741 //===----------------------------------------------------------------------===//
7743 let Predicates = [HasSSE4A] in {
7745 let Constraints = "$src = $dst" in {
7746 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
7747 (ins VR128:$src, u8imm:$len, u8imm:$idx),
7748 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7749 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7751 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7752 (ins VR128:$src, VR128:$mask),
7753 "extrq\t{$mask, $src|$src, $mask}",
7754 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7755 VR128:$mask))]>, PD;
7757 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7758 (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
7759 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7760 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7761 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7762 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7763 (ins VR128:$src, VR128:$mask),
7764 "insertq\t{$mask, $src|$src, $mask}",
7765 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7766 VR128:$mask))]>, XD;
7769 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7770 "movntss\t{$src, $dst|$dst, $src}",
7771 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7773 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7774 "movntsd\t{$src, $dst|$dst, $src}",
7775 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7778 //===----------------------------------------------------------------------===//
7780 //===----------------------------------------------------------------------===//
7782 //===----------------------------------------------------------------------===//
7783 // VBROADCAST - Load from memory and broadcast to all elements of the
7784 // destination operand
7786 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7787 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
7788 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7789 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7790 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
7792 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
7793 X86MemOperand x86memop, ValueType VT,
7794 PatFrag ld_frag, SchedWrite Sched> :
7795 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7796 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7797 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
7798 Sched<[Sched]>, VEX {
7802 // AVX2 adds register forms
7803 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7804 Intrinsic Int, SchedWrite Sched> :
7805 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7806 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7807 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
7809 let ExeDomain = SSEPackedSingle in {
7810 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
7811 f32mem, v4f32, loadf32, WriteLoad>;
7812 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
7813 f32mem, v8f32, loadf32,
7814 WriteFShuffleLd>, VEX_L;
7816 let ExeDomain = SSEPackedDouble in
7817 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
7818 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
7819 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7820 int_x86_avx_vbroadcastf128_pd_256,
7821 WriteFShuffleLd>, VEX_L;
7823 let ExeDomain = SSEPackedSingle in {
7824 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7825 int_x86_avx2_vbroadcast_ss_ps,
7827 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7828 int_x86_avx2_vbroadcast_ss_ps_256,
7829 WriteFShuffle256>, VEX_L;
7831 let ExeDomain = SSEPackedDouble in
7832 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7833 int_x86_avx2_vbroadcast_sd_pd_256,
7834 WriteFShuffle256>, VEX_L;
7836 let Predicates = [HasAVX] in
7837 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7838 (VBROADCASTF128 addr:$src)>;
7841 //===----------------------------------------------------------------------===//
7842 // VINSERTF128 - Insert packed floating-point values
7844 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7845 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7846 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
7847 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7848 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
7850 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7851 (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
7852 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7853 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
7856 let Predicates = [HasAVX] in {
7857 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7859 (VINSERTF128rr VR256:$src1, VR128:$src2,
7860 (INSERT_get_vinsert128_imm VR256:$ins))>;
7861 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7863 (VINSERTF128rr VR256:$src1, VR128:$src2,
7864 (INSERT_get_vinsert128_imm VR256:$ins))>;
7866 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7868 (VINSERTF128rm VR256:$src1, addr:$src2,
7869 (INSERT_get_vinsert128_imm VR256:$ins))>;
7870 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7872 (VINSERTF128rm VR256:$src1, addr:$src2,
7873 (INSERT_get_vinsert128_imm VR256:$ins))>;
7876 let Predicates = [HasAVX1Only] in {
7877 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7879 (VINSERTF128rr VR256:$src1, VR128:$src2,
7880 (INSERT_get_vinsert128_imm VR256:$ins))>;
7881 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7883 (VINSERTF128rr VR256:$src1, VR128:$src2,
7884 (INSERT_get_vinsert128_imm VR256:$ins))>;
7885 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7887 (VINSERTF128rr VR256:$src1, VR128:$src2,
7888 (INSERT_get_vinsert128_imm VR256:$ins))>;
7889 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7891 (VINSERTF128rr VR256:$src1, VR128:$src2,
7892 (INSERT_get_vinsert128_imm VR256:$ins))>;
7894 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7896 (VINSERTF128rm VR256:$src1, addr:$src2,
7897 (INSERT_get_vinsert128_imm VR256:$ins))>;
7898 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7899 (bc_v4i32 (loadv2i64 addr:$src2)),
7901 (VINSERTF128rm VR256:$src1, addr:$src2,
7902 (INSERT_get_vinsert128_imm VR256:$ins))>;
7903 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7904 (bc_v16i8 (loadv2i64 addr:$src2)),
7906 (VINSERTF128rm VR256:$src1, addr:$src2,
7907 (INSERT_get_vinsert128_imm VR256:$ins))>;
7908 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7909 (bc_v8i16 (loadv2i64 addr:$src2)),
7911 (VINSERTF128rm VR256:$src1, addr:$src2,
7912 (INSERT_get_vinsert128_imm VR256:$ins))>;
7915 //===----------------------------------------------------------------------===//
7916 // VEXTRACTF128 - Extract packed floating-point values
7918 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7919 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7920 (ins VR256:$src1, u8imm:$src2),
7921 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7922 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
7924 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7925 (ins f128mem:$dst, VR256:$src1, u8imm:$src2),
7926 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7927 []>, Sched<[WriteStore]>, VEX, VEX_L;
7931 let Predicates = [HasAVX] in {
7932 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7933 (v4f32 (VEXTRACTF128rr
7934 (v8f32 VR256:$src1),
7935 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7936 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7937 (v2f64 (VEXTRACTF128rr
7938 (v4f64 VR256:$src1),
7939 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7941 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7942 (iPTR imm))), addr:$dst),
7943 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7944 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7945 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7946 (iPTR imm))), addr:$dst),
7947 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7948 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7951 let Predicates = [HasAVX1Only] in {
7952 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7953 (v2i64 (VEXTRACTF128rr
7954 (v4i64 VR256:$src1),
7955 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7956 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7957 (v4i32 (VEXTRACTF128rr
7958 (v8i32 VR256:$src1),
7959 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7960 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7961 (v8i16 (VEXTRACTF128rr
7962 (v16i16 VR256:$src1),
7963 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7964 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7965 (v16i8 (VEXTRACTF128rr
7966 (v32i8 VR256:$src1),
7967 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7969 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
7970 (iPTR imm))), addr:$dst),
7971 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7972 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7973 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
7974 (iPTR imm))), addr:$dst),
7975 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7976 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7977 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
7978 (iPTR imm))), addr:$dst),
7979 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7980 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7981 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
7982 (iPTR imm))), addr:$dst),
7983 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7984 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7987 //===----------------------------------------------------------------------===//
7988 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7990 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7991 Intrinsic IntLd, Intrinsic IntLd256,
7992 Intrinsic IntSt, Intrinsic IntSt256> {
7993 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7994 (ins VR128:$src1, f128mem:$src2),
7995 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7996 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7998 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7999 (ins VR256:$src1, f256mem:$src2),
8000 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8001 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8003 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8004 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8005 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8006 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8007 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8008 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8009 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8010 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8013 let ExeDomain = SSEPackedSingle in
8014 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8015 int_x86_avx_maskload_ps,
8016 int_x86_avx_maskload_ps_256,
8017 int_x86_avx_maskstore_ps,
8018 int_x86_avx_maskstore_ps_256>;
8019 let ExeDomain = SSEPackedDouble in
8020 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8021 int_x86_avx_maskload_pd,
8022 int_x86_avx_maskload_pd_256,
8023 int_x86_avx_maskstore_pd,
8024 int_x86_avx_maskstore_pd_256>;
8026 //===----------------------------------------------------------------------===//
8027 // VPERMIL - Permute Single and Double Floating-Point Values
8029 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8030 RegisterClass RC, X86MemOperand x86memop_f,
8031 X86MemOperand x86memop_i, PatFrag i_frag,
8032 Intrinsic IntVar, ValueType vt> {
8033 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8034 (ins RC:$src1, RC:$src2),
8035 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8036 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8037 Sched<[WriteFShuffle]>;
8038 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8039 (ins RC:$src1, x86memop_i:$src2),
8040 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8041 [(set RC:$dst, (IntVar RC:$src1,
8042 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8043 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8045 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8046 (ins RC:$src1, u8imm:$src2),
8047 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8048 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8049 Sched<[WriteFShuffle]>;
8050 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8051 (ins x86memop_f:$src1, u8imm:$src2),
8052 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8054 (vt (X86VPermilpi (load addr:$src1), (i8 imm:$src2))))]>, VEX,
8055 Sched<[WriteFShuffleLd]>;
8058 let ExeDomain = SSEPackedSingle in {
8059 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8060 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8061 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8062 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8064 let ExeDomain = SSEPackedDouble in {
8065 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8066 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8067 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8068 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8071 let Predicates = [HasAVX] in {
8072 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8073 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8074 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8075 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8076 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8077 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8078 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8079 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8081 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8082 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8083 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8084 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8085 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8087 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8088 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8089 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8091 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8092 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8093 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8094 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8095 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8096 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8097 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8098 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8100 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8101 (VPERMILPDri VR128:$src1, imm:$imm)>;
8102 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8103 (VPERMILPDmi addr:$src1, imm:$imm)>;
8106 //===----------------------------------------------------------------------===//
8107 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8109 let ExeDomain = SSEPackedSingle in {
8110 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8111 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8112 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8113 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8114 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8115 Sched<[WriteFShuffle]>;
8116 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8117 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8118 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8119 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8120 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8121 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8124 let Predicates = [HasAVX] in {
8125 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8126 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8127 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8128 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8129 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8132 let Predicates = [HasAVX1Only] in {
8133 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8134 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8135 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8136 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8137 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8138 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8139 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8140 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8142 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8143 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8144 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8145 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8146 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8147 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8148 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8149 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8150 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8151 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8152 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8153 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8156 //===----------------------------------------------------------------------===//
8157 // VZERO - Zero YMM registers
8159 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8160 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8161 // Zero All YMM registers
8162 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8163 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8165 // Zero Upper bits of YMM registers
8166 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8167 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8170 //===----------------------------------------------------------------------===//
8171 // Half precision conversion instructions
8172 //===----------------------------------------------------------------------===//
8173 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8174 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8175 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8176 [(set RC:$dst, (Int VR128:$src))]>,
8177 T8PD, VEX, Sched<[WriteCvtF2F]>;
8178 let hasSideEffects = 0, mayLoad = 1 in
8179 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8180 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8181 Sched<[WriteCvtF2FLd]>;
8184 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8185 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8186 (ins RC:$src1, i32u8imm:$src2),
8187 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8188 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8189 TAPD, VEX, Sched<[WriteCvtF2F]>;
8190 let hasSideEffects = 0, mayStore = 1,
8191 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8192 def mr : Ii8<0x1D, MRMDestMem, (outs),
8193 (ins x86memop:$dst, RC:$src1, i32u8imm:$src2),
8194 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8198 let Predicates = [HasF16C] in {
8199 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8200 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8201 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8202 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8204 // Pattern match vcvtph2ps of a scalar i64 load.
8205 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8206 (VCVTPH2PSrm addr:$src)>;
8207 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8208 (VCVTPH2PSrm addr:$src)>;
8211 // Patterns for matching conversions from float to half-float and vice versa.
8212 let Predicates = [HasF16C] in {
8213 def : Pat<(fp_to_f16 FR32:$src),
8214 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8215 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8217 def : Pat<(f16_to_fp GR16:$src),
8218 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8219 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8221 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8222 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8223 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8226 //===----------------------------------------------------------------------===//
8227 // AVX2 Instructions
8228 //===----------------------------------------------------------------------===//
8230 /// AVX2_binop_rmi - AVX2 binary operator with 8-bit immediate
8231 multiclass AVX2_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
8232 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
8233 X86MemOperand x86memop> {
8234 let isCommutable = 1 in
8235 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8236 (ins RC:$src1, RC:$src2, u8imm:$src3),
8237 !strconcat(OpcodeStr,
8238 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8239 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))]>,
8240 Sched<[WriteBlend]>, VEX_4V;
8241 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8242 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
8243 !strconcat(OpcodeStr,
8244 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8246 (OpVT (OpNode RC:$src1,
8247 (bitconvert (memop_frag addr:$src2)), imm:$src3)))]>,
8248 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8251 defm VPBLENDD : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v4i32,
8252 VR128, loadv2i64, i128mem>;
8253 defm VPBLENDDY : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v8i32,
8254 VR256, loadv4i64, i256mem>, VEX_L;
8256 //===----------------------------------------------------------------------===//
8257 // VPBROADCAST - Load from memory and broadcast to all elements of the
8258 // destination operand
8260 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8261 X86MemOperand x86memop, PatFrag ld_frag,
8262 Intrinsic Int128, Intrinsic Int256> {
8263 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8264 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8265 [(set VR128:$dst, (Int128 VR128:$src))]>,
8266 Sched<[WriteShuffle]>, VEX;
8267 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8268 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8270 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8271 Sched<[WriteLoad]>, VEX;
8272 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8273 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8274 [(set VR256:$dst, (Int256 VR128:$src))]>,
8275 Sched<[WriteShuffle256]>, VEX, VEX_L;
8276 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8277 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8279 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8280 Sched<[WriteLoad]>, VEX, VEX_L;
8283 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8284 int_x86_avx2_pbroadcastb_128,
8285 int_x86_avx2_pbroadcastb_256>;
8286 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8287 int_x86_avx2_pbroadcastw_128,
8288 int_x86_avx2_pbroadcastw_256>;
8289 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8290 int_x86_avx2_pbroadcastd_128,
8291 int_x86_avx2_pbroadcastd_256>;
8292 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8293 int_x86_avx2_pbroadcastq_128,
8294 int_x86_avx2_pbroadcastq_256>;
8296 let Predicates = [HasAVX2] in {
8297 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8298 (VPBROADCASTBrm addr:$src)>;
8299 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8300 (VPBROADCASTBYrm addr:$src)>;
8301 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8302 (VPBROADCASTWrm addr:$src)>;
8303 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8304 (VPBROADCASTWYrm addr:$src)>;
8305 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8306 (VPBROADCASTDrm addr:$src)>;
8307 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8308 (VPBROADCASTDYrm addr:$src)>;
8309 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8310 (VPBROADCASTQrm addr:$src)>;
8311 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8312 (VPBROADCASTQYrm addr:$src)>;
8314 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8315 (VPBROADCASTBrr VR128:$src)>;
8316 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8317 (VPBROADCASTBYrr VR128:$src)>;
8318 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8319 (VPBROADCASTWrr VR128:$src)>;
8320 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8321 (VPBROADCASTWYrr VR128:$src)>;
8322 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8323 (VPBROADCASTDrr VR128:$src)>;
8324 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8325 (VPBROADCASTDYrr VR128:$src)>;
8326 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8327 (VPBROADCASTQrr VR128:$src)>;
8328 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8329 (VPBROADCASTQYrr VR128:$src)>;
8330 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8331 (VBROADCASTSSrr VR128:$src)>;
8332 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8333 (VBROADCASTSSYrr VR128:$src)>;
8334 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8335 (VPBROADCASTQrr VR128:$src)>;
8336 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8337 (VBROADCASTSDYrr VR128:$src)>;
8339 // Provide aliases for broadcast from the same regitser class that
8340 // automatically does the extract.
8341 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8342 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8344 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8345 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8347 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8348 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8350 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8351 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8353 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8354 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8356 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8357 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8360 // Provide fallback in case the load node that is used in the patterns above
8361 // is used by additional users, which prevents the pattern selection.
8362 let AddedComplexity = 20 in {
8363 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8364 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8365 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8366 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8367 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8368 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8370 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8371 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8372 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8373 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8374 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8375 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8377 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8378 (VPBROADCASTBrr (COPY_TO_REGCLASS
8379 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8381 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8382 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8383 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8386 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8387 (VPBROADCASTWrr (COPY_TO_REGCLASS
8388 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8390 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8391 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8392 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8395 // The patterns for VPBROADCASTD are not needed because they would match
8396 // the exact same thing as VBROADCASTSS patterns.
8398 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8399 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8400 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8404 // AVX1 broadcast patterns
8405 let Predicates = [HasAVX1Only] in {
8406 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8407 (VBROADCASTSSYrm addr:$src)>;
8408 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8409 (VBROADCASTSDYrm addr:$src)>;
8410 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8411 (VBROADCASTSSrm addr:$src)>;
8414 let Predicates = [HasAVX] in {
8415 // Provide fallback in case the load node that is used in the patterns above
8416 // is used by additional users, which prevents the pattern selection.
8417 let AddedComplexity = 20 in {
8418 // 128bit broadcasts:
8419 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8420 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8421 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8422 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8423 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8424 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8425 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8426 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8427 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8428 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8430 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8431 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8432 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8433 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8434 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8435 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8436 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8437 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8438 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8439 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8442 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8443 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8446 //===----------------------------------------------------------------------===//
8447 // VPERM - Permute instructions
8450 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8451 ValueType OpVT, X86FoldableSchedWrite Sched> {
8452 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8453 (ins VR256:$src1, VR256:$src2),
8454 !strconcat(OpcodeStr,
8455 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8457 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8458 Sched<[Sched]>, VEX_4V, VEX_L;
8459 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8460 (ins VR256:$src1, i256mem:$src2),
8461 !strconcat(OpcodeStr,
8462 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8464 (OpVT (X86VPermv VR256:$src1,
8465 (bitconvert (mem_frag addr:$src2)))))]>,
8466 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8469 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8470 let ExeDomain = SSEPackedSingle in
8471 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8473 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8474 ValueType OpVT, X86FoldableSchedWrite Sched> {
8475 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8476 (ins VR256:$src1, u8imm:$src2),
8477 !strconcat(OpcodeStr,
8478 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8480 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8481 Sched<[Sched]>, VEX, VEX_L;
8482 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8483 (ins i256mem:$src1, u8imm:$src2),
8484 !strconcat(OpcodeStr,
8485 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8487 (OpVT (X86VPermi (mem_frag addr:$src1),
8488 (i8 imm:$src2))))]>,
8489 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8492 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8493 WriteShuffle256>, VEX_W;
8494 let ExeDomain = SSEPackedDouble in
8495 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8496 WriteFShuffle256>, VEX_W;
8498 //===----------------------------------------------------------------------===//
8499 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8501 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8502 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8503 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8504 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8505 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8507 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8508 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8509 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8510 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8512 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8514 let Predicates = [HasAVX2] in {
8515 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8516 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8517 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8518 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8519 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8520 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8522 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8524 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8525 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8526 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8527 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8528 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8530 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8534 //===----------------------------------------------------------------------===//
8535 // VINSERTI128 - Insert packed integer values
8537 let hasSideEffects = 0 in {
8538 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8539 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8540 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8541 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8543 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8544 (ins VR256:$src1, i128mem:$src2, u8imm:$src3),
8545 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8546 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8549 let Predicates = [HasAVX2] in {
8550 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8552 (VINSERTI128rr VR256:$src1, VR128:$src2,
8553 (INSERT_get_vinsert128_imm VR256:$ins))>;
8554 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8556 (VINSERTI128rr VR256:$src1, VR128:$src2,
8557 (INSERT_get_vinsert128_imm VR256:$ins))>;
8558 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8560 (VINSERTI128rr VR256:$src1, VR128:$src2,
8561 (INSERT_get_vinsert128_imm VR256:$ins))>;
8562 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8564 (VINSERTI128rr VR256:$src1, VR128:$src2,
8565 (INSERT_get_vinsert128_imm VR256:$ins))>;
8567 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8569 (VINSERTI128rm VR256:$src1, addr:$src2,
8570 (INSERT_get_vinsert128_imm VR256:$ins))>;
8571 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8572 (bc_v4i32 (loadv2i64 addr:$src2)),
8574 (VINSERTI128rm VR256:$src1, addr:$src2,
8575 (INSERT_get_vinsert128_imm VR256:$ins))>;
8576 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8577 (bc_v16i8 (loadv2i64 addr:$src2)),
8579 (VINSERTI128rm VR256:$src1, addr:$src2,
8580 (INSERT_get_vinsert128_imm VR256:$ins))>;
8581 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8582 (bc_v8i16 (loadv2i64 addr:$src2)),
8584 (VINSERTI128rm VR256:$src1, addr:$src2,
8585 (INSERT_get_vinsert128_imm VR256:$ins))>;
8588 //===----------------------------------------------------------------------===//
8589 // VEXTRACTI128 - Extract packed integer values
8591 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8592 (ins VR256:$src1, u8imm:$src2),
8593 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8595 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8596 Sched<[WriteShuffle256]>, VEX, VEX_L;
8597 let hasSideEffects = 0, mayStore = 1 in
8598 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8599 (ins i128mem:$dst, VR256:$src1, u8imm:$src2),
8600 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8601 Sched<[WriteStore]>, VEX, VEX_L;
8603 let Predicates = [HasAVX2] in {
8604 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8605 (v2i64 (VEXTRACTI128rr
8606 (v4i64 VR256:$src1),
8607 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8608 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8609 (v4i32 (VEXTRACTI128rr
8610 (v8i32 VR256:$src1),
8611 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8612 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8613 (v8i16 (VEXTRACTI128rr
8614 (v16i16 VR256:$src1),
8615 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8616 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8617 (v16i8 (VEXTRACTI128rr
8618 (v32i8 VR256:$src1),
8619 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8621 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8622 (iPTR imm))), addr:$dst),
8623 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8624 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8625 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8626 (iPTR imm))), addr:$dst),
8627 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8628 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8629 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8630 (iPTR imm))), addr:$dst),
8631 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8632 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8633 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8634 (iPTR imm))), addr:$dst),
8635 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8636 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8639 //===----------------------------------------------------------------------===//
8640 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8642 multiclass avx2_pmovmask<string OpcodeStr,
8643 Intrinsic IntLd128, Intrinsic IntLd256,
8644 Intrinsic IntSt128, Intrinsic IntSt256> {
8645 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8646 (ins VR128:$src1, i128mem:$src2),
8647 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8648 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8649 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8650 (ins VR256:$src1, i256mem:$src2),
8651 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8652 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8654 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8655 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8656 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8657 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8658 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8659 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8660 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8661 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8664 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8665 int_x86_avx2_maskload_d,
8666 int_x86_avx2_maskload_d_256,
8667 int_x86_avx2_maskstore_d,
8668 int_x86_avx2_maskstore_d_256>;
8669 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8670 int_x86_avx2_maskload_q,
8671 int_x86_avx2_maskload_q_256,
8672 int_x86_avx2_maskstore_q,
8673 int_x86_avx2_maskstore_q_256>, VEX_W;
8675 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8676 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8678 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8679 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8681 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8682 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
8684 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
8685 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8687 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8688 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8690 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
8691 (bc_v8f32 (v8i32 immAllZerosV)))),
8692 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8694 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
8695 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
8698 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8699 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8701 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
8702 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8704 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
8705 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
8708 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8709 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8711 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
8712 (bc_v4f32 (v4i32 immAllZerosV)))),
8713 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8715 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
8716 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
8719 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8720 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8722 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
8723 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8725 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
8726 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
8729 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
8730 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8732 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
8733 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8735 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8736 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8738 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8739 (v4f64 immAllZerosV))),
8740 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8742 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
8743 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
8746 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8747 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8749 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8750 (bc_v4i64 (v8i32 immAllZerosV)))),
8751 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8753 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
8754 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
8757 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
8758 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8760 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
8761 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
8763 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8764 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8766 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8767 (v2f64 immAllZerosV))),
8768 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8770 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
8771 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
8774 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8775 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8777 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8778 (bc_v2i64 (v4i32 immAllZerosV)))),
8779 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8781 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
8782 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
8785 //===----------------------------------------------------------------------===//
8786 // Variable Bit Shifts
8788 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8789 ValueType vt128, ValueType vt256> {
8790 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8791 (ins VR128:$src1, VR128:$src2),
8792 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8794 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8795 VEX_4V, Sched<[WriteVarVecShift]>;
8796 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8797 (ins VR128:$src1, i128mem:$src2),
8798 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8800 (vt128 (OpNode VR128:$src1,
8801 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8802 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8803 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8804 (ins VR256:$src1, VR256:$src2),
8805 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8807 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8808 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
8809 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8810 (ins VR256:$src1, i256mem:$src2),
8811 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8813 (vt256 (OpNode VR256:$src1,
8814 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8815 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8818 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8819 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8820 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8821 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8822 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8824 //===----------------------------------------------------------------------===//
8825 // VGATHER - GATHER Operations
8826 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8827 X86MemOperand memop128, X86MemOperand memop256> {
8828 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8829 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8830 !strconcat(OpcodeStr,
8831 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8833 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8834 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8835 !strconcat(OpcodeStr,
8836 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8837 []>, VEX_4VOp3, VEX_L;
8840 let mayLoad = 1, Constraints
8841 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8843 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8844 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8845 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8846 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
8848 let ExeDomain = SSEPackedDouble in {
8849 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8850 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8853 let ExeDomain = SSEPackedSingle in {
8854 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8855 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;