1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pextrb : SDNode<"X86ISD::PEXTRB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
41 def X86pextrw : SDNode<"X86ISD::PEXTRW",
42 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
43 def X86pinsrb : SDNode<"X86ISD::PINSRB",
44 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
45 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
46 def X86pinsrw : SDNode<"X86ISD::PINSRW",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86insrtps : SDNode<"X86ISD::INSERTPS",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
52 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
53 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
54 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
55 [SDNPHasChain, SDNPMayLoad]>;
56 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
57 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
58 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
59 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
60 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
61 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
62 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
63 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
65 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
66 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
67 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
69 //===----------------------------------------------------------------------===//
70 // SSE Complex Patterns
71 //===----------------------------------------------------------------------===//
73 // These are 'extloads' from a scalar to the low element of a vector, zeroing
74 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
76 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
77 [SDNPHasChain, SDNPMayLoad]>;
78 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
79 [SDNPHasChain, SDNPMayLoad]>;
81 def ssmem : Operand<v4f32> {
82 let PrintMethod = "printf32mem";
83 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
85 def sdmem : Operand<v2f64> {
86 let PrintMethod = "printf64mem";
87 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
90 //===----------------------------------------------------------------------===//
91 // SSE pattern fragments
92 //===----------------------------------------------------------------------===//
94 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
95 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
96 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
97 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
99 // Like 'store', but always requires vector alignment.
100 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
101 (st node:$val, node:$ptr), [{
102 StoreSDNode *ST = cast<StoreSDNode>(N);
103 return !ST->isTruncatingStore() &&
104 ST->getAddressingMode() == ISD::UNINDEXED &&
105 ST->getAlignment() >= 16;
108 // Like 'load', but always requires vector alignment.
109 def alignedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
110 LoadSDNode *LD = cast<LoadSDNode>(N);
111 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
112 LD->getAddressingMode() == ISD::UNINDEXED &&
113 LD->getAlignment() >= 16;
116 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
117 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
118 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
119 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
120 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
121 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
123 // Like 'load', but uses special alignment checks suitable for use in
124 // memory operands in most SSE instructions, which are required to
125 // be naturally aligned on some targets but not on others.
126 // FIXME: Actually implement support for targets that don't require the
127 // alignment. This probably wants a subtarget predicate.
128 def memop : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
129 LoadSDNode *LD = cast<LoadSDNode>(N);
130 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
131 LD->getAddressingMode() == ISD::UNINDEXED &&
132 LD->getAlignment() >= 16;
135 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
136 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
137 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
138 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
139 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
140 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
141 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
143 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
145 // FIXME: 8 byte alignment for mmx reads is not required
146 def memop64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
147 LoadSDNode *LD = cast<LoadSDNode>(N);
148 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
149 LD->getAddressingMode() == ISD::UNINDEXED &&
150 LD->getAlignment() >= 8;
153 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
154 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
155 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
156 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
158 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
159 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
160 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
161 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
162 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
163 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
165 def vzmovl_v2i64 : PatFrag<(ops node:$src),
166 (bitconvert (v2i64 (X86vzmovl
167 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
168 def vzmovl_v4i32 : PatFrag<(ops node:$src),
169 (bitconvert (v4i32 (X86vzmovl
170 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
172 def vzload_v2i64 : PatFrag<(ops node:$src),
173 (bitconvert (v2i64 (X86vzload node:$src)))>;
176 def fp32imm0 : PatLeaf<(f32 fpimm), [{
177 return N->isExactlyValue(+0.0);
180 def PSxLDQ_imm : SDNodeXForm<imm, [{
181 // Transformation function: imm >> 3
182 return getI32Imm(N->getZExtValue() >> 3);
185 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
187 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
188 return getI8Imm(X86::getShuffleSHUFImmediate(N));
191 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
193 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
194 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
197 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
199 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
200 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
203 def SSE_splat_mask : PatLeaf<(build_vector), [{
204 return X86::isSplatMask(N);
205 }], SHUFFLE_get_shuf_imm>;
207 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
208 return X86::isSplatLoMask(N);
211 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
212 return X86::isMOVHLPSMask(N);
215 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
216 return X86::isMOVHLPS_v_undef_Mask(N);
219 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
220 return X86::isMOVHPMask(N);
223 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
224 return X86::isMOVLPMask(N);
227 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
228 return X86::isMOVLMask(N);
231 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
232 return X86::isMOVSHDUPMask(N);
235 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
236 return X86::isMOVSLDUPMask(N);
239 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
240 return X86::isUNPCKLMask(N);
243 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
244 return X86::isUNPCKHMask(N);
247 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
248 return X86::isUNPCKL_v_undef_Mask(N);
251 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
252 return X86::isUNPCKH_v_undef_Mask(N);
255 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
256 return X86::isPSHUFDMask(N);
257 }], SHUFFLE_get_shuf_imm>;
259 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
260 return X86::isPSHUFHWMask(N);
261 }], SHUFFLE_get_pshufhw_imm>;
263 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
264 return X86::isPSHUFLWMask(N);
265 }], SHUFFLE_get_pshuflw_imm>;
267 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
268 return X86::isPSHUFDMask(N);
269 }], SHUFFLE_get_shuf_imm>;
271 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
272 return X86::isSHUFPMask(N);
273 }], SHUFFLE_get_shuf_imm>;
275 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
276 return X86::isSHUFPMask(N);
277 }], SHUFFLE_get_shuf_imm>;
280 //===----------------------------------------------------------------------===//
281 // SSE scalar FP Instructions
282 //===----------------------------------------------------------------------===//
284 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
285 // scheduler into a branch sequence.
286 // These are expanded by the scheduler.
287 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
288 def CMOV_FR32 : I<0, Pseudo,
289 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
290 "#CMOV_FR32 PSEUDO!",
291 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
293 def CMOV_FR64 : I<0, Pseudo,
294 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
295 "#CMOV_FR64 PSEUDO!",
296 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
298 def CMOV_V4F32 : I<0, Pseudo,
299 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
300 "#CMOV_V4F32 PSEUDO!",
302 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
304 def CMOV_V2F64 : I<0, Pseudo,
305 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
306 "#CMOV_V2F64 PSEUDO!",
308 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
310 def CMOV_V2I64 : I<0, Pseudo,
311 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
312 "#CMOV_V2I64 PSEUDO!",
314 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
318 //===----------------------------------------------------------------------===//
320 //===----------------------------------------------------------------------===//
323 let neverHasSideEffects = 1 in
324 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
325 "movss\t{$src, $dst|$dst, $src}", []>;
326 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
327 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
328 "movss\t{$src, $dst|$dst, $src}",
329 [(set FR32:$dst, (loadf32 addr:$src))]>;
330 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
331 "movss\t{$src, $dst|$dst, $src}",
332 [(store FR32:$src, addr:$dst)]>;
334 // Conversion instructions
335 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
336 "cvttss2si\t{$src, $dst|$dst, $src}",
337 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
338 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
339 "cvttss2si\t{$src, $dst|$dst, $src}",
340 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
341 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
342 "cvtsi2ss\t{$src, $dst|$dst, $src}",
343 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
344 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
345 "cvtsi2ss\t{$src, $dst|$dst, $src}",
346 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
348 // Match intrinsics which expect XMM operand(s).
349 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
350 "cvtss2si\t{$src, $dst|$dst, $src}",
351 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
352 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
353 "cvtss2si\t{$src, $dst|$dst, $src}",
354 [(set GR32:$dst, (int_x86_sse_cvtss2si
355 (load addr:$src)))]>;
357 // Match intrinisics which expect MM and XMM operand(s).
358 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
359 "cvtps2pi\t{$src, $dst|$dst, $src}",
360 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
361 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
362 "cvtps2pi\t{$src, $dst|$dst, $src}",
363 [(set VR64:$dst, (int_x86_sse_cvtps2pi
364 (load addr:$src)))]>;
365 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
366 "cvttps2pi\t{$src, $dst|$dst, $src}",
367 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
368 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
369 "cvttps2pi\t{$src, $dst|$dst, $src}",
370 [(set VR64:$dst, (int_x86_sse_cvttps2pi
371 (load addr:$src)))]>;
372 let Constraints = "$src1 = $dst" in {
373 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
374 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
375 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
376 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
378 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
379 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
380 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
381 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
382 (load addr:$src2)))]>;
385 // Aliases for intrinsics
386 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
387 "cvttss2si\t{$src, $dst|$dst, $src}",
389 (int_x86_sse_cvttss2si VR128:$src))]>;
390 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
391 "cvttss2si\t{$src, $dst|$dst, $src}",
393 (int_x86_sse_cvttss2si(load addr:$src)))]>;
395 let Constraints = "$src1 = $dst" in {
396 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
397 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
398 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
399 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
401 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
402 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
403 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
404 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
405 (loadi32 addr:$src2)))]>;
408 // Comparison instructions
409 let Constraints = "$src1 = $dst" in {
410 let neverHasSideEffects = 1 in
411 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
412 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
413 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
414 let neverHasSideEffects = 1, mayLoad = 1 in
415 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
416 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
417 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
420 let Defs = [EFLAGS] in {
421 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
422 "ucomiss\t{$src2, $src1|$src1, $src2}",
423 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
424 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
425 "ucomiss\t{$src2, $src1|$src1, $src2}",
426 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
430 // Aliases to match intrinsics which expect XMM operand(s).
431 let Constraints = "$src1 = $dst" in {
432 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
433 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
434 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
435 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
436 VR128:$src, imm:$cc))]>;
437 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
438 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
439 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
440 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
441 (load addr:$src), imm:$cc))]>;
444 let Defs = [EFLAGS] in {
445 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
446 (ins VR128:$src1, VR128:$src2),
447 "ucomiss\t{$src2, $src1|$src1, $src2}",
448 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
450 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
451 (ins VR128:$src1, f128mem:$src2),
452 "ucomiss\t{$src2, $src1|$src1, $src2}",
453 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
456 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
457 (ins VR128:$src1, VR128:$src2),
458 "comiss\t{$src2, $src1|$src1, $src2}",
459 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
461 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
462 (ins VR128:$src1, f128mem:$src2),
463 "comiss\t{$src2, $src1|$src1, $src2}",
464 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
468 // Aliases of packed SSE1 instructions for scalar use. These all have names that
471 // Alias instructions that map fld0 to pxor for sse.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
473 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
474 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
475 Requires<[HasSSE1]>, TB, OpSize;
477 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
479 let neverHasSideEffects = 1 in
480 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
481 "movaps\t{$src, $dst|$dst, $src}", []>;
483 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
485 let isSimpleLoad = 1 in
486 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
487 "movaps\t{$src, $dst|$dst, $src}",
488 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
490 // Alias bitwise logical operations using SSE logical ops on packed FP values.
491 let Constraints = "$src1 = $dst" in {
492 let isCommutable = 1 in {
493 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
494 "andps\t{$src2, $dst|$dst, $src2}",
495 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
496 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
497 "orps\t{$src2, $dst|$dst, $src2}",
498 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
499 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
500 "xorps\t{$src2, $dst|$dst, $src2}",
501 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
504 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
505 "andps\t{$src2, $dst|$dst, $src2}",
506 [(set FR32:$dst, (X86fand FR32:$src1,
507 (memopfsf32 addr:$src2)))]>;
508 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
509 "orps\t{$src2, $dst|$dst, $src2}",
510 [(set FR32:$dst, (X86for FR32:$src1,
511 (memopfsf32 addr:$src2)))]>;
512 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
513 "xorps\t{$src2, $dst|$dst, $src2}",
514 [(set FR32:$dst, (X86fxor FR32:$src1,
515 (memopfsf32 addr:$src2)))]>;
516 let neverHasSideEffects = 1 in {
517 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
518 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
519 "andnps\t{$src2, $dst|$dst, $src2}", []>;
522 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
523 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
524 "andnps\t{$src2, $dst|$dst, $src2}", []>;
528 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
530 /// In addition, we also have a special variant of the scalar form here to
531 /// represent the associated intrinsic operation. This form is unlike the
532 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
533 /// and leaves the top elements undefined.
535 /// These three forms can each be reg+reg or reg+mem, so there are a total of
536 /// six "instructions".
538 let Constraints = "$src1 = $dst" in {
539 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
540 SDNode OpNode, Intrinsic F32Int,
541 bit Commutable = 0> {
542 // Scalar operation, reg+reg.
543 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
544 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
545 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
546 let isCommutable = Commutable;
549 // Scalar operation, reg+mem.
550 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
551 (ins FR32:$src1, f32mem:$src2),
552 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
553 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
555 // Vector operation, reg+reg.
556 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
557 (ins VR128:$src1, VR128:$src2),
558 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
559 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
560 let isCommutable = Commutable;
563 // Vector operation, reg+mem.
564 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
565 (ins VR128:$src1, f128mem:$src2),
566 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
567 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
569 // Intrinsic operation, reg+reg.
570 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
571 (ins VR128:$src1, VR128:$src2),
572 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
573 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
574 let isCommutable = Commutable;
577 // Intrinsic operation, reg+mem.
578 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
579 (ins VR128:$src1, ssmem:$src2),
580 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
581 [(set VR128:$dst, (F32Int VR128:$src1,
582 sse_load_f32:$src2))]>;
586 // Arithmetic instructions
587 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
588 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
589 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
590 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
592 /// sse1_fp_binop_rm - Other SSE1 binops
594 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
595 /// instructions for a full-vector intrinsic form. Operations that map
596 /// onto C operators don't use this form since they just use the plain
597 /// vector form instead of having a separate vector intrinsic form.
599 /// This provides a total of eight "instructions".
601 let Constraints = "$src1 = $dst" in {
602 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
606 bit Commutable = 0> {
608 // Scalar operation, reg+reg.
609 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
610 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
611 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
612 let isCommutable = Commutable;
615 // Scalar operation, reg+mem.
616 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
617 (ins FR32:$src1, f32mem:$src2),
618 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
619 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
621 // Vector operation, reg+reg.
622 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
623 (ins VR128:$src1, VR128:$src2),
624 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
625 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
626 let isCommutable = Commutable;
629 // Vector operation, reg+mem.
630 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
631 (ins VR128:$src1, f128mem:$src2),
632 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
633 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
635 // Intrinsic operation, reg+reg.
636 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
637 (ins VR128:$src1, VR128:$src2),
638 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
639 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
640 let isCommutable = Commutable;
643 // Intrinsic operation, reg+mem.
644 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
645 (ins VR128:$src1, ssmem:$src2),
646 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
647 [(set VR128:$dst, (F32Int VR128:$src1,
648 sse_load_f32:$src2))]>;
650 // Vector intrinsic operation, reg+reg.
651 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
652 (ins VR128:$src1, VR128:$src2),
653 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
654 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
655 let isCommutable = Commutable;
658 // Vector intrinsic operation, reg+mem.
659 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
660 (ins VR128:$src1, f128mem:$src2),
661 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
662 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
666 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
667 int_x86_sse_max_ss, int_x86_sse_max_ps>;
668 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
669 int_x86_sse_min_ss, int_x86_sse_min_ps>;
671 //===----------------------------------------------------------------------===//
672 // SSE packed FP Instructions
675 let neverHasSideEffects = 1 in
676 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
677 "movaps\t{$src, $dst|$dst, $src}", []>;
678 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
679 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
680 "movaps\t{$src, $dst|$dst, $src}",
681 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
683 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
684 "movaps\t{$src, $dst|$dst, $src}",
685 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
687 let neverHasSideEffects = 1 in
688 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
689 "movups\t{$src, $dst|$dst, $src}", []>;
690 let isSimpleLoad = 1 in
691 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
692 "movups\t{$src, $dst|$dst, $src}",
693 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
694 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
695 "movups\t{$src, $dst|$dst, $src}",
696 [(store (v4f32 VR128:$src), addr:$dst)]>;
698 // Intrinsic forms of MOVUPS load and store
699 let isSimpleLoad = 1 in
700 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
701 "movups\t{$src, $dst|$dst, $src}",
702 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
703 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
704 "movups\t{$src, $dst|$dst, $src}",
705 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
707 let Constraints = "$src1 = $dst" in {
708 let AddedComplexity = 20 in {
709 def MOVLPSrm : PSI<0x12, MRMSrcMem,
710 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
711 "movlps\t{$src2, $dst|$dst, $src2}",
713 (v4f32 (vector_shuffle VR128:$src1,
714 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
715 MOVLP_shuffle_mask)))]>;
716 def MOVHPSrm : PSI<0x16, MRMSrcMem,
717 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
718 "movhps\t{$src2, $dst|$dst, $src2}",
720 (v4f32 (vector_shuffle VR128:$src1,
721 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
722 MOVHP_shuffle_mask)))]>;
724 } // Constraints = "$src1 = $dst"
727 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
728 "movlps\t{$src, $dst|$dst, $src}",
729 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
730 (iPTR 0))), addr:$dst)]>;
732 // v2f64 extract element 1 is always custom lowered to unpack high to low
733 // and extract element 0 so the non-store version isn't too horrible.
734 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
735 "movhps\t{$src, $dst|$dst, $src}",
736 [(store (f64 (vector_extract
737 (v2f64 (vector_shuffle
738 (bc_v2f64 (v4f32 VR128:$src)), (undef),
739 UNPCKH_shuffle_mask)), (iPTR 0))),
742 let Constraints = "$src1 = $dst" in {
743 let AddedComplexity = 15 in {
744 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
745 "movlhps\t{$src2, $dst|$dst, $src2}",
747 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
748 MOVHP_shuffle_mask)))]>;
750 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
751 "movhlps\t{$src2, $dst|$dst, $src2}",
753 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
754 MOVHLPS_shuffle_mask)))]>;
756 } // Constraints = "$src1 = $dst"
762 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
764 /// In addition, we also have a special variant of the scalar form here to
765 /// represent the associated intrinsic operation. This form is unlike the
766 /// plain scalar form, in that it takes an entire vector (instead of a
767 /// scalar) and leaves the top elements undefined.
769 /// And, we have a special variant form for a full-vector intrinsic form.
771 /// These four forms can each have a reg or a mem operand, so there are a
772 /// total of eight "instructions".
774 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
778 bit Commutable = 0> {
779 // Scalar operation, reg.
780 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
781 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
782 [(set FR32:$dst, (OpNode FR32:$src))]> {
783 let isCommutable = Commutable;
786 // Scalar operation, mem.
787 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
788 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
789 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
791 // Vector operation, reg.
792 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
793 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
794 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
795 let isCommutable = Commutable;
798 // Vector operation, mem.
799 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
800 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
801 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
803 // Intrinsic operation, reg.
804 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
805 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
806 [(set VR128:$dst, (F32Int VR128:$src))]> {
807 let isCommutable = Commutable;
810 // Intrinsic operation, mem.
811 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
812 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
813 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
815 // Vector intrinsic operation, reg
816 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
817 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
818 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
819 let isCommutable = Commutable;
822 // Vector intrinsic operation, mem
823 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
824 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
825 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
829 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
830 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
832 // Reciprocal approximations. Note that these typically require refinement
833 // in order to obtain suitable precision.
834 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
835 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
836 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
837 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
840 let Constraints = "$src1 = $dst" in {
841 let isCommutable = 1 in {
842 def ANDPSrr : PSI<0x54, MRMSrcReg,
843 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
844 "andps\t{$src2, $dst|$dst, $src2}",
845 [(set VR128:$dst, (v2i64
846 (and VR128:$src1, VR128:$src2)))]>;
847 def ORPSrr : PSI<0x56, MRMSrcReg,
848 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
849 "orps\t{$src2, $dst|$dst, $src2}",
850 [(set VR128:$dst, (v2i64
851 (or VR128:$src1, VR128:$src2)))]>;
852 def XORPSrr : PSI<0x57, MRMSrcReg,
853 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
854 "xorps\t{$src2, $dst|$dst, $src2}",
855 [(set VR128:$dst, (v2i64
856 (xor VR128:$src1, VR128:$src2)))]>;
859 def ANDPSrm : PSI<0x54, MRMSrcMem,
860 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
861 "andps\t{$src2, $dst|$dst, $src2}",
862 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
863 (memopv2i64 addr:$src2)))]>;
864 def ORPSrm : PSI<0x56, MRMSrcMem,
865 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
866 "orps\t{$src2, $dst|$dst, $src2}",
867 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
868 (memopv2i64 addr:$src2)))]>;
869 def XORPSrm : PSI<0x57, MRMSrcMem,
870 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
871 "xorps\t{$src2, $dst|$dst, $src2}",
872 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
873 (memopv2i64 addr:$src2)))]>;
874 def ANDNPSrr : PSI<0x55, MRMSrcReg,
875 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
876 "andnps\t{$src2, $dst|$dst, $src2}",
878 (v2i64 (and (xor VR128:$src1,
879 (bc_v2i64 (v4i32 immAllOnesV))),
881 def ANDNPSrm : PSI<0x55, MRMSrcMem,
882 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
883 "andnps\t{$src2, $dst|$dst, $src2}",
885 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
886 (bc_v2i64 (v4i32 immAllOnesV))),
887 (memopv2i64 addr:$src2))))]>;
890 let Constraints = "$src1 = $dst" in {
891 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
892 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
893 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
894 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
895 VR128:$src, imm:$cc))]>;
896 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
897 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
898 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
899 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
900 (memop addr:$src), imm:$cc))]>;
902 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
903 (CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>;
904 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
905 (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>;
907 // Shuffle and unpack instructions
908 let Constraints = "$src1 = $dst" in {
909 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
910 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
911 (outs VR128:$dst), (ins VR128:$src1,
912 VR128:$src2, i32i8imm:$src3),
913 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
915 (v4f32 (vector_shuffle
916 VR128:$src1, VR128:$src2,
917 SHUFP_shuffle_mask:$src3)))]>;
918 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
919 (outs VR128:$dst), (ins VR128:$src1,
920 f128mem:$src2, i32i8imm:$src3),
921 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
923 (v4f32 (vector_shuffle
924 VR128:$src1, (memopv4f32 addr:$src2),
925 SHUFP_shuffle_mask:$src3)))]>;
927 let AddedComplexity = 10 in {
928 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
929 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
930 "unpckhps\t{$src2, $dst|$dst, $src2}",
932 (v4f32 (vector_shuffle
933 VR128:$src1, VR128:$src2,
934 UNPCKH_shuffle_mask)))]>;
935 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
936 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
937 "unpckhps\t{$src2, $dst|$dst, $src2}",
939 (v4f32 (vector_shuffle
940 VR128:$src1, (memopv4f32 addr:$src2),
941 UNPCKH_shuffle_mask)))]>;
943 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
944 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
945 "unpcklps\t{$src2, $dst|$dst, $src2}",
947 (v4f32 (vector_shuffle
948 VR128:$src1, VR128:$src2,
949 UNPCKL_shuffle_mask)))]>;
950 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
951 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
952 "unpcklps\t{$src2, $dst|$dst, $src2}",
954 (v4f32 (vector_shuffle
955 VR128:$src1, (memopv4f32 addr:$src2),
956 UNPCKL_shuffle_mask)))]>;
958 } // Constraints = "$src1 = $dst"
961 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
962 "movmskps\t{$src, $dst|$dst, $src}",
963 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
964 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
965 "movmskpd\t{$src, $dst|$dst, $src}",
966 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
968 // Prefetch intrinsic.
969 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
970 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
971 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
972 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
973 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
974 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
975 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
976 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
978 // Non-temporal stores
979 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
980 "movntps\t{$src, $dst|$dst, $src}",
981 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
983 // Load, store, and memory fence
984 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
987 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
988 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
989 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
990 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
992 // Alias instructions that map zero vector to pxor / xorp* for sse.
993 let isReMaterializable = 1 in
994 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
996 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
998 let Predicates = [HasSSE1] in {
999 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
1000 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
1001 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
1002 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1003 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1006 // FR32 to 128-bit vector conversion.
1007 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
1008 "movss\t{$src, $dst|$dst, $src}",
1010 (v4f32 (scalar_to_vector FR32:$src)))]>;
1011 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1012 "movss\t{$src, $dst|$dst, $src}",
1014 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1016 // FIXME: may not be able to eliminate this movss with coalescing the src and
1017 // dest register classes are different. We really want to write this pattern
1019 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1020 // (f32 FR32:$src)>;
1021 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1022 "movss\t{$src, $dst|$dst, $src}",
1023 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1025 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1026 "movss\t{$src, $dst|$dst, $src}",
1027 [(store (f32 (vector_extract (v4f32 VR128:$src),
1028 (iPTR 0))), addr:$dst)]>;
1031 // Move to lower bits of a VR128, leaving upper bits alone.
1032 // Three operand (but two address) aliases.
1033 let Constraints = "$src1 = $dst" in {
1034 let neverHasSideEffects = 1 in
1035 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1036 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1037 "movss\t{$src2, $dst|$dst, $src2}", []>;
1039 let AddedComplexity = 15 in
1040 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1041 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1042 "movss\t{$src2, $dst|$dst, $src2}",
1044 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1045 MOVL_shuffle_mask)))]>;
1048 // Move to lower bits of a VR128 and zeroing upper bits.
1049 // Loading from memory automatically zeroing upper bits.
1050 let AddedComplexity = 20 in
1051 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1052 "movss\t{$src, $dst|$dst, $src}",
1053 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1054 (loadf32 addr:$src))))))]>;
1056 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1057 (MOVZSS2PSrm addr:$src)>;
1059 //===----------------------------------------------------------------------===//
1060 // SSE2 Instructions
1061 //===----------------------------------------------------------------------===//
1063 // Move Instructions
1064 let neverHasSideEffects = 1 in
1065 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1066 "movsd\t{$src, $dst|$dst, $src}", []>;
1067 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1068 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1069 "movsd\t{$src, $dst|$dst, $src}",
1070 [(set FR64:$dst, (loadf64 addr:$src))]>;
1071 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1072 "movsd\t{$src, $dst|$dst, $src}",
1073 [(store FR64:$src, addr:$dst)]>;
1075 // Conversion instructions
1076 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1077 "cvttsd2si\t{$src, $dst|$dst, $src}",
1078 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1079 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1080 "cvttsd2si\t{$src, $dst|$dst, $src}",
1081 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1082 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1083 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1084 [(set FR32:$dst, (fround FR64:$src))]>;
1085 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1086 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1087 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1088 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1089 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1090 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1091 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1092 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1093 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1095 // SSE2 instructions with XS prefix
1096 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1097 "cvtss2sd\t{$src, $dst|$dst, $src}",
1098 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1099 Requires<[HasSSE2]>;
1100 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1101 "cvtss2sd\t{$src, $dst|$dst, $src}",
1102 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1103 Requires<[HasSSE2]>;
1105 // Match intrinsics which expect XMM operand(s).
1106 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1107 "cvtsd2si\t{$src, $dst|$dst, $src}",
1108 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1109 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1110 "cvtsd2si\t{$src, $dst|$dst, $src}",
1111 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1112 (load addr:$src)))]>;
1114 // Match intrinisics which expect MM and XMM operand(s).
1115 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1116 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1117 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1118 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1119 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1120 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1121 (memop addr:$src)))]>;
1122 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1123 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1124 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1125 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1126 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1127 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1128 (memop addr:$src)))]>;
1129 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1130 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1131 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1132 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1133 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1134 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1135 (load addr:$src)))]>;
1137 // Aliases for intrinsics
1138 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1139 "cvttsd2si\t{$src, $dst|$dst, $src}",
1141 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1142 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1143 "cvttsd2si\t{$src, $dst|$dst, $src}",
1144 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1145 (load addr:$src)))]>;
1147 // Comparison instructions
1148 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1149 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1150 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1151 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1153 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1154 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1155 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1158 let Defs = [EFLAGS] in {
1159 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1160 "ucomisd\t{$src2, $src1|$src1, $src2}",
1161 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1162 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1163 "ucomisd\t{$src2, $src1|$src1, $src2}",
1164 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1165 (implicit EFLAGS)]>;
1168 // Aliases to match intrinsics which expect XMM operand(s).
1169 let Constraints = "$src1 = $dst" in {
1170 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1171 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1172 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1173 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1174 VR128:$src, imm:$cc))]>;
1175 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1176 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1177 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1178 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1179 (load addr:$src), imm:$cc))]>;
1182 let Defs = [EFLAGS] in {
1183 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1184 "ucomisd\t{$src2, $src1|$src1, $src2}",
1185 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1186 (implicit EFLAGS)]>;
1187 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1188 "ucomisd\t{$src2, $src1|$src1, $src2}",
1189 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1190 (implicit EFLAGS)]>;
1192 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1193 "comisd\t{$src2, $src1|$src1, $src2}",
1194 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1195 (implicit EFLAGS)]>;
1196 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1197 "comisd\t{$src2, $src1|$src1, $src2}",
1198 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1199 (implicit EFLAGS)]>;
1202 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1205 // Alias instructions that map fld0 to pxor for sse.
1206 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1207 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1208 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1209 Requires<[HasSSE2]>, TB, OpSize;
1211 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1213 let neverHasSideEffects = 1 in
1214 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1215 "movapd\t{$src, $dst|$dst, $src}", []>;
1217 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1219 let isSimpleLoad = 1 in
1220 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1221 "movapd\t{$src, $dst|$dst, $src}",
1222 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1224 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1225 let Constraints = "$src1 = $dst" in {
1226 let isCommutable = 1 in {
1227 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1228 (ins FR64:$src1, FR64:$src2),
1229 "andpd\t{$src2, $dst|$dst, $src2}",
1230 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1231 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1232 (ins FR64:$src1, FR64:$src2),
1233 "orpd\t{$src2, $dst|$dst, $src2}",
1234 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1235 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1236 (ins FR64:$src1, FR64:$src2),
1237 "xorpd\t{$src2, $dst|$dst, $src2}",
1238 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1241 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1242 (ins FR64:$src1, f128mem:$src2),
1243 "andpd\t{$src2, $dst|$dst, $src2}",
1244 [(set FR64:$dst, (X86fand FR64:$src1,
1245 (memopfsf64 addr:$src2)))]>;
1246 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1247 (ins FR64:$src1, f128mem:$src2),
1248 "orpd\t{$src2, $dst|$dst, $src2}",
1249 [(set FR64:$dst, (X86for FR64:$src1,
1250 (memopfsf64 addr:$src2)))]>;
1251 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1252 (ins FR64:$src1, f128mem:$src2),
1253 "xorpd\t{$src2, $dst|$dst, $src2}",
1254 [(set FR64:$dst, (X86fxor FR64:$src1,
1255 (memopfsf64 addr:$src2)))]>;
1257 let neverHasSideEffects = 1 in {
1258 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1259 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1260 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1262 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1263 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1264 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1268 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1270 /// In addition, we also have a special variant of the scalar form here to
1271 /// represent the associated intrinsic operation. This form is unlike the
1272 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1273 /// and leaves the top elements undefined.
1275 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1276 /// six "instructions".
1278 let Constraints = "$src1 = $dst" in {
1279 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1280 SDNode OpNode, Intrinsic F64Int,
1281 bit Commutable = 0> {
1282 // Scalar operation, reg+reg.
1283 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1284 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1285 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1286 let isCommutable = Commutable;
1289 // Scalar operation, reg+mem.
1290 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1291 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1292 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1294 // Vector operation, reg+reg.
1295 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1296 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1297 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1298 let isCommutable = Commutable;
1301 // Vector operation, reg+mem.
1302 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1303 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1304 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1306 // Intrinsic operation, reg+reg.
1307 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1308 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1309 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1310 let isCommutable = Commutable;
1313 // Intrinsic operation, reg+mem.
1314 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1315 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1316 [(set VR128:$dst, (F64Int VR128:$src1,
1317 sse_load_f64:$src2))]>;
1321 // Arithmetic instructions
1322 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1323 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1324 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1325 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1327 /// sse2_fp_binop_rm - Other SSE2 binops
1329 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1330 /// instructions for a full-vector intrinsic form. Operations that map
1331 /// onto C operators don't use this form since they just use the plain
1332 /// vector form instead of having a separate vector intrinsic form.
1334 /// This provides a total of eight "instructions".
1336 let Constraints = "$src1 = $dst" in {
1337 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1341 bit Commutable = 0> {
1343 // Scalar operation, reg+reg.
1344 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1345 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1346 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1347 let isCommutable = Commutable;
1350 // Scalar operation, reg+mem.
1351 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1352 (ins FR64:$src1, f64mem:$src2),
1353 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1354 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1356 // Vector operation, reg+reg.
1357 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1358 (ins VR128:$src1, VR128:$src2),
1359 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1360 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1361 let isCommutable = Commutable;
1364 // Vector operation, reg+mem.
1365 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1366 (ins VR128:$src1, f128mem:$src2),
1367 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1368 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1370 // Intrinsic operation, reg+reg.
1371 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1372 (ins VR128:$src1, VR128:$src2),
1373 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1374 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1375 let isCommutable = Commutable;
1378 // Intrinsic operation, reg+mem.
1379 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1380 (ins VR128:$src1, sdmem:$src2),
1381 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1382 [(set VR128:$dst, (F64Int VR128:$src1,
1383 sse_load_f64:$src2))]>;
1385 // Vector intrinsic operation, reg+reg.
1386 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1387 (ins VR128:$src1, VR128:$src2),
1388 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1389 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1390 let isCommutable = Commutable;
1393 // Vector intrinsic operation, reg+mem.
1394 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1395 (ins VR128:$src1, f128mem:$src2),
1396 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1397 [(set VR128:$dst, (V2F64Int VR128:$src1,
1398 (memopv2f64 addr:$src2)))]>;
1402 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1403 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1404 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1405 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1407 //===----------------------------------------------------------------------===//
1408 // SSE packed FP Instructions
1410 // Move Instructions
1411 let neverHasSideEffects = 1 in
1412 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1413 "movapd\t{$src, $dst|$dst, $src}", []>;
1414 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1415 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1416 "movapd\t{$src, $dst|$dst, $src}",
1417 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1419 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1420 "movapd\t{$src, $dst|$dst, $src}",
1421 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1423 let neverHasSideEffects = 1 in
1424 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1425 "movupd\t{$src, $dst|$dst, $src}", []>;
1426 let isSimpleLoad = 1 in
1427 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1428 "movupd\t{$src, $dst|$dst, $src}",
1429 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1430 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1431 "movupd\t{$src, $dst|$dst, $src}",
1432 [(store (v2f64 VR128:$src), addr:$dst)]>;
1434 // Intrinsic forms of MOVUPD load and store
1435 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1436 "movupd\t{$src, $dst|$dst, $src}",
1437 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1438 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1439 "movupd\t{$src, $dst|$dst, $src}",
1440 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1442 let Constraints = "$src1 = $dst" in {
1443 let AddedComplexity = 20 in {
1444 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1445 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1446 "movlpd\t{$src2, $dst|$dst, $src2}",
1448 (v2f64 (vector_shuffle VR128:$src1,
1449 (scalar_to_vector (loadf64 addr:$src2)),
1450 MOVLP_shuffle_mask)))]>;
1451 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1452 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1453 "movhpd\t{$src2, $dst|$dst, $src2}",
1455 (v2f64 (vector_shuffle VR128:$src1,
1456 (scalar_to_vector (loadf64 addr:$src2)),
1457 MOVHP_shuffle_mask)))]>;
1458 } // AddedComplexity
1459 } // Constraints = "$src1 = $dst"
1461 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1462 "movlpd\t{$src, $dst|$dst, $src}",
1463 [(store (f64 (vector_extract (v2f64 VR128:$src),
1464 (iPTR 0))), addr:$dst)]>;
1466 // v2f64 extract element 1 is always custom lowered to unpack high to low
1467 // and extract element 0 so the non-store version isn't too horrible.
1468 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1469 "movhpd\t{$src, $dst|$dst, $src}",
1470 [(store (f64 (vector_extract
1471 (v2f64 (vector_shuffle VR128:$src, (undef),
1472 UNPCKH_shuffle_mask)), (iPTR 0))),
1475 // SSE2 instructions without OpSize prefix
1476 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1477 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1478 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1479 TB, Requires<[HasSSE2]>;
1480 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1481 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1482 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1483 (bitconvert (memopv2i64 addr:$src))))]>,
1484 TB, Requires<[HasSSE2]>;
1486 // SSE2 instructions with XS prefix
1487 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1488 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1489 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1490 XS, Requires<[HasSSE2]>;
1491 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1492 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1493 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1494 (bitconvert (memopv2i64 addr:$src))))]>,
1495 XS, Requires<[HasSSE2]>;
1497 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1498 "cvtps2dq\t{$src, $dst|$dst, $src}",
1499 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1500 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1501 "cvtps2dq\t{$src, $dst|$dst, $src}",
1502 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1503 (memop addr:$src)))]>;
1504 // SSE2 packed instructions with XS prefix
1505 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1506 "cvttps2dq\t{$src, $dst|$dst, $src}",
1507 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1508 XS, Requires<[HasSSE2]>;
1509 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1510 "cvttps2dq\t{$src, $dst|$dst, $src}",
1511 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1512 (memop addr:$src)))]>,
1513 XS, Requires<[HasSSE2]>;
1515 // SSE2 packed instructions with XD prefix
1516 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1517 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1518 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1519 XD, Requires<[HasSSE2]>;
1520 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1521 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1522 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1523 (memop addr:$src)))]>,
1524 XD, Requires<[HasSSE2]>;
1526 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1527 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1528 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1529 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1530 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1531 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1532 (memop addr:$src)))]>;
1534 // SSE2 instructions without OpSize prefix
1535 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1536 "cvtps2pd\t{$src, $dst|$dst, $src}",
1537 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1538 TB, Requires<[HasSSE2]>;
1539 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1540 "cvtps2pd\t{$src, $dst|$dst, $src}",
1541 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1542 (load addr:$src)))]>,
1543 TB, Requires<[HasSSE2]>;
1545 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1546 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1547 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1548 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1549 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1550 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1551 (memop addr:$src)))]>;
1553 // Match intrinsics which expect XMM operand(s).
1554 // Aliases for intrinsics
1555 let Constraints = "$src1 = $dst" in {
1556 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1557 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1558 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1559 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1561 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1562 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1563 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1564 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1565 (loadi32 addr:$src2)))]>;
1566 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1567 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1568 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1569 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1571 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1572 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1573 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1574 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1575 (load addr:$src2)))]>;
1576 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1577 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1578 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1579 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1580 VR128:$src2))]>, XS,
1581 Requires<[HasSSE2]>;
1582 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1583 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1584 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1585 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1586 (load addr:$src2)))]>, XS,
1587 Requires<[HasSSE2]>;
1592 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1594 /// In addition, we also have a special variant of the scalar form here to
1595 /// represent the associated intrinsic operation. This form is unlike the
1596 /// plain scalar form, in that it takes an entire vector (instead of a
1597 /// scalar) and leaves the top elements undefined.
1599 /// And, we have a special variant form for a full-vector intrinsic form.
1601 /// These four forms can each have a reg or a mem operand, so there are a
1602 /// total of eight "instructions".
1604 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1608 bit Commutable = 0> {
1609 // Scalar operation, reg.
1610 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1611 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1612 [(set FR64:$dst, (OpNode FR64:$src))]> {
1613 let isCommutable = Commutable;
1616 // Scalar operation, mem.
1617 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1618 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1619 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1621 // Vector operation, reg.
1622 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1623 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1624 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1625 let isCommutable = Commutable;
1628 // Vector operation, mem.
1629 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1630 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1631 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1633 // Intrinsic operation, reg.
1634 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1635 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1636 [(set VR128:$dst, (F64Int VR128:$src))]> {
1637 let isCommutable = Commutable;
1640 // Intrinsic operation, mem.
1641 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1642 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1643 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1645 // Vector intrinsic operation, reg
1646 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1647 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1648 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1649 let isCommutable = Commutable;
1652 // Vector intrinsic operation, mem
1653 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1654 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1655 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1659 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1660 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1662 // There is no f64 version of the reciprocal approximation instructions.
1665 let Constraints = "$src1 = $dst" in {
1666 let isCommutable = 1 in {
1667 def ANDPDrr : PDI<0x54, MRMSrcReg,
1668 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1669 "andpd\t{$src2, $dst|$dst, $src2}",
1671 (and (bc_v2i64 (v2f64 VR128:$src1)),
1672 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1673 def ORPDrr : PDI<0x56, MRMSrcReg,
1674 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1675 "orpd\t{$src2, $dst|$dst, $src2}",
1677 (or (bc_v2i64 (v2f64 VR128:$src1)),
1678 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1679 def XORPDrr : PDI<0x57, MRMSrcReg,
1680 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1681 "xorpd\t{$src2, $dst|$dst, $src2}",
1683 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1684 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1687 def ANDPDrm : PDI<0x54, MRMSrcMem,
1688 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1689 "andpd\t{$src2, $dst|$dst, $src2}",
1691 (and (bc_v2i64 (v2f64 VR128:$src1)),
1692 (memopv2i64 addr:$src2)))]>;
1693 def ORPDrm : PDI<0x56, MRMSrcMem,
1694 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1695 "orpd\t{$src2, $dst|$dst, $src2}",
1697 (or (bc_v2i64 (v2f64 VR128:$src1)),
1698 (memopv2i64 addr:$src2)))]>;
1699 def XORPDrm : PDI<0x57, MRMSrcMem,
1700 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1701 "xorpd\t{$src2, $dst|$dst, $src2}",
1703 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1704 (memopv2i64 addr:$src2)))]>;
1705 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1706 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1707 "andnpd\t{$src2, $dst|$dst, $src2}",
1709 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1710 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1711 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1712 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1713 "andnpd\t{$src2, $dst|$dst, $src2}",
1715 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1716 (memopv2i64 addr:$src2)))]>;
1719 let Constraints = "$src1 = $dst" in {
1720 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1721 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1722 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1723 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1724 VR128:$src, imm:$cc))]>;
1725 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1726 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1727 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1728 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1729 (memop addr:$src), imm:$cc))]>;
1731 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1732 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1733 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1734 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1736 // Shuffle and unpack instructions
1737 let Constraints = "$src1 = $dst" in {
1738 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1739 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1740 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1741 [(set VR128:$dst, (v2f64 (vector_shuffle
1742 VR128:$src1, VR128:$src2,
1743 SHUFP_shuffle_mask:$src3)))]>;
1744 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1745 (outs VR128:$dst), (ins VR128:$src1,
1746 f128mem:$src2, i8imm:$src3),
1747 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1749 (v2f64 (vector_shuffle
1750 VR128:$src1, (memopv2f64 addr:$src2),
1751 SHUFP_shuffle_mask:$src3)))]>;
1753 let AddedComplexity = 10 in {
1754 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1755 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1756 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1758 (v2f64 (vector_shuffle
1759 VR128:$src1, VR128:$src2,
1760 UNPCKH_shuffle_mask)))]>;
1761 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1762 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1763 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1765 (v2f64 (vector_shuffle
1766 VR128:$src1, (memopv2f64 addr:$src2),
1767 UNPCKH_shuffle_mask)))]>;
1769 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1770 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1771 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1773 (v2f64 (vector_shuffle
1774 VR128:$src1, VR128:$src2,
1775 UNPCKL_shuffle_mask)))]>;
1776 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1777 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1778 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1780 (v2f64 (vector_shuffle
1781 VR128:$src1, (memopv2f64 addr:$src2),
1782 UNPCKL_shuffle_mask)))]>;
1783 } // AddedComplexity
1784 } // Constraints = "$src1 = $dst"
1787 //===----------------------------------------------------------------------===//
1788 // SSE integer instructions
1790 // Move Instructions
1791 let neverHasSideEffects = 1 in
1792 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1793 "movdqa\t{$src, $dst|$dst, $src}", []>;
1794 let isSimpleLoad = 1, mayLoad = 1 in
1795 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1796 "movdqa\t{$src, $dst|$dst, $src}",
1797 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1799 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1800 "movdqa\t{$src, $dst|$dst, $src}",
1801 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1802 let isSimpleLoad = 1, mayLoad = 1 in
1803 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1804 "movdqu\t{$src, $dst|$dst, $src}",
1805 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1806 XS, Requires<[HasSSE2]>;
1808 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1809 "movdqu\t{$src, $dst|$dst, $src}",
1810 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1811 XS, Requires<[HasSSE2]>;
1813 // Intrinsic forms of MOVDQU load and store
1814 let isSimpleLoad = 1 in
1815 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1816 "movdqu\t{$src, $dst|$dst, $src}",
1817 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1818 XS, Requires<[HasSSE2]>;
1819 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1820 "movdqu\t{$src, $dst|$dst, $src}",
1821 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1822 XS, Requires<[HasSSE2]>;
1824 let Constraints = "$src1 = $dst" in {
1826 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1827 bit Commutable = 0> {
1828 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1829 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1830 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1831 let isCommutable = Commutable;
1833 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1834 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1835 [(set VR128:$dst, (IntId VR128:$src1,
1836 (bitconvert (memopv2i64 addr:$src2))))]>;
1839 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1841 Intrinsic IntId, Intrinsic IntId2> {
1842 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1843 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1844 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1845 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1846 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1847 [(set VR128:$dst, (IntId VR128:$src1,
1848 (bitconvert (memopv2i64 addr:$src2))))]>;
1849 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1850 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1851 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1854 /// PDI_binop_rm - Simple SSE2 binary operator.
1855 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1856 ValueType OpVT, bit Commutable = 0> {
1857 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1858 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1859 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1860 let isCommutable = Commutable;
1862 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1863 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1864 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1865 (bitconvert (memopv2i64 addr:$src2)))))]>;
1868 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1870 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1871 /// to collapse (bitconvert VT to VT) into its operand.
1873 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1874 bit Commutable = 0> {
1875 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1876 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1877 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1878 let isCommutable = Commutable;
1880 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1881 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1882 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1885 } // Constraints = "$src1 = $dst"
1887 // 128-bit Integer Arithmetic
1889 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1890 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1891 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1892 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1894 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1895 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1896 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1897 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1899 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1900 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1901 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1902 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1904 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1905 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1906 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1907 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1909 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1911 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1912 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1913 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1915 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1917 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1918 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1921 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1922 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1923 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1924 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1925 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1928 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1929 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1930 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
1931 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
1932 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
1933 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
1935 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
1936 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
1937 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
1938 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
1939 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
1940 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
1942 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
1943 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
1944 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
1945 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
1947 // 128-bit logical shifts.
1948 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1949 def PSLLDQri : PDIi8<0x73, MRM7r,
1950 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1951 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1952 def PSRLDQri : PDIi8<0x73, MRM3r,
1953 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1954 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1955 // PSRADQri doesn't exist in SSE[1-3].
1958 let Predicates = [HasSSE2] in {
1959 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1960 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1961 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1962 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1963 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1964 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1966 // Shift up / down and insert zero's.
1967 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
1968 (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1969 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
1970 (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1974 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1975 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1976 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1978 let Constraints = "$src1 = $dst" in {
1979 def PANDNrr : PDI<0xDF, MRMSrcReg,
1980 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1981 "pandn\t{$src2, $dst|$dst, $src2}",
1982 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1985 def PANDNrm : PDI<0xDF, MRMSrcMem,
1986 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1987 "pandn\t{$src2, $dst|$dst, $src2}",
1988 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1989 (memopv2i64 addr:$src2))))]>;
1992 // SSE2 Integer comparison
1993 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1994 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1995 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1996 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1997 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1998 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2000 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2001 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2002 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2003 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2004 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2005 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2006 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2007 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2008 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2009 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2010 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2011 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2013 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2014 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2015 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2016 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2017 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2018 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2019 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2020 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2021 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2022 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2023 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2024 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2027 // Pack instructions
2028 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2029 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2030 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2032 // Shuffle and unpack instructions
2033 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2034 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2035 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2036 [(set VR128:$dst, (v4i32 (vector_shuffle
2037 VR128:$src1, (undef),
2038 PSHUFD_shuffle_mask:$src2)))]>;
2039 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2040 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2041 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2042 [(set VR128:$dst, (v4i32 (vector_shuffle
2043 (bc_v4i32(memopv2i64 addr:$src1)),
2045 PSHUFD_shuffle_mask:$src2)))]>;
2047 // SSE2 with ImmT == Imm8 and XS prefix.
2048 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2049 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2050 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2051 [(set VR128:$dst, (v8i16 (vector_shuffle
2052 VR128:$src1, (undef),
2053 PSHUFHW_shuffle_mask:$src2)))]>,
2054 XS, Requires<[HasSSE2]>;
2055 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2056 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2057 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2058 [(set VR128:$dst, (v8i16 (vector_shuffle
2059 (bc_v8i16 (memopv2i64 addr:$src1)),
2061 PSHUFHW_shuffle_mask:$src2)))]>,
2062 XS, Requires<[HasSSE2]>;
2064 // SSE2 with ImmT == Imm8 and XD prefix.
2065 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2066 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2067 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2068 [(set VR128:$dst, (v8i16 (vector_shuffle
2069 VR128:$src1, (undef),
2070 PSHUFLW_shuffle_mask:$src2)))]>,
2071 XD, Requires<[HasSSE2]>;
2072 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2073 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
2074 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2075 [(set VR128:$dst, (v8i16 (vector_shuffle
2076 (bc_v8i16 (memopv2i64 addr:$src1)),
2078 PSHUFLW_shuffle_mask:$src2)))]>,
2079 XD, Requires<[HasSSE2]>;
2082 let Constraints = "$src1 = $dst" in {
2083 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2084 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2085 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2087 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2088 UNPCKL_shuffle_mask)))]>;
2089 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2090 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2091 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2093 (v16i8 (vector_shuffle VR128:$src1,
2094 (bc_v16i8 (memopv2i64 addr:$src2)),
2095 UNPCKL_shuffle_mask)))]>;
2096 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2097 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2098 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2100 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2101 UNPCKL_shuffle_mask)))]>;
2102 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2103 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2104 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2106 (v8i16 (vector_shuffle VR128:$src1,
2107 (bc_v8i16 (memopv2i64 addr:$src2)),
2108 UNPCKL_shuffle_mask)))]>;
2109 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2110 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2111 "punpckldq\t{$src2, $dst|$dst, $src2}",
2113 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2114 UNPCKL_shuffle_mask)))]>;
2115 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2116 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2117 "punpckldq\t{$src2, $dst|$dst, $src2}",
2119 (v4i32 (vector_shuffle VR128:$src1,
2120 (bc_v4i32 (memopv2i64 addr:$src2)),
2121 UNPCKL_shuffle_mask)))]>;
2122 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2123 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2124 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2126 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2127 UNPCKL_shuffle_mask)))]>;
2128 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2129 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2130 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2132 (v2i64 (vector_shuffle VR128:$src1,
2133 (memopv2i64 addr:$src2),
2134 UNPCKL_shuffle_mask)))]>;
2136 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2137 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2138 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2140 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2141 UNPCKH_shuffle_mask)))]>;
2142 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2143 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2144 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2146 (v16i8 (vector_shuffle VR128:$src1,
2147 (bc_v16i8 (memopv2i64 addr:$src2)),
2148 UNPCKH_shuffle_mask)))]>;
2149 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2150 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2151 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2153 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2154 UNPCKH_shuffle_mask)))]>;
2155 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2156 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2157 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2159 (v8i16 (vector_shuffle VR128:$src1,
2160 (bc_v8i16 (memopv2i64 addr:$src2)),
2161 UNPCKH_shuffle_mask)))]>;
2162 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2163 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2164 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2166 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2167 UNPCKH_shuffle_mask)))]>;
2168 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2169 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2170 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2172 (v4i32 (vector_shuffle VR128:$src1,
2173 (bc_v4i32 (memopv2i64 addr:$src2)),
2174 UNPCKH_shuffle_mask)))]>;
2175 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2176 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2177 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2179 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2180 UNPCKH_shuffle_mask)))]>;
2181 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2182 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2183 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2185 (v2i64 (vector_shuffle VR128:$src1,
2186 (memopv2i64 addr:$src2),
2187 UNPCKH_shuffle_mask)))]>;
2191 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2192 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2193 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2194 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2196 let Constraints = "$src1 = $dst" in {
2197 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2198 (outs VR128:$dst), (ins VR128:$src1,
2199 GR32:$src2, i32i8imm:$src3),
2200 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2202 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2203 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2204 (outs VR128:$dst), (ins VR128:$src1,
2205 i16mem:$src2, i32i8imm:$src3),
2206 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2208 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2213 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2214 "pmovmskb\t{$src, $dst|$dst, $src}",
2215 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2217 // Conditional store
2219 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2220 "maskmovdqu\t{$mask, $src|$src, $mask}",
2221 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2223 // Non-temporal stores
2224 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2225 "movntpd\t{$src, $dst|$dst, $src}",
2226 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2227 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2228 "movntdq\t{$src, $dst|$dst, $src}",
2229 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2230 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2231 "movnti\t{$src, $dst|$dst, $src}",
2232 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2233 TB, Requires<[HasSSE2]>;
2236 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2237 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2238 TB, Requires<[HasSSE2]>;
2240 // Load, store, and memory fence
2241 def LFENCE : I<0xAE, MRM5m, (outs), (ins),
2242 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2243 def MFENCE : I<0xAE, MRM6m, (outs), (ins),
2244 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2246 //TODO: custom lower this so as to never even generate the noop
2247 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2249 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2250 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2251 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2254 // Alias instructions that map zero vector to pxor / xorp* for sse.
2255 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
2256 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2257 "pcmpeqd\t$dst, $dst",
2258 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2260 // FR64 to 128-bit vector conversion.
2261 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2262 "movsd\t{$src, $dst|$dst, $src}",
2264 (v2f64 (scalar_to_vector FR64:$src)))]>;
2265 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2266 "movsd\t{$src, $dst|$dst, $src}",
2268 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2270 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2271 "movd\t{$src, $dst|$dst, $src}",
2273 (v4i32 (scalar_to_vector GR32:$src)))]>;
2274 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2275 "movd\t{$src, $dst|$dst, $src}",
2277 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2279 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2280 "movd\t{$src, $dst|$dst, $src}",
2281 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2283 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2284 "movd\t{$src, $dst|$dst, $src}",
2285 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2287 // SSE2 instructions with XS prefix
2288 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2289 "movq\t{$src, $dst|$dst, $src}",
2291 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2292 Requires<[HasSSE2]>;
2293 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2294 "movq\t{$src, $dst|$dst, $src}",
2295 [(store (i64 (vector_extract (v2i64 VR128:$src),
2296 (iPTR 0))), addr:$dst)]>;
2298 // FIXME: may not be able to eliminate this movss with coalescing the src and
2299 // dest register classes are different. We really want to write this pattern
2301 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2302 // (f32 FR32:$src)>;
2303 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2304 "movsd\t{$src, $dst|$dst, $src}",
2305 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2307 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2308 "movsd\t{$src, $dst|$dst, $src}",
2309 [(store (f64 (vector_extract (v2f64 VR128:$src),
2310 (iPTR 0))), addr:$dst)]>;
2311 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2312 "movd\t{$src, $dst|$dst, $src}",
2313 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2315 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2316 "movd\t{$src, $dst|$dst, $src}",
2317 [(store (i32 (vector_extract (v4i32 VR128:$src),
2318 (iPTR 0))), addr:$dst)]>;
2320 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2321 "movd\t{$src, $dst|$dst, $src}",
2322 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2323 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2324 "movd\t{$src, $dst|$dst, $src}",
2325 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2328 // Move to lower bits of a VR128, leaving upper bits alone.
2329 // Three operand (but two address) aliases.
2330 let Constraints = "$src1 = $dst" in {
2331 let neverHasSideEffects = 1 in
2332 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2333 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2334 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2336 let AddedComplexity = 15 in
2337 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2338 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2339 "movsd\t{$src2, $dst|$dst, $src2}",
2341 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2342 MOVL_shuffle_mask)))]>;
2345 // Store / copy lower 64-bits of a XMM register.
2346 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2347 "movq\t{$src, $dst|$dst, $src}",
2348 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2350 // Move to lower bits of a VR128 and zeroing upper bits.
2351 // Loading from memory automatically zeroing upper bits.
2352 let AddedComplexity = 20 in {
2353 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2354 "movsd\t{$src, $dst|$dst, $src}",
2356 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2357 (loadf64 addr:$src))))))]>;
2359 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2360 (MOVZSD2PDrm addr:$src)>;
2361 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2362 (MOVZSD2PDrm addr:$src)>;
2363 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2366 // movd / movq to XMM register zero-extends
2367 let AddedComplexity = 15 in {
2368 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2369 "movd\t{$src, $dst|$dst, $src}",
2370 [(set VR128:$dst, (v4i32 (X86vzmovl
2371 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2372 // This is X86-64 only.
2373 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2374 "mov{d|q}\t{$src, $dst|$dst, $src}",
2375 [(set VR128:$dst, (v2i64 (X86vzmovl
2376 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2379 let AddedComplexity = 20 in {
2380 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2381 "movd\t{$src, $dst|$dst, $src}",
2383 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2384 (loadi32 addr:$src))))))]>;
2386 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2387 (MOVZDI2PDIrm addr:$src)>;
2388 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2389 (MOVZDI2PDIrm addr:$src)>;
2390 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2391 (MOVZDI2PDIrm addr:$src)>;
2393 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2394 "movq\t{$src, $dst|$dst, $src}",
2396 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2397 (loadi64 addr:$src))))))]>, XS,
2398 Requires<[HasSSE2]>;
2400 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2401 (MOVZQI2PQIrm addr:$src)>;
2402 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2403 (MOVZQI2PQIrm addr:$src)>;
2404 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2407 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2408 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2409 let AddedComplexity = 15 in
2410 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2411 "movq\t{$src, $dst|$dst, $src}",
2412 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2413 XS, Requires<[HasSSE2]>;
2415 let AddedComplexity = 20 in {
2416 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2417 "movq\t{$src, $dst|$dst, $src}",
2418 [(set VR128:$dst, (v2i64 (X86vzmovl
2419 (loadv2i64 addr:$src))))]>,
2420 XS, Requires<[HasSSE2]>;
2422 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2423 (MOVZPQILo2PQIrm addr:$src)>;
2426 //===----------------------------------------------------------------------===//
2427 // SSE3 Instructions
2428 //===----------------------------------------------------------------------===//
2430 // Move Instructions
2431 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2432 "movshdup\t{$src, $dst|$dst, $src}",
2433 [(set VR128:$dst, (v4f32 (vector_shuffle
2434 VR128:$src, (undef),
2435 MOVSHDUP_shuffle_mask)))]>;
2436 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2437 "movshdup\t{$src, $dst|$dst, $src}",
2438 [(set VR128:$dst, (v4f32 (vector_shuffle
2439 (memopv4f32 addr:$src), (undef),
2440 MOVSHDUP_shuffle_mask)))]>;
2442 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2443 "movsldup\t{$src, $dst|$dst, $src}",
2444 [(set VR128:$dst, (v4f32 (vector_shuffle
2445 VR128:$src, (undef),
2446 MOVSLDUP_shuffle_mask)))]>;
2447 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2448 "movsldup\t{$src, $dst|$dst, $src}",
2449 [(set VR128:$dst, (v4f32 (vector_shuffle
2450 (memopv4f32 addr:$src), (undef),
2451 MOVSLDUP_shuffle_mask)))]>;
2453 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2454 "movddup\t{$src, $dst|$dst, $src}",
2455 [(set VR128:$dst, (v2f64 (vector_shuffle
2456 VR128:$src, (undef),
2457 SSE_splat_lo_mask)))]>;
2458 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2459 "movddup\t{$src, $dst|$dst, $src}",
2461 (v2f64 (vector_shuffle
2462 (scalar_to_vector (loadf64 addr:$src)),
2464 SSE_splat_lo_mask)))]>;
2467 let Constraints = "$src1 = $dst" in {
2468 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2469 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2470 "addsubps\t{$src2, $dst|$dst, $src2}",
2471 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2473 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2474 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2475 "addsubps\t{$src2, $dst|$dst, $src2}",
2476 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2477 (memop addr:$src2)))]>;
2478 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2479 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2480 "addsubpd\t{$src2, $dst|$dst, $src2}",
2481 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2483 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2484 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2485 "addsubpd\t{$src2, $dst|$dst, $src2}",
2486 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2487 (memop addr:$src2)))]>;
2490 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2491 "lddqu\t{$src, $dst|$dst, $src}",
2492 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2495 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2496 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2497 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2498 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2499 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2500 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2501 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2502 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2503 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2504 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2505 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2506 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2507 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2508 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2509 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2510 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2512 let Constraints = "$src1 = $dst" in {
2513 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2514 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2515 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2516 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2517 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2518 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2519 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2520 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2523 // Thread synchronization
2524 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2525 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2526 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2527 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2529 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2530 let AddedComplexity = 15 in
2531 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2532 MOVSHDUP_shuffle_mask)),
2533 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2534 let AddedComplexity = 20 in
2535 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2536 MOVSHDUP_shuffle_mask)),
2537 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2539 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2540 let AddedComplexity = 15 in
2541 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2542 MOVSLDUP_shuffle_mask)),
2543 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2544 let AddedComplexity = 20 in
2545 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2546 MOVSLDUP_shuffle_mask)),
2547 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2549 //===----------------------------------------------------------------------===//
2550 // SSSE3 Instructions
2551 //===----------------------------------------------------------------------===//
2553 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2554 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2555 Intrinsic IntId64, Intrinsic IntId128> {
2556 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2557 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2558 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2560 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2561 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2563 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2565 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2567 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2568 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2571 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2573 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2576 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2579 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2580 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2581 Intrinsic IntId64, Intrinsic IntId128> {
2582 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2585 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2587 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2589 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2592 (bitconvert (memopv4i16 addr:$src))))]>;
2594 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2596 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2597 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2600 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2602 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2605 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2608 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2609 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2610 Intrinsic IntId64, Intrinsic IntId128> {
2611 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2613 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2614 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2616 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2618 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2621 (bitconvert (memopv2i32 addr:$src))))]>;
2623 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2625 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2626 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2629 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2631 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2634 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2637 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2638 int_x86_ssse3_pabs_b,
2639 int_x86_ssse3_pabs_b_128>;
2640 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2641 int_x86_ssse3_pabs_w,
2642 int_x86_ssse3_pabs_w_128>;
2643 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2644 int_x86_ssse3_pabs_d,
2645 int_x86_ssse3_pabs_d_128>;
2647 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2648 let Constraints = "$src1 = $dst" in {
2649 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2650 Intrinsic IntId64, Intrinsic IntId128,
2651 bit Commutable = 0> {
2652 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2653 (ins VR64:$src1, VR64:$src2),
2654 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2655 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2656 let isCommutable = Commutable;
2658 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2659 (ins VR64:$src1, i64mem:$src2),
2660 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2662 (IntId64 VR64:$src1,
2663 (bitconvert (memopv8i8 addr:$src2))))]>;
2665 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2666 (ins VR128:$src1, VR128:$src2),
2667 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2668 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2670 let isCommutable = Commutable;
2672 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2673 (ins VR128:$src1, i128mem:$src2),
2674 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2676 (IntId128 VR128:$src1,
2677 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2681 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2682 let Constraints = "$src1 = $dst" in {
2683 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2684 Intrinsic IntId64, Intrinsic IntId128,
2685 bit Commutable = 0> {
2686 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2687 (ins VR64:$src1, VR64:$src2),
2688 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2689 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2690 let isCommutable = Commutable;
2692 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2693 (ins VR64:$src1, i64mem:$src2),
2694 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2696 (IntId64 VR64:$src1,
2697 (bitconvert (memopv4i16 addr:$src2))))]>;
2699 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2700 (ins VR128:$src1, VR128:$src2),
2701 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2702 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2704 let isCommutable = Commutable;
2706 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2707 (ins VR128:$src1, i128mem:$src2),
2708 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2710 (IntId128 VR128:$src1,
2711 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2715 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2716 let Constraints = "$src1 = $dst" in {
2717 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2718 Intrinsic IntId64, Intrinsic IntId128,
2719 bit Commutable = 0> {
2720 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2721 (ins VR64:$src1, VR64:$src2),
2722 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2723 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2724 let isCommutable = Commutable;
2726 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2727 (ins VR64:$src1, i64mem:$src2),
2728 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2730 (IntId64 VR64:$src1,
2731 (bitconvert (memopv2i32 addr:$src2))))]>;
2733 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2734 (ins VR128:$src1, VR128:$src2),
2735 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2736 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2738 let isCommutable = Commutable;
2740 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2741 (ins VR128:$src1, i128mem:$src2),
2742 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2744 (IntId128 VR128:$src1,
2745 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2749 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2750 int_x86_ssse3_phadd_w,
2751 int_x86_ssse3_phadd_w_128>;
2752 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2753 int_x86_ssse3_phadd_d,
2754 int_x86_ssse3_phadd_d_128>;
2755 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2756 int_x86_ssse3_phadd_sw,
2757 int_x86_ssse3_phadd_sw_128>;
2758 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2759 int_x86_ssse3_phsub_w,
2760 int_x86_ssse3_phsub_w_128>;
2761 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2762 int_x86_ssse3_phsub_d,
2763 int_x86_ssse3_phsub_d_128>;
2764 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2765 int_x86_ssse3_phsub_sw,
2766 int_x86_ssse3_phsub_sw_128>;
2767 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2768 int_x86_ssse3_pmadd_ub_sw,
2769 int_x86_ssse3_pmadd_ub_sw_128>;
2770 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2771 int_x86_ssse3_pmul_hr_sw,
2772 int_x86_ssse3_pmul_hr_sw_128, 1>;
2773 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2774 int_x86_ssse3_pshuf_b,
2775 int_x86_ssse3_pshuf_b_128>;
2776 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2777 int_x86_ssse3_psign_b,
2778 int_x86_ssse3_psign_b_128>;
2779 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2780 int_x86_ssse3_psign_w,
2781 int_x86_ssse3_psign_w_128>;
2782 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2783 int_x86_ssse3_psign_d,
2784 int_x86_ssse3_psign_d_128>;
2786 let Constraints = "$src1 = $dst" in {
2787 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2788 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2789 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2791 (int_x86_ssse3_palign_r
2792 VR64:$src1, VR64:$src2,
2794 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2795 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2796 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2798 (int_x86_ssse3_palign_r
2800 (bitconvert (memopv2i32 addr:$src2)),
2803 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2804 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2805 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2807 (int_x86_ssse3_palign_r_128
2808 VR128:$src1, VR128:$src2,
2809 imm:$src3))]>, OpSize;
2810 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2811 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2812 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2814 (int_x86_ssse3_palign_r_128
2816 (bitconvert (memopv4i32 addr:$src2)),
2817 imm:$src3))]>, OpSize;
2820 //===----------------------------------------------------------------------===//
2821 // Non-Instruction Patterns
2822 //===----------------------------------------------------------------------===//
2824 // extload f32 -> f64. This matches load+fextend because we have a hack in
2825 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2826 // Since these loads aren't folded into the fextend, we have to match it
2828 let Predicates = [HasSSE2] in
2829 def : Pat<(fextend (loadf32 addr:$src)),
2830 (CVTSS2SDrm addr:$src)>;
2833 let Predicates = [HasSSE2] in {
2834 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2835 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2836 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2837 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2838 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2839 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2840 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2841 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2842 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2843 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2844 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2845 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2846 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2847 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2848 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2849 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2850 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2851 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2852 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2853 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2854 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2855 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2856 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2857 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2858 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2859 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2860 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2861 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2862 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2863 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2866 // Move scalar to XMM zero-extended
2867 // movd to XMM register zero-extends
2868 let AddedComplexity = 15 in {
2869 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2870 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2871 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2872 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2873 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2874 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2875 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
2876 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2877 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
2880 // Splat v2f64 / v2i64
2881 let AddedComplexity = 10 in {
2882 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2883 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2884 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2885 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2886 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2887 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2888 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2889 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2892 // Special unary SHUFPSrri case.
2893 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2894 SHUFP_unary_shuffle_mask:$sm)),
2895 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2896 Requires<[HasSSE1]>;
2897 // Special unary SHUFPDrri case.
2898 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
2899 SHUFP_unary_shuffle_mask:$sm)),
2900 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2901 Requires<[HasSSE2]>;
2902 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2903 def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef),
2904 SHUFP_unary_shuffle_mask:$sm),
2905 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2906 Requires<[HasSSE2]>;
2907 // Special binary v4i32 shuffle cases with SHUFPS.
2908 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
2909 PSHUFD_binary_shuffle_mask:$sm)),
2910 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2911 Requires<[HasSSE2]>;
2912 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2913 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
2914 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2915 Requires<[HasSSE2]>;
2916 // Special binary v2i64 shuffle cases using SHUFPDrri.
2917 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2918 SHUFP_shuffle_mask:$sm)),
2919 (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
2920 Requires<[HasSSE2]>;
2921 // Special unary SHUFPDrri case.
2922 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
2923 SHUFP_unary_shuffle_mask:$sm)),
2924 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2925 Requires<[HasSSE2]>;
2927 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2928 let AddedComplexity = 10 in {
2929 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2930 UNPCKL_v_undef_shuffle_mask)),
2931 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2932 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2933 UNPCKL_v_undef_shuffle_mask)),
2934 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2935 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2936 UNPCKL_v_undef_shuffle_mask)),
2937 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2938 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2939 UNPCKL_v_undef_shuffle_mask)),
2940 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2943 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2944 let AddedComplexity = 10 in {
2945 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2946 UNPCKH_v_undef_shuffle_mask)),
2947 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2948 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2949 UNPCKH_v_undef_shuffle_mask)),
2950 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2951 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2952 UNPCKH_v_undef_shuffle_mask)),
2953 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2954 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2955 UNPCKH_v_undef_shuffle_mask)),
2956 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2959 let AddedComplexity = 15 in {
2960 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2961 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2962 MOVHP_shuffle_mask)),
2963 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2965 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2966 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2967 MOVHLPS_shuffle_mask)),
2968 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2970 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2971 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2972 MOVHLPS_v_undef_shuffle_mask)),
2973 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2974 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2975 MOVHLPS_v_undef_shuffle_mask)),
2976 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2979 let AddedComplexity = 20 in {
2980 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2981 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2982 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
2983 MOVLP_shuffle_mask)),
2984 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2985 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
2986 MOVLP_shuffle_mask)),
2987 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2988 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
2989 MOVHP_shuffle_mask)),
2990 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2991 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
2992 MOVHP_shuffle_mask)),
2993 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2995 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2996 (bc_v4i32 (memopv2i64 addr:$src2)),
2997 MOVLP_shuffle_mask)),
2998 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2999 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3000 MOVLP_shuffle_mask)),
3001 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3002 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
3003 (bc_v4i32 (memopv2i64 addr:$src2)),
3004 MOVHP_shuffle_mask)),
3005 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3006 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3007 MOVHP_shuffle_mask)),
3008 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3011 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3012 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
3013 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3014 MOVLP_shuffle_mask)), addr:$src1),
3015 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3016 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3017 MOVLP_shuffle_mask)), addr:$src1),
3018 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3019 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3020 MOVHP_shuffle_mask)), addr:$src1),
3021 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3022 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3023 MOVHP_shuffle_mask)), addr:$src1),
3024 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3026 def : Pat<(store (v4i32 (vector_shuffle
3027 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3028 MOVLP_shuffle_mask)), addr:$src1),
3029 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3030 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3031 MOVLP_shuffle_mask)), addr:$src1),
3032 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3033 def : Pat<(store (v4i32 (vector_shuffle
3034 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3035 MOVHP_shuffle_mask)), addr:$src1),
3036 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3037 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3038 MOVHP_shuffle_mask)), addr:$src1),
3039 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3042 let AddedComplexity = 15 in {
3043 // Setting the lowest element in the vector.
3044 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3045 MOVL_shuffle_mask)),
3046 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3047 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
3048 MOVL_shuffle_mask)),
3049 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3051 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
3052 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
3053 MOVLP_shuffle_mask)),
3054 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3055 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3056 MOVLP_shuffle_mask)),
3057 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3060 // Set lowest element and zero upper elements.
3061 let AddedComplexity = 15 in
3062 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
3063 MOVL_shuffle_mask)),
3064 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3065 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3066 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3068 // Some special case pandn patterns.
3069 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3071 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3072 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3074 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3075 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3077 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3079 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3080 (memop addr:$src2))),
3081 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3082 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3083 (memop addr:$src2))),
3084 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3085 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3086 (memop addr:$src2))),
3087 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3089 // vector -> vector casts
3090 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3091 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3092 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3093 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3094 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3095 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3096 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3097 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3099 // Use movaps / movups for SSE integer load / store (one byte shorter).
3100 def : Pat<(alignedloadv4i32 addr:$src),
3101 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3102 def : Pat<(loadv4i32 addr:$src),
3103 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3104 def : Pat<(alignedloadv2i64 addr:$src),
3105 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3106 def : Pat<(loadv2i64 addr:$src),
3107 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3109 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3110 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3111 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3112 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3113 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3114 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3115 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3116 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3117 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3118 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3119 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3120 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3121 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3122 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3123 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3124 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3126 //===----------------------------------------------------------------------===//
3127 // SSE4.1 Instructions
3128 //===----------------------------------------------------------------------===//
3130 multiclass sse41_fp_unop_rm<bits<8> opcss, bits<8> opcps,
3131 bits<8> opcsd, bits<8> opcpd,
3136 Intrinsic V2F64Int> {
3137 // Intrinsic operation, reg.
3138 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3139 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3140 !strconcat(OpcodeStr,
3141 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3142 [(set VR128:$dst, (F32Int VR128:$src1, imm:$src2))]>,
3145 // Intrinsic operation, mem.
3146 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3147 (outs VR128:$dst), (ins ssmem:$src1, i32i8imm:$src2),
3148 !strconcat(OpcodeStr,
3149 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3150 [(set VR128:$dst, (F32Int sse_load_f32:$src1, imm:$src2))]>,
3153 // Vector intrinsic operation, reg
3154 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3155 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3156 !strconcat(OpcodeStr,
3157 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3158 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3161 // Vector intrinsic operation, mem
3162 def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
3163 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3164 !strconcat(OpcodeStr,
3165 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3167 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3170 // Intrinsic operation, reg.
3171 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3172 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3173 !strconcat(OpcodeStr,
3174 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3175 [(set VR128:$dst, (F64Int VR128:$src1, imm:$src2))]>,
3178 // Intrinsic operation, mem.
3179 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3180 (outs VR128:$dst), (ins sdmem:$src1, i32i8imm:$src2),
3181 !strconcat(OpcodeStr,
3182 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3183 [(set VR128:$dst, (F64Int sse_load_f64:$src1, imm:$src2))]>,
3186 // Vector intrinsic operation, reg
3187 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3188 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3189 !strconcat(OpcodeStr,
3190 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3191 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3194 // Vector intrinsic operation, mem
3195 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3196 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3197 !strconcat(OpcodeStr,
3198 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3200 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3204 // FP round - roundss, roundps, roundsd, roundpd
3205 defm ROUND : sse41_fp_unop_rm<0x0A, 0x08, 0x0B, 0x09, "round",
3206 int_x86_sse41_round_ss, int_x86_sse41_round_ps,
3207 int_x86_sse41_round_sd, int_x86_sse41_round_pd>;
3209 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3210 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3211 Intrinsic IntId128> {
3212 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3214 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3215 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3216 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3218 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3221 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3224 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3225 int_x86_sse41_phminposuw>;
3227 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3228 let Constraints = "$src1 = $dst" in {
3229 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3230 Intrinsic IntId128, bit Commutable = 0> {
3231 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3232 (ins VR128:$src1, VR128:$src2),
3233 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3234 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3236 let isCommutable = Commutable;
3238 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3239 (ins VR128:$src1, i128mem:$src2),
3240 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3242 (IntId128 VR128:$src1,
3243 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3247 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3248 int_x86_sse41_pcmpeqq, 1>;
3249 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3250 int_x86_sse41_packusdw, 0>;
3251 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3252 int_x86_sse41_pminsb, 1>;
3253 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3254 int_x86_sse41_pminsd, 1>;
3255 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3256 int_x86_sse41_pminud, 1>;
3257 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3258 int_x86_sse41_pminuw, 1>;
3259 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3260 int_x86_sse41_pmaxsb, 1>;
3261 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3262 int_x86_sse41_pmaxsd, 1>;
3263 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3264 int_x86_sse41_pmaxud, 1>;
3265 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3266 int_x86_sse41_pmaxuw, 1>;
3268 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3269 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3270 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3271 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3274 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3275 let Constraints = "$src1 = $dst" in {
3276 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3277 SDNode OpNode, Intrinsic IntId128,
3278 bit Commutable = 0> {
3279 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3280 (ins VR128:$src1, VR128:$src2),
3281 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3282 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3283 VR128:$src2))]>, OpSize {
3284 let isCommutable = Commutable;
3286 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3287 (ins VR128:$src1, VR128:$src2),
3288 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3289 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3291 let isCommutable = Commutable;
3293 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3294 (ins VR128:$src1, i128mem:$src2),
3295 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3297 (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
3298 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3299 (ins VR128:$src1, i128mem:$src2),
3300 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3302 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3306 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3307 int_x86_sse41_pmulld, 1>;
3308 defm PMULDQ : SS41I_binop_patint<0x28, "pmuldq", v2i64, mul,
3309 int_x86_sse41_pmuldq, 1>;
3312 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3313 let Constraints = "$src1 = $dst" in {
3314 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3315 Intrinsic IntId128, bit Commutable = 0> {
3316 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3317 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3318 !strconcat(OpcodeStr,
3319 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3321 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3323 let isCommutable = Commutable;
3325 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3326 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3327 !strconcat(OpcodeStr,
3328 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3330 (IntId128 VR128:$src1,
3331 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3336 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3337 int_x86_sse41_blendps, 0>;
3338 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3339 int_x86_sse41_blendpd, 0>;
3340 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3341 int_x86_sse41_pblendw, 0>;
3342 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3343 int_x86_sse41_dpps, 1>;
3344 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3345 int_x86_sse41_dppd, 1>;
3346 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3347 int_x86_sse41_mpsadbw, 1>;
3350 /// SS41I_ternary_int - SSE 4.1 ternary operator
3351 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3352 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3353 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3354 (ins VR128:$src1, VR128:$src2),
3355 !strconcat(OpcodeStr,
3356 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3357 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3360 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3361 (ins VR128:$src1, i128mem:$src2),
3362 !strconcat(OpcodeStr,
3363 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3366 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3370 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3371 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3372 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3375 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3376 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3377 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3378 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3380 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3381 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3383 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3387 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3388 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3389 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3390 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3391 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3392 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3394 // Common patterns involving scalar load.
3395 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3396 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3397 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3398 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3400 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3401 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3402 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3403 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3405 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3406 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3407 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3408 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3410 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3411 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3412 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3413 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3415 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3416 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3417 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3418 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3420 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3421 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3422 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3423 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3426 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3427 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3428 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3429 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3431 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3432 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3434 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3438 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3439 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3440 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3441 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3443 // Common patterns involving scalar load
3444 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3445 (PMOVSXBDrm addr:$src)>;
3446 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3447 (PMOVSXWQrm addr:$src)>;
3449 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3450 (PMOVZXBDrm addr:$src)>;
3451 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3452 (PMOVZXWQrm addr:$src)>;
3455 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3456 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3457 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3458 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3460 // Expecting a i16 load any extended to i32 value.
3461 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3462 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3463 [(set VR128:$dst, (IntId (bitconvert
3464 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3468 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3469 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
3471 // Common patterns involving scalar load
3472 def : Pat<(int_x86_sse41_pmovsxbq
3473 (bitconvert (v4i32 (X86vzmovl
3474 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3475 (PMOVSXBQrm addr:$src)>;
3477 def : Pat<(int_x86_sse41_pmovzxbq
3478 (bitconvert (v4i32 (X86vzmovl
3479 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3480 (PMOVZXBQrm addr:$src)>;
3483 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3484 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3485 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3486 (ins VR128:$src1, i32i8imm:$src2),
3487 !strconcat(OpcodeStr,
3488 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3489 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3491 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3492 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3493 !strconcat(OpcodeStr,
3494 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3497 // There's an AssertZext in the way of writing the store pattern
3498 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3501 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3504 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3505 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3506 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3507 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3508 !strconcat(OpcodeStr,
3509 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3512 // There's an AssertZext in the way of writing the store pattern
3513 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3516 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3519 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3520 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3521 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3522 (ins VR128:$src1, i32i8imm:$src2),
3523 !strconcat(OpcodeStr,
3524 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3526 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3527 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3528 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3529 !strconcat(OpcodeStr,
3530 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3531 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3532 addr:$dst)]>, OpSize;
3535 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3538 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3540 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3541 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3542 (ins VR128:$src1, i32i8imm:$src2),
3543 !strconcat(OpcodeStr,
3544 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3546 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3548 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3549 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3550 !strconcat(OpcodeStr,
3551 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3552 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3553 addr:$dst)]>, OpSize;
3556 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3558 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3559 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3562 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3563 Requires<[HasSSE41]>;
3565 let Constraints = "$src1 = $dst" in {
3566 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3567 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3568 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3569 !strconcat(OpcodeStr,
3570 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3572 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3573 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3574 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3575 !strconcat(OpcodeStr,
3576 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3578 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3579 imm:$src3))]>, OpSize;
3583 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3585 let Constraints = "$src1 = $dst" in {
3586 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3587 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3588 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3589 !strconcat(OpcodeStr,
3590 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3592 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3594 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3595 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3596 !strconcat(OpcodeStr,
3597 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3599 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3600 imm:$src3)))]>, OpSize;
3604 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3606 let Constraints = "$src1 = $dst" in {
3607 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3608 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3609 (ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
3610 !strconcat(OpcodeStr,
3611 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3613 (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
3614 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3615 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3616 !strconcat(OpcodeStr,
3617 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3619 (X86insrtps VR128:$src1, (loadf32 addr:$src2),
3620 imm:$src3))]>, OpSize;
3624 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3626 let Defs = [EFLAGS] in {
3627 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3628 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3629 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3630 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3633 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3634 "movntdqa\t{$src, $dst|$dst, $src}",
3635 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
3637 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3638 let Constraints = "$src1 = $dst" in {
3639 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3640 Intrinsic IntId128, bit Commutable = 0> {
3641 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3642 (ins VR128:$src1, VR128:$src2),
3643 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3644 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3646 let isCommutable = Commutable;
3648 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3649 (ins VR128:$src1, i128mem:$src2),
3650 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3652 (IntId128 VR128:$src1,
3653 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3657 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3659 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3660 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3661 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3662 (PCMPGTQrm VR128:$src1, addr:$src2)>;