1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // SSE 1 & 2 - Move Instructions
120 //===----------------------------------------------------------------------===//
122 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
123 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
124 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
126 // Loading from memory automatically zeroing upper bits.
127 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
128 PatFrag mem_pat, string OpcodeStr> :
129 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
131 [(set RC:$dst, (mem_pat addr:$src))]>;
133 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
134 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
135 // is used instead. Register-to-register movss/movsd is not modeled as an
136 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
137 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
138 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
139 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
140 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
141 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
143 let canFoldAsLoad = 1, isReMaterializable = 1 in {
144 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
146 let AddedComplexity = 20 in
147 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
150 let Constraints = "$src1 = $dst" in {
151 def MOVSSrr : sse12_move_rr<FR32, v4f32,
152 "movss\t{$src2, $dst|$dst, $src2}">, XS;
153 def MOVSDrr : sse12_move_rr<FR64, v2f64,
154 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
157 let canFoldAsLoad = 1, isReMaterializable = 1 in {
158 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
160 let AddedComplexity = 20 in
161 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
164 let AddedComplexity = 15 in {
165 // Extract the low 32-bit value from one vector and insert it into another.
166 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
167 (MOVSSrr (v4f32 VR128:$src1),
168 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
169 // Extract the low 64-bit value from one vector and insert it into another.
170 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
171 (MOVSDrr (v2f64 VR128:$src1),
172 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
175 // Implicitly promote a 32-bit scalar to a vector.
176 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
177 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
178 // Implicitly promote a 64-bit scalar to a vector.
179 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
180 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
181 // Implicitly promote a 32-bit scalar to a vector.
182 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
183 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
184 // Implicitly promote a 64-bit scalar to a vector.
185 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
186 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
188 let AddedComplexity = 20 in {
189 let Predicates = [HasSSE1] in {
190 // MOVSSrm zeros the high parts of the register; represent this
191 // with SUBREG_TO_REG.
192 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
193 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
194 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
195 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
196 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
197 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
199 let Predicates = [HasSSE2] in {
200 // MOVSDrm zeros the high parts of the register; represent this
201 // with SUBREG_TO_REG.
202 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
203 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
204 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
205 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
206 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
207 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
208 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
209 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
210 def : Pat<(v2f64 (X86vzload addr:$src)),
211 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
215 let AddedComplexity = 20, Predicates = [HasAVX] in {
216 // MOVSSrm zeros the high parts of the register; represent this
217 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
218 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
219 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
220 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
221 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
222 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
223 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
224 // MOVSDrm zeros the high parts of the register; represent this
225 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
226 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
227 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
228 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
229 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
230 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
231 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
232 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
233 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
234 def : Pat<(v2f64 (X86vzload addr:$src)),
235 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
236 // Represent the same patterns above but in the form they appear for
238 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
239 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
240 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
241 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
242 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
243 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
246 // Store scalar value to memory.
247 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
248 "movss\t{$src, $dst|$dst, $src}",
249 [(store FR32:$src, addr:$dst)]>;
250 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
251 "movsd\t{$src, $dst|$dst, $src}",
252 [(store FR64:$src, addr:$dst)]>;
254 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
255 "movss\t{$src, $dst|$dst, $src}",
256 [(store FR32:$src, addr:$dst)]>, XS, VEX;
257 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
258 "movsd\t{$src, $dst|$dst, $src}",
259 [(store FR64:$src, addr:$dst)]>, XD, VEX;
261 // Extract and store.
262 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
265 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
266 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
269 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
271 // Move Aligned/Unaligned floating point values
272 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
273 X86MemOperand x86memop, PatFrag ld_frag,
274 string asm, Domain d,
275 bit IsReMaterializable = 1> {
276 let neverHasSideEffects = 1 in
277 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
278 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
279 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
280 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
281 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
282 [(set RC:$dst, (ld_frag addr:$src))], d>;
285 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
286 "movaps", SSEPackedSingle>, VEX;
287 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
288 "movapd", SSEPackedDouble>, OpSize, VEX;
289 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
290 "movups", SSEPackedSingle>, VEX;
291 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
292 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
294 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
295 "movaps", SSEPackedSingle>, VEX;
296 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
297 "movapd", SSEPackedDouble>, OpSize, VEX;
298 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
299 "movups", SSEPackedSingle>, VEX;
300 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
301 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
302 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
303 "movaps", SSEPackedSingle>, TB;
304 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
305 "movapd", SSEPackedDouble>, TB, OpSize;
306 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
307 "movups", SSEPackedSingle>, TB;
308 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
309 "movupd", SSEPackedDouble, 0>, TB, OpSize;
311 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
312 "movaps\t{$src, $dst|$dst, $src}",
313 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
314 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
315 "movapd\t{$src, $dst|$dst, $src}",
316 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
317 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
318 "movups\t{$src, $dst|$dst, $src}",
319 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
320 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
321 "movupd\t{$src, $dst|$dst, $src}",
322 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
323 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
324 "movaps\t{$src, $dst|$dst, $src}",
325 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
326 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
327 "movapd\t{$src, $dst|$dst, $src}",
328 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
329 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
330 "movups\t{$src, $dst|$dst, $src}",
331 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
332 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
333 "movupd\t{$src, $dst|$dst, $src}",
334 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
336 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
337 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
338 (VMOVUPSYmr addr:$dst, VR256:$src)>;
340 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
341 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
342 (VMOVUPDYmr addr:$dst, VR256:$src)>;
344 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
345 "movaps\t{$src, $dst|$dst, $src}",
346 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
347 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
348 "movapd\t{$src, $dst|$dst, $src}",
349 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
350 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
351 "movups\t{$src, $dst|$dst, $src}",
352 [(store (v4f32 VR128:$src), addr:$dst)]>;
353 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
354 "movupd\t{$src, $dst|$dst, $src}",
355 [(store (v2f64 VR128:$src), addr:$dst)]>;
357 // Intrinsic forms of MOVUPS/D load and store
358 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
359 (ins f128mem:$dst, VR128:$src),
360 "movups\t{$src, $dst|$dst, $src}",
361 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
362 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
363 (ins f128mem:$dst, VR128:$src),
364 "movupd\t{$src, $dst|$dst, $src}",
365 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
367 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
368 "movups\t{$src, $dst|$dst, $src}",
369 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
370 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
371 "movupd\t{$src, $dst|$dst, $src}",
372 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
374 // Move Low/High packed floating point values
375 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
376 PatFrag mov_frag, string base_opc,
378 def PSrm : PI<opc, MRMSrcMem,
379 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
380 !strconcat(base_opc, "s", asm_opr),
383 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
384 SSEPackedSingle>, TB;
386 def PDrm : PI<opc, MRMSrcMem,
387 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
388 !strconcat(base_opc, "d", asm_opr),
389 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
390 (scalar_to_vector (loadf64 addr:$src2)))))],
391 SSEPackedDouble>, TB, OpSize;
394 let AddedComplexity = 20 in {
395 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
396 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
397 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
398 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
400 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
401 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
402 "\t{$src2, $dst|$dst, $src2}">;
403 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
404 "\t{$src2, $dst|$dst, $src2}">;
407 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
408 "movlps\t{$src, $dst|$dst, $src}",
409 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
410 (iPTR 0))), addr:$dst)]>, VEX;
411 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
412 "movlpd\t{$src, $dst|$dst, $src}",
413 [(store (f64 (vector_extract (v2f64 VR128:$src),
414 (iPTR 0))), addr:$dst)]>, VEX;
415 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
416 "movlps\t{$src, $dst|$dst, $src}",
417 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
418 (iPTR 0))), addr:$dst)]>;
419 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
420 "movlpd\t{$src, $dst|$dst, $src}",
421 [(store (f64 (vector_extract (v2f64 VR128:$src),
422 (iPTR 0))), addr:$dst)]>;
424 // v2f64 extract element 1 is always custom lowered to unpack high to low
425 // and extract element 0 so the non-store version isn't too horrible.
426 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
427 "movhps\t{$src, $dst|$dst, $src}",
428 [(store (f64 (vector_extract
429 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
430 (undef)), (iPTR 0))), addr:$dst)]>,
432 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
433 "movhpd\t{$src, $dst|$dst, $src}",
434 [(store (f64 (vector_extract
435 (v2f64 (unpckh VR128:$src, (undef))),
436 (iPTR 0))), addr:$dst)]>,
438 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
439 "movhps\t{$src, $dst|$dst, $src}",
440 [(store (f64 (vector_extract
441 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
442 (undef)), (iPTR 0))), addr:$dst)]>;
443 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
444 "movhpd\t{$src, $dst|$dst, $src}",
445 [(store (f64 (vector_extract
446 (v2f64 (unpckh VR128:$src, (undef))),
447 (iPTR 0))), addr:$dst)]>;
449 let AddedComplexity = 20 in {
450 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
451 (ins VR128:$src1, VR128:$src2),
452 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
454 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
456 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
457 (ins VR128:$src1, VR128:$src2),
458 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
460 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
463 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
464 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
465 (ins VR128:$src1, VR128:$src2),
466 "movlhps\t{$src2, $dst|$dst, $src2}",
468 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
469 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
470 (ins VR128:$src1, VR128:$src2),
471 "movhlps\t{$src2, $dst|$dst, $src2}",
473 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
476 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
477 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
478 let AddedComplexity = 20 in {
479 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
480 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
481 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
482 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
485 //===----------------------------------------------------------------------===//
486 // SSE 1 & 2 - Conversion Instructions
487 //===----------------------------------------------------------------------===//
489 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
490 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
492 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
493 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
494 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
495 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
498 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
499 X86MemOperand x86memop, string asm> {
500 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
502 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
506 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
507 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
508 string asm, Domain d> {
509 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
510 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
511 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
512 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
515 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
516 X86MemOperand x86memop, string asm> {
517 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
518 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
519 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
520 (ins DstRC:$src1, x86memop:$src),
521 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
524 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
525 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
526 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
527 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
529 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
530 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
531 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
532 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
535 // The assembler can recognize rr 64-bit instructions by seeing a rxx
536 // register, but the same isn't true when only using memory operands,
537 // provide other assembly "l" and "q" forms to address this explicitly
538 // where appropriate to do so.
539 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
541 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
543 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
545 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
547 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
550 let Predicates = [HasAVX] in {
551 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
552 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
553 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
554 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
555 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
556 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
557 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
558 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
560 def : Pat<(f32 (sint_to_fp GR32:$src)),
561 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
562 def : Pat<(f32 (sint_to_fp GR64:$src)),
563 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
564 def : Pat<(f64 (sint_to_fp GR32:$src)),
565 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
566 def : Pat<(f64 (sint_to_fp GR64:$src)),
567 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
570 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
571 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
572 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
573 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
574 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
575 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
576 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
577 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
578 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
579 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
580 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
581 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
582 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
583 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
584 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
585 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
587 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
588 // and/or XMM operand(s).
590 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
591 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
593 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
594 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
595 [(set DstRC:$dst, (Int SrcRC:$src))]>;
596 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
597 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
598 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
601 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
602 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
603 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
604 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
606 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
607 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
608 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
609 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
610 (ins DstRC:$src1, x86memop:$src2),
612 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
613 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
614 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
617 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
618 f32mem, load, "cvtss2si">, XS, VEX;
619 defm Int_VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
620 int_x86_sse_cvtss2si64, f32mem, load, "cvtss2si">,
622 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
623 f128mem, load, "cvtsd2si">, XD, VEX;
624 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
625 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
628 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
629 // Get rid of this hack or rename the intrinsics, there are several
630 // intructions that only match with the intrinsic form, why create duplicates
631 // to let them be recognized by the assembler?
632 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
633 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
634 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
635 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
636 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
637 f32mem, load, "cvtss2si">, XS;
638 defm Int_CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
639 f32mem, load, "cvtss2si{q}">, XS, REX_W;
640 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
641 f128mem, load, "cvtsd2si{l}">, XD;
642 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
643 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
646 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
647 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
648 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
649 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
651 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
652 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
653 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
654 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
657 let Constraints = "$src1 = $dst" in {
658 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
659 int_x86_sse_cvtsi2ss, i32mem, loadi32,
661 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
662 int_x86_sse_cvtsi642ss, i64mem, loadi64,
663 "cvtsi2ss{q}">, XS, REX_W;
664 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
665 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
667 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
668 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
669 "cvtsi2sd">, XD, REX_W;
674 // Aliases for intrinsics
675 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
676 f32mem, load, "cvttss2si">, XS, VEX;
677 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
678 int_x86_sse_cvttss2si64, f32mem, load,
679 "cvttss2si">, XS, VEX, VEX_W;
680 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
681 f128mem, load, "cvttsd2si">, XD, VEX;
682 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
683 int_x86_sse2_cvttsd2si64, f128mem, load,
684 "cvttsd2si">, XD, VEX, VEX_W;
685 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
686 f32mem, load, "cvttss2si">, XS;
687 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
688 int_x86_sse_cvttss2si64, f32mem, load,
689 "cvttss2si{q}">, XS, REX_W;
690 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
691 f128mem, load, "cvttsd2si">, XD;
692 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
693 int_x86_sse2_cvttsd2si64, f128mem, load,
694 "cvttsd2si{q}">, XD, REX_W;
696 let Pattern = []<dag> in {
697 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
698 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
699 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
700 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
702 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
703 "cvtdq2ps\t{$src, $dst|$dst, $src}",
704 SSEPackedSingle>, TB, VEX;
705 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
706 "cvtdq2ps\t{$src, $dst|$dst, $src}",
707 SSEPackedSingle>, TB, VEX;
709 let Pattern = []<dag> in {
710 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
711 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
712 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
713 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
714 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
715 "cvtdq2ps\t{$src, $dst|$dst, $src}",
716 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
721 // Convert scalar double to scalar single
722 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
723 (ins FR64:$src1, FR64:$src2),
724 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
726 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
727 (ins FR64:$src1, f64mem:$src2),
728 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
729 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
730 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
733 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
734 "cvtsd2ss\t{$src, $dst|$dst, $src}",
735 [(set FR32:$dst, (fround FR64:$src))]>;
736 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
737 "cvtsd2ss\t{$src, $dst|$dst, $src}",
738 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
739 Requires<[HasSSE2, OptForSize]>;
741 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
742 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
744 let Constraints = "$src1 = $dst" in
745 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
746 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
748 // Convert scalar single to scalar double
749 // SSE2 instructions with XS prefix
750 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
751 (ins FR32:$src1, FR32:$src2),
752 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
753 []>, XS, Requires<[HasAVX]>, VEX_4V;
754 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
755 (ins FR32:$src1, f32mem:$src2),
756 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
757 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
759 let Predicates = [HasAVX] in {
760 def : Pat<(f64 (fextend FR32:$src)),
761 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
762 def : Pat<(fextend (loadf32 addr:$src)),
763 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
764 def : Pat<(extloadf32 addr:$src),
765 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
768 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
769 "cvtss2sd\t{$src, $dst|$dst, $src}",
770 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
772 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
773 "cvtss2sd\t{$src, $dst|$dst, $src}",
774 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
775 Requires<[HasSSE2, OptForSize]>;
777 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
778 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
779 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
780 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
781 VR128:$src2))]>, XS, VEX_4V,
783 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
784 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
785 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
786 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
787 (load addr:$src2)))]>, XS, VEX_4V,
789 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
790 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
791 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
792 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
793 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
796 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
797 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
798 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
799 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
800 (load addr:$src2)))]>, XS,
804 def : Pat<(extloadf32 addr:$src),
805 (CVTSS2SDrr (MOVSSrm addr:$src))>,
806 Requires<[HasSSE2, OptForSpeed]>;
808 // Convert doubleword to packed single/double fp
809 // SSE2 instructions without OpSize prefix
810 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
811 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
812 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
813 TB, VEX, Requires<[HasAVX]>;
814 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
815 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
816 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
817 (bitconvert (memopv2i64 addr:$src))))]>,
818 TB, VEX, Requires<[HasAVX]>;
819 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
820 "cvtdq2ps\t{$src, $dst|$dst, $src}",
821 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
822 TB, Requires<[HasSSE2]>;
823 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
824 "cvtdq2ps\t{$src, $dst|$dst, $src}",
825 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
826 (bitconvert (memopv2i64 addr:$src))))]>,
827 TB, Requires<[HasSSE2]>;
829 // FIXME: why the non-intrinsic version is described as SSE3?
830 // SSE2 instructions with XS prefix
831 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
832 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
833 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
834 XS, VEX, Requires<[HasAVX]>;
835 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
836 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
837 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
838 (bitconvert (memopv2i64 addr:$src))))]>,
839 XS, VEX, Requires<[HasAVX]>;
840 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
841 "cvtdq2pd\t{$src, $dst|$dst, $src}",
842 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
843 XS, Requires<[HasSSE2]>;
844 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
845 "cvtdq2pd\t{$src, $dst|$dst, $src}",
846 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
847 (bitconvert (memopv2i64 addr:$src))))]>,
848 XS, Requires<[HasSSE2]>;
851 // Convert packed single/double fp to doubleword
852 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
853 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
854 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
855 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
856 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
857 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
858 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
859 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
860 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
861 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
862 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
863 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
865 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
866 "cvtps2dq\t{$src, $dst|$dst, $src}",
867 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
869 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
871 "cvtps2dq\t{$src, $dst|$dst, $src}",
872 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
873 (memop addr:$src)))]>, VEX;
874 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
875 "cvtps2dq\t{$src, $dst|$dst, $src}",
876 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
877 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
878 "cvtps2dq\t{$src, $dst|$dst, $src}",
879 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
880 (memop addr:$src)))]>;
882 // SSE2 packed instructions with XD prefix
883 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
884 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
885 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
886 XD, VEX, Requires<[HasAVX]>;
887 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
888 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
889 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
890 (memop addr:$src)))]>,
891 XD, VEX, Requires<[HasAVX]>;
892 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
893 "cvtpd2dq\t{$src, $dst|$dst, $src}",
894 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
895 XD, Requires<[HasSSE2]>;
896 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
897 "cvtpd2dq\t{$src, $dst|$dst, $src}",
898 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
899 (memop addr:$src)))]>,
900 XD, Requires<[HasSSE2]>;
903 // Convert with truncation packed single/double fp to doubleword
904 // SSE2 packed instructions with XS prefix
905 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
906 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
907 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
908 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
909 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
910 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
911 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
912 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
913 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
914 "cvttps2dq\t{$src, $dst|$dst, $src}",
916 (int_x86_sse2_cvttps2dq VR128:$src))]>;
917 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
918 "cvttps2dq\t{$src, $dst|$dst, $src}",
920 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
922 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
923 "vcvttps2dq\t{$src, $dst|$dst, $src}",
925 (int_x86_sse2_cvttps2dq VR128:$src))]>,
926 XS, VEX, Requires<[HasAVX]>;
927 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
928 "vcvttps2dq\t{$src, $dst|$dst, $src}",
929 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
930 (memop addr:$src)))]>,
931 XS, VEX, Requires<[HasAVX]>;
933 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
934 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
935 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
936 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
938 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
939 (Int_VCVTDQ2PSrr VR128:$src)>, Requires<[HasAVX]>;
940 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
941 (VCVTTPS2DQrr VR128:$src)>, Requires<[HasAVX]>;
942 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
943 (VCVTDQ2PSYrr VR256:$src)>, Requires<[HasAVX]>;
944 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
945 (VCVTTPS2DQYrr VR256:$src)>, Requires<[HasAVX]>;
947 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
949 "cvttpd2dq\t{$src, $dst|$dst, $src}",
950 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
952 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
954 "cvttpd2dq\t{$src, $dst|$dst, $src}",
955 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
956 (memop addr:$src)))]>, VEX;
957 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
958 "cvttpd2dq\t{$src, $dst|$dst, $src}",
959 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
960 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
961 "cvttpd2dq\t{$src, $dst|$dst, $src}",
962 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
963 (memop addr:$src)))]>;
965 // The assembler can recognize rr 256-bit instructions by seeing a ymm
966 // register, but the same isn't true when using memory operands instead.
967 // Provide other assembly rr and rm forms to address this explicitly.
968 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
969 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
970 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
971 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
974 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
975 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
976 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
977 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
980 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
981 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
982 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
983 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
985 // Convert packed single to packed double
986 let Predicates = [HasAVX] in {
987 // SSE2 instructions without OpSize prefix
988 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
989 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
990 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
991 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
992 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
993 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
994 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
995 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
997 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
998 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
999 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1000 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1002 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1003 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1004 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1005 VEX, Requires<[HasAVX]>;
1006 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1007 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1008 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1009 (load addr:$src)))]>,
1010 VEX, Requires<[HasAVX]>;
1011 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1012 "cvtps2pd\t{$src, $dst|$dst, $src}",
1013 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1014 TB, Requires<[HasSSE2]>;
1015 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1016 "cvtps2pd\t{$src, $dst|$dst, $src}",
1017 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1018 (load addr:$src)))]>,
1019 TB, Requires<[HasSSE2]>;
1021 // Convert packed double to packed single
1022 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1023 // register, but the same isn't true when using memory operands instead.
1024 // Provide other assembly rr and rm forms to address this explicitly.
1025 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1026 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1027 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1028 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1031 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1032 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1033 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1034 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1037 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1038 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1039 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1040 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1041 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1042 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1043 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1044 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1047 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1048 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1049 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1050 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1052 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1053 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1054 (memop addr:$src)))]>;
1055 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1056 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1057 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1058 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1059 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1060 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1061 (memop addr:$src)))]>;
1063 // AVX 256-bit register conversion intrinsics
1064 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1065 // whenever possible to avoid declaring two versions of each one.
1066 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1067 (VCVTDQ2PSYrr VR256:$src)>;
1068 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1069 (VCVTDQ2PSYrm addr:$src)>;
1071 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1072 (VCVTPD2PSYrr VR256:$src)>;
1073 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1074 (VCVTPD2PSYrm addr:$src)>;
1076 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1077 (VCVTPS2DQYrr VR256:$src)>;
1078 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1079 (VCVTPS2DQYrm addr:$src)>;
1081 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1082 (VCVTPS2PDYrr VR128:$src)>;
1083 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1084 (VCVTPS2PDYrm addr:$src)>;
1086 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1087 (VCVTTPD2DQYrr VR256:$src)>;
1088 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1089 (VCVTTPD2DQYrm addr:$src)>;
1091 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1092 (VCVTTPS2DQYrr VR256:$src)>;
1093 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1094 (VCVTTPS2DQYrm addr:$src)>;
1096 // Match fround and fextend for 128/256-bit conversions
1097 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1098 (VCVTPD2PSYrr VR256:$src)>;
1099 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1100 (VCVTPD2PSYrm addr:$src)>;
1102 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1103 (VCVTPS2PDYrr VR128:$src)>;
1104 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1105 (VCVTPS2PDYrm addr:$src)>;
1107 //===----------------------------------------------------------------------===//
1108 // SSE 1 & 2 - Compare Instructions
1109 //===----------------------------------------------------------------------===//
1111 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1112 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1113 string asm, string asm_alt> {
1114 let isAsmParserOnly = 1 in {
1115 def rr : SIi8<0xC2, MRMSrcReg,
1116 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1119 def rm : SIi8<0xC2, MRMSrcMem,
1120 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1124 // Accept explicit immediate argument form instead of comparison code.
1125 def rr_alt : SIi8<0xC2, MRMSrcReg,
1126 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1129 def rm_alt : SIi8<0xC2, MRMSrcMem,
1130 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1134 let neverHasSideEffects = 1 in {
1135 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1136 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1137 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1139 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1140 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1141 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1145 let Constraints = "$src1 = $dst" in {
1146 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
1147 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
1148 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1149 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
1150 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
1151 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
1152 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1153 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
1154 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
1155 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
1156 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1157 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
1158 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
1159 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
1160 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1161 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
1163 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1164 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
1165 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
1166 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1167 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
1168 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
1169 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1170 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
1171 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1172 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1173 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
1174 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1175 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1178 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1179 Intrinsic Int, string asm> {
1180 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1181 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1182 [(set VR128:$dst, (Int VR128:$src1,
1183 VR128:$src, imm:$cc))]>;
1184 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1185 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1186 [(set VR128:$dst, (Int VR128:$src1,
1187 (load addr:$src), imm:$cc))]>;
1190 // Aliases to match intrinsics which expect XMM operand(s).
1191 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1192 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1194 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1195 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1197 let Constraints = "$src1 = $dst" in {
1198 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1199 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1200 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1201 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1205 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1206 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1207 ValueType vt, X86MemOperand x86memop,
1208 PatFrag ld_frag, string OpcodeStr, Domain d> {
1209 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1210 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1211 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1212 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1213 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1214 [(set EFLAGS, (OpNode (vt RC:$src1),
1215 (ld_frag addr:$src2)))], d>;
1218 let Defs = [EFLAGS] in {
1219 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1220 "ucomiss", SSEPackedSingle>, VEX;
1221 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1222 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1223 let Pattern = []<dag> in {
1224 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1225 "comiss", SSEPackedSingle>, VEX;
1226 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1227 "comisd", SSEPackedDouble>, OpSize, VEX;
1230 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1231 load, "ucomiss", SSEPackedSingle>, VEX;
1232 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1233 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1235 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1236 load, "comiss", SSEPackedSingle>, VEX;
1237 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1238 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1239 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1240 "ucomiss", SSEPackedSingle>, TB;
1241 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1242 "ucomisd", SSEPackedDouble>, TB, OpSize;
1244 let Pattern = []<dag> in {
1245 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1246 "comiss", SSEPackedSingle>, TB;
1247 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1248 "comisd", SSEPackedDouble>, TB, OpSize;
1251 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1252 load, "ucomiss", SSEPackedSingle>, TB;
1253 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1254 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1256 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1257 "comiss", SSEPackedSingle>, TB;
1258 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1259 "comisd", SSEPackedDouble>, TB, OpSize;
1260 } // Defs = [EFLAGS]
1262 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1263 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1264 Intrinsic Int, string asm, string asm_alt,
1266 let isAsmParserOnly = 1 in {
1267 def rri : PIi8<0xC2, MRMSrcReg,
1268 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1269 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1270 def rmi : PIi8<0xC2, MRMSrcMem,
1271 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1272 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1275 // Accept explicit immediate argument form instead of comparison code.
1276 def rri_alt : PIi8<0xC2, MRMSrcReg,
1277 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1279 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1280 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1284 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1285 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1286 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1287 SSEPackedSingle>, VEX_4V;
1288 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1289 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1290 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1291 SSEPackedDouble>, OpSize, VEX_4V;
1292 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1293 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1294 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1295 SSEPackedSingle>, VEX_4V;
1296 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1297 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1298 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1299 SSEPackedDouble>, OpSize, VEX_4V;
1300 let Constraints = "$src1 = $dst" in {
1301 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1302 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1303 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1304 SSEPackedSingle>, TB;
1305 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1306 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1307 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1308 SSEPackedDouble>, TB, OpSize;
1311 let Predicates = [HasSSE1] in {
1312 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1313 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1314 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1315 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1318 let Predicates = [HasSSE2] in {
1319 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1320 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1321 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1322 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1325 let Predicates = [HasAVX] in {
1326 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1327 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1328 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1329 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1330 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1331 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1332 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1333 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1335 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
1336 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
1337 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
1338 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
1339 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
1340 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
1341 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
1342 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
1345 //===----------------------------------------------------------------------===//
1346 // SSE 1 & 2 - Shuffle Instructions
1347 //===----------------------------------------------------------------------===//
1349 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1350 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1351 ValueType vt, string asm, PatFrag mem_frag,
1352 Domain d, bit IsConvertibleToThreeAddress = 0> {
1353 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1354 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1355 [(set RC:$dst, (vt (shufp:$src3
1356 RC:$src1, (mem_frag addr:$src2))))], d>;
1357 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1358 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1359 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1361 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1364 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1365 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1366 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
1367 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1368 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1369 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
1370 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1371 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1372 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1373 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1374 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1375 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1377 let Constraints = "$src1 = $dst" in {
1378 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1379 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1380 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1382 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1383 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1384 memopv2f64, SSEPackedDouble>, TB, OpSize;
1387 //===----------------------------------------------------------------------===//
1388 // SSE 1 & 2 - Unpack Instructions
1389 //===----------------------------------------------------------------------===//
1391 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1392 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1393 PatFrag mem_frag, RegisterClass RC,
1394 X86MemOperand x86memop, string asm,
1396 def rr : PI<opc, MRMSrcReg,
1397 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1399 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1400 def rm : PI<opc, MRMSrcMem,
1401 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1403 (vt (OpNode RC:$src1,
1404 (mem_frag addr:$src2))))], d>;
1407 let AddedComplexity = 10 in {
1408 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1409 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1410 SSEPackedSingle>, VEX_4V;
1411 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1412 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1413 SSEPackedDouble>, OpSize, VEX_4V;
1414 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1415 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1416 SSEPackedSingle>, VEX_4V;
1417 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1418 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1419 SSEPackedDouble>, OpSize, VEX_4V;
1421 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1422 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1423 SSEPackedSingle>, VEX_4V;
1424 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1425 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1426 SSEPackedDouble>, OpSize, VEX_4V;
1427 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1428 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1429 SSEPackedSingle>, VEX_4V;
1430 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1431 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1432 SSEPackedDouble>, OpSize, VEX_4V;
1434 let Constraints = "$src1 = $dst" in {
1435 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1436 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1437 SSEPackedSingle>, TB;
1438 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1439 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1440 SSEPackedDouble>, TB, OpSize;
1441 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1442 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1443 SSEPackedSingle>, TB;
1444 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1445 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1446 SSEPackedDouble>, TB, OpSize;
1447 } // Constraints = "$src1 = $dst"
1448 } // AddedComplexity
1450 //===----------------------------------------------------------------------===//
1451 // SSE 1 & 2 - Extract Floating-Point Sign mask
1452 //===----------------------------------------------------------------------===//
1454 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1455 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1457 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1458 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1459 [(set GR32:$dst, (Int RC:$src))], d>;
1460 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1461 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1465 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1466 "movmskps", SSEPackedSingle>, VEX;
1467 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1468 "movmskpd", SSEPackedDouble>, OpSize,
1470 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1471 "movmskps", SSEPackedSingle>, VEX;
1472 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1473 "movmskpd", SSEPackedDouble>, OpSize,
1475 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1476 SSEPackedSingle>, TB;
1477 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1478 SSEPackedDouble>, TB, OpSize;
1481 def MOVMSKPDrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1482 "movmskpd\t{$src, $dst|$dst, $src}",
1483 [(set GR32:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1484 def MOVMSKPDrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1485 "movmskpd\t{$src, $dst|$dst, $src}",
1486 [(set GR64:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1487 def MOVMSKPSrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
1488 "movmskps\t{$src, $dst|$dst, $src}",
1489 [(set GR32:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1490 def MOVMSKPSrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1491 "movmskps\t{$src, $dst|$dst, $src}",
1492 [(set GR64:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1495 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1496 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1497 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1498 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1500 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1501 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1502 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1503 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1506 //===----------------------------------------------------------------------===//
1507 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1508 //===----------------------------------------------------------------------===//
1510 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1511 // names that start with 'Fs'.
1513 // Alias instructions that map fld0 to pxor for sse.
1514 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1515 canFoldAsLoad = 1 in {
1516 // FIXME: Set encoding to pseudo!
1517 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1518 [(set FR32:$dst, fp32imm0)]>,
1519 Requires<[HasSSE1]>, TB, OpSize;
1520 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1521 [(set FR64:$dst, fpimm0)]>,
1522 Requires<[HasSSE2]>, TB, OpSize;
1523 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1524 [(set FR32:$dst, fp32imm0)]>,
1525 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1526 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1527 [(set FR64:$dst, fpimm0)]>,
1528 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1531 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1532 // bits are disregarded.
1533 let neverHasSideEffects = 1 in {
1534 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1535 "movaps\t{$src, $dst|$dst, $src}", []>;
1536 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1537 "movapd\t{$src, $dst|$dst, $src}", []>;
1540 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1541 // bits are disregarded.
1542 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1543 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1544 "movaps\t{$src, $dst|$dst, $src}",
1545 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1546 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1547 "movapd\t{$src, $dst|$dst, $src}",
1548 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1551 //===----------------------------------------------------------------------===//
1552 // SSE 1 & 2 - Logical Instructions
1553 //===----------------------------------------------------------------------===//
1555 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1557 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1559 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1560 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1562 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1563 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1565 let Constraints = "$src1 = $dst" in {
1566 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1567 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1569 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1570 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1574 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1575 let mayLoad = 0 in {
1576 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1577 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1578 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1581 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1582 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1584 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1586 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1588 let Pattern = []<dag> in {
1589 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1590 !strconcat(OpcodeStr, "ps"), f128mem,
1591 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1592 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1593 (memopv2i64 addr:$src2)))], 0>, VEX_4V;
1595 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1596 !strconcat(OpcodeStr, "pd"), f128mem,
1597 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1598 (bc_v2i64 (v2f64 VR128:$src2))))],
1599 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1600 (memopv2i64 addr:$src2)))], 0>,
1603 let Constraints = "$src1 = $dst" in {
1604 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1605 !strconcat(OpcodeStr, "ps"), f128mem,
1606 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1607 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1608 (memopv2i64 addr:$src2)))]>, TB;
1610 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1611 !strconcat(OpcodeStr, "pd"), f128mem,
1612 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1613 (bc_v2i64 (v2f64 VR128:$src2))))],
1614 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1615 (memopv2i64 addr:$src2)))]>, TB, OpSize;
1619 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1621 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
1623 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1624 !strconcat(OpcodeStr, "ps"), f256mem,
1625 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
1626 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
1627 (memopv4i64 addr:$src2)))], 0>, VEX_4V;
1629 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1630 !strconcat(OpcodeStr, "pd"), f256mem,
1631 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1632 (bc_v4i64 (v4f64 VR256:$src2))))],
1633 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1634 (memopv4i64 addr:$src2)))], 0>,
1638 // AVX 256-bit packed logical ops forms
1639 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
1640 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
1641 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
1642 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
1644 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1645 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1646 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1647 let isCommutable = 0 in
1648 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
1650 //===----------------------------------------------------------------------===//
1651 // SSE 1 & 2 - Arithmetic Instructions
1652 //===----------------------------------------------------------------------===//
1654 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1657 /// In addition, we also have a special variant of the scalar form here to
1658 /// represent the associated intrinsic operation. This form is unlike the
1659 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1660 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1662 /// These three forms can each be reg+reg or reg+mem.
1665 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1667 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1669 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1670 OpNode, FR32, f32mem, Is2Addr>, XS;
1671 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1672 OpNode, FR64, f64mem, Is2Addr>, XD;
1675 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1677 let mayLoad = 0 in {
1678 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1679 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1680 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1681 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1685 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1687 let mayLoad = 0 in {
1688 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1689 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1690 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1691 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1695 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1697 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1698 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1699 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1700 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1703 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1705 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1706 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1707 SSEPackedSingle, Is2Addr>, TB;
1709 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1710 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1711 SSEPackedDouble, Is2Addr>, TB, OpSize;
1714 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1715 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1716 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1717 SSEPackedSingle, 0>, TB;
1719 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1720 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1721 SSEPackedDouble, 0>, TB, OpSize;
1724 // Binary Arithmetic instructions
1725 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1726 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1727 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1728 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1729 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1730 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1731 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1732 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1734 let isCommutable = 0 in {
1735 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1736 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1737 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1738 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1739 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1740 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1741 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1742 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1743 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1744 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1745 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1746 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1747 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1748 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1749 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1750 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1751 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1752 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1753 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1754 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1757 let Constraints = "$src1 = $dst" in {
1758 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1759 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1760 basic_sse12_fp_binop_s_int<0x58, "add">;
1761 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1762 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1763 basic_sse12_fp_binop_s_int<0x59, "mul">;
1765 let isCommutable = 0 in {
1766 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1767 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1768 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1769 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1770 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1771 basic_sse12_fp_binop_s_int<0x5E, "div">;
1772 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1773 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1774 basic_sse12_fp_binop_s_int<0x5F, "max">,
1775 basic_sse12_fp_binop_p_int<0x5F, "max">;
1776 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1777 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1778 basic_sse12_fp_binop_s_int<0x5D, "min">,
1779 basic_sse12_fp_binop_p_int<0x5D, "min">;
1784 /// In addition, we also have a special variant of the scalar form here to
1785 /// represent the associated intrinsic operation. This form is unlike the
1786 /// plain scalar form, in that it takes an entire vector (instead of a
1787 /// scalar) and leaves the top elements undefined.
1789 /// And, we have a special variant form for a full-vector intrinsic form.
1791 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1792 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1793 SDNode OpNode, Intrinsic F32Int> {
1794 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1795 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1796 [(set FR32:$dst, (OpNode FR32:$src))]>;
1797 // For scalar unary operations, fold a load into the operation
1798 // only in OptForSize mode. It eliminates an instruction, but it also
1799 // eliminates a whole-register clobber (the load), so it introduces a
1800 // partial register update condition.
1801 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1802 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1803 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1804 Requires<[HasSSE1, OptForSize]>;
1805 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1806 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1807 [(set VR128:$dst, (F32Int VR128:$src))]>;
1808 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1809 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1810 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1813 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1814 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1815 SDNode OpNode, Intrinsic F32Int> {
1816 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1817 !strconcat(OpcodeStr,
1818 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1819 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1820 !strconcat(OpcodeStr,
1821 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1822 []>, XS, Requires<[HasAVX, OptForSize]>;
1823 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1824 !strconcat(OpcodeStr,
1825 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1826 [(set VR128:$dst, (F32Int VR128:$src))]>;
1827 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1828 !strconcat(OpcodeStr,
1829 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1830 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1833 /// sse1_fp_unop_p - SSE1 unops in packed form.
1834 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1835 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1836 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1837 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1838 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1839 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1840 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1843 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1844 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1845 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1846 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1847 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1848 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1849 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1850 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1853 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1854 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1855 Intrinsic V4F32Int> {
1856 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1857 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1858 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1859 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1860 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1861 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1864 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1865 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1866 Intrinsic V4F32Int> {
1867 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1868 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1869 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1870 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1871 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1872 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1875 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1876 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1877 SDNode OpNode, Intrinsic F64Int> {
1878 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1879 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1880 [(set FR64:$dst, (OpNode FR64:$src))]>;
1881 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1882 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1883 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1884 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1885 Requires<[HasSSE2, OptForSize]>;
1886 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1887 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1888 [(set VR128:$dst, (F64Int VR128:$src))]>;
1889 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1890 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1891 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1894 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1895 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1896 SDNode OpNode, Intrinsic F64Int> {
1897 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1898 !strconcat(OpcodeStr,
1899 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1900 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1901 (ins FR64:$src1, f64mem:$src2),
1902 !strconcat(OpcodeStr,
1903 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1904 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1905 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1906 [(set VR128:$dst, (F64Int VR128:$src))]>;
1907 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1908 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1909 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1912 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1913 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1915 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1916 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1917 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1918 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1919 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1920 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1923 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1924 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1925 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1926 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1927 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1928 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1929 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1930 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1933 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1934 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1935 Intrinsic V2F64Int> {
1936 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1937 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1938 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1939 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1940 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1941 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1944 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
1945 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1946 Intrinsic V2F64Int> {
1947 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1948 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1949 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1950 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1951 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1952 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1955 let Predicates = [HasAVX] in {
1957 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
1958 sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1961 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1962 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1963 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1964 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1965 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
1966 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
1967 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
1968 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
1971 // Reciprocal approximations. Note that these typically require refinement
1972 // in order to obtain suitable precision.
1973 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
1974 int_x86_sse_rsqrt_ss>, VEX_4V;
1975 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
1976 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
1977 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
1978 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
1980 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
1982 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
1983 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
1984 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
1985 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
1988 def : Pat<(f32 (fsqrt FR32:$src)),
1989 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
1990 def : Pat<(f64 (fsqrt FR64:$src)),
1991 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
1992 def : Pat<(f64 (fsqrt (load addr:$src))),
1993 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
1994 Requires<[HasAVX, OptForSize]>;
1995 def : Pat<(f32 (fsqrt (load addr:$src))),
1996 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
1997 Requires<[HasAVX, OptForSize]>;
2000 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
2001 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
2002 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
2003 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
2004 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
2005 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
2007 // Reciprocal approximations. Note that these typically require refinement
2008 // in order to obtain suitable precision.
2009 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
2010 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
2011 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
2012 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2013 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
2014 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
2016 // There is no f64 version of the reciprocal approximation instructions.
2018 //===----------------------------------------------------------------------===//
2019 // SSE 1 & 2 - Non-temporal stores
2020 //===----------------------------------------------------------------------===//
2022 let AddedComplexity = 400 in { // Prefer non-temporal versions
2023 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
2024 (ins f128mem:$dst, VR128:$src),
2025 "movntps\t{$src, $dst|$dst, $src}",
2026 [(alignednontemporalstore (v4f32 VR128:$src),
2028 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
2029 (ins f128mem:$dst, VR128:$src),
2030 "movntpd\t{$src, $dst|$dst, $src}",
2031 [(alignednontemporalstore (v2f64 VR128:$src),
2033 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
2034 (ins f128mem:$dst, VR128:$src),
2035 "movntdq\t{$src, $dst|$dst, $src}",
2036 [(alignednontemporalstore (v2f64 VR128:$src),
2039 let ExeDomain = SSEPackedInt in
2040 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
2041 (ins f128mem:$dst, VR128:$src),
2042 "movntdq\t{$src, $dst|$dst, $src}",
2043 [(alignednontemporalstore (v4f32 VR128:$src),
2046 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2047 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
2049 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
2050 (ins f256mem:$dst, VR256:$src),
2051 "movntps\t{$src, $dst|$dst, $src}",
2052 [(alignednontemporalstore (v8f32 VR256:$src),
2054 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
2055 (ins f256mem:$dst, VR256:$src),
2056 "movntpd\t{$src, $dst|$dst, $src}",
2057 [(alignednontemporalstore (v4f64 VR256:$src),
2059 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
2060 (ins f256mem:$dst, VR256:$src),
2061 "movntdq\t{$src, $dst|$dst, $src}",
2062 [(alignednontemporalstore (v4f64 VR256:$src),
2064 let ExeDomain = SSEPackedInt in
2065 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
2066 (ins f256mem:$dst, VR256:$src),
2067 "movntdq\t{$src, $dst|$dst, $src}",
2068 [(alignednontemporalstore (v8f32 VR256:$src),
2072 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
2073 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
2074 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
2075 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
2076 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
2077 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
2079 let AddedComplexity = 400 in { // Prefer non-temporal versions
2080 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2081 "movntps\t{$src, $dst|$dst, $src}",
2082 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2083 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2084 "movntpd\t{$src, $dst|$dst, $src}",
2085 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2087 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2088 "movntdq\t{$src, $dst|$dst, $src}",
2089 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2091 let ExeDomain = SSEPackedInt in
2092 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2093 "movntdq\t{$src, $dst|$dst, $src}",
2094 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2096 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2097 (MOVNTDQmr addr:$dst, VR128:$src)>;
2099 // There is no AVX form for instructions below this point
2100 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2101 "movnti{l}\t{$src, $dst|$dst, $src}",
2102 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2103 TB, Requires<[HasSSE2]>;
2104 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2105 "movnti{q}\t{$src, $dst|$dst, $src}",
2106 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2107 TB, Requires<[HasSSE2]>;
2110 //===----------------------------------------------------------------------===//
2111 // SSE 1 & 2 - Misc Instructions (No AVX form)
2112 //===----------------------------------------------------------------------===//
2114 // Prefetch intrinsic.
2115 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2116 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
2117 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2118 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
2119 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2120 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
2121 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2122 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
2124 // Load, store, and memory fence
2125 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2126 TB, Requires<[HasSSE1]>;
2127 def : Pat<(X86SFence), (SFENCE)>;
2129 // Alias instructions that map zero vector to pxor / xorp* for sse.
2130 // We set canFoldAsLoad because this can be converted to a constant-pool
2131 // load of an all-zeros value if folding it would be beneficial.
2132 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2133 // JIT implementation, it does not expand the instructions below like
2134 // X86MCInstLower does.
2135 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2136 isCodeGenOnly = 1 in {
2137 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2138 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2139 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2140 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2141 let ExeDomain = SSEPackedInt in
2142 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2143 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2146 // The same as done above but for AVX. The 128-bit versions are the
2147 // same, but re-encoded. The 256-bit does not support PI version, and
2148 // doesn't need it because on sandy bridge the register is set to zero
2149 // at the rename stage without using any execution unit, so SET0PSY
2150 // and SET0PDY can be used for vector int instructions without penalty
2151 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2152 // JIT implementatioan, it does not expand the instructions below like
2153 // X86MCInstLower does.
2154 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2155 isCodeGenOnly = 1, Predicates = [HasAVX] in {
2156 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2157 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
2158 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2159 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
2160 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2161 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
2162 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2163 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
2164 let ExeDomain = SSEPackedInt in
2165 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2166 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2169 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2170 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2171 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2173 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2174 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2176 // AVX has no support for 256-bit integer instructions, but since the 128-bit
2177 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
2178 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
2179 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
2180 (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
2182 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
2183 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
2184 (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
2186 //===----------------------------------------------------------------------===//
2187 // SSE 1 & 2 - Load/Store XCSR register
2188 //===----------------------------------------------------------------------===//
2190 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2191 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2192 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2193 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2195 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2196 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2197 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2198 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2200 //===---------------------------------------------------------------------===//
2201 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2202 //===---------------------------------------------------------------------===//
2204 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2206 let neverHasSideEffects = 1 in {
2207 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2208 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2209 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2210 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2212 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2213 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2214 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2215 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2217 let canFoldAsLoad = 1, mayLoad = 1 in {
2218 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2219 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2220 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2221 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2222 let Predicates = [HasAVX] in {
2223 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2224 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2225 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2226 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2230 let mayStore = 1 in {
2231 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2232 (ins i128mem:$dst, VR128:$src),
2233 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2234 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2235 (ins i256mem:$dst, VR256:$src),
2236 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2237 let Predicates = [HasAVX] in {
2238 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2239 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2240 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2241 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2245 let neverHasSideEffects = 1 in
2246 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2247 "movdqa\t{$src, $dst|$dst, $src}", []>;
2249 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2250 "movdqu\t{$src, $dst|$dst, $src}",
2251 []>, XS, Requires<[HasSSE2]>;
2253 let canFoldAsLoad = 1, mayLoad = 1 in {
2254 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2255 "movdqa\t{$src, $dst|$dst, $src}",
2256 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2257 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2258 "movdqu\t{$src, $dst|$dst, $src}",
2259 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2260 XS, Requires<[HasSSE2]>;
2263 let mayStore = 1 in {
2264 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2265 "movdqa\t{$src, $dst|$dst, $src}",
2266 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2267 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2268 "movdqu\t{$src, $dst|$dst, $src}",
2269 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2270 XS, Requires<[HasSSE2]>;
2273 // Intrinsic forms of MOVDQU load and store
2274 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2275 "vmovdqu\t{$src, $dst|$dst, $src}",
2276 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2277 XS, VEX, Requires<[HasAVX]>;
2279 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2280 "movdqu\t{$src, $dst|$dst, $src}",
2281 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2282 XS, Requires<[HasSSE2]>;
2284 } // ExeDomain = SSEPackedInt
2286 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2287 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2288 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2290 //===---------------------------------------------------------------------===//
2291 // SSE2 - Packed Integer Arithmetic Instructions
2292 //===---------------------------------------------------------------------===//
2294 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2296 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2297 bit IsCommutable = 0, bit Is2Addr = 1> {
2298 let isCommutable = IsCommutable in
2299 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2300 (ins VR128:$src1, VR128:$src2),
2302 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2303 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2304 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2305 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2306 (ins VR128:$src1, i128mem:$src2),
2308 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2309 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2310 [(set VR128:$dst, (IntId VR128:$src1,
2311 (bitconvert (memopv2i64 addr:$src2))))]>;
2314 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2315 string OpcodeStr, Intrinsic IntId,
2316 Intrinsic IntId2, bit Is2Addr = 1> {
2317 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2318 (ins VR128:$src1, VR128:$src2),
2320 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2321 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2322 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2323 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2324 (ins VR128:$src1, i128mem:$src2),
2326 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2327 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2328 [(set VR128:$dst, (IntId VR128:$src1,
2329 (bitconvert (memopv2i64 addr:$src2))))]>;
2330 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2331 (ins VR128:$src1, i32i8imm:$src2),
2333 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2334 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2335 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2338 /// PDI_binop_rm - Simple SSE2 binary operator.
2339 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2340 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2341 let isCommutable = IsCommutable in
2342 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2343 (ins VR128:$src1, VR128:$src2),
2345 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2346 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2347 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2348 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2349 (ins VR128:$src1, i128mem:$src2),
2351 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2352 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2353 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2354 (bitconvert (memopv2i64 addr:$src2)))))]>;
2357 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2359 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2360 /// to collapse (bitconvert VT to VT) into its operand.
2362 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2363 bit IsCommutable = 0, bit Is2Addr = 1> {
2364 let isCommutable = IsCommutable in
2365 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2366 (ins VR128:$src1, VR128:$src2),
2368 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2369 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2370 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2371 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2372 (ins VR128:$src1, i128mem:$src2),
2374 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2375 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2376 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2379 } // ExeDomain = SSEPackedInt
2381 // 128-bit Integer Arithmetic
2383 let Predicates = [HasAVX] in {
2384 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2385 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2386 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2387 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2388 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2389 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2390 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2391 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2392 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2395 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2397 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2399 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2401 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2403 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2405 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2407 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2409 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2411 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2413 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2415 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2417 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2419 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2421 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2423 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2425 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2427 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2429 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2431 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2435 let Constraints = "$src1 = $dst" in {
2436 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2437 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2438 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2439 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2440 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2441 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2442 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2443 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2444 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2447 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2448 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2449 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2450 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2451 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2452 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2453 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2454 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2455 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2456 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2457 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2458 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2459 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2460 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2461 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2462 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2463 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2464 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2465 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2467 } // Constraints = "$src1 = $dst"
2469 //===---------------------------------------------------------------------===//
2470 // SSE2 - Packed Integer Logical Instructions
2471 //===---------------------------------------------------------------------===//
2473 let Predicates = [HasAVX] in {
2474 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2475 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2477 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2478 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2480 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2481 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2484 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2485 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2487 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2488 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2490 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2491 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2494 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2495 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2497 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2498 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2501 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2502 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2503 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2505 let ExeDomain = SSEPackedInt in {
2506 let neverHasSideEffects = 1 in {
2507 // 128-bit logical shifts.
2508 def VPSLLDQri : PDIi8<0x73, MRM7r,
2509 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2510 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2512 def VPSRLDQri : PDIi8<0x73, MRM3r,
2513 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2514 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2516 // PSRADQri doesn't exist in SSE[1-3].
2518 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2519 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2520 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2521 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2522 VR128:$src2)))]>, VEX_4V;
2524 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2525 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2526 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2527 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2528 (memopv2i64 addr:$src2))))]>,
2533 let Constraints = "$src1 = $dst" in {
2534 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2535 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2536 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2537 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2538 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2539 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2541 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2542 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2543 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2544 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2545 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2546 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2548 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2549 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2550 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2551 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2553 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2554 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2555 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2557 let ExeDomain = SSEPackedInt in {
2558 let neverHasSideEffects = 1 in {
2559 // 128-bit logical shifts.
2560 def PSLLDQri : PDIi8<0x73, MRM7r,
2561 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2562 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2563 def PSRLDQri : PDIi8<0x73, MRM3r,
2564 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2565 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2566 // PSRADQri doesn't exist in SSE[1-3].
2568 def PANDNrr : PDI<0xDF, MRMSrcReg,
2569 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2570 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2572 def PANDNrm : PDI<0xDF, MRMSrcMem,
2573 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2574 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2576 } // Constraints = "$src1 = $dst"
2578 let Predicates = [HasAVX] in {
2579 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2580 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2581 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2582 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2583 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2584 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2585 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2586 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2587 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2588 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2590 // Shift up / down and insert zero's.
2591 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2592 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2593 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2594 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2597 let Predicates = [HasSSE2] in {
2598 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2599 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2600 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2601 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2602 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2603 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2604 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2605 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2606 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2607 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2609 // Shift up / down and insert zero's.
2610 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2611 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2612 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2613 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2616 //===---------------------------------------------------------------------===//
2617 // SSE2 - Packed Integer Comparison Instructions
2618 //===---------------------------------------------------------------------===//
2620 let Predicates = [HasAVX] in {
2621 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2623 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2625 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2627 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2629 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2631 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2635 let Constraints = "$src1 = $dst" in {
2636 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2637 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2638 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2639 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2640 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2641 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2642 } // Constraints = "$src1 = $dst"
2644 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2645 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2646 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2647 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2648 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2649 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2650 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2651 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2652 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2653 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2654 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2655 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2657 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2658 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2659 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2660 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2661 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2662 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2663 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2664 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2665 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2666 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2667 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2668 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2670 //===---------------------------------------------------------------------===//
2671 // SSE2 - Packed Integer Pack Instructions
2672 //===---------------------------------------------------------------------===//
2674 let Predicates = [HasAVX] in {
2675 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2677 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2679 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2683 let Constraints = "$src1 = $dst" in {
2684 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2685 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2686 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2687 } // Constraints = "$src1 = $dst"
2689 //===---------------------------------------------------------------------===//
2690 // SSE2 - Packed Integer Shuffle Instructions
2691 //===---------------------------------------------------------------------===//
2693 let ExeDomain = SSEPackedInt in {
2694 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2696 def ri : Ii8<0x70, MRMSrcReg,
2697 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2698 !strconcat(OpcodeStr,
2699 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2700 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2702 def mi : Ii8<0x70, MRMSrcMem,
2703 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2704 !strconcat(OpcodeStr,
2705 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2706 [(set VR128:$dst, (vt (pshuf_frag:$src2
2707 (bc_frag (memopv2i64 addr:$src1)),
2710 } // ExeDomain = SSEPackedInt
2712 let Predicates = [HasAVX] in {
2713 let AddedComplexity = 5 in
2714 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2717 // SSE2 with ImmT == Imm8 and XS prefix.
2718 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2721 // SSE2 with ImmT == Imm8 and XD prefix.
2722 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2726 let Predicates = [HasSSE2] in {
2727 let AddedComplexity = 5 in
2728 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2730 // SSE2 with ImmT == Imm8 and XS prefix.
2731 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2733 // SSE2 with ImmT == Imm8 and XD prefix.
2734 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2737 //===---------------------------------------------------------------------===//
2738 // SSE2 - Packed Integer Unpack Instructions
2739 //===---------------------------------------------------------------------===//
2741 let ExeDomain = SSEPackedInt in {
2742 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2743 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
2744 def rr : PDI<opc, MRMSrcReg,
2745 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2747 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2748 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2749 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
2750 def rm : PDI<opc, MRMSrcMem,
2751 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2753 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2754 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2755 [(set VR128:$dst, (OpNode VR128:$src1,
2756 (bc_frag (memopv2i64
2760 let Predicates = [HasAVX] in {
2761 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
2762 bc_v16i8, 0>, VEX_4V;
2763 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
2764 bc_v8i16, 0>, VEX_4V;
2765 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
2766 bc_v4i32, 0>, VEX_4V;
2768 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2769 /// knew to collapse (bitconvert VT to VT) into its operand.
2770 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2771 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2772 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2773 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
2774 VR128:$src2)))]>, VEX_4V;
2775 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2776 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2777 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2778 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
2779 (memopv2i64 addr:$src2))))]>, VEX_4V;
2781 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
2782 bc_v16i8, 0>, VEX_4V;
2783 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
2784 bc_v8i16, 0>, VEX_4V;
2785 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
2786 bc_v4i32, 0>, VEX_4V;
2788 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2789 /// knew to collapse (bitconvert VT to VT) into its operand.
2790 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2791 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2792 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2793 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
2794 VR128:$src2)))]>, VEX_4V;
2795 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2796 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2797 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2798 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
2799 (memopv2i64 addr:$src2))))]>, VEX_4V;
2802 let Constraints = "$src1 = $dst" in {
2803 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
2804 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
2805 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
2807 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2808 /// knew to collapse (bitconvert VT to VT) into its operand.
2809 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2810 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2811 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2813 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
2814 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2815 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2816 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2818 (v2i64 (X86Punpcklqdq VR128:$src1,
2819 (memopv2i64 addr:$src2))))]>;
2821 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
2822 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
2823 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
2825 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2826 /// knew to collapse (bitconvert VT to VT) into its operand.
2827 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2828 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2829 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2831 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
2832 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2833 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2834 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2836 (v2i64 (X86Punpckhqdq VR128:$src1,
2837 (memopv2i64 addr:$src2))))]>;
2840 } // ExeDomain = SSEPackedInt
2842 //===---------------------------------------------------------------------===//
2843 // SSE2 - Packed Integer Extract and Insert
2844 //===---------------------------------------------------------------------===//
2846 let ExeDomain = SSEPackedInt in {
2847 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2848 def rri : Ii8<0xC4, MRMSrcReg,
2849 (outs VR128:$dst), (ins VR128:$src1,
2850 GR32:$src2, i32i8imm:$src3),
2852 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2853 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2855 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2856 def rmi : Ii8<0xC4, MRMSrcMem,
2857 (outs VR128:$dst), (ins VR128:$src1,
2858 i16mem:$src2, i32i8imm:$src3),
2860 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2861 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2863 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2868 let Predicates = [HasAVX] in
2869 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2870 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2871 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2872 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2873 imm:$src2))]>, OpSize, VEX;
2874 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2875 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2876 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2877 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2881 let Predicates = [HasAVX] in {
2882 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2883 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2884 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2885 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2886 []>, OpSize, VEX_4V;
2889 let Constraints = "$src1 = $dst" in
2890 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
2892 } // ExeDomain = SSEPackedInt
2894 //===---------------------------------------------------------------------===//
2895 // SSE2 - Packed Mask Creation
2896 //===---------------------------------------------------------------------===//
2898 let ExeDomain = SSEPackedInt in {
2900 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2901 "pmovmskb\t{$src, $dst|$dst, $src}",
2902 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2903 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2904 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2905 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2906 "pmovmskb\t{$src, $dst|$dst, $src}",
2907 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2909 } // ExeDomain = SSEPackedInt
2911 //===---------------------------------------------------------------------===//
2912 // SSE2 - Conditional Store
2913 //===---------------------------------------------------------------------===//
2915 let ExeDomain = SSEPackedInt in {
2918 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2919 (ins VR128:$src, VR128:$mask),
2920 "maskmovdqu\t{$mask, $src|$src, $mask}",
2921 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2923 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2924 (ins VR128:$src, VR128:$mask),
2925 "maskmovdqu\t{$mask, $src|$src, $mask}",
2926 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2929 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2930 "maskmovdqu\t{$mask, $src|$src, $mask}",
2931 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2933 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2934 "maskmovdqu\t{$mask, $src|$src, $mask}",
2935 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2937 } // ExeDomain = SSEPackedInt
2939 //===---------------------------------------------------------------------===//
2940 // SSE2 - Move Doubleword
2941 //===---------------------------------------------------------------------===//
2943 //===---------------------------------------------------------------------===//
2944 // Move Int Doubleword to Packed Double Int
2946 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2947 "movd\t{$src, $dst|$dst, $src}",
2949 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2950 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2951 "movd\t{$src, $dst|$dst, $src}",
2953 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2955 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2956 "mov{d|q}\t{$src, $dst|$dst, $src}",
2958 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
2959 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2960 "mov{d|q}\t{$src, $dst|$dst, $src}",
2961 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
2963 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2964 "movd\t{$src, $dst|$dst, $src}",
2966 (v4i32 (scalar_to_vector GR32:$src)))]>;
2967 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2968 "movd\t{$src, $dst|$dst, $src}",
2970 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2971 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2972 "mov{d|q}\t{$src, $dst|$dst, $src}",
2974 (v2i64 (scalar_to_vector GR64:$src)))]>;
2975 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2976 "mov{d|q}\t{$src, $dst|$dst, $src}",
2977 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2979 //===---------------------------------------------------------------------===//
2980 // Move Int Doubleword to Single Scalar
2982 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2983 "movd\t{$src, $dst|$dst, $src}",
2984 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2986 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2987 "movd\t{$src, $dst|$dst, $src}",
2988 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2990 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2991 "movd\t{$src, $dst|$dst, $src}",
2992 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2994 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2995 "movd\t{$src, $dst|$dst, $src}",
2996 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2998 //===---------------------------------------------------------------------===//
2999 // Move Packed Doubleword Int to Packed Double Int
3001 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3002 "movd\t{$src, $dst|$dst, $src}",
3003 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3005 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
3006 (ins i32mem:$dst, VR128:$src),
3007 "movd\t{$src, $dst|$dst, $src}",
3008 [(store (i32 (vector_extract (v4i32 VR128:$src),
3009 (iPTR 0))), addr:$dst)]>, VEX;
3010 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3011 "movd\t{$src, $dst|$dst, $src}",
3012 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3014 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
3015 "movd\t{$src, $dst|$dst, $src}",
3016 [(store (i32 (vector_extract (v4i32 VR128:$src),
3017 (iPTR 0))), addr:$dst)]>;
3019 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3020 "mov{d|q}\t{$src, $dst|$dst, $src}",
3021 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
3023 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
3024 "movq\t{$src, $dst|$dst, $src}",
3025 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
3027 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
3028 "mov{d|q}\t{$src, $dst|$dst, $src}",
3029 [(set GR64:$dst, (bitconvert FR64:$src))]>;
3030 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
3031 "movq\t{$src, $dst|$dst, $src}",
3032 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
3034 //===---------------------------------------------------------------------===//
3035 // Move Scalar Single to Double Int
3037 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3038 "movd\t{$src, $dst|$dst, $src}",
3039 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
3040 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3041 "movd\t{$src, $dst|$dst, $src}",
3042 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
3043 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3044 "movd\t{$src, $dst|$dst, $src}",
3045 [(set GR32:$dst, (bitconvert FR32:$src))]>;
3046 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3047 "movd\t{$src, $dst|$dst, $src}",
3048 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
3050 //===---------------------------------------------------------------------===//
3051 // Patterns and instructions to describe movd/movq to XMM register zero-extends
3053 let AddedComplexity = 15 in {
3054 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3055 "movd\t{$src, $dst|$dst, $src}",
3056 [(set VR128:$dst, (v4i32 (X86vzmovl
3057 (v4i32 (scalar_to_vector GR32:$src)))))]>,
3059 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3060 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3061 [(set VR128:$dst, (v2i64 (X86vzmovl
3062 (v2i64 (scalar_to_vector GR64:$src)))))]>,
3065 let AddedComplexity = 15 in {
3066 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3067 "movd\t{$src, $dst|$dst, $src}",
3068 [(set VR128:$dst, (v4i32 (X86vzmovl
3069 (v4i32 (scalar_to_vector GR32:$src)))))]>;
3070 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3071 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3072 [(set VR128:$dst, (v2i64 (X86vzmovl
3073 (v2i64 (scalar_to_vector GR64:$src)))))]>;
3076 let AddedComplexity = 20 in {
3077 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3078 "movd\t{$src, $dst|$dst, $src}",
3080 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3081 (loadi32 addr:$src))))))]>,
3083 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3084 "movd\t{$src, $dst|$dst, $src}",
3086 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3087 (loadi32 addr:$src))))))]>;
3089 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
3090 (MOVZDI2PDIrm addr:$src)>;
3091 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3092 (MOVZDI2PDIrm addr:$src)>;
3093 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3094 (MOVZDI2PDIrm addr:$src)>;
3097 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3098 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3099 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3100 (v4i32 (scalar_to_vector GR32:$src)), (i32 0)))),
3101 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
3102 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3103 (v2i64 (scalar_to_vector GR64:$src)), (i32 0)))),
3104 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
3106 // These are the correct encodings of the instructions so that we know how to
3107 // read correct assembly, even though we continue to emit the wrong ones for
3108 // compatibility with Darwin's buggy assembler.
3109 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3110 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
3111 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3112 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
3113 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3114 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
3115 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3116 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
3117 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3118 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3119 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3120 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3122 //===---------------------------------------------------------------------===//
3123 // SSE2 - Move Quadword
3124 //===---------------------------------------------------------------------===//
3126 //===---------------------------------------------------------------------===//
3127 // Move Quadword Int to Packed Quadword Int
3129 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3130 "vmovq\t{$src, $dst|$dst, $src}",
3132 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3133 VEX, Requires<[HasAVX]>;
3134 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3135 "movq\t{$src, $dst|$dst, $src}",
3137 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3138 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3140 //===---------------------------------------------------------------------===//
3141 // Move Packed Quadword Int to Quadword Int
3143 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3144 "movq\t{$src, $dst|$dst, $src}",
3145 [(store (i64 (vector_extract (v2i64 VR128:$src),
3146 (iPTR 0))), addr:$dst)]>, VEX;
3147 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3148 "movq\t{$src, $dst|$dst, $src}",
3149 [(store (i64 (vector_extract (v2i64 VR128:$src),
3150 (iPTR 0))), addr:$dst)]>;
3152 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3153 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3155 //===---------------------------------------------------------------------===//
3156 // Store / copy lower 64-bits of a XMM register.
3158 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3159 "movq\t{$src, $dst|$dst, $src}",
3160 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3161 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3162 "movq\t{$src, $dst|$dst, $src}",
3163 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3165 let AddedComplexity = 20 in
3166 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3167 "vmovq\t{$src, $dst|$dst, $src}",
3169 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3170 (loadi64 addr:$src))))))]>,
3171 XS, VEX, Requires<[HasAVX]>;
3173 let AddedComplexity = 20 in {
3174 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3175 "movq\t{$src, $dst|$dst, $src}",
3177 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3178 (loadi64 addr:$src))))))]>,
3179 XS, Requires<[HasSSE2]>;
3181 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3182 (MOVZQI2PQIrm addr:$src)>;
3183 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3184 (MOVZQI2PQIrm addr:$src)>;
3185 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3188 //===---------------------------------------------------------------------===//
3189 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3190 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3192 let AddedComplexity = 15 in
3193 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3194 "vmovq\t{$src, $dst|$dst, $src}",
3195 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3196 XS, VEX, Requires<[HasAVX]>;
3197 let AddedComplexity = 15 in
3198 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3199 "movq\t{$src, $dst|$dst, $src}",
3200 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3201 XS, Requires<[HasSSE2]>;
3203 let AddedComplexity = 20 in
3204 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3205 "vmovq\t{$src, $dst|$dst, $src}",
3206 [(set VR128:$dst, (v2i64 (X86vzmovl
3207 (loadv2i64 addr:$src))))]>,
3208 XS, VEX, Requires<[HasAVX]>;
3209 let AddedComplexity = 20 in {
3210 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3211 "movq\t{$src, $dst|$dst, $src}",
3212 [(set VR128:$dst, (v2i64 (X86vzmovl
3213 (loadv2i64 addr:$src))))]>,
3214 XS, Requires<[HasSSE2]>;
3216 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3217 (MOVZPQILo2PQIrm addr:$src)>;
3220 // Instructions to match in the assembler
3221 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3222 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3223 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3224 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3225 // Recognize "movd" with GR64 destination, but encode as a "movq"
3226 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3227 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3229 // Instructions for the disassembler
3230 // xr = XMM register
3233 let Predicates = [HasAVX] in
3234 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3235 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3236 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3237 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3239 //===---------------------------------------------------------------------===//
3240 // SSE2 - Misc Instructions
3241 //===---------------------------------------------------------------------===//
3244 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3245 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3246 TB, Requires<[HasSSE2]>;
3248 // Load, store, and memory fence
3249 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3250 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3251 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3252 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3253 def : Pat<(X86LFence), (LFENCE)>;
3254 def : Pat<(X86MFence), (MFENCE)>;
3257 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3258 // was introduced with SSE2, it's backward compatible.
3259 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3261 // Alias instructions that map zero vector to pxor / xorp* for sse.
3262 // We set canFoldAsLoad because this can be converted to a constant-pool
3263 // load of an all-ones value if folding it would be beneficial.
3264 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
3265 // JIT implementation, it does not expand the instructions below like
3266 // X86MCInstLower does.
3267 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3268 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3269 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3270 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3271 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3272 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
3273 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3274 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
3276 //===---------------------------------------------------------------------===//
3277 // SSE3 - Conversion Instructions
3278 //===---------------------------------------------------------------------===//
3280 // Convert Packed Double FP to Packed DW Integers
3281 let Predicates = [HasAVX] in {
3282 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3283 // register, but the same isn't true when using memory operands instead.
3284 // Provide other assembly rr and rm forms to address this explicitly.
3285 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3286 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3287 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3288 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3291 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3292 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3293 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3294 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3297 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3298 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3299 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3300 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3303 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3304 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3305 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3306 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3308 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
3309 (VCVTPD2DQYrr VR256:$src)>;
3310 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
3311 (VCVTPD2DQYrm addr:$src)>;
3313 // Convert Packed DW Integers to Packed Double FP
3314 let Predicates = [HasAVX] in {
3315 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3316 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3317 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3318 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3319 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3320 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3321 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3322 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3325 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3326 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3327 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3328 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3330 // AVX 256-bit register conversion intrinsics
3331 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3332 (VCVTDQ2PDYrr VR128:$src)>;
3333 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3334 (VCVTDQ2PDYrm addr:$src)>;
3336 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3337 (VCVTPD2DQYrr VR256:$src)>;
3338 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3339 (VCVTPD2DQYrm addr:$src)>;
3341 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
3342 (VCVTDQ2PDYrr VR128:$src)>;
3343 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
3344 (VCVTDQ2PDYrm addr:$src)>;
3346 //===---------------------------------------------------------------------===//
3347 // SSE3 - Move Instructions
3348 //===---------------------------------------------------------------------===//
3350 //===---------------------------------------------------------------------===//
3351 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3353 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3354 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3355 X86MemOperand x86memop> {
3356 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3357 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3358 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
3359 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3360 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3361 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
3364 let Predicates = [HasAVX] in {
3365 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3366 v4f32, VR128, memopv4f32, f128mem>, VEX;
3367 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3368 v4f32, VR128, memopv4f32, f128mem>, VEX;
3369 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3370 v8f32, VR256, memopv8f32, f256mem>, VEX;
3371 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3372 v8f32, VR256, memopv8f32, f256mem>, VEX;
3374 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
3375 memopv4f32, f128mem>;
3376 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
3377 memopv4f32, f128mem>;
3379 let Predicates = [HasSSE3] in {
3380 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3381 (MOVSHDUPrr VR128:$src)>;
3382 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3383 (MOVSHDUPrm addr:$src)>;
3384 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3385 (MOVSLDUPrr VR128:$src)>;
3386 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3387 (MOVSLDUPrm addr:$src)>;
3390 let Predicates = [HasAVX] in {
3391 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3392 (VMOVSHDUPrr VR128:$src)>;
3393 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3394 (VMOVSHDUPrm addr:$src)>;
3395 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3396 (VMOVSLDUPrr VR128:$src)>;
3397 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3398 (VMOVSLDUPrm addr:$src)>;
3399 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
3400 (VMOVSHDUPYrr VR256:$src)>;
3401 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
3402 (VMOVSHDUPYrm addr:$src)>;
3403 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
3404 (VMOVSLDUPYrr VR256:$src)>;
3405 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
3406 (VMOVSLDUPYrm addr:$src)>;
3409 //===---------------------------------------------------------------------===//
3410 // Replicate Double FP - MOVDDUP
3412 multiclass sse3_replicate_dfp<string OpcodeStr> {
3413 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3414 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3415 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3416 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3417 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3419 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3423 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3424 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3425 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3427 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3428 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3432 let Predicates = [HasAVX] in {
3433 // FIXME: Merge above classes when we have patterns for the ymm version
3434 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3435 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3437 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3439 // Move Unaligned Integer
3440 let Predicates = [HasAVX] in {
3441 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3442 "vlddqu\t{$src, $dst|$dst, $src}",
3443 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3444 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3445 "vlddqu\t{$src, $dst|$dst, $src}",
3446 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
3448 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3449 "lddqu\t{$src, $dst|$dst, $src}",
3450 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3452 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3454 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3456 // Several Move patterns
3457 let AddedComplexity = 5 in {
3458 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3459 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3460 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3461 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3462 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3463 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3464 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3465 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3468 //===---------------------------------------------------------------------===//
3469 // SSE3 - Arithmetic
3470 //===---------------------------------------------------------------------===//
3472 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3473 X86MemOperand x86memop, bit Is2Addr = 1> {
3474 def rr : I<0xD0, MRMSrcReg,
3475 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3477 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3478 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3479 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3480 def rm : I<0xD0, MRMSrcMem,
3481 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3483 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3484 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3485 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3488 let Predicates = [HasAVX],
3489 ExeDomain = SSEPackedDouble in {
3490 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3491 f128mem, 0>, TB, XD, VEX_4V;
3492 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3493 f128mem, 0>, TB, OpSize, VEX_4V;
3494 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3495 f256mem, 0>, TB, XD, VEX_4V;
3496 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3497 f256mem, 0>, TB, OpSize, VEX_4V;
3499 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3500 ExeDomain = SSEPackedDouble in {
3501 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3503 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3504 f128mem>, TB, OpSize;
3507 //===---------------------------------------------------------------------===//
3508 // SSE3 Instructions
3509 //===---------------------------------------------------------------------===//
3512 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3513 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3514 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3516 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3517 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3518 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3520 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3522 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3523 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3524 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3526 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3527 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3528 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3530 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3531 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3532 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3534 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3536 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3537 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3538 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3541 let Predicates = [HasAVX] in {
3542 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3543 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3544 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3545 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3546 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3547 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3548 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3549 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3550 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3551 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3552 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3553 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3554 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3555 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3556 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3557 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3560 let Constraints = "$src1 = $dst" in {
3561 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3562 int_x86_sse3_hadd_ps>;
3563 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3564 int_x86_sse3_hadd_pd>;
3565 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3566 int_x86_sse3_hsub_ps>;
3567 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3568 int_x86_sse3_hsub_pd>;
3571 //===---------------------------------------------------------------------===//
3572 // SSSE3 - Packed Absolute Instructions
3573 //===---------------------------------------------------------------------===//
3576 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3577 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3578 PatFrag mem_frag128, Intrinsic IntId128> {
3579 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3581 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3582 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3585 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3587 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3590 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3593 let Predicates = [HasAVX] in {
3594 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
3595 int_x86_ssse3_pabs_b_128>, VEX;
3596 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
3597 int_x86_ssse3_pabs_w_128>, VEX;
3598 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
3599 int_x86_ssse3_pabs_d_128>, VEX;
3602 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
3603 int_x86_ssse3_pabs_b_128>;
3604 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
3605 int_x86_ssse3_pabs_w_128>;
3606 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
3607 int_x86_ssse3_pabs_d_128>;
3609 //===---------------------------------------------------------------------===//
3610 // SSSE3 - Packed Binary Operator Instructions
3611 //===---------------------------------------------------------------------===//
3613 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3614 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3615 PatFrag mem_frag128, Intrinsic IntId128,
3617 let isCommutable = 1 in
3618 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3619 (ins VR128:$src1, VR128:$src2),
3621 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3622 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3623 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3625 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3626 (ins VR128:$src1, i128mem:$src2),
3628 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3629 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3631 (IntId128 VR128:$src1,
3632 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3635 let Predicates = [HasAVX] in {
3636 let isCommutable = 0 in {
3637 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
3638 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3639 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
3640 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3641 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
3642 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3643 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
3644 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3645 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
3646 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3647 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
3648 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3649 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
3650 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3651 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
3652 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3653 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
3654 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3655 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
3656 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3657 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
3658 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3660 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
3661 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3664 // None of these have i8 immediate fields.
3665 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3666 let isCommutable = 0 in {
3667 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
3668 int_x86_ssse3_phadd_w_128>;
3669 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
3670 int_x86_ssse3_phadd_d_128>;
3671 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
3672 int_x86_ssse3_phadd_sw_128>;
3673 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
3674 int_x86_ssse3_phsub_w_128>;
3675 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
3676 int_x86_ssse3_phsub_d_128>;
3677 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
3678 int_x86_ssse3_phsub_sw_128>;
3679 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
3680 int_x86_ssse3_pmadd_ub_sw_128>;
3681 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
3682 int_x86_ssse3_pshuf_b_128>;
3683 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
3684 int_x86_ssse3_psign_b_128>;
3685 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
3686 int_x86_ssse3_psign_w_128>;
3687 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
3688 int_x86_ssse3_psign_d_128>;
3690 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
3691 int_x86_ssse3_pmul_hr_sw_128>;
3694 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3695 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3696 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3697 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3699 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
3700 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3701 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
3702 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3703 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
3704 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3706 //===---------------------------------------------------------------------===//
3707 // SSSE3 - Packed Align Instruction Patterns
3708 //===---------------------------------------------------------------------===//
3710 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
3711 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3712 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3714 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3716 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3718 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3719 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3721 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3723 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3727 let Predicates = [HasAVX] in
3728 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
3729 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
3730 defm PALIGN : ssse3_palign<"palignr">;
3732 let Predicates = [HasSSSE3] in {
3733 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3734 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3735 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3736 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3737 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3738 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3739 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3740 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3743 let Predicates = [HasAVX] in {
3744 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3745 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3746 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3747 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3748 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3749 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3750 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3751 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3754 //===---------------------------------------------------------------------===//
3755 // SSSE3 Misc Instructions
3756 //===---------------------------------------------------------------------===//
3758 // Thread synchronization
3759 let usesCustomInserter = 1 in {
3760 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
3761 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
3762 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
3763 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
3766 let Uses = [EAX, ECX, EDX] in
3767 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
3768 Requires<[HasSSE3]>;
3769 let Uses = [ECX, EAX] in
3770 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
3771 Requires<[HasSSE3]>;
3773 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
3774 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
3776 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
3777 Requires<[In32BitMode]>;
3778 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
3779 Requires<[In64BitMode]>;
3781 //===---------------------------------------------------------------------===//
3782 // Non-Instruction Patterns
3783 //===---------------------------------------------------------------------===//
3785 // extload f32 -> f64. This matches load+fextend because we have a hack in
3786 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3788 // Since these loads aren't folded into the fextend, we have to match it
3790 let Predicates = [HasSSE2] in
3791 def : Pat<(fextend (loadf32 addr:$src)),
3792 (CVTSS2SDrm addr:$src)>;
3794 // Bitcasts between 128-bit vector types. Return the original type since
3795 // no instruction is needed for the conversion
3796 let Predicates = [HasXMMInt] in {
3797 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3798 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3799 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3800 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3801 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3802 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3803 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3804 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3805 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3806 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3807 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3808 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3809 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3810 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3811 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3812 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3813 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3814 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3815 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3816 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3817 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3818 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3819 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3820 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3821 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3822 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3823 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3824 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3825 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3826 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3829 // Bitcasts between 256-bit vector types. Return the original type since
3830 // no instruction is needed for the conversion
3831 let Predicates = [HasAVX] in {
3832 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
3833 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
3834 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
3835 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
3836 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
3837 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
3838 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
3839 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
3840 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
3841 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
3842 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
3843 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
3844 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
3845 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
3846 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
3847 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
3848 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
3849 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
3850 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
3851 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
3852 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
3853 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
3854 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
3855 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
3856 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
3857 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
3858 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
3859 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
3860 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
3861 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
3864 // Move scalar to XMM zero-extended
3865 // movd to XMM register zero-extends
3866 let AddedComplexity = 15 in {
3867 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3868 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3869 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3870 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3871 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3872 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3873 (MOVSSrr (v4f32 (V_SET0PS)),
3874 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3875 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3876 (MOVSSrr (v4i32 (V_SET0PI)),
3877 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3880 // Splat v2f64 / v2i64
3881 let AddedComplexity = 10 in {
3882 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3883 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3884 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3885 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3888 // Special unary SHUFPSrri case.
3889 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3890 (SHUFPSrri VR128:$src1, VR128:$src1,
3891 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3892 let AddedComplexity = 5 in
3893 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3894 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3895 Requires<[HasSSE2]>;
3896 // Special unary SHUFPDrri case.
3897 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3898 (SHUFPDrri VR128:$src1, VR128:$src1,
3899 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3900 Requires<[HasSSE2]>;
3901 // Special unary SHUFPDrri case.
3902 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3903 (SHUFPDrri VR128:$src1, VR128:$src1,
3904 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3905 Requires<[HasSSE2]>;
3906 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3907 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3908 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3909 Requires<[HasSSE2]>;
3911 // Special binary v4i32 shuffle cases with SHUFPS.
3912 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3913 (SHUFPSrri VR128:$src1, VR128:$src2,
3914 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3915 Requires<[HasSSE2]>;
3916 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3917 (SHUFPSrmi VR128:$src1, addr:$src2,
3918 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3919 Requires<[HasSSE2]>;
3920 // Special binary v2i64 shuffle cases using SHUFPDrri.
3921 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3922 (SHUFPDrri VR128:$src1, VR128:$src2,
3923 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3924 Requires<[HasSSE2]>;
3926 let AddedComplexity = 20 in {
3927 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3928 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3929 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3931 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3932 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3933 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3935 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3936 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3937 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3938 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3939 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3942 let AddedComplexity = 20 in {
3943 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3944 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3945 (MOVLPSrm VR128:$src1, addr:$src2)>;
3946 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3947 (MOVLPDrm VR128:$src1, addr:$src2)>;
3948 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3949 (MOVLPSrm VR128:$src1, addr:$src2)>;
3950 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3951 (MOVLPDrm VR128:$src1, addr:$src2)>;
3954 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3955 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3956 (MOVLPSmr addr:$src1, VR128:$src2)>;
3957 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3958 (MOVLPDmr addr:$src1, VR128:$src2)>;
3959 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3961 (MOVLPSmr addr:$src1, VR128:$src2)>;
3962 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3963 (MOVLPDmr addr:$src1, VR128:$src2)>;
3965 let AddedComplexity = 15 in {
3966 // Setting the lowest element in the vector.
3967 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3968 (MOVSSrr (v4i32 VR128:$src1),
3969 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3970 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3971 (MOVSDrr (v2i64 VR128:$src1),
3972 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3974 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3975 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3976 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3977 Requires<[HasSSE2]>;
3978 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3979 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3980 Requires<[HasSSE2]>;
3983 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3984 // fall back to this for SSE1)
3985 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3986 (SHUFPSrri VR128:$src2, VR128:$src1,
3987 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3989 // Set lowest element and zero upper elements.
3990 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3991 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3993 // Use movaps / movups for SSE integer load / store (one byte shorter).
3994 // The instructions selected below are then converted to MOVDQA/MOVDQU
3995 // during the SSE domain pass.
3996 let Predicates = [HasSSE1] in {
3997 def : Pat<(alignedloadv4i32 addr:$src),
3998 (MOVAPSrm addr:$src)>;
3999 def : Pat<(loadv4i32 addr:$src),
4000 (MOVUPSrm addr:$src)>;
4001 def : Pat<(alignedloadv2i64 addr:$src),
4002 (MOVAPSrm addr:$src)>;
4003 def : Pat<(loadv2i64 addr:$src),
4004 (MOVUPSrm addr:$src)>;
4006 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4007 (MOVAPSmr addr:$dst, VR128:$src)>;
4008 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4009 (MOVAPSmr addr:$dst, VR128:$src)>;
4010 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4011 (MOVAPSmr addr:$dst, VR128:$src)>;
4012 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4013 (MOVAPSmr addr:$dst, VR128:$src)>;
4014 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4015 (MOVUPSmr addr:$dst, VR128:$src)>;
4016 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4017 (MOVUPSmr addr:$dst, VR128:$src)>;
4018 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4019 (MOVUPSmr addr:$dst, VR128:$src)>;
4020 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4021 (MOVUPSmr addr:$dst, VR128:$src)>;
4024 // Use vmovaps/vmovups for AVX integer load/store.
4025 let Predicates = [HasAVX] in {
4026 // 128-bit load/store
4027 def : Pat<(alignedloadv4i32 addr:$src),
4028 (VMOVAPSrm addr:$src)>;
4029 def : Pat<(loadv4i32 addr:$src),
4030 (VMOVUPSrm addr:$src)>;
4031 def : Pat<(alignedloadv2i64 addr:$src),
4032 (VMOVAPSrm addr:$src)>;
4033 def : Pat<(loadv2i64 addr:$src),
4034 (VMOVUPSrm addr:$src)>;
4036 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4037 (VMOVAPSmr addr:$dst, VR128:$src)>;
4038 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4039 (VMOVAPSmr addr:$dst, VR128:$src)>;
4040 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4041 (VMOVAPSmr addr:$dst, VR128:$src)>;
4042 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4043 (VMOVAPSmr addr:$dst, VR128:$src)>;
4044 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4045 (VMOVUPSmr addr:$dst, VR128:$src)>;
4046 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4047 (VMOVUPSmr addr:$dst, VR128:$src)>;
4048 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4049 (VMOVUPSmr addr:$dst, VR128:$src)>;
4050 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4051 (VMOVUPSmr addr:$dst, VR128:$src)>;
4053 // 256-bit load/store
4054 def : Pat<(alignedloadv4i64 addr:$src),
4055 (VMOVAPSYrm addr:$src)>;
4056 def : Pat<(loadv4i64 addr:$src),
4057 (VMOVUPSYrm addr:$src)>;
4058 def : Pat<(alignedloadv8i32 addr:$src),
4059 (VMOVAPSYrm addr:$src)>;
4060 def : Pat<(loadv8i32 addr:$src),
4061 (VMOVUPSYrm addr:$src)>;
4062 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
4063 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4064 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
4065 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4066 def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst),
4067 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4068 def : Pat<(alignedstore (v32i8 VR256:$src), addr:$dst),
4069 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4070 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
4071 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4072 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
4073 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4074 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
4075 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4076 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
4077 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4080 //===----------------------------------------------------------------------===//
4081 // SSE4.1 - Packed Move with Sign/Zero Extend
4082 //===----------------------------------------------------------------------===//
4084 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4085 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4086 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4087 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4089 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4090 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4092 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
4096 let Predicates = [HasAVX] in {
4097 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
4099 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
4101 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
4103 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
4105 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
4107 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
4111 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4112 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4113 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4114 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4115 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4116 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4118 // Common patterns involving scalar load.
4119 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4120 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4121 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4122 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4124 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4125 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4126 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4127 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4129 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4130 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4131 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4132 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4134 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4135 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4136 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4137 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4139 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4140 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4141 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4142 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4144 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4145 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4146 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4147 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4150 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4151 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4152 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4153 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4155 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4156 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4158 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4162 let Predicates = [HasAVX] in {
4163 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
4165 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
4167 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
4169 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
4173 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4174 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4175 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4176 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4178 // Common patterns involving scalar load
4179 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4180 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4181 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4182 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4184 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4185 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4186 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4187 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4190 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4191 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4192 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4193 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4195 // Expecting a i16 load any extended to i32 value.
4196 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4197 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4198 [(set VR128:$dst, (IntId (bitconvert
4199 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4203 let Predicates = [HasAVX] in {
4204 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4206 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4209 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4210 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4212 // Common patterns involving scalar load
4213 def : Pat<(int_x86_sse41_pmovsxbq
4214 (bitconvert (v4i32 (X86vzmovl
4215 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4216 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4218 def : Pat<(int_x86_sse41_pmovzxbq
4219 (bitconvert (v4i32 (X86vzmovl
4220 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4221 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4223 //===----------------------------------------------------------------------===//
4224 // SSE4.1 - Extract Instructions
4225 //===----------------------------------------------------------------------===//
4227 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4228 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4229 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4230 (ins VR128:$src1, i32i8imm:$src2),
4231 !strconcat(OpcodeStr,
4232 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4233 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4235 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4236 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4237 !strconcat(OpcodeStr,
4238 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4241 // There's an AssertZext in the way of writing the store pattern
4242 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4245 let Predicates = [HasAVX] in {
4246 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4247 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4248 (ins VR128:$src1, i32i8imm:$src2),
4249 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4252 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4255 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4256 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4257 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4258 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4259 !strconcat(OpcodeStr,
4260 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4263 // There's an AssertZext in the way of writing the store pattern
4264 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4267 let Predicates = [HasAVX] in
4268 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4270 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4273 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4274 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4275 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4276 (ins VR128:$src1, i32i8imm:$src2),
4277 !strconcat(OpcodeStr,
4278 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4280 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4281 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4282 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4283 !strconcat(OpcodeStr,
4284 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4285 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4286 addr:$dst)]>, OpSize;
4289 let Predicates = [HasAVX] in
4290 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4292 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4294 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4295 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4296 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4297 (ins VR128:$src1, i32i8imm:$src2),
4298 !strconcat(OpcodeStr,
4299 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4301 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4302 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4303 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4304 !strconcat(OpcodeStr,
4305 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4306 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4307 addr:$dst)]>, OpSize, REX_W;
4310 let Predicates = [HasAVX] in
4311 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4313 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4315 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4317 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4318 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4319 (ins VR128:$src1, i32i8imm:$src2),
4320 !strconcat(OpcodeStr,
4321 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4323 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4325 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4326 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4327 !strconcat(OpcodeStr,
4328 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4329 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4330 addr:$dst)]>, OpSize;
4333 let Predicates = [HasAVX] in {
4334 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4335 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4336 (ins VR128:$src1, i32i8imm:$src2),
4337 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4340 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4342 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4343 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4346 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4347 Requires<[HasSSE41]>;
4349 //===----------------------------------------------------------------------===//
4350 // SSE4.1 - Insert Instructions
4351 //===----------------------------------------------------------------------===//
4353 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4354 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4355 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4357 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4359 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4361 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4362 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4363 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4365 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4367 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4369 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4370 imm:$src3))]>, OpSize;
4373 let Predicates = [HasAVX] in
4374 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4375 let Constraints = "$src1 = $dst" in
4376 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4378 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4379 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4380 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4382 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4384 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4386 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4388 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4389 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4391 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4393 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4395 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4396 imm:$src3)))]>, OpSize;
4399 let Predicates = [HasAVX] in
4400 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4401 let Constraints = "$src1 = $dst" in
4402 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4404 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4405 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4406 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4408 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4410 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4412 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4414 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4415 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4417 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4419 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4421 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4422 imm:$src3)))]>, OpSize;
4425 let Predicates = [HasAVX] in
4426 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4427 let Constraints = "$src1 = $dst" in
4428 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4430 // insertps has a few different modes, there's the first two here below which
4431 // are optimized inserts that won't zero arbitrary elements in the destination
4432 // vector. The next one matches the intrinsic and could zero arbitrary elements
4433 // in the target vector.
4434 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4435 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4436 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
4438 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4440 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4442 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4444 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4445 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
4447 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4449 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4451 (X86insrtps VR128:$src1,
4452 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4453 imm:$src3))]>, OpSize;
4456 let Constraints = "$src1 = $dst" in
4457 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4458 let Predicates = [HasAVX] in
4459 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4461 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4462 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4464 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4465 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4466 Requires<[HasSSE41]>;
4468 //===----------------------------------------------------------------------===//
4469 // SSE4.1 - Round Instructions
4470 //===----------------------------------------------------------------------===//
4472 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4473 X86MemOperand x86memop, RegisterClass RC,
4474 PatFrag mem_frag32, PatFrag mem_frag64,
4475 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4476 // Intrinsic operation, reg.
4477 // Vector intrinsic operation, reg
4478 def PSr : SS4AIi8<opcps, MRMSrcReg,
4479 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4480 !strconcat(OpcodeStr,
4481 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4482 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4485 // Vector intrinsic operation, mem
4486 def PSm : Ii8<opcps, MRMSrcMem,
4487 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4488 !strconcat(OpcodeStr,
4489 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4491 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4493 Requires<[HasSSE41]>;
4495 // Vector intrinsic operation, reg
4496 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4497 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4498 !strconcat(OpcodeStr,
4499 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4500 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4503 // Vector intrinsic operation, mem
4504 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4505 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4506 !strconcat(OpcodeStr,
4507 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4509 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4513 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4514 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4515 // Intrinsic operation, reg.
4516 // Vector intrinsic operation, reg
4517 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
4518 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4519 !strconcat(OpcodeStr,
4520 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4523 // Vector intrinsic operation, mem
4524 def PSm_AVX : Ii8<opcps, MRMSrcMem,
4525 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4526 !strconcat(OpcodeStr,
4527 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4528 []>, TA, OpSize, Requires<[HasSSE41]>;
4530 // Vector intrinsic operation, reg
4531 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
4532 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4533 !strconcat(OpcodeStr,
4534 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4537 // Vector intrinsic operation, mem
4538 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
4539 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4540 !strconcat(OpcodeStr,
4541 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4545 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4548 Intrinsic F64Int, bit Is2Addr = 1> {
4549 // Intrinsic operation, reg.
4550 def SSr : SS4AIi8<opcss, MRMSrcReg,
4551 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4553 !strconcat(OpcodeStr,
4554 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4555 !strconcat(OpcodeStr,
4556 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4557 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4560 // Intrinsic operation, mem.
4561 def SSm : SS4AIi8<opcss, MRMSrcMem,
4562 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4564 !strconcat(OpcodeStr,
4565 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4566 !strconcat(OpcodeStr,
4567 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4569 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4572 // Intrinsic operation, reg.
4573 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4574 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4576 !strconcat(OpcodeStr,
4577 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4578 !strconcat(OpcodeStr,
4579 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4580 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4583 // Intrinsic operation, mem.
4584 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4585 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4587 !strconcat(OpcodeStr,
4588 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4589 !strconcat(OpcodeStr,
4590 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4592 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4596 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4598 // Intrinsic operation, reg.
4599 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
4600 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4601 !strconcat(OpcodeStr,
4602 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4605 // Intrinsic operation, mem.
4606 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
4607 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4608 !strconcat(OpcodeStr,
4609 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4612 // Intrinsic operation, reg.
4613 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
4614 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4615 !strconcat(OpcodeStr,
4616 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4619 // Intrinsic operation, mem.
4620 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
4621 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4622 !strconcat(OpcodeStr,
4623 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4627 // FP round - roundss, roundps, roundsd, roundpd
4628 let Predicates = [HasAVX] in {
4630 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4631 memopv4f32, memopv2f64,
4632 int_x86_sse41_round_ps,
4633 int_x86_sse41_round_pd>, VEX;
4634 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4635 memopv8f32, memopv4f64,
4636 int_x86_avx_round_ps_256,
4637 int_x86_avx_round_pd_256>, VEX;
4638 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4639 int_x86_sse41_round_ss,
4640 int_x86_sse41_round_sd, 0>, VEX_4V;
4642 // Instructions for the assembler
4643 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4645 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4647 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4650 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4651 memopv4f32, memopv2f64,
4652 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4653 let Constraints = "$src1 = $dst" in
4654 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4655 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4657 //===----------------------------------------------------------------------===//
4658 // SSE4.1 - Packed Bit Test
4659 //===----------------------------------------------------------------------===//
4661 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4662 // the intel intrinsic that corresponds to this.
4663 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4664 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4665 "vptest\t{$src2, $src1|$src1, $src2}",
4666 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4668 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4669 "vptest\t{$src2, $src1|$src1, $src2}",
4670 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4673 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4674 "vptest\t{$src2, $src1|$src1, $src2}",
4675 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
4677 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4678 "vptest\t{$src2, $src1|$src1, $src2}",
4679 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
4683 let Defs = [EFLAGS] in {
4684 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4685 "ptest \t{$src2, $src1|$src1, $src2}",
4686 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4688 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4689 "ptest \t{$src2, $src1|$src1, $src2}",
4690 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4694 // The bit test instructions below are AVX only
4695 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4696 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
4697 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
4698 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4699 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
4700 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
4701 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4702 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
4706 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4707 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
4708 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
4709 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
4710 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
4713 //===----------------------------------------------------------------------===//
4714 // SSE4.1 - Misc Instructions
4715 //===----------------------------------------------------------------------===//
4717 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4718 "popcnt{w}\t{$src, $dst|$dst, $src}",
4719 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
4720 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4721 "popcnt{w}\t{$src, $dst|$dst, $src}",
4722 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
4724 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4725 "popcnt{l}\t{$src, $dst|$dst, $src}",
4726 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
4727 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4728 "popcnt{l}\t{$src, $dst|$dst, $src}",
4729 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
4731 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4732 "popcnt{q}\t{$src, $dst|$dst, $src}",
4733 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
4734 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4735 "popcnt{q}\t{$src, $dst|$dst, $src}",
4736 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
4740 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4741 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4742 Intrinsic IntId128> {
4743 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4745 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4746 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4747 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4749 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4752 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4755 let Predicates = [HasAVX] in
4756 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4757 int_x86_sse41_phminposuw>, VEX;
4758 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4759 int_x86_sse41_phminposuw>;
4761 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4762 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4763 Intrinsic IntId128, bit Is2Addr = 1> {
4764 let isCommutable = 1 in
4765 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4766 (ins VR128:$src1, VR128:$src2),
4768 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4769 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4770 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4771 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4772 (ins VR128:$src1, i128mem:$src2),
4774 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4775 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4777 (IntId128 VR128:$src1,
4778 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4781 let Predicates = [HasAVX] in {
4782 let isCommutable = 0 in
4783 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4785 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4787 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4789 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4791 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4793 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4795 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4797 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4799 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4801 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4803 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4807 let Constraints = "$src1 = $dst" in {
4808 let isCommutable = 0 in
4809 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4810 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4811 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4812 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4813 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4814 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4815 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4816 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4817 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4818 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4819 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4822 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4823 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4824 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4825 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4827 /// SS48I_binop_rm - Simple SSE41 binary operator.
4828 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4829 ValueType OpVT, bit Is2Addr = 1> {
4830 let isCommutable = 1 in
4831 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4832 (ins VR128:$src1, VR128:$src2),
4834 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4835 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4836 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4838 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4839 (ins VR128:$src1, i128mem:$src2),
4841 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4842 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4843 [(set VR128:$dst, (OpNode VR128:$src1,
4844 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4848 let Predicates = [HasAVX] in
4849 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4850 let Constraints = "$src1 = $dst" in
4851 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4853 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4854 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4855 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4856 X86MemOperand x86memop, bit Is2Addr = 1> {
4857 let isCommutable = 1 in
4858 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4859 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
4861 !strconcat(OpcodeStr,
4862 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4863 !strconcat(OpcodeStr,
4864 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4865 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4867 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4868 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
4870 !strconcat(OpcodeStr,
4871 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4872 !strconcat(OpcodeStr,
4873 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4876 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4880 let Predicates = [HasAVX] in {
4881 let isCommutable = 0 in {
4882 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4883 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4884 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4885 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4886 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
4887 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4888 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
4889 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4890 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4891 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4892 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4893 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4895 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4896 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4897 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4898 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4899 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
4900 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4903 let Constraints = "$src1 = $dst" in {
4904 let isCommutable = 0 in {
4905 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4906 VR128, memopv16i8, i128mem>;
4907 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4908 VR128, memopv16i8, i128mem>;
4909 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4910 VR128, memopv16i8, i128mem>;
4911 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4912 VR128, memopv16i8, i128mem>;
4914 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4915 VR128, memopv16i8, i128mem>;
4916 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4917 VR128, memopv16i8, i128mem>;
4920 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4921 let Predicates = [HasAVX] in {
4922 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4923 RegisterClass RC, X86MemOperand x86memop,
4924 PatFrag mem_frag, Intrinsic IntId> {
4925 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4926 (ins RC:$src1, RC:$src2, RC:$src3),
4927 !strconcat(OpcodeStr,
4928 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4929 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4930 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4932 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4933 (ins RC:$src1, x86memop:$src2, RC:$src3),
4934 !strconcat(OpcodeStr,
4935 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4937 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
4939 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4943 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
4944 memopv16i8, int_x86_sse41_blendvpd>;
4945 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
4946 memopv16i8, int_x86_sse41_blendvps>;
4947 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
4948 memopv16i8, int_x86_sse41_pblendvb>;
4949 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
4950 memopv32i8, int_x86_avx_blendv_pd_256>;
4951 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
4952 memopv32i8, int_x86_avx_blendv_ps_256>;
4954 /// SS41I_ternary_int - SSE 4.1 ternary operator
4955 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4956 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4957 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4958 (ins VR128:$src1, VR128:$src2),
4959 !strconcat(OpcodeStr,
4960 "\t{$src2, $dst|$dst, $src2}"),
4961 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4964 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4965 (ins VR128:$src1, i128mem:$src2),
4966 !strconcat(OpcodeStr,
4967 "\t{$src2, $dst|$dst, $src2}"),
4970 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4974 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4975 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4976 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4978 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
4979 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
4981 let Predicates = [HasAVX] in
4982 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4983 "vmovntdqa\t{$src, $dst|$dst, $src}",
4984 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4986 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4987 "movntdqa\t{$src, $dst|$dst, $src}",
4988 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4991 //===----------------------------------------------------------------------===//
4992 // SSE4.2 - Compare Instructions
4993 //===----------------------------------------------------------------------===//
4995 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4996 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4997 Intrinsic IntId128, bit Is2Addr = 1> {
4998 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4999 (ins VR128:$src1, VR128:$src2),
5001 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5002 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5003 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5005 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
5006 (ins VR128:$src1, i128mem:$src2),
5008 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5009 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5011 (IntId128 VR128:$src1,
5012 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5015 let Predicates = [HasAVX] in
5016 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
5018 let Constraints = "$src1 = $dst" in
5019 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
5021 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
5022 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
5023 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
5024 (PCMPGTQrm VR128:$src1, addr:$src2)>;
5026 //===----------------------------------------------------------------------===//
5027 // SSE4.2 - String/text Processing Instructions
5028 //===----------------------------------------------------------------------===//
5030 // Packed Compare Implicit Length Strings, Return Mask
5031 multiclass pseudo_pcmpistrm<string asm> {
5032 def REG : PseudoI<(outs VR128:$dst),
5033 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5034 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
5036 def MEM : PseudoI<(outs VR128:$dst),
5037 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5038 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
5039 VR128:$src1, (load addr:$src2), imm:$src3))]>;
5042 let Defs = [EFLAGS], usesCustomInserter = 1 in {
5043 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
5044 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
5047 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
5048 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5049 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5050 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5051 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5052 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5053 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5056 let Defs = [XMM0, EFLAGS] in {
5057 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5058 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5059 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5060 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5061 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5062 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5065 // Packed Compare Explicit Length Strings, Return Mask
5066 multiclass pseudo_pcmpestrm<string asm> {
5067 def REG : PseudoI<(outs VR128:$dst),
5068 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5069 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5070 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
5071 def MEM : PseudoI<(outs VR128:$dst),
5072 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5073 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5074 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
5077 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
5078 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
5079 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
5082 let Predicates = [HasAVX],
5083 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5084 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5085 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5086 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5087 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5088 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5089 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5092 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5093 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5094 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5095 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5096 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5097 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5098 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5101 // Packed Compare Implicit Length Strings, Return Index
5102 let Defs = [ECX, EFLAGS] in {
5103 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
5104 def rr : SS42AI<0x63, MRMSrcReg, (outs),
5105 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5106 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5107 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
5108 (implicit EFLAGS)]>, OpSize;
5109 def rm : SS42AI<0x63, MRMSrcMem, (outs),
5110 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5111 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5112 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
5113 (implicit EFLAGS)]>, OpSize;
5117 let Predicates = [HasAVX] in {
5118 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
5120 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
5122 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
5124 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
5126 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
5128 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
5132 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
5133 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
5134 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
5135 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
5136 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
5137 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
5139 // Packed Compare Explicit Length Strings, Return Index
5140 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
5141 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
5142 def rr : SS42AI<0x61, MRMSrcReg, (outs),
5143 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5144 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5145 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
5146 (implicit EFLAGS)]>, OpSize;
5147 def rm : SS42AI<0x61, MRMSrcMem, (outs),
5148 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5149 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5151 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
5152 (implicit EFLAGS)]>, OpSize;
5156 let Predicates = [HasAVX] in {
5157 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
5159 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
5161 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
5163 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
5165 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
5167 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
5171 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
5172 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
5173 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
5174 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
5175 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
5176 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
5178 //===----------------------------------------------------------------------===//
5179 // SSE4.2 - CRC Instructions
5180 //===----------------------------------------------------------------------===//
5182 // No CRC instructions have AVX equivalents
5184 // crc intrinsic instruction
5185 // This set of instructions are only rm, the only difference is the size
5187 let Constraints = "$src1 = $dst" in {
5188 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5189 (ins GR32:$src1, i8mem:$src2),
5190 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5192 (int_x86_sse42_crc32_32_8 GR32:$src1,
5193 (load addr:$src2)))]>;
5194 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5195 (ins GR32:$src1, GR8:$src2),
5196 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5198 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
5199 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5200 (ins GR32:$src1, i16mem:$src2),
5201 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5203 (int_x86_sse42_crc32_32_16 GR32:$src1,
5204 (load addr:$src2)))]>,
5206 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5207 (ins GR32:$src1, GR16:$src2),
5208 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5210 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
5212 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5213 (ins GR32:$src1, i32mem:$src2),
5214 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5216 (int_x86_sse42_crc32_32_32 GR32:$src1,
5217 (load addr:$src2)))]>;
5218 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5219 (ins GR32:$src1, GR32:$src2),
5220 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5222 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
5223 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5224 (ins GR64:$src1, i8mem:$src2),
5225 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5227 (int_x86_sse42_crc32_64_8 GR64:$src1,
5228 (load addr:$src2)))]>,
5230 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5231 (ins GR64:$src1, GR8:$src2),
5232 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5234 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
5236 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5237 (ins GR64:$src1, i64mem:$src2),
5238 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5240 (int_x86_sse42_crc32_64_64 GR64:$src1,
5241 (load addr:$src2)))]>,
5243 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5244 (ins GR64:$src1, GR64:$src2),
5245 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5247 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
5251 //===----------------------------------------------------------------------===//
5252 // AES-NI Instructions
5253 //===----------------------------------------------------------------------===//
5255 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5256 Intrinsic IntId128, bit Is2Addr = 1> {
5257 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5258 (ins VR128:$src1, VR128:$src2),
5260 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5261 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5262 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5264 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5265 (ins VR128:$src1, i128mem:$src2),
5267 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5268 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5270 (IntId128 VR128:$src1,
5271 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5274 // Perform One Round of an AES Encryption/Decryption Flow
5275 let Predicates = [HasAVX, HasAES] in {
5276 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5277 int_x86_aesni_aesenc, 0>, VEX_4V;
5278 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5279 int_x86_aesni_aesenclast, 0>, VEX_4V;
5280 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5281 int_x86_aesni_aesdec, 0>, VEX_4V;
5282 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5283 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5286 let Constraints = "$src1 = $dst" in {
5287 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5288 int_x86_aesni_aesenc>;
5289 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5290 int_x86_aesni_aesenclast>;
5291 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5292 int_x86_aesni_aesdec>;
5293 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5294 int_x86_aesni_aesdeclast>;
5297 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5298 (AESENCrr VR128:$src1, VR128:$src2)>;
5299 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5300 (AESENCrm VR128:$src1, addr:$src2)>;
5301 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5302 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5303 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5304 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5305 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5306 (AESDECrr VR128:$src1, VR128:$src2)>;
5307 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5308 (AESDECrm VR128:$src1, addr:$src2)>;
5309 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5310 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5311 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5312 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5314 // Perform the AES InvMixColumn Transformation
5315 let Predicates = [HasAVX, HasAES] in {
5316 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5318 "vaesimc\t{$src1, $dst|$dst, $src1}",
5320 (int_x86_aesni_aesimc VR128:$src1))]>,
5322 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5323 (ins i128mem:$src1),
5324 "vaesimc\t{$src1, $dst|$dst, $src1}",
5326 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5329 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5331 "aesimc\t{$src1, $dst|$dst, $src1}",
5333 (int_x86_aesni_aesimc VR128:$src1))]>,
5335 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5336 (ins i128mem:$src1),
5337 "aesimc\t{$src1, $dst|$dst, $src1}",
5339 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5342 // AES Round Key Generation Assist
5343 let Predicates = [HasAVX, HasAES] in {
5344 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5345 (ins VR128:$src1, i8imm:$src2),
5346 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5348 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5350 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5351 (ins i128mem:$src1, i8imm:$src2),
5352 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5354 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5358 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5359 (ins VR128:$src1, i8imm:$src2),
5360 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5362 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5364 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5365 (ins i128mem:$src1, i8imm:$src2),
5366 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5368 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5372 //===----------------------------------------------------------------------===//
5373 // CLMUL Instructions
5374 //===----------------------------------------------------------------------===//
5376 // Carry-less Multiplication instructions
5377 let Constraints = "$src1 = $dst" in {
5378 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5379 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5380 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5383 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5384 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5385 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5389 // AVX carry-less Multiplication instructions
5390 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5391 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5392 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5395 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5396 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5397 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5401 multiclass pclmul_alias<string asm, int immop> {
5402 def : InstAlias<!strconcat("pclmul", asm,
5403 "dq {$src, $dst|$dst, $src}"),
5404 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
5406 def : InstAlias<!strconcat("pclmul", asm,
5407 "dq {$src, $dst|$dst, $src}"),
5408 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
5410 def : InstAlias<!strconcat("vpclmul", asm,
5411 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5412 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
5414 def : InstAlias<!strconcat("vpclmul", asm,
5415 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5416 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
5418 defm : pclmul_alias<"hqhq", 0x11>;
5419 defm : pclmul_alias<"hqlq", 0x01>;
5420 defm : pclmul_alias<"lqhq", 0x10>;
5421 defm : pclmul_alias<"lqlq", 0x00>;
5423 //===----------------------------------------------------------------------===//
5425 //===----------------------------------------------------------------------===//
5427 //===----------------------------------------------------------------------===//
5428 // VBROADCAST - Load from memory and broadcast to all elements of the
5429 // destination operand
5431 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5432 X86MemOperand x86memop, Intrinsic Int> :
5433 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5434 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5435 [(set RC:$dst, (Int addr:$src))]>, VEX;
5437 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5438 int_x86_avx_vbroadcastss>;
5439 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5440 int_x86_avx_vbroadcastss_256>;
5441 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5442 int_x86_avx_vbroadcast_sd_256>;
5443 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5444 int_x86_avx_vbroadcastf128_pd_256>;
5446 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5447 (VBROADCASTF128 addr:$src)>;
5449 //===----------------------------------------------------------------------===//
5450 // VINSERTF128 - Insert packed floating-point values
5452 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5453 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5454 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5456 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5457 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5458 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5461 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5462 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5463 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5464 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5465 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5466 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5468 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
5470 (VINSERTF128rr VR256:$src1, VR128:$src2,
5471 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5472 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
5474 (VINSERTF128rr VR256:$src1, VR128:$src2,
5475 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5476 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
5478 (VINSERTF128rr VR256:$src1, VR128:$src2,
5479 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5480 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
5482 (VINSERTF128rr VR256:$src1, VR128:$src2,
5483 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5484 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
5486 (VINSERTF128rr VR256:$src1, VR128:$src2,
5487 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5488 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
5490 (VINSERTF128rr VR256:$src1, VR128:$src2,
5491 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5493 // Special COPY patterns
5494 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
5495 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5496 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
5497 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5498 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
5499 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5500 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
5501 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5502 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
5503 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5504 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
5505 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5507 //===----------------------------------------------------------------------===//
5508 // VEXTRACTF128 - Extract packed floating-point values
5510 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5511 (ins VR256:$src1, i8imm:$src2),
5512 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5514 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5515 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5516 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5519 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
5520 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5521 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
5522 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5523 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
5524 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5526 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5527 (v4f32 (VEXTRACTF128rr
5528 (v8f32 VR256:$src1),
5529 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5530 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5531 (v2f64 (VEXTRACTF128rr
5532 (v4f64 VR256:$src1),
5533 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5534 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5535 (v4i32 (VEXTRACTF128rr
5536 (v8i32 VR256:$src1),
5537 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5538 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5539 (v2i64 (VEXTRACTF128rr
5540 (v4i64 VR256:$src1),
5541 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5542 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5543 (v8i16 (VEXTRACTF128rr
5544 (v16i16 VR256:$src1),
5545 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5546 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5547 (v16i8 (VEXTRACTF128rr
5548 (v32i8 VR256:$src1),
5549 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5551 // Special COPY patterns
5552 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
5553 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
5554 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
5555 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
5557 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
5558 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
5559 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
5560 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
5563 //===----------------------------------------------------------------------===//
5564 // VMASKMOV - Conditional SIMD Packed Loads and Stores
5566 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
5567 Intrinsic IntLd, Intrinsic IntLd256,
5568 Intrinsic IntSt, Intrinsic IntSt256,
5569 PatFrag pf128, PatFrag pf256> {
5570 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5571 (ins VR128:$src1, f128mem:$src2),
5572 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5573 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
5575 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5576 (ins VR256:$src1, f256mem:$src2),
5577 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5578 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
5580 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5581 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5582 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5583 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
5584 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5585 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5586 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5587 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
5590 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
5591 int_x86_avx_maskload_ps,
5592 int_x86_avx_maskload_ps_256,
5593 int_x86_avx_maskstore_ps,
5594 int_x86_avx_maskstore_ps_256,
5595 memopv4f32, memopv8f32>;
5596 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
5597 int_x86_avx_maskload_pd,
5598 int_x86_avx_maskload_pd_256,
5599 int_x86_avx_maskstore_pd,
5600 int_x86_avx_maskstore_pd_256,
5601 memopv2f64, memopv4f64>;
5603 //===----------------------------------------------------------------------===//
5604 // VPERM - Permute Floating-Point Values
5606 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5607 RegisterClass RC, X86MemOperand x86memop_f,
5608 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5609 Intrinsic IntVar, Intrinsic IntImm> {
5610 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5611 (ins RC:$src1, RC:$src2),
5612 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5613 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5614 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5615 (ins RC:$src1, x86memop_i:$src2),
5616 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5617 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5619 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5620 (ins RC:$src1, i8imm:$src2),
5621 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5622 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5623 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5624 (ins x86memop_f:$src1, i8imm:$src2),
5625 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5626 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5629 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5630 memopv4f32, memopv4i32,
5631 int_x86_avx_vpermilvar_ps,
5632 int_x86_avx_vpermil_ps>;
5633 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5634 memopv8f32, memopv8i32,
5635 int_x86_avx_vpermilvar_ps_256,
5636 int_x86_avx_vpermil_ps_256>;
5637 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5638 memopv2f64, memopv2i64,
5639 int_x86_avx_vpermilvar_pd,
5640 int_x86_avx_vpermil_pd>;
5641 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5642 memopv4f64, memopv4i64,
5643 int_x86_avx_vpermilvar_pd_256,
5644 int_x86_avx_vpermil_pd_256>;
5646 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5647 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5648 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5650 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5651 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5652 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5655 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5656 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5657 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5658 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5659 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5660 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5662 def : Pat<(int_x86_avx_vperm2f128_ps_256
5663 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5664 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5665 def : Pat<(int_x86_avx_vperm2f128_pd_256
5666 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5667 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5668 def : Pat<(int_x86_avx_vperm2f128_si_256
5669 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5670 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5672 // Shuffle with VPERMIL instructions
5673 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
5674 (VPERMILPSYri VR256:$src1, imm:$imm)>;
5675 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
5676 (VPERMILPDYri VR256:$src1, imm:$imm)>;
5677 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
5678 (VPERMILPSYri VR256:$src1, imm:$imm)>;
5679 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
5680 (VPERMILPDYri VR256:$src1, imm:$imm)>;
5682 //===----------------------------------------------------------------------===//
5683 // VZERO - Zero YMM registers
5685 // Zero All YMM registers
5686 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
5687 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
5689 // Zero Upper bits of YMM registers
5690 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
5691 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
5693 //===----------------------------------------------------------------------===//
5694 // SSE Shuffle pattern fragments
5695 //===----------------------------------------------------------------------===//
5697 // This is part of a "work in progress" refactoring. The idea is that all
5698 // vector shuffles are going to be translated into target specific nodes and
5699 // directly matched by the patterns below (which can be changed along the way)
5700 // The AVX version of some but not all of them are described here, and more
5701 // should come in a near future.
5703 // Shuffle with PSHUFD instruction folding loads. The first two patterns match
5704 // SSE2 loads, which are always promoted to v2i64. The last one should match
5705 // the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD
5706 // in SSE2, how does it ever worked? Anyway, the pattern will remain here until
5707 // we investigate further.
5708 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5710 (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
5711 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5713 (PSHUFDmi addr:$src1, imm:$imm)>;
5714 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
5716 (PSHUFDmi addr:$src1, imm:$imm)>; // FIXME: has this ever worked?
5718 // Shuffle with PSHUFD instruction.
5719 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5720 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5721 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5722 (PSHUFDri VR128:$src1, imm:$imm)>;
5724 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5725 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5726 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5727 (PSHUFDri VR128:$src1, imm:$imm)>;
5729 // Shuffle with SHUFPD instruction.
5730 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5731 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5732 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5733 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5734 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5735 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
5737 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5738 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5739 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5740 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5742 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5743 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5744 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5745 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5747 // Shuffle with SHUFPS instruction.
5748 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5749 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5750 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5751 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5752 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5753 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5755 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5756 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5757 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5758 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5760 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5761 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5762 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5763 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5764 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5765 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5767 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5768 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5769 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5770 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5772 // Shuffle with MOVHLPS instruction
5773 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
5774 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5775 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
5776 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5778 // Shuffle with MOVDDUP instruction
5779 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5780 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5781 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5782 (MOVDDUPrm addr:$src)>;
5784 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5785 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5786 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5787 (MOVDDUPrm addr:$src)>;
5789 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5790 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5791 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5792 (MOVDDUPrm addr:$src)>;
5794 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5795 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5796 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5797 (MOVDDUPrm addr:$src)>;
5799 def : Pat<(X86Movddup (bc_v2f64
5800 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5801 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5802 def : Pat<(X86Movddup (bc_v2f64
5803 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5804 (MOVDDUPrm addr:$src)>;
5807 // Shuffle with UNPCKLPS
5808 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5809 (VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5810 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5811 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
5813 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5814 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5815 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5816 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
5818 // Shuffle with VUNPCKHPSY
5819 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
5820 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5821 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
5822 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5823 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
5824 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5825 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
5826 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5828 // Shuffle with UNPCKHPS
5829 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5830 (VUNPCKHPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5831 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5832 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
5834 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5835 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5836 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5837 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
5839 // Shuffle with VUNPCKHPSY
5840 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
5841 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5842 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
5843 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5845 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
5846 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5847 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
5848 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5850 // Shuffle with UNPCKLPD
5851 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5852 (VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5853 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5854 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
5856 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5857 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5858 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5859 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
5861 // Shuffle with VUNPCKLPDY
5862 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
5863 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5864 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
5865 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5867 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
5868 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5869 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
5870 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5872 // Shuffle with UNPCKHPD
5873 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5874 (VUNPCKHPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5875 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5876 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
5878 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5879 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5880 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5881 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
5883 // Shuffle with VUNPCKHPDY
5884 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
5885 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5886 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
5887 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5888 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
5889 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5890 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
5891 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5893 // Shuffle with MOVLHPS
5894 def : Pat<(X86Movlhps VR128:$src1,
5895 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5896 (MOVHPSrm VR128:$src1, addr:$src2)>;
5897 def : Pat<(X86Movlhps VR128:$src1,
5898 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
5899 (MOVHPSrm VR128:$src1, addr:$src2)>;
5900 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
5901 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5902 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
5903 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5904 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
5905 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
5907 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem
5908 // is during lowering, where it's not possible to recognize the load fold cause
5909 // it has two uses through a bitcast. One use disappears at isel time and the
5910 // fold opportunity reappears.
5911 def : Pat<(v2f64 (X86Movddup VR128:$src)),
5912 (UNPCKLPDrr VR128:$src, VR128:$src)>;
5914 // Shuffle with MOVLHPD
5915 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
5916 (scalar_to_vector (loadf64 addr:$src2)))),
5917 (MOVHPDrm VR128:$src1, addr:$src2)>;
5919 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
5920 // is during lowering, where it's not possible to recognize the load fold cause
5921 // it has two uses through a bitcast. One use disappears at isel time and the
5922 // fold opportunity reappears.
5923 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
5924 (scalar_to_vector (loadf64 addr:$src2)))),
5925 (MOVHPDrm VR128:$src1, addr:$src2)>;
5927 // Shuffle with MOVSS
5928 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
5929 (MOVSSrr VR128:$src1, FR32:$src2)>;
5930 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
5931 (MOVSSrr (v4i32 VR128:$src1),
5932 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
5933 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
5934 (MOVSSrr (v4f32 VR128:$src1),
5935 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
5936 // FIXME: Instead of a X86Movss there should be a X86Movlps here, the problem
5937 // is during lowering, where it's not possible to recognize the load fold cause
5938 // it has two uses through a bitcast. One use disappears at isel time and the
5939 // fold opportunity reappears.
5940 def : Pat<(X86Movss VR128:$src1,
5941 (bc_v4i32 (v2i64 (load addr:$src2)))),
5942 (MOVLPSrm VR128:$src1, addr:$src2)>;
5944 // Shuffle with MOVSD
5945 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
5946 (MOVSDrr VR128:$src1, FR64:$src2)>;
5947 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
5948 (MOVSDrr (v2i64 VR128:$src1),
5949 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
5950 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
5951 (MOVSDrr (v2f64 VR128:$src1),
5952 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
5953 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
5954 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5955 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
5956 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5958 // Shuffle with PSHUFHW
5959 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
5960 (PSHUFHWri VR128:$src, imm:$imm)>;
5961 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5962 (PSHUFHWmi addr:$src, imm:$imm)>;
5964 // Shuffle with PSHUFLW
5965 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
5966 (PSHUFLWri VR128:$src, imm:$imm)>;
5967 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5968 (PSHUFLWmi addr:$src, imm:$imm)>;
5970 // Shuffle with MOVLPS
5971 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
5972 (MOVLPSrm VR128:$src1, addr:$src2)>;
5973 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
5974 (MOVLPSrm VR128:$src1, addr:$src2)>;
5975 def : Pat<(X86Movlps VR128:$src1,
5976 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5977 (MOVLPSrm VR128:$src1, addr:$src2)>;
5978 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
5979 // is during lowering, where it's not possible to recognize the load fold cause
5980 // it has two uses through a bitcast. One use disappears at isel time and the
5981 // fold opportunity reappears.
5982 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
5983 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5985 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
5986 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5988 // Shuffle with MOVLPD
5989 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5990 (MOVLPDrm VR128:$src1, addr:$src2)>;
5991 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5992 (MOVLPDrm VR128:$src1, addr:$src2)>;
5993 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
5994 (scalar_to_vector (loadf64 addr:$src2)))),
5995 (MOVLPDrm VR128:$src1, addr:$src2)>;
5997 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
5998 def : Pat<(store (f64 (vector_extract
5999 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
6000 (MOVHPSmr addr:$dst, VR128:$src)>;
6001 def : Pat<(store (f64 (vector_extract
6002 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
6003 (MOVHPDmr addr:$dst, VR128:$src)>;
6005 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
6006 (MOVLPSmr addr:$src1, VR128:$src2)>;
6007 def : Pat<(store (v4i32 (X86Movlps
6008 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
6009 (MOVLPSmr addr:$src1, VR128:$src2)>;
6011 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
6012 (MOVLPDmr addr:$src1, VR128:$src2)>;
6013 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
6014 (MOVLPDmr addr:$src1, VR128:$src2)>;