1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // SSE 1 & 2 - Move Instructions
120 //===----------------------------------------------------------------------===//
122 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
123 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
124 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
126 // Loading from memory automatically zeroing upper bits.
127 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
128 PatFrag mem_pat, string OpcodeStr> :
129 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
131 [(set RC:$dst, (mem_pat addr:$src))]>;
133 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
134 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
135 // is used instead. Register-to-register movss/movsd is not modeled as an
136 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
137 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
138 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
139 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
140 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
141 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
143 let canFoldAsLoad = 1, isReMaterializable = 1 in {
144 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
146 let AddedComplexity = 20 in
147 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
150 let Constraints = "$src1 = $dst" in {
151 def MOVSSrr : sse12_move_rr<FR32, v4f32,
152 "movss\t{$src2, $dst|$dst, $src2}">, XS;
153 def MOVSDrr : sse12_move_rr<FR64, v2f64,
154 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
157 let canFoldAsLoad = 1, isReMaterializable = 1 in {
158 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
160 let AddedComplexity = 20 in
161 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
164 let AddedComplexity = 15 in {
165 // Extract the low 32-bit value from one vector and insert it into another.
166 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
167 (MOVSSrr (v4f32 VR128:$src1),
168 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
169 // Extract the low 64-bit value from one vector and insert it into another.
170 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
171 (MOVSDrr (v2f64 VR128:$src1),
172 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
175 // Implicitly promote a 32-bit scalar to a vector.
176 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
177 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
178 // Implicitly promote a 64-bit scalar to a vector.
179 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
180 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
181 // Implicitly promote a 32-bit scalar to a vector.
182 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
183 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
184 // Implicitly promote a 64-bit scalar to a vector.
185 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
186 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
188 let AddedComplexity = 20 in {
189 let Predicates = [HasSSE1] in {
190 // MOVSSrm zeros the high parts of the register; represent this
191 // with SUBREG_TO_REG.
192 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
193 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
194 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
195 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
196 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
197 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
199 let Predicates = [HasSSE2] in {
200 // MOVSDrm zeros the high parts of the register; represent this
201 // with SUBREG_TO_REG.
202 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
203 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
204 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
205 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
206 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
207 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
208 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
209 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
210 def : Pat<(v2f64 (X86vzload addr:$src)),
211 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
215 let AddedComplexity = 20, Predicates = [HasAVX] in {
216 // MOVSSrm zeros the high parts of the register; represent this
217 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
218 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
219 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
220 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
221 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
222 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
223 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
224 // MOVSDrm zeros the high parts of the register; represent this
225 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
226 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
227 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
228 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
229 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
230 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
231 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
232 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
233 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
234 def : Pat<(v2f64 (X86vzload addr:$src)),
235 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
236 // Represent the same patterns above but in the form they appear for
238 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
239 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
240 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
241 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
242 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
243 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
246 // Store scalar value to memory.
247 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
248 "movss\t{$src, $dst|$dst, $src}",
249 [(store FR32:$src, addr:$dst)]>;
250 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
251 "movsd\t{$src, $dst|$dst, $src}",
252 [(store FR64:$src, addr:$dst)]>;
254 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
255 "movss\t{$src, $dst|$dst, $src}",
256 [(store FR32:$src, addr:$dst)]>, XS, VEX;
257 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
258 "movsd\t{$src, $dst|$dst, $src}",
259 [(store FR64:$src, addr:$dst)]>, XD, VEX;
261 // Extract and store.
262 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
265 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
266 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
269 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
271 // Move Aligned/Unaligned floating point values
272 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
273 X86MemOperand x86memop, PatFrag ld_frag,
274 string asm, Domain d,
275 bit IsReMaterializable = 1> {
276 let neverHasSideEffects = 1 in
277 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
278 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
279 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
280 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
281 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
282 [(set RC:$dst, (ld_frag addr:$src))], d>;
285 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
286 "movaps", SSEPackedSingle>, VEX;
287 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
288 "movapd", SSEPackedDouble>, OpSize, VEX;
289 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
290 "movups", SSEPackedSingle>, VEX;
291 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
292 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
294 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
295 "movaps", SSEPackedSingle>, VEX;
296 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
297 "movapd", SSEPackedDouble>, OpSize, VEX;
298 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
299 "movups", SSEPackedSingle>, VEX;
300 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
301 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
302 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
303 "movaps", SSEPackedSingle>, TB;
304 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
305 "movapd", SSEPackedDouble>, TB, OpSize;
306 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
307 "movups", SSEPackedSingle>, TB;
308 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
309 "movupd", SSEPackedDouble, 0>, TB, OpSize;
311 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
312 "movaps\t{$src, $dst|$dst, $src}",
313 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
314 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
315 "movapd\t{$src, $dst|$dst, $src}",
316 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
317 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
318 "movups\t{$src, $dst|$dst, $src}",
319 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
320 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
321 "movupd\t{$src, $dst|$dst, $src}",
322 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
323 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
324 "movaps\t{$src, $dst|$dst, $src}",
325 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
326 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
327 "movapd\t{$src, $dst|$dst, $src}",
328 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
329 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
330 "movups\t{$src, $dst|$dst, $src}",
331 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
332 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
333 "movupd\t{$src, $dst|$dst, $src}",
334 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
336 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
337 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
338 (VMOVUPSYmr addr:$dst, VR256:$src)>;
340 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
341 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
342 (VMOVUPDYmr addr:$dst, VR256:$src)>;
344 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
345 "movaps\t{$src, $dst|$dst, $src}",
346 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
347 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
348 "movapd\t{$src, $dst|$dst, $src}",
349 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
350 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
351 "movups\t{$src, $dst|$dst, $src}",
352 [(store (v4f32 VR128:$src), addr:$dst)]>;
353 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
354 "movupd\t{$src, $dst|$dst, $src}",
355 [(store (v2f64 VR128:$src), addr:$dst)]>;
357 // Intrinsic forms of MOVUPS/D load and store
358 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
359 (ins f128mem:$dst, VR128:$src),
360 "movups\t{$src, $dst|$dst, $src}",
361 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
362 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
363 (ins f128mem:$dst, VR128:$src),
364 "movupd\t{$src, $dst|$dst, $src}",
365 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
367 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
368 "movups\t{$src, $dst|$dst, $src}",
369 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
370 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
371 "movupd\t{$src, $dst|$dst, $src}",
372 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
374 // Move Low/High packed floating point values
375 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
376 PatFrag mov_frag, string base_opc,
378 def PSrm : PI<opc, MRMSrcMem,
379 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
380 !strconcat(base_opc, "s", asm_opr),
383 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
384 SSEPackedSingle>, TB;
386 def PDrm : PI<opc, MRMSrcMem,
387 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
388 !strconcat(base_opc, "d", asm_opr),
389 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
390 (scalar_to_vector (loadf64 addr:$src2)))))],
391 SSEPackedDouble>, TB, OpSize;
394 let AddedComplexity = 20 in {
395 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
396 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
397 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
398 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
400 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
401 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
402 "\t{$src2, $dst|$dst, $src2}">;
403 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
404 "\t{$src2, $dst|$dst, $src2}">;
407 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
408 "movlps\t{$src, $dst|$dst, $src}",
409 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
410 (iPTR 0))), addr:$dst)]>, VEX;
411 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
412 "movlpd\t{$src, $dst|$dst, $src}",
413 [(store (f64 (vector_extract (v2f64 VR128:$src),
414 (iPTR 0))), addr:$dst)]>, VEX;
415 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
416 "movlps\t{$src, $dst|$dst, $src}",
417 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
418 (iPTR 0))), addr:$dst)]>;
419 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
420 "movlpd\t{$src, $dst|$dst, $src}",
421 [(store (f64 (vector_extract (v2f64 VR128:$src),
422 (iPTR 0))), addr:$dst)]>;
424 // v2f64 extract element 1 is always custom lowered to unpack high to low
425 // and extract element 0 so the non-store version isn't too horrible.
426 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
427 "movhps\t{$src, $dst|$dst, $src}",
428 [(store (f64 (vector_extract
429 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
430 (undef)), (iPTR 0))), addr:$dst)]>,
432 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
433 "movhpd\t{$src, $dst|$dst, $src}",
434 [(store (f64 (vector_extract
435 (v2f64 (unpckh VR128:$src, (undef))),
436 (iPTR 0))), addr:$dst)]>,
438 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
439 "movhps\t{$src, $dst|$dst, $src}",
440 [(store (f64 (vector_extract
441 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
442 (undef)), (iPTR 0))), addr:$dst)]>;
443 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
444 "movhpd\t{$src, $dst|$dst, $src}",
445 [(store (f64 (vector_extract
446 (v2f64 (unpckh VR128:$src, (undef))),
447 (iPTR 0))), addr:$dst)]>;
449 let AddedComplexity = 20 in {
450 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
451 (ins VR128:$src1, VR128:$src2),
452 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
454 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
456 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
457 (ins VR128:$src1, VR128:$src2),
458 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
460 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
463 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
464 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
465 (ins VR128:$src1, VR128:$src2),
466 "movlhps\t{$src2, $dst|$dst, $src2}",
468 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
469 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
470 (ins VR128:$src1, VR128:$src2),
471 "movhlps\t{$src2, $dst|$dst, $src2}",
473 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
476 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
477 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
478 let AddedComplexity = 20 in {
479 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
480 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
481 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
482 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
485 //===----------------------------------------------------------------------===//
486 // SSE 1 & 2 - Conversion Instructions
487 //===----------------------------------------------------------------------===//
489 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
490 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
492 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
493 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
494 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
495 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
498 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
499 X86MemOperand x86memop, string asm> {
500 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
502 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
506 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
507 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
508 string asm, Domain d> {
509 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
510 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
511 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
512 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
515 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
516 X86MemOperand x86memop, string asm> {
517 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
518 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
519 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
520 (ins DstRC:$src1, x86memop:$src),
521 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
524 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
525 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
526 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
527 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
529 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
530 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
531 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
532 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
535 // The assembler can recognize rr 64-bit instructions by seeing a rxx
536 // register, but the same isn't true when only using memory operands,
537 // provide other assembly "l" and "q" forms to address this explicitly
538 // where appropriate to do so.
539 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
541 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
543 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
545 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
547 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
550 let Predicates = [HasAVX] in {
551 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
552 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
553 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
554 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
555 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
556 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
557 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
558 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
560 def : Pat<(f32 (sint_to_fp GR32:$src)),
561 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
562 def : Pat<(f32 (sint_to_fp GR64:$src)),
563 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
564 def : Pat<(f64 (sint_to_fp GR32:$src)),
565 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
566 def : Pat<(f64 (sint_to_fp GR64:$src)),
567 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
570 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
571 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
572 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
573 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
574 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
575 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
576 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
577 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
578 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
579 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
580 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
581 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
582 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
583 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
584 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
585 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
587 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
588 // and/or XMM operand(s).
590 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
591 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
593 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
594 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
595 [(set DstRC:$dst, (Int SrcRC:$src))]>;
596 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
597 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
598 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
601 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
602 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
603 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
604 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
606 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
607 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
608 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
609 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
610 (ins DstRC:$src1, x86memop:$src2),
612 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
613 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
614 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
617 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
618 f128mem, load, "cvtsd2si">, XD, VEX;
619 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
620 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
623 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
624 // Get rid of this hack or rename the intrinsics, there are several
625 // intructions that only match with the intrinsic form, why create duplicates
626 // to let them be recognized by the assembler?
627 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
628 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
629 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
630 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
631 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
632 f128mem, load, "cvtsd2si{l}">, XD;
633 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
634 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
637 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
638 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
639 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
640 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
642 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
643 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
644 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
645 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
648 let Constraints = "$src1 = $dst" in {
649 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
650 int_x86_sse_cvtsi2ss, i32mem, loadi32,
652 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
653 int_x86_sse_cvtsi642ss, i64mem, loadi64,
654 "cvtsi2ss{q}">, XS, REX_W;
655 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
656 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
658 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
659 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
660 "cvtsi2sd">, XD, REX_W;
665 // Aliases for intrinsics
666 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
667 f32mem, load, "cvttss2si">, XS, VEX;
668 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
669 int_x86_sse_cvttss2si64, f32mem, load,
670 "cvttss2si">, XS, VEX, VEX_W;
671 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
672 f128mem, load, "cvttsd2si">, XD, VEX;
673 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
674 int_x86_sse2_cvttsd2si64, f128mem, load,
675 "cvttsd2si">, XD, VEX, VEX_W;
676 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
677 f32mem, load, "cvttss2si">, XS;
678 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
679 int_x86_sse_cvttss2si64, f32mem, load,
680 "cvttss2si{q}">, XS, REX_W;
681 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
682 f128mem, load, "cvttsd2si">, XD;
683 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
684 int_x86_sse2_cvttsd2si64, f128mem, load,
685 "cvttsd2si{q}">, XD, REX_W;
687 let Pattern = []<dag> in {
688 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
689 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
690 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
691 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
693 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
694 "cvtdq2ps\t{$src, $dst|$dst, $src}",
695 SSEPackedSingle>, TB, VEX;
696 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
697 "cvtdq2ps\t{$src, $dst|$dst, $src}",
698 SSEPackedSingle>, TB, VEX;
701 let Pattern = []<dag> in {
702 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
703 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
704 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
705 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
706 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
707 "cvtdq2ps\t{$src, $dst|$dst, $src}",
708 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
711 let Predicates = [HasSSE1] in {
712 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
713 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
714 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
715 (CVTSS2SIrm addr:$src)>;
716 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
717 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
718 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
719 (CVTSS2SI64rm addr:$src)>;
722 let Predicates = [HasAVX] in {
723 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
724 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
725 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
726 (VCVTSS2SIrm addr:$src)>;
727 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
728 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
729 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
730 (VCVTSS2SI64rm addr:$src)>;
735 // Convert scalar double to scalar single
736 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
737 (ins FR64:$src1, FR64:$src2),
738 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
740 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
741 (ins FR64:$src1, f64mem:$src2),
742 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
743 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
744 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
747 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
748 "cvtsd2ss\t{$src, $dst|$dst, $src}",
749 [(set FR32:$dst, (fround FR64:$src))]>;
750 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
751 "cvtsd2ss\t{$src, $dst|$dst, $src}",
752 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
753 Requires<[HasSSE2, OptForSize]>;
755 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
756 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
758 let Constraints = "$src1 = $dst" in
759 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
760 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
762 // Convert scalar single to scalar double
763 // SSE2 instructions with XS prefix
764 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
765 (ins FR32:$src1, FR32:$src2),
766 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
767 []>, XS, Requires<[HasAVX]>, VEX_4V;
768 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
769 (ins FR32:$src1, f32mem:$src2),
770 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
771 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
773 let Predicates = [HasAVX] in {
774 def : Pat<(f64 (fextend FR32:$src)),
775 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
776 def : Pat<(fextend (loadf32 addr:$src)),
777 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
778 def : Pat<(extloadf32 addr:$src),
779 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
782 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
783 "cvtss2sd\t{$src, $dst|$dst, $src}",
784 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
786 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
787 "cvtss2sd\t{$src, $dst|$dst, $src}",
788 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
789 Requires<[HasSSE2, OptForSize]>;
791 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
792 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
793 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
794 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
795 VR128:$src2))]>, XS, VEX_4V,
797 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
798 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
799 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
800 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
801 (load addr:$src2)))]>, XS, VEX_4V,
803 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
804 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
805 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
806 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
807 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
810 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
811 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
812 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
813 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
814 (load addr:$src2)))]>, XS,
818 def : Pat<(extloadf32 addr:$src),
819 (CVTSS2SDrr (MOVSSrm addr:$src))>,
820 Requires<[HasSSE2, OptForSpeed]>;
822 // Convert doubleword to packed single/double fp
823 // SSE2 instructions without OpSize prefix
824 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
825 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
826 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
827 TB, VEX, Requires<[HasAVX]>;
828 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
829 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
830 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
831 (bitconvert (memopv2i64 addr:$src))))]>,
832 TB, VEX, Requires<[HasAVX]>;
833 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
834 "cvtdq2ps\t{$src, $dst|$dst, $src}",
835 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
836 TB, Requires<[HasSSE2]>;
837 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
838 "cvtdq2ps\t{$src, $dst|$dst, $src}",
839 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
840 (bitconvert (memopv2i64 addr:$src))))]>,
841 TB, Requires<[HasSSE2]>;
843 // FIXME: why the non-intrinsic version is described as SSE3?
844 // SSE2 instructions with XS prefix
845 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
846 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
847 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
848 XS, VEX, Requires<[HasAVX]>;
849 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
850 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
851 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
852 (bitconvert (memopv2i64 addr:$src))))]>,
853 XS, VEX, Requires<[HasAVX]>;
854 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
855 "cvtdq2pd\t{$src, $dst|$dst, $src}",
856 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
857 XS, Requires<[HasSSE2]>;
858 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
859 "cvtdq2pd\t{$src, $dst|$dst, $src}",
860 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
861 (bitconvert (memopv2i64 addr:$src))))]>,
862 XS, Requires<[HasSSE2]>;
865 // Convert packed single/double fp to doubleword
866 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
867 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
868 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
869 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
870 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
871 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
872 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
873 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
874 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
875 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
876 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
877 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
879 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
880 "cvtps2dq\t{$src, $dst|$dst, $src}",
881 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
883 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
885 "cvtps2dq\t{$src, $dst|$dst, $src}",
886 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
887 (memop addr:$src)))]>, VEX;
888 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
889 "cvtps2dq\t{$src, $dst|$dst, $src}",
890 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
891 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
892 "cvtps2dq\t{$src, $dst|$dst, $src}",
893 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
894 (memop addr:$src)))]>;
896 // SSE2 packed instructions with XD prefix
897 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
898 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
899 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
900 XD, VEX, Requires<[HasAVX]>;
901 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
902 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
903 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
904 (memop addr:$src)))]>,
905 XD, VEX, Requires<[HasAVX]>;
906 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
907 "cvtpd2dq\t{$src, $dst|$dst, $src}",
908 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
909 XD, Requires<[HasSSE2]>;
910 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
911 "cvtpd2dq\t{$src, $dst|$dst, $src}",
912 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
913 (memop addr:$src)))]>,
914 XD, Requires<[HasSSE2]>;
917 // Convert with truncation packed single/double fp to doubleword
918 // SSE2 packed instructions with XS prefix
919 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
920 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
921 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
922 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
923 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
924 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
925 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
926 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
927 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
928 "cvttps2dq\t{$src, $dst|$dst, $src}",
930 (int_x86_sse2_cvttps2dq VR128:$src))]>;
931 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
932 "cvttps2dq\t{$src, $dst|$dst, $src}",
934 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
936 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
937 "vcvttps2dq\t{$src, $dst|$dst, $src}",
939 (int_x86_sse2_cvttps2dq VR128:$src))]>,
940 XS, VEX, Requires<[HasAVX]>;
941 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
942 "vcvttps2dq\t{$src, $dst|$dst, $src}",
943 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
944 (memop addr:$src)))]>,
945 XS, VEX, Requires<[HasAVX]>;
947 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
948 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
949 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
950 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
952 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
953 (Int_VCVTDQ2PSrr VR128:$src)>, Requires<[HasAVX]>;
954 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
955 (VCVTTPS2DQrr VR128:$src)>, Requires<[HasAVX]>;
956 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
957 (VCVTDQ2PSYrr VR256:$src)>, Requires<[HasAVX]>;
958 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
959 (VCVTTPS2DQYrr VR256:$src)>, Requires<[HasAVX]>;
961 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
963 "cvttpd2dq\t{$src, $dst|$dst, $src}",
964 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
966 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
968 "cvttpd2dq\t{$src, $dst|$dst, $src}",
969 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
970 (memop addr:$src)))]>, VEX;
971 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
972 "cvttpd2dq\t{$src, $dst|$dst, $src}",
973 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
974 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
975 "cvttpd2dq\t{$src, $dst|$dst, $src}",
976 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
977 (memop addr:$src)))]>;
979 // The assembler can recognize rr 256-bit instructions by seeing a ymm
980 // register, but the same isn't true when using memory operands instead.
981 // Provide other assembly rr and rm forms to address this explicitly.
982 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
983 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
984 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
985 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
988 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
989 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
990 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
991 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
994 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
995 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
996 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
997 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
999 // Convert packed single to packed double
1000 let Predicates = [HasAVX] in {
1001 // SSE2 instructions without OpSize prefix
1002 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1003 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1004 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1005 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1006 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1007 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1008 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1009 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1011 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1012 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1013 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1014 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1016 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1017 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1018 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1019 VEX, Requires<[HasAVX]>;
1020 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1021 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1022 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1023 (load addr:$src)))]>,
1024 VEX, Requires<[HasAVX]>;
1025 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1026 "cvtps2pd\t{$src, $dst|$dst, $src}",
1027 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1028 TB, Requires<[HasSSE2]>;
1029 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1030 "cvtps2pd\t{$src, $dst|$dst, $src}",
1031 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1032 (load addr:$src)))]>,
1033 TB, Requires<[HasSSE2]>;
1035 // Convert packed double to packed single
1036 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1037 // register, but the same isn't true when using memory operands instead.
1038 // Provide other assembly rr and rm forms to address this explicitly.
1039 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1040 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1041 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1042 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1045 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1046 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1047 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1048 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1051 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1052 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1053 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1054 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1055 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1056 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1057 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1058 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1061 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1062 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1063 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1064 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1066 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1067 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1068 (memop addr:$src)))]>;
1069 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1070 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1071 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1072 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1073 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1074 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1075 (memop addr:$src)))]>;
1077 // AVX 256-bit register conversion intrinsics
1078 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1079 // whenever possible to avoid declaring two versions of each one.
1080 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1081 (VCVTDQ2PSYrr VR256:$src)>;
1082 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1083 (VCVTDQ2PSYrm addr:$src)>;
1085 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1086 (VCVTPD2PSYrr VR256:$src)>;
1087 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1088 (VCVTPD2PSYrm addr:$src)>;
1090 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1091 (VCVTPS2DQYrr VR256:$src)>;
1092 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1093 (VCVTPS2DQYrm addr:$src)>;
1095 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1096 (VCVTPS2PDYrr VR128:$src)>;
1097 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1098 (VCVTPS2PDYrm addr:$src)>;
1100 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1101 (VCVTTPD2DQYrr VR256:$src)>;
1102 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1103 (VCVTTPD2DQYrm addr:$src)>;
1105 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1106 (VCVTTPS2DQYrr VR256:$src)>;
1107 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1108 (VCVTTPS2DQYrm addr:$src)>;
1110 // Match fround and fextend for 128/256-bit conversions
1111 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1112 (VCVTPD2PSYrr VR256:$src)>;
1113 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1114 (VCVTPD2PSYrm addr:$src)>;
1116 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1117 (VCVTPS2PDYrr VR128:$src)>;
1118 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1119 (VCVTPS2PDYrm addr:$src)>;
1121 //===----------------------------------------------------------------------===//
1122 // SSE 1 & 2 - Compare Instructions
1123 //===----------------------------------------------------------------------===//
1125 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1126 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1127 string asm, string asm_alt> {
1128 let isAsmParserOnly = 1 in {
1129 def rr : SIi8<0xC2, MRMSrcReg,
1130 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1133 def rm : SIi8<0xC2, MRMSrcMem,
1134 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1138 // Accept explicit immediate argument form instead of comparison code.
1139 def rr_alt : SIi8<0xC2, MRMSrcReg,
1140 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1143 def rm_alt : SIi8<0xC2, MRMSrcMem,
1144 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1148 let neverHasSideEffects = 1 in {
1149 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1150 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1151 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1153 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1154 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1155 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1159 let Constraints = "$src1 = $dst" in {
1160 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
1161 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
1162 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1163 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
1164 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
1165 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
1166 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1167 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
1168 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
1169 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
1170 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1171 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
1172 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
1173 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
1174 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1175 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
1177 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1178 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
1179 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
1180 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1181 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
1182 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
1183 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1184 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
1185 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1186 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1187 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
1188 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1189 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1192 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1193 Intrinsic Int, string asm> {
1194 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1195 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1196 [(set VR128:$dst, (Int VR128:$src1,
1197 VR128:$src, imm:$cc))]>;
1198 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1199 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1200 [(set VR128:$dst, (Int VR128:$src1,
1201 (load addr:$src), imm:$cc))]>;
1204 // Aliases to match intrinsics which expect XMM operand(s).
1205 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1206 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1208 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1209 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1211 let Constraints = "$src1 = $dst" in {
1212 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1213 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1214 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1215 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1219 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1220 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1221 ValueType vt, X86MemOperand x86memop,
1222 PatFrag ld_frag, string OpcodeStr, Domain d> {
1223 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1224 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1225 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1226 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1227 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1228 [(set EFLAGS, (OpNode (vt RC:$src1),
1229 (ld_frag addr:$src2)))], d>;
1232 let Defs = [EFLAGS] in {
1233 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1234 "ucomiss", SSEPackedSingle>, VEX;
1235 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1236 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1237 let Pattern = []<dag> in {
1238 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1239 "comiss", SSEPackedSingle>, VEX;
1240 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1241 "comisd", SSEPackedDouble>, OpSize, VEX;
1244 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1245 load, "ucomiss", SSEPackedSingle>, VEX;
1246 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1247 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1249 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1250 load, "comiss", SSEPackedSingle>, VEX;
1251 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1252 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1253 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1254 "ucomiss", SSEPackedSingle>, TB;
1255 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1256 "ucomisd", SSEPackedDouble>, TB, OpSize;
1258 let Pattern = []<dag> in {
1259 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1260 "comiss", SSEPackedSingle>, TB;
1261 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1262 "comisd", SSEPackedDouble>, TB, OpSize;
1265 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1266 load, "ucomiss", SSEPackedSingle>, TB;
1267 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1268 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1270 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1271 "comiss", SSEPackedSingle>, TB;
1272 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1273 "comisd", SSEPackedDouble>, TB, OpSize;
1274 } // Defs = [EFLAGS]
1276 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1277 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1278 Intrinsic Int, string asm, string asm_alt,
1280 let isAsmParserOnly = 1 in {
1281 def rri : PIi8<0xC2, MRMSrcReg,
1282 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1283 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1284 def rmi : PIi8<0xC2, MRMSrcMem,
1285 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1286 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1289 // Accept explicit immediate argument form instead of comparison code.
1290 def rri_alt : PIi8<0xC2, MRMSrcReg,
1291 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1293 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1294 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1298 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1299 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1300 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1301 SSEPackedSingle>, VEX_4V;
1302 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1303 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1304 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1305 SSEPackedDouble>, OpSize, VEX_4V;
1306 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1307 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1308 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1309 SSEPackedSingle>, VEX_4V;
1310 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1311 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1312 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1313 SSEPackedDouble>, OpSize, VEX_4V;
1314 let Constraints = "$src1 = $dst" in {
1315 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1316 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1317 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1318 SSEPackedSingle>, TB;
1319 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1320 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1321 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1322 SSEPackedDouble>, TB, OpSize;
1325 let Predicates = [HasSSE1] in {
1326 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1327 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1328 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1329 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1332 let Predicates = [HasSSE2] in {
1333 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1334 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1335 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1336 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1339 let Predicates = [HasAVX] in {
1340 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1341 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1342 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1343 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1344 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1345 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1346 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1347 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1349 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
1350 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
1351 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
1352 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
1353 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
1354 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
1355 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
1356 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
1359 //===----------------------------------------------------------------------===//
1360 // SSE 1 & 2 - Shuffle Instructions
1361 //===----------------------------------------------------------------------===//
1363 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1364 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1365 ValueType vt, string asm, PatFrag mem_frag,
1366 Domain d, bit IsConvertibleToThreeAddress = 0> {
1367 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1368 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1369 [(set RC:$dst, (vt (shufp:$src3
1370 RC:$src1, (mem_frag addr:$src2))))], d>;
1371 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1372 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1373 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1375 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1378 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1379 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1380 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
1381 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1382 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1383 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
1384 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1385 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1386 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1387 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1388 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1389 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1391 let Constraints = "$src1 = $dst" in {
1392 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1393 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1394 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1396 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1397 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1398 memopv2f64, SSEPackedDouble>, TB, OpSize;
1401 //===----------------------------------------------------------------------===//
1402 // SSE 1 & 2 - Unpack Instructions
1403 //===----------------------------------------------------------------------===//
1405 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1406 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1407 PatFrag mem_frag, RegisterClass RC,
1408 X86MemOperand x86memop, string asm,
1410 def rr : PI<opc, MRMSrcReg,
1411 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1413 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1414 def rm : PI<opc, MRMSrcMem,
1415 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1417 (vt (OpNode RC:$src1,
1418 (mem_frag addr:$src2))))], d>;
1421 let AddedComplexity = 10 in {
1422 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1423 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1424 SSEPackedSingle>, VEX_4V;
1425 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1426 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1427 SSEPackedDouble>, OpSize, VEX_4V;
1428 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1429 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1430 SSEPackedSingle>, VEX_4V;
1431 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1432 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1433 SSEPackedDouble>, OpSize, VEX_4V;
1435 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1436 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1437 SSEPackedSingle>, VEX_4V;
1438 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1439 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1440 SSEPackedDouble>, OpSize, VEX_4V;
1441 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1442 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1443 SSEPackedSingle>, VEX_4V;
1444 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1445 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1446 SSEPackedDouble>, OpSize, VEX_4V;
1448 let Constraints = "$src1 = $dst" in {
1449 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1450 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1451 SSEPackedSingle>, TB;
1452 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1453 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1454 SSEPackedDouble>, TB, OpSize;
1455 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1456 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1457 SSEPackedSingle>, TB;
1458 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1459 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1460 SSEPackedDouble>, TB, OpSize;
1461 } // Constraints = "$src1 = $dst"
1462 } // AddedComplexity
1464 //===----------------------------------------------------------------------===//
1465 // SSE 1 & 2 - Extract Floating-Point Sign mask
1466 //===----------------------------------------------------------------------===//
1468 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1469 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1471 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1472 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1473 [(set GR32:$dst, (Int RC:$src))], d>;
1474 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1475 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1479 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1480 "movmskps", SSEPackedSingle>, VEX;
1481 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1482 "movmskpd", SSEPackedDouble>, OpSize,
1484 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1485 "movmskps", SSEPackedSingle>, VEX;
1486 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1487 "movmskpd", SSEPackedDouble>, OpSize,
1489 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1490 SSEPackedSingle>, TB;
1491 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1492 SSEPackedDouble>, TB, OpSize;
1495 def MOVMSKPDrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1496 "movmskpd\t{$src, $dst|$dst, $src}",
1497 [(set GR32:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1498 def MOVMSKPDrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1499 "movmskpd\t{$src, $dst|$dst, $src}",
1500 [(set GR64:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1501 def MOVMSKPSrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
1502 "movmskps\t{$src, $dst|$dst, $src}",
1503 [(set GR32:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1504 def MOVMSKPSrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1505 "movmskps\t{$src, $dst|$dst, $src}",
1506 [(set GR64:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1509 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1510 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1511 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1512 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1514 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1515 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1516 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1517 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1520 //===----------------------------------------------------------------------===//
1521 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1522 //===----------------------------------------------------------------------===//
1524 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1525 // names that start with 'Fs'.
1527 // Alias instructions that map fld0 to pxor for sse.
1528 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1529 canFoldAsLoad = 1 in {
1530 // FIXME: Set encoding to pseudo!
1531 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1532 [(set FR32:$dst, fp32imm0)]>,
1533 Requires<[HasSSE1]>, TB, OpSize;
1534 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1535 [(set FR64:$dst, fpimm0)]>,
1536 Requires<[HasSSE2]>, TB, OpSize;
1537 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1538 [(set FR32:$dst, fp32imm0)]>,
1539 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1540 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1541 [(set FR64:$dst, fpimm0)]>,
1542 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1545 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1546 // bits are disregarded.
1547 let neverHasSideEffects = 1 in {
1548 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1549 "movaps\t{$src, $dst|$dst, $src}", []>;
1550 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1551 "movapd\t{$src, $dst|$dst, $src}", []>;
1554 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1555 // bits are disregarded.
1556 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1557 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1558 "movaps\t{$src, $dst|$dst, $src}",
1559 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1560 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1561 "movapd\t{$src, $dst|$dst, $src}",
1562 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1565 //===----------------------------------------------------------------------===//
1566 // SSE 1 & 2 - Logical Instructions
1567 //===----------------------------------------------------------------------===//
1569 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1571 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1573 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1574 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1576 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1577 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1579 let Constraints = "$src1 = $dst" in {
1580 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1581 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1583 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1584 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1588 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1589 let mayLoad = 0 in {
1590 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1591 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1592 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1595 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1596 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1598 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1600 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1602 let Pattern = []<dag> in {
1603 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1604 !strconcat(OpcodeStr, "ps"), f128mem,
1605 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1606 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1607 (memopv2i64 addr:$src2)))], 0>, VEX_4V;
1609 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1610 !strconcat(OpcodeStr, "pd"), f128mem,
1611 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1612 (bc_v2i64 (v2f64 VR128:$src2))))],
1613 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1614 (memopv2i64 addr:$src2)))], 0>,
1617 let Constraints = "$src1 = $dst" in {
1618 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1619 !strconcat(OpcodeStr, "ps"), f128mem,
1620 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1621 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1622 (memopv2i64 addr:$src2)))]>, TB;
1624 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1625 !strconcat(OpcodeStr, "pd"), f128mem,
1626 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1627 (bc_v2i64 (v2f64 VR128:$src2))))],
1628 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1629 (memopv2i64 addr:$src2)))]>, TB, OpSize;
1633 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1635 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
1637 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1638 !strconcat(OpcodeStr, "ps"), f256mem,
1639 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
1640 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
1641 (memopv4i64 addr:$src2)))], 0>, VEX_4V;
1643 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1644 !strconcat(OpcodeStr, "pd"), f256mem,
1645 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1646 (bc_v4i64 (v4f64 VR256:$src2))))],
1647 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1648 (memopv4i64 addr:$src2)))], 0>,
1652 // AVX 256-bit packed logical ops forms
1653 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
1654 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
1655 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
1656 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
1658 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1659 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1660 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1661 let isCommutable = 0 in
1662 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
1664 //===----------------------------------------------------------------------===//
1665 // SSE 1 & 2 - Arithmetic Instructions
1666 //===----------------------------------------------------------------------===//
1668 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1671 /// In addition, we also have a special variant of the scalar form here to
1672 /// represent the associated intrinsic operation. This form is unlike the
1673 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1674 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1676 /// These three forms can each be reg+reg or reg+mem.
1679 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1681 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1683 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1684 OpNode, FR32, f32mem, Is2Addr>, XS;
1685 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1686 OpNode, FR64, f64mem, Is2Addr>, XD;
1689 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1691 let mayLoad = 0 in {
1692 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1693 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1694 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1695 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1699 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1701 let mayLoad = 0 in {
1702 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1703 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1704 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1705 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1709 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1711 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1712 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1713 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1714 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1717 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1719 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1720 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1721 SSEPackedSingle, Is2Addr>, TB;
1723 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1724 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1725 SSEPackedDouble, Is2Addr>, TB, OpSize;
1728 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1729 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1730 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1731 SSEPackedSingle, 0>, TB;
1733 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1734 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1735 SSEPackedDouble, 0>, TB, OpSize;
1738 // Binary Arithmetic instructions
1739 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1740 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1741 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1742 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1743 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1744 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1745 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1746 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1748 let isCommutable = 0 in {
1749 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1750 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1751 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1752 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1753 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1754 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1755 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1756 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1757 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1758 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1759 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1760 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1761 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1762 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1763 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1764 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1765 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1766 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1767 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1768 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1771 let Constraints = "$src1 = $dst" in {
1772 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1773 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1774 basic_sse12_fp_binop_s_int<0x58, "add">;
1775 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1776 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1777 basic_sse12_fp_binop_s_int<0x59, "mul">;
1779 let isCommutable = 0 in {
1780 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1781 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1782 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1783 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1784 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1785 basic_sse12_fp_binop_s_int<0x5E, "div">;
1786 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1787 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1788 basic_sse12_fp_binop_s_int<0x5F, "max">,
1789 basic_sse12_fp_binop_p_int<0x5F, "max">;
1790 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1791 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1792 basic_sse12_fp_binop_s_int<0x5D, "min">,
1793 basic_sse12_fp_binop_p_int<0x5D, "min">;
1798 /// In addition, we also have a special variant of the scalar form here to
1799 /// represent the associated intrinsic operation. This form is unlike the
1800 /// plain scalar form, in that it takes an entire vector (instead of a
1801 /// scalar) and leaves the top elements undefined.
1803 /// And, we have a special variant form for a full-vector intrinsic form.
1805 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1806 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1807 SDNode OpNode, Intrinsic F32Int> {
1808 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1809 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1810 [(set FR32:$dst, (OpNode FR32:$src))]>;
1811 // For scalar unary operations, fold a load into the operation
1812 // only in OptForSize mode. It eliminates an instruction, but it also
1813 // eliminates a whole-register clobber (the load), so it introduces a
1814 // partial register update condition.
1815 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1816 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1817 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1818 Requires<[HasSSE1, OptForSize]>;
1819 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1820 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1821 [(set VR128:$dst, (F32Int VR128:$src))]>;
1822 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1823 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1824 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1827 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1828 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1829 SDNode OpNode, Intrinsic F32Int> {
1830 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1831 !strconcat(OpcodeStr,
1832 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1833 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1834 !strconcat(OpcodeStr,
1835 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1836 []>, XS, Requires<[HasAVX, OptForSize]>;
1837 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1838 !strconcat(OpcodeStr,
1839 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1840 [(set VR128:$dst, (F32Int VR128:$src))]>;
1841 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1842 !strconcat(OpcodeStr,
1843 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1844 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1847 /// sse1_fp_unop_p - SSE1 unops in packed form.
1848 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1849 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1850 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1851 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1852 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1853 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1854 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1857 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1858 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1859 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1860 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1861 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1862 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1863 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1864 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1867 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1868 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1869 Intrinsic V4F32Int> {
1870 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1871 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1872 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1873 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1874 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1875 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1878 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1879 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1880 Intrinsic V4F32Int> {
1881 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1882 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1883 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1884 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1885 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1886 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1889 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1890 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1891 SDNode OpNode, Intrinsic F64Int> {
1892 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1893 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1894 [(set FR64:$dst, (OpNode FR64:$src))]>;
1895 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1896 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1897 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1898 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1899 Requires<[HasSSE2, OptForSize]>;
1900 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1901 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1902 [(set VR128:$dst, (F64Int VR128:$src))]>;
1903 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1904 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1905 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1908 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1909 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1910 SDNode OpNode, Intrinsic F64Int> {
1911 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1912 !strconcat(OpcodeStr,
1913 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1914 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1915 (ins FR64:$src1, f64mem:$src2),
1916 !strconcat(OpcodeStr,
1917 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1918 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1919 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1920 [(set VR128:$dst, (F64Int VR128:$src))]>;
1921 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1922 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1923 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1926 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1927 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1929 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1930 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1931 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1932 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1933 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1934 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1937 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1938 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1939 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1940 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1941 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1942 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1943 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1944 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1947 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1948 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1949 Intrinsic V2F64Int> {
1950 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1951 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1952 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1953 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1954 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1955 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1958 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
1959 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1960 Intrinsic V2F64Int> {
1961 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1962 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1963 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1964 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1965 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1966 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1969 let Predicates = [HasAVX] in {
1971 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
1972 sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1975 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1976 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1977 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1978 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1979 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
1980 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
1981 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
1982 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
1985 // Reciprocal approximations. Note that these typically require refinement
1986 // in order to obtain suitable precision.
1987 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
1988 int_x86_sse_rsqrt_ss>, VEX_4V;
1989 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
1990 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
1991 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
1992 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
1994 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
1996 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
1997 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
1998 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
1999 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
2002 def : Pat<(f32 (fsqrt FR32:$src)),
2003 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2004 def : Pat<(f64 (fsqrt FR64:$src)),
2005 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
2006 def : Pat<(f64 (fsqrt (load addr:$src))),
2007 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
2008 Requires<[HasAVX, OptForSize]>;
2009 def : Pat<(f32 (fsqrt (load addr:$src))),
2010 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2011 Requires<[HasAVX, OptForSize]>;
2014 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
2015 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
2016 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
2017 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
2018 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
2019 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
2021 // Reciprocal approximations. Note that these typically require refinement
2022 // in order to obtain suitable precision.
2023 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
2024 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
2025 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
2026 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2027 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
2028 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
2030 // There is no f64 version of the reciprocal approximation instructions.
2032 //===----------------------------------------------------------------------===//
2033 // SSE 1 & 2 - Non-temporal stores
2034 //===----------------------------------------------------------------------===//
2036 let AddedComplexity = 400 in { // Prefer non-temporal versions
2037 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
2038 (ins f128mem:$dst, VR128:$src),
2039 "movntps\t{$src, $dst|$dst, $src}",
2040 [(alignednontemporalstore (v4f32 VR128:$src),
2042 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
2043 (ins f128mem:$dst, VR128:$src),
2044 "movntpd\t{$src, $dst|$dst, $src}",
2045 [(alignednontemporalstore (v2f64 VR128:$src),
2047 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
2048 (ins f128mem:$dst, VR128:$src),
2049 "movntdq\t{$src, $dst|$dst, $src}",
2050 [(alignednontemporalstore (v2f64 VR128:$src),
2053 let ExeDomain = SSEPackedInt in
2054 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
2055 (ins f128mem:$dst, VR128:$src),
2056 "movntdq\t{$src, $dst|$dst, $src}",
2057 [(alignednontemporalstore (v4f32 VR128:$src),
2060 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2061 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
2063 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
2064 (ins f256mem:$dst, VR256:$src),
2065 "movntps\t{$src, $dst|$dst, $src}",
2066 [(alignednontemporalstore (v8f32 VR256:$src),
2068 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
2069 (ins f256mem:$dst, VR256:$src),
2070 "movntpd\t{$src, $dst|$dst, $src}",
2071 [(alignednontemporalstore (v4f64 VR256:$src),
2073 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
2074 (ins f256mem:$dst, VR256:$src),
2075 "movntdq\t{$src, $dst|$dst, $src}",
2076 [(alignednontemporalstore (v4f64 VR256:$src),
2078 let ExeDomain = SSEPackedInt in
2079 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
2080 (ins f256mem:$dst, VR256:$src),
2081 "movntdq\t{$src, $dst|$dst, $src}",
2082 [(alignednontemporalstore (v8f32 VR256:$src),
2086 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
2087 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
2088 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
2089 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
2090 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
2091 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
2093 let AddedComplexity = 400 in { // Prefer non-temporal versions
2094 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2095 "movntps\t{$src, $dst|$dst, $src}",
2096 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2097 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2098 "movntpd\t{$src, $dst|$dst, $src}",
2099 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2101 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2102 "movntdq\t{$src, $dst|$dst, $src}",
2103 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2105 let ExeDomain = SSEPackedInt in
2106 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2107 "movntdq\t{$src, $dst|$dst, $src}",
2108 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2110 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2111 (MOVNTDQmr addr:$dst, VR128:$src)>;
2113 // There is no AVX form for instructions below this point
2114 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2115 "movnti{l}\t{$src, $dst|$dst, $src}",
2116 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2117 TB, Requires<[HasSSE2]>;
2118 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2119 "movnti{q}\t{$src, $dst|$dst, $src}",
2120 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2121 TB, Requires<[HasSSE2]>;
2124 //===----------------------------------------------------------------------===//
2125 // SSE 1 & 2 - Misc Instructions (No AVX form)
2126 //===----------------------------------------------------------------------===//
2128 // Prefetch intrinsic.
2129 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2130 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
2131 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2132 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
2133 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2134 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
2135 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2136 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
2138 // Load, store, and memory fence
2139 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2140 TB, Requires<[HasSSE1]>;
2141 def : Pat<(X86SFence), (SFENCE)>;
2143 // Alias instructions that map zero vector to pxor / xorp* for sse.
2144 // We set canFoldAsLoad because this can be converted to a constant-pool
2145 // load of an all-zeros value if folding it would be beneficial.
2146 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2147 // JIT implementation, it does not expand the instructions below like
2148 // X86MCInstLower does.
2149 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2150 isCodeGenOnly = 1 in {
2151 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2152 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2153 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2154 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2155 let ExeDomain = SSEPackedInt in
2156 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2157 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2160 // The same as done above but for AVX. The 128-bit versions are the
2161 // same, but re-encoded. The 256-bit does not support PI version, and
2162 // doesn't need it because on sandy bridge the register is set to zero
2163 // at the rename stage without using any execution unit, so SET0PSY
2164 // and SET0PDY can be used for vector int instructions without penalty
2165 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2166 // JIT implementatioan, it does not expand the instructions below like
2167 // X86MCInstLower does.
2168 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2169 isCodeGenOnly = 1, Predicates = [HasAVX] in {
2170 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2171 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
2172 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2173 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
2174 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2175 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
2176 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2177 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
2178 let ExeDomain = SSEPackedInt in
2179 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2180 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2183 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2184 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2185 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2187 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2188 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2190 // AVX has no support for 256-bit integer instructions, but since the 128-bit
2191 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
2192 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
2193 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
2194 (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
2196 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
2197 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
2198 (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
2200 //===----------------------------------------------------------------------===//
2201 // SSE 1 & 2 - Load/Store XCSR register
2202 //===----------------------------------------------------------------------===//
2204 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2205 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2206 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2207 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2209 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2210 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2211 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2212 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2214 //===---------------------------------------------------------------------===//
2215 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2216 //===---------------------------------------------------------------------===//
2218 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2220 let neverHasSideEffects = 1 in {
2221 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2222 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2223 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2224 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2226 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2227 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2228 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2229 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2231 let canFoldAsLoad = 1, mayLoad = 1 in {
2232 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2233 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2234 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2235 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2236 let Predicates = [HasAVX] in {
2237 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2238 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2239 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2240 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2244 let mayStore = 1 in {
2245 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2246 (ins i128mem:$dst, VR128:$src),
2247 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2248 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2249 (ins i256mem:$dst, VR256:$src),
2250 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2251 let Predicates = [HasAVX] in {
2252 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2253 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2254 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2255 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2259 let neverHasSideEffects = 1 in
2260 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2261 "movdqa\t{$src, $dst|$dst, $src}", []>;
2263 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2264 "movdqu\t{$src, $dst|$dst, $src}",
2265 []>, XS, Requires<[HasSSE2]>;
2267 let canFoldAsLoad = 1, mayLoad = 1 in {
2268 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2269 "movdqa\t{$src, $dst|$dst, $src}",
2270 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2271 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2272 "movdqu\t{$src, $dst|$dst, $src}",
2273 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2274 XS, Requires<[HasSSE2]>;
2277 let mayStore = 1 in {
2278 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2279 "movdqa\t{$src, $dst|$dst, $src}",
2280 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2281 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2282 "movdqu\t{$src, $dst|$dst, $src}",
2283 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2284 XS, Requires<[HasSSE2]>;
2287 // Intrinsic forms of MOVDQU load and store
2288 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2289 "vmovdqu\t{$src, $dst|$dst, $src}",
2290 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2291 XS, VEX, Requires<[HasAVX]>;
2293 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2294 "movdqu\t{$src, $dst|$dst, $src}",
2295 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2296 XS, Requires<[HasSSE2]>;
2298 } // ExeDomain = SSEPackedInt
2300 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2301 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2302 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2304 //===---------------------------------------------------------------------===//
2305 // SSE2 - Packed Integer Arithmetic Instructions
2306 //===---------------------------------------------------------------------===//
2308 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2310 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2311 bit IsCommutable = 0, bit Is2Addr = 1> {
2312 let isCommutable = IsCommutable in
2313 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2314 (ins VR128:$src1, VR128:$src2),
2316 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2318 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2319 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2320 (ins VR128:$src1, i128mem:$src2),
2322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2324 [(set VR128:$dst, (IntId VR128:$src1,
2325 (bitconvert (memopv2i64 addr:$src2))))]>;
2328 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2329 string OpcodeStr, Intrinsic IntId,
2330 Intrinsic IntId2, bit Is2Addr = 1> {
2331 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2332 (ins VR128:$src1, VR128:$src2),
2334 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2335 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2336 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2337 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2338 (ins VR128:$src1, i128mem:$src2),
2340 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2341 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2342 [(set VR128:$dst, (IntId VR128:$src1,
2343 (bitconvert (memopv2i64 addr:$src2))))]>;
2344 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2345 (ins VR128:$src1, i32i8imm:$src2),
2347 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2348 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2349 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2352 /// PDI_binop_rm - Simple SSE2 binary operator.
2353 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2354 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2355 let isCommutable = IsCommutable in
2356 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2357 (ins VR128:$src1, VR128:$src2),
2359 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2360 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2361 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2362 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2363 (ins VR128:$src1, i128mem:$src2),
2365 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2366 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2367 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2368 (bitconvert (memopv2i64 addr:$src2)))))]>;
2371 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2373 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2374 /// to collapse (bitconvert VT to VT) into its operand.
2376 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2377 bit IsCommutable = 0, bit Is2Addr = 1> {
2378 let isCommutable = IsCommutable in
2379 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2380 (ins VR128:$src1, VR128:$src2),
2382 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2383 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2384 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2385 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2386 (ins VR128:$src1, i128mem:$src2),
2388 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2389 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2390 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2393 } // ExeDomain = SSEPackedInt
2395 // 128-bit Integer Arithmetic
2397 let Predicates = [HasAVX] in {
2398 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2399 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2400 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2401 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2402 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2403 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2404 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2405 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2406 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2409 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2411 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2413 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2415 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2417 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2419 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2421 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2423 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2425 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2427 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2429 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2431 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2433 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2435 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2437 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2439 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2441 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2443 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2445 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2449 let Constraints = "$src1 = $dst" in {
2450 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2451 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2452 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2453 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2454 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2455 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2456 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2457 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2458 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2461 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2462 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2463 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2464 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2465 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2466 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2467 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2468 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2469 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2470 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2471 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2472 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2473 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2474 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2475 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2476 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2477 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2478 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2479 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2481 } // Constraints = "$src1 = $dst"
2483 //===---------------------------------------------------------------------===//
2484 // SSE2 - Packed Integer Logical Instructions
2485 //===---------------------------------------------------------------------===//
2487 let Predicates = [HasAVX] in {
2488 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2489 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2491 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2492 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2494 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2495 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2498 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2499 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2501 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2502 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2504 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2505 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2508 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2509 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2511 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2512 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2515 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2516 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2517 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2519 let ExeDomain = SSEPackedInt in {
2520 let neverHasSideEffects = 1 in {
2521 // 128-bit logical shifts.
2522 def VPSLLDQri : PDIi8<0x73, MRM7r,
2523 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2524 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2526 def VPSRLDQri : PDIi8<0x73, MRM3r,
2527 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2528 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2530 // PSRADQri doesn't exist in SSE[1-3].
2532 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2533 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2534 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2535 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2536 VR128:$src2)))]>, VEX_4V;
2538 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2539 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2540 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2541 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2542 (memopv2i64 addr:$src2))))]>,
2547 let Constraints = "$src1 = $dst" in {
2548 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2549 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2550 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2551 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2552 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2553 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2555 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2556 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2557 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2558 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2559 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2560 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2562 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2563 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2564 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2565 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2567 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2568 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2569 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2571 let ExeDomain = SSEPackedInt in {
2572 let neverHasSideEffects = 1 in {
2573 // 128-bit logical shifts.
2574 def PSLLDQri : PDIi8<0x73, MRM7r,
2575 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2576 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2577 def PSRLDQri : PDIi8<0x73, MRM3r,
2578 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2579 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2580 // PSRADQri doesn't exist in SSE[1-3].
2582 def PANDNrr : PDI<0xDF, MRMSrcReg,
2583 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2584 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2586 def PANDNrm : PDI<0xDF, MRMSrcMem,
2587 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2588 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2590 } // Constraints = "$src1 = $dst"
2592 let Predicates = [HasAVX] in {
2593 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2594 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2595 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2596 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2597 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2598 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2599 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2600 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2601 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2602 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2604 // Shift up / down and insert zero's.
2605 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2606 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2607 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2608 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2611 let Predicates = [HasSSE2] in {
2612 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2613 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2614 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2615 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2616 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2617 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2618 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2619 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2620 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2621 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2623 // Shift up / down and insert zero's.
2624 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2625 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2626 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2627 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2630 //===---------------------------------------------------------------------===//
2631 // SSE2 - Packed Integer Comparison Instructions
2632 //===---------------------------------------------------------------------===//
2634 let Predicates = [HasAVX] in {
2635 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2637 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2639 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2641 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2643 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2645 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2649 let Constraints = "$src1 = $dst" in {
2650 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2651 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2652 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2653 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2654 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2655 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2656 } // Constraints = "$src1 = $dst"
2658 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2659 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2660 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2661 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2662 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2663 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2664 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2665 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2666 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2667 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2668 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2669 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2671 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2672 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2673 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2674 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2675 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2676 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2677 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2678 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2679 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2680 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2681 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2682 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2684 //===---------------------------------------------------------------------===//
2685 // SSE2 - Packed Integer Pack Instructions
2686 //===---------------------------------------------------------------------===//
2688 let Predicates = [HasAVX] in {
2689 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2691 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2693 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2697 let Constraints = "$src1 = $dst" in {
2698 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2699 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2700 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2701 } // Constraints = "$src1 = $dst"
2703 //===---------------------------------------------------------------------===//
2704 // SSE2 - Packed Integer Shuffle Instructions
2705 //===---------------------------------------------------------------------===//
2707 let ExeDomain = SSEPackedInt in {
2708 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2710 def ri : Ii8<0x70, MRMSrcReg,
2711 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2712 !strconcat(OpcodeStr,
2713 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2714 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2716 def mi : Ii8<0x70, MRMSrcMem,
2717 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2718 !strconcat(OpcodeStr,
2719 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2720 [(set VR128:$dst, (vt (pshuf_frag:$src2
2721 (bc_frag (memopv2i64 addr:$src1)),
2724 } // ExeDomain = SSEPackedInt
2726 let Predicates = [HasAVX] in {
2727 let AddedComplexity = 5 in
2728 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2731 // SSE2 with ImmT == Imm8 and XS prefix.
2732 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2735 // SSE2 with ImmT == Imm8 and XD prefix.
2736 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2740 let Predicates = [HasSSE2] in {
2741 let AddedComplexity = 5 in
2742 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2744 // SSE2 with ImmT == Imm8 and XS prefix.
2745 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2747 // SSE2 with ImmT == Imm8 and XD prefix.
2748 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2751 //===---------------------------------------------------------------------===//
2752 // SSE2 - Packed Integer Unpack Instructions
2753 //===---------------------------------------------------------------------===//
2755 let ExeDomain = SSEPackedInt in {
2756 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2757 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
2758 def rr : PDI<opc, MRMSrcReg,
2759 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2761 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2762 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2763 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
2764 def rm : PDI<opc, MRMSrcMem,
2765 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2767 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2768 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2769 [(set VR128:$dst, (OpNode VR128:$src1,
2770 (bc_frag (memopv2i64
2774 let Predicates = [HasAVX] in {
2775 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
2776 bc_v16i8, 0>, VEX_4V;
2777 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
2778 bc_v8i16, 0>, VEX_4V;
2779 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
2780 bc_v4i32, 0>, VEX_4V;
2782 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2783 /// knew to collapse (bitconvert VT to VT) into its operand.
2784 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2785 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2786 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2787 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
2788 VR128:$src2)))]>, VEX_4V;
2789 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2790 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2791 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2792 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
2793 (memopv2i64 addr:$src2))))]>, VEX_4V;
2795 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
2796 bc_v16i8, 0>, VEX_4V;
2797 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
2798 bc_v8i16, 0>, VEX_4V;
2799 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
2800 bc_v4i32, 0>, VEX_4V;
2802 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2803 /// knew to collapse (bitconvert VT to VT) into its operand.
2804 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2805 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2806 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2807 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
2808 VR128:$src2)))]>, VEX_4V;
2809 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2810 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2811 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2812 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
2813 (memopv2i64 addr:$src2))))]>, VEX_4V;
2816 let Constraints = "$src1 = $dst" in {
2817 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
2818 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
2819 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
2821 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2822 /// knew to collapse (bitconvert VT to VT) into its operand.
2823 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2824 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2825 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2827 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
2828 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2829 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2830 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2832 (v2i64 (X86Punpcklqdq VR128:$src1,
2833 (memopv2i64 addr:$src2))))]>;
2835 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
2836 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
2837 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
2839 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2840 /// knew to collapse (bitconvert VT to VT) into its operand.
2841 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2842 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2843 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2845 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
2846 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2847 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2848 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2850 (v2i64 (X86Punpckhqdq VR128:$src1,
2851 (memopv2i64 addr:$src2))))]>;
2854 } // ExeDomain = SSEPackedInt
2856 //===---------------------------------------------------------------------===//
2857 // SSE2 - Packed Integer Extract and Insert
2858 //===---------------------------------------------------------------------===//
2860 let ExeDomain = SSEPackedInt in {
2861 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2862 def rri : Ii8<0xC4, MRMSrcReg,
2863 (outs VR128:$dst), (ins VR128:$src1,
2864 GR32:$src2, i32i8imm:$src3),
2866 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2867 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2869 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2870 def rmi : Ii8<0xC4, MRMSrcMem,
2871 (outs VR128:$dst), (ins VR128:$src1,
2872 i16mem:$src2, i32i8imm:$src3),
2874 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2875 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2877 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2882 let Predicates = [HasAVX] in
2883 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2884 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2885 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2886 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2887 imm:$src2))]>, OpSize, VEX;
2888 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2889 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2890 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2891 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2895 let Predicates = [HasAVX] in {
2896 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2897 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2898 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2899 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2900 []>, OpSize, VEX_4V;
2903 let Constraints = "$src1 = $dst" in
2904 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
2906 } // ExeDomain = SSEPackedInt
2908 //===---------------------------------------------------------------------===//
2909 // SSE2 - Packed Mask Creation
2910 //===---------------------------------------------------------------------===//
2912 let ExeDomain = SSEPackedInt in {
2914 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2915 "pmovmskb\t{$src, $dst|$dst, $src}",
2916 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2917 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2918 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2919 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2920 "pmovmskb\t{$src, $dst|$dst, $src}",
2921 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2923 } // ExeDomain = SSEPackedInt
2925 //===---------------------------------------------------------------------===//
2926 // SSE2 - Conditional Store
2927 //===---------------------------------------------------------------------===//
2929 let ExeDomain = SSEPackedInt in {
2932 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2933 (ins VR128:$src, VR128:$mask),
2934 "maskmovdqu\t{$mask, $src|$src, $mask}",
2935 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2937 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2938 (ins VR128:$src, VR128:$mask),
2939 "maskmovdqu\t{$mask, $src|$src, $mask}",
2940 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2943 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2944 "maskmovdqu\t{$mask, $src|$src, $mask}",
2945 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2947 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2948 "maskmovdqu\t{$mask, $src|$src, $mask}",
2949 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2951 } // ExeDomain = SSEPackedInt
2953 //===---------------------------------------------------------------------===//
2954 // SSE2 - Move Doubleword
2955 //===---------------------------------------------------------------------===//
2957 //===---------------------------------------------------------------------===//
2958 // Move Int Doubleword to Packed Double Int
2960 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2961 "movd\t{$src, $dst|$dst, $src}",
2963 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2964 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2965 "movd\t{$src, $dst|$dst, $src}",
2967 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2969 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2970 "mov{d|q}\t{$src, $dst|$dst, $src}",
2972 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
2973 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2974 "mov{d|q}\t{$src, $dst|$dst, $src}",
2975 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
2977 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2978 "movd\t{$src, $dst|$dst, $src}",
2980 (v4i32 (scalar_to_vector GR32:$src)))]>;
2981 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2982 "movd\t{$src, $dst|$dst, $src}",
2984 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2985 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2986 "mov{d|q}\t{$src, $dst|$dst, $src}",
2988 (v2i64 (scalar_to_vector GR64:$src)))]>;
2989 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2990 "mov{d|q}\t{$src, $dst|$dst, $src}",
2991 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2993 //===---------------------------------------------------------------------===//
2994 // Move Int Doubleword to Single Scalar
2996 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2997 "movd\t{$src, $dst|$dst, $src}",
2998 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
3000 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
3001 "movd\t{$src, $dst|$dst, $src}",
3002 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
3004 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
3005 "movd\t{$src, $dst|$dst, $src}",
3006 [(set FR32:$dst, (bitconvert GR32:$src))]>;
3008 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
3009 "movd\t{$src, $dst|$dst, $src}",
3010 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
3012 //===---------------------------------------------------------------------===//
3013 // Move Packed Doubleword Int to Packed Double Int
3015 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3016 "movd\t{$src, $dst|$dst, $src}",
3017 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3019 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
3020 (ins i32mem:$dst, VR128:$src),
3021 "movd\t{$src, $dst|$dst, $src}",
3022 [(store (i32 (vector_extract (v4i32 VR128:$src),
3023 (iPTR 0))), addr:$dst)]>, VEX;
3024 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
3025 "movd\t{$src, $dst|$dst, $src}",
3026 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
3028 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
3029 "movd\t{$src, $dst|$dst, $src}",
3030 [(store (i32 (vector_extract (v4i32 VR128:$src),
3031 (iPTR 0))), addr:$dst)]>;
3033 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3034 "mov{d|q}\t{$src, $dst|$dst, $src}",
3035 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
3037 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
3038 "movq\t{$src, $dst|$dst, $src}",
3039 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
3041 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
3042 "mov{d|q}\t{$src, $dst|$dst, $src}",
3043 [(set GR64:$dst, (bitconvert FR64:$src))]>;
3044 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
3045 "movq\t{$src, $dst|$dst, $src}",
3046 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
3048 //===---------------------------------------------------------------------===//
3049 // Move Scalar Single to Double Int
3051 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3052 "movd\t{$src, $dst|$dst, $src}",
3053 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
3054 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3055 "movd\t{$src, $dst|$dst, $src}",
3056 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
3057 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3058 "movd\t{$src, $dst|$dst, $src}",
3059 [(set GR32:$dst, (bitconvert FR32:$src))]>;
3060 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3061 "movd\t{$src, $dst|$dst, $src}",
3062 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
3064 //===---------------------------------------------------------------------===//
3065 // Patterns and instructions to describe movd/movq to XMM register zero-extends
3067 let AddedComplexity = 15 in {
3068 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3069 "movd\t{$src, $dst|$dst, $src}",
3070 [(set VR128:$dst, (v4i32 (X86vzmovl
3071 (v4i32 (scalar_to_vector GR32:$src)))))]>,
3073 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3074 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3075 [(set VR128:$dst, (v2i64 (X86vzmovl
3076 (v2i64 (scalar_to_vector GR64:$src)))))]>,
3079 let AddedComplexity = 15 in {
3080 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3081 "movd\t{$src, $dst|$dst, $src}",
3082 [(set VR128:$dst, (v4i32 (X86vzmovl
3083 (v4i32 (scalar_to_vector GR32:$src)))))]>;
3084 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3085 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3086 [(set VR128:$dst, (v2i64 (X86vzmovl
3087 (v2i64 (scalar_to_vector GR64:$src)))))]>;
3090 let AddedComplexity = 20 in {
3091 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3092 "movd\t{$src, $dst|$dst, $src}",
3094 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3095 (loadi32 addr:$src))))))]>,
3097 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3098 "movd\t{$src, $dst|$dst, $src}",
3100 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3101 (loadi32 addr:$src))))))]>;
3103 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
3104 (MOVZDI2PDIrm addr:$src)>;
3105 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3106 (MOVZDI2PDIrm addr:$src)>;
3107 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3108 (MOVZDI2PDIrm addr:$src)>;
3111 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3112 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3113 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3114 (v4i32 (scalar_to_vector GR32:$src)), (i32 0)))),
3115 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
3116 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3117 (v2i64 (scalar_to_vector GR64:$src)), (i32 0)))),
3118 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
3120 // These are the correct encodings of the instructions so that we know how to
3121 // read correct assembly, even though we continue to emit the wrong ones for
3122 // compatibility with Darwin's buggy assembler.
3123 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3124 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
3125 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3126 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
3127 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3128 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
3129 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3130 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
3131 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3132 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3133 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3134 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3136 //===---------------------------------------------------------------------===//
3137 // SSE2 - Move Quadword
3138 //===---------------------------------------------------------------------===//
3140 //===---------------------------------------------------------------------===//
3141 // Move Quadword Int to Packed Quadword Int
3143 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3144 "vmovq\t{$src, $dst|$dst, $src}",
3146 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3147 VEX, Requires<[HasAVX]>;
3148 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3149 "movq\t{$src, $dst|$dst, $src}",
3151 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3152 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3154 //===---------------------------------------------------------------------===//
3155 // Move Packed Quadword Int to Quadword Int
3157 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3158 "movq\t{$src, $dst|$dst, $src}",
3159 [(store (i64 (vector_extract (v2i64 VR128:$src),
3160 (iPTR 0))), addr:$dst)]>, VEX;
3161 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3162 "movq\t{$src, $dst|$dst, $src}",
3163 [(store (i64 (vector_extract (v2i64 VR128:$src),
3164 (iPTR 0))), addr:$dst)]>;
3166 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3167 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3169 //===---------------------------------------------------------------------===//
3170 // Store / copy lower 64-bits of a XMM register.
3172 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3173 "movq\t{$src, $dst|$dst, $src}",
3174 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3175 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3176 "movq\t{$src, $dst|$dst, $src}",
3177 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3179 let AddedComplexity = 20 in
3180 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3181 "vmovq\t{$src, $dst|$dst, $src}",
3183 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3184 (loadi64 addr:$src))))))]>,
3185 XS, VEX, Requires<[HasAVX]>;
3187 let AddedComplexity = 20 in {
3188 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3189 "movq\t{$src, $dst|$dst, $src}",
3191 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3192 (loadi64 addr:$src))))))]>,
3193 XS, Requires<[HasSSE2]>;
3195 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3196 (MOVZQI2PQIrm addr:$src)>;
3197 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3198 (MOVZQI2PQIrm addr:$src)>;
3199 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3202 //===---------------------------------------------------------------------===//
3203 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3204 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3206 let AddedComplexity = 15 in
3207 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3208 "vmovq\t{$src, $dst|$dst, $src}",
3209 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3210 XS, VEX, Requires<[HasAVX]>;
3211 let AddedComplexity = 15 in
3212 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3213 "movq\t{$src, $dst|$dst, $src}",
3214 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3215 XS, Requires<[HasSSE2]>;
3217 let AddedComplexity = 20 in
3218 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3219 "vmovq\t{$src, $dst|$dst, $src}",
3220 [(set VR128:$dst, (v2i64 (X86vzmovl
3221 (loadv2i64 addr:$src))))]>,
3222 XS, VEX, Requires<[HasAVX]>;
3223 let AddedComplexity = 20 in {
3224 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3225 "movq\t{$src, $dst|$dst, $src}",
3226 [(set VR128:$dst, (v2i64 (X86vzmovl
3227 (loadv2i64 addr:$src))))]>,
3228 XS, Requires<[HasSSE2]>;
3230 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3231 (MOVZPQILo2PQIrm addr:$src)>;
3234 // Instructions to match in the assembler
3235 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3236 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3237 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3238 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3239 // Recognize "movd" with GR64 destination, but encode as a "movq"
3240 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3241 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3243 // Instructions for the disassembler
3244 // xr = XMM register
3247 let Predicates = [HasAVX] in
3248 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3249 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3250 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3251 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3253 //===---------------------------------------------------------------------===//
3254 // SSE2 - Misc Instructions
3255 //===---------------------------------------------------------------------===//
3258 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3259 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3260 TB, Requires<[HasSSE2]>;
3262 // Load, store, and memory fence
3263 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3264 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3265 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3266 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3267 def : Pat<(X86LFence), (LFENCE)>;
3268 def : Pat<(X86MFence), (MFENCE)>;
3271 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3272 // was introduced with SSE2, it's backward compatible.
3273 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3275 // Alias instructions that map zero vector to pxor / xorp* for sse.
3276 // We set canFoldAsLoad because this can be converted to a constant-pool
3277 // load of an all-ones value if folding it would be beneficial.
3278 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
3279 // JIT implementation, it does not expand the instructions below like
3280 // X86MCInstLower does.
3281 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3282 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3283 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3284 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3285 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3286 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
3287 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3288 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
3290 //===---------------------------------------------------------------------===//
3291 // SSE3 - Conversion Instructions
3292 //===---------------------------------------------------------------------===//
3294 // Convert Packed Double FP to Packed DW Integers
3295 let Predicates = [HasAVX] in {
3296 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3297 // register, but the same isn't true when using memory operands instead.
3298 // Provide other assembly rr and rm forms to address this explicitly.
3299 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3300 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3301 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3302 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3305 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3306 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3307 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3308 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3311 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3312 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3313 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3314 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3317 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3318 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3319 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3320 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3322 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
3323 (VCVTPD2DQYrr VR256:$src)>;
3324 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
3325 (VCVTPD2DQYrm addr:$src)>;
3327 // Convert Packed DW Integers to Packed Double FP
3328 let Predicates = [HasAVX] in {
3329 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3330 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3331 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3332 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3333 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3334 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3335 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3336 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3339 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3340 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3341 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3342 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3344 // AVX 256-bit register conversion intrinsics
3345 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3346 (VCVTDQ2PDYrr VR128:$src)>;
3347 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3348 (VCVTDQ2PDYrm addr:$src)>;
3350 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3351 (VCVTPD2DQYrr VR256:$src)>;
3352 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3353 (VCVTPD2DQYrm addr:$src)>;
3355 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
3356 (VCVTDQ2PDYrr VR128:$src)>;
3357 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
3358 (VCVTDQ2PDYrm addr:$src)>;
3360 //===---------------------------------------------------------------------===//
3361 // SSE3 - Move Instructions
3362 //===---------------------------------------------------------------------===//
3364 //===---------------------------------------------------------------------===//
3365 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3367 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3368 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3369 X86MemOperand x86memop> {
3370 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3371 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3372 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
3373 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3374 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3375 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
3378 let Predicates = [HasAVX] in {
3379 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3380 v4f32, VR128, memopv4f32, f128mem>, VEX;
3381 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3382 v4f32, VR128, memopv4f32, f128mem>, VEX;
3383 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3384 v8f32, VR256, memopv8f32, f256mem>, VEX;
3385 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3386 v8f32, VR256, memopv8f32, f256mem>, VEX;
3388 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
3389 memopv4f32, f128mem>;
3390 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
3391 memopv4f32, f128mem>;
3393 let Predicates = [HasSSE3] in {
3394 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3395 (MOVSHDUPrr VR128:$src)>;
3396 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3397 (MOVSHDUPrm addr:$src)>;
3398 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3399 (MOVSLDUPrr VR128:$src)>;
3400 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3401 (MOVSLDUPrm addr:$src)>;
3404 let Predicates = [HasAVX] in {
3405 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3406 (VMOVSHDUPrr VR128:$src)>;
3407 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3408 (VMOVSHDUPrm addr:$src)>;
3409 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3410 (VMOVSLDUPrr VR128:$src)>;
3411 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3412 (VMOVSLDUPrm addr:$src)>;
3413 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
3414 (VMOVSHDUPYrr VR256:$src)>;
3415 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
3416 (VMOVSHDUPYrm addr:$src)>;
3417 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
3418 (VMOVSLDUPYrr VR256:$src)>;
3419 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
3420 (VMOVSLDUPYrm addr:$src)>;
3423 //===---------------------------------------------------------------------===//
3424 // Replicate Double FP - MOVDDUP
3426 multiclass sse3_replicate_dfp<string OpcodeStr> {
3427 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3428 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3429 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3430 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3431 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3433 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3437 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3438 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3439 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3441 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3442 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3446 let Predicates = [HasAVX] in {
3447 // FIXME: Merge above classes when we have patterns for the ymm version
3448 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3449 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3451 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3453 // Move Unaligned Integer
3454 let Predicates = [HasAVX] in {
3455 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3456 "vlddqu\t{$src, $dst|$dst, $src}",
3457 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3458 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3459 "vlddqu\t{$src, $dst|$dst, $src}",
3460 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
3462 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3463 "lddqu\t{$src, $dst|$dst, $src}",
3464 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3466 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3468 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3470 // Several Move patterns
3471 let AddedComplexity = 5 in {
3472 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3473 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3474 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3475 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3476 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3477 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3478 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3479 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3482 //===---------------------------------------------------------------------===//
3483 // SSE3 - Arithmetic
3484 //===---------------------------------------------------------------------===//
3486 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3487 X86MemOperand x86memop, bit Is2Addr = 1> {
3488 def rr : I<0xD0, MRMSrcReg,
3489 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3491 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3492 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3493 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3494 def rm : I<0xD0, MRMSrcMem,
3495 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3497 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3498 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3499 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3502 let Predicates = [HasAVX],
3503 ExeDomain = SSEPackedDouble in {
3504 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3505 f128mem, 0>, TB, XD, VEX_4V;
3506 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3507 f128mem, 0>, TB, OpSize, VEX_4V;
3508 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3509 f256mem, 0>, TB, XD, VEX_4V;
3510 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3511 f256mem, 0>, TB, OpSize, VEX_4V;
3513 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3514 ExeDomain = SSEPackedDouble in {
3515 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3517 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3518 f128mem>, TB, OpSize;
3521 //===---------------------------------------------------------------------===//
3522 // SSE3 Instructions
3523 //===---------------------------------------------------------------------===//
3526 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3527 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3528 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3530 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3531 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3532 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3534 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3536 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3537 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3538 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3540 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3541 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3542 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3544 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3545 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3546 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3548 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3550 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3551 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3552 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3555 let Predicates = [HasAVX] in {
3556 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3557 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3558 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3559 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3560 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3561 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3562 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3563 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3564 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3565 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3566 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3567 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3568 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3569 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3570 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3571 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3574 let Constraints = "$src1 = $dst" in {
3575 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3576 int_x86_sse3_hadd_ps>;
3577 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3578 int_x86_sse3_hadd_pd>;
3579 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3580 int_x86_sse3_hsub_ps>;
3581 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3582 int_x86_sse3_hsub_pd>;
3585 //===---------------------------------------------------------------------===//
3586 // SSSE3 - Packed Absolute Instructions
3587 //===---------------------------------------------------------------------===//
3590 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3591 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3592 PatFrag mem_frag128, Intrinsic IntId128> {
3593 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3595 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3596 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3599 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3601 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3604 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3607 let Predicates = [HasAVX] in {
3608 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
3609 int_x86_ssse3_pabs_b_128>, VEX;
3610 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
3611 int_x86_ssse3_pabs_w_128>, VEX;
3612 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
3613 int_x86_ssse3_pabs_d_128>, VEX;
3616 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
3617 int_x86_ssse3_pabs_b_128>;
3618 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
3619 int_x86_ssse3_pabs_w_128>;
3620 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
3621 int_x86_ssse3_pabs_d_128>;
3623 //===---------------------------------------------------------------------===//
3624 // SSSE3 - Packed Binary Operator Instructions
3625 //===---------------------------------------------------------------------===//
3627 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3628 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3629 PatFrag mem_frag128, Intrinsic IntId128,
3631 let isCommutable = 1 in
3632 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3633 (ins VR128:$src1, VR128:$src2),
3635 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3636 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3637 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3639 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3640 (ins VR128:$src1, i128mem:$src2),
3642 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3643 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3645 (IntId128 VR128:$src1,
3646 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3649 let Predicates = [HasAVX] in {
3650 let isCommutable = 0 in {
3651 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
3652 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3653 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
3654 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3655 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
3656 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3657 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
3658 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3659 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
3660 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3661 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
3662 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3663 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
3664 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3665 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
3666 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3667 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
3668 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3669 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
3670 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3671 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
3672 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3674 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
3675 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3678 // None of these have i8 immediate fields.
3679 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3680 let isCommutable = 0 in {
3681 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
3682 int_x86_ssse3_phadd_w_128>;
3683 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
3684 int_x86_ssse3_phadd_d_128>;
3685 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
3686 int_x86_ssse3_phadd_sw_128>;
3687 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
3688 int_x86_ssse3_phsub_w_128>;
3689 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
3690 int_x86_ssse3_phsub_d_128>;
3691 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
3692 int_x86_ssse3_phsub_sw_128>;
3693 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
3694 int_x86_ssse3_pmadd_ub_sw_128>;
3695 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
3696 int_x86_ssse3_pshuf_b_128>;
3697 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
3698 int_x86_ssse3_psign_b_128>;
3699 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
3700 int_x86_ssse3_psign_w_128>;
3701 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
3702 int_x86_ssse3_psign_d_128>;
3704 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
3705 int_x86_ssse3_pmul_hr_sw_128>;
3708 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3709 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3710 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3711 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3713 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
3714 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3715 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
3716 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3717 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
3718 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3720 //===---------------------------------------------------------------------===//
3721 // SSSE3 - Packed Align Instruction Patterns
3722 //===---------------------------------------------------------------------===//
3724 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
3725 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3726 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3728 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3730 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3732 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3733 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3735 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3737 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3741 let Predicates = [HasAVX] in
3742 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
3743 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
3744 defm PALIGN : ssse3_palign<"palignr">;
3746 let Predicates = [HasSSSE3] in {
3747 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3748 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3749 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3750 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3751 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3752 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3753 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3754 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3757 let Predicates = [HasAVX] in {
3758 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3759 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3760 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3761 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3762 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3763 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3764 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
3765 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
3768 //===---------------------------------------------------------------------===//
3769 // SSSE3 Misc Instructions
3770 //===---------------------------------------------------------------------===//
3772 // Thread synchronization
3773 let usesCustomInserter = 1 in {
3774 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
3775 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
3776 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
3777 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
3780 let Uses = [EAX, ECX, EDX] in
3781 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
3782 Requires<[HasSSE3]>;
3783 let Uses = [ECX, EAX] in
3784 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
3785 Requires<[HasSSE3]>;
3787 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
3788 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
3790 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
3791 Requires<[In32BitMode]>;
3792 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
3793 Requires<[In64BitMode]>;
3795 //===---------------------------------------------------------------------===//
3796 // Non-Instruction Patterns
3797 //===---------------------------------------------------------------------===//
3799 // extload f32 -> f64. This matches load+fextend because we have a hack in
3800 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3802 // Since these loads aren't folded into the fextend, we have to match it
3804 let Predicates = [HasSSE2] in
3805 def : Pat<(fextend (loadf32 addr:$src)),
3806 (CVTSS2SDrm addr:$src)>;
3808 // Bitcasts between 128-bit vector types. Return the original type since
3809 // no instruction is needed for the conversion
3810 let Predicates = [HasXMMInt] in {
3811 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3812 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3813 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3814 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3815 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3816 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3817 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3818 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3819 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3820 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3821 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3822 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3823 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3824 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3825 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3826 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3827 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3828 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3829 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3830 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3831 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3832 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3833 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3834 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3835 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3836 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3837 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3838 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3839 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3840 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3843 // Bitcasts between 256-bit vector types. Return the original type since
3844 // no instruction is needed for the conversion
3845 let Predicates = [HasAVX] in {
3846 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
3847 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
3848 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
3849 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
3850 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
3851 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
3852 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
3853 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
3854 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
3855 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
3856 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
3857 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
3858 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
3859 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
3860 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
3861 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
3862 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
3863 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
3864 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
3865 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
3866 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
3867 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
3868 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
3869 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
3870 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
3871 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
3872 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
3873 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
3874 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
3875 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
3878 // Move scalar to XMM zero-extended
3879 // movd to XMM register zero-extends
3880 let AddedComplexity = 15 in {
3881 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3882 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3883 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3884 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3885 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3886 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3887 (MOVSSrr (v4f32 (V_SET0PS)),
3888 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3889 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3890 (MOVSSrr (v4i32 (V_SET0PI)),
3891 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3894 // Splat v2f64 / v2i64
3895 let AddedComplexity = 10 in {
3896 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3897 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3898 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3899 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3902 // Special unary SHUFPSrri case.
3903 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3904 (SHUFPSrri VR128:$src1, VR128:$src1,
3905 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3906 let AddedComplexity = 5 in
3907 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3908 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3909 Requires<[HasSSE2]>;
3910 // Special unary SHUFPDrri case.
3911 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3912 (SHUFPDrri VR128:$src1, VR128:$src1,
3913 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3914 Requires<[HasSSE2]>;
3915 // Special unary SHUFPDrri case.
3916 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3917 (SHUFPDrri VR128:$src1, VR128:$src1,
3918 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3919 Requires<[HasSSE2]>;
3920 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3921 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3922 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3923 Requires<[HasSSE2]>;
3925 // Special binary v4i32 shuffle cases with SHUFPS.
3926 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3927 (SHUFPSrri VR128:$src1, VR128:$src2,
3928 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3929 Requires<[HasSSE2]>;
3930 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3931 (SHUFPSrmi VR128:$src1, addr:$src2,
3932 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3933 Requires<[HasSSE2]>;
3934 // Special binary v2i64 shuffle cases using SHUFPDrri.
3935 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3936 (SHUFPDrri VR128:$src1, VR128:$src2,
3937 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3938 Requires<[HasSSE2]>;
3940 let AddedComplexity = 20 in {
3941 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3942 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3943 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3945 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3946 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3947 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3949 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3950 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3951 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3952 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3953 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3956 let AddedComplexity = 20 in {
3957 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3958 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3959 (MOVLPSrm VR128:$src1, addr:$src2)>;
3960 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3961 (MOVLPDrm VR128:$src1, addr:$src2)>;
3962 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3963 (MOVLPSrm VR128:$src1, addr:$src2)>;
3964 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3965 (MOVLPDrm VR128:$src1, addr:$src2)>;
3968 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3969 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3970 (MOVLPSmr addr:$src1, VR128:$src2)>;
3971 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3972 (MOVLPDmr addr:$src1, VR128:$src2)>;
3973 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3975 (MOVLPSmr addr:$src1, VR128:$src2)>;
3976 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3977 (MOVLPDmr addr:$src1, VR128:$src2)>;
3979 let AddedComplexity = 15 in {
3980 // Setting the lowest element in the vector.
3981 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3982 (MOVSSrr (v4i32 VR128:$src1),
3983 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3984 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3985 (MOVSDrr (v2i64 VR128:$src1),
3986 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3988 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3989 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3990 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3991 Requires<[HasSSE2]>;
3992 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3993 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3994 Requires<[HasSSE2]>;
3997 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3998 // fall back to this for SSE1)
3999 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
4000 (SHUFPSrri VR128:$src2, VR128:$src1,
4001 (SHUFFLE_get_shuf_imm VR128:$src3))>;
4003 // Set lowest element and zero upper elements.
4004 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4005 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
4007 // Use movaps / movups for SSE integer load / store (one byte shorter).
4008 // The instructions selected below are then converted to MOVDQA/MOVDQU
4009 // during the SSE domain pass.
4010 let Predicates = [HasSSE1] in {
4011 def : Pat<(alignedloadv4i32 addr:$src),
4012 (MOVAPSrm addr:$src)>;
4013 def : Pat<(loadv4i32 addr:$src),
4014 (MOVUPSrm addr:$src)>;
4015 def : Pat<(alignedloadv2i64 addr:$src),
4016 (MOVAPSrm addr:$src)>;
4017 def : Pat<(loadv2i64 addr:$src),
4018 (MOVUPSrm addr:$src)>;
4020 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4021 (MOVAPSmr addr:$dst, VR128:$src)>;
4022 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4023 (MOVAPSmr addr:$dst, VR128:$src)>;
4024 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4025 (MOVAPSmr addr:$dst, VR128:$src)>;
4026 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4027 (MOVAPSmr addr:$dst, VR128:$src)>;
4028 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4029 (MOVUPSmr addr:$dst, VR128:$src)>;
4030 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4031 (MOVUPSmr addr:$dst, VR128:$src)>;
4032 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4033 (MOVUPSmr addr:$dst, VR128:$src)>;
4034 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4035 (MOVUPSmr addr:$dst, VR128:$src)>;
4038 // Use vmovaps/vmovups for AVX integer load/store.
4039 let Predicates = [HasAVX] in {
4040 // 128-bit load/store
4041 def : Pat<(alignedloadv4i32 addr:$src),
4042 (VMOVAPSrm addr:$src)>;
4043 def : Pat<(loadv4i32 addr:$src),
4044 (VMOVUPSrm addr:$src)>;
4045 def : Pat<(alignedloadv2i64 addr:$src),
4046 (VMOVAPSrm addr:$src)>;
4047 def : Pat<(loadv2i64 addr:$src),
4048 (VMOVUPSrm addr:$src)>;
4050 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
4051 (VMOVAPSmr addr:$dst, VR128:$src)>;
4052 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
4053 (VMOVAPSmr addr:$dst, VR128:$src)>;
4054 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
4055 (VMOVAPSmr addr:$dst, VR128:$src)>;
4056 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
4057 (VMOVAPSmr addr:$dst, VR128:$src)>;
4058 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
4059 (VMOVUPSmr addr:$dst, VR128:$src)>;
4060 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
4061 (VMOVUPSmr addr:$dst, VR128:$src)>;
4062 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
4063 (VMOVUPSmr addr:$dst, VR128:$src)>;
4064 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4065 (VMOVUPSmr addr:$dst, VR128:$src)>;
4067 // 256-bit load/store
4068 def : Pat<(alignedloadv4i64 addr:$src),
4069 (VMOVAPSYrm addr:$src)>;
4070 def : Pat<(loadv4i64 addr:$src),
4071 (VMOVUPSYrm addr:$src)>;
4072 def : Pat<(alignedloadv8i32 addr:$src),
4073 (VMOVAPSYrm addr:$src)>;
4074 def : Pat<(loadv8i32 addr:$src),
4075 (VMOVUPSYrm addr:$src)>;
4076 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
4077 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4078 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
4079 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4080 def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst),
4081 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4082 def : Pat<(alignedstore (v32i8 VR256:$src), addr:$dst),
4083 (VMOVAPSYmr addr:$dst, VR256:$src)>;
4084 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
4085 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4086 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
4087 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4088 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
4089 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4090 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
4091 (VMOVUPSYmr addr:$dst, VR256:$src)>;
4094 //===----------------------------------------------------------------------===//
4095 // SSE4.1 - Packed Move with Sign/Zero Extend
4096 //===----------------------------------------------------------------------===//
4098 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4099 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4100 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4101 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4103 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4104 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4106 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
4110 let Predicates = [HasAVX] in {
4111 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
4113 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
4115 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
4117 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
4119 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
4121 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
4125 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4126 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4127 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4128 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4129 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4130 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4132 // Common patterns involving scalar load.
4133 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4134 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4135 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4136 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4138 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4139 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4140 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4141 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4143 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4144 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4145 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4146 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4148 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4149 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4150 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4151 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4153 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4154 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4155 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4156 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4158 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4159 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4160 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4161 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4164 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4165 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4166 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4167 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4169 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4170 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4172 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4176 let Predicates = [HasAVX] in {
4177 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
4179 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
4181 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
4183 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
4187 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4188 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4189 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4190 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4192 // Common patterns involving scalar load
4193 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4194 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4195 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4196 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4198 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4199 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4200 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4201 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4204 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4205 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4206 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4207 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4209 // Expecting a i16 load any extended to i32 value.
4210 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4211 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4212 [(set VR128:$dst, (IntId (bitconvert
4213 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4217 let Predicates = [HasAVX] in {
4218 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4220 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4223 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4224 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4226 // Common patterns involving scalar load
4227 def : Pat<(int_x86_sse41_pmovsxbq
4228 (bitconvert (v4i32 (X86vzmovl
4229 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4230 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4232 def : Pat<(int_x86_sse41_pmovzxbq
4233 (bitconvert (v4i32 (X86vzmovl
4234 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4235 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4237 //===----------------------------------------------------------------------===//
4238 // SSE4.1 - Extract Instructions
4239 //===----------------------------------------------------------------------===//
4241 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4242 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4243 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4244 (ins VR128:$src1, i32i8imm:$src2),
4245 !strconcat(OpcodeStr,
4246 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4247 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4249 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4250 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4251 !strconcat(OpcodeStr,
4252 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4255 // There's an AssertZext in the way of writing the store pattern
4256 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4259 let Predicates = [HasAVX] in {
4260 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4261 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4262 (ins VR128:$src1, i32i8imm:$src2),
4263 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4266 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4269 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4270 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4271 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4272 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4273 !strconcat(OpcodeStr,
4274 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4277 // There's an AssertZext in the way of writing the store pattern
4278 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4281 let Predicates = [HasAVX] in
4282 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4284 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4287 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4288 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4289 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4290 (ins VR128:$src1, i32i8imm:$src2),
4291 !strconcat(OpcodeStr,
4292 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4294 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4295 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4296 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4297 !strconcat(OpcodeStr,
4298 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4299 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4300 addr:$dst)]>, OpSize;
4303 let Predicates = [HasAVX] in
4304 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4306 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4308 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4309 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4310 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4311 (ins VR128:$src1, i32i8imm:$src2),
4312 !strconcat(OpcodeStr,
4313 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4315 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4316 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4317 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4318 !strconcat(OpcodeStr,
4319 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4320 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4321 addr:$dst)]>, OpSize, REX_W;
4324 let Predicates = [HasAVX] in
4325 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4327 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4329 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4331 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4332 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4333 (ins VR128:$src1, i32i8imm:$src2),
4334 !strconcat(OpcodeStr,
4335 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4337 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4339 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4340 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4341 !strconcat(OpcodeStr,
4342 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4343 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4344 addr:$dst)]>, OpSize;
4347 let Predicates = [HasAVX] in {
4348 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4349 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4350 (ins VR128:$src1, i32i8imm:$src2),
4351 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4354 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4356 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4357 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4360 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4361 Requires<[HasSSE41]>;
4363 //===----------------------------------------------------------------------===//
4364 // SSE4.1 - Insert Instructions
4365 //===----------------------------------------------------------------------===//
4367 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4368 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4369 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4371 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4373 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4375 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4376 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4377 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4379 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4381 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4383 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4384 imm:$src3))]>, OpSize;
4387 let Predicates = [HasAVX] in
4388 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4389 let Constraints = "$src1 = $dst" in
4390 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4392 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4393 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4394 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4396 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4398 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4400 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4402 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4403 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4405 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4407 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4409 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4410 imm:$src3)))]>, OpSize;
4413 let Predicates = [HasAVX] in
4414 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4415 let Constraints = "$src1 = $dst" in
4416 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4418 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4419 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4420 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4422 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4424 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4426 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4428 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4429 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4431 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4433 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4435 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4436 imm:$src3)))]>, OpSize;
4439 let Predicates = [HasAVX] in
4440 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4441 let Constraints = "$src1 = $dst" in
4442 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4444 // insertps has a few different modes, there's the first two here below which
4445 // are optimized inserts that won't zero arbitrary elements in the destination
4446 // vector. The next one matches the intrinsic and could zero arbitrary elements
4447 // in the target vector.
4448 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4449 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4450 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
4452 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4454 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4456 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4458 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4459 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
4461 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4463 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4465 (X86insrtps VR128:$src1,
4466 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4467 imm:$src3))]>, OpSize;
4470 let Constraints = "$src1 = $dst" in
4471 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4472 let Predicates = [HasAVX] in
4473 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4475 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4476 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4478 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4479 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4480 Requires<[HasSSE41]>;
4482 //===----------------------------------------------------------------------===//
4483 // SSE4.1 - Round Instructions
4484 //===----------------------------------------------------------------------===//
4486 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4487 X86MemOperand x86memop, RegisterClass RC,
4488 PatFrag mem_frag32, PatFrag mem_frag64,
4489 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4490 // Intrinsic operation, reg.
4491 // Vector intrinsic operation, reg
4492 def PSr : SS4AIi8<opcps, MRMSrcReg,
4493 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4494 !strconcat(OpcodeStr,
4495 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4496 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4499 // Vector intrinsic operation, mem
4500 def PSm : Ii8<opcps, MRMSrcMem,
4501 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4502 !strconcat(OpcodeStr,
4503 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4505 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4507 Requires<[HasSSE41]>;
4509 // Vector intrinsic operation, reg
4510 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4511 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4512 !strconcat(OpcodeStr,
4513 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4514 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4517 // Vector intrinsic operation, mem
4518 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4519 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4520 !strconcat(OpcodeStr,
4521 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4523 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4527 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4528 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4529 // Intrinsic operation, reg.
4530 // Vector intrinsic operation, reg
4531 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
4532 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4533 !strconcat(OpcodeStr,
4534 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4537 // Vector intrinsic operation, mem
4538 def PSm_AVX : Ii8<opcps, MRMSrcMem,
4539 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4540 !strconcat(OpcodeStr,
4541 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4542 []>, TA, OpSize, Requires<[HasSSE41]>;
4544 // Vector intrinsic operation, reg
4545 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
4546 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4547 !strconcat(OpcodeStr,
4548 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4551 // Vector intrinsic operation, mem
4552 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
4553 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4554 !strconcat(OpcodeStr,
4555 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4559 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4562 Intrinsic F64Int, bit Is2Addr = 1> {
4563 // Intrinsic operation, reg.
4564 def SSr : SS4AIi8<opcss, MRMSrcReg,
4565 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4567 !strconcat(OpcodeStr,
4568 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4569 !strconcat(OpcodeStr,
4570 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4571 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4574 // Intrinsic operation, mem.
4575 def SSm : SS4AIi8<opcss, MRMSrcMem,
4576 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4578 !strconcat(OpcodeStr,
4579 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4580 !strconcat(OpcodeStr,
4581 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4583 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4586 // Intrinsic operation, reg.
4587 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4588 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4590 !strconcat(OpcodeStr,
4591 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4592 !strconcat(OpcodeStr,
4593 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4594 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4597 // Intrinsic operation, mem.
4598 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4599 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4601 !strconcat(OpcodeStr,
4602 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4603 !strconcat(OpcodeStr,
4604 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4606 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4610 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4612 // Intrinsic operation, reg.
4613 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
4614 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4615 !strconcat(OpcodeStr,
4616 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4619 // Intrinsic operation, mem.
4620 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
4621 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4622 !strconcat(OpcodeStr,
4623 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4626 // Intrinsic operation, reg.
4627 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
4628 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4629 !strconcat(OpcodeStr,
4630 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4633 // Intrinsic operation, mem.
4634 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
4635 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4636 !strconcat(OpcodeStr,
4637 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4641 // FP round - roundss, roundps, roundsd, roundpd
4642 let Predicates = [HasAVX] in {
4644 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4645 memopv4f32, memopv2f64,
4646 int_x86_sse41_round_ps,
4647 int_x86_sse41_round_pd>, VEX;
4648 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4649 memopv8f32, memopv4f64,
4650 int_x86_avx_round_ps_256,
4651 int_x86_avx_round_pd_256>, VEX;
4652 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4653 int_x86_sse41_round_ss,
4654 int_x86_sse41_round_sd, 0>, VEX_4V;
4656 // Instructions for the assembler
4657 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4659 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4661 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4664 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4665 memopv4f32, memopv2f64,
4666 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4667 let Constraints = "$src1 = $dst" in
4668 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4669 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4671 //===----------------------------------------------------------------------===//
4672 // SSE4.1 - Packed Bit Test
4673 //===----------------------------------------------------------------------===//
4675 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4676 // the intel intrinsic that corresponds to this.
4677 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4678 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4679 "vptest\t{$src2, $src1|$src1, $src2}",
4680 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4682 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4683 "vptest\t{$src2, $src1|$src1, $src2}",
4684 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4687 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4688 "vptest\t{$src2, $src1|$src1, $src2}",
4689 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
4691 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4692 "vptest\t{$src2, $src1|$src1, $src2}",
4693 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
4697 let Defs = [EFLAGS] in {
4698 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4699 "ptest \t{$src2, $src1|$src1, $src2}",
4700 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4702 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4703 "ptest \t{$src2, $src1|$src1, $src2}",
4704 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4708 // The bit test instructions below are AVX only
4709 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4710 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
4711 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
4712 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4713 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
4714 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
4715 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4716 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
4720 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4721 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
4722 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
4723 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
4724 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
4727 //===----------------------------------------------------------------------===//
4728 // SSE4.1 - Misc Instructions
4729 //===----------------------------------------------------------------------===//
4731 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4732 "popcnt{w}\t{$src, $dst|$dst, $src}",
4733 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
4734 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4735 "popcnt{w}\t{$src, $dst|$dst, $src}",
4736 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
4738 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4739 "popcnt{l}\t{$src, $dst|$dst, $src}",
4740 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
4741 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4742 "popcnt{l}\t{$src, $dst|$dst, $src}",
4743 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
4745 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4746 "popcnt{q}\t{$src, $dst|$dst, $src}",
4747 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
4748 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4749 "popcnt{q}\t{$src, $dst|$dst, $src}",
4750 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
4754 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4755 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4756 Intrinsic IntId128> {
4757 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4759 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4760 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4761 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4763 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4766 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4769 let Predicates = [HasAVX] in
4770 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4771 int_x86_sse41_phminposuw>, VEX;
4772 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4773 int_x86_sse41_phminposuw>;
4775 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4776 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4777 Intrinsic IntId128, bit Is2Addr = 1> {
4778 let isCommutable = 1 in
4779 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4780 (ins VR128:$src1, VR128:$src2),
4782 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4783 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4784 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4785 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4786 (ins VR128:$src1, i128mem:$src2),
4788 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4789 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4791 (IntId128 VR128:$src1,
4792 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4795 let Predicates = [HasAVX] in {
4796 let isCommutable = 0 in
4797 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4799 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4801 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4803 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4805 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4807 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4809 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4811 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4813 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4815 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4817 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4821 let Constraints = "$src1 = $dst" in {
4822 let isCommutable = 0 in
4823 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4824 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4825 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4826 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4827 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4828 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4829 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4830 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4831 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4832 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4833 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4836 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4837 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4838 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4839 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4841 /// SS48I_binop_rm - Simple SSE41 binary operator.
4842 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4843 ValueType OpVT, bit Is2Addr = 1> {
4844 let isCommutable = 1 in
4845 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4846 (ins VR128:$src1, VR128:$src2),
4848 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4849 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4850 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4852 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4853 (ins VR128:$src1, i128mem:$src2),
4855 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4856 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4857 [(set VR128:$dst, (OpNode VR128:$src1,
4858 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4862 let Predicates = [HasAVX] in
4863 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4864 let Constraints = "$src1 = $dst" in
4865 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4867 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4868 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4869 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4870 X86MemOperand x86memop, bit Is2Addr = 1> {
4871 let isCommutable = 1 in
4872 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4873 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
4875 !strconcat(OpcodeStr,
4876 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4877 !strconcat(OpcodeStr,
4878 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4879 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4881 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4882 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
4884 !strconcat(OpcodeStr,
4885 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4886 !strconcat(OpcodeStr,
4887 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4890 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4894 let Predicates = [HasAVX] in {
4895 let isCommutable = 0 in {
4896 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4897 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4898 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4899 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4900 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
4901 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4902 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
4903 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4904 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4905 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4906 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4907 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4909 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4910 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4911 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4912 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4913 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
4914 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4917 let Constraints = "$src1 = $dst" in {
4918 let isCommutable = 0 in {
4919 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4920 VR128, memopv16i8, i128mem>;
4921 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4922 VR128, memopv16i8, i128mem>;
4923 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4924 VR128, memopv16i8, i128mem>;
4925 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4926 VR128, memopv16i8, i128mem>;
4928 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4929 VR128, memopv16i8, i128mem>;
4930 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4931 VR128, memopv16i8, i128mem>;
4934 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4935 let Predicates = [HasAVX] in {
4936 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4937 RegisterClass RC, X86MemOperand x86memop,
4938 PatFrag mem_frag, Intrinsic IntId> {
4939 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4940 (ins RC:$src1, RC:$src2, RC:$src3),
4941 !strconcat(OpcodeStr,
4942 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4943 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4944 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4946 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4947 (ins RC:$src1, x86memop:$src2, RC:$src3),
4948 !strconcat(OpcodeStr,
4949 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4951 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
4953 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4957 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
4958 memopv16i8, int_x86_sse41_blendvpd>;
4959 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
4960 memopv16i8, int_x86_sse41_blendvps>;
4961 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
4962 memopv16i8, int_x86_sse41_pblendvb>;
4963 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
4964 memopv32i8, int_x86_avx_blendv_pd_256>;
4965 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
4966 memopv32i8, int_x86_avx_blendv_ps_256>;
4968 /// SS41I_ternary_int - SSE 4.1 ternary operator
4969 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4970 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4971 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4972 (ins VR128:$src1, VR128:$src2),
4973 !strconcat(OpcodeStr,
4974 "\t{$src2, $dst|$dst, $src2}"),
4975 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4978 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4979 (ins VR128:$src1, i128mem:$src2),
4980 !strconcat(OpcodeStr,
4981 "\t{$src2, $dst|$dst, $src2}"),
4984 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4988 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4989 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4990 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4992 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
4993 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
4995 let Predicates = [HasAVX] in
4996 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4997 "vmovntdqa\t{$src, $dst|$dst, $src}",
4998 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
5000 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5001 "movntdqa\t{$src, $dst|$dst, $src}",
5002 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
5005 //===----------------------------------------------------------------------===//
5006 // SSE4.2 - Compare Instructions
5007 //===----------------------------------------------------------------------===//
5009 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
5010 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
5011 Intrinsic IntId128, bit Is2Addr = 1> {
5012 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
5013 (ins VR128:$src1, VR128:$src2),
5015 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5016 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5017 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5019 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
5020 (ins VR128:$src1, i128mem:$src2),
5022 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5023 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5025 (IntId128 VR128:$src1,
5026 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5029 let Predicates = [HasAVX] in
5030 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
5032 let Constraints = "$src1 = $dst" in
5033 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
5035 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
5036 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
5037 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
5038 (PCMPGTQrm VR128:$src1, addr:$src2)>;
5040 //===----------------------------------------------------------------------===//
5041 // SSE4.2 - String/text Processing Instructions
5042 //===----------------------------------------------------------------------===//
5044 // Packed Compare Implicit Length Strings, Return Mask
5045 multiclass pseudo_pcmpistrm<string asm> {
5046 def REG : PseudoI<(outs VR128:$dst),
5047 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5048 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
5050 def MEM : PseudoI<(outs VR128:$dst),
5051 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5052 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
5053 VR128:$src1, (load addr:$src2), imm:$src3))]>;
5056 let Defs = [EFLAGS], usesCustomInserter = 1 in {
5057 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
5058 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
5061 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
5062 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5063 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5064 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5065 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5066 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5067 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5070 let Defs = [XMM0, EFLAGS] in {
5071 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5072 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5073 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5074 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5075 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5076 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5079 // Packed Compare Explicit Length Strings, Return Mask
5080 multiclass pseudo_pcmpestrm<string asm> {
5081 def REG : PseudoI<(outs VR128:$dst),
5082 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5083 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5084 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
5085 def MEM : PseudoI<(outs VR128:$dst),
5086 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5087 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
5088 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
5091 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
5092 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
5093 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
5096 let Predicates = [HasAVX],
5097 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5098 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5099 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5100 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5101 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5102 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5103 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
5106 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
5107 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
5108 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5109 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5110 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5111 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5112 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5115 // Packed Compare Implicit Length Strings, Return Index
5116 let Defs = [ECX, EFLAGS] in {
5117 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
5118 def rr : SS42AI<0x63, MRMSrcReg, (outs),
5119 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5120 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5121 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
5122 (implicit EFLAGS)]>, OpSize;
5123 def rm : SS42AI<0x63, MRMSrcMem, (outs),
5124 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5125 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5126 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
5127 (implicit EFLAGS)]>, OpSize;
5131 let Predicates = [HasAVX] in {
5132 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
5134 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
5136 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
5138 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
5140 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
5142 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
5146 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
5147 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
5148 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
5149 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
5150 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
5151 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
5153 // Packed Compare Explicit Length Strings, Return Index
5154 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
5155 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
5156 def rr : SS42AI<0x61, MRMSrcReg, (outs),
5157 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5158 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5159 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
5160 (implicit EFLAGS)]>, OpSize;
5161 def rm : SS42AI<0x61, MRMSrcMem, (outs),
5162 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5163 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5165 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
5166 (implicit EFLAGS)]>, OpSize;
5170 let Predicates = [HasAVX] in {
5171 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
5173 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
5175 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
5177 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
5179 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
5181 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
5185 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
5186 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
5187 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
5188 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
5189 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
5190 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
5192 //===----------------------------------------------------------------------===//
5193 // SSE4.2 - CRC Instructions
5194 //===----------------------------------------------------------------------===//
5196 // No CRC instructions have AVX equivalents
5198 // crc intrinsic instruction
5199 // This set of instructions are only rm, the only difference is the size
5201 let Constraints = "$src1 = $dst" in {
5202 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5203 (ins GR32:$src1, i8mem:$src2),
5204 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5206 (int_x86_sse42_crc32_32_8 GR32:$src1,
5207 (load addr:$src2)))]>;
5208 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5209 (ins GR32:$src1, GR8:$src2),
5210 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5212 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
5213 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5214 (ins GR32:$src1, i16mem:$src2),
5215 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5217 (int_x86_sse42_crc32_32_16 GR32:$src1,
5218 (load addr:$src2)))]>,
5220 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5221 (ins GR32:$src1, GR16:$src2),
5222 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5224 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
5226 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5227 (ins GR32:$src1, i32mem:$src2),
5228 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5230 (int_x86_sse42_crc32_32_32 GR32:$src1,
5231 (load addr:$src2)))]>;
5232 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5233 (ins GR32:$src1, GR32:$src2),
5234 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5236 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
5237 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5238 (ins GR64:$src1, i8mem:$src2),
5239 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5241 (int_x86_sse42_crc32_64_8 GR64:$src1,
5242 (load addr:$src2)))]>,
5244 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5245 (ins GR64:$src1, GR8:$src2),
5246 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5248 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
5250 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5251 (ins GR64:$src1, i64mem:$src2),
5252 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5254 (int_x86_sse42_crc32_64_64 GR64:$src1,
5255 (load addr:$src2)))]>,
5257 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5258 (ins GR64:$src1, GR64:$src2),
5259 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5261 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
5265 //===----------------------------------------------------------------------===//
5266 // AES-NI Instructions
5267 //===----------------------------------------------------------------------===//
5269 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5270 Intrinsic IntId128, bit Is2Addr = 1> {
5271 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5272 (ins VR128:$src1, VR128:$src2),
5274 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5275 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5276 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5278 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5279 (ins VR128:$src1, i128mem:$src2),
5281 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5282 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5284 (IntId128 VR128:$src1,
5285 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5288 // Perform One Round of an AES Encryption/Decryption Flow
5289 let Predicates = [HasAVX, HasAES] in {
5290 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5291 int_x86_aesni_aesenc, 0>, VEX_4V;
5292 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5293 int_x86_aesni_aesenclast, 0>, VEX_4V;
5294 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5295 int_x86_aesni_aesdec, 0>, VEX_4V;
5296 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5297 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5300 let Constraints = "$src1 = $dst" in {
5301 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5302 int_x86_aesni_aesenc>;
5303 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5304 int_x86_aesni_aesenclast>;
5305 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5306 int_x86_aesni_aesdec>;
5307 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5308 int_x86_aesni_aesdeclast>;
5311 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5312 (AESENCrr VR128:$src1, VR128:$src2)>;
5313 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5314 (AESENCrm VR128:$src1, addr:$src2)>;
5315 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5316 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5317 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5318 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5319 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5320 (AESDECrr VR128:$src1, VR128:$src2)>;
5321 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5322 (AESDECrm VR128:$src1, addr:$src2)>;
5323 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5324 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5325 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5326 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5328 // Perform the AES InvMixColumn Transformation
5329 let Predicates = [HasAVX, HasAES] in {
5330 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5332 "vaesimc\t{$src1, $dst|$dst, $src1}",
5334 (int_x86_aesni_aesimc VR128:$src1))]>,
5336 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5337 (ins i128mem:$src1),
5338 "vaesimc\t{$src1, $dst|$dst, $src1}",
5340 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5343 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5345 "aesimc\t{$src1, $dst|$dst, $src1}",
5347 (int_x86_aesni_aesimc VR128:$src1))]>,
5349 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5350 (ins i128mem:$src1),
5351 "aesimc\t{$src1, $dst|$dst, $src1}",
5353 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5356 // AES Round Key Generation Assist
5357 let Predicates = [HasAVX, HasAES] in {
5358 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5359 (ins VR128:$src1, i8imm:$src2),
5360 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5362 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5364 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5365 (ins i128mem:$src1, i8imm:$src2),
5366 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5368 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5372 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5373 (ins VR128:$src1, i8imm:$src2),
5374 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5376 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5378 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5379 (ins i128mem:$src1, i8imm:$src2),
5380 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5382 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5386 //===----------------------------------------------------------------------===//
5387 // CLMUL Instructions
5388 //===----------------------------------------------------------------------===//
5390 // Carry-less Multiplication instructions
5391 let Constraints = "$src1 = $dst" in {
5392 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5393 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5394 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5397 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5398 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5399 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5403 // AVX carry-less Multiplication instructions
5404 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5405 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5406 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5409 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5410 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5411 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5415 multiclass pclmul_alias<string asm, int immop> {
5416 def : InstAlias<!strconcat("pclmul", asm,
5417 "dq {$src, $dst|$dst, $src}"),
5418 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
5420 def : InstAlias<!strconcat("pclmul", asm,
5421 "dq {$src, $dst|$dst, $src}"),
5422 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
5424 def : InstAlias<!strconcat("vpclmul", asm,
5425 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5426 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
5428 def : InstAlias<!strconcat("vpclmul", asm,
5429 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5430 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
5432 defm : pclmul_alias<"hqhq", 0x11>;
5433 defm : pclmul_alias<"hqlq", 0x01>;
5434 defm : pclmul_alias<"lqhq", 0x10>;
5435 defm : pclmul_alias<"lqlq", 0x00>;
5437 //===----------------------------------------------------------------------===//
5439 //===----------------------------------------------------------------------===//
5441 //===----------------------------------------------------------------------===//
5442 // VBROADCAST - Load from memory and broadcast to all elements of the
5443 // destination operand
5445 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5446 X86MemOperand x86memop, Intrinsic Int> :
5447 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5448 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5449 [(set RC:$dst, (Int addr:$src))]>, VEX;
5451 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5452 int_x86_avx_vbroadcastss>;
5453 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5454 int_x86_avx_vbroadcastss_256>;
5455 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5456 int_x86_avx_vbroadcast_sd_256>;
5457 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5458 int_x86_avx_vbroadcastf128_pd_256>;
5460 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5461 (VBROADCASTF128 addr:$src)>;
5463 //===----------------------------------------------------------------------===//
5464 // VINSERTF128 - Insert packed floating-point values
5466 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5467 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5468 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5470 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5471 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5472 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5475 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5476 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5477 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5478 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5479 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5480 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5482 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
5484 (VINSERTF128rr VR256:$src1, VR128:$src2,
5485 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5486 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
5488 (VINSERTF128rr VR256:$src1, VR128:$src2,
5489 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5490 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
5492 (VINSERTF128rr VR256:$src1, VR128:$src2,
5493 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5494 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
5496 (VINSERTF128rr VR256:$src1, VR128:$src2,
5497 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5498 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
5500 (VINSERTF128rr VR256:$src1, VR128:$src2,
5501 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5502 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
5504 (VINSERTF128rr VR256:$src1, VR128:$src2,
5505 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5507 // Special COPY patterns
5508 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
5509 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5510 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
5511 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5512 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
5513 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5514 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
5515 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5516 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
5517 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5518 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
5519 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5521 //===----------------------------------------------------------------------===//
5522 // VEXTRACTF128 - Extract packed floating-point values
5524 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5525 (ins VR256:$src1, i8imm:$src2),
5526 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5528 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5529 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5530 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5533 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
5534 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5535 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
5536 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5537 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
5538 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5540 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5541 (v4f32 (VEXTRACTF128rr
5542 (v8f32 VR256:$src1),
5543 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5544 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5545 (v2f64 (VEXTRACTF128rr
5546 (v4f64 VR256:$src1),
5547 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5548 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5549 (v4i32 (VEXTRACTF128rr
5550 (v8i32 VR256:$src1),
5551 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5552 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5553 (v2i64 (VEXTRACTF128rr
5554 (v4i64 VR256:$src1),
5555 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5556 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5557 (v8i16 (VEXTRACTF128rr
5558 (v16i16 VR256:$src1),
5559 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5560 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5561 (v16i8 (VEXTRACTF128rr
5562 (v32i8 VR256:$src1),
5563 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5565 // Special COPY patterns
5566 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
5567 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
5568 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
5569 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
5571 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
5572 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
5573 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
5574 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
5577 //===----------------------------------------------------------------------===//
5578 // VMASKMOV - Conditional SIMD Packed Loads and Stores
5580 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
5581 Intrinsic IntLd, Intrinsic IntLd256,
5582 Intrinsic IntSt, Intrinsic IntSt256,
5583 PatFrag pf128, PatFrag pf256> {
5584 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5585 (ins VR128:$src1, f128mem:$src2),
5586 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5587 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
5589 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5590 (ins VR256:$src1, f256mem:$src2),
5591 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5592 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
5594 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5595 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5596 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5597 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
5598 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5599 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5600 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5601 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
5604 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
5605 int_x86_avx_maskload_ps,
5606 int_x86_avx_maskload_ps_256,
5607 int_x86_avx_maskstore_ps,
5608 int_x86_avx_maskstore_ps_256,
5609 memopv4f32, memopv8f32>;
5610 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
5611 int_x86_avx_maskload_pd,
5612 int_x86_avx_maskload_pd_256,
5613 int_x86_avx_maskstore_pd,
5614 int_x86_avx_maskstore_pd_256,
5615 memopv2f64, memopv4f64>;
5617 //===----------------------------------------------------------------------===//
5618 // VPERMIL - Permute Single and Double Floating-Point Values
5620 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5621 RegisterClass RC, X86MemOperand x86memop_f,
5622 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5623 Intrinsic IntVar, Intrinsic IntImm> {
5624 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5625 (ins RC:$src1, RC:$src2),
5626 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5627 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5628 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5629 (ins RC:$src1, x86memop_i:$src2),
5630 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5631 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5633 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5634 (ins RC:$src1, i8imm:$src2),
5635 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5636 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5637 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5638 (ins x86memop_f:$src1, i8imm:$src2),
5639 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5640 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5643 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5644 memopv4f32, memopv4i32,
5645 int_x86_avx_vpermilvar_ps,
5646 int_x86_avx_vpermil_ps>;
5647 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5648 memopv8f32, memopv8i32,
5649 int_x86_avx_vpermilvar_ps_256,
5650 int_x86_avx_vpermil_ps_256>;
5651 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5652 memopv2f64, memopv2i64,
5653 int_x86_avx_vpermilvar_pd,
5654 int_x86_avx_vpermil_pd>;
5655 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5656 memopv4f64, memopv4i64,
5657 int_x86_avx_vpermilvar_pd_256,
5658 int_x86_avx_vpermil_pd_256>;
5660 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
5661 (VPERMILPSYri VR256:$src1, imm:$imm)>;
5662 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
5663 (VPERMILPDYri VR256:$src1, imm:$imm)>;
5664 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
5665 (VPERMILPSYri VR256:$src1, imm:$imm)>;
5666 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
5667 (VPERMILPDYri VR256:$src1, imm:$imm)>;
5669 //===----------------------------------------------------------------------===//
5670 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
5672 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5673 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5674 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5676 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5677 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5678 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5681 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5682 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5683 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5684 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5685 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5686 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5688 def : Pat<(int_x86_avx_vperm2f128_ps_256
5689 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5690 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5691 def : Pat<(int_x86_avx_vperm2f128_pd_256
5692 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5693 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5694 def : Pat<(int_x86_avx_vperm2f128_si_256
5695 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5696 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5698 //===----------------------------------------------------------------------===//
5699 // VZERO - Zero YMM registers
5701 // Zero All YMM registers
5702 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
5703 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
5705 // Zero Upper bits of YMM registers
5706 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
5707 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
5709 //===----------------------------------------------------------------------===//
5710 // SSE Shuffle pattern fragments
5711 //===----------------------------------------------------------------------===//
5713 // This is part of a "work in progress" refactoring. The idea is that all
5714 // vector shuffles are going to be translated into target specific nodes and
5715 // directly matched by the patterns below (which can be changed along the way)
5716 // The AVX version of some but not all of them are described here, and more
5717 // should come in a near future.
5719 // Shuffle with PSHUFD instruction folding loads. The first two patterns match
5720 // SSE2 loads, which are always promoted to v2i64. The last one should match
5721 // the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD
5722 // in SSE2, how does it ever worked? Anyway, the pattern will remain here until
5723 // we investigate further.
5724 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5726 (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
5727 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5729 (PSHUFDmi addr:$src1, imm:$imm)>;
5730 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
5732 (PSHUFDmi addr:$src1, imm:$imm)>; // FIXME: has this ever worked?
5734 // Shuffle with PSHUFD instruction.
5735 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5736 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5737 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5738 (PSHUFDri VR128:$src1, imm:$imm)>;
5740 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5741 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5742 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5743 (PSHUFDri VR128:$src1, imm:$imm)>;
5745 // Shuffle with SHUFPD instruction.
5746 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5747 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5748 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5749 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5750 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5751 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
5753 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5754 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5755 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5756 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5758 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5759 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5760 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5761 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5763 // Shuffle with SHUFPS instruction.
5764 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5765 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5766 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5767 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5768 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5769 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5771 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5772 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5773 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5774 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5776 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5777 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5778 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5779 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5780 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5781 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5783 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5784 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5785 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5786 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5788 // Shuffle with MOVHLPS instruction
5789 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
5790 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5791 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
5792 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5794 // Shuffle with MOVDDUP instruction
5795 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5796 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5797 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5798 (MOVDDUPrm addr:$src)>;
5800 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5801 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5802 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5803 (MOVDDUPrm addr:$src)>;
5805 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5806 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5807 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5808 (MOVDDUPrm addr:$src)>;
5810 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5811 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5812 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5813 (MOVDDUPrm addr:$src)>;
5815 def : Pat<(X86Movddup (bc_v2f64
5816 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5817 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5818 def : Pat<(X86Movddup (bc_v2f64
5819 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5820 (MOVDDUPrm addr:$src)>;
5823 // Shuffle with UNPCKLPS
5824 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5825 (VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5826 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5827 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
5829 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5830 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5831 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5832 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
5834 // Shuffle with VUNPCKHPSY
5835 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
5836 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5837 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
5838 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5839 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
5840 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5841 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
5842 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5844 // Shuffle with UNPCKHPS
5845 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5846 (VUNPCKHPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5847 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5848 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
5850 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5851 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5852 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5853 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
5855 // Shuffle with VUNPCKHPSY
5856 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
5857 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5858 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
5859 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5861 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
5862 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5863 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
5864 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5866 // Shuffle with UNPCKLPD
5867 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5868 (VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5869 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5870 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
5872 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5873 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5874 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5875 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
5877 // Shuffle with VUNPCKLPDY
5878 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
5879 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5880 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
5881 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5883 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
5884 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5885 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
5886 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5888 // Shuffle with UNPCKHPD
5889 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5890 (VUNPCKHPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5891 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5892 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
5894 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5895 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5896 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5897 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
5899 // Shuffle with VUNPCKHPDY
5900 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
5901 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5902 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
5903 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5904 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
5905 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5906 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
5907 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5909 // Shuffle with MOVLHPS
5910 def : Pat<(X86Movlhps VR128:$src1,
5911 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5912 (MOVHPSrm VR128:$src1, addr:$src2)>;
5913 def : Pat<(X86Movlhps VR128:$src1,
5914 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
5915 (MOVHPSrm VR128:$src1, addr:$src2)>;
5916 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
5917 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5918 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
5919 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5920 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
5921 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
5923 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem
5924 // is during lowering, where it's not possible to recognize the load fold cause
5925 // it has two uses through a bitcast. One use disappears at isel time and the
5926 // fold opportunity reappears.
5927 def : Pat<(v2f64 (X86Movddup VR128:$src)),
5928 (UNPCKLPDrr VR128:$src, VR128:$src)>;
5930 // Shuffle with MOVLHPD
5931 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
5932 (scalar_to_vector (loadf64 addr:$src2)))),
5933 (MOVHPDrm VR128:$src1, addr:$src2)>;
5935 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
5936 // is during lowering, where it's not possible to recognize the load fold cause
5937 // it has two uses through a bitcast. One use disappears at isel time and the
5938 // fold opportunity reappears.
5939 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
5940 (scalar_to_vector (loadf64 addr:$src2)))),
5941 (MOVHPDrm VR128:$src1, addr:$src2)>;
5943 // Shuffle with MOVSS
5944 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
5945 (MOVSSrr VR128:$src1, FR32:$src2)>;
5946 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
5947 (MOVSSrr (v4i32 VR128:$src1),
5948 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
5949 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
5950 (MOVSSrr (v4f32 VR128:$src1),
5951 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
5953 // Shuffle with MOVSD
5954 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
5955 (MOVSDrr VR128:$src1, FR64:$src2)>;
5956 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
5957 (MOVSDrr (v2i64 VR128:$src1),
5958 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
5959 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
5960 (MOVSDrr (v2f64 VR128:$src1),
5961 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
5962 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
5963 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5964 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
5965 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5967 // Shuffle with PSHUFHW
5968 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
5969 (PSHUFHWri VR128:$src, imm:$imm)>;
5970 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5971 (PSHUFHWmi addr:$src, imm:$imm)>;
5973 // Shuffle with PSHUFLW
5974 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
5975 (PSHUFLWri VR128:$src, imm:$imm)>;
5976 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5977 (PSHUFLWmi addr:$src, imm:$imm)>;
5979 // Shuffle with MOVLPS
5980 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
5981 (MOVLPSrm VR128:$src1, addr:$src2)>;
5982 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
5983 (MOVLPSrm VR128:$src1, addr:$src2)>;
5984 def : Pat<(X86Movlps VR128:$src1,
5985 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5986 (MOVLPSrm VR128:$src1, addr:$src2)>;
5987 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
5988 // is during lowering, where it's not possible to recognize the load fold cause
5989 // it has two uses through a bitcast. One use disappears at isel time and the
5990 // fold opportunity reappears.
5991 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
5992 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5994 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
5995 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5997 // Shuffle with MOVLPD
5998 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5999 (MOVLPDrm VR128:$src1, addr:$src2)>;
6000 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
6001 (MOVLPDrm VR128:$src1, addr:$src2)>;
6002 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
6003 (scalar_to_vector (loadf64 addr:$src2)))),
6004 (MOVLPDrm VR128:$src1, addr:$src2)>;
6006 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
6007 def : Pat<(store (f64 (vector_extract
6008 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
6009 (MOVHPSmr addr:$dst, VR128:$src)>;
6010 def : Pat<(store (f64 (vector_extract
6011 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
6012 (MOVHPDmr addr:$dst, VR128:$src)>;
6014 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
6015 (MOVLPSmr addr:$src1, VR128:$src2)>;
6016 def : Pat<(store (v4i32 (X86Movlps
6017 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
6018 (MOVLPSmr addr:$src1, VR128:$src2)>;
6020 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
6021 (MOVLPDmr addr:$src1, VR128:$src2)>;
6022 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
6023 (MOVLPDmr addr:$src1, VR128:$src2)>;