1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 bit rr_hasSideEffects = 0> {
208 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 pat_rr, IIC_DEFAULT, d>;
214 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 pat_rm, IIC_DEFAULT, d>;
221 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
222 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 string asm, string SSEVer, string FPSizeStr,
224 X86MemOperand x86memop, PatFrag mem_frag,
225 Domain d, OpndItins itins, bit Is2Addr = 1> {
226 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
228 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
229 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
230 [(set RC:$dst, (!cast<Intrinsic>(
231 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
232 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
233 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
235 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
236 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
237 [(set RC:$dst, (!cast<Intrinsic>(
238 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
239 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
242 //===----------------------------------------------------------------------===//
243 // Non-instruction patterns
244 //===----------------------------------------------------------------------===//
246 // A vector extract of the first f32/f64 position is a subregister copy
247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
249 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
250 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
252 // A 128-bit subvector extract from the first 256-bit vector position
253 // is a subregister copy that needs no instruction.
254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
261 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
264 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
266 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
269 // A 128-bit subvector insert to the first 256-bit vector position
270 // is a subregister copy that needs no instruction.
271 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
272 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
273 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
274 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
275 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
276 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
278 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
280 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
282 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
284 // Implicitly promote a 32-bit scalar to a vector.
285 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
286 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
287 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
288 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
289 // Implicitly promote a 64-bit scalar to a vector.
290 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
291 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
292 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
293 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
295 // Bitcasts between 128-bit vector types. Return the original type since
296 // no instruction is needed for the conversion
297 let Predicates = [HasSSE2] in {
298 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
299 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
300 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
304 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
309 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
314 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
319 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
324 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
330 // Bitcasts between 256-bit vector types. Return the original type since
331 // no instruction is needed for the conversion
332 let Predicates = [HasAVX] in {
333 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
334 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
335 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
339 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
344 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
349 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
354 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
359 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
365 // Alias instructions that map fld0 to pxor for sse.
366 // This is expanded by ExpandPostRAPseudos.
367 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
369 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
370 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
371 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
372 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
375 //===----------------------------------------------------------------------===//
376 // AVX & SSE - Zero/One Vectors
377 //===----------------------------------------------------------------------===//
379 // Alias instruction that maps zero vector to pxor / xorp* for sse.
380 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
381 // swizzled by ExecutionDepsFix to pxor.
382 // We set canFoldAsLoad because this can be converted to a constant-pool
383 // load of an all-zeros value if folding it would be beneficial.
384 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
385 isPseudo = 1, neverHasSideEffects = 1 in {
386 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
389 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
390 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
391 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
392 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
393 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
394 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
397 // The same as done above but for AVX. The 256-bit ISA does not support PI,
398 // and doesn't need it because on sandy bridge the register is set to zero
399 // at the rename stage without using any execution unit, so SET0PSY
400 // and SET0PDY can be used for vector int instructions without penalty
401 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
402 // JIT implementatioan, it does not expand the instructions below like
403 // X86MCInstLower does.
404 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
405 isCodeGenOnly = 1 in {
406 let Predicates = [HasAVX] in {
407 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
408 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
409 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
410 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
412 let Predicates = [HasAVX2], neverHasSideEffects = 1 in
413 def AVX2_SET0 : PDI<0xef, MRMInitReg, (outs VR256:$dst), (ins), "",
417 let Predicates = [HasAVX2], AddedComplexity = 5 in {
418 def : Pat<(v4i64 immAllZerosV), (AVX2_SET0)>;
419 def : Pat<(v8i32 immAllZerosV), (AVX2_SET0)>;
420 def : Pat<(v16i16 immAllZerosV), (AVX2_SET0)>;
421 def : Pat<(v32i8 immAllZerosV), (AVX2_SET0)>;
424 // AVX has no support for 256-bit integer instructions, but since the 128-bit
425 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
426 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
427 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
428 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
430 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
431 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
432 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
434 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
435 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
436 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
438 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
439 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
440 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
442 // We set canFoldAsLoad because this can be converted to a constant-pool
443 // load of an all-ones value if folding it would be beneficial.
444 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
445 // JIT implementation, it does not expand the instructions below like
446 // X86MCInstLower does.
447 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
448 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
449 let Predicates = [HasAVX] in
450 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
451 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
452 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
453 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
454 let Predicates = [HasAVX2] in
455 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
456 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
460 //===----------------------------------------------------------------------===//
461 // SSE 1 & 2 - Move FP Scalar Instructions
463 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
464 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
465 // is used instead. Register-to-register movss/movsd is not modeled as an
466 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
467 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
468 //===----------------------------------------------------------------------===//
470 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
471 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
472 [(set VR128:$dst, (vt (OpNode VR128:$src1,
473 (scalar_to_vector RC:$src2))))],
476 // Loading from memory automatically zeroing upper bits.
477 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
478 PatFrag mem_pat, string OpcodeStr> :
479 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
480 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
481 [(set RC:$dst, (mem_pat addr:$src))],
485 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
486 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
488 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
489 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
492 // For the disassembler
493 let isCodeGenOnly = 1 in {
494 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
495 (ins VR128:$src1, FR32:$src2),
496 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
499 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
500 (ins VR128:$src1, FR64:$src2),
501 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
506 let canFoldAsLoad = 1, isReMaterializable = 1 in {
507 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
509 let AddedComplexity = 20 in
510 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
514 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
515 "movss\t{$src, $dst|$dst, $src}",
516 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
518 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
519 "movsd\t{$src, $dst|$dst, $src}",
520 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
524 let Constraints = "$src1 = $dst" in {
525 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
526 "movss\t{$src2, $dst|$dst, $src2}">, XS;
527 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
528 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
530 // For the disassembler
531 let isCodeGenOnly = 1 in {
532 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
533 (ins VR128:$src1, FR32:$src2),
534 "movss\t{$src2, $dst|$dst, $src2}", [],
535 IIC_SSE_MOV_S_RR>, XS;
536 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
537 (ins VR128:$src1, FR64:$src2),
538 "movsd\t{$src2, $dst|$dst, $src2}", [],
539 IIC_SSE_MOV_S_RR>, XD;
543 let canFoldAsLoad = 1, isReMaterializable = 1 in {
544 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
546 let AddedComplexity = 20 in
547 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
550 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
551 "movss\t{$src, $dst|$dst, $src}",
552 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
553 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
554 "movsd\t{$src, $dst|$dst, $src}",
555 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
558 let Predicates = [HasAVX] in {
559 let AddedComplexity = 15 in {
560 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
561 // MOVS{S,D} to the lower bits.
562 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
563 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
564 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
565 (VMOVSSrr (v4f32 (V_SET0)),
566 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
567 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
568 (VMOVSSrr (v4i32 (V_SET0)),
569 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
570 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
571 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
573 // Move low f32 and clear high bits.
574 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
575 (SUBREG_TO_REG (i32 0),
576 (VMOVSSrr (v4f32 (V_SET0)),
577 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_ss)), sub_xmm)>;
578 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
579 (SUBREG_TO_REG (i32 0),
580 (VMOVSSrr (v4i32 (V_SET0)),
581 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_ss)), sub_xmm)>;
584 let AddedComplexity = 20 in {
585 // MOVSSrm zeros the high parts of the register; represent this
586 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
587 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
588 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
589 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
590 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
591 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
592 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
594 // MOVSDrm zeros the high parts of the register; represent this
595 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
596 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
597 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
598 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
599 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
600 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
601 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
602 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
603 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
604 def : Pat<(v2f64 (X86vzload addr:$src)),
605 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
607 // Represent the same patterns above but in the form they appear for
609 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
610 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
611 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
612 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
613 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
614 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
615 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
616 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
617 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
619 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
620 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
621 (SUBREG_TO_REG (i32 0),
622 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
624 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
625 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
626 (SUBREG_TO_REG (i64 0),
627 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
629 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
630 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
631 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
633 // Move low f64 and clear high bits.
634 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
635 (SUBREG_TO_REG (i32 0),
636 (VMOVSDrr (v2f64 (V_SET0)),
637 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_sd)), sub_xmm)>;
639 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
640 (SUBREG_TO_REG (i32 0),
641 (VMOVSDrr (v2i64 (V_SET0)),
642 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_sd)), sub_xmm)>;
644 // Extract and store.
645 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
648 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
649 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
652 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
654 // Shuffle with VMOVSS
655 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
656 (VMOVSSrr (v4i32 VR128:$src1),
657 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
658 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
659 (VMOVSSrr (v4f32 VR128:$src1),
660 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
663 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
664 (SUBREG_TO_REG (i32 0),
665 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_ss),
666 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_ss)), sub_xmm)>;
667 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
668 (SUBREG_TO_REG (i32 0),
669 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_ss),
670 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_ss)), sub_xmm)>;
672 // Shuffle with VMOVSD
673 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
674 (VMOVSDrr (v2i64 VR128:$src1),
675 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
676 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
677 (VMOVSDrr (v2f64 VR128:$src1),
678 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
679 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
680 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
682 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
683 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
687 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
688 (SUBREG_TO_REG (i32 0),
689 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_sd),
690 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_sd)), sub_xmm)>;
691 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_sd),
694 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_sd)), sub_xmm)>;
697 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
698 // is during lowering, where it's not possible to recognize the fold cause
699 // it has two uses through a bitcast. One use disappears at isel time and the
700 // fold opportunity reappears.
701 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
702 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
704 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
705 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),
707 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
708 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
710 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
715 let Predicates = [HasSSE1] in {
716 let AddedComplexity = 15 in {
717 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
718 // MOVSS to the lower bits.
719 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
720 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
721 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
722 (MOVSSrr (v4f32 (V_SET0)),
723 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)),
726 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
729 let AddedComplexity = 20 in {
730 // MOVSSrm zeros the high parts of the register; represent this
731 // with SUBREG_TO_REG.
732 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
733 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
734 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
735 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
736 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
737 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
740 // Extract and store.
741 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
744 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
746 // Shuffle with MOVSS
747 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
748 (MOVSSrr (v4i32 VR128:$src1),
749 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
750 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
751 (MOVSSrr (v4f32 VR128:$src1),
752 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
755 let Predicates = [HasSSE2] in {
756 let AddedComplexity = 15 in {
757 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
758 // MOVSD to the lower bits.
759 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
760 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
763 let AddedComplexity = 20 in {
764 // MOVSDrm zeros the high parts of the register; represent this
765 // with SUBREG_TO_REG.
766 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
767 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
768 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
769 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
770 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
771 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
772 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
773 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
774 def : Pat<(v2f64 (X86vzload addr:$src)),
775 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
778 // Extract and store.
779 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
782 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
784 // Shuffle with MOVSD
785 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
786 (MOVSDrr (v2i64 VR128:$src1),
787 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
788 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
789 (MOVSDrr (v2f64 VR128:$src1),
790 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
791 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
793 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
796 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
797 // is during lowering, where it's not possible to recognize the fold cause
798 // it has two uses through a bitcast. One use disappears at isel time and the
799 // fold opportunity reappears.
800 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
801 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
802 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
803 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
804 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
805 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
806 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
807 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
810 //===----------------------------------------------------------------------===//
811 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
812 //===----------------------------------------------------------------------===//
814 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
815 X86MemOperand x86memop, PatFrag ld_frag,
816 string asm, Domain d,
818 bit IsReMaterializable = 1> {
819 let neverHasSideEffects = 1 in
820 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
821 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
822 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
823 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
824 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
825 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
828 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
829 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
831 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
832 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
834 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
835 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
837 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
838 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
841 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
842 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
844 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
845 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
847 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
848 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
850 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
851 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
853 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
854 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
856 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
857 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
859 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
860 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
862 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
863 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
867 "movaps\t{$src, $dst|$dst, $src}",
868 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
869 IIC_SSE_MOVA_P_MR>, VEX;
870 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
871 "movapd\t{$src, $dst|$dst, $src}",
872 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
873 IIC_SSE_MOVA_P_MR>, VEX;
874 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
875 "movups\t{$src, $dst|$dst, $src}",
876 [(store (v4f32 VR128:$src), addr:$dst)],
877 IIC_SSE_MOVU_P_MR>, VEX;
878 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
879 "movupd\t{$src, $dst|$dst, $src}",
880 [(store (v2f64 VR128:$src), addr:$dst)],
881 IIC_SSE_MOVU_P_MR>, VEX;
882 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
883 "movaps\t{$src, $dst|$dst, $src}",
884 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
885 IIC_SSE_MOVA_P_MR>, VEX;
886 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
887 "movapd\t{$src, $dst|$dst, $src}",
888 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
889 IIC_SSE_MOVA_P_MR>, VEX;
890 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
891 "movups\t{$src, $dst|$dst, $src}",
892 [(store (v8f32 VR256:$src), addr:$dst)],
893 IIC_SSE_MOVU_P_MR>, VEX;
894 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
895 "movupd\t{$src, $dst|$dst, $src}",
896 [(store (v4f64 VR256:$src), addr:$dst)],
897 IIC_SSE_MOVU_P_MR>, VEX;
900 let isCodeGenOnly = 1 in {
901 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
903 "movaps\t{$src, $dst|$dst, $src}", [],
904 IIC_SSE_MOVA_P_RR>, VEX;
905 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
907 "movapd\t{$src, $dst|$dst, $src}", [],
908 IIC_SSE_MOVA_P_RR>, VEX;
909 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
911 "movups\t{$src, $dst|$dst, $src}", [],
912 IIC_SSE_MOVU_P_RR>, VEX;
913 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
915 "movupd\t{$src, $dst|$dst, $src}", [],
916 IIC_SSE_MOVU_P_RR>, VEX;
917 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
919 "movaps\t{$src, $dst|$dst, $src}", [],
920 IIC_SSE_MOVA_P_RR>, VEX;
921 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
923 "movapd\t{$src, $dst|$dst, $src}", [],
924 IIC_SSE_MOVA_P_RR>, VEX;
925 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
927 "movups\t{$src, $dst|$dst, $src}", [],
928 IIC_SSE_MOVU_P_RR>, VEX;
929 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
931 "movupd\t{$src, $dst|$dst, $src}", [],
932 IIC_SSE_MOVU_P_RR>, VEX;
935 let Predicates = [HasAVX] in {
936 def : Pat<(v8i32 (X86vzmovl
937 (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
938 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
939 def : Pat<(v4i64 (X86vzmovl
940 (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v8f32 (X86vzmovl
943 (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v4f64 (X86vzmovl
946 (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
951 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
952 (VMOVUPSYmr addr:$dst, VR256:$src)>;
953 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
954 (VMOVUPDYmr addr:$dst, VR256:$src)>;
956 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
957 "movaps\t{$src, $dst|$dst, $src}",
958 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
960 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movapd\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
964 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movups\t{$src, $dst|$dst, $src}",
966 [(store (v4f32 VR128:$src), addr:$dst)],
968 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movupd\t{$src, $dst|$dst, $src}",
970 [(store (v2f64 VR128:$src), addr:$dst)],
974 let isCodeGenOnly = 1 in {
975 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
976 "movaps\t{$src, $dst|$dst, $src}", [],
978 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
979 "movapd\t{$src, $dst|$dst, $src}", [],
981 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movups\t{$src, $dst|$dst, $src}", [],
984 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movupd\t{$src, $dst|$dst, $src}", [],
989 let Predicates = [HasAVX] in {
990 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
991 (VMOVUPSmr addr:$dst, VR128:$src)>;
992 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
993 (VMOVUPDmr addr:$dst, VR128:$src)>;
996 let Predicates = [HasSSE1] in
997 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
998 (MOVUPSmr addr:$dst, VR128:$src)>;
999 let Predicates = [HasSSE2] in
1000 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1001 (MOVUPDmr addr:$dst, VR128:$src)>;
1003 // Use vmovaps/vmovups for AVX integer load/store.
1004 let Predicates = [HasAVX] in {
1005 // 128-bit load/store
1006 def : Pat<(alignedloadv2i64 addr:$src),
1007 (VMOVAPSrm addr:$src)>;
1008 def : Pat<(loadv2i64 addr:$src),
1009 (VMOVUPSrm addr:$src)>;
1011 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1012 (VMOVAPSmr addr:$dst, VR128:$src)>;
1013 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1014 (VMOVAPSmr addr:$dst, VR128:$src)>;
1015 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1016 (VMOVAPSmr addr:$dst, VR128:$src)>;
1017 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1020 (VMOVUPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1022 (VMOVUPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1024 (VMOVUPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1028 // 256-bit load/store
1029 def : Pat<(alignedloadv4i64 addr:$src),
1030 (VMOVAPSYrm addr:$src)>;
1031 def : Pat<(loadv4i64 addr:$src),
1032 (VMOVUPSYrm addr:$src)>;
1033 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1034 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1035 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1036 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1037 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1038 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1039 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1042 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1044 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1046 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 // Use movaps / movups for SSE integer load / store (one byte shorter).
1052 // The instructions selected below are then converted to MOVDQA/MOVDQU
1053 // during the SSE domain pass.
1054 let Predicates = [HasSSE1] in {
1055 def : Pat<(alignedloadv2i64 addr:$src),
1056 (MOVAPSrm addr:$src)>;
1057 def : Pat<(loadv2i64 addr:$src),
1058 (MOVUPSrm addr:$src)>;
1060 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1061 (MOVAPSmr addr:$dst, VR128:$src)>;
1062 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1063 (MOVAPSmr addr:$dst, VR128:$src)>;
1064 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1065 (MOVAPSmr addr:$dst, VR128:$src)>;
1066 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1067 (MOVAPSmr addr:$dst, VR128:$src)>;
1068 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1069 (MOVUPSmr addr:$dst, VR128:$src)>;
1070 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1071 (MOVUPSmr addr:$dst, VR128:$src)>;
1072 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1073 (MOVUPSmr addr:$dst, VR128:$src)>;
1074 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1075 (MOVUPSmr addr:$dst, VR128:$src)>;
1078 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1079 // bits are disregarded. FIXME: Set encoding to pseudo!
1080 let neverHasSideEffects = 1 in {
1081 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1082 "movaps\t{$src, $dst|$dst, $src}", [],
1083 IIC_SSE_MOVA_P_RR>, VEX;
1084 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1085 "movapd\t{$src, $dst|$dst, $src}", [],
1086 IIC_SSE_MOVA_P_RR>, VEX;
1087 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1088 "movaps\t{$src, $dst|$dst, $src}", [],
1090 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1091 "movapd\t{$src, $dst|$dst, $src}", [],
1095 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1096 // bits are disregarded. FIXME: Set encoding to pseudo!
1097 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1098 let isCodeGenOnly = 1 in {
1099 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1100 "movaps\t{$src, $dst|$dst, $src}",
1101 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1102 IIC_SSE_MOVA_P_RM>, VEX;
1103 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1104 "movapd\t{$src, $dst|$dst, $src}",
1105 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1106 IIC_SSE_MOVA_P_RM>, VEX;
1108 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1109 "movaps\t{$src, $dst|$dst, $src}",
1110 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1112 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1113 "movapd\t{$src, $dst|$dst, $src}",
1114 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1118 //===----------------------------------------------------------------------===//
1119 // SSE 1 & 2 - Move Low packed FP Instructions
1120 //===----------------------------------------------------------------------===//
1122 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1123 SDNode psnode, SDNode pdnode, string base_opc,
1124 string asm_opr, InstrItinClass itin> {
1125 def PSrm : PI<opc, MRMSrcMem,
1126 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1127 !strconcat(base_opc, "s", asm_opr),
1130 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1131 itin, SSEPackedSingle>, TB;
1133 def PDrm : PI<opc, MRMSrcMem,
1134 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1135 !strconcat(base_opc, "d", asm_opr),
1136 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1137 (scalar_to_vector (loadf64 addr:$src2)))))],
1138 itin, SSEPackedDouble>, TB, OpSize;
1141 let AddedComplexity = 20 in {
1142 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1143 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1144 IIC_SSE_MOV_LH>, VEX_4V;
1146 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1147 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1148 "\t{$src2, $dst|$dst, $src2}",
1152 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1153 "movlps\t{$src, $dst|$dst, $src}",
1154 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1155 (iPTR 0))), addr:$dst)],
1156 IIC_SSE_MOV_LH>, VEX;
1157 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1158 "movlpd\t{$src, $dst|$dst, $src}",
1159 [(store (f64 (vector_extract (v2f64 VR128:$src),
1160 (iPTR 0))), addr:$dst)],
1161 IIC_SSE_MOV_LH>, VEX;
1162 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1163 "movlps\t{$src, $dst|$dst, $src}",
1164 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1165 (iPTR 0))), addr:$dst)],
1167 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1168 "movlpd\t{$src, $dst|$dst, $src}",
1169 [(store (f64 (vector_extract (v2f64 VR128:$src),
1170 (iPTR 0))), addr:$dst)],
1173 let Predicates = [HasAVX] in {
1174 // Shuffle with VMOVLPS
1175 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1176 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1177 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1178 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1180 // Shuffle with VMOVLPD
1181 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1182 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1183 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1184 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1187 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1189 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1190 def : Pat<(store (v4i32 (X86Movlps
1191 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1192 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1193 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1195 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1196 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1198 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1201 let Predicates = [HasSSE1] in {
1202 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1203 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1204 (iPTR 0))), addr:$src1),
1205 (MOVLPSmr addr:$src1, VR128:$src2)>;
1207 // Shuffle with MOVLPS
1208 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1209 (MOVLPSrm VR128:$src1, addr:$src2)>;
1210 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1211 (MOVLPSrm VR128:$src1, addr:$src2)>;
1212 def : Pat<(X86Movlps VR128:$src1,
1213 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1214 (MOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1219 (MOVLPSmr addr:$src1, VR128:$src2)>;
1220 def : Pat<(store (v4i32 (X86Movlps
1221 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1223 (MOVLPSmr addr:$src1, VR128:$src2)>;
1226 let Predicates = [HasSSE2] in {
1227 // Shuffle with MOVLPD
1228 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1229 (MOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1231 (MOVLPDrm VR128:$src1, addr:$src2)>;
1234 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1236 (MOVLPDmr addr:$src1, VR128:$src2)>;
1237 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1239 (MOVLPDmr addr:$src1, VR128:$src2)>;
1242 //===----------------------------------------------------------------------===//
1243 // SSE 1 & 2 - Move Hi packed FP Instructions
1244 //===----------------------------------------------------------------------===//
1246 let AddedComplexity = 20 in {
1247 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1248 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1249 IIC_SSE_MOV_LH>, VEX_4V;
1251 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1252 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1253 "\t{$src2, $dst|$dst, $src2}",
1257 // v2f64 extract element 1 is always custom lowered to unpack high to low
1258 // and extract element 0 so the non-store version isn't too horrible.
1259 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1260 "movhps\t{$src, $dst|$dst, $src}",
1261 [(store (f64 (vector_extract
1262 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1263 (bc_v2f64 (v4f32 VR128:$src))),
1264 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1265 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1266 "movhpd\t{$src, $dst|$dst, $src}",
1267 [(store (f64 (vector_extract
1268 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1269 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1270 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1271 "movhps\t{$src, $dst|$dst, $src}",
1272 [(store (f64 (vector_extract
1273 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1274 (bc_v2f64 (v4f32 VR128:$src))),
1275 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1276 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1277 "movhpd\t{$src, $dst|$dst, $src}",
1278 [(store (f64 (vector_extract
1279 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1280 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1282 let Predicates = [HasAVX] in {
1284 def : Pat<(X86Movlhps VR128:$src1,
1285 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1286 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1287 def : Pat<(X86Movlhps VR128:$src1,
1288 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1289 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1291 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1292 // is during lowering, where it's not possible to recognize the load fold
1293 // cause it has two uses through a bitcast. One use disappears at isel time
1294 // and the fold opportunity reappears.
1295 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1296 (scalar_to_vector (loadf64 addr:$src2)))),
1297 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1300 let Predicates = [HasSSE1] in {
1302 def : Pat<(X86Movlhps VR128:$src1,
1303 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1304 (MOVHPSrm VR128:$src1, addr:$src2)>;
1305 def : Pat<(X86Movlhps VR128:$src1,
1306 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1307 (MOVHPSrm VR128:$src1, addr:$src2)>;
1310 let Predicates = [HasSSE2] in {
1311 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1312 // is during lowering, where it's not possible to recognize the load fold
1313 // cause it has two uses through a bitcast. One use disappears at isel time
1314 // and the fold opportunity reappears.
1315 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1316 (scalar_to_vector (loadf64 addr:$src2)))),
1317 (MOVHPDrm VR128:$src1, addr:$src2)>;
1320 //===----------------------------------------------------------------------===//
1321 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1322 //===----------------------------------------------------------------------===//
1324 let AddedComplexity = 20 in {
1325 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1326 (ins VR128:$src1, VR128:$src2),
1327 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1329 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1332 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1333 (ins VR128:$src1, VR128:$src2),
1334 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1336 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1340 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1341 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1342 (ins VR128:$src1, VR128:$src2),
1343 "movlhps\t{$src2, $dst|$dst, $src2}",
1345 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1347 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1348 (ins VR128:$src1, VR128:$src2),
1349 "movhlps\t{$src2, $dst|$dst, $src2}",
1351 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1355 let Predicates = [HasAVX] in {
1357 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1358 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1359 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1360 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1363 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1364 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1367 let Predicates = [HasSSE1] in {
1369 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1370 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1371 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1372 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1375 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1376 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1379 //===----------------------------------------------------------------------===//
1380 // SSE 1 & 2 - Conversion Instructions
1381 //===----------------------------------------------------------------------===//
1383 def SSE_CVT_PD : OpndItins<
1384 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1387 def SSE_CVT_PS : OpndItins<
1388 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1391 def SSE_CVT_Scalar : OpndItins<
1392 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1395 def SSE_CVT_SS2SI_32 : OpndItins<
1396 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1399 def SSE_CVT_SS2SI_64 : OpndItins<
1400 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1403 def SSE_CVT_SD2SI : OpndItins<
1404 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1407 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1408 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1409 string asm, OpndItins itins> {
1410 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1411 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1413 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1414 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1418 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1419 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1420 string asm, Domain d, OpndItins itins> {
1421 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1422 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1424 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1425 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1429 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1430 X86MemOperand x86memop, string asm> {
1431 let neverHasSideEffects = 1 in {
1432 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1433 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1435 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1436 (ins DstRC:$src1, x86memop:$src),
1437 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1438 } // neverHasSideEffects = 1
1441 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1442 "cvttss2si\t{$src, $dst|$dst, $src}",
1445 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1446 "cvttss2si\t{$src, $dst|$dst, $src}",
1448 XS, VEX, VEX_W, VEX_LIG;
1449 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1450 "cvttsd2si\t{$src, $dst|$dst, $src}",
1453 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1454 "cvttsd2si\t{$src, $dst|$dst, $src}",
1456 XD, VEX, VEX_W, VEX_LIG;
1458 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1459 // register, but the same isn't true when only using memory operands,
1460 // provide other assembly "l" and "q" forms to address this explicitly
1461 // where appropriate to do so.
1462 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1463 XS, VEX_4V, VEX_LIG;
1464 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1465 XS, VEX_4V, VEX_W, VEX_LIG;
1466 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1467 XD, VEX_4V, VEX_LIG;
1468 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1469 XD, VEX_4V, VEX_LIG;
1470 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1471 XD, VEX_4V, VEX_W, VEX_LIG;
1473 let Predicates = [HasAVX], AddedComplexity = 1 in {
1474 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1475 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1476 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1477 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1478 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1479 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1480 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1481 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1483 def : Pat<(f32 (sint_to_fp GR32:$src)),
1484 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1485 def : Pat<(f32 (sint_to_fp GR64:$src)),
1486 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1487 def : Pat<(f64 (sint_to_fp GR32:$src)),
1488 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1489 def : Pat<(f64 (sint_to_fp GR64:$src)),
1490 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1493 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1494 "cvttss2si\t{$src, $dst|$dst, $src}",
1495 SSE_CVT_SS2SI_32>, XS;
1496 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1497 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1498 SSE_CVT_SS2SI_64>, XS, REX_W;
1499 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1500 "cvttsd2si\t{$src, $dst|$dst, $src}",
1502 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1503 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1504 SSE_CVT_SD2SI>, XD, REX_W;
1505 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1506 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1507 SSE_CVT_Scalar>, XS;
1508 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1509 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1510 SSE_CVT_Scalar>, XS, REX_W;
1511 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1512 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1513 SSE_CVT_Scalar>, XD;
1514 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1515 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1516 SSE_CVT_Scalar>, XD, REX_W;
1518 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1519 // and/or XMM operand(s).
1521 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1522 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1523 string asm, OpndItins itins> {
1524 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1525 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1526 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1527 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1528 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1529 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm>;
1532 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1533 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1534 PatFrag ld_frag, string asm, OpndItins itins,
1536 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1538 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1539 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1540 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1542 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1543 (ins DstRC:$src1, x86memop:$src2),
1545 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1546 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1547 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1551 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1552 f128mem, load, "cvtsd2si", SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1553 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1554 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si",
1555 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1557 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1558 f128mem, load, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1559 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1560 f128mem, load, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1563 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1564 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1565 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1566 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1567 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss",
1568 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1570 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1571 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1572 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1573 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1574 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd",
1575 SSE_CVT_Scalar, 0>, XD,
1578 let Constraints = "$src1 = $dst" in {
1579 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1580 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1581 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1582 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1583 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1584 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1585 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1586 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1587 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1588 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1589 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1590 "cvtsi2sd", SSE_CVT_Scalar>, XD, REX_W;
1595 // Aliases for intrinsics
1596 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1597 f32mem, load, "cvttss2si",
1598 SSE_CVT_SS2SI_32>, XS, VEX;
1599 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1600 int_x86_sse_cvttss2si64, f32mem, load,
1601 "cvttss2si", SSE_CVT_SS2SI_64>,
1603 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1604 f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
1606 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1607 int_x86_sse2_cvttsd2si64, f128mem, load,
1608 "cvttsd2si", SSE_CVT_SD2SI>,
1610 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1611 f32mem, load, "cvttss2si",
1612 SSE_CVT_SS2SI_32>, XS;
1613 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1614 int_x86_sse_cvttss2si64, f32mem, load,
1615 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1617 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1618 f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
1620 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1621 int_x86_sse2_cvttsd2si64, f128mem, load,
1622 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1625 let Pattern = []<dag> in {
1626 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1627 "cvtss2si{l}\t{$src, $dst|$dst, $src}",
1628 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1629 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1630 "cvtss2si\t{$src, $dst|$dst, $src}",
1631 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1632 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1633 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1634 SSEPackedSingle, SSE_CVT_PS>, TB, VEX;
1635 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1636 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1637 SSEPackedSingle, SSE_CVT_PS>, TB, VEX;
1640 let Pattern = []<dag> in {
1641 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1642 "cvtss2si{l}\t{$src, $dst|$dst, $src}",
1643 SSE_CVT_SS2SI_32>, XS;
1644 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1645 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1646 SSE_CVT_SS2SI_64>, XS, REX_W;
1647 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1648 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1649 SSEPackedSingle, SSE_CVT_PS>,
1650 TB; /* PD SSE3 form is avaiable */
1653 let Predicates = [HasAVX] in {
1654 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1655 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1656 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1657 (VCVTSS2SIrm addr:$src)>;
1658 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1659 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1660 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1661 (VCVTSS2SI64rm addr:$src)>;
1664 let Predicates = [HasSSE1] in {
1665 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1666 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1667 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1668 (CVTSS2SIrm addr:$src)>;
1669 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1670 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1671 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1672 (CVTSS2SI64rm addr:$src)>;
1677 // Convert scalar double to scalar single
1678 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1679 (ins FR64:$src1, FR64:$src2),
1680 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1681 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1683 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1684 (ins FR64:$src1, f64mem:$src2),
1685 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1686 [], IIC_SSE_CVT_Scalar_RM>,
1687 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1689 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1692 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1693 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1694 [(set FR32:$dst, (fround FR64:$src))],
1695 IIC_SSE_CVT_Scalar_RR>;
1696 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1697 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1698 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1699 IIC_SSE_CVT_Scalar_RM>,
1701 Requires<[HasSSE2, OptForSize]>;
1703 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1704 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss",
1707 let Constraints = "$src1 = $dst" in
1708 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1709 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss",
1710 SSE_CVT_Scalar>, XS;
1712 // Convert scalar single to scalar double
1713 // SSE2 instructions with XS prefix
1714 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1715 (ins FR32:$src1, FR32:$src2),
1716 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1717 [], IIC_SSE_CVT_Scalar_RR>,
1718 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1720 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1721 (ins FR32:$src1, f32mem:$src2),
1722 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1723 [], IIC_SSE_CVT_Scalar_RM>,
1724 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1726 let Predicates = [HasAVX] in {
1727 def : Pat<(f64 (fextend FR32:$src)),
1728 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1729 def : Pat<(fextend (loadf32 addr:$src)),
1730 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1731 def : Pat<(extloadf32 addr:$src),
1732 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1735 def : Pat<(extloadf32 addr:$src),
1736 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1737 Requires<[HasAVX, OptForSpeed]>;
1739 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1740 "cvtss2sd\t{$src, $dst|$dst, $src}",
1741 [(set FR64:$dst, (fextend FR32:$src))],
1742 IIC_SSE_CVT_Scalar_RR>, XS,
1743 Requires<[HasSSE2]>;
1744 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1745 "cvtss2sd\t{$src, $dst|$dst, $src}",
1746 [(set FR64:$dst, (extloadf32 addr:$src))],
1747 IIC_SSE_CVT_Scalar_RM>, XS,
1748 Requires<[HasSSE2, OptForSize]>;
1750 // extload f32 -> f64. This matches load+fextend because we have a hack in
1751 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1753 // Since these loads aren't folded into the fextend, we have to match it
1755 def : Pat<(fextend (loadf32 addr:$src)),
1756 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1757 def : Pat<(extloadf32 addr:$src),
1758 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1760 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1761 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1762 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1763 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1765 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V,
1767 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1768 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1769 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1770 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1771 (load addr:$src2)))],
1772 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V,
1774 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1775 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1776 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1777 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1778 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1780 IIC_SSE_CVT_Scalar_RR>, XS,
1781 Requires<[HasSSE2]>;
1782 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1783 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1784 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1785 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1786 (load addr:$src2)))],
1787 IIC_SSE_CVT_Scalar_RM>, XS,
1788 Requires<[HasSSE2]>;
1791 // Convert doubleword to packed single/double fp
1792 // SSE2 instructions without OpSize prefix
1793 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1794 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1795 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))],
1797 TB, VEX, Requires<[HasAVX]>;
1798 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1799 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1800 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1801 (bitconvert (memopv2i64 addr:$src))))],
1803 TB, VEX, Requires<[HasAVX]>;
1804 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1805 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1806 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))],
1808 TB, Requires<[HasSSE2]>;
1809 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1810 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1811 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1812 (bitconvert (memopv2i64 addr:$src))))],
1814 TB, Requires<[HasSSE2]>;
1817 // Convert packed single/double fp to doubleword
1818 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1819 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1820 IIC_SSE_CVT_PS_RR>, VEX;
1821 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1822 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1823 IIC_SSE_CVT_PS_RM>, VEX;
1824 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1825 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1826 IIC_SSE_CVT_PS_RR>, VEX;
1827 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1828 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1829 IIC_SSE_CVT_PS_RM>, VEX;
1830 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1831 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1833 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1834 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1837 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1838 "cvtps2dq\t{$src, $dst|$dst, $src}",
1839 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1842 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1844 "cvtps2dq\t{$src, $dst|$dst, $src}",
1845 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1846 (memop addr:$src)))],
1847 IIC_SSE_CVT_PS_RM>, VEX;
1848 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1849 "cvtps2dq\t{$src, $dst|$dst, $src}",
1850 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1852 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1853 "cvtps2dq\t{$src, $dst|$dst, $src}",
1854 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1855 (memop addr:$src)))],
1858 // SSE2 packed instructions with XD prefix
1859 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1860 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1861 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1863 XD, VEX, Requires<[HasAVX]>;
1864 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1865 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1866 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1867 (memop addr:$src)))],
1869 XD, VEX, Requires<[HasAVX]>;
1870 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1871 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1872 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1874 XD, Requires<[HasSSE2]>;
1875 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1876 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1877 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1878 (memop addr:$src)))],
1880 XD, Requires<[HasSSE2]>;
1883 // Convert with truncation packed single/double fp to doubleword
1884 // SSE2 packed instructions with XS prefix
1885 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1886 "cvttps2dq\t{$src, $dst|$dst, $src}",
1888 (int_x86_sse2_cvttps2dq VR128:$src))],
1889 IIC_SSE_CVT_PS_RR>, VEX;
1890 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1891 "cvttps2dq\t{$src, $dst|$dst, $src}",
1892 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1893 (memop addr:$src)))],
1894 IIC_SSE_CVT_PS_RM>, VEX;
1895 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1896 "cvttps2dq\t{$src, $dst|$dst, $src}",
1898 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1899 IIC_SSE_CVT_PS_RR>, VEX;
1900 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1901 "cvttps2dq\t{$src, $dst|$dst, $src}",
1902 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1903 (memopv8f32 addr:$src)))],
1904 IIC_SSE_CVT_PS_RM>, VEX;
1906 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1907 "cvttps2dq\t{$src, $dst|$dst, $src}",
1909 (int_x86_sse2_cvttps2dq VR128:$src))],
1911 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1912 "cvttps2dq\t{$src, $dst|$dst, $src}",
1914 (int_x86_sse2_cvttps2dq (memop addr:$src)))],
1917 let Predicates = [HasAVX] in {
1918 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1919 (Int_VCVTDQ2PSrr VR128:$src)>;
1920 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1921 (Int_VCVTDQ2PSrm addr:$src)>;
1923 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1924 (VCVTTPS2DQrr VR128:$src)>;
1925 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1926 (VCVTTPS2DQrm addr:$src)>;
1928 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1929 (VCVTDQ2PSYrr VR256:$src)>;
1930 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1931 (VCVTDQ2PSYrm addr:$src)>;
1933 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1934 (VCVTTPS2DQYrr VR256:$src)>;
1935 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1936 (VCVTTPS2DQYrm addr:$src)>;
1939 let Predicates = [HasSSE2] in {
1940 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1941 (Int_CVTDQ2PSrr VR128:$src)>;
1942 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1943 (Int_CVTDQ2PSrm addr:$src)>;
1945 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1946 (CVTTPS2DQrr VR128:$src)>;
1947 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1948 (CVTTPS2DQrm addr:$src)>;
1951 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1952 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1954 (int_x86_sse2_cvttpd2dq VR128:$src))],
1955 IIC_SSE_CVT_PD_RR>, VEX;
1956 let isCodeGenOnly = 1 in
1957 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1958 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1959 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1960 (memop addr:$src)))],
1961 IIC_SSE_CVT_PD_RM>, VEX;
1962 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1963 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1964 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1966 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1967 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1968 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1969 (memop addr:$src)))],
1972 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1973 // register, but the same isn't true when using memory operands instead.
1974 // Provide other assembly rr and rm forms to address this explicitly.
1975 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1976 "cvttpd2dq\t{$src, $dst|$dst, $src}", [],
1977 IIC_SSE_CVT_PD_RR>, VEX;
1980 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1981 "cvttpd2dqx\t{$src, $dst|$dst, $src}", [],
1982 IIC_SSE_CVT_PD_RR>, VEX;
1983 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1984 "cvttpd2dqx\t{$src, $dst|$dst, $src}", [],
1985 IIC_SSE_CVT_PD_RM>, VEX;
1988 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1989 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [],
1990 IIC_SSE_CVT_PD_RR>, VEX;
1991 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1992 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [],
1993 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
1995 // Convert packed single to packed double
1996 let Predicates = [HasAVX] in {
1997 // SSE2 instructions without OpSize prefix
1998 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1999 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2000 IIC_SSE_CVT_PD_RR>, TB, VEX;
2001 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2002 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2003 IIC_SSE_CVT_PD_RM>, TB, VEX;
2004 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2005 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2006 IIC_SSE_CVT_PD_RR>, TB, VEX;
2007 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2008 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2009 IIC_SSE_CVT_PD_RM>, TB, VEX;
2011 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2012 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2013 IIC_SSE_CVT_PD_RR>, TB;
2014 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2015 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2016 IIC_SSE_CVT_PD_RM>, TB;
2018 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2019 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2020 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2022 TB, VEX, Requires<[HasAVX]>;
2023 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2024 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2025 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
2026 (load addr:$src)))],
2028 TB, VEX, Requires<[HasAVX]>;
2029 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2030 "cvtps2pd\t{$src, $dst|$dst, $src}",
2031 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2033 TB, Requires<[HasSSE2]>;
2034 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2035 "cvtps2pd\t{$src, $dst|$dst, $src}",
2036 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
2037 (load addr:$src)))],
2039 TB, Requires<[HasSSE2]>;
2041 // Convert packed double to packed single
2042 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2043 // register, but the same isn't true when using memory operands instead.
2044 // Provide other assembly rr and rm forms to address this explicitly.
2045 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2046 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2047 IIC_SSE_CVT_PD_RR>, VEX;
2048 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2049 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2050 IIC_SSE_CVT_PD_RR>, VEX;
2053 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2054 "cvtpd2psx\t{$src, $dst|$dst, $src}", [],
2055 IIC_SSE_CVT_PD_RR>, VEX;
2056 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2057 "cvtpd2psx\t{$src, $dst|$dst, $src}", [],
2058 IIC_SSE_CVT_PD_RM>, VEX;
2061 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2062 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", [],
2063 IIC_SSE_CVT_PD_RR>, VEX;
2064 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2065 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", [],
2066 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2067 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2068 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2070 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2071 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2075 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2076 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2077 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2079 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
2081 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2082 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
2083 (memop addr:$src)))],
2085 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2086 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2087 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2089 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2090 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2091 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
2092 (memop addr:$src)))],
2095 // AVX 256-bit register conversion intrinsics
2096 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2097 // whenever possible to avoid declaring two versions of each one.
2098 let Predicates = [HasAVX] in {
2099 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2100 (VCVTDQ2PSYrr VR256:$src)>;
2101 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2102 (VCVTDQ2PSYrm addr:$src)>;
2104 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
2105 (VCVTPD2PSYrr VR256:$src)>;
2106 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
2107 (VCVTPD2PSYrm addr:$src)>;
2109 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
2110 (VCVTPS2DQYrr VR256:$src)>;
2111 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
2112 (VCVTPS2DQYrm addr:$src)>;
2114 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
2115 (VCVTPS2PDYrr VR128:$src)>;
2116 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
2117 (VCVTPS2PDYrm addr:$src)>;
2119 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
2120 (VCVTTPD2DQYrr VR256:$src)>;
2121 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
2122 (VCVTTPD2DQYrm addr:$src)>;
2124 // Match fround and fextend for 128/256-bit conversions
2125 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2126 (VCVTPD2PSYrr VR256:$src)>;
2127 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2128 (VCVTPD2PSYrm addr:$src)>;
2130 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2131 (VCVTPS2PDYrr VR128:$src)>;
2132 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
2133 (VCVTPS2PDYrm addr:$src)>;
2136 //===----------------------------------------------------------------------===//
2137 // SSE 1 & 2 - Compare Instructions
2138 //===----------------------------------------------------------------------===//
2140 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2141 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2142 Operand CC, SDNode OpNode, ValueType VT,
2143 PatFrag ld_frag, string asm, string asm_alt,
2145 def rr : SIi8<0xC2, MRMSrcReg,
2146 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2147 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2149 def rm : SIi8<0xC2, MRMSrcMem,
2150 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2151 [(set RC:$dst, (OpNode (VT RC:$src1),
2152 (ld_frag addr:$src2), imm:$cc))],
2155 // Accept explicit immediate argument form instead of comparison code.
2156 let neverHasSideEffects = 1 in {
2157 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2158 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2159 IIC_SSE_ALU_F32S_RR>;
2161 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2162 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2163 IIC_SSE_ALU_F32S_RM>;
2167 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2168 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2169 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2171 XS, VEX_4V, VEX_LIG;
2172 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2173 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2174 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2175 SSE_ALU_F32S>, // same latency as 32 bit compare
2176 XD, VEX_4V, VEX_LIG;
2178 let Constraints = "$src1 = $dst" in {
2179 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2180 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2181 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2183 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2184 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2185 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2186 SSE_ALU_F32S>, // same latency as 32 bit compare
2190 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2191 Intrinsic Int, string asm, OpndItins itins> {
2192 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2193 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2194 [(set VR128:$dst, (Int VR128:$src1,
2195 VR128:$src, imm:$cc))],
2197 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2198 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2199 [(set VR128:$dst, (Int VR128:$src1,
2200 (load addr:$src), imm:$cc))],
2204 // Aliases to match intrinsics which expect XMM operand(s).
2205 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2206 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2209 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2210 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2211 SSE_ALU_F32S>, // same latency as f32
2213 let Constraints = "$src1 = $dst" in {
2214 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2215 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2217 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2218 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2219 SSE_ALU_F32S>, // same latency as f32
2224 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2225 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2226 ValueType vt, X86MemOperand x86memop,
2227 PatFrag ld_frag, string OpcodeStr, Domain d> {
2228 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2229 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2230 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2231 IIC_SSE_COMIS_RR, d>;
2232 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2233 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2234 [(set EFLAGS, (OpNode (vt RC:$src1),
2235 (ld_frag addr:$src2)))],
2236 IIC_SSE_COMIS_RM, d>;
2239 let Defs = [EFLAGS] in {
2240 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2241 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2242 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2243 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2245 let Pattern = []<dag> in {
2246 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2247 "comiss", SSEPackedSingle>, TB, VEX,
2249 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2250 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2254 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2255 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2256 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2257 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2259 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2260 load, "comiss", SSEPackedSingle>, TB, VEX;
2261 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2262 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2263 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2264 "ucomiss", SSEPackedSingle>, TB;
2265 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2266 "ucomisd", SSEPackedDouble>, TB, OpSize;
2268 let Pattern = []<dag> in {
2269 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2270 "comiss", SSEPackedSingle>, TB;
2271 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2272 "comisd", SSEPackedDouble>, TB, OpSize;
2275 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2276 load, "ucomiss", SSEPackedSingle>, TB;
2277 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2278 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2280 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2281 "comiss", SSEPackedSingle>, TB;
2282 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2283 "comisd", SSEPackedDouble>, TB, OpSize;
2284 } // Defs = [EFLAGS]
2286 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2287 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2288 Operand CC, Intrinsic Int, string asm,
2289 string asm_alt, Domain d> {
2290 def rri : PIi8<0xC2, MRMSrcReg,
2291 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2292 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2293 IIC_SSE_CMPP_RR, d>;
2294 def rmi : PIi8<0xC2, MRMSrcMem,
2295 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2296 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2297 IIC_SSE_CMPP_RM, d>;
2299 // Accept explicit immediate argument form instead of comparison code.
2300 let neverHasSideEffects = 1 in {
2301 def rri_alt : PIi8<0xC2, MRMSrcReg,
2302 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2303 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2304 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2305 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2306 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2310 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2311 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2312 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2313 SSEPackedSingle>, TB, VEX_4V;
2314 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2315 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2316 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2317 SSEPackedDouble>, TB, OpSize, VEX_4V;
2318 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2319 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2320 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2321 SSEPackedSingle>, TB, VEX_4V;
2322 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2323 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2324 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2325 SSEPackedDouble>, TB, OpSize, VEX_4V;
2326 let Constraints = "$src1 = $dst" in {
2327 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2328 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2329 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2330 SSEPackedSingle>, TB;
2331 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2332 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2333 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2334 SSEPackedDouble>, TB, OpSize;
2337 let Predicates = [HasAVX] in {
2338 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2339 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2340 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2341 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2342 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2343 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2344 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2345 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2347 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2348 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2349 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2350 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2351 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2352 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2353 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2354 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2357 let Predicates = [HasSSE1] in {
2358 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2359 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2360 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2361 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2364 let Predicates = [HasSSE2] in {
2365 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2366 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2367 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2368 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2371 //===----------------------------------------------------------------------===//
2372 // SSE 1 & 2 - Shuffle Instructions
2373 //===----------------------------------------------------------------------===//
2375 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2376 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2377 ValueType vt, string asm, PatFrag mem_frag,
2378 Domain d, bit IsConvertibleToThreeAddress = 0> {
2379 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2380 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2381 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2382 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2383 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2384 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2385 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2386 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2387 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2390 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2391 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2392 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2393 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2394 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2395 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2396 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2397 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2398 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2399 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2400 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2401 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2403 let Constraints = "$src1 = $dst" in {
2404 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2405 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2406 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2408 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2409 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2410 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2414 let Predicates = [HasAVX] in {
2415 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2416 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2417 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2418 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2419 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2421 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2422 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2423 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2424 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2425 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2428 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2429 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2430 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2431 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2432 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2434 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2435 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2436 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2437 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2438 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2441 let Predicates = [HasSSE1] in {
2442 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2443 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2444 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2445 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2446 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2449 let Predicates = [HasSSE2] in {
2450 // Generic SHUFPD patterns
2451 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2452 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2453 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2454 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2455 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2458 //===----------------------------------------------------------------------===//
2459 // SSE 1 & 2 - Unpack Instructions
2460 //===----------------------------------------------------------------------===//
2462 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2463 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2464 PatFrag mem_frag, RegisterClass RC,
2465 X86MemOperand x86memop, string asm,
2467 def rr : PI<opc, MRMSrcReg,
2468 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2470 (vt (OpNode RC:$src1, RC:$src2)))],
2472 def rm : PI<opc, MRMSrcMem,
2473 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2475 (vt (OpNode RC:$src1,
2476 (mem_frag addr:$src2))))],
2480 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2481 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2482 SSEPackedSingle>, TB, VEX_4V;
2483 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2484 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2485 SSEPackedDouble>, TB, OpSize, VEX_4V;
2486 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2487 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2488 SSEPackedSingle>, TB, VEX_4V;
2489 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2490 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2491 SSEPackedDouble>, TB, OpSize, VEX_4V;
2493 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2494 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2495 SSEPackedSingle>, TB, VEX_4V;
2496 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2497 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2498 SSEPackedDouble>, TB, OpSize, VEX_4V;
2499 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2500 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2501 SSEPackedSingle>, TB, VEX_4V;
2502 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2503 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2504 SSEPackedDouble>, TB, OpSize, VEX_4V;
2506 let Constraints = "$src1 = $dst" in {
2507 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2508 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2509 SSEPackedSingle>, TB;
2510 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2511 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2512 SSEPackedDouble>, TB, OpSize;
2513 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2514 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2515 SSEPackedSingle>, TB;
2516 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2517 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2518 SSEPackedDouble>, TB, OpSize;
2519 } // Constraints = "$src1 = $dst"
2521 let Predicates = [HasAVX], AddedComplexity = 1 in {
2522 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2523 // problem is during lowering, where it's not possible to recognize the load
2524 // fold cause it has two uses through a bitcast. One use disappears at isel
2525 // time and the fold opportunity reappears.
2526 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2527 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2530 let Predicates = [HasSSE2] in {
2531 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2532 // problem is during lowering, where it's not possible to recognize the load
2533 // fold cause it has two uses through a bitcast. One use disappears at isel
2534 // time and the fold opportunity reappears.
2535 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2536 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2539 //===----------------------------------------------------------------------===//
2540 // SSE 1 & 2 - Extract Floating-Point Sign mask
2541 //===----------------------------------------------------------------------===//
2543 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2544 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2546 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2547 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2548 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2549 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2550 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2551 IIC_SSE_MOVMSK, d>, REX_W;
2554 let Predicates = [HasAVX] in {
2555 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2556 "movmskps", SSEPackedSingle>, TB, VEX;
2557 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2558 "movmskpd", SSEPackedDouble>, TB,
2560 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2561 "movmskps", SSEPackedSingle>, TB, VEX;
2562 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2563 "movmskpd", SSEPackedDouble>, TB,
2566 def : Pat<(i32 (X86fgetsign FR32:$src)),
2567 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2569 def : Pat<(i64 (X86fgetsign FR32:$src)),
2570 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2572 def : Pat<(i32 (X86fgetsign FR64:$src)),
2573 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2575 def : Pat<(i64 (X86fgetsign FR64:$src)),
2576 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2580 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2581 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2582 SSEPackedSingle>, TB, VEX;
2583 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2584 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2585 SSEPackedDouble>, TB,
2587 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2588 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2589 SSEPackedSingle>, TB, VEX;
2590 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2591 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2592 SSEPackedDouble>, TB,
2596 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2597 SSEPackedSingle>, TB;
2598 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2599 SSEPackedDouble>, TB, OpSize;
2601 def : Pat<(i32 (X86fgetsign FR32:$src)),
2602 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2603 sub_ss))>, Requires<[HasSSE1]>;
2604 def : Pat<(i64 (X86fgetsign FR32:$src)),
2605 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2606 sub_ss))>, Requires<[HasSSE1]>;
2607 def : Pat<(i32 (X86fgetsign FR64:$src)),
2608 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2609 sub_sd))>, Requires<[HasSSE2]>;
2610 def : Pat<(i64 (X86fgetsign FR64:$src)),
2611 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2612 sub_sd))>, Requires<[HasSSE2]>;
2614 //===---------------------------------------------------------------------===//
2615 // SSE2 - Packed Integer Logical Instructions
2616 //===---------------------------------------------------------------------===//
2618 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2620 /// PDI_binop_rm - Simple SSE2 binary operator.
2621 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2622 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2623 X86MemOperand x86memop,
2625 bit IsCommutable = 0,
2627 let isCommutable = IsCommutable in
2628 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2629 (ins RC:$src1, RC:$src2),
2631 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2632 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2633 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2634 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2635 (ins RC:$src1, x86memop:$src2),
2637 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2638 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2639 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2640 (bitconvert (memop_frag addr:$src2)))))],
2643 } // ExeDomain = SSEPackedInt
2645 // These are ordered here for pattern ordering requirements with the fp versions
2647 let Predicates = [HasAVX] in {
2648 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2649 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2650 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2651 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2652 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2653 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2654 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2655 i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2658 let Constraints = "$src1 = $dst" in {
2659 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2660 i128mem, SSE_BIT_ITINS_P, 1>;
2661 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2662 i128mem, SSE_BIT_ITINS_P, 1>;
2663 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2664 i128mem, SSE_BIT_ITINS_P, 1>;
2665 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2666 i128mem, SSE_BIT_ITINS_P, 0>;
2667 } // Constraints = "$src1 = $dst"
2669 let Predicates = [HasAVX2] in {
2670 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2671 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2672 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2673 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2674 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2675 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2676 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2677 i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2680 //===----------------------------------------------------------------------===//
2681 // SSE 1 & 2 - Logical Instructions
2682 //===----------------------------------------------------------------------===//
2684 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2686 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2687 SDNode OpNode, OpndItins itins> {
2688 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2689 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2692 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2693 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2696 let Constraints = "$src1 = $dst" in {
2697 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2698 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2701 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2702 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2707 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2708 let mayLoad = 0 in {
2709 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2711 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2713 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2717 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2718 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2721 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2723 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2725 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2726 // are all promoted to v2i64, and the patterns are covered by the int
2727 // version. This is needed in SSE only, because v2i64 isn't supported on
2728 // SSE1, but only on SSE2.
2729 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2730 !strconcat(OpcodeStr, "ps"), f128mem, [],
2731 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2732 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2734 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2735 !strconcat(OpcodeStr, "pd"), f128mem,
2736 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2737 (bc_v2i64 (v2f64 VR128:$src2))))],
2738 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2739 (memopv2i64 addr:$src2)))], 0>,
2741 let Constraints = "$src1 = $dst" in {
2742 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2743 !strconcat(OpcodeStr, "ps"), f128mem,
2744 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2745 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2746 (memopv2i64 addr:$src2)))]>, TB;
2748 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2749 !strconcat(OpcodeStr, "pd"), f128mem,
2750 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2751 (bc_v2i64 (v2f64 VR128:$src2))))],
2752 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2753 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2757 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2759 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2761 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2762 !strconcat(OpcodeStr, "ps"), f256mem,
2763 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2764 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2765 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2767 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2768 !strconcat(OpcodeStr, "pd"), f256mem,
2769 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2770 (bc_v4i64 (v4f64 VR256:$src2))))],
2771 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2772 (memopv4i64 addr:$src2)))], 0>,
2776 // AVX 256-bit packed logical ops forms
2777 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2778 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2779 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2780 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2782 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2783 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2784 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2785 let isCommutable = 0 in
2786 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2788 //===----------------------------------------------------------------------===//
2789 // SSE 1 & 2 - Arithmetic Instructions
2790 //===----------------------------------------------------------------------===//
2792 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2795 /// In addition, we also have a special variant of the scalar form here to
2796 /// represent the associated intrinsic operation. This form is unlike the
2797 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2798 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2800 /// These three forms can each be reg+reg or reg+mem.
2803 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2805 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2808 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2809 OpNode, FR32, f32mem,
2810 itins.s, Is2Addr>, XS;
2811 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2812 OpNode, FR64, f64mem,
2813 itins.d, Is2Addr>, XD;
2816 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2819 let mayLoad = 0 in {
2820 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2821 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2823 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2824 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2829 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2832 let mayLoad = 0 in {
2833 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2834 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2836 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2837 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2842 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2845 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2846 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2847 itins.s, Is2Addr>, XS;
2848 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2849 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2850 itins.d, Is2Addr>, XD;
2853 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2856 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2857 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2858 SSEPackedSingle, itins.s, Is2Addr>,
2861 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2862 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2863 SSEPackedDouble, itins.d, Is2Addr>,
2867 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2869 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2870 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2871 SSEPackedSingle, itins.s, 0>, TB;
2873 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2874 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2875 SSEPackedDouble, itins.d, 0>, TB, OpSize;
2878 // Binary Arithmetic instructions
2879 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2880 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2882 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2883 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2885 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2886 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2888 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2889 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2892 let isCommutable = 0 in {
2893 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2894 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2896 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2897 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>, VEX_4V;
2898 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2899 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2901 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2902 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2904 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2905 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2907 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2908 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2909 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2910 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2912 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2913 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2915 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2916 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
2917 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
2918 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2922 let Constraints = "$src1 = $dst" in {
2923 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2924 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2925 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2926 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2927 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2928 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2930 let isCommutable = 0 in {
2931 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2932 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2933 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2934 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2935 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2936 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2937 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2938 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2939 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
2940 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
2941 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2942 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2943 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
2944 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
2949 /// In addition, we also have a special variant of the scalar form here to
2950 /// represent the associated intrinsic operation. This form is unlike the
2951 /// plain scalar form, in that it takes an entire vector (instead of a
2952 /// scalar) and leaves the top elements undefined.
2954 /// And, we have a special variant form for a full-vector intrinsic form.
2956 def SSE_SQRTP : OpndItins<
2957 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
2960 def SSE_SQRTS : OpndItins<
2961 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
2964 def SSE_RCPP : OpndItins<
2965 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
2968 def SSE_RCPS : OpndItins<
2969 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
2972 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2973 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2974 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
2975 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2976 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2977 [(set FR32:$dst, (OpNode FR32:$src))]>;
2978 // For scalar unary operations, fold a load into the operation
2979 // only in OptForSize mode. It eliminates an instruction, but it also
2980 // eliminates a whole-register clobber (the load), so it introduces a
2981 // partial register update condition.
2982 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2983 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2984 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
2985 Requires<[HasSSE1, OptForSize]>;
2986 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2987 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2988 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
2989 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2990 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2991 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
2994 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2995 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2996 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2997 !strconcat(OpcodeStr,
2998 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3000 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
3001 !strconcat(OpcodeStr,
3002 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3003 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3004 (ins VR128:$src1, ssmem:$src2),
3005 !strconcat(OpcodeStr,
3006 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3009 /// sse1_fp_unop_p - SSE1 unops in packed form.
3010 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3012 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3013 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3014 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3015 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3016 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3017 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3020 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3021 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3023 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3024 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3025 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3027 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3028 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3029 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3033 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3034 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3035 Intrinsic V4F32Int, OpndItins itins> {
3036 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3037 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3038 [(set VR128:$dst, (V4F32Int VR128:$src))],
3040 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3041 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3042 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3046 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3047 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3048 Intrinsic V4F32Int, OpndItins itins> {
3049 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3050 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3051 [(set VR256:$dst, (V4F32Int VR256:$src))],
3053 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3054 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3055 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3059 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3060 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3061 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3062 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3063 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3064 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3065 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3066 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3067 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3068 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3069 Requires<[HasSSE2, OptForSize]>;
3070 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3071 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3072 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3073 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3074 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3075 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3078 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3079 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3080 let neverHasSideEffects = 1 in {
3081 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3082 !strconcat(OpcodeStr,
3083 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3085 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3086 !strconcat(OpcodeStr,
3087 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3089 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3090 (ins VR128:$src1, sdmem:$src2),
3091 !strconcat(OpcodeStr,
3092 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3095 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3096 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3097 SDNode OpNode, OpndItins itins> {
3098 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3099 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3100 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3101 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3102 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3103 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3106 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3107 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3109 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3110 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3111 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3113 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3114 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3115 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3119 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3120 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3121 Intrinsic V2F64Int, OpndItins itins> {
3122 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3123 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3124 [(set VR128:$dst, (V2F64Int VR128:$src))],
3126 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3127 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3128 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3132 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3133 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3134 Intrinsic V2F64Int, OpndItins itins> {
3135 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3136 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3137 [(set VR256:$dst, (V2F64Int VR256:$src))],
3139 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3140 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3141 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3145 let Predicates = [HasAVX] in {
3147 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3148 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3150 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3151 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3152 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3153 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3154 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3156 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3158 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3160 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3164 // Reciprocal approximations. Note that these typically require refinement
3165 // in order to obtain suitable precision.
3166 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3167 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3168 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3169 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3171 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3174 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3175 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3176 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3177 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3179 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3183 let AddedComplexity = 1 in {
3184 def : Pat<(f32 (fsqrt FR32:$src)),
3185 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3186 def : Pat<(f32 (fsqrt (load addr:$src))),
3187 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3188 Requires<[HasAVX, OptForSize]>;
3189 def : Pat<(f64 (fsqrt FR64:$src)),
3190 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3191 def : Pat<(f64 (fsqrt (load addr:$src))),
3192 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3193 Requires<[HasAVX, OptForSize]>;
3195 def : Pat<(f32 (X86frsqrt FR32:$src)),
3196 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3197 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3198 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3199 Requires<[HasAVX, OptForSize]>;
3201 def : Pat<(f32 (X86frcp FR32:$src)),
3202 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3203 def : Pat<(f32 (X86frcp (load addr:$src))),
3204 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3205 Requires<[HasAVX, OptForSize]>;
3208 let Predicates = [HasAVX], AddedComplexity = 1 in {
3209 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3210 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3211 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3212 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3214 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3215 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3217 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3218 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3219 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3220 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3222 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3223 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3225 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3226 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3227 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3228 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3230 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3231 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3233 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3234 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3235 (VRCPSSr (f32 (IMPLICIT_DEF)),
3236 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3238 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3239 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3243 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3245 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3246 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3247 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3249 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3250 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3252 // Reciprocal approximations. Note that these typically require refinement
3253 // in order to obtain suitable precision.
3254 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3256 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3257 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3259 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3261 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3262 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3264 // There is no f64 version of the reciprocal approximation instructions.
3266 //===----------------------------------------------------------------------===//
3267 // SSE 1 & 2 - Non-temporal stores
3268 //===----------------------------------------------------------------------===//
3270 let AddedComplexity = 400 in { // Prefer non-temporal versions
3271 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3272 (ins f128mem:$dst, VR128:$src),
3273 "movntps\t{$src, $dst|$dst, $src}",
3274 [(alignednontemporalstore (v4f32 VR128:$src),
3276 IIC_SSE_MOVNT>, VEX;
3277 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3278 (ins f128mem:$dst, VR128:$src),
3279 "movntpd\t{$src, $dst|$dst, $src}",
3280 [(alignednontemporalstore (v2f64 VR128:$src),
3282 IIC_SSE_MOVNT>, VEX;
3284 let ExeDomain = SSEPackedInt in
3285 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3286 (ins f128mem:$dst, VR128:$src),
3287 "movntdq\t{$src, $dst|$dst, $src}",
3288 [(alignednontemporalstore (v2i64 VR128:$src),
3290 IIC_SSE_MOVNT>, VEX;
3292 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3293 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3295 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3296 (ins f256mem:$dst, VR256:$src),
3297 "movntps\t{$src, $dst|$dst, $src}",
3298 [(alignednontemporalstore (v8f32 VR256:$src),
3300 IIC_SSE_MOVNT>, VEX;
3301 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3302 (ins f256mem:$dst, VR256:$src),
3303 "movntpd\t{$src, $dst|$dst, $src}",
3304 [(alignednontemporalstore (v4f64 VR256:$src),
3306 IIC_SSE_MOVNT>, VEX;
3307 let ExeDomain = SSEPackedInt in
3308 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3309 (ins f256mem:$dst, VR256:$src),
3310 "movntdq\t{$src, $dst|$dst, $src}",
3311 [(alignednontemporalstore (v4i64 VR256:$src),
3313 IIC_SSE_MOVNT>, VEX;
3316 let AddedComplexity = 400 in { // Prefer non-temporal versions
3317 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3318 "movntps\t{$src, $dst|$dst, $src}",
3319 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3321 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3322 "movntpd\t{$src, $dst|$dst, $src}",
3323 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3326 let ExeDomain = SSEPackedInt in
3327 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3328 "movntdq\t{$src, $dst|$dst, $src}",
3329 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3332 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3333 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3335 // There is no AVX form for instructions below this point
3336 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3337 "movnti{l}\t{$src, $dst|$dst, $src}",
3338 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3340 TB, Requires<[HasSSE2]>;
3341 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3342 "movnti{q}\t{$src, $dst|$dst, $src}",
3343 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3345 TB, Requires<[HasSSE2]>;
3348 //===----------------------------------------------------------------------===//
3349 // SSE 1 & 2 - Prefetch and memory fence
3350 //===----------------------------------------------------------------------===//
3352 // Prefetch intrinsic.
3353 let Predicates = [HasSSE1] in {
3354 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3355 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3356 IIC_SSE_PREFETCH>, TB;
3357 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3358 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3359 IIC_SSE_PREFETCH>, TB;
3360 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3361 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3362 IIC_SSE_PREFETCH>, TB;
3363 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3364 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3365 IIC_SSE_PREFETCH>, TB;
3369 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3370 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3371 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3373 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3374 // was introduced with SSE2, it's backward compatible.
3375 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3377 // Load, store, and memory fence
3378 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3379 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3380 TB, Requires<[HasSSE1]>;
3381 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3382 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3383 TB, Requires<[HasSSE2]>;
3384 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3385 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3386 TB, Requires<[HasSSE2]>;
3388 def : Pat<(X86SFence), (SFENCE)>;
3389 def : Pat<(X86LFence), (LFENCE)>;
3390 def : Pat<(X86MFence), (MFENCE)>;
3392 //===----------------------------------------------------------------------===//
3393 // SSE 1 & 2 - Load/Store XCSR register
3394 //===----------------------------------------------------------------------===//
3396 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3397 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3398 IIC_SSE_LDMXCSR>, VEX;
3399 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3400 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3401 IIC_SSE_STMXCSR>, VEX;
3403 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3404 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3406 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3407 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3410 //===---------------------------------------------------------------------===//
3411 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3412 //===---------------------------------------------------------------------===//
3414 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3416 let neverHasSideEffects = 1 in {
3417 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3418 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3420 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3421 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3424 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3425 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3427 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3428 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3432 let isCodeGenOnly = 1 in {
3433 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3434 "movdqa\t{$src, $dst|$dst, $src}", [],
3437 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3438 "movdqa\t{$src, $dst|$dst, $src}", [],
3441 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3442 "movdqu\t{$src, $dst|$dst, $src}", [],
3445 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3446 "movdqu\t{$src, $dst|$dst, $src}", [],
3451 let canFoldAsLoad = 1, mayLoad = 1 in {
3452 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3453 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3455 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3456 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3458 let Predicates = [HasAVX] in {
3459 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3460 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3462 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3463 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3468 let mayStore = 1 in {
3469 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3470 (ins i128mem:$dst, VR128:$src),
3471 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3473 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3474 (ins i256mem:$dst, VR256:$src),
3475 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3477 let Predicates = [HasAVX] in {
3478 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3479 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3481 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3482 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3487 let neverHasSideEffects = 1 in
3488 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3489 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3491 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3492 "movdqu\t{$src, $dst|$dst, $src}",
3493 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3496 let isCodeGenOnly = 1 in {
3497 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3498 "movdqa\t{$src, $dst|$dst, $src}", [],
3501 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3502 "movdqu\t{$src, $dst|$dst, $src}",
3503 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3506 let canFoldAsLoad = 1, mayLoad = 1 in {
3507 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3508 "movdqa\t{$src, $dst|$dst, $src}",
3509 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3511 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3512 "movdqu\t{$src, $dst|$dst, $src}",
3513 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3515 XS, Requires<[HasSSE2]>;
3518 let mayStore = 1 in {
3519 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3520 "movdqa\t{$src, $dst|$dst, $src}",
3521 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3523 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3524 "movdqu\t{$src, $dst|$dst, $src}",
3525 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3527 XS, Requires<[HasSSE2]>;
3530 // Intrinsic forms of MOVDQU load and store
3531 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3532 "vmovdqu\t{$src, $dst|$dst, $src}",
3533 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3535 XS, VEX, Requires<[HasAVX]>;
3537 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3538 "movdqu\t{$src, $dst|$dst, $src}",
3539 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3541 XS, Requires<[HasSSE2]>;
3543 } // ExeDomain = SSEPackedInt
3545 let Predicates = [HasAVX] in {
3546 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3547 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3550 //===---------------------------------------------------------------------===//
3551 // SSE2 - Packed Integer Arithmetic Instructions
3552 //===---------------------------------------------------------------------===//
3554 def SSE_PMADD : OpndItins<
3555 IIC_SSE_PMADD, IIC_SSE_PMADD
3558 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3560 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3561 RegisterClass RC, PatFrag memop_frag,
3562 X86MemOperand x86memop,
3564 bit IsCommutable = 0,
3566 let isCommutable = IsCommutable in
3567 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3568 (ins RC:$src1, RC:$src2),
3570 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3571 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3572 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3573 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3574 (ins RC:$src1, x86memop:$src2),
3576 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3577 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3578 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3582 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3583 string OpcodeStr, SDNode OpNode,
3584 SDNode OpNode2, RegisterClass RC,
3585 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3586 ShiftOpndItins itins,
3588 // src2 is always 128-bit
3589 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3590 (ins RC:$src1, VR128:$src2),
3592 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3593 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3594 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3596 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3597 (ins RC:$src1, i128mem:$src2),
3599 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3600 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3601 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3602 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3603 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3604 (ins RC:$src1, i32i8imm:$src2),
3606 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3607 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3608 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3611 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3612 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3613 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3614 PatFrag memop_frag, X86MemOperand x86memop,
3616 bit IsCommutable = 0, bit Is2Addr = 1> {
3617 let isCommutable = IsCommutable in
3618 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3619 (ins RC:$src1, RC:$src2),
3621 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3622 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3623 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3624 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3625 (ins RC:$src1, x86memop:$src2),
3627 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3628 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3629 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3630 (bitconvert (memop_frag addr:$src2)))))]>;
3632 } // ExeDomain = SSEPackedInt
3634 // 128-bit Integer Arithmetic
3636 let Predicates = [HasAVX] in {
3637 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3638 i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
3640 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3641 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3642 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3643 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3644 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3645 i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3646 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3647 i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3648 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3649 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3650 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3651 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3652 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3653 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3654 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3655 i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3656 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3657 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3661 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3662 VR128, memopv2i64, i128mem,
3663 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3664 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3665 VR128, memopv2i64, i128mem,
3666 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3667 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3668 VR128, memopv2i64, i128mem,
3669 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3670 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3671 VR128, memopv2i64, i128mem,
3672 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3673 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3674 VR128, memopv2i64, i128mem,
3675 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3676 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3677 VR128, memopv2i64, i128mem,
3678 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3679 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3680 VR128, memopv2i64, i128mem,
3681 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3682 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3683 VR128, memopv2i64, i128mem,
3684 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3685 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3686 VR128, memopv2i64, i128mem,
3687 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3688 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3689 VR128, memopv2i64, i128mem,
3690 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3691 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3692 VR128, memopv2i64, i128mem,
3693 SSE_PMADD, 1, 0>, VEX_4V;
3694 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3695 VR128, memopv2i64, i128mem,
3696 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3697 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3698 VR128, memopv2i64, i128mem,
3699 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3700 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3701 VR128, memopv2i64, i128mem,
3702 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3703 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3704 VR128, memopv2i64, i128mem,
3705 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3706 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3707 VR128, memopv2i64, i128mem,
3708 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3709 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3710 VR128, memopv2i64, i128mem,
3711 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3712 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3713 VR128, memopv2i64, i128mem,
3714 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3717 let Predicates = [HasAVX2] in {
3718 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3719 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3720 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3721 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3722 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3723 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3724 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3725 i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3726 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3727 i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3728 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3729 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3730 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3731 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3732 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3733 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3734 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3735 i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3736 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3737 VR256, memopv4i64, i256mem,
3738 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3741 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3742 VR256, memopv4i64, i256mem,
3743 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3744 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3745 VR256, memopv4i64, i256mem,
3746 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3747 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3748 VR256, memopv4i64, i256mem,
3749 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3750 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3751 VR256, memopv4i64, i256mem,
3752 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3753 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3754 VR256, memopv4i64, i256mem,
3755 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3756 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3757 VR256, memopv4i64, i256mem,
3758 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3759 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3760 VR256, memopv4i64, i256mem,
3761 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3762 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3763 VR256, memopv4i64, i256mem,
3764 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3765 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3766 VR256, memopv4i64, i256mem,
3767 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3768 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3769 VR256, memopv4i64, i256mem,
3770 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3771 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3772 VR256, memopv4i64, i256mem,
3773 SSE_PMADD, 1, 0>, VEX_4V;
3774 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3775 VR256, memopv4i64, i256mem,
3776 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3777 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3778 VR256, memopv4i64, i256mem,
3779 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3780 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3781 VR256, memopv4i64, i256mem,
3782 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3783 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3784 VR256, memopv4i64, i256mem,
3785 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3786 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3787 VR256, memopv4i64, i256mem,
3788 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3789 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3790 VR256, memopv4i64, i256mem,
3791 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3792 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3793 VR256, memopv4i64, i256mem,
3794 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3797 let Constraints = "$src1 = $dst" in {
3798 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3799 i128mem, SSE_INTALU_ITINS_P, 1>;
3800 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3801 i128mem, SSE_INTALU_ITINS_P, 1>;
3802 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3803 i128mem, SSE_INTALU_ITINS_P, 1>;
3804 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3805 i128mem, SSE_INTALUQ_ITINS_P, 1>;
3806 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3807 i128mem, SSE_INTMUL_ITINS_P, 1>;
3808 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3809 i128mem, SSE_INTALU_ITINS_P>;
3810 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3811 i128mem, SSE_INTALU_ITINS_P>;
3812 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3813 i128mem, SSE_INTALU_ITINS_P>;
3814 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3815 i128mem, SSE_INTALUQ_ITINS_P>;
3816 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3817 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3820 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3821 VR128, memopv2i64, i128mem,
3822 SSE_INTALU_ITINS_P>;
3823 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3824 VR128, memopv2i64, i128mem,
3825 SSE_INTALU_ITINS_P>;
3826 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3827 VR128, memopv2i64, i128mem,
3828 SSE_INTALU_ITINS_P>;
3829 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3830 VR128, memopv2i64, i128mem,
3831 SSE_INTALU_ITINS_P>;
3832 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3833 VR128, memopv2i64, i128mem,
3834 SSE_INTALU_ITINS_P, 1>;
3835 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3836 VR128, memopv2i64, i128mem,
3837 SSE_INTALU_ITINS_P, 1>;
3838 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3839 VR128, memopv2i64, i128mem,
3840 SSE_INTALU_ITINS_P, 1>;
3841 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3842 VR128, memopv2i64, i128mem,
3843 SSE_INTALU_ITINS_P, 1>;
3844 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3845 VR128, memopv2i64, i128mem,
3846 SSE_INTMUL_ITINS_P, 1>;
3847 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3848 VR128, memopv2i64, i128mem,
3849 SSE_INTMUL_ITINS_P, 1>;
3850 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3851 VR128, memopv2i64, i128mem,
3853 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3854 VR128, memopv2i64, i128mem,
3855 SSE_INTALU_ITINS_P, 1>;
3856 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3857 VR128, memopv2i64, i128mem,
3858 SSE_INTALU_ITINS_P, 1>;
3859 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3860 VR128, memopv2i64, i128mem,
3861 SSE_INTALU_ITINS_P, 1>;
3862 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3863 VR128, memopv2i64, i128mem,
3864 SSE_INTALU_ITINS_P, 1>;
3865 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3866 VR128, memopv2i64, i128mem,
3867 SSE_INTALU_ITINS_P, 1>;
3868 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3869 VR128, memopv2i64, i128mem,
3870 SSE_INTALU_ITINS_P, 1>;
3871 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3872 VR128, memopv2i64, i128mem,
3873 SSE_INTALU_ITINS_P, 1>;
3875 } // Constraints = "$src1 = $dst"
3877 //===---------------------------------------------------------------------===//
3878 // SSE2 - Packed Integer Logical Instructions
3879 //===---------------------------------------------------------------------===//
3881 let Predicates = [HasAVX] in {
3882 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3883 VR128, v8i16, v8i16, bc_v8i16,
3884 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3885 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3886 VR128, v4i32, v4i32, bc_v4i32,
3887 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3888 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3889 VR128, v2i64, v2i64, bc_v2i64,
3890 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3892 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3893 VR128, v8i16, v8i16, bc_v8i16,
3894 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3895 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3896 VR128, v4i32, v4i32, bc_v4i32,
3897 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3898 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3899 VR128, v2i64, v2i64, bc_v2i64,
3900 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3902 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3903 VR128, v8i16, v8i16, bc_v8i16,
3904 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3905 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3906 VR128, v4i32, v4i32, bc_v4i32,
3907 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3909 let ExeDomain = SSEPackedInt in {
3910 // 128-bit logical shifts.
3911 def VPSLLDQri : PDIi8<0x73, MRM7r,
3912 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3913 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3915 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3917 def VPSRLDQri : PDIi8<0x73, MRM3r,
3918 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3919 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3921 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3923 // PSRADQri doesn't exist in SSE[1-3].
3925 } // Predicates = [HasAVX]
3927 let Predicates = [HasAVX2] in {
3928 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3929 VR256, v16i16, v8i16, bc_v8i16,
3930 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3931 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3932 VR256, v8i32, v4i32, bc_v4i32,
3933 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3934 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3935 VR256, v4i64, v2i64, bc_v2i64,
3936 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3938 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3939 VR256, v16i16, v8i16, bc_v8i16,
3940 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3941 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3942 VR256, v8i32, v4i32, bc_v4i32,
3943 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3944 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3945 VR256, v4i64, v2i64, bc_v2i64,
3946 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3948 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3949 VR256, v16i16, v8i16, bc_v8i16,
3950 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3951 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3952 VR256, v8i32, v4i32, bc_v4i32,
3953 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3955 let ExeDomain = SSEPackedInt in {
3956 // 256-bit logical shifts.
3957 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3958 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3959 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3961 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3963 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3964 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3965 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3967 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3969 // PSRADQYri doesn't exist in SSE[1-3].
3971 } // Predicates = [HasAVX2]
3973 let Constraints = "$src1 = $dst" in {
3974 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3975 VR128, v8i16, v8i16, bc_v8i16,
3976 SSE_INTSHIFT_ITINS_P>;
3977 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3978 VR128, v4i32, v4i32, bc_v4i32,
3979 SSE_INTSHIFT_ITINS_P>;
3980 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3981 VR128, v2i64, v2i64, bc_v2i64,
3982 SSE_INTSHIFT_ITINS_P>;
3984 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3985 VR128, v8i16, v8i16, bc_v8i16,
3986 SSE_INTSHIFT_ITINS_P>;
3987 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3988 VR128, v4i32, v4i32, bc_v4i32,
3989 SSE_INTSHIFT_ITINS_P>;
3990 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3991 VR128, v2i64, v2i64, bc_v2i64,
3992 SSE_INTSHIFT_ITINS_P>;
3994 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3995 VR128, v8i16, v8i16, bc_v8i16,
3996 SSE_INTSHIFT_ITINS_P>;
3997 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3998 VR128, v4i32, v4i32, bc_v4i32,
3999 SSE_INTSHIFT_ITINS_P>;
4001 let ExeDomain = SSEPackedInt in {
4002 // 128-bit logical shifts.
4003 def PSLLDQri : PDIi8<0x73, MRM7r,
4004 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4005 "pslldq\t{$src2, $dst|$dst, $src2}",
4007 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
4008 def PSRLDQri : PDIi8<0x73, MRM3r,
4009 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4010 "psrldq\t{$src2, $dst|$dst, $src2}",
4012 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4013 // PSRADQri doesn't exist in SSE[1-3].
4015 } // Constraints = "$src1 = $dst"
4017 let Predicates = [HasAVX] in {
4018 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4019 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4020 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4021 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4022 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4023 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4025 // Shift up / down and insert zero's.
4026 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4027 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4028 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4029 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4032 let Predicates = [HasAVX2] in {
4033 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4034 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4035 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4036 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4039 let Predicates = [HasSSE2] in {
4040 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4041 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4042 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4043 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4044 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4045 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4047 // Shift up / down and insert zero's.
4048 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4049 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4050 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4051 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4054 //===---------------------------------------------------------------------===//
4055 // SSE2 - Packed Integer Comparison Instructions
4056 //===---------------------------------------------------------------------===//
4058 let Predicates = [HasAVX] in {
4059 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
4060 VR128, memopv2i64, i128mem,
4061 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4062 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
4063 VR128, memopv2i64, i128mem,
4064 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4065 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
4066 VR128, memopv2i64, i128mem,
4067 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4068 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
4069 VR128, memopv2i64, i128mem,
4070 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4071 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
4072 VR128, memopv2i64, i128mem,
4073 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4074 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
4075 VR128, memopv2i64, i128mem,
4076 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4079 let Predicates = [HasAVX2] in {
4080 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
4081 VR256, memopv4i64, i256mem,
4082 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4083 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
4084 VR256, memopv4i64, i256mem,
4085 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4086 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
4087 VR256, memopv4i64, i256mem,
4088 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4089 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
4090 VR256, memopv4i64, i256mem,
4091 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4092 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
4093 VR256, memopv4i64, i256mem,
4094 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4095 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
4096 VR256, memopv4i64, i256mem,
4097 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4100 let Constraints = "$src1 = $dst" in {
4101 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
4102 VR128, memopv2i64, i128mem,
4103 SSE_INTALU_ITINS_P, 1>;
4104 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
4105 VR128, memopv2i64, i128mem,
4106 SSE_INTALU_ITINS_P, 1>;
4107 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
4108 VR128, memopv2i64, i128mem,
4109 SSE_INTALU_ITINS_P, 1>;
4110 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
4111 VR128, memopv2i64, i128mem,
4112 SSE_INTALU_ITINS_P>;
4113 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
4114 VR128, memopv2i64, i128mem,
4115 SSE_INTALU_ITINS_P>;
4116 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
4117 VR128, memopv2i64, i128mem,
4118 SSE_INTALU_ITINS_P>;
4119 } // Constraints = "$src1 = $dst"
4121 //===---------------------------------------------------------------------===//
4122 // SSE2 - Packed Integer Pack Instructions
4123 //===---------------------------------------------------------------------===//
4125 let Predicates = [HasAVX] in {
4126 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4127 VR128, memopv2i64, i128mem,
4128 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4129 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4130 VR128, memopv2i64, i128mem,
4131 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4132 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4133 VR128, memopv2i64, i128mem,
4134 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4137 let Predicates = [HasAVX2] in {
4138 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4139 VR256, memopv4i64, i256mem,
4140 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4141 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4142 VR256, memopv4i64, i256mem,
4143 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4144 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4145 VR256, memopv4i64, i256mem,
4146 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4149 let Constraints = "$src1 = $dst" in {
4150 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4151 VR128, memopv2i64, i128mem,
4152 SSE_INTALU_ITINS_P>;
4153 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4154 VR128, memopv2i64, i128mem,
4155 SSE_INTALU_ITINS_P>;
4156 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4157 VR128, memopv2i64, i128mem,
4158 SSE_INTALU_ITINS_P>;
4159 } // Constraints = "$src1 = $dst"
4161 //===---------------------------------------------------------------------===//
4162 // SSE2 - Packed Integer Shuffle Instructions
4163 //===---------------------------------------------------------------------===//
4165 let ExeDomain = SSEPackedInt in {
4166 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
4167 def ri : Ii8<0x70, MRMSrcReg,
4168 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4169 !strconcat(OpcodeStr,
4170 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4171 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
4173 def mi : Ii8<0x70, MRMSrcMem,
4174 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4175 !strconcat(OpcodeStr,
4176 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4178 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
4183 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
4184 def Yri : Ii8<0x70, MRMSrcReg,
4185 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4186 !strconcat(OpcodeStr,
4187 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4188 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4189 def Ymi : Ii8<0x70, MRMSrcMem,
4190 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4191 !strconcat(OpcodeStr,
4192 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4194 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4195 (i8 imm:$src2))))]>;
4197 } // ExeDomain = SSEPackedInt
4199 let Predicates = [HasAVX] in {
4200 let AddedComplexity = 5 in
4201 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4203 // SSE2 with ImmT == Imm8 and XS prefix.
4204 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4206 // SSE2 with ImmT == Imm8 and XD prefix.
4207 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4209 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4210 (VPSHUFDmi addr:$src1, imm:$imm)>;
4211 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4212 (VPSHUFDri VR128:$src1, imm:$imm)>;
4215 let Predicates = [HasAVX2] in {
4216 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
4217 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>, XS, VEX;
4218 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>, XD, VEX;
4221 let Predicates = [HasSSE2] in {
4222 let AddedComplexity = 5 in
4223 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4225 // SSE2 with ImmT == Imm8 and XS prefix.
4226 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4228 // SSE2 with ImmT == Imm8 and XD prefix.
4229 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4231 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4232 (PSHUFDmi addr:$src1, imm:$imm)>;
4233 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4234 (PSHUFDri VR128:$src1, imm:$imm)>;
4237 //===---------------------------------------------------------------------===//
4238 // SSE2 - Packed Integer Unpack Instructions
4239 //===---------------------------------------------------------------------===//
4241 let ExeDomain = SSEPackedInt in {
4242 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4243 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4244 def rr : PDI<opc, MRMSrcReg,
4245 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4247 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4248 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4249 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4251 def rm : PDI<opc, MRMSrcMem,
4252 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4254 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4255 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4256 [(set VR128:$dst, (OpNode VR128:$src1,
4257 (bc_frag (memopv2i64
4262 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4263 SDNode OpNode, PatFrag bc_frag> {
4264 def Yrr : PDI<opc, MRMSrcReg,
4265 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4266 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4267 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4268 def Yrm : PDI<opc, MRMSrcMem,
4269 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4270 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4271 [(set VR256:$dst, (OpNode VR256:$src1,
4272 (bc_frag (memopv4i64 addr:$src2))))]>;
4275 let Predicates = [HasAVX] in {
4276 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4277 bc_v16i8, 0>, VEX_4V;
4278 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4279 bc_v8i16, 0>, VEX_4V;
4280 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4281 bc_v4i32, 0>, VEX_4V;
4282 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4283 bc_v2i64, 0>, VEX_4V;
4285 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4286 bc_v16i8, 0>, VEX_4V;
4287 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4288 bc_v8i16, 0>, VEX_4V;
4289 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4290 bc_v4i32, 0>, VEX_4V;
4291 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4292 bc_v2i64, 0>, VEX_4V;
4295 let Predicates = [HasAVX2] in {
4296 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4298 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4300 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4302 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4305 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4307 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4309 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4311 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4315 let Constraints = "$src1 = $dst" in {
4316 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4318 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4320 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4322 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4325 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4327 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4329 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4331 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4334 } // ExeDomain = SSEPackedInt
4336 // Patterns for using AVX1 instructions with integer vectors
4337 // Here to give AVX2 priority
4338 let Predicates = [HasAVX] in {
4339 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4340 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
4341 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
4342 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
4343 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4344 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
4345 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
4346 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
4348 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
4349 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
4350 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
4351 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
4352 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
4353 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
4354 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
4355 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
4358 //===---------------------------------------------------------------------===//
4359 // SSE2 - Packed Integer Extract and Insert
4360 //===---------------------------------------------------------------------===//
4362 let ExeDomain = SSEPackedInt in {
4363 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4364 def rri : Ii8<0xC4, MRMSrcReg,
4365 (outs VR128:$dst), (ins VR128:$src1,
4366 GR32:$src2, i32i8imm:$src3),
4368 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4369 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4371 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4372 def rmi : Ii8<0xC4, MRMSrcMem,
4373 (outs VR128:$dst), (ins VR128:$src1,
4374 i16mem:$src2, i32i8imm:$src3),
4376 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4377 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4379 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4380 imm:$src3))], IIC_SSE_PINSRW>;
4384 let Predicates = [HasAVX] in
4385 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4386 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4387 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4388 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4389 imm:$src2))]>, TB, OpSize, VEX;
4390 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4391 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4392 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4393 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4394 imm:$src2))], IIC_SSE_PEXTRW>;
4397 let Predicates = [HasAVX] in {
4398 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4399 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4400 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4401 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4402 []>, TB, OpSize, VEX_4V;
4405 let Constraints = "$src1 = $dst" in
4406 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4408 } // ExeDomain = SSEPackedInt
4410 //===---------------------------------------------------------------------===//
4411 // SSE2 - Packed Mask Creation
4412 //===---------------------------------------------------------------------===//
4414 let ExeDomain = SSEPackedInt in {
4416 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4417 "pmovmskb\t{$src, $dst|$dst, $src}",
4418 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4419 IIC_SSE_MOVMSK>, VEX;
4420 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4421 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4423 let Predicates = [HasAVX2] in {
4424 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4425 "pmovmskb\t{$src, $dst|$dst, $src}",
4426 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4427 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4428 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4431 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4432 "pmovmskb\t{$src, $dst|$dst, $src}",
4433 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4436 } // ExeDomain = SSEPackedInt
4438 //===---------------------------------------------------------------------===//
4439 // SSE2 - Conditional Store
4440 //===---------------------------------------------------------------------===//
4442 let ExeDomain = SSEPackedInt in {
4445 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4446 (ins VR128:$src, VR128:$mask),
4447 "maskmovdqu\t{$mask, $src|$src, $mask}",
4448 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4449 IIC_SSE_MASKMOV>, VEX;
4451 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4452 (ins VR128:$src, VR128:$mask),
4453 "maskmovdqu\t{$mask, $src|$src, $mask}",
4454 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4455 IIC_SSE_MASKMOV>, VEX;
4458 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4459 "maskmovdqu\t{$mask, $src|$src, $mask}",
4460 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4463 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4464 "maskmovdqu\t{$mask, $src|$src, $mask}",
4465 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4468 } // ExeDomain = SSEPackedInt
4470 //===---------------------------------------------------------------------===//
4471 // SSE2 - Move Doubleword
4472 //===---------------------------------------------------------------------===//
4474 //===---------------------------------------------------------------------===//
4475 // Move Int Doubleword to Packed Double Int
4477 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4478 "movd\t{$src, $dst|$dst, $src}",
4480 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4482 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4483 "movd\t{$src, $dst|$dst, $src}",
4485 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4488 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4489 "mov{d|q}\t{$src, $dst|$dst, $src}",
4491 (v2i64 (scalar_to_vector GR64:$src)))],
4492 IIC_SSE_MOVDQ>, VEX;
4493 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4494 "mov{d|q}\t{$src, $dst|$dst, $src}",
4495 [(set FR64:$dst, (bitconvert GR64:$src))],
4496 IIC_SSE_MOVDQ>, VEX;
4498 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4499 "movd\t{$src, $dst|$dst, $src}",
4501 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4502 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4503 "movd\t{$src, $dst|$dst, $src}",
4505 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4507 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4508 "mov{d|q}\t{$src, $dst|$dst, $src}",
4510 (v2i64 (scalar_to_vector GR64:$src)))],
4512 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4513 "mov{d|q}\t{$src, $dst|$dst, $src}",
4514 [(set FR64:$dst, (bitconvert GR64:$src))],
4517 //===---------------------------------------------------------------------===//
4518 // Move Int Doubleword to Single Scalar
4520 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4521 "movd\t{$src, $dst|$dst, $src}",
4522 [(set FR32:$dst, (bitconvert GR32:$src))],
4523 IIC_SSE_MOVDQ>, VEX;
4525 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4526 "movd\t{$src, $dst|$dst, $src}",
4527 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4530 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4531 "movd\t{$src, $dst|$dst, $src}",
4532 [(set FR32:$dst, (bitconvert GR32:$src))],
4535 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4536 "movd\t{$src, $dst|$dst, $src}",
4537 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4540 //===---------------------------------------------------------------------===//
4541 // Move Packed Doubleword Int to Packed Double Int
4543 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4544 "movd\t{$src, $dst|$dst, $src}",
4545 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4546 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4547 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4548 (ins i32mem:$dst, VR128:$src),
4549 "movd\t{$src, $dst|$dst, $src}",
4550 [(store (i32 (vector_extract (v4i32 VR128:$src),
4551 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4553 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4554 "movd\t{$src, $dst|$dst, $src}",
4555 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4556 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4557 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4558 "movd\t{$src, $dst|$dst, $src}",
4559 [(store (i32 (vector_extract (v4i32 VR128:$src),
4560 (iPTR 0))), addr:$dst)],
4563 //===---------------------------------------------------------------------===//
4564 // Move Packed Doubleword Int first element to Doubleword Int
4566 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4567 "mov{d|q}\t{$src, $dst|$dst, $src}",
4568 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4571 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4573 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4574 "mov{d|q}\t{$src, $dst|$dst, $src}",
4575 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4579 //===---------------------------------------------------------------------===//
4580 // Bitcast FR64 <-> GR64
4582 let Predicates = [HasAVX] in
4583 def VMOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4584 "vmovq\t{$src, $dst|$dst, $src}",
4585 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4587 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4588 "mov{d|q}\t{$src, $dst|$dst, $src}",
4589 [(set GR64:$dst, (bitconvert FR64:$src))],
4590 IIC_SSE_MOVDQ>, VEX;
4591 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4592 "movq\t{$src, $dst|$dst, $src}",
4593 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4594 IIC_SSE_MOVDQ>, VEX;
4596 def MOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4597 "movq\t{$src, $dst|$dst, $src}",
4598 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4600 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4601 "mov{d|q}\t{$src, $dst|$dst, $src}",
4602 [(set GR64:$dst, (bitconvert FR64:$src))],
4604 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4605 "movq\t{$src, $dst|$dst, $src}",
4606 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4609 //===---------------------------------------------------------------------===//
4610 // Move Scalar Single to Double Int
4612 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4613 "movd\t{$src, $dst|$dst, $src}",
4614 [(set GR32:$dst, (bitconvert FR32:$src))],
4615 IIC_SSE_MOVD_ToGP>, VEX;
4616 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4617 "movd\t{$src, $dst|$dst, $src}",
4618 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4619 IIC_SSE_MOVDQ>, VEX;
4620 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4621 "movd\t{$src, $dst|$dst, $src}",
4622 [(set GR32:$dst, (bitconvert FR32:$src))],
4624 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4625 "movd\t{$src, $dst|$dst, $src}",
4626 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4629 //===---------------------------------------------------------------------===//
4630 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4632 let AddedComplexity = 15 in {
4633 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4634 "movd\t{$src, $dst|$dst, $src}",
4635 [(set VR128:$dst, (v4i32 (X86vzmovl
4636 (v4i32 (scalar_to_vector GR32:$src)))))],
4637 IIC_SSE_MOVDQ>, VEX;
4638 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4639 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4640 [(set VR128:$dst, (v2i64 (X86vzmovl
4641 (v2i64 (scalar_to_vector GR64:$src)))))],
4645 let AddedComplexity = 15 in {
4646 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4647 "movd\t{$src, $dst|$dst, $src}",
4648 [(set VR128:$dst, (v4i32 (X86vzmovl
4649 (v4i32 (scalar_to_vector GR32:$src)))))],
4651 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4652 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4653 [(set VR128:$dst, (v2i64 (X86vzmovl
4654 (v2i64 (scalar_to_vector GR64:$src)))))],
4658 let AddedComplexity = 20 in {
4659 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4660 "movd\t{$src, $dst|$dst, $src}",
4662 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4663 (loadi32 addr:$src))))))],
4664 IIC_SSE_MOVDQ>, VEX;
4665 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4666 "movd\t{$src, $dst|$dst, $src}",
4668 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4669 (loadi32 addr:$src))))))],
4673 let Predicates = [HasAVX] in {
4674 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4675 let AddedComplexity = 20 in {
4676 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4677 (VMOVZDI2PDIrm addr:$src)>;
4678 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4679 (VMOVZDI2PDIrm addr:$src)>;
4681 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4682 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4683 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4684 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4685 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4686 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4687 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4690 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4691 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4692 (MOVZDI2PDIrm addr:$src)>;
4693 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4694 (MOVZDI2PDIrm addr:$src)>;
4697 // These are the correct encodings of the instructions so that we know how to
4698 // read correct assembly, even though we continue to emit the wrong ones for
4699 // compatibility with Darwin's buggy assembler.
4700 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4701 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4702 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4703 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4704 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4705 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4706 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4707 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4708 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4709 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4710 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4711 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4713 //===---------------------------------------------------------------------===//
4714 // SSE2 - Move Quadword
4715 //===---------------------------------------------------------------------===//
4717 //===---------------------------------------------------------------------===//
4718 // Move Quadword Int to Packed Quadword Int
4720 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4721 "vmovq\t{$src, $dst|$dst, $src}",
4723 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4724 VEX, Requires<[HasAVX]>;
4725 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4726 "movq\t{$src, $dst|$dst, $src}",
4728 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4730 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4732 //===---------------------------------------------------------------------===//
4733 // Move Packed Quadword Int to Quadword Int
4735 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4736 "movq\t{$src, $dst|$dst, $src}",
4737 [(store (i64 (vector_extract (v2i64 VR128:$src),
4738 (iPTR 0))), addr:$dst)],
4739 IIC_SSE_MOVDQ>, VEX;
4740 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4741 "movq\t{$src, $dst|$dst, $src}",
4742 [(store (i64 (vector_extract (v2i64 VR128:$src),
4743 (iPTR 0))), addr:$dst)],
4746 //===---------------------------------------------------------------------===//
4747 // Store / copy lower 64-bits of a XMM register.
4749 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4750 "movq\t{$src, $dst|$dst, $src}",
4751 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4752 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4753 "movq\t{$src, $dst|$dst, $src}",
4754 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4757 let AddedComplexity = 20 in
4758 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4759 "vmovq\t{$src, $dst|$dst, $src}",
4761 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4762 (loadi64 addr:$src))))))],
4764 XS, VEX, Requires<[HasAVX]>;
4766 let AddedComplexity = 20 in
4767 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4768 "movq\t{$src, $dst|$dst, $src}",
4770 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4771 (loadi64 addr:$src))))))],
4773 XS, Requires<[HasSSE2]>;
4775 let Predicates = [HasAVX], AddedComplexity = 20 in {
4776 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4777 (VMOVZQI2PQIrm addr:$src)>;
4778 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4779 (VMOVZQI2PQIrm addr:$src)>;
4780 def : Pat<(v2i64 (X86vzload addr:$src)),
4781 (VMOVZQI2PQIrm addr:$src)>;
4784 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4785 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4786 (MOVZQI2PQIrm addr:$src)>;
4787 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4788 (MOVZQI2PQIrm addr:$src)>;
4789 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4792 let Predicates = [HasAVX] in {
4793 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4794 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4795 def : Pat<(v4i64 (X86vzload addr:$src)),
4796 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4799 //===---------------------------------------------------------------------===//
4800 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4801 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4803 let AddedComplexity = 15 in
4804 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4805 "vmovq\t{$src, $dst|$dst, $src}",
4806 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4808 XS, VEX, Requires<[HasAVX]>;
4809 let AddedComplexity = 15 in
4810 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4811 "movq\t{$src, $dst|$dst, $src}",
4812 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4814 XS, Requires<[HasSSE2]>;
4816 let AddedComplexity = 20 in
4817 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4818 "vmovq\t{$src, $dst|$dst, $src}",
4819 [(set VR128:$dst, (v2i64 (X86vzmovl
4820 (loadv2i64 addr:$src))))],
4822 XS, VEX, Requires<[HasAVX]>;
4823 let AddedComplexity = 20 in {
4824 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4825 "movq\t{$src, $dst|$dst, $src}",
4826 [(set VR128:$dst, (v2i64 (X86vzmovl
4827 (loadv2i64 addr:$src))))],
4829 XS, Requires<[HasSSE2]>;
4832 let AddedComplexity = 20 in {
4833 let Predicates = [HasAVX] in {
4834 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4835 (VMOVZPQILo2PQIrm addr:$src)>;
4836 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4837 (VMOVZPQILo2PQIrr VR128:$src)>;
4839 let Predicates = [HasSSE2] in {
4840 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4841 (MOVZPQILo2PQIrm addr:$src)>;
4842 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4843 (MOVZPQILo2PQIrr VR128:$src)>;
4847 // Instructions to match in the assembler
4848 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4849 "movq\t{$src, $dst|$dst, $src}", [],
4850 IIC_SSE_MOVDQ>, VEX, VEX_W;
4851 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4852 "movq\t{$src, $dst|$dst, $src}", [],
4853 IIC_SSE_MOVDQ>, VEX, VEX_W;
4854 // Recognize "movd" with GR64 destination, but encode as a "movq"
4855 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4856 "movd\t{$src, $dst|$dst, $src}", [],
4857 IIC_SSE_MOVDQ>, VEX, VEX_W;
4859 // Instructions for the disassembler
4860 // xr = XMM register
4863 let Predicates = [HasAVX] in
4864 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4865 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4866 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4867 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4869 //===---------------------------------------------------------------------===//
4870 // SSE3 - Conversion Instructions
4871 //===---------------------------------------------------------------------===//
4873 // Convert Packed Double FP to Packed DW Integers
4874 let Predicates = [HasAVX] in {
4875 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4876 // register, but the same isn't true when using memory operands instead.
4877 // Provide other assembly rr and rm forms to address this explicitly.
4878 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4879 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4880 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4881 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4884 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4885 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4886 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4887 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4890 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4891 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX;
4892 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4893 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4896 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4897 "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
4899 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4900 "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
4903 let Predicates = [HasAVX] in {
4904 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4905 (VCVTTPD2DQYrr VR256:$src)>;
4906 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4907 (VCVTTPD2DQYrm addr:$src)>;
4908 } // Predicates = [HasAVX]
4910 // Convert Packed DW Integers to Packed Double FP
4911 let Predicates = [HasAVX] in {
4912 def VCVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4913 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4914 def VCVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4915 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4916 def VCVTDQ2PDYrm : SSDI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4917 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4918 def VCVTDQ2PDYrr : SSDI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4919 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4922 def CVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4923 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
4925 def CVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4926 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
4929 // 128 bit register conversion intrinsics
4930 let Predicates = [HasAVX] in
4931 def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),
4932 (VCVTDQ2PDrr VR128:$src)>;
4934 let Predicates = [HasSSE2] in
4935 def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),
4936 (CVTDQ2PDrr VR128:$src)>;
4938 // AVX 256-bit register conversion intrinsics
4939 let Predicates = [HasAVX] in {
4940 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4941 (VCVTDQ2PDYrr VR128:$src)>;
4942 def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
4943 (VCVTDQ2PDYrm addr:$src)>;
4945 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4946 (VCVTPD2DQYrr VR256:$src)>;
4947 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4948 (VCVTPD2DQYrm addr:$src)>;
4950 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4951 (VCVTDQ2PDYrr VR128:$src)>;
4952 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
4953 (VCVTDQ2PDYrm addr:$src)>;
4954 } // Predicates = [HasAVX]
4956 //===---------------------------------------------------------------------===//
4957 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4958 //===---------------------------------------------------------------------===//
4959 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4960 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4961 X86MemOperand x86memop> {
4962 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4963 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4964 [(set RC:$dst, (vt (OpNode RC:$src)))],
4966 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4967 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4968 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4972 let Predicates = [HasAVX] in {
4973 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4974 v4f32, VR128, memopv4f32, f128mem>, VEX;
4975 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4976 v4f32, VR128, memopv4f32, f128mem>, VEX;
4977 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4978 v8f32, VR256, memopv8f32, f256mem>, VEX;
4979 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4980 v8f32, VR256, memopv8f32, f256mem>, VEX;
4982 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4983 memopv4f32, f128mem>;
4984 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4985 memopv4f32, f128mem>;
4987 let Predicates = [HasAVX] in {
4988 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4989 (VMOVSHDUPrr VR128:$src)>;
4990 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4991 (VMOVSHDUPrm addr:$src)>;
4992 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4993 (VMOVSLDUPrr VR128:$src)>;
4994 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4995 (VMOVSLDUPrm addr:$src)>;
4996 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4997 (VMOVSHDUPYrr VR256:$src)>;
4998 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4999 (VMOVSHDUPYrm addr:$src)>;
5000 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5001 (VMOVSLDUPYrr VR256:$src)>;
5002 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
5003 (VMOVSLDUPYrm addr:$src)>;
5006 let Predicates = [HasSSE3] in {
5007 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5008 (MOVSHDUPrr VR128:$src)>;
5009 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5010 (MOVSHDUPrm addr:$src)>;
5011 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5012 (MOVSLDUPrr VR128:$src)>;
5013 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5014 (MOVSLDUPrm addr:$src)>;
5017 //===---------------------------------------------------------------------===//
5018 // SSE3 - Replicate Double FP - MOVDDUP
5019 //===---------------------------------------------------------------------===//
5021 multiclass sse3_replicate_dfp<string OpcodeStr> {
5022 let neverHasSideEffects = 1 in
5023 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5024 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5025 [], IIC_SSE_MOV_LH>;
5026 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5027 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5030 (scalar_to_vector (loadf64 addr:$src)))))],
5034 // FIXME: Merge with above classe when there're patterns for the ymm version
5035 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5036 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5037 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5038 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
5039 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5040 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5043 (scalar_to_vector (loadf64 addr:$src)))))]>;
5046 let Predicates = [HasAVX] in {
5047 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5048 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
5051 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5053 let Predicates = [HasAVX] in {
5054 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5055 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5056 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5057 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5058 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5059 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5060 def : Pat<(X86Movddup (bc_v2f64
5061 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5062 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5065 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
5066 (VMOVDDUPYrm addr:$src)>;
5067 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
5068 (VMOVDDUPYrm addr:$src)>;
5069 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5070 (VMOVDDUPYrm addr:$src)>;
5071 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5072 (VMOVDDUPYrr VR256:$src)>;
5075 let Predicates = [HasSSE3] in {
5076 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5077 (MOVDDUPrm addr:$src)>;
5078 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5079 (MOVDDUPrm addr:$src)>;
5080 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5081 (MOVDDUPrm addr:$src)>;
5082 def : Pat<(X86Movddup (bc_v2f64
5083 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5084 (MOVDDUPrm addr:$src)>;
5087 //===---------------------------------------------------------------------===//
5088 // SSE3 - Move Unaligned Integer
5089 //===---------------------------------------------------------------------===//
5091 let Predicates = [HasAVX] in {
5092 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5093 "vlddqu\t{$src, $dst|$dst, $src}",
5094 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5095 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5096 "vlddqu\t{$src, $dst|$dst, $src}",
5097 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
5099 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5100 "lddqu\t{$src, $dst|$dst, $src}",
5101 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5104 //===---------------------------------------------------------------------===//
5105 // SSE3 - Arithmetic
5106 //===---------------------------------------------------------------------===//
5108 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5109 X86MemOperand x86memop, OpndItins itins,
5111 def rr : I<0xD0, MRMSrcReg,
5112 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5114 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5115 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5116 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
5117 def rm : I<0xD0, MRMSrcMem,
5118 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5120 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5121 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5122 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
5125 let Predicates = [HasAVX] in {
5126 let ExeDomain = SSEPackedSingle in {
5127 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5128 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5129 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5130 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5132 let ExeDomain = SSEPackedDouble in {
5133 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5134 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5135 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5136 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5139 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
5140 let ExeDomain = SSEPackedSingle in
5141 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5142 f128mem, SSE_ALU_F32P>, TB, XD;
5143 let ExeDomain = SSEPackedDouble in
5144 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5145 f128mem, SSE_ALU_F64P>, TB, OpSize;
5148 //===---------------------------------------------------------------------===//
5149 // SSE3 Instructions
5150 //===---------------------------------------------------------------------===//
5153 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5154 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5155 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5157 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5158 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5159 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5161 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5163 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5164 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5165 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5166 IIC_SSE_HADDSUB_RM>;
5168 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5169 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5170 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5172 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5173 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5174 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5176 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5178 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5179 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5180 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5181 IIC_SSE_HADDSUB_RM>;
5184 let Predicates = [HasAVX] in {
5185 let ExeDomain = SSEPackedSingle in {
5186 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5187 X86fhadd, 0>, VEX_4V;
5188 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5189 X86fhsub, 0>, VEX_4V;
5190 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5191 X86fhadd, 0>, VEX_4V;
5192 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5193 X86fhsub, 0>, VEX_4V;
5195 let ExeDomain = SSEPackedDouble in {
5196 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5197 X86fhadd, 0>, VEX_4V;
5198 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5199 X86fhsub, 0>, VEX_4V;
5200 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5201 X86fhadd, 0>, VEX_4V;
5202 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5203 X86fhsub, 0>, VEX_4V;
5207 let Constraints = "$src1 = $dst" in {
5208 let ExeDomain = SSEPackedSingle in {
5209 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5210 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5212 let ExeDomain = SSEPackedDouble in {
5213 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5214 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5218 //===---------------------------------------------------------------------===//
5219 // SSSE3 - Packed Absolute Instructions
5220 //===---------------------------------------------------------------------===//
5223 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5224 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5225 Intrinsic IntId128> {
5226 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5228 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5229 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5232 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5234 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5237 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5241 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5242 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5243 Intrinsic IntId256> {
5244 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5246 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5247 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5250 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5252 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5255 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5258 let Predicates = [HasAVX] in {
5259 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5260 int_x86_ssse3_pabs_b_128>, VEX;
5261 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5262 int_x86_ssse3_pabs_w_128>, VEX;
5263 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5264 int_x86_ssse3_pabs_d_128>, VEX;
5267 let Predicates = [HasAVX2] in {
5268 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5269 int_x86_avx2_pabs_b>, VEX;
5270 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5271 int_x86_avx2_pabs_w>, VEX;
5272 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5273 int_x86_avx2_pabs_d>, VEX;
5276 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5277 int_x86_ssse3_pabs_b_128>;
5278 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5279 int_x86_ssse3_pabs_w_128>;
5280 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5281 int_x86_ssse3_pabs_d_128>;
5283 //===---------------------------------------------------------------------===//
5284 // SSSE3 - Packed Binary Operator Instructions
5285 //===---------------------------------------------------------------------===//
5287 def SSE_PHADDSUBD : OpndItins<
5288 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5290 def SSE_PHADDSUBSW : OpndItins<
5291 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5293 def SSE_PHADDSUBW : OpndItins<
5294 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5296 def SSE_PSHUFB : OpndItins<
5297 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5299 def SSE_PSIGN : OpndItins<
5300 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5302 def SSE_PMULHRSW : OpndItins<
5303 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5306 /// SS3I_binop_rm - Simple SSSE3 bin op
5307 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5308 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5309 X86MemOperand x86memop, OpndItins itins,
5311 let isCommutable = 1 in
5312 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5313 (ins RC:$src1, RC:$src2),
5315 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5316 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5317 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5319 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5320 (ins RC:$src1, x86memop:$src2),
5322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5325 (OpVT (OpNode RC:$src1,
5326 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5329 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5330 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5331 Intrinsic IntId128, OpndItins itins,
5333 let isCommutable = 1 in
5334 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5335 (ins VR128:$src1, VR128:$src2),
5337 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5338 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5339 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5341 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5342 (ins VR128:$src1, i128mem:$src2),
5344 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5345 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5347 (IntId128 VR128:$src1,
5348 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5351 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5352 Intrinsic IntId256> {
5353 let isCommutable = 1 in
5354 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5355 (ins VR256:$src1, VR256:$src2),
5356 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5357 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5359 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5360 (ins VR256:$src1, i256mem:$src2),
5361 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5363 (IntId256 VR256:$src1,
5364 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5367 let ImmT = NoImm, Predicates = [HasAVX] in {
5368 let isCommutable = 0 in {
5369 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5370 memopv2i64, i128mem,
5371 SSE_PHADDSUBW, 0>, VEX_4V;
5372 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5373 memopv2i64, i128mem,
5374 SSE_PHADDSUBD, 0>, VEX_4V;
5375 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5376 memopv2i64, i128mem,
5377 SSE_PHADDSUBW, 0>, VEX_4V;
5378 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5379 memopv2i64, i128mem,
5380 SSE_PHADDSUBD, 0>, VEX_4V;
5381 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5382 memopv2i64, i128mem,
5383 SSE_PSIGN, 0>, VEX_4V;
5384 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5385 memopv2i64, i128mem,
5386 SSE_PSIGN, 0>, VEX_4V;
5387 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5388 memopv2i64, i128mem,
5389 SSE_PSIGN, 0>, VEX_4V;
5390 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5391 memopv2i64, i128mem,
5392 SSE_PSHUFB, 0>, VEX_4V;
5393 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5394 int_x86_ssse3_phadd_sw_128,
5395 SSE_PHADDSUBSW, 0>, VEX_4V;
5396 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5397 int_x86_ssse3_phsub_sw_128,
5398 SSE_PHADDSUBSW, 0>, VEX_4V;
5399 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5400 int_x86_ssse3_pmadd_ub_sw_128,
5401 SSE_PMADD, 0>, VEX_4V;
5403 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5404 int_x86_ssse3_pmul_hr_sw_128,
5405 SSE_PMULHRSW, 0>, VEX_4V;
5408 let ImmT = NoImm, Predicates = [HasAVX2] in {
5409 let isCommutable = 0 in {
5410 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5411 memopv4i64, i256mem,
5412 SSE_PHADDSUBW, 0>, VEX_4V;
5413 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5414 memopv4i64, i256mem,
5415 SSE_PHADDSUBW, 0>, VEX_4V;
5416 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5417 memopv4i64, i256mem,
5418 SSE_PHADDSUBW, 0>, VEX_4V;
5419 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5420 memopv4i64, i256mem,
5421 SSE_PHADDSUBW, 0>, VEX_4V;
5422 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5423 memopv4i64, i256mem,
5424 SSE_PHADDSUBW, 0>, VEX_4V;
5425 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5426 memopv4i64, i256mem,
5427 SSE_PHADDSUBW, 0>, VEX_4V;
5428 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5429 memopv4i64, i256mem,
5430 SSE_PHADDSUBW, 0>, VEX_4V;
5431 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5432 memopv4i64, i256mem,
5433 SSE_PHADDSUBW, 0>, VEX_4V;
5434 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5435 int_x86_avx2_phadd_sw>, VEX_4V;
5436 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5437 int_x86_avx2_phsub_sw>, VEX_4V;
5438 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5439 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5441 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5442 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5445 // None of these have i8 immediate fields.
5446 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5447 let isCommutable = 0 in {
5448 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5449 memopv2i64, i128mem, SSE_PHADDSUBW>;
5450 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5451 memopv2i64, i128mem, SSE_PHADDSUBD>;
5452 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5453 memopv2i64, i128mem, SSE_PHADDSUBW>;
5454 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5455 memopv2i64, i128mem, SSE_PHADDSUBD>;
5456 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5457 memopv2i64, i128mem, SSE_PSIGN>;
5458 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5459 memopv2i64, i128mem, SSE_PSIGN>;
5460 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5461 memopv2i64, i128mem, SSE_PSIGN>;
5462 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5463 memopv2i64, i128mem, SSE_PSHUFB>;
5464 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5465 int_x86_ssse3_phadd_sw_128,
5467 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5468 int_x86_ssse3_phsub_sw_128,
5470 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5471 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5473 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5474 int_x86_ssse3_pmul_hr_sw_128,
5478 //===---------------------------------------------------------------------===//
5479 // SSSE3 - Packed Align Instruction Patterns
5480 //===---------------------------------------------------------------------===//
5482 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5483 let neverHasSideEffects = 1 in {
5484 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5485 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5487 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5489 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5490 [], IIC_SSE_PALIGNR>, OpSize;
5492 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5493 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5495 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5497 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5498 [], IIC_SSE_PALIGNR>, OpSize;
5502 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5503 let neverHasSideEffects = 1 in {
5504 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5505 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5507 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5510 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5511 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5513 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5518 let Predicates = [HasAVX] in
5519 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5520 let Predicates = [HasAVX2] in
5521 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5522 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5523 defm PALIGN : ssse3_palign<"palignr">;
5525 let Predicates = [HasAVX2] in {
5526 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5527 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5528 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5529 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5530 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5531 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5532 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5533 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5536 let Predicates = [HasAVX] in {
5537 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5538 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5539 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5540 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5541 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5542 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5543 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5544 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5547 let Predicates = [HasSSSE3] in {
5548 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5549 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5550 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5551 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5552 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5553 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5554 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5555 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5558 //===---------------------------------------------------------------------===//
5559 // SSSE3 - Thread synchronization
5560 //===---------------------------------------------------------------------===//
5562 let usesCustomInserter = 1 in {
5563 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5564 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5565 Requires<[HasSSE3]>;
5566 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5567 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>,
5568 Requires<[HasSSE3]>;
5571 let Uses = [EAX, ECX, EDX] in
5572 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5573 TB, Requires<[HasSSE3]>;
5574 let Uses = [ECX, EAX] in
5575 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", [], IIC_SSE_MWAIT>,
5576 TB, Requires<[HasSSE3]>;
5578 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5579 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5581 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5582 Requires<[In32BitMode]>;
5583 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5584 Requires<[In64BitMode]>;
5586 //===----------------------------------------------------------------------===//
5587 // SSE4.1 - Packed Move with Sign/Zero Extend
5588 //===----------------------------------------------------------------------===//
5590 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5591 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5592 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5593 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5595 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5596 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5598 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5602 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5604 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5605 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5606 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5608 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5609 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5610 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5613 let Predicates = [HasAVX] in {
5614 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5616 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5618 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5620 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5622 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5624 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5628 let Predicates = [HasAVX2] in {
5629 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5630 int_x86_avx2_pmovsxbw>, VEX;
5631 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5632 int_x86_avx2_pmovsxwd>, VEX;
5633 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5634 int_x86_avx2_pmovsxdq>, VEX;
5635 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5636 int_x86_avx2_pmovzxbw>, VEX;
5637 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5638 int_x86_avx2_pmovzxwd>, VEX;
5639 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5640 int_x86_avx2_pmovzxdq>, VEX;
5643 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5644 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5645 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5646 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5647 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5648 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5650 let Predicates = [HasAVX] in {
5651 // Common patterns involving scalar load.
5652 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5653 (VPMOVSXBWrm addr:$src)>;
5654 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5655 (VPMOVSXBWrm addr:$src)>;
5657 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5658 (VPMOVSXWDrm addr:$src)>;
5659 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5660 (VPMOVSXWDrm addr:$src)>;
5662 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5663 (VPMOVSXDQrm addr:$src)>;
5664 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5665 (VPMOVSXDQrm addr:$src)>;
5667 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5668 (VPMOVZXBWrm addr:$src)>;
5669 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5670 (VPMOVZXBWrm addr:$src)>;
5672 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5673 (VPMOVZXWDrm addr:$src)>;
5674 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5675 (VPMOVZXWDrm addr:$src)>;
5677 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5678 (VPMOVZXDQrm addr:$src)>;
5679 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5680 (VPMOVZXDQrm addr:$src)>;
5683 let Predicates = [HasSSE41] in {
5684 // Common patterns involving scalar load.
5685 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5686 (PMOVSXBWrm addr:$src)>;
5687 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5688 (PMOVSXBWrm addr:$src)>;
5690 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5691 (PMOVSXWDrm addr:$src)>;
5692 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5693 (PMOVSXWDrm addr:$src)>;
5695 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5696 (PMOVSXDQrm addr:$src)>;
5697 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5698 (PMOVSXDQrm addr:$src)>;
5700 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5701 (PMOVZXBWrm addr:$src)>;
5702 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5703 (PMOVZXBWrm addr:$src)>;
5705 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5706 (PMOVZXWDrm addr:$src)>;
5707 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5708 (PMOVZXWDrm addr:$src)>;
5710 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5711 (PMOVZXDQrm addr:$src)>;
5712 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5713 (PMOVZXDQrm addr:$src)>;
5716 let Predicates = [HasAVX2] in {
5717 let AddedComplexity = 15 in {
5718 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5719 (VPMOVZXDQYrr VR128:$src)>;
5720 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5721 (VPMOVZXWDYrr VR128:$src)>;
5724 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5725 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5728 let Predicates = [HasAVX] in {
5729 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5730 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5733 let Predicates = [HasSSE41] in {
5734 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5735 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5739 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5740 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5741 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5742 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5744 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5745 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5747 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5751 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5753 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5754 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5755 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5757 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5758 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5760 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5764 let Predicates = [HasAVX] in {
5765 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5767 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5769 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5771 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5775 let Predicates = [HasAVX2] in {
5776 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5777 int_x86_avx2_pmovsxbd>, VEX;
5778 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5779 int_x86_avx2_pmovsxwq>, VEX;
5780 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5781 int_x86_avx2_pmovzxbd>, VEX;
5782 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5783 int_x86_avx2_pmovzxwq>, VEX;
5786 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5787 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5788 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5789 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5791 let Predicates = [HasAVX] in {
5792 // Common patterns involving scalar load
5793 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5794 (VPMOVSXBDrm addr:$src)>;
5795 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5796 (VPMOVSXWQrm addr:$src)>;
5798 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5799 (VPMOVZXBDrm addr:$src)>;
5800 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5801 (VPMOVZXWQrm addr:$src)>;
5804 let Predicates = [HasSSE41] in {
5805 // Common patterns involving scalar load
5806 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5807 (PMOVSXBDrm addr:$src)>;
5808 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5809 (PMOVSXWQrm addr:$src)>;
5811 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5812 (PMOVZXBDrm addr:$src)>;
5813 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5814 (PMOVZXWQrm addr:$src)>;
5817 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5818 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5819 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5820 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5822 // Expecting a i16 load any extended to i32 value.
5823 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5824 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5825 [(set VR128:$dst, (IntId (bitconvert
5826 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5830 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5832 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5833 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5834 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5836 // Expecting a i16 load any extended to i32 value.
5837 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5838 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5839 [(set VR256:$dst, (IntId (bitconvert
5840 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5844 let Predicates = [HasAVX] in {
5845 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5847 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5850 let Predicates = [HasAVX2] in {
5851 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5852 int_x86_avx2_pmovsxbq>, VEX;
5853 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5854 int_x86_avx2_pmovzxbq>, VEX;
5856 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5857 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5859 let Predicates = [HasAVX] in {
5860 // Common patterns involving scalar load
5861 def : Pat<(int_x86_sse41_pmovsxbq
5862 (bitconvert (v4i32 (X86vzmovl
5863 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5864 (VPMOVSXBQrm addr:$src)>;
5866 def : Pat<(int_x86_sse41_pmovzxbq
5867 (bitconvert (v4i32 (X86vzmovl
5868 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5869 (VPMOVZXBQrm addr:$src)>;
5872 let Predicates = [HasSSE41] in {
5873 // Common patterns involving scalar load
5874 def : Pat<(int_x86_sse41_pmovsxbq
5875 (bitconvert (v4i32 (X86vzmovl
5876 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5877 (PMOVSXBQrm addr:$src)>;
5879 def : Pat<(int_x86_sse41_pmovzxbq
5880 (bitconvert (v4i32 (X86vzmovl
5881 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5882 (PMOVZXBQrm addr:$src)>;
5885 //===----------------------------------------------------------------------===//
5886 // SSE4.1 - Extract Instructions
5887 //===----------------------------------------------------------------------===//
5889 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5890 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5891 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5892 (ins VR128:$src1, i32i8imm:$src2),
5893 !strconcat(OpcodeStr,
5894 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5895 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5897 let neverHasSideEffects = 1, mayStore = 1 in
5898 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5899 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5900 !strconcat(OpcodeStr,
5901 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5904 // There's an AssertZext in the way of writing the store pattern
5905 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5908 let Predicates = [HasAVX] in {
5909 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5910 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5911 (ins VR128:$src1, i32i8imm:$src2),
5912 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5915 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5918 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5919 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5920 let neverHasSideEffects = 1, mayStore = 1 in
5921 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5922 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5923 !strconcat(OpcodeStr,
5924 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5927 // There's an AssertZext in the way of writing the store pattern
5928 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5931 let Predicates = [HasAVX] in
5932 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5934 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5937 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5938 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5939 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5940 (ins VR128:$src1, i32i8imm:$src2),
5941 !strconcat(OpcodeStr,
5942 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5944 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5945 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5946 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5947 !strconcat(OpcodeStr,
5948 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5949 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5950 addr:$dst)]>, OpSize;
5953 let Predicates = [HasAVX] in
5954 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5956 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5958 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5959 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5960 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5961 (ins VR128:$src1, i32i8imm:$src2),
5962 !strconcat(OpcodeStr,
5963 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5965 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5966 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5967 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5968 !strconcat(OpcodeStr,
5969 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5970 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5971 addr:$dst)]>, OpSize, REX_W;
5974 let Predicates = [HasAVX] in
5975 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5977 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5979 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5981 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5982 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5983 (ins VR128:$src1, i32i8imm:$src2),
5984 !strconcat(OpcodeStr,
5985 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5987 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5989 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5990 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5991 !strconcat(OpcodeStr,
5992 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5993 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5994 addr:$dst)]>, OpSize;
5997 let ExeDomain = SSEPackedSingle in {
5998 let Predicates = [HasAVX] in {
5999 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6000 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
6001 (ins VR128:$src1, i32i8imm:$src2),
6002 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
6005 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
6008 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6009 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6012 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6014 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6017 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6018 Requires<[HasSSE41]>;
6020 //===----------------------------------------------------------------------===//
6021 // SSE4.1 - Insert Instructions
6022 //===----------------------------------------------------------------------===//
6024 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6025 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6026 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6028 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6030 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6032 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
6033 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6034 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6036 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6038 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6040 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6041 imm:$src3))]>, OpSize;
6044 let Predicates = [HasAVX] in
6045 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6046 let Constraints = "$src1 = $dst" in
6047 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6049 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6050 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6051 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6053 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6055 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6057 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6059 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6060 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6062 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6064 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6066 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6067 imm:$src3)))]>, OpSize;
6070 let Predicates = [HasAVX] in
6071 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6072 let Constraints = "$src1 = $dst" in
6073 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6075 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6076 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6077 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6079 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6081 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6083 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6085 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6086 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6088 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6090 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6092 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6093 imm:$src3)))]>, OpSize;
6096 let Predicates = [HasAVX] in
6097 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6098 let Constraints = "$src1 = $dst" in
6099 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6101 // insertps has a few different modes, there's the first two here below which
6102 // are optimized inserts that won't zero arbitrary elements in the destination
6103 // vector. The next one matches the intrinsic and could zero arbitrary elements
6104 // in the target vector.
6105 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6106 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6107 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6109 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6111 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6113 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6115 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6116 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6118 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6120 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6122 (X86insrtps VR128:$src1,
6123 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6124 imm:$src3))]>, OpSize;
6127 let ExeDomain = SSEPackedSingle in {
6128 let Predicates = [HasAVX] in
6129 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6130 let Constraints = "$src1 = $dst" in
6131 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6134 //===----------------------------------------------------------------------===//
6135 // SSE4.1 - Round Instructions
6136 //===----------------------------------------------------------------------===//
6138 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6139 X86MemOperand x86memop, RegisterClass RC,
6140 PatFrag mem_frag32, PatFrag mem_frag64,
6141 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6142 let ExeDomain = SSEPackedSingle in {
6143 // Intrinsic operation, reg.
6144 // Vector intrinsic operation, reg
6145 def PSr : SS4AIi8<opcps, MRMSrcReg,
6146 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6147 !strconcat(OpcodeStr,
6148 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6149 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6152 // Vector intrinsic operation, mem
6153 def PSm : SS4AIi8<opcps, MRMSrcMem,
6154 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6155 !strconcat(OpcodeStr,
6156 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6158 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6160 } // ExeDomain = SSEPackedSingle
6162 let ExeDomain = SSEPackedDouble in {
6163 // Vector intrinsic operation, reg
6164 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6165 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6166 !strconcat(OpcodeStr,
6167 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6168 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6171 // Vector intrinsic operation, mem
6172 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6173 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6174 !strconcat(OpcodeStr,
6175 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6177 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6179 } // ExeDomain = SSEPackedDouble
6182 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6185 Intrinsic F64Int, bit Is2Addr = 1> {
6186 let ExeDomain = GenericDomain in {
6188 def SSr : SS4AIi8<opcss, MRMSrcReg,
6189 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6191 !strconcat(OpcodeStr,
6192 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6193 !strconcat(OpcodeStr,
6194 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6197 // Intrinsic operation, reg.
6198 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6199 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6201 !strconcat(OpcodeStr,
6202 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6203 !strconcat(OpcodeStr,
6204 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6205 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6208 // Intrinsic operation, mem.
6209 def SSm : SS4AIi8<opcss, MRMSrcMem,
6210 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6212 !strconcat(OpcodeStr,
6213 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6214 !strconcat(OpcodeStr,
6215 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6217 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6221 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6222 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6224 !strconcat(OpcodeStr,
6225 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6226 !strconcat(OpcodeStr,
6227 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6230 // Intrinsic operation, reg.
6231 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6232 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6234 !strconcat(OpcodeStr,
6235 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6236 !strconcat(OpcodeStr,
6237 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6238 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6241 // Intrinsic operation, mem.
6242 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6243 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6245 !strconcat(OpcodeStr,
6246 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6247 !strconcat(OpcodeStr,
6248 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6250 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6252 } // ExeDomain = GenericDomain
6255 // FP round - roundss, roundps, roundsd, roundpd
6256 let Predicates = [HasAVX] in {
6258 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6259 memopv4f32, memopv2f64,
6260 int_x86_sse41_round_ps,
6261 int_x86_sse41_round_pd>, VEX;
6262 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6263 memopv8f32, memopv4f64,
6264 int_x86_avx_round_ps_256,
6265 int_x86_avx_round_pd_256>, VEX;
6266 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6267 int_x86_sse41_round_ss,
6268 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6270 def : Pat<(ffloor FR32:$src),
6271 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6272 def : Pat<(f64 (ffloor FR64:$src)),
6273 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6274 def : Pat<(f32 (fnearbyint FR32:$src)),
6275 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6276 def : Pat<(f64 (fnearbyint FR64:$src)),
6277 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6278 def : Pat<(f32 (fceil FR32:$src)),
6279 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6280 def : Pat<(f64 (fceil FR64:$src)),
6281 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6282 def : Pat<(f32 (frint FR32:$src)),
6283 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6284 def : Pat<(f64 (frint FR64:$src)),
6285 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6286 def : Pat<(f32 (ftrunc FR32:$src)),
6287 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6288 def : Pat<(f64 (ftrunc FR64:$src)),
6289 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6292 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6293 memopv4f32, memopv2f64,
6294 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6295 let Constraints = "$src1 = $dst" in
6296 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6297 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6299 def : Pat<(ffloor FR32:$src),
6300 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6301 def : Pat<(f64 (ffloor FR64:$src)),
6302 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6303 def : Pat<(f32 (fnearbyint FR32:$src)),
6304 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6305 def : Pat<(f64 (fnearbyint FR64:$src)),
6306 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6307 def : Pat<(f32 (fceil FR32:$src)),
6308 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6309 def : Pat<(f64 (fceil FR64:$src)),
6310 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6311 def : Pat<(f32 (frint FR32:$src)),
6312 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6313 def : Pat<(f64 (frint FR64:$src)),
6314 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6315 def : Pat<(f32 (ftrunc FR32:$src)),
6316 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6317 def : Pat<(f64 (ftrunc FR64:$src)),
6318 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6320 //===----------------------------------------------------------------------===//
6321 // SSE4.1 - Packed Bit Test
6322 //===----------------------------------------------------------------------===//
6324 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6325 // the intel intrinsic that corresponds to this.
6326 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6327 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6328 "vptest\t{$src2, $src1|$src1, $src2}",
6329 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6331 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6332 "vptest\t{$src2, $src1|$src1, $src2}",
6333 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6336 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6337 "vptest\t{$src2, $src1|$src1, $src2}",
6338 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6340 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6341 "vptest\t{$src2, $src1|$src1, $src2}",
6342 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6346 let Defs = [EFLAGS] in {
6347 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6348 "ptest\t{$src2, $src1|$src1, $src2}",
6349 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6351 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6352 "ptest\t{$src2, $src1|$src1, $src2}",
6353 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6357 // The bit test instructions below are AVX only
6358 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6359 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6360 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6361 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6362 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6363 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6364 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6365 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6369 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6370 let ExeDomain = SSEPackedSingle in {
6371 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6372 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6374 let ExeDomain = SSEPackedDouble in {
6375 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6376 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6380 //===----------------------------------------------------------------------===//
6381 // SSE4.1 - Misc Instructions
6382 //===----------------------------------------------------------------------===//
6384 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6385 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6386 "popcnt{w}\t{$src, $dst|$dst, $src}",
6387 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6389 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6390 "popcnt{w}\t{$src, $dst|$dst, $src}",
6391 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6392 (implicit EFLAGS)]>, OpSize, XS;
6394 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6395 "popcnt{l}\t{$src, $dst|$dst, $src}",
6396 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6398 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6399 "popcnt{l}\t{$src, $dst|$dst, $src}",
6400 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6401 (implicit EFLAGS)]>, XS;
6403 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6404 "popcnt{q}\t{$src, $dst|$dst, $src}",
6405 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6407 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6408 "popcnt{q}\t{$src, $dst|$dst, $src}",
6409 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6410 (implicit EFLAGS)]>, XS;
6415 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6416 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6417 Intrinsic IntId128> {
6418 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6420 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6421 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6422 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6424 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6427 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6430 let Predicates = [HasAVX] in
6431 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6432 int_x86_sse41_phminposuw>, VEX;
6433 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6434 int_x86_sse41_phminposuw>;
6436 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6437 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6438 Intrinsic IntId128, bit Is2Addr = 1> {
6439 let isCommutable = 1 in
6440 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6441 (ins VR128:$src1, VR128:$src2),
6443 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6444 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6445 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6446 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6447 (ins VR128:$src1, i128mem:$src2),
6449 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6450 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6452 (IntId128 VR128:$src1,
6453 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6456 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6457 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6458 Intrinsic IntId256> {
6459 let isCommutable = 1 in
6460 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6461 (ins VR256:$src1, VR256:$src2),
6462 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6463 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6464 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6465 (ins VR256:$src1, i256mem:$src2),
6466 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6468 (IntId256 VR256:$src1,
6469 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6472 let Predicates = [HasAVX] in {
6473 let isCommutable = 0 in
6474 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6476 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6478 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6480 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6482 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6484 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6486 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6488 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6490 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6492 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6496 let Predicates = [HasAVX2] in {
6497 let isCommutable = 0 in
6498 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6499 int_x86_avx2_packusdw>, VEX_4V;
6500 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6501 int_x86_avx2_pmins_b>, VEX_4V;
6502 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6503 int_x86_avx2_pmins_d>, VEX_4V;
6504 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6505 int_x86_avx2_pminu_d>, VEX_4V;
6506 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6507 int_x86_avx2_pminu_w>, VEX_4V;
6508 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6509 int_x86_avx2_pmaxs_b>, VEX_4V;
6510 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6511 int_x86_avx2_pmaxs_d>, VEX_4V;
6512 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6513 int_x86_avx2_pmaxu_d>, VEX_4V;
6514 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6515 int_x86_avx2_pmaxu_w>, VEX_4V;
6516 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6517 int_x86_avx2_pmul_dq>, VEX_4V;
6520 let Constraints = "$src1 = $dst" in {
6521 let isCommutable = 0 in
6522 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6523 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6524 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6525 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6526 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6527 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6528 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6529 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6530 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6531 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6534 /// SS48I_binop_rm - Simple SSE41 binary operator.
6535 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6536 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6537 X86MemOperand x86memop, bit Is2Addr = 1> {
6538 let isCommutable = 1 in
6539 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6540 (ins RC:$src1, RC:$src2),
6542 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6543 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6544 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6545 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6546 (ins RC:$src1, x86memop:$src2),
6548 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6549 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6551 (OpVT (OpNode RC:$src1,
6552 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6555 let Predicates = [HasAVX] in {
6556 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6557 memopv2i64, i128mem, 0>, VEX_4V;
6558 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6559 memopv2i64, i128mem, 0>, VEX_4V;
6561 let Predicates = [HasAVX2] in {
6562 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6563 memopv4i64, i256mem, 0>, VEX_4V;
6564 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6565 memopv4i64, i256mem, 0>, VEX_4V;
6568 let Constraints = "$src1 = $dst" in {
6569 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6570 memopv2i64, i128mem>;
6571 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6572 memopv2i64, i128mem>;
6575 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6576 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6577 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6578 X86MemOperand x86memop, bit Is2Addr = 1> {
6579 let isCommutable = 1 in
6580 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6581 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6583 !strconcat(OpcodeStr,
6584 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6585 !strconcat(OpcodeStr,
6586 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6587 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6589 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6590 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6592 !strconcat(OpcodeStr,
6593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6594 !strconcat(OpcodeStr,
6595 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6598 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6602 let Predicates = [HasAVX] in {
6603 let isCommutable = 0 in {
6604 let ExeDomain = SSEPackedSingle in {
6605 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6606 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6607 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6608 int_x86_avx_blend_ps_256, VR256, memopv8f32, i256mem, 0>, VEX_4V;
6610 let ExeDomain = SSEPackedDouble in {
6611 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6612 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6613 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6614 int_x86_avx_blend_pd_256, VR256, memopv4f64, i256mem, 0>, VEX_4V;
6616 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6617 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6618 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6619 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6621 let ExeDomain = SSEPackedSingle in
6622 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6623 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6624 let ExeDomain = SSEPackedDouble in
6625 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6626 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6627 let ExeDomain = SSEPackedSingle in
6628 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6629 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6632 let Predicates = [HasAVX2] in {
6633 let isCommutable = 0 in {
6634 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6635 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6636 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6637 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6641 let Constraints = "$src1 = $dst" in {
6642 let isCommutable = 0 in {
6643 let ExeDomain = SSEPackedSingle in
6644 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6645 VR128, memopv4f32, i128mem>;
6646 let ExeDomain = SSEPackedDouble in
6647 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6648 VR128, memopv2f64, i128mem>;
6649 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6650 VR128, memopv2i64, i128mem>;
6651 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6652 VR128, memopv2i64, i128mem>;
6654 let ExeDomain = SSEPackedSingle in
6655 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6656 VR128, memopv4f32, i128mem>;
6657 let ExeDomain = SSEPackedDouble in
6658 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6659 VR128, memopv2f64, i128mem>;
6662 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6663 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6664 RegisterClass RC, X86MemOperand x86memop,
6665 PatFrag mem_frag, Intrinsic IntId> {
6666 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6667 (ins RC:$src1, RC:$src2, RC:$src3),
6668 !strconcat(OpcodeStr,
6669 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6670 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6671 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6673 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6674 (ins RC:$src1, x86memop:$src2, RC:$src3),
6675 !strconcat(OpcodeStr,
6676 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6678 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6680 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6683 let Predicates = [HasAVX] in {
6684 let ExeDomain = SSEPackedDouble in {
6685 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
6686 memopv2f64, int_x86_sse41_blendvpd>;
6687 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
6688 memopv4f64, int_x86_avx_blendv_pd_256>;
6689 } // ExeDomain = SSEPackedDouble
6690 let ExeDomain = SSEPackedSingle in {
6691 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
6692 memopv4f32, int_x86_sse41_blendvps>;
6693 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
6694 memopv8f32, int_x86_avx_blendv_ps_256>;
6695 } // ExeDomain = SSEPackedSingle
6696 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6697 memopv2i64, int_x86_sse41_pblendvb>;
6700 let Predicates = [HasAVX2] in {
6701 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6702 memopv4i64, int_x86_avx2_pblendvb>;
6705 let Predicates = [HasAVX] in {
6706 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6707 (v16i8 VR128:$src2))),
6708 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6709 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6710 (v4i32 VR128:$src2))),
6711 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6712 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6713 (v4f32 VR128:$src2))),
6714 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6715 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6716 (v2i64 VR128:$src2))),
6717 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6718 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6719 (v2f64 VR128:$src2))),
6720 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6721 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6722 (v8i32 VR256:$src2))),
6723 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6724 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6725 (v8f32 VR256:$src2))),
6726 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6727 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6728 (v4i64 VR256:$src2))),
6729 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6730 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6731 (v4f64 VR256:$src2))),
6732 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6734 def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6736 (VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6737 def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6739 (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6741 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6743 (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6744 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6746 (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6747 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6749 (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6752 let Predicates = [HasAVX2] in {
6753 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6754 (v32i8 VR256:$src2))),
6755 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6756 def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6758 (VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6761 /// SS41I_ternary_int - SSE 4.1 ternary operator
6762 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6763 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6765 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6766 (ins VR128:$src1, VR128:$src2),
6767 !strconcat(OpcodeStr,
6768 "\t{$src2, $dst|$dst, $src2}"),
6769 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6772 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6773 (ins VR128:$src1, i128mem:$src2),
6774 !strconcat(OpcodeStr,
6775 "\t{$src2, $dst|$dst, $src2}"),
6778 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6782 let ExeDomain = SSEPackedDouble in
6783 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64,
6784 int_x86_sse41_blendvpd>;
6785 let ExeDomain = SSEPackedSingle in
6786 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32,
6787 int_x86_sse41_blendvps>;
6788 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64,
6789 int_x86_sse41_pblendvb>;
6791 let Predicates = [HasSSE41] in {
6792 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6793 (v16i8 VR128:$src2))),
6794 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6795 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6796 (v4i32 VR128:$src2))),
6797 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6798 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6799 (v4f32 VR128:$src2))),
6800 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6801 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6802 (v2i64 VR128:$src2))),
6803 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6804 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6805 (v2f64 VR128:$src2))),
6806 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6808 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6810 (PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6811 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6813 (BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6814 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6816 (BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6820 let Predicates = [HasAVX] in
6821 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6822 "vmovntdqa\t{$src, $dst|$dst, $src}",
6823 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6825 let Predicates = [HasAVX2] in
6826 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6827 "vmovntdqa\t{$src, $dst|$dst, $src}",
6828 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6830 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6831 "movntdqa\t{$src, $dst|$dst, $src}",
6832 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6835 //===----------------------------------------------------------------------===//
6836 // SSE4.2 - Compare Instructions
6837 //===----------------------------------------------------------------------===//
6839 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6840 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6841 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6842 X86MemOperand x86memop, bit Is2Addr = 1> {
6843 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6844 (ins RC:$src1, RC:$src2),
6846 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6847 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6848 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6850 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6851 (ins RC:$src1, x86memop:$src2),
6853 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6854 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6856 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6859 let Predicates = [HasAVX] in
6860 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6861 memopv2i64, i128mem, 0>, VEX_4V;
6863 let Predicates = [HasAVX2] in
6864 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6865 memopv4i64, i256mem, 0>, VEX_4V;
6867 let Constraints = "$src1 = $dst" in
6868 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6869 memopv2i64, i128mem>;
6871 //===----------------------------------------------------------------------===//
6872 // SSE4.2 - String/text Processing Instructions
6873 //===----------------------------------------------------------------------===//
6875 // Packed Compare Implicit Length Strings, Return Mask
6876 multiclass pseudo_pcmpistrm<string asm> {
6877 def REG : PseudoI<(outs VR128:$dst),
6878 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6879 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6881 def MEM : PseudoI<(outs VR128:$dst),
6882 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6883 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6884 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6887 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6888 let AddedComplexity = 1 in
6889 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6890 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6893 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6894 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6895 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6896 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6898 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6899 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6900 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6903 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6904 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6905 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6906 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6908 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6909 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6910 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6913 // Packed Compare Explicit Length Strings, Return Mask
6914 multiclass pseudo_pcmpestrm<string asm> {
6915 def REG : PseudoI<(outs VR128:$dst),
6916 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6917 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6918 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6919 def MEM : PseudoI<(outs VR128:$dst),
6920 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6921 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6922 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6925 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6926 let AddedComplexity = 1 in
6927 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6928 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6931 let Predicates = [HasAVX],
6932 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6933 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6934 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6935 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6937 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6938 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6939 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6942 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6943 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6944 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6945 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6947 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6948 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6949 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6952 // Packed Compare Implicit Length Strings, Return Index
6953 let Defs = [ECX, EFLAGS] in {
6954 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6955 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6956 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6957 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6958 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6959 (implicit EFLAGS)]>, OpSize;
6960 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6961 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6962 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6963 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6964 (implicit EFLAGS)]>, OpSize;
6968 let Predicates = [HasAVX] in {
6969 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6971 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6973 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6975 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6977 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6979 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6983 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6984 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6985 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6986 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6987 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6988 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6990 // Packed Compare Explicit Length Strings, Return Index
6991 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6992 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6993 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6994 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6995 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6996 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6997 (implicit EFLAGS)]>, OpSize;
6998 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6999 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7000 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7002 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
7003 (implicit EFLAGS)]>, OpSize;
7007 let Predicates = [HasAVX] in {
7008 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
7010 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
7012 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
7014 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
7016 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
7018 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
7022 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
7023 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
7024 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
7025 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
7026 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
7027 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
7029 //===----------------------------------------------------------------------===//
7030 // SSE4.2 - CRC Instructions
7031 //===----------------------------------------------------------------------===//
7033 // No CRC instructions have AVX equivalents
7035 // crc intrinsic instruction
7036 // This set of instructions are only rm, the only difference is the size
7038 let Constraints = "$src1 = $dst" in {
7039 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7040 (ins GR32:$src1, i8mem:$src2),
7041 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7043 (int_x86_sse42_crc32_32_8 GR32:$src1,
7044 (load addr:$src2)))]>;
7045 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7046 (ins GR32:$src1, GR8:$src2),
7047 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7049 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
7050 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7051 (ins GR32:$src1, i16mem:$src2),
7052 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7054 (int_x86_sse42_crc32_32_16 GR32:$src1,
7055 (load addr:$src2)))]>,
7057 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7058 (ins GR32:$src1, GR16:$src2),
7059 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7061 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7063 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7064 (ins GR32:$src1, i32mem:$src2),
7065 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7067 (int_x86_sse42_crc32_32_32 GR32:$src1,
7068 (load addr:$src2)))]>;
7069 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7070 (ins GR32:$src1, GR32:$src2),
7071 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7073 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7074 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7075 (ins GR64:$src1, i8mem:$src2),
7076 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7078 (int_x86_sse42_crc32_64_8 GR64:$src1,
7079 (load addr:$src2)))]>,
7081 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7082 (ins GR64:$src1, GR8:$src2),
7083 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7085 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7087 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7088 (ins GR64:$src1, i64mem:$src2),
7089 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7091 (int_x86_sse42_crc32_64_64 GR64:$src1,
7092 (load addr:$src2)))]>,
7094 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7095 (ins GR64:$src1, GR64:$src2),
7096 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7098 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7102 //===----------------------------------------------------------------------===//
7103 // AES-NI Instructions
7104 //===----------------------------------------------------------------------===//
7106 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7107 Intrinsic IntId128, bit Is2Addr = 1> {
7108 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7109 (ins VR128:$src1, VR128:$src2),
7111 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7112 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7113 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7115 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7116 (ins VR128:$src1, i128mem:$src2),
7118 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7119 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7121 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7124 // Perform One Round of an AES Encryption/Decryption Flow
7125 let Predicates = [HasAVX, HasAES] in {
7126 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7127 int_x86_aesni_aesenc, 0>, VEX_4V;
7128 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7129 int_x86_aesni_aesenclast, 0>, VEX_4V;
7130 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7131 int_x86_aesni_aesdec, 0>, VEX_4V;
7132 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7133 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7136 let Constraints = "$src1 = $dst" in {
7137 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7138 int_x86_aesni_aesenc>;
7139 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7140 int_x86_aesni_aesenclast>;
7141 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7142 int_x86_aesni_aesdec>;
7143 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7144 int_x86_aesni_aesdeclast>;
7147 // Perform the AES InvMixColumn Transformation
7148 let Predicates = [HasAVX, HasAES] in {
7149 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7151 "vaesimc\t{$src1, $dst|$dst, $src1}",
7153 (int_x86_aesni_aesimc VR128:$src1))]>,
7155 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7156 (ins i128mem:$src1),
7157 "vaesimc\t{$src1, $dst|$dst, $src1}",
7158 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7161 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7163 "aesimc\t{$src1, $dst|$dst, $src1}",
7165 (int_x86_aesni_aesimc VR128:$src1))]>,
7167 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7168 (ins i128mem:$src1),
7169 "aesimc\t{$src1, $dst|$dst, $src1}",
7170 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7173 // AES Round Key Generation Assist
7174 let Predicates = [HasAVX, HasAES] in {
7175 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7176 (ins VR128:$src1, i8imm:$src2),
7177 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7179 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7181 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7182 (ins i128mem:$src1, i8imm:$src2),
7183 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7185 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7188 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7189 (ins VR128:$src1, i8imm:$src2),
7190 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7192 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7194 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7195 (ins i128mem:$src1, i8imm:$src2),
7196 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7198 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7201 //===----------------------------------------------------------------------===//
7202 // PCLMUL Instructions
7203 //===----------------------------------------------------------------------===//
7205 // AVX carry-less Multiplication instructions
7206 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7207 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7208 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7210 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7212 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7213 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7214 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7215 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7216 (memopv2i64 addr:$src2), imm:$src3))]>;
7218 // Carry-less Multiplication instructions
7219 let Constraints = "$src1 = $dst" in {
7220 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7221 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7222 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7224 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7226 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7227 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7228 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7229 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7230 (memopv2i64 addr:$src2), imm:$src3))]>;
7231 } // Constraints = "$src1 = $dst"
7234 multiclass pclmul_alias<string asm, int immop> {
7235 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7236 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7238 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7239 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7241 def : InstAlias<!strconcat("vpclmul", asm,
7242 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7243 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7245 def : InstAlias<!strconcat("vpclmul", asm,
7246 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7247 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7249 defm : pclmul_alias<"hqhq", 0x11>;
7250 defm : pclmul_alias<"hqlq", 0x01>;
7251 defm : pclmul_alias<"lqhq", 0x10>;
7252 defm : pclmul_alias<"lqlq", 0x00>;
7254 //===----------------------------------------------------------------------===//
7255 // SSE4A Instructions
7256 //===----------------------------------------------------------------------===//
7258 let Predicates = [HasSSE4A] in {
7260 let Constraints = "$src = $dst" in {
7261 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7262 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7263 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7264 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7265 imm:$idx))]>, TB, OpSize;
7266 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7267 (ins VR128:$src, VR128:$mask),
7268 "extrq\t{$mask, $src|$src, $mask}",
7269 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7270 VR128:$mask))]>, TB, OpSize;
7272 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7273 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7274 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7275 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7276 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7277 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7278 (ins VR128:$src, VR128:$mask),
7279 "insertq\t{$mask, $src|$src, $mask}",
7280 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7281 VR128:$mask))]>, XD;
7284 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7285 "movntss\t{$src, $dst|$dst, $src}",
7286 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7288 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7289 "movntsd\t{$src, $dst|$dst, $src}",
7290 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7293 //===----------------------------------------------------------------------===//
7295 //===----------------------------------------------------------------------===//
7297 //===----------------------------------------------------------------------===//
7298 // VBROADCAST - Load from memory and broadcast to all elements of the
7299 // destination operand
7301 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7302 X86MemOperand x86memop, Intrinsic Int> :
7303 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7304 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7305 [(set RC:$dst, (Int addr:$src))]>, VEX;
7307 // AVX2 adds register forms
7308 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7310 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7311 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7312 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7314 let ExeDomain = SSEPackedSingle in {
7315 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7316 int_x86_avx_vbroadcast_ss>;
7317 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7318 int_x86_avx_vbroadcast_ss_256>;
7320 let ExeDomain = SSEPackedDouble in
7321 def VBROADCASTSDrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7322 int_x86_avx_vbroadcast_sd_256>;
7323 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7324 int_x86_avx_vbroadcastf128_pd_256>;
7326 let ExeDomain = SSEPackedSingle in {
7327 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7328 int_x86_avx2_vbroadcast_ss_ps>;
7329 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7330 int_x86_avx2_vbroadcast_ss_ps_256>;
7332 let ExeDomain = SSEPackedDouble in
7333 def VBROADCASTSDrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7334 int_x86_avx2_vbroadcast_sd_pd_256>;
7336 let Predicates = [HasAVX2] in
7337 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7338 int_x86_avx2_vbroadcasti128>;
7340 let Predicates = [HasAVX] in
7341 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7342 (VBROADCASTF128 addr:$src)>;
7345 //===----------------------------------------------------------------------===//
7346 // VINSERTF128 - Insert packed floating-point values
7348 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7349 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7350 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7351 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7354 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7355 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7356 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7360 let Predicates = [HasAVX] in {
7361 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7363 (VINSERTF128rr VR256:$src1, VR128:$src2,
7364 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7365 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7367 (VINSERTF128rr VR256:$src1, VR128:$src2,
7368 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7369 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7371 (VINSERTF128rr VR256:$src1, VR128:$src2,
7372 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7373 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7375 (VINSERTF128rr VR256:$src1, VR128:$src2,
7376 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7377 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7379 (VINSERTF128rr VR256:$src1, VR128:$src2,
7380 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7381 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7383 (VINSERTF128rr VR256:$src1, VR128:$src2,
7384 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7386 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7388 (VINSERTF128rm VR256:$src1, addr:$src2,
7389 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7390 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7392 (VINSERTF128rm VR256:$src1, addr:$src2,
7393 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7394 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7396 (VINSERTF128rm VR256:$src1, addr:$src2,
7397 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7400 //===----------------------------------------------------------------------===//
7401 // VEXTRACTF128 - Extract packed floating-point values
7403 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7404 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7405 (ins VR256:$src1, i8imm:$src2),
7406 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7409 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7410 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7411 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7415 // Extract and store.
7416 let Predicates = [HasAVX] in {
7417 def : Pat<(alignedstore (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2), addr:$dst),
7418 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7419 def : Pat<(alignedstore (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2), addr:$dst),
7420 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7421 def : Pat<(alignedstore (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2), addr:$dst),
7422 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7424 def : Pat<(int_x86_sse_storeu_ps addr:$dst, (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2)),
7425 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7426 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2)),
7427 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7428 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, (bc_v16i8 (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2))),
7429 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7433 let Predicates = [HasAVX] in {
7434 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
7435 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7436 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
7437 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7438 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
7439 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7441 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7442 (v4f32 (VEXTRACTF128rr
7443 (v8f32 VR256:$src1),
7444 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7445 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7446 (v2f64 (VEXTRACTF128rr
7447 (v4f64 VR256:$src1),
7448 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7449 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7450 (v2i64 (VEXTRACTF128rr
7451 (v4i64 VR256:$src1),
7452 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7453 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7454 (v4i32 (VEXTRACTF128rr
7455 (v8i32 VR256:$src1),
7456 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7457 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7458 (v8i16 (VEXTRACTF128rr
7459 (v16i16 VR256:$src1),
7460 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7461 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7462 (v16i8 (VEXTRACTF128rr
7463 (v32i8 VR256:$src1),
7464 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7467 //===----------------------------------------------------------------------===//
7468 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7470 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7471 Intrinsic IntLd, Intrinsic IntLd256,
7472 Intrinsic IntSt, Intrinsic IntSt256> {
7473 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7474 (ins VR128:$src1, f128mem:$src2),
7475 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7476 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7478 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7479 (ins VR256:$src1, f256mem:$src2),
7480 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7481 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7483 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7484 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7485 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7486 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7487 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7488 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7489 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7490 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7493 let ExeDomain = SSEPackedSingle in
7494 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7495 int_x86_avx_maskload_ps,
7496 int_x86_avx_maskload_ps_256,
7497 int_x86_avx_maskstore_ps,
7498 int_x86_avx_maskstore_ps_256>;
7499 let ExeDomain = SSEPackedDouble in
7500 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7501 int_x86_avx_maskload_pd,
7502 int_x86_avx_maskload_pd_256,
7503 int_x86_avx_maskstore_pd,
7504 int_x86_avx_maskstore_pd_256>;
7506 //===----------------------------------------------------------------------===//
7507 // VPERMIL - Permute Single and Double Floating-Point Values
7509 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7510 RegisterClass RC, X86MemOperand x86memop_f,
7511 X86MemOperand x86memop_i, PatFrag i_frag,
7512 Intrinsic IntVar, ValueType vt> {
7513 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7514 (ins RC:$src1, RC:$src2),
7515 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7516 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7517 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7518 (ins RC:$src1, x86memop_i:$src2),
7519 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7520 [(set RC:$dst, (IntVar RC:$src1,
7521 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7523 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7524 (ins RC:$src1, i8imm:$src2),
7525 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7526 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7527 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7528 (ins x86memop_f:$src1, i8imm:$src2),
7529 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7531 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7534 let ExeDomain = SSEPackedSingle in {
7535 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7536 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7537 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7538 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>;
7540 let ExeDomain = SSEPackedDouble in {
7541 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7542 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7543 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7544 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>;
7547 let Predicates = [HasAVX] in {
7548 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7549 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7550 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7551 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7552 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7554 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7555 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7556 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7558 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7559 (VPERMILPDri VR128:$src1, imm:$imm)>;
7560 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7561 (VPERMILPDmi addr:$src1, imm:$imm)>;
7564 //===----------------------------------------------------------------------===//
7565 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7567 let ExeDomain = SSEPackedSingle in {
7568 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7569 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7570 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7571 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7572 (i8 imm:$src3))))]>, VEX_4V;
7573 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7574 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7575 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7576 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7577 (i8 imm:$src3)))]>, VEX_4V;
7580 let Predicates = [HasAVX] in {
7581 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7582 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7583 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7584 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7585 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7586 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7587 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7588 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7589 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7590 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7592 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1,
7593 (memopv8f32 addr:$src2), (i8 imm:$imm))),
7594 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7595 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7596 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7597 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7598 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7599 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7600 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7601 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7602 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7603 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7604 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7605 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7606 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7607 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7608 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7609 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7612 //===----------------------------------------------------------------------===//
7613 // VZERO - Zero YMM registers
7615 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7616 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7617 // Zero All YMM registers
7618 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7619 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7621 // Zero Upper bits of YMM registers
7622 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7623 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7626 //===----------------------------------------------------------------------===//
7627 // Half precision conversion instructions
7628 //===----------------------------------------------------------------------===//
7629 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7630 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7631 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7632 [(set RC:$dst, (Int VR128:$src))]>,
7634 let neverHasSideEffects = 1, mayLoad = 1 in
7635 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7636 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7639 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7640 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7641 (ins RC:$src1, i32i8imm:$src2),
7642 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7643 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7645 let neverHasSideEffects = 1, mayStore = 1 in
7646 def mr : Ii8<0x1D, MRMDestMem, (outs),
7647 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7648 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7652 let Predicates = [HasAVX, HasF16C] in {
7653 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7654 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7655 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7656 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7659 //===----------------------------------------------------------------------===//
7660 // AVX2 Instructions
7661 //===----------------------------------------------------------------------===//
7663 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7664 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7665 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7666 X86MemOperand x86memop> {
7667 let isCommutable = 1 in
7668 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7669 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7670 !strconcat(OpcodeStr,
7671 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7672 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7674 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7675 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7676 !strconcat(OpcodeStr,
7677 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7680 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7684 let isCommutable = 0 in {
7685 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7686 VR128, memopv2i64, i128mem>;
7687 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7688 VR256, memopv4i64, i256mem>;
7691 //===----------------------------------------------------------------------===//
7692 // VPBROADCAST - Load from memory and broadcast to all elements of the
7693 // destination operand
7695 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7696 X86MemOperand x86memop, PatFrag ld_frag,
7697 Intrinsic Int128, Intrinsic Int256> {
7698 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7699 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7700 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7701 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7702 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7704 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7705 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7706 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7707 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7708 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7709 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7711 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7714 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7715 int_x86_avx2_pbroadcastb_128,
7716 int_x86_avx2_pbroadcastb_256>;
7717 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7718 int_x86_avx2_pbroadcastw_128,
7719 int_x86_avx2_pbroadcastw_256>;
7720 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7721 int_x86_avx2_pbroadcastd_128,
7722 int_x86_avx2_pbroadcastd_256>;
7723 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7724 int_x86_avx2_pbroadcastq_128,
7725 int_x86_avx2_pbroadcastq_256>;
7727 let Predicates = [HasAVX2] in {
7728 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7729 (VPBROADCASTBrm addr:$src)>;
7730 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7731 (VPBROADCASTBYrm addr:$src)>;
7732 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7733 (VPBROADCASTWrm addr:$src)>;
7734 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7735 (VPBROADCASTWYrm addr:$src)>;
7736 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7737 (VPBROADCASTDrm addr:$src)>;
7738 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7739 (VPBROADCASTDYrm addr:$src)>;
7740 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7741 (VPBROADCASTQrm addr:$src)>;
7742 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7743 (VPBROADCASTQYrm addr:$src)>;
7745 // Provide fallback in case the load node that is used in the patterns above
7746 // is used by additional users, which prevents the pattern selection.
7747 let AddedComplexity = 20 in {
7748 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7750 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
7751 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7753 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
7754 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7756 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd))>;
7758 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7760 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
7761 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7763 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
7764 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7766 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd))>;
7770 // AVX1 broadcast patterns
7771 let Predicates = [HasAVX] in {
7772 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7773 (VBROADCASTSSYrm addr:$src)>;
7774 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7775 (VBROADCASTSDrm addr:$src)>;
7776 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7777 (VBROADCASTSSYrm addr:$src)>;
7778 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7779 (VBROADCASTSDrm addr:$src)>;
7780 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7781 (VBROADCASTSSrm addr:$src)>;
7782 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7783 (VBROADCASTSSrm addr:$src)>;
7785 // Provide fallback in case the load node that is used in the patterns above
7786 // is used by additional users, which prevents the pattern selection.
7787 let AddedComplexity = 20 in {
7788 // 128bit broadcasts:
7789 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7791 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0)>;
7792 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7793 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7795 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0),
7798 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss),
7800 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7801 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7803 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd), 0),
7806 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd),
7809 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7811 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0)>;
7812 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7813 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7815 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0),
7818 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss),
7820 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7821 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7823 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd), 0),
7826 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd),
7831 //===----------------------------------------------------------------------===//
7832 // VPERM - Permute instructions
7835 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7837 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7838 (ins VR256:$src1, VR256:$src2),
7839 !strconcat(OpcodeStr,
7840 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7842 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>, VEX_4V;
7843 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7844 (ins VR256:$src1, i256mem:$src2),
7845 !strconcat(OpcodeStr,
7846 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7848 (OpVT (X86VPermv VR256:$src1,
7849 (bitconvert (mem_frag addr:$src2)))))]>,
7853 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7854 let ExeDomain = SSEPackedSingle in
7855 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7857 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7859 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7860 (ins VR256:$src1, i8imm:$src2),
7861 !strconcat(OpcodeStr,
7862 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7864 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>, VEX;
7865 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7866 (ins i256mem:$src1, i8imm:$src2),
7867 !strconcat(OpcodeStr,
7868 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7870 (OpVT (X86VPermi (mem_frag addr:$src1),
7871 (i8 imm:$src2))))]>, VEX;
7874 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7875 let ExeDomain = SSEPackedDouble in
7876 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7878 //===----------------------------------------------------------------------===//
7879 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7881 let AddedComplexity = 1 in {
7882 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7883 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7884 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7885 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7886 (i8 imm:$src3))))]>, VEX_4V;
7887 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7888 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7889 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7890 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7891 (i8 imm:$src3)))]>, VEX_4V;
7894 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7895 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7896 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7897 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7898 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7899 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7900 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7902 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7904 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7905 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7906 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7907 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7908 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7910 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7914 //===----------------------------------------------------------------------===//
7915 // VINSERTI128 - Insert packed integer values
7917 let neverHasSideEffects = 1 in {
7918 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7919 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7920 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7923 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7924 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7925 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7929 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7930 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7932 (VINSERTI128rr VR256:$src1, VR128:$src2,
7933 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7934 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7936 (VINSERTI128rr VR256:$src1, VR128:$src2,
7937 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7938 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7940 (VINSERTI128rr VR256:$src1, VR128:$src2,
7941 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7942 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7944 (VINSERTI128rr VR256:$src1, VR128:$src2,
7945 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7948 //===----------------------------------------------------------------------===//
7949 // VEXTRACTI128 - Extract packed integer values
7951 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7952 (ins VR256:$src1, i8imm:$src2),
7953 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7955 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7957 let neverHasSideEffects = 1, mayStore = 1 in
7958 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7959 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7960 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7962 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7963 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7964 (v2i64 (VEXTRACTI128rr
7965 (v4i64 VR256:$src1),
7966 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7967 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7968 (v4i32 (VEXTRACTI128rr
7969 (v8i32 VR256:$src1),
7970 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7971 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7972 (v8i16 (VEXTRACTI128rr
7973 (v16i16 VR256:$src1),
7974 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7975 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7976 (v16i8 (VEXTRACTI128rr
7977 (v32i8 VR256:$src1),
7978 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7981 //===----------------------------------------------------------------------===//
7982 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7984 multiclass avx2_pmovmask<string OpcodeStr,
7985 Intrinsic IntLd128, Intrinsic IntLd256,
7986 Intrinsic IntSt128, Intrinsic IntSt256> {
7987 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7988 (ins VR128:$src1, i128mem:$src2),
7989 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7990 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7991 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7992 (ins VR256:$src1, i256mem:$src2),
7993 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7994 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7995 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7996 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7997 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7998 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7999 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8000 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8001 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8002 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
8005 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8006 int_x86_avx2_maskload_d,
8007 int_x86_avx2_maskload_d_256,
8008 int_x86_avx2_maskstore_d,
8009 int_x86_avx2_maskstore_d_256>;
8010 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8011 int_x86_avx2_maskload_q,
8012 int_x86_avx2_maskload_q_256,
8013 int_x86_avx2_maskstore_q,
8014 int_x86_avx2_maskstore_q_256>, VEX_W;
8017 //===----------------------------------------------------------------------===//
8018 // Variable Bit Shifts
8020 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8021 ValueType vt128, ValueType vt256> {
8022 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8023 (ins VR128:$src1, VR128:$src2),
8024 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8026 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8028 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8029 (ins VR128:$src1, i128mem:$src2),
8030 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8032 (vt128 (OpNode VR128:$src1,
8033 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8035 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8036 (ins VR256:$src1, VR256:$src2),
8037 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8039 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8041 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8042 (ins VR256:$src1, i256mem:$src2),
8043 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8045 (vt256 (OpNode VR256:$src1,
8046 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8050 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8051 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8052 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8053 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8054 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;