1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // SSE 1 & 2 - Move Instructions
120 //===----------------------------------------------------------------------===//
122 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
123 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
124 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
126 // Loading from memory automatically zeroing upper bits.
127 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
128 PatFrag mem_pat, string OpcodeStr> :
129 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
131 [(set RC:$dst, (mem_pat addr:$src))]>;
133 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
134 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
135 // is used instead. Register-to-register movss/movsd is not modeled as an
136 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
137 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
138 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
139 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
140 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
141 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
143 let canFoldAsLoad = 1, isReMaterializable = 1 in {
144 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
146 let AddedComplexity = 20 in
147 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
150 let Constraints = "$src1 = $dst" in {
151 def MOVSSrr : sse12_move_rr<FR32, v4f32,
152 "movss\t{$src2, $dst|$dst, $src2}">, XS;
153 def MOVSDrr : sse12_move_rr<FR64, v2f64,
154 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
157 let canFoldAsLoad = 1, isReMaterializable = 1 in {
158 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
160 let AddedComplexity = 20 in
161 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
164 let AddedComplexity = 15 in {
165 // Extract the low 32-bit value from one vector and insert it into another.
166 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
167 (MOVSSrr (v4f32 VR128:$src1),
168 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
169 // Extract the low 64-bit value from one vector and insert it into another.
170 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
171 (MOVSDrr (v2f64 VR128:$src1),
172 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
175 // Implicitly promote a 32-bit scalar to a vector.
176 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
177 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
178 // Implicitly promote a 64-bit scalar to a vector.
179 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
180 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
181 // Implicitly promote a 32-bit scalar to a vector.
182 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
183 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
184 // Implicitly promote a 64-bit scalar to a vector.
185 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
186 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
188 let AddedComplexity = 20 in {
189 // MOVSSrm zeros the high parts of the register; represent this
190 // with SUBREG_TO_REG.
191 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
192 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
193 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
194 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
195 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
196 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
197 // MOVSDrm zeros the high parts of the register; represent this
198 // with SUBREG_TO_REG.
199 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
200 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
201 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
202 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
203 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
204 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
205 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
206 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
207 def : Pat<(v2f64 (X86vzload addr:$src)),
208 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
211 // Store scalar value to memory.
212 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
213 "movss\t{$src, $dst|$dst, $src}",
214 [(store FR32:$src, addr:$dst)]>;
215 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
216 "movsd\t{$src, $dst|$dst, $src}",
217 [(store FR64:$src, addr:$dst)]>;
219 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
220 "movss\t{$src, $dst|$dst, $src}",
221 [(store FR32:$src, addr:$dst)]>, XS, VEX;
222 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
223 "movsd\t{$src, $dst|$dst, $src}",
224 [(store FR64:$src, addr:$dst)]>, XD, VEX;
226 // Extract and store.
227 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
230 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
231 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
234 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
236 // Move Aligned/Unaligned floating point values
237 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
238 X86MemOperand x86memop, PatFrag ld_frag,
239 string asm, Domain d,
240 bit IsReMaterializable = 1> {
241 let neverHasSideEffects = 1 in
242 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
243 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
244 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
245 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
246 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
247 [(set RC:$dst, (ld_frag addr:$src))], d>;
250 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
251 "movaps", SSEPackedSingle>, VEX;
252 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
253 "movapd", SSEPackedDouble>, OpSize, VEX;
254 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
255 "movups", SSEPackedSingle>, VEX;
256 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
257 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
259 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
260 "movaps", SSEPackedSingle>, VEX;
261 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
262 "movapd", SSEPackedDouble>, OpSize, VEX;
263 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
264 "movups", SSEPackedSingle>, VEX;
265 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
266 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
267 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
268 "movaps", SSEPackedSingle>, TB;
269 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
270 "movapd", SSEPackedDouble>, TB, OpSize;
271 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
272 "movups", SSEPackedSingle>, TB;
273 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
274 "movupd", SSEPackedDouble, 0>, TB, OpSize;
276 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
277 "movaps\t{$src, $dst|$dst, $src}",
278 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
279 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
280 "movapd\t{$src, $dst|$dst, $src}",
281 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
282 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
283 "movups\t{$src, $dst|$dst, $src}",
284 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
285 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
286 "movupd\t{$src, $dst|$dst, $src}",
287 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
288 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
289 "movaps\t{$src, $dst|$dst, $src}",
290 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
291 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
292 "movapd\t{$src, $dst|$dst, $src}",
293 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
294 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
295 "movups\t{$src, $dst|$dst, $src}",
296 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
297 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
298 "movupd\t{$src, $dst|$dst, $src}",
299 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
301 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
302 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
303 (VMOVUPSYmr addr:$dst, VR256:$src)>;
305 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
306 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
307 (VMOVUPDYmr addr:$dst, VR256:$src)>;
309 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
310 "movaps\t{$src, $dst|$dst, $src}",
311 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
312 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
313 "movapd\t{$src, $dst|$dst, $src}",
314 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
315 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
316 "movups\t{$src, $dst|$dst, $src}",
317 [(store (v4f32 VR128:$src), addr:$dst)]>;
318 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
319 "movupd\t{$src, $dst|$dst, $src}",
320 [(store (v2f64 VR128:$src), addr:$dst)]>;
322 // Intrinsic forms of MOVUPS/D load and store
323 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
324 (ins f128mem:$dst, VR128:$src),
325 "movups\t{$src, $dst|$dst, $src}",
326 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
327 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
328 (ins f128mem:$dst, VR128:$src),
329 "movupd\t{$src, $dst|$dst, $src}",
330 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
332 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
333 "movups\t{$src, $dst|$dst, $src}",
334 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
335 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
336 "movupd\t{$src, $dst|$dst, $src}",
337 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
339 // Move Low/High packed floating point values
340 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
341 PatFrag mov_frag, string base_opc,
343 def PSrm : PI<opc, MRMSrcMem,
344 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
345 !strconcat(base_opc, "s", asm_opr),
348 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
349 SSEPackedSingle>, TB;
351 def PDrm : PI<opc, MRMSrcMem,
352 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
353 !strconcat(base_opc, "d", asm_opr),
354 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
355 (scalar_to_vector (loadf64 addr:$src2)))))],
356 SSEPackedDouble>, TB, OpSize;
359 let AddedComplexity = 20 in {
360 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
361 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
362 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
363 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
365 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
366 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
367 "\t{$src2, $dst|$dst, $src2}">;
368 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
369 "\t{$src2, $dst|$dst, $src2}">;
372 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
373 "movlps\t{$src, $dst|$dst, $src}",
374 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
375 (iPTR 0))), addr:$dst)]>, VEX;
376 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
377 "movlpd\t{$src, $dst|$dst, $src}",
378 [(store (f64 (vector_extract (v2f64 VR128:$src),
379 (iPTR 0))), addr:$dst)]>, VEX;
380 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
381 "movlps\t{$src, $dst|$dst, $src}",
382 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
383 (iPTR 0))), addr:$dst)]>;
384 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
385 "movlpd\t{$src, $dst|$dst, $src}",
386 [(store (f64 (vector_extract (v2f64 VR128:$src),
387 (iPTR 0))), addr:$dst)]>;
389 // v2f64 extract element 1 is always custom lowered to unpack high to low
390 // and extract element 0 so the non-store version isn't too horrible.
391 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
392 "movhps\t{$src, $dst|$dst, $src}",
393 [(store (f64 (vector_extract
394 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
395 (undef)), (iPTR 0))), addr:$dst)]>,
397 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
398 "movhpd\t{$src, $dst|$dst, $src}",
399 [(store (f64 (vector_extract
400 (v2f64 (unpckh VR128:$src, (undef))),
401 (iPTR 0))), addr:$dst)]>,
403 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
404 "movhps\t{$src, $dst|$dst, $src}",
405 [(store (f64 (vector_extract
406 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
407 (undef)), (iPTR 0))), addr:$dst)]>;
408 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
409 "movhpd\t{$src, $dst|$dst, $src}",
410 [(store (f64 (vector_extract
411 (v2f64 (unpckh VR128:$src, (undef))),
412 (iPTR 0))), addr:$dst)]>;
414 let AddedComplexity = 20 in {
415 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
416 (ins VR128:$src1, VR128:$src2),
417 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
419 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
421 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
422 (ins VR128:$src1, VR128:$src2),
423 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
425 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
428 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
429 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
430 (ins VR128:$src1, VR128:$src2),
431 "movlhps\t{$src2, $dst|$dst, $src2}",
433 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
434 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
435 (ins VR128:$src1, VR128:$src2),
436 "movhlps\t{$src2, $dst|$dst, $src2}",
438 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
441 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
442 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
443 let AddedComplexity = 20 in {
444 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
445 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
446 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
447 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
450 //===----------------------------------------------------------------------===//
451 // SSE 1 & 2 - Conversion Instructions
452 //===----------------------------------------------------------------------===//
454 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
455 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
457 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
458 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
459 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
460 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
463 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
464 X86MemOperand x86memop, string asm> {
465 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
467 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
471 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
472 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
473 string asm, Domain d> {
474 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
475 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
476 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
477 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
480 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
481 X86MemOperand x86memop, string asm> {
482 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
483 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
485 (ins DstRC:$src1, x86memop:$src),
486 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
489 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
490 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
491 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
492 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
494 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
495 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
496 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
497 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
500 // The assembler can recognize rr 64-bit instructions by seeing a rxx
501 // register, but the same isn't true when only using memory operands,
502 // provide other assembly "l" and "q" forms to address this explicitly
503 // where appropriate to do so.
504 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
506 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
508 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
510 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
512 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
515 let Predicates = [HasAVX] in {
516 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
517 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
518 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
519 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
520 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
521 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
522 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
523 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
525 def : Pat<(f32 (sint_to_fp GR32:$src)),
526 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
527 def : Pat<(f32 (sint_to_fp GR64:$src)),
528 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
529 def : Pat<(f64 (sint_to_fp GR32:$src)),
530 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
531 def : Pat<(f64 (sint_to_fp GR64:$src)),
532 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
535 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
536 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
537 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
538 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
539 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
540 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
541 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
542 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
543 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
544 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
545 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
546 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
547 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
548 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
549 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
550 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
552 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
553 // and/or XMM operand(s).
555 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
556 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
558 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
559 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
560 [(set DstRC:$dst, (Int SrcRC:$src))]>;
561 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
562 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
563 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
566 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
567 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
568 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
569 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
571 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
572 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
573 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
574 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
575 (ins DstRC:$src1, x86memop:$src2),
577 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
578 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
579 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
582 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
583 f32mem, load, "cvtss2si">, XS, VEX;
584 defm Int_VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
585 int_x86_sse_cvtss2si64, f32mem, load, "cvtss2si">,
587 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
588 f128mem, load, "cvtsd2si">, XD, VEX;
589 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
590 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
593 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
594 // Get rid of this hack or rename the intrinsics, there are several
595 // intructions that only match with the intrinsic form, why create duplicates
596 // to let them be recognized by the assembler?
597 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
598 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
599 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
600 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
601 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
602 f32mem, load, "cvtss2si">, XS;
603 defm Int_CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
604 f32mem, load, "cvtss2si{q}">, XS, REX_W;
605 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
606 f128mem, load, "cvtsd2si{l}">, XD;
607 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
608 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
611 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
612 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
613 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
614 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
616 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
617 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
618 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
619 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
622 let Constraints = "$src1 = $dst" in {
623 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
624 int_x86_sse_cvtsi2ss, i32mem, loadi32,
626 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
627 int_x86_sse_cvtsi642ss, i64mem, loadi64,
628 "cvtsi2ss{q}">, XS, REX_W;
629 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
630 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
632 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
633 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
634 "cvtsi2sd">, XD, REX_W;
639 // Aliases for intrinsics
640 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
641 f32mem, load, "cvttss2si">, XS, VEX;
642 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
643 int_x86_sse_cvttss2si64, f32mem, load,
644 "cvttss2si">, XS, VEX, VEX_W;
645 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
646 f128mem, load, "cvttsd2si">, XD, VEX;
647 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
648 int_x86_sse2_cvttsd2si64, f128mem, load,
649 "cvttsd2si">, XD, VEX, VEX_W;
650 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
651 f32mem, load, "cvttss2si">, XS;
652 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
653 int_x86_sse_cvttss2si64, f32mem, load,
654 "cvttss2si{q}">, XS, REX_W;
655 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
656 f128mem, load, "cvttsd2si">, XD;
657 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
658 int_x86_sse2_cvttsd2si64, f128mem, load,
659 "cvttsd2si{q}">, XD, REX_W;
661 let Pattern = []<dag> in {
662 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
663 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
664 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
665 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
667 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
668 "cvtdq2ps\t{$src, $dst|$dst, $src}",
669 SSEPackedSingle>, TB, VEX;
670 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
671 "cvtdq2ps\t{$src, $dst|$dst, $src}",
672 SSEPackedSingle>, TB, VEX;
674 let Pattern = []<dag> in {
675 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
676 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
677 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
678 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
679 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
680 "cvtdq2ps\t{$src, $dst|$dst, $src}",
681 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
686 // Convert scalar double to scalar single
687 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
688 (ins FR64:$src1, FR64:$src2),
689 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
691 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
692 (ins FR64:$src1, f64mem:$src2),
693 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
694 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
695 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
698 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
699 "cvtsd2ss\t{$src, $dst|$dst, $src}",
700 [(set FR32:$dst, (fround FR64:$src))]>;
701 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
702 "cvtsd2ss\t{$src, $dst|$dst, $src}",
703 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
704 Requires<[HasSSE2, OptForSize]>;
706 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
707 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
709 let Constraints = "$src1 = $dst" in
710 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
711 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
713 // Convert scalar single to scalar double
714 // SSE2 instructions with XS prefix
715 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
716 (ins FR32:$src1, FR32:$src2),
717 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
718 []>, XS, Requires<[HasAVX]>, VEX_4V;
719 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
720 (ins FR32:$src1, f32mem:$src2),
721 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
722 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
724 let Predicates = [HasAVX] in {
725 def : Pat<(f64 (fextend FR32:$src)),
726 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
727 def : Pat<(fextend (loadf32 addr:$src)),
728 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
729 def : Pat<(extloadf32 addr:$src),
730 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
733 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
734 "cvtss2sd\t{$src, $dst|$dst, $src}",
735 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
737 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
738 "cvtss2sd\t{$src, $dst|$dst, $src}",
739 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
740 Requires<[HasSSE2, OptForSize]>;
742 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
743 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
744 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
745 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
746 VR128:$src2))]>, XS, VEX_4V,
748 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
749 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
750 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
751 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
752 (load addr:$src2)))]>, XS, VEX_4V,
754 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
755 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
756 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
757 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
758 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
761 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
762 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
763 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
764 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
765 (load addr:$src2)))]>, XS,
769 def : Pat<(extloadf32 addr:$src),
770 (CVTSS2SDrr (MOVSSrm addr:$src))>,
771 Requires<[HasSSE2, OptForSpeed]>;
773 // Convert doubleword to packed single/double fp
774 // SSE2 instructions without OpSize prefix
775 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
776 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
777 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
778 TB, VEX, Requires<[HasAVX]>;
779 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
780 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
781 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
782 (bitconvert (memopv2i64 addr:$src))))]>,
783 TB, VEX, Requires<[HasAVX]>;
784 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
785 "cvtdq2ps\t{$src, $dst|$dst, $src}",
786 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
787 TB, Requires<[HasSSE2]>;
788 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
789 "cvtdq2ps\t{$src, $dst|$dst, $src}",
790 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
791 (bitconvert (memopv2i64 addr:$src))))]>,
792 TB, Requires<[HasSSE2]>;
794 // FIXME: why the non-intrinsic version is described as SSE3?
795 // SSE2 instructions with XS prefix
796 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
797 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
798 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
799 XS, VEX, Requires<[HasAVX]>;
800 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
801 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
802 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
803 (bitconvert (memopv2i64 addr:$src))))]>,
804 XS, VEX, Requires<[HasAVX]>;
805 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
806 "cvtdq2pd\t{$src, $dst|$dst, $src}",
807 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
808 XS, Requires<[HasSSE2]>;
809 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
810 "cvtdq2pd\t{$src, $dst|$dst, $src}",
811 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
812 (bitconvert (memopv2i64 addr:$src))))]>,
813 XS, Requires<[HasSSE2]>;
816 // Convert packed single/double fp to doubleword
817 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
818 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
819 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
820 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
821 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
822 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
823 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
824 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
825 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
826 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
827 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
828 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
830 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
831 "cvtps2dq\t{$src, $dst|$dst, $src}",
832 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
834 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
836 "cvtps2dq\t{$src, $dst|$dst, $src}",
837 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
838 (memop addr:$src)))]>, VEX;
839 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
840 "cvtps2dq\t{$src, $dst|$dst, $src}",
841 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
842 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
843 "cvtps2dq\t{$src, $dst|$dst, $src}",
844 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
845 (memop addr:$src)))]>;
847 // SSE2 packed instructions with XD prefix
848 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
849 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
850 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
851 XD, VEX, Requires<[HasAVX]>;
852 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
853 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
854 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
855 (memop addr:$src)))]>,
856 XD, VEX, Requires<[HasAVX]>;
857 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
858 "cvtpd2dq\t{$src, $dst|$dst, $src}",
859 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
860 XD, Requires<[HasSSE2]>;
861 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
862 "cvtpd2dq\t{$src, $dst|$dst, $src}",
863 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
864 (memop addr:$src)))]>,
865 XD, Requires<[HasSSE2]>;
868 // Convert with truncation packed single/double fp to doubleword
869 // SSE2 packed instructions with XS prefix
870 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
871 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
872 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
873 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
874 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
875 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
876 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
877 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
878 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
879 "cvttps2dq\t{$src, $dst|$dst, $src}",
881 (int_x86_sse2_cvttps2dq VR128:$src))]>;
882 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
883 "cvttps2dq\t{$src, $dst|$dst, $src}",
885 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
887 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
888 "vcvttps2dq\t{$src, $dst|$dst, $src}",
890 (int_x86_sse2_cvttps2dq VR128:$src))]>,
891 XS, VEX, Requires<[HasAVX]>;
892 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
893 "vcvttps2dq\t{$src, $dst|$dst, $src}",
894 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
895 (memop addr:$src)))]>,
896 XS, VEX, Requires<[HasAVX]>;
898 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
899 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
900 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
901 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
903 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
904 (VCVTDQ2PSYrr VR256:$src)>, Requires<[HasAVX]>;
905 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
906 (VCVTTPS2DQYrr VR256:$src)>, Requires<[HasAVX]>;
908 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
910 "cvttpd2dq\t{$src, $dst|$dst, $src}",
911 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
913 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
915 "cvttpd2dq\t{$src, $dst|$dst, $src}",
916 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
917 (memop addr:$src)))]>, VEX;
918 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
919 "cvttpd2dq\t{$src, $dst|$dst, $src}",
920 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
921 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
922 "cvttpd2dq\t{$src, $dst|$dst, $src}",
923 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
924 (memop addr:$src)))]>;
926 // The assembler can recognize rr 256-bit instructions by seeing a ymm
927 // register, but the same isn't true when using memory operands instead.
928 // Provide other assembly rr and rm forms to address this explicitly.
929 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
930 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
931 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
932 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
935 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
936 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
937 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
938 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
941 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
942 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
943 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
944 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
946 // Convert packed single to packed double
947 let Predicates = [HasAVX] in {
948 // SSE2 instructions without OpSize prefix
949 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
950 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
951 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
952 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
953 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
954 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
955 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
956 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
958 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
959 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
960 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
961 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
963 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
964 "vcvtps2pd\t{$src, $dst|$dst, $src}",
965 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
966 VEX, Requires<[HasAVX]>;
967 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
968 "vcvtps2pd\t{$src, $dst|$dst, $src}",
969 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
970 (load addr:$src)))]>,
971 VEX, Requires<[HasAVX]>;
972 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
973 "cvtps2pd\t{$src, $dst|$dst, $src}",
974 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
975 TB, Requires<[HasSSE2]>;
976 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
977 "cvtps2pd\t{$src, $dst|$dst, $src}",
978 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
979 (load addr:$src)))]>,
980 TB, Requires<[HasSSE2]>;
982 // Convert packed double to packed single
983 // The assembler can recognize rr 256-bit instructions by seeing a ymm
984 // register, but the same isn't true when using memory operands instead.
985 // Provide other assembly rr and rm forms to address this explicitly.
986 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
987 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
988 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
989 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
992 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
993 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
994 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
995 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
998 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
999 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1000 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1001 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1002 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1003 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1004 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1005 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1008 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1009 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1010 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1011 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1013 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1014 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1015 (memop addr:$src)))]>;
1016 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1017 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1018 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1019 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1020 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1021 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1022 (memop addr:$src)))]>;
1024 // AVX 256-bit register conversion intrinsics
1025 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1026 // whenever possible to avoid declaring two versions of each one.
1027 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1028 (VCVTDQ2PSYrr VR256:$src)>;
1029 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1030 (VCVTDQ2PSYrm addr:$src)>;
1032 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1033 (VCVTPD2PSYrr VR256:$src)>;
1034 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1035 (VCVTPD2PSYrm addr:$src)>;
1037 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1038 (VCVTPS2DQYrr VR256:$src)>;
1039 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1040 (VCVTPS2DQYrm addr:$src)>;
1042 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1043 (VCVTPS2PDYrr VR128:$src)>;
1044 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1045 (VCVTPS2PDYrm addr:$src)>;
1047 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1048 (VCVTTPD2DQYrr VR256:$src)>;
1049 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1050 (VCVTTPD2DQYrm addr:$src)>;
1052 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1053 (VCVTTPS2DQYrr VR256:$src)>;
1054 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1055 (VCVTTPS2DQYrm addr:$src)>;
1057 //===----------------------------------------------------------------------===//
1058 // SSE 1 & 2 - Compare Instructions
1059 //===----------------------------------------------------------------------===//
1061 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1062 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1063 string asm, string asm_alt> {
1064 let isAsmParserOnly = 1 in {
1065 def rr : SIi8<0xC2, MRMSrcReg,
1066 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1069 def rm : SIi8<0xC2, MRMSrcMem,
1070 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1074 // Accept explicit immediate argument form instead of comparison code.
1075 def rr_alt : SIi8<0xC2, MRMSrcReg,
1076 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1079 def rm_alt : SIi8<0xC2, MRMSrcMem,
1080 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1084 let neverHasSideEffects = 1 in {
1085 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1086 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1087 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1089 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1090 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1091 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1095 let Constraints = "$src1 = $dst" in {
1096 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
1097 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
1098 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1099 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
1100 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
1101 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
1102 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1103 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
1104 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
1105 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
1106 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1107 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
1108 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
1109 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
1110 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1111 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
1113 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1114 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
1115 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
1116 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1117 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
1118 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
1119 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1120 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
1121 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1122 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1123 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
1124 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1125 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1128 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1129 Intrinsic Int, string asm> {
1130 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1131 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1132 [(set VR128:$dst, (Int VR128:$src1,
1133 VR128:$src, imm:$cc))]>;
1134 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1135 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1136 [(set VR128:$dst, (Int VR128:$src1,
1137 (load addr:$src), imm:$cc))]>;
1140 // Aliases to match intrinsics which expect XMM operand(s).
1141 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1142 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1144 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1145 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1147 let Constraints = "$src1 = $dst" in {
1148 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1149 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1150 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1151 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1155 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1156 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1157 ValueType vt, X86MemOperand x86memop,
1158 PatFrag ld_frag, string OpcodeStr, Domain d> {
1159 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1160 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1161 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1162 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1163 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1164 [(set EFLAGS, (OpNode (vt RC:$src1),
1165 (ld_frag addr:$src2)))], d>;
1168 let Defs = [EFLAGS] in {
1169 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1170 "ucomiss", SSEPackedSingle>, VEX;
1171 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1172 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1173 let Pattern = []<dag> in {
1174 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1175 "comiss", SSEPackedSingle>, VEX;
1176 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1177 "comisd", SSEPackedDouble>, OpSize, VEX;
1180 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1181 load, "ucomiss", SSEPackedSingle>, VEX;
1182 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1183 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1185 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1186 load, "comiss", SSEPackedSingle>, VEX;
1187 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1188 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1189 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1190 "ucomiss", SSEPackedSingle>, TB;
1191 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1192 "ucomisd", SSEPackedDouble>, TB, OpSize;
1194 let Pattern = []<dag> in {
1195 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1196 "comiss", SSEPackedSingle>, TB;
1197 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1198 "comisd", SSEPackedDouble>, TB, OpSize;
1201 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1202 load, "ucomiss", SSEPackedSingle>, TB;
1203 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1204 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1206 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1207 "comiss", SSEPackedSingle>, TB;
1208 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1209 "comisd", SSEPackedDouble>, TB, OpSize;
1210 } // Defs = [EFLAGS]
1212 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1213 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1214 Intrinsic Int, string asm, string asm_alt,
1216 let isAsmParserOnly = 1 in {
1217 def rri : PIi8<0xC2, MRMSrcReg,
1218 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1219 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1220 def rmi : PIi8<0xC2, MRMSrcMem,
1221 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1222 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1225 // Accept explicit immediate argument form instead of comparison code.
1226 def rri_alt : PIi8<0xC2, MRMSrcReg,
1227 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1229 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1230 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1234 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1235 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1236 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1237 SSEPackedSingle>, VEX_4V;
1238 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1239 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1240 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1241 SSEPackedDouble>, OpSize, VEX_4V;
1242 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1243 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1244 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1245 SSEPackedSingle>, VEX_4V;
1246 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1247 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1248 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1249 SSEPackedDouble>, OpSize, VEX_4V;
1250 let Constraints = "$src1 = $dst" in {
1251 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1252 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1253 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1254 SSEPackedSingle>, TB;
1255 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1256 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1257 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1258 SSEPackedDouble>, TB, OpSize;
1261 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1262 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1263 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1264 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1265 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1266 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1267 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1268 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1270 //===----------------------------------------------------------------------===//
1271 // SSE 1 & 2 - Shuffle Instructions
1272 //===----------------------------------------------------------------------===//
1274 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1275 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1276 ValueType vt, string asm, PatFrag mem_frag,
1277 Domain d, bit IsConvertibleToThreeAddress = 0> {
1278 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1279 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1280 [(set RC:$dst, (vt (shufp:$src3
1281 RC:$src1, (mem_frag addr:$src2))))], d>;
1282 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1283 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1284 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1286 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1289 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1290 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1291 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
1292 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1293 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1294 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
1295 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1296 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1297 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1298 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1299 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1300 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1302 let Constraints = "$src1 = $dst" in {
1303 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1304 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1305 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1307 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1308 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1309 memopv2f64, SSEPackedDouble>, TB, OpSize;
1312 //===----------------------------------------------------------------------===//
1313 // SSE 1 & 2 - Unpack Instructions
1314 //===----------------------------------------------------------------------===//
1316 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1317 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1318 PatFrag mem_frag, RegisterClass RC,
1319 X86MemOperand x86memop, string asm,
1321 def rr : PI<opc, MRMSrcReg,
1322 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1324 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1325 def rm : PI<opc, MRMSrcMem,
1326 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1328 (vt (OpNode RC:$src1,
1329 (mem_frag addr:$src2))))], d>;
1332 let AddedComplexity = 10 in {
1333 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1334 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1335 SSEPackedSingle>, VEX_4V;
1336 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1337 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1338 SSEPackedDouble>, OpSize, VEX_4V;
1339 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1340 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1341 SSEPackedSingle>, VEX_4V;
1342 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1343 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1344 SSEPackedDouble>, OpSize, VEX_4V;
1346 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1347 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1348 SSEPackedSingle>, VEX_4V;
1349 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1350 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1351 SSEPackedDouble>, OpSize, VEX_4V;
1352 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1353 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1354 SSEPackedSingle>, VEX_4V;
1355 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1356 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1357 SSEPackedDouble>, OpSize, VEX_4V;
1359 let Constraints = "$src1 = $dst" in {
1360 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1361 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1362 SSEPackedSingle>, TB;
1363 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1364 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1365 SSEPackedDouble>, TB, OpSize;
1366 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1367 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1368 SSEPackedSingle>, TB;
1369 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1370 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1371 SSEPackedDouble>, TB, OpSize;
1372 } // Constraints = "$src1 = $dst"
1373 } // AddedComplexity
1375 //===----------------------------------------------------------------------===//
1376 // SSE 1 & 2 - Extract Floating-Point Sign mask
1377 //===----------------------------------------------------------------------===//
1379 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1380 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1382 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1383 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1384 [(set GR32:$dst, (Int RC:$src))], d>;
1385 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1386 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1390 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1391 "movmskps", SSEPackedSingle>, VEX;
1392 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1393 "movmskpd", SSEPackedDouble>, OpSize,
1395 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1396 "movmskps", SSEPackedSingle>, VEX;
1397 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1398 "movmskpd", SSEPackedDouble>, OpSize,
1400 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1401 SSEPackedSingle>, TB;
1402 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1403 SSEPackedDouble>, TB, OpSize;
1406 def MOVMSKPDrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1407 "movmskpd\t{$src, $dst|$dst, $src}",
1408 [(set GR32:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1409 def MOVMSKPDrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1410 "movmskpd\t{$src, $dst|$dst, $src}",
1411 [(set GR64:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1412 def MOVMSKPSrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
1413 "movmskps\t{$src, $dst|$dst, $src}",
1414 [(set GR32:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1415 def MOVMSKPSrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1416 "movmskps\t{$src, $dst|$dst, $src}",
1417 [(set GR64:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1420 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1421 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1422 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1423 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1425 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1426 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1427 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1428 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1431 //===----------------------------------------------------------------------===//
1432 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1433 //===----------------------------------------------------------------------===//
1435 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1436 // names that start with 'Fs'.
1438 // Alias instructions that map fld0 to pxor for sse.
1439 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1440 canFoldAsLoad = 1 in {
1441 // FIXME: Set encoding to pseudo!
1442 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1443 [(set FR32:$dst, fp32imm0)]>,
1444 Requires<[HasSSE1]>, TB, OpSize;
1445 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1446 [(set FR64:$dst, fpimm0)]>,
1447 Requires<[HasSSE2]>, TB, OpSize;
1448 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1449 [(set FR32:$dst, fp32imm0)]>,
1450 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1451 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1452 [(set FR64:$dst, fpimm0)]>,
1453 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1456 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1457 // bits are disregarded.
1458 let neverHasSideEffects = 1 in {
1459 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1460 "movaps\t{$src, $dst|$dst, $src}", []>;
1461 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1462 "movapd\t{$src, $dst|$dst, $src}", []>;
1465 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1466 // bits are disregarded.
1467 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1468 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1469 "movaps\t{$src, $dst|$dst, $src}",
1470 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1471 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1472 "movapd\t{$src, $dst|$dst, $src}",
1473 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1476 //===----------------------------------------------------------------------===//
1477 // SSE 1 & 2 - Logical Instructions
1478 //===----------------------------------------------------------------------===//
1480 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1482 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1484 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1485 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1487 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1488 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1490 let Constraints = "$src1 = $dst" in {
1491 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1492 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1494 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1495 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1499 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1500 let mayLoad = 0 in {
1501 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1502 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1503 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1506 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1507 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1509 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1511 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1513 let Pattern = []<dag> in {
1514 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1515 !strconcat(OpcodeStr, "ps"), f128mem,
1516 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1517 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1518 (memopv2i64 addr:$src2)))], 0>, VEX_4V;
1520 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1521 !strconcat(OpcodeStr, "pd"), f128mem,
1522 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1523 (bc_v2i64 (v2f64 VR128:$src2))))],
1524 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1525 (memopv2i64 addr:$src2)))], 0>,
1528 let Constraints = "$src1 = $dst" in {
1529 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1530 !strconcat(OpcodeStr, "ps"), f128mem,
1531 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
1532 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1533 (memopv2i64 addr:$src2)))]>, TB;
1535 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1536 !strconcat(OpcodeStr, "pd"), f128mem,
1537 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1538 (bc_v2i64 (v2f64 VR128:$src2))))],
1539 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1540 (memopv2i64 addr:$src2)))]>, TB, OpSize;
1544 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1546 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
1548 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1549 !strconcat(OpcodeStr, "ps"), f256mem,
1550 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
1551 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
1552 (memopv4i64 addr:$src2)))], 0>, VEX_4V;
1554 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1555 !strconcat(OpcodeStr, "pd"), f256mem,
1556 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1557 (bc_v4i64 (v4f64 VR256:$src2))))],
1558 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
1559 (memopv4i64 addr:$src2)))], 0>,
1563 // AVX 256-bit packed logical ops forms
1564 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
1565 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
1566 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
1567 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
1569 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1570 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1571 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1572 let isCommutable = 0 in
1573 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
1575 //===----------------------------------------------------------------------===//
1576 // SSE 1 & 2 - Arithmetic Instructions
1577 //===----------------------------------------------------------------------===//
1579 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1582 /// In addition, we also have a special variant of the scalar form here to
1583 /// represent the associated intrinsic operation. This form is unlike the
1584 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1585 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1587 /// These three forms can each be reg+reg or reg+mem.
1590 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1592 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1594 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1595 OpNode, FR32, f32mem, Is2Addr>, XS;
1596 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1597 OpNode, FR64, f64mem, Is2Addr>, XD;
1600 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1602 let mayLoad = 0 in {
1603 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1604 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1605 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1606 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1610 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1612 let mayLoad = 0 in {
1613 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1614 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1615 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1616 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1620 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1622 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1623 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1624 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1625 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1628 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1630 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1631 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1632 SSEPackedSingle, Is2Addr>, TB;
1634 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1635 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1636 SSEPackedDouble, Is2Addr>, TB, OpSize;
1639 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1640 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1641 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1642 SSEPackedSingle, 0>, TB;
1644 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1645 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1646 SSEPackedDouble, 0>, TB, OpSize;
1649 // Binary Arithmetic instructions
1650 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1651 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1652 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1653 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1654 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1655 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1656 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1657 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1659 let isCommutable = 0 in {
1660 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1661 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1662 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1663 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1664 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1665 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1666 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1667 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1668 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1669 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1670 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1671 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1672 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1673 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1674 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1675 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1676 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1677 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1678 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1679 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1682 let Constraints = "$src1 = $dst" in {
1683 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1684 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1685 basic_sse12_fp_binop_s_int<0x58, "add">;
1686 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1687 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1688 basic_sse12_fp_binop_s_int<0x59, "mul">;
1690 let isCommutable = 0 in {
1691 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1692 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1693 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1694 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1695 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1696 basic_sse12_fp_binop_s_int<0x5E, "div">;
1697 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1698 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1699 basic_sse12_fp_binop_s_int<0x5F, "max">,
1700 basic_sse12_fp_binop_p_int<0x5F, "max">;
1701 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1702 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1703 basic_sse12_fp_binop_s_int<0x5D, "min">,
1704 basic_sse12_fp_binop_p_int<0x5D, "min">;
1709 /// In addition, we also have a special variant of the scalar form here to
1710 /// represent the associated intrinsic operation. This form is unlike the
1711 /// plain scalar form, in that it takes an entire vector (instead of a
1712 /// scalar) and leaves the top elements undefined.
1714 /// And, we have a special variant form for a full-vector intrinsic form.
1716 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1717 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1718 SDNode OpNode, Intrinsic F32Int> {
1719 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1720 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1721 [(set FR32:$dst, (OpNode FR32:$src))]>;
1722 // For scalar unary operations, fold a load into the operation
1723 // only in OptForSize mode. It eliminates an instruction, but it also
1724 // eliminates a whole-register clobber (the load), so it introduces a
1725 // partial register update condition.
1726 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1727 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1728 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1729 Requires<[HasSSE1, OptForSize]>;
1730 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1731 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1732 [(set VR128:$dst, (F32Int VR128:$src))]>;
1733 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1734 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1735 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1738 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1739 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1740 SDNode OpNode, Intrinsic F32Int> {
1741 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1742 !strconcat(OpcodeStr,
1743 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1744 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1745 !strconcat(OpcodeStr,
1746 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1747 []>, XS, Requires<[HasAVX, OptForSize]>;
1748 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1749 !strconcat(OpcodeStr,
1750 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1751 [(set VR128:$dst, (F32Int VR128:$src))]>;
1752 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1753 !strconcat(OpcodeStr,
1754 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1755 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1758 /// sse1_fp_unop_p - SSE1 unops in packed form.
1759 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1760 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1761 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1762 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1763 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1764 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1765 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1768 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1769 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1770 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1771 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1772 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1773 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1774 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1775 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1778 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1779 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1780 Intrinsic V4F32Int> {
1781 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1782 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1783 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1784 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1785 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1786 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1789 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1790 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1791 Intrinsic V4F32Int> {
1792 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1793 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1794 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1795 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1796 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1797 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1800 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1801 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1802 SDNode OpNode, Intrinsic F64Int> {
1803 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1804 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1805 [(set FR64:$dst, (OpNode FR64:$src))]>;
1806 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1807 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1808 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1809 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1810 Requires<[HasSSE2, OptForSize]>;
1811 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1812 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1813 [(set VR128:$dst, (F64Int VR128:$src))]>;
1814 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1815 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1816 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1819 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1820 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1821 SDNode OpNode, Intrinsic F64Int> {
1822 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1823 !strconcat(OpcodeStr,
1824 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1825 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1826 (ins FR64:$src1, f64mem:$src2),
1827 !strconcat(OpcodeStr,
1828 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1829 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1830 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1831 [(set VR128:$dst, (F64Int VR128:$src))]>;
1832 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1833 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1834 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1837 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1838 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1840 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1841 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1842 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1843 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1844 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1845 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1848 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1849 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1850 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1851 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1852 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1853 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1854 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1855 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1858 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1859 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1860 Intrinsic V2F64Int> {
1861 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1862 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1863 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1864 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1865 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1866 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1869 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
1870 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1871 Intrinsic V2F64Int> {
1872 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1873 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1874 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1875 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1876 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1877 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1880 let Predicates = [HasAVX] in {
1882 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
1883 sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1886 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1887 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1888 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1889 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1890 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
1891 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
1892 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
1893 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
1896 // Reciprocal approximations. Note that these typically require refinement
1897 // in order to obtain suitable precision.
1898 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
1899 int_x86_sse_rsqrt_ss>, VEX_4V;
1900 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
1901 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
1902 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
1903 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
1905 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
1907 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
1908 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
1909 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
1910 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
1913 def : Pat<(f32 (fsqrt FR32:$src)),
1914 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
1915 def : Pat<(f64 (fsqrt FR64:$src)),
1916 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
1917 def : Pat<(f64 (fsqrt (load addr:$src))),
1918 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
1919 Requires<[HasAVX, OptForSize]>;
1920 def : Pat<(f32 (fsqrt (load addr:$src))),
1921 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
1922 Requires<[HasAVX, OptForSize]>;
1925 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1926 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
1927 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
1928 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1929 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
1930 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
1932 // Reciprocal approximations. Note that these typically require refinement
1933 // in order to obtain suitable precision.
1934 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
1935 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
1936 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
1937 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
1938 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
1939 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
1941 // There is no f64 version of the reciprocal approximation instructions.
1943 //===----------------------------------------------------------------------===//
1944 // SSE 1 & 2 - Non-temporal stores
1945 //===----------------------------------------------------------------------===//
1947 let AddedComplexity = 400 in { // Prefer non-temporal versions
1948 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
1949 (ins f128mem:$dst, VR128:$src),
1950 "movntps\t{$src, $dst|$dst, $src}",
1951 [(alignednontemporalstore (v4f32 VR128:$src),
1953 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
1954 (ins f128mem:$dst, VR128:$src),
1955 "movntpd\t{$src, $dst|$dst, $src}",
1956 [(alignednontemporalstore (v2f64 VR128:$src),
1958 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
1959 (ins f128mem:$dst, VR128:$src),
1960 "movntdq\t{$src, $dst|$dst, $src}",
1961 [(alignednontemporalstore (v2f64 VR128:$src),
1964 let ExeDomain = SSEPackedInt in
1965 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
1966 (ins f128mem:$dst, VR128:$src),
1967 "movntdq\t{$src, $dst|$dst, $src}",
1968 [(alignednontemporalstore (v4f32 VR128:$src),
1971 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
1972 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
1974 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
1975 (ins f256mem:$dst, VR256:$src),
1976 "movntps\t{$src, $dst|$dst, $src}",
1977 [(alignednontemporalstore (v8f32 VR256:$src),
1979 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
1980 (ins f256mem:$dst, VR256:$src),
1981 "movntpd\t{$src, $dst|$dst, $src}",
1982 [(alignednontemporalstore (v4f64 VR256:$src),
1984 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
1985 (ins f256mem:$dst, VR256:$src),
1986 "movntdq\t{$src, $dst|$dst, $src}",
1987 [(alignednontemporalstore (v4f64 VR256:$src),
1989 let ExeDomain = SSEPackedInt in
1990 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
1991 (ins f256mem:$dst, VR256:$src),
1992 "movntdq\t{$src, $dst|$dst, $src}",
1993 [(alignednontemporalstore (v8f32 VR256:$src),
1997 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
1998 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
1999 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
2000 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
2001 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
2002 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
2004 let AddedComplexity = 400 in { // Prefer non-temporal versions
2005 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2006 "movntps\t{$src, $dst|$dst, $src}",
2007 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2008 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2009 "movntpd\t{$src, $dst|$dst, $src}",
2010 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2012 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2013 "movntdq\t{$src, $dst|$dst, $src}",
2014 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2016 let ExeDomain = SSEPackedInt in
2017 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2018 "movntdq\t{$src, $dst|$dst, $src}",
2019 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2021 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
2022 (MOVNTDQmr addr:$dst, VR128:$src)>;
2024 // There is no AVX form for instructions below this point
2025 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2026 "movnti{l}\t{$src, $dst|$dst, $src}",
2027 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2028 TB, Requires<[HasSSE2]>;
2029 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2030 "movnti{q}\t{$src, $dst|$dst, $src}",
2031 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2032 TB, Requires<[HasSSE2]>;
2035 //===----------------------------------------------------------------------===//
2036 // SSE 1 & 2 - Misc Instructions (No AVX form)
2037 //===----------------------------------------------------------------------===//
2039 // Prefetch intrinsic.
2040 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2041 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
2042 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2043 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
2044 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2045 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
2046 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2047 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
2049 // Load, store, and memory fence
2050 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2051 TB, Requires<[HasSSE1]>;
2052 def : Pat<(X86SFence), (SFENCE)>;
2054 // Alias instructions that map zero vector to pxor / xorp* for sse.
2055 // We set canFoldAsLoad because this can be converted to a constant-pool
2056 // load of an all-zeros value if folding it would be beneficial.
2057 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2058 // JIT implementation, it does not expand the instructions below like
2059 // X86MCInstLower does.
2060 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2061 isCodeGenOnly = 1 in {
2062 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2063 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2064 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2065 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2066 let ExeDomain = SSEPackedInt in
2067 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2068 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2071 // The same as done above but for AVX. The 128-bit versions are the
2072 // same, but re-encoded. The 256-bit does not support PI version, and
2073 // doesn't need it because on sandy bridge the register is set to zero
2074 // at the rename stage without using any execution unit, so SET0PSY
2075 // and SET0PDY can be used for vector int instructions without penalty
2076 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2077 // JIT implementatioan, it does not expand the instructions below like
2078 // X86MCInstLower does.
2079 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2080 isCodeGenOnly = 1, Predicates = [HasAVX] in {
2081 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2082 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
2083 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2084 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
2085 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2086 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
2087 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2088 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
2089 let ExeDomain = SSEPackedInt in
2090 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2091 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2094 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2095 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2096 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2098 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2099 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2101 // AVX has no support for 256-bit integer instructions, but since the 128-bit
2102 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
2103 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
2104 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
2105 (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
2107 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
2108 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
2109 (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
2111 //===----------------------------------------------------------------------===//
2112 // SSE 1 & 2 - Load/Store XCSR register
2113 //===----------------------------------------------------------------------===//
2115 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2116 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2117 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2118 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2120 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2121 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2122 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2123 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2125 //===---------------------------------------------------------------------===//
2126 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2127 //===---------------------------------------------------------------------===//
2129 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2131 let neverHasSideEffects = 1 in {
2132 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2133 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2134 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2135 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2137 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2138 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2139 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2140 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2142 let canFoldAsLoad = 1, mayLoad = 1 in {
2143 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2144 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2145 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2146 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2147 let Predicates = [HasAVX] in {
2148 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2149 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2150 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2151 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2155 let mayStore = 1 in {
2156 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2157 (ins i128mem:$dst, VR128:$src),
2158 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2159 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2160 (ins i256mem:$dst, VR256:$src),
2161 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2162 let Predicates = [HasAVX] in {
2163 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2164 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2165 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2166 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2170 let neverHasSideEffects = 1 in
2171 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2172 "movdqa\t{$src, $dst|$dst, $src}", []>;
2174 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2175 "movdqu\t{$src, $dst|$dst, $src}",
2176 []>, XS, Requires<[HasSSE2]>;
2178 let canFoldAsLoad = 1, mayLoad = 1 in {
2179 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2180 "movdqa\t{$src, $dst|$dst, $src}",
2181 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2182 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2183 "movdqu\t{$src, $dst|$dst, $src}",
2184 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2185 XS, Requires<[HasSSE2]>;
2188 let mayStore = 1 in {
2189 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2190 "movdqa\t{$src, $dst|$dst, $src}",
2191 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2192 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2193 "movdqu\t{$src, $dst|$dst, $src}",
2194 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2195 XS, Requires<[HasSSE2]>;
2198 // Intrinsic forms of MOVDQU load and store
2199 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2200 "vmovdqu\t{$src, $dst|$dst, $src}",
2201 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2202 XS, VEX, Requires<[HasAVX]>;
2204 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2205 "movdqu\t{$src, $dst|$dst, $src}",
2206 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2207 XS, Requires<[HasSSE2]>;
2209 } // ExeDomain = SSEPackedInt
2211 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2212 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2213 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2215 //===---------------------------------------------------------------------===//
2216 // SSE2 - Packed Integer Arithmetic Instructions
2217 //===---------------------------------------------------------------------===//
2219 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2221 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2222 bit IsCommutable = 0, bit Is2Addr = 1> {
2223 let isCommutable = IsCommutable in
2224 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2225 (ins VR128:$src1, VR128:$src2),
2227 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2228 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2229 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2230 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2231 (ins VR128:$src1, i128mem:$src2),
2233 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2234 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2235 [(set VR128:$dst, (IntId VR128:$src1,
2236 (bitconvert (memopv2i64 addr:$src2))))]>;
2239 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2240 string OpcodeStr, Intrinsic IntId,
2241 Intrinsic IntId2, bit Is2Addr = 1> {
2242 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2243 (ins VR128:$src1, VR128:$src2),
2245 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2246 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2247 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2248 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2249 (ins VR128:$src1, i128mem:$src2),
2251 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2252 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2253 [(set VR128:$dst, (IntId VR128:$src1,
2254 (bitconvert (memopv2i64 addr:$src2))))]>;
2255 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2256 (ins VR128:$src1, i32i8imm:$src2),
2258 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2259 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2260 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2263 /// PDI_binop_rm - Simple SSE2 binary operator.
2264 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2265 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2266 let isCommutable = IsCommutable in
2267 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2268 (ins VR128:$src1, VR128:$src2),
2270 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2271 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2272 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2273 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2274 (ins VR128:$src1, i128mem:$src2),
2276 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2277 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2278 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2279 (bitconvert (memopv2i64 addr:$src2)))))]>;
2282 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2284 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2285 /// to collapse (bitconvert VT to VT) into its operand.
2287 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2288 bit IsCommutable = 0, bit Is2Addr = 1> {
2289 let isCommutable = IsCommutable in
2290 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2291 (ins VR128:$src1, VR128:$src2),
2293 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2294 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2295 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2296 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2297 (ins VR128:$src1, i128mem:$src2),
2299 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2300 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2301 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2304 } // ExeDomain = SSEPackedInt
2306 // 128-bit Integer Arithmetic
2308 let Predicates = [HasAVX] in {
2309 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2310 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2311 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2312 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2313 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2314 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2315 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2316 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2317 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2320 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2322 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2324 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2326 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2328 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2330 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2332 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2334 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2336 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2338 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2340 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2342 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2344 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2346 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2348 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2350 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2352 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2354 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2356 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2360 let Constraints = "$src1 = $dst" in {
2361 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2362 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2363 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2364 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2365 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2366 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2367 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2368 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2369 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2372 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2373 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2374 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2375 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2376 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2377 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2378 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2379 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2380 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2381 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2382 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2383 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2384 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2385 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2386 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2387 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2388 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2389 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2390 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2392 } // Constraints = "$src1 = $dst"
2394 //===---------------------------------------------------------------------===//
2395 // SSE2 - Packed Integer Logical Instructions
2396 //===---------------------------------------------------------------------===//
2398 let Predicates = [HasAVX] in {
2399 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2400 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2402 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2403 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2405 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2406 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2409 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2410 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2412 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2413 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2415 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2416 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2419 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2420 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2422 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2423 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2426 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2427 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2428 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2430 let ExeDomain = SSEPackedInt in {
2431 let neverHasSideEffects = 1 in {
2432 // 128-bit logical shifts.
2433 def VPSLLDQri : PDIi8<0x73, MRM7r,
2434 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2435 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2437 def VPSRLDQri : PDIi8<0x73, MRM3r,
2438 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2439 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2441 // PSRADQri doesn't exist in SSE[1-3].
2443 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2444 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2445 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2446 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2447 VR128:$src2)))]>, VEX_4V;
2449 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2450 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2451 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2452 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2453 (memopv2i64 addr:$src2))))]>,
2458 let Constraints = "$src1 = $dst" in {
2459 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2460 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2461 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2462 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2463 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2464 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2466 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2467 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2468 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2469 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2470 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2471 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2473 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2474 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2475 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2476 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2478 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2479 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2480 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2482 let ExeDomain = SSEPackedInt in {
2483 let neverHasSideEffects = 1 in {
2484 // 128-bit logical shifts.
2485 def PSLLDQri : PDIi8<0x73, MRM7r,
2486 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2487 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2488 def PSRLDQri : PDIi8<0x73, MRM3r,
2489 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2490 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2491 // PSRADQri doesn't exist in SSE[1-3].
2493 def PANDNrr : PDI<0xDF, MRMSrcReg,
2494 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2495 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2497 def PANDNrm : PDI<0xDF, MRMSrcMem,
2498 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2499 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2501 } // Constraints = "$src1 = $dst"
2503 let Predicates = [HasAVX] in {
2504 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2505 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2506 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2507 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2508 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2509 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2510 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2511 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2512 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2513 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2515 // Shift up / down and insert zero's.
2516 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2517 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2518 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2519 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2522 let Predicates = [HasSSE2] in {
2523 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2524 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2525 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2526 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2527 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2528 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2529 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2530 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2531 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2532 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2534 // Shift up / down and insert zero's.
2535 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2536 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2537 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2538 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2541 //===---------------------------------------------------------------------===//
2542 // SSE2 - Packed Integer Comparison Instructions
2543 //===---------------------------------------------------------------------===//
2545 let Predicates = [HasAVX] in {
2546 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2548 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2550 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2552 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2554 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2556 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2560 let Constraints = "$src1 = $dst" in {
2561 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2562 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2563 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2564 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2565 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2566 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2567 } // Constraints = "$src1 = $dst"
2569 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2570 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2571 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2572 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2573 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2574 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2575 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2576 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2577 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2578 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2579 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2580 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2582 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2583 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2584 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2585 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2586 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2587 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2588 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2589 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2590 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2591 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2592 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2593 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2595 //===---------------------------------------------------------------------===//
2596 // SSE2 - Packed Integer Pack Instructions
2597 //===---------------------------------------------------------------------===//
2599 let Predicates = [HasAVX] in {
2600 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2602 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2604 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2608 let Constraints = "$src1 = $dst" in {
2609 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2610 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2611 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2612 } // Constraints = "$src1 = $dst"
2614 //===---------------------------------------------------------------------===//
2615 // SSE2 - Packed Integer Shuffle Instructions
2616 //===---------------------------------------------------------------------===//
2618 let ExeDomain = SSEPackedInt in {
2619 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2621 def ri : Ii8<0x70, MRMSrcReg,
2622 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2623 !strconcat(OpcodeStr,
2624 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2625 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2627 def mi : Ii8<0x70, MRMSrcMem,
2628 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2629 !strconcat(OpcodeStr,
2630 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2631 [(set VR128:$dst, (vt (pshuf_frag:$src2
2632 (bc_frag (memopv2i64 addr:$src1)),
2635 } // ExeDomain = SSEPackedInt
2637 let Predicates = [HasAVX] in {
2638 let AddedComplexity = 5 in
2639 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2642 // SSE2 with ImmT == Imm8 and XS prefix.
2643 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2646 // SSE2 with ImmT == Imm8 and XD prefix.
2647 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2651 let Predicates = [HasSSE2] in {
2652 let AddedComplexity = 5 in
2653 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2655 // SSE2 with ImmT == Imm8 and XS prefix.
2656 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2658 // SSE2 with ImmT == Imm8 and XD prefix.
2659 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2662 //===---------------------------------------------------------------------===//
2663 // SSE2 - Packed Integer Unpack Instructions
2664 //===---------------------------------------------------------------------===//
2666 let ExeDomain = SSEPackedInt in {
2667 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2668 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
2669 def rr : PDI<opc, MRMSrcReg,
2670 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2672 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2673 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2674 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
2675 def rm : PDI<opc, MRMSrcMem,
2676 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2678 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2679 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2680 [(set VR128:$dst, (OpNode VR128:$src1,
2681 (bc_frag (memopv2i64
2685 let Predicates = [HasAVX] in {
2686 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
2687 bc_v16i8, 0>, VEX_4V;
2688 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
2689 bc_v8i16, 0>, VEX_4V;
2690 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
2691 bc_v4i32, 0>, VEX_4V;
2693 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2694 /// knew to collapse (bitconvert VT to VT) into its operand.
2695 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2696 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2697 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2698 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
2699 VR128:$src2)))]>, VEX_4V;
2700 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2701 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2702 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2703 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
2704 (memopv2i64 addr:$src2))))]>, VEX_4V;
2706 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
2707 bc_v16i8, 0>, VEX_4V;
2708 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
2709 bc_v8i16, 0>, VEX_4V;
2710 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
2711 bc_v4i32, 0>, VEX_4V;
2713 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2714 /// knew to collapse (bitconvert VT to VT) into its operand.
2715 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2716 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2717 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2718 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
2719 VR128:$src2)))]>, VEX_4V;
2720 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2721 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2722 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2723 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
2724 (memopv2i64 addr:$src2))))]>, VEX_4V;
2727 let Constraints = "$src1 = $dst" in {
2728 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
2729 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
2730 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
2732 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2733 /// knew to collapse (bitconvert VT to VT) into its operand.
2734 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2735 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2736 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2738 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
2739 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2740 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2741 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2743 (v2i64 (X86Punpcklqdq VR128:$src1,
2744 (memopv2i64 addr:$src2))))]>;
2746 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
2747 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
2748 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
2750 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2751 /// knew to collapse (bitconvert VT to VT) into its operand.
2752 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2753 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2754 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2756 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
2757 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2758 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2759 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2761 (v2i64 (X86Punpckhqdq VR128:$src1,
2762 (memopv2i64 addr:$src2))))]>;
2765 } // ExeDomain = SSEPackedInt
2767 //===---------------------------------------------------------------------===//
2768 // SSE2 - Packed Integer Extract and Insert
2769 //===---------------------------------------------------------------------===//
2771 let ExeDomain = SSEPackedInt in {
2772 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2773 def rri : Ii8<0xC4, MRMSrcReg,
2774 (outs VR128:$dst), (ins VR128:$src1,
2775 GR32:$src2, i32i8imm:$src3),
2777 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2778 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2780 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2781 def rmi : Ii8<0xC4, MRMSrcMem,
2782 (outs VR128:$dst), (ins VR128:$src1,
2783 i16mem:$src2, i32i8imm:$src3),
2785 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2786 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2788 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2793 let Predicates = [HasAVX] in
2794 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2795 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2796 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2797 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2798 imm:$src2))]>, OpSize, VEX;
2799 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2800 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2801 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2802 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2806 let Predicates = [HasAVX] in {
2807 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2808 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2809 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2810 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2811 []>, OpSize, VEX_4V;
2814 let Constraints = "$src1 = $dst" in
2815 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
2817 } // ExeDomain = SSEPackedInt
2819 //===---------------------------------------------------------------------===//
2820 // SSE2 - Packed Mask Creation
2821 //===---------------------------------------------------------------------===//
2823 let ExeDomain = SSEPackedInt in {
2825 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2826 "pmovmskb\t{$src, $dst|$dst, $src}",
2827 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2828 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2829 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2830 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2831 "pmovmskb\t{$src, $dst|$dst, $src}",
2832 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2834 } // ExeDomain = SSEPackedInt
2836 //===---------------------------------------------------------------------===//
2837 // SSE2 - Conditional Store
2838 //===---------------------------------------------------------------------===//
2840 let ExeDomain = SSEPackedInt in {
2843 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2844 (ins VR128:$src, VR128:$mask),
2845 "maskmovdqu\t{$mask, $src|$src, $mask}",
2846 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2848 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2849 (ins VR128:$src, VR128:$mask),
2850 "maskmovdqu\t{$mask, $src|$src, $mask}",
2851 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2854 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2855 "maskmovdqu\t{$mask, $src|$src, $mask}",
2856 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2858 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2859 "maskmovdqu\t{$mask, $src|$src, $mask}",
2860 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2862 } // ExeDomain = SSEPackedInt
2864 //===---------------------------------------------------------------------===//
2865 // SSE2 - Move Doubleword
2866 //===---------------------------------------------------------------------===//
2868 //===---------------------------------------------------------------------===//
2869 // Move Int Doubleword to Packed Double Int
2871 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2872 "movd\t{$src, $dst|$dst, $src}",
2874 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2875 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2876 "movd\t{$src, $dst|$dst, $src}",
2878 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2880 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2881 "mov{d|q}\t{$src, $dst|$dst, $src}",
2883 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
2884 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2885 "mov{d|q}\t{$src, $dst|$dst, $src}",
2886 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
2888 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2889 "movd\t{$src, $dst|$dst, $src}",
2891 (v4i32 (scalar_to_vector GR32:$src)))]>;
2892 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2893 "movd\t{$src, $dst|$dst, $src}",
2895 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2896 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2897 "mov{d|q}\t{$src, $dst|$dst, $src}",
2899 (v2i64 (scalar_to_vector GR64:$src)))]>;
2900 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2901 "mov{d|q}\t{$src, $dst|$dst, $src}",
2902 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2904 //===---------------------------------------------------------------------===//
2905 // Move Int Doubleword to Single Scalar
2907 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2908 "movd\t{$src, $dst|$dst, $src}",
2909 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2911 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2912 "movd\t{$src, $dst|$dst, $src}",
2913 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2915 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2916 "movd\t{$src, $dst|$dst, $src}",
2917 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2919 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2920 "movd\t{$src, $dst|$dst, $src}",
2921 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2923 //===---------------------------------------------------------------------===//
2924 // Move Packed Doubleword Int to Packed Double Int
2926 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2927 "movd\t{$src, $dst|$dst, $src}",
2928 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2930 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
2931 (ins i32mem:$dst, VR128:$src),
2932 "movd\t{$src, $dst|$dst, $src}",
2933 [(store (i32 (vector_extract (v4i32 VR128:$src),
2934 (iPTR 0))), addr:$dst)]>, VEX;
2935 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2936 "movd\t{$src, $dst|$dst, $src}",
2937 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2939 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2940 "movd\t{$src, $dst|$dst, $src}",
2941 [(store (i32 (vector_extract (v4i32 VR128:$src),
2942 (iPTR 0))), addr:$dst)]>;
2944 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2945 "mov{d|q}\t{$src, $dst|$dst, $src}",
2946 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2948 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2949 "movq\t{$src, $dst|$dst, $src}",
2950 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2952 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2953 "mov{d|q}\t{$src, $dst|$dst, $src}",
2954 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2955 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2956 "movq\t{$src, $dst|$dst, $src}",
2957 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2959 //===---------------------------------------------------------------------===//
2960 // Move Scalar Single to Double Int
2962 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2963 "movd\t{$src, $dst|$dst, $src}",
2964 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
2965 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2966 "movd\t{$src, $dst|$dst, $src}",
2967 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
2968 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2969 "movd\t{$src, $dst|$dst, $src}",
2970 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2971 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2972 "movd\t{$src, $dst|$dst, $src}",
2973 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2975 //===---------------------------------------------------------------------===//
2976 // Patterns and instructions to describe movd/movq to XMM register zero-extends
2978 let AddedComplexity = 15 in {
2979 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2980 "movd\t{$src, $dst|$dst, $src}",
2981 [(set VR128:$dst, (v4i32 (X86vzmovl
2982 (v4i32 (scalar_to_vector GR32:$src)))))]>,
2984 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2985 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2986 [(set VR128:$dst, (v2i64 (X86vzmovl
2987 (v2i64 (scalar_to_vector GR64:$src)))))]>,
2990 let AddedComplexity = 15 in {
2991 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2992 "movd\t{$src, $dst|$dst, $src}",
2993 [(set VR128:$dst, (v4i32 (X86vzmovl
2994 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2995 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2996 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2997 [(set VR128:$dst, (v2i64 (X86vzmovl
2998 (v2i64 (scalar_to_vector GR64:$src)))))]>;
3001 let AddedComplexity = 20 in {
3002 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3003 "movd\t{$src, $dst|$dst, $src}",
3005 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3006 (loadi32 addr:$src))))))]>,
3008 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3009 "movd\t{$src, $dst|$dst, $src}",
3011 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3012 (loadi32 addr:$src))))))]>;
3014 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
3015 (MOVZDI2PDIrm addr:$src)>;
3016 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3017 (MOVZDI2PDIrm addr:$src)>;
3018 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3019 (MOVZDI2PDIrm addr:$src)>;
3022 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
3023 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
3024 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
3025 (v4i32 (scalar_to_vector GR32:$src)), (i32 0)))),
3026 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
3027 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
3028 (v2i64 (scalar_to_vector GR64:$src)), (i32 0)))),
3029 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
3031 // These are the correct encodings of the instructions so that we know how to
3032 // read correct assembly, even though we continue to emit the wrong ones for
3033 // compatibility with Darwin's buggy assembler.
3034 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3035 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
3036 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3037 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
3038 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3039 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
3040 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3041 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
3042 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3043 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3044 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
3045 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
3047 //===---------------------------------------------------------------------===//
3048 // SSE2 - Move Quadword
3049 //===---------------------------------------------------------------------===//
3051 //===---------------------------------------------------------------------===//
3052 // Move Quadword Int to Packed Quadword Int
3054 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3055 "vmovq\t{$src, $dst|$dst, $src}",
3057 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3058 VEX, Requires<[HasAVX]>;
3059 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3060 "movq\t{$src, $dst|$dst, $src}",
3062 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3063 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3065 //===---------------------------------------------------------------------===//
3066 // Move Packed Quadword Int to Quadword Int
3068 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3069 "movq\t{$src, $dst|$dst, $src}",
3070 [(store (i64 (vector_extract (v2i64 VR128:$src),
3071 (iPTR 0))), addr:$dst)]>, VEX;
3072 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3073 "movq\t{$src, $dst|$dst, $src}",
3074 [(store (i64 (vector_extract (v2i64 VR128:$src),
3075 (iPTR 0))), addr:$dst)]>;
3077 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3078 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3080 //===---------------------------------------------------------------------===//
3081 // Store / copy lower 64-bits of a XMM register.
3083 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3084 "movq\t{$src, $dst|$dst, $src}",
3085 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3086 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3087 "movq\t{$src, $dst|$dst, $src}",
3088 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3090 let AddedComplexity = 20 in
3091 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3092 "vmovq\t{$src, $dst|$dst, $src}",
3094 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3095 (loadi64 addr:$src))))))]>,
3096 XS, VEX, Requires<[HasAVX]>;
3098 let AddedComplexity = 20 in {
3099 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3100 "movq\t{$src, $dst|$dst, $src}",
3102 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3103 (loadi64 addr:$src))))))]>,
3104 XS, Requires<[HasSSE2]>;
3106 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3107 (MOVZQI2PQIrm addr:$src)>;
3108 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3109 (MOVZQI2PQIrm addr:$src)>;
3110 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3113 //===---------------------------------------------------------------------===//
3114 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3115 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3117 let AddedComplexity = 15 in
3118 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3119 "vmovq\t{$src, $dst|$dst, $src}",
3120 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3121 XS, VEX, Requires<[HasAVX]>;
3122 let AddedComplexity = 15 in
3123 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3124 "movq\t{$src, $dst|$dst, $src}",
3125 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3126 XS, Requires<[HasSSE2]>;
3128 let AddedComplexity = 20 in
3129 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3130 "vmovq\t{$src, $dst|$dst, $src}",
3131 [(set VR128:$dst, (v2i64 (X86vzmovl
3132 (loadv2i64 addr:$src))))]>,
3133 XS, VEX, Requires<[HasAVX]>;
3134 let AddedComplexity = 20 in {
3135 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3136 "movq\t{$src, $dst|$dst, $src}",
3137 [(set VR128:$dst, (v2i64 (X86vzmovl
3138 (loadv2i64 addr:$src))))]>,
3139 XS, Requires<[HasSSE2]>;
3141 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3142 (MOVZPQILo2PQIrm addr:$src)>;
3145 // Instructions to match in the assembler
3146 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3147 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3148 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3149 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3150 // Recognize "movd" with GR64 destination, but encode as a "movq"
3151 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3152 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3154 // Instructions for the disassembler
3155 // xr = XMM register
3158 let Predicates = [HasAVX] in
3159 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3160 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3161 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3162 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3164 //===---------------------------------------------------------------------===//
3165 // SSE2 - Misc Instructions
3166 //===---------------------------------------------------------------------===//
3169 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3170 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3171 TB, Requires<[HasSSE2]>;
3173 // Load, store, and memory fence
3174 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3175 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3176 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3177 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3178 def : Pat<(X86LFence), (LFENCE)>;
3179 def : Pat<(X86MFence), (MFENCE)>;
3182 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3183 // was introduced with SSE2, it's backward compatible.
3184 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3186 // Alias instructions that map zero vector to pxor / xorp* for sse.
3187 // We set canFoldAsLoad because this can be converted to a constant-pool
3188 // load of an all-ones value if folding it would be beneficial.
3189 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
3190 // JIT implementation, it does not expand the instructions below like
3191 // X86MCInstLower does.
3192 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3193 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3194 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3195 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3196 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3197 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
3198 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3199 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
3201 //===---------------------------------------------------------------------===//
3202 // SSE3 - Conversion Instructions
3203 //===---------------------------------------------------------------------===//
3205 // Convert Packed Double FP to Packed DW Integers
3206 let Predicates = [HasAVX] in {
3207 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3208 // register, but the same isn't true when using memory operands instead.
3209 // Provide other assembly rr and rm forms to address this explicitly.
3210 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3211 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3212 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3213 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3216 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3217 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3218 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3219 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3222 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3223 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3224 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3225 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3228 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3229 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3230 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3231 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3233 // Convert Packed DW Integers to Packed Double FP
3234 let Predicates = [HasAVX] in {
3235 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3236 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3237 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3238 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3239 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3240 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3241 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3242 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3245 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3246 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3247 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3248 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3250 // AVX 256-bit register conversion intrinsics
3251 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3252 (VCVTDQ2PDYrr VR128:$src)>;
3253 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3254 (VCVTDQ2PDYrm addr:$src)>;
3256 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3257 (VCVTPD2DQYrr VR256:$src)>;
3258 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3259 (VCVTPD2DQYrm addr:$src)>;
3261 //===---------------------------------------------------------------------===//
3262 // SSE3 - Move Instructions
3263 //===---------------------------------------------------------------------===//
3265 //===---------------------------------------------------------------------===//
3266 // Replicate Single FP - MOVSHDUP and MOVSLDUP
3268 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3269 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3270 X86MemOperand x86memop> {
3271 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3272 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3273 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
3274 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
3275 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3276 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
3279 let Predicates = [HasAVX] in {
3280 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3281 v4f32, VR128, memopv4f32, f128mem>, VEX;
3282 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3283 v4f32, VR128, memopv4f32, f128mem>, VEX;
3284 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3285 v8f32, VR256, memopv8f32, f256mem>, VEX;
3286 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3287 v8f32, VR256, memopv8f32, f256mem>, VEX;
3289 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
3290 memopv4f32, f128mem>;
3291 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
3292 memopv4f32, f128mem>;
3294 let Predicates = [HasSSE3] in {
3295 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3296 (MOVSHDUPrr VR128:$src)>;
3297 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3298 (MOVSHDUPrm addr:$src)>;
3299 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3300 (MOVSLDUPrr VR128:$src)>;
3301 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3302 (MOVSLDUPrm addr:$src)>;
3305 let Predicates = [HasAVX] in {
3306 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
3307 (VMOVSHDUPrr VR128:$src)>;
3308 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
3309 (VMOVSHDUPrm addr:$src)>;
3310 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
3311 (VMOVSLDUPrr VR128:$src)>;
3312 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
3313 (VMOVSLDUPrm addr:$src)>;
3314 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
3315 (VMOVSHDUPYrr VR256:$src)>;
3316 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
3317 (VMOVSHDUPYrm addr:$src)>;
3318 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
3319 (VMOVSLDUPYrr VR256:$src)>;
3320 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
3321 (VMOVSLDUPYrm addr:$src)>;
3324 //===---------------------------------------------------------------------===//
3325 // Replicate Double FP - MOVDDUP
3327 multiclass sse3_replicate_dfp<string OpcodeStr> {
3328 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3329 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3330 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3331 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3332 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3334 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3338 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3339 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3340 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3342 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3343 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3347 let Predicates = [HasAVX] in {
3348 // FIXME: Merge above classes when we have patterns for the ymm version
3349 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3350 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3352 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3354 // Move Unaligned Integer
3355 let Predicates = [HasAVX] in {
3356 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3357 "vlddqu\t{$src, $dst|$dst, $src}",
3358 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3359 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3360 "vlddqu\t{$src, $dst|$dst, $src}",
3361 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
3363 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3364 "lddqu\t{$src, $dst|$dst, $src}",
3365 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3367 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3369 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3371 // Several Move patterns
3372 let AddedComplexity = 5 in {
3373 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3374 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3375 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3376 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3377 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3378 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3379 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3380 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3383 //===---------------------------------------------------------------------===//
3384 // SSE3 - Arithmetic
3385 //===---------------------------------------------------------------------===//
3387 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3388 X86MemOperand x86memop, bit Is2Addr = 1> {
3389 def rr : I<0xD0, MRMSrcReg,
3390 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3392 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3393 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3394 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3395 def rm : I<0xD0, MRMSrcMem,
3396 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3398 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3399 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3400 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3403 let Predicates = [HasAVX],
3404 ExeDomain = SSEPackedDouble in {
3405 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3406 f128mem, 0>, TB, XD, VEX_4V;
3407 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3408 f128mem, 0>, TB, OpSize, VEX_4V;
3409 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3410 f256mem, 0>, TB, XD, VEX_4V;
3411 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3412 f256mem, 0>, TB, OpSize, VEX_4V;
3414 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3415 ExeDomain = SSEPackedDouble in {
3416 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3418 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3419 f128mem>, TB, OpSize;
3422 //===---------------------------------------------------------------------===//
3423 // SSE3 Instructions
3424 //===---------------------------------------------------------------------===//
3427 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3428 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3429 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3431 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3432 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3433 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3435 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3437 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3438 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3439 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3441 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3442 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3443 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3445 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3446 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3447 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3449 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3451 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3452 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3453 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3456 let Predicates = [HasAVX] in {
3457 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3458 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3459 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3460 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3461 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3462 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3463 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3464 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3465 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3466 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3467 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3468 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3469 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3470 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3471 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3472 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3475 let Constraints = "$src1 = $dst" in {
3476 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3477 int_x86_sse3_hadd_ps>;
3478 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3479 int_x86_sse3_hadd_pd>;
3480 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3481 int_x86_sse3_hsub_ps>;
3482 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3483 int_x86_sse3_hsub_pd>;
3486 //===---------------------------------------------------------------------===//
3487 // SSSE3 - Packed Absolute Instructions
3488 //===---------------------------------------------------------------------===//
3491 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3492 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3493 PatFrag mem_frag128, Intrinsic IntId128> {
3494 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3496 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3497 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3500 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3502 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3505 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3508 let Predicates = [HasAVX] in {
3509 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
3510 int_x86_ssse3_pabs_b_128>, VEX;
3511 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
3512 int_x86_ssse3_pabs_w_128>, VEX;
3513 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
3514 int_x86_ssse3_pabs_d_128>, VEX;
3517 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
3518 int_x86_ssse3_pabs_b_128>;
3519 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
3520 int_x86_ssse3_pabs_w_128>;
3521 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
3522 int_x86_ssse3_pabs_d_128>;
3524 //===---------------------------------------------------------------------===//
3525 // SSSE3 - Packed Binary Operator Instructions
3526 //===---------------------------------------------------------------------===//
3528 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3529 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3530 PatFrag mem_frag128, Intrinsic IntId128,
3532 let isCommutable = 1 in
3533 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3534 (ins VR128:$src1, VR128:$src2),
3536 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3537 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3538 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3540 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3541 (ins VR128:$src1, i128mem:$src2),
3543 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3544 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3546 (IntId128 VR128:$src1,
3547 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3550 let Predicates = [HasAVX] in {
3551 let isCommutable = 0 in {
3552 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
3553 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3554 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
3555 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3556 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
3557 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3558 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
3559 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3560 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
3561 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3562 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
3563 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3564 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
3565 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3566 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
3567 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3568 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
3569 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3570 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
3571 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3572 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
3573 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3575 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
3576 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3579 // None of these have i8 immediate fields.
3580 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3581 let isCommutable = 0 in {
3582 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
3583 int_x86_ssse3_phadd_w_128>;
3584 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
3585 int_x86_ssse3_phadd_d_128>;
3586 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
3587 int_x86_ssse3_phadd_sw_128>;
3588 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
3589 int_x86_ssse3_phsub_w_128>;
3590 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
3591 int_x86_ssse3_phsub_d_128>;
3592 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
3593 int_x86_ssse3_phsub_sw_128>;
3594 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
3595 int_x86_ssse3_pmadd_ub_sw_128>;
3596 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
3597 int_x86_ssse3_pshuf_b_128>;
3598 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
3599 int_x86_ssse3_psign_b_128>;
3600 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
3601 int_x86_ssse3_psign_w_128>;
3602 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
3603 int_x86_ssse3_psign_d_128>;
3605 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
3606 int_x86_ssse3_pmul_hr_sw_128>;
3609 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3610 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3611 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3612 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3614 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
3615 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3616 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
3617 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3618 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
3619 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3621 //===---------------------------------------------------------------------===//
3622 // SSSE3 - Packed Align Instruction Patterns
3623 //===---------------------------------------------------------------------===//
3625 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
3626 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3627 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3629 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3631 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3633 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3634 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3636 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3638 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3642 let Predicates = [HasAVX] in
3643 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
3644 let Constraints = "$src1 = $dst" in
3645 defm PALIGN : ssse3_palign<"palignr">;
3647 let AddedComplexity = 5 in {
3648 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3649 (PALIGNR128rr VR128:$src2, VR128:$src1,
3650 (SHUFFLE_get_palign_imm VR128:$src3))>,
3651 Requires<[HasSSSE3]>;
3652 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3653 (PALIGNR128rr VR128:$src2, VR128:$src1,
3654 (SHUFFLE_get_palign_imm VR128:$src3))>,
3655 Requires<[HasSSSE3]>;
3656 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3657 (PALIGNR128rr VR128:$src2, VR128:$src1,
3658 (SHUFFLE_get_palign_imm VR128:$src3))>,
3659 Requires<[HasSSSE3]>;
3660 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3661 (PALIGNR128rr VR128:$src2, VR128:$src1,
3662 (SHUFFLE_get_palign_imm VR128:$src3))>,
3663 Requires<[HasSSSE3]>;
3666 //===---------------------------------------------------------------------===//
3667 // SSSE3 Misc Instructions
3668 //===---------------------------------------------------------------------===//
3670 // Thread synchronization
3671 let usesCustomInserter = 1 in {
3672 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
3673 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
3674 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
3675 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
3678 let Uses = [EAX, ECX, EDX] in
3679 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
3680 Requires<[HasSSE3]>;
3681 let Uses = [ECX, EAX] in
3682 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
3683 Requires<[HasSSE3]>;
3685 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
3686 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
3688 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
3689 Requires<[In32BitMode]>;
3690 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
3691 Requires<[In64BitMode]>;
3693 //===---------------------------------------------------------------------===//
3694 // Non-Instruction Patterns
3695 //===---------------------------------------------------------------------===//
3697 // extload f32 -> f64. This matches load+fextend because we have a hack in
3698 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3700 // Since these loads aren't folded into the fextend, we have to match it
3702 let Predicates = [HasSSE2] in
3703 def : Pat<(fextend (loadf32 addr:$src)),
3704 (CVTSS2SDrm addr:$src)>;
3706 // Bitcasts between 128-bit vector types. Return the original type since
3707 // no instruction is needed for the conversion
3708 let Predicates = [HasXMMInt] in {
3709 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3710 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3711 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3712 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3713 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3714 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3715 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3716 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3717 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3718 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3719 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3720 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3721 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3722 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3723 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3724 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3725 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3726 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3727 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3728 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3729 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3730 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3731 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3732 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3733 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3734 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3735 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3736 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3737 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3738 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3741 // Bitcasts between 256-bit vector types. Return the original type since
3742 // no instruction is needed for the conversion
3743 let Predicates = [HasAVX] in {
3744 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
3745 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
3746 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
3747 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
3748 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
3749 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
3750 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
3751 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
3752 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
3753 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
3754 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
3755 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
3756 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
3757 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
3758 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
3759 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
3760 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
3761 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
3762 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
3763 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
3764 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
3765 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
3766 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
3767 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
3768 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
3769 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
3770 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
3771 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
3772 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
3773 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
3776 // Move scalar to XMM zero-extended
3777 // movd to XMM register zero-extends
3778 let AddedComplexity = 15 in {
3779 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3780 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3781 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3782 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3783 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3784 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3785 (MOVSSrr (v4f32 (V_SET0PS)),
3786 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3787 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3788 (MOVSSrr (v4i32 (V_SET0PI)),
3789 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3792 // Splat v2f64 / v2i64
3793 let AddedComplexity = 10 in {
3794 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3795 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3796 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3797 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3800 // Special unary SHUFPSrri case.
3801 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3802 (SHUFPSrri VR128:$src1, VR128:$src1,
3803 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3804 let AddedComplexity = 5 in
3805 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3806 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3807 Requires<[HasSSE2]>;
3808 // Special unary SHUFPDrri case.
3809 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3810 (SHUFPDrri VR128:$src1, VR128:$src1,
3811 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3812 Requires<[HasSSE2]>;
3813 // Special unary SHUFPDrri case.
3814 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3815 (SHUFPDrri VR128:$src1, VR128:$src1,
3816 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3817 Requires<[HasSSE2]>;
3818 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3819 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3820 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3821 Requires<[HasSSE2]>;
3823 // Special binary v4i32 shuffle cases with SHUFPS.
3824 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3825 (SHUFPSrri VR128:$src1, VR128:$src2,
3826 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3827 Requires<[HasSSE2]>;
3828 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3829 (SHUFPSrmi VR128:$src1, addr:$src2,
3830 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3831 Requires<[HasSSE2]>;
3832 // Special binary v2i64 shuffle cases using SHUFPDrri.
3833 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3834 (SHUFPDrri VR128:$src1, VR128:$src2,
3835 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3836 Requires<[HasSSE2]>;
3838 let AddedComplexity = 20 in {
3839 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3840 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3841 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3843 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3844 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3845 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3847 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3848 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3849 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3850 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3851 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3854 let AddedComplexity = 20 in {
3855 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3856 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3857 (MOVLPSrm VR128:$src1, addr:$src2)>;
3858 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3859 (MOVLPDrm VR128:$src1, addr:$src2)>;
3860 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3861 (MOVLPSrm VR128:$src1, addr:$src2)>;
3862 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3863 (MOVLPDrm VR128:$src1, addr:$src2)>;
3866 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3867 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3868 (MOVLPSmr addr:$src1, VR128:$src2)>;
3869 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3870 (MOVLPDmr addr:$src1, VR128:$src2)>;
3871 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3873 (MOVLPSmr addr:$src1, VR128:$src2)>;
3874 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3875 (MOVLPDmr addr:$src1, VR128:$src2)>;
3877 let AddedComplexity = 15 in {
3878 // Setting the lowest element in the vector.
3879 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3880 (MOVSSrr (v4i32 VR128:$src1),
3881 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3882 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3883 (MOVSDrr (v2i64 VR128:$src1),
3884 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3886 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3887 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3888 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3889 Requires<[HasSSE2]>;
3890 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3891 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3892 Requires<[HasSSE2]>;
3895 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3896 // fall back to this for SSE1)
3897 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3898 (SHUFPSrri VR128:$src2, VR128:$src1,
3899 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3901 // Set lowest element and zero upper elements.
3902 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3903 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3905 // Use movaps / movups for SSE integer load / store (one byte shorter).
3906 // The instructions selected below are then converted to MOVDQA/MOVDQU
3907 // during the SSE domain pass.
3908 let Predicates = [HasSSE1] in {
3909 def : Pat<(alignedloadv4i32 addr:$src),
3910 (MOVAPSrm addr:$src)>;
3911 def : Pat<(loadv4i32 addr:$src),
3912 (MOVUPSrm addr:$src)>;
3913 def : Pat<(alignedloadv2i64 addr:$src),
3914 (MOVAPSrm addr:$src)>;
3915 def : Pat<(loadv2i64 addr:$src),
3916 (MOVUPSrm addr:$src)>;
3918 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3919 (MOVAPSmr addr:$dst, VR128:$src)>;
3920 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3921 (MOVAPSmr addr:$dst, VR128:$src)>;
3922 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3923 (MOVAPSmr addr:$dst, VR128:$src)>;
3924 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3925 (MOVAPSmr addr:$dst, VR128:$src)>;
3926 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3927 (MOVUPSmr addr:$dst, VR128:$src)>;
3928 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3929 (MOVUPSmr addr:$dst, VR128:$src)>;
3930 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3931 (MOVUPSmr addr:$dst, VR128:$src)>;
3932 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3933 (MOVUPSmr addr:$dst, VR128:$src)>;
3936 // Use vmovaps/vmovups for AVX integer load/store.
3937 let Predicates = [HasAVX] in {
3938 // 128-bit load/store
3939 def : Pat<(alignedloadv4i32 addr:$src),
3940 (VMOVAPSrm addr:$src)>;
3941 def : Pat<(loadv4i32 addr:$src),
3942 (VMOVUPSrm addr:$src)>;
3943 def : Pat<(alignedloadv2i64 addr:$src),
3944 (VMOVAPSrm addr:$src)>;
3945 def : Pat<(loadv2i64 addr:$src),
3946 (VMOVUPSrm addr:$src)>;
3948 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3949 (VMOVAPSmr addr:$dst, VR128:$src)>;
3950 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3951 (VMOVAPSmr addr:$dst, VR128:$src)>;
3952 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3953 (VMOVAPSmr addr:$dst, VR128:$src)>;
3954 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3955 (VMOVAPSmr addr:$dst, VR128:$src)>;
3956 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3957 (VMOVUPSmr addr:$dst, VR128:$src)>;
3958 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3959 (VMOVUPSmr addr:$dst, VR128:$src)>;
3960 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3961 (VMOVUPSmr addr:$dst, VR128:$src)>;
3962 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3963 (VMOVUPSmr addr:$dst, VR128:$src)>;
3965 // 256-bit load/store
3966 def : Pat<(alignedloadv4i64 addr:$src),
3967 (VMOVAPSYrm addr:$src)>;
3968 def : Pat<(loadv4i64 addr:$src),
3969 (VMOVUPSYrm addr:$src)>;
3970 def : Pat<(alignedloadv8i32 addr:$src),
3971 (VMOVAPSYrm addr:$src)>;
3972 def : Pat<(loadv8i32 addr:$src),
3973 (VMOVUPSYrm addr:$src)>;
3974 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
3975 (VMOVAPSYmr addr:$dst, VR256:$src)>;
3976 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
3977 (VMOVAPSYmr addr:$dst, VR256:$src)>;
3978 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
3979 (VMOVUPSYmr addr:$dst, VR256:$src)>;
3980 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
3981 (VMOVUPSYmr addr:$dst, VR256:$src)>;
3984 //===----------------------------------------------------------------------===//
3985 // SSE4.1 - Packed Move with Sign/Zero Extend
3986 //===----------------------------------------------------------------------===//
3988 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3989 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3990 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3991 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3993 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3994 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3996 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
4000 let Predicates = [HasAVX] in {
4001 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
4003 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
4005 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
4007 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
4009 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
4011 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
4015 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4016 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4017 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4018 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4019 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4020 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4022 // Common patterns involving scalar load.
4023 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4024 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4025 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4026 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4028 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4029 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4030 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4031 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4033 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4034 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4035 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4036 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4038 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4039 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4040 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4041 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4043 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4044 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4045 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4046 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4048 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4049 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4050 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4051 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4054 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4055 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4056 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4057 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4059 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4060 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4062 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4066 let Predicates = [HasAVX] in {
4067 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
4069 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
4071 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
4073 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
4077 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4078 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4079 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4080 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4082 // Common patterns involving scalar load
4083 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4084 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4085 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4086 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4088 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4089 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4090 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4091 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4094 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4095 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4096 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4097 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4099 // Expecting a i16 load any extended to i32 value.
4100 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4101 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4102 [(set VR128:$dst, (IntId (bitconvert
4103 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4107 let Predicates = [HasAVX] in {
4108 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4110 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4113 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4114 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4116 // Common patterns involving scalar load
4117 def : Pat<(int_x86_sse41_pmovsxbq
4118 (bitconvert (v4i32 (X86vzmovl
4119 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4120 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4122 def : Pat<(int_x86_sse41_pmovzxbq
4123 (bitconvert (v4i32 (X86vzmovl
4124 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4125 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4127 //===----------------------------------------------------------------------===//
4128 // SSE4.1 - Extract Instructions
4129 //===----------------------------------------------------------------------===//
4131 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4132 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4133 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4134 (ins VR128:$src1, i32i8imm:$src2),
4135 !strconcat(OpcodeStr,
4136 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4137 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4139 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4140 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4141 !strconcat(OpcodeStr,
4142 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4145 // There's an AssertZext in the way of writing the store pattern
4146 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4149 let Predicates = [HasAVX] in {
4150 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4151 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4152 (ins VR128:$src1, i32i8imm:$src2),
4153 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4156 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4159 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4160 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4161 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4162 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4163 !strconcat(OpcodeStr,
4164 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4167 // There's an AssertZext in the way of writing the store pattern
4168 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4171 let Predicates = [HasAVX] in
4172 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4174 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4177 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4178 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4179 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4180 (ins VR128:$src1, i32i8imm:$src2),
4181 !strconcat(OpcodeStr,
4182 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4184 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4185 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4186 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4187 !strconcat(OpcodeStr,
4188 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4189 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4190 addr:$dst)]>, OpSize;
4193 let Predicates = [HasAVX] in
4194 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4196 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4198 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4199 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4200 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4201 (ins VR128:$src1, i32i8imm:$src2),
4202 !strconcat(OpcodeStr,
4203 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4205 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4206 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4207 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4208 !strconcat(OpcodeStr,
4209 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4210 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4211 addr:$dst)]>, OpSize, REX_W;
4214 let Predicates = [HasAVX] in
4215 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4217 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4219 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4221 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4222 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4223 (ins VR128:$src1, i32i8imm:$src2),
4224 !strconcat(OpcodeStr,
4225 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4227 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4229 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4230 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4231 !strconcat(OpcodeStr,
4232 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4233 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4234 addr:$dst)]>, OpSize;
4237 let Predicates = [HasAVX] in {
4238 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4239 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4240 (ins VR128:$src1, i32i8imm:$src2),
4241 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4244 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4246 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4247 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4250 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4251 Requires<[HasSSE41]>;
4253 //===----------------------------------------------------------------------===//
4254 // SSE4.1 - Insert Instructions
4255 //===----------------------------------------------------------------------===//
4257 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4258 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4259 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4261 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4263 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4265 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4266 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4267 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4269 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4271 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4273 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4274 imm:$src3))]>, OpSize;
4277 let Predicates = [HasAVX] in
4278 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4279 let Constraints = "$src1 = $dst" in
4280 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4282 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4283 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4284 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4286 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4288 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4290 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4292 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4293 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4295 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4297 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4299 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4300 imm:$src3)))]>, OpSize;
4303 let Predicates = [HasAVX] in
4304 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4305 let Constraints = "$src1 = $dst" in
4306 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4308 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4309 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4310 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4312 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4314 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4316 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4318 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4319 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4321 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4323 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4325 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4326 imm:$src3)))]>, OpSize;
4329 let Predicates = [HasAVX] in
4330 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4331 let Constraints = "$src1 = $dst" in
4332 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4334 // insertps has a few different modes, there's the first two here below which
4335 // are optimized inserts that won't zero arbitrary elements in the destination
4336 // vector. The next one matches the intrinsic and could zero arbitrary elements
4337 // in the target vector.
4338 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4339 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4340 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
4342 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4344 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4346 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4348 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4349 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
4351 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4353 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4355 (X86insrtps VR128:$src1,
4356 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4357 imm:$src3))]>, OpSize;
4360 let Constraints = "$src1 = $dst" in
4361 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4362 let Predicates = [HasAVX] in
4363 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4365 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4366 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4368 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4369 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4370 Requires<[HasSSE41]>;
4372 //===----------------------------------------------------------------------===//
4373 // SSE4.1 - Round Instructions
4374 //===----------------------------------------------------------------------===//
4376 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4377 X86MemOperand x86memop, RegisterClass RC,
4378 PatFrag mem_frag32, PatFrag mem_frag64,
4379 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4380 // Intrinsic operation, reg.
4381 // Vector intrinsic operation, reg
4382 def PSr : SS4AIi8<opcps, MRMSrcReg,
4383 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4384 !strconcat(OpcodeStr,
4385 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4386 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4389 // Vector intrinsic operation, mem
4390 def PSm : Ii8<opcps, MRMSrcMem,
4391 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4392 !strconcat(OpcodeStr,
4393 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4395 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4397 Requires<[HasSSE41]>;
4399 // Vector intrinsic operation, reg
4400 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4401 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4402 !strconcat(OpcodeStr,
4403 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4404 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4407 // Vector intrinsic operation, mem
4408 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4409 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4410 !strconcat(OpcodeStr,
4411 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4413 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4417 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4418 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4419 // Intrinsic operation, reg.
4420 // Vector intrinsic operation, reg
4421 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
4422 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4423 !strconcat(OpcodeStr,
4424 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4427 // Vector intrinsic operation, mem
4428 def PSm_AVX : Ii8<opcps, MRMSrcMem,
4429 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4430 !strconcat(OpcodeStr,
4431 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4432 []>, TA, OpSize, Requires<[HasSSE41]>;
4434 // Vector intrinsic operation, reg
4435 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
4436 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4437 !strconcat(OpcodeStr,
4438 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4441 // Vector intrinsic operation, mem
4442 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
4443 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4444 !strconcat(OpcodeStr,
4445 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4449 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4452 Intrinsic F64Int, bit Is2Addr = 1> {
4453 // Intrinsic operation, reg.
4454 def SSr : SS4AIi8<opcss, MRMSrcReg,
4455 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4457 !strconcat(OpcodeStr,
4458 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4459 !strconcat(OpcodeStr,
4460 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4461 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4464 // Intrinsic operation, mem.
4465 def SSm : SS4AIi8<opcss, MRMSrcMem,
4466 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4468 !strconcat(OpcodeStr,
4469 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4470 !strconcat(OpcodeStr,
4471 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4473 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4476 // Intrinsic operation, reg.
4477 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4478 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4480 !strconcat(OpcodeStr,
4481 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4482 !strconcat(OpcodeStr,
4483 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4484 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4487 // Intrinsic operation, mem.
4488 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4489 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4491 !strconcat(OpcodeStr,
4492 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4493 !strconcat(OpcodeStr,
4494 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4496 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4500 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4502 // Intrinsic operation, reg.
4503 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
4504 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4505 !strconcat(OpcodeStr,
4506 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4509 // Intrinsic operation, mem.
4510 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
4511 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4512 !strconcat(OpcodeStr,
4513 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4516 // Intrinsic operation, reg.
4517 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
4518 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4519 !strconcat(OpcodeStr,
4520 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4523 // Intrinsic operation, mem.
4524 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
4525 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4526 !strconcat(OpcodeStr,
4527 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4531 // FP round - roundss, roundps, roundsd, roundpd
4532 let Predicates = [HasAVX] in {
4534 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4535 memopv4f32, memopv2f64,
4536 int_x86_sse41_round_ps,
4537 int_x86_sse41_round_pd>, VEX;
4538 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4539 memopv8f32, memopv4f64,
4540 int_x86_avx_round_ps_256,
4541 int_x86_avx_round_pd_256>, VEX;
4542 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4543 int_x86_sse41_round_ss,
4544 int_x86_sse41_round_sd, 0>, VEX_4V;
4546 // Instructions for the assembler
4547 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4549 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4551 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4554 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4555 memopv4f32, memopv2f64,
4556 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4557 let Constraints = "$src1 = $dst" in
4558 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4559 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4561 //===----------------------------------------------------------------------===//
4562 // SSE4.1 - Packed Bit Test
4563 //===----------------------------------------------------------------------===//
4565 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4566 // the intel intrinsic that corresponds to this.
4567 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4568 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4569 "vptest\t{$src2, $src1|$src1, $src2}",
4570 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4572 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4573 "vptest\t{$src2, $src1|$src1, $src2}",
4574 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4577 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4578 "vptest\t{$src2, $src1|$src1, $src2}",
4579 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
4581 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4582 "vptest\t{$src2, $src1|$src1, $src2}",
4583 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
4587 let Defs = [EFLAGS] in {
4588 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4589 "ptest \t{$src2, $src1|$src1, $src2}",
4590 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4592 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4593 "ptest \t{$src2, $src1|$src1, $src2}",
4594 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4598 // The bit test instructions below are AVX only
4599 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4600 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
4601 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
4602 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4603 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
4604 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
4605 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4606 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
4610 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4611 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
4612 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
4613 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
4614 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
4617 //===----------------------------------------------------------------------===//
4618 // SSE4.1 - Misc Instructions
4619 //===----------------------------------------------------------------------===//
4621 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4622 "popcnt{w}\t{$src, $dst|$dst, $src}",
4623 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
4624 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4625 "popcnt{w}\t{$src, $dst|$dst, $src}",
4626 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
4628 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4629 "popcnt{l}\t{$src, $dst|$dst, $src}",
4630 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
4631 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4632 "popcnt{l}\t{$src, $dst|$dst, $src}",
4633 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
4635 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4636 "popcnt{q}\t{$src, $dst|$dst, $src}",
4637 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
4638 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4639 "popcnt{q}\t{$src, $dst|$dst, $src}",
4640 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
4644 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4645 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4646 Intrinsic IntId128> {
4647 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4649 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4650 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4651 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4653 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4656 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4659 let Predicates = [HasAVX] in
4660 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4661 int_x86_sse41_phminposuw>, VEX;
4662 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4663 int_x86_sse41_phminposuw>;
4665 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4666 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4667 Intrinsic IntId128, bit Is2Addr = 1> {
4668 let isCommutable = 1 in
4669 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4670 (ins VR128:$src1, VR128:$src2),
4672 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4673 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4674 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4675 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4676 (ins VR128:$src1, i128mem:$src2),
4678 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4679 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4681 (IntId128 VR128:$src1,
4682 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4685 let Predicates = [HasAVX] in {
4686 let isCommutable = 0 in
4687 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4689 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4691 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4693 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4695 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4697 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4699 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4701 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4703 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4705 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4707 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4711 let Constraints = "$src1 = $dst" in {
4712 let isCommutable = 0 in
4713 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4714 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4715 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4716 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4717 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4718 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4719 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4720 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4721 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4722 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4723 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4726 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4727 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4728 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4729 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4731 /// SS48I_binop_rm - Simple SSE41 binary operator.
4732 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4733 ValueType OpVT, bit Is2Addr = 1> {
4734 let isCommutable = 1 in
4735 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4736 (ins VR128:$src1, VR128:$src2),
4738 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4739 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4740 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4742 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4743 (ins VR128:$src1, i128mem:$src2),
4745 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4746 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4747 [(set VR128:$dst, (OpNode VR128:$src1,
4748 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4752 let Predicates = [HasAVX] in
4753 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4754 let Constraints = "$src1 = $dst" in
4755 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4757 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4758 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4759 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4760 X86MemOperand x86memop, bit Is2Addr = 1> {
4761 let isCommutable = 1 in
4762 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4763 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
4765 !strconcat(OpcodeStr,
4766 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4767 !strconcat(OpcodeStr,
4768 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4769 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4771 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4772 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
4774 !strconcat(OpcodeStr,
4775 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4776 !strconcat(OpcodeStr,
4777 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4780 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4784 let Predicates = [HasAVX] in {
4785 let isCommutable = 0 in {
4786 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4787 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4788 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4789 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4790 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
4791 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4792 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
4793 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4794 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4795 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4796 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4797 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4799 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4800 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4801 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4802 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4803 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
4804 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4807 let Constraints = "$src1 = $dst" in {
4808 let isCommutable = 0 in {
4809 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4810 VR128, memopv16i8, i128mem>;
4811 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4812 VR128, memopv16i8, i128mem>;
4813 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4814 VR128, memopv16i8, i128mem>;
4815 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4816 VR128, memopv16i8, i128mem>;
4818 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4819 VR128, memopv16i8, i128mem>;
4820 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4821 VR128, memopv16i8, i128mem>;
4824 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4825 let Predicates = [HasAVX] in {
4826 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4827 RegisterClass RC, X86MemOperand x86memop,
4828 PatFrag mem_frag, Intrinsic IntId> {
4829 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4830 (ins RC:$src1, RC:$src2, RC:$src3),
4831 !strconcat(OpcodeStr,
4832 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4833 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4834 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4836 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4837 (ins RC:$src1, x86memop:$src2, RC:$src3),
4838 !strconcat(OpcodeStr,
4839 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4841 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
4843 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4847 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
4848 memopv16i8, int_x86_sse41_blendvpd>;
4849 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
4850 memopv16i8, int_x86_sse41_blendvps>;
4851 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
4852 memopv16i8, int_x86_sse41_pblendvb>;
4853 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
4854 memopv32i8, int_x86_avx_blendv_pd_256>;
4855 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
4856 memopv32i8, int_x86_avx_blendv_ps_256>;
4858 /// SS41I_ternary_int - SSE 4.1 ternary operator
4859 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4860 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4861 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4862 (ins VR128:$src1, VR128:$src2),
4863 !strconcat(OpcodeStr,
4864 "\t{$src2, $dst|$dst, $src2}"),
4865 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4868 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4869 (ins VR128:$src1, i128mem:$src2),
4870 !strconcat(OpcodeStr,
4871 "\t{$src2, $dst|$dst, $src2}"),
4874 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4878 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4879 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4880 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4882 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
4883 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
4885 let Predicates = [HasAVX] in
4886 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4887 "vmovntdqa\t{$src, $dst|$dst, $src}",
4888 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4890 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4891 "movntdqa\t{$src, $dst|$dst, $src}",
4892 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4895 //===----------------------------------------------------------------------===//
4896 // SSE4.2 - Compare Instructions
4897 //===----------------------------------------------------------------------===//
4899 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4900 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4901 Intrinsic IntId128, bit Is2Addr = 1> {
4902 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4903 (ins VR128:$src1, VR128:$src2),
4905 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4906 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4907 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4909 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4910 (ins VR128:$src1, i128mem:$src2),
4912 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4913 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4915 (IntId128 VR128:$src1,
4916 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4919 let Predicates = [HasAVX] in
4920 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
4922 let Constraints = "$src1 = $dst" in
4923 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4925 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4926 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4927 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4928 (PCMPGTQrm VR128:$src1, addr:$src2)>;
4930 //===----------------------------------------------------------------------===//
4931 // SSE4.2 - String/text Processing Instructions
4932 //===----------------------------------------------------------------------===//
4934 // Packed Compare Implicit Length Strings, Return Mask
4935 multiclass pseudo_pcmpistrm<string asm> {
4936 def REG : PseudoI<(outs VR128:$dst),
4937 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4938 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4940 def MEM : PseudoI<(outs VR128:$dst),
4941 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4942 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
4943 VR128:$src1, (load addr:$src2), imm:$src3))]>;
4946 let Defs = [EFLAGS], usesCustomInserter = 1 in {
4947 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
4948 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
4951 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
4952 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4953 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4954 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4955 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4956 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4957 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4960 let Defs = [XMM0, EFLAGS] in {
4961 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4962 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4963 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4964 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4965 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4966 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4969 // Packed Compare Explicit Length Strings, Return Mask
4970 multiclass pseudo_pcmpestrm<string asm> {
4971 def REG : PseudoI<(outs VR128:$dst),
4972 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4973 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4974 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
4975 def MEM : PseudoI<(outs VR128:$dst),
4976 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4977 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4978 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
4981 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
4982 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
4983 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
4986 let Predicates = [HasAVX],
4987 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4988 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4989 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4990 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4991 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4992 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4993 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4996 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4997 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4998 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4999 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5000 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
5001 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5002 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
5005 // Packed Compare Implicit Length Strings, Return Index
5006 let Defs = [ECX, EFLAGS] in {
5007 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
5008 def rr : SS42AI<0x63, MRMSrcReg, (outs),
5009 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5010 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5011 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
5012 (implicit EFLAGS)]>, OpSize;
5013 def rm : SS42AI<0x63, MRMSrcMem, (outs),
5014 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5015 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5016 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
5017 (implicit EFLAGS)]>, OpSize;
5021 let Predicates = [HasAVX] in {
5022 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
5024 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
5026 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
5028 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
5030 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
5032 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
5036 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
5037 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
5038 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
5039 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
5040 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
5041 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
5043 // Packed Compare Explicit Length Strings, Return Index
5044 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
5045 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
5046 def rr : SS42AI<0x61, MRMSrcReg, (outs),
5047 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5048 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5049 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
5050 (implicit EFLAGS)]>, OpSize;
5051 def rm : SS42AI<0x61, MRMSrcMem, (outs),
5052 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5053 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5055 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
5056 (implicit EFLAGS)]>, OpSize;
5060 let Predicates = [HasAVX] in {
5061 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
5063 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
5065 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
5067 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
5069 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
5071 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
5075 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
5076 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
5077 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
5078 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
5079 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
5080 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
5082 //===----------------------------------------------------------------------===//
5083 // SSE4.2 - CRC Instructions
5084 //===----------------------------------------------------------------------===//
5086 // No CRC instructions have AVX equivalents
5088 // crc intrinsic instruction
5089 // This set of instructions are only rm, the only difference is the size
5091 let Constraints = "$src1 = $dst" in {
5092 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5093 (ins GR32:$src1, i8mem:$src2),
5094 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5096 (int_x86_sse42_crc32_32_8 GR32:$src1,
5097 (load addr:$src2)))]>;
5098 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5099 (ins GR32:$src1, GR8:$src2),
5100 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5102 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
5103 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5104 (ins GR32:$src1, i16mem:$src2),
5105 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5107 (int_x86_sse42_crc32_32_16 GR32:$src1,
5108 (load addr:$src2)))]>,
5110 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5111 (ins GR32:$src1, GR16:$src2),
5112 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5114 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
5116 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5117 (ins GR32:$src1, i32mem:$src2),
5118 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5120 (int_x86_sse42_crc32_32_32 GR32:$src1,
5121 (load addr:$src2)))]>;
5122 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5123 (ins GR32:$src1, GR32:$src2),
5124 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5126 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
5127 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5128 (ins GR64:$src1, i8mem:$src2),
5129 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5131 (int_x86_sse42_crc32_64_8 GR64:$src1,
5132 (load addr:$src2)))]>,
5134 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5135 (ins GR64:$src1, GR8:$src2),
5136 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5138 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
5140 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5141 (ins GR64:$src1, i64mem:$src2),
5142 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5144 (int_x86_sse42_crc32_64_64 GR64:$src1,
5145 (load addr:$src2)))]>,
5147 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5148 (ins GR64:$src1, GR64:$src2),
5149 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5151 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
5155 //===----------------------------------------------------------------------===//
5156 // AES-NI Instructions
5157 //===----------------------------------------------------------------------===//
5159 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5160 Intrinsic IntId128, bit Is2Addr = 1> {
5161 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5162 (ins VR128:$src1, VR128:$src2),
5164 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5165 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5166 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5168 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5169 (ins VR128:$src1, i128mem:$src2),
5171 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5172 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5174 (IntId128 VR128:$src1,
5175 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5178 // Perform One Round of an AES Encryption/Decryption Flow
5179 let Predicates = [HasAVX, HasAES] in {
5180 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5181 int_x86_aesni_aesenc, 0>, VEX_4V;
5182 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5183 int_x86_aesni_aesenclast, 0>, VEX_4V;
5184 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5185 int_x86_aesni_aesdec, 0>, VEX_4V;
5186 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5187 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5190 let Constraints = "$src1 = $dst" in {
5191 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5192 int_x86_aesni_aesenc>;
5193 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5194 int_x86_aesni_aesenclast>;
5195 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5196 int_x86_aesni_aesdec>;
5197 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5198 int_x86_aesni_aesdeclast>;
5201 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5202 (AESENCrr VR128:$src1, VR128:$src2)>;
5203 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5204 (AESENCrm VR128:$src1, addr:$src2)>;
5205 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5206 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5207 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5208 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5209 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5210 (AESDECrr VR128:$src1, VR128:$src2)>;
5211 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5212 (AESDECrm VR128:$src1, addr:$src2)>;
5213 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5214 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5215 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5216 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5218 // Perform the AES InvMixColumn Transformation
5219 let Predicates = [HasAVX, HasAES] in {
5220 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5222 "vaesimc\t{$src1, $dst|$dst, $src1}",
5224 (int_x86_aesni_aesimc VR128:$src1))]>,
5226 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5227 (ins i128mem:$src1),
5228 "vaesimc\t{$src1, $dst|$dst, $src1}",
5230 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5233 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5235 "aesimc\t{$src1, $dst|$dst, $src1}",
5237 (int_x86_aesni_aesimc VR128:$src1))]>,
5239 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5240 (ins i128mem:$src1),
5241 "aesimc\t{$src1, $dst|$dst, $src1}",
5243 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5246 // AES Round Key Generation Assist
5247 let Predicates = [HasAVX, HasAES] in {
5248 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5249 (ins VR128:$src1, i8imm:$src2),
5250 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5252 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5254 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5255 (ins i128mem:$src1, i8imm:$src2),
5256 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5258 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5262 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5263 (ins VR128:$src1, i8imm:$src2),
5264 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5266 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5268 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5269 (ins i128mem:$src1, i8imm:$src2),
5270 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5272 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5276 //===----------------------------------------------------------------------===//
5277 // CLMUL Instructions
5278 //===----------------------------------------------------------------------===//
5280 // Carry-less Multiplication instructions
5281 let Constraints = "$src1 = $dst" in {
5282 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5283 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5284 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5287 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5288 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5289 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
5293 // AVX carry-less Multiplication instructions
5294 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5295 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5296 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5299 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5300 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5301 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5305 multiclass pclmul_alias<string asm, int immop> {
5306 def : InstAlias<!strconcat("pclmul", asm,
5307 "dq {$src, $dst|$dst, $src}"),
5308 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
5310 def : InstAlias<!strconcat("pclmul", asm,
5311 "dq {$src, $dst|$dst, $src}"),
5312 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
5314 def : InstAlias<!strconcat("vpclmul", asm,
5315 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5316 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
5318 def : InstAlias<!strconcat("vpclmul", asm,
5319 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
5320 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
5322 defm : pclmul_alias<"hqhq", 0x11>;
5323 defm : pclmul_alias<"hqlq", 0x01>;
5324 defm : pclmul_alias<"lqhq", 0x10>;
5325 defm : pclmul_alias<"lqlq", 0x00>;
5327 //===----------------------------------------------------------------------===//
5329 //===----------------------------------------------------------------------===//
5331 //===----------------------------------------------------------------------===//
5332 // VBROADCAST - Load from memory and broadcast to all elements of the
5333 // destination operand
5335 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5336 X86MemOperand x86memop, Intrinsic Int> :
5337 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5338 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5339 [(set RC:$dst, (Int addr:$src))]>, VEX;
5341 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5342 int_x86_avx_vbroadcastss>;
5343 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5344 int_x86_avx_vbroadcastss_256>;
5345 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5346 int_x86_avx_vbroadcast_sd_256>;
5347 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5348 int_x86_avx_vbroadcastf128_pd_256>;
5350 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5351 (VBROADCASTF128 addr:$src)>;
5353 //===----------------------------------------------------------------------===//
5354 // VINSERTF128 - Insert packed floating-point values
5356 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5357 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5358 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5360 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5361 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5362 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5365 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5366 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5367 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5368 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5369 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5370 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5372 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
5374 (VINSERTF128rr VR256:$src1, VR128:$src2,
5375 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5376 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
5378 (VINSERTF128rr VR256:$src1, VR128:$src2,
5379 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5380 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
5382 (VINSERTF128rr VR256:$src1, VR128:$src2,
5383 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5384 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
5386 (VINSERTF128rr VR256:$src1, VR128:$src2,
5387 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5388 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
5390 (VINSERTF128rr VR256:$src1, VR128:$src2,
5391 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5392 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
5394 (VINSERTF128rr VR256:$src1, VR128:$src2,
5395 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5397 // Special COPY patterns
5398 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
5399 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5400 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
5401 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5402 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
5403 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5404 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
5405 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5406 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
5407 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5408 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
5409 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
5411 //===----------------------------------------------------------------------===//
5412 // VEXTRACTF128 - Extract packed floating-point values
5414 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5415 (ins VR256:$src1, i8imm:$src2),
5416 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5418 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5419 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5420 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5423 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
5424 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5425 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
5426 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5427 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
5428 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5430 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5431 (v4f32 (VEXTRACTF128rr
5432 (v8f32 VR256:$src1),
5433 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5434 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5435 (v2f64 (VEXTRACTF128rr
5436 (v4f64 VR256:$src1),
5437 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5438 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5439 (v4i32 (VEXTRACTF128rr
5440 (v8i32 VR256:$src1),
5441 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5442 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5443 (v2i64 (VEXTRACTF128rr
5444 (v4i64 VR256:$src1),
5445 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5446 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5447 (v8i16 (VEXTRACTF128rr
5448 (v16i16 VR256:$src1),
5449 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5450 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5451 (v16i8 (VEXTRACTF128rr
5452 (v32i8 VR256:$src1),
5453 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5455 //===----------------------------------------------------------------------===//
5456 // VMASKMOV - Conditional SIMD Packed Loads and Stores
5458 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
5459 Intrinsic IntLd, Intrinsic IntLd256,
5460 Intrinsic IntSt, Intrinsic IntSt256,
5461 PatFrag pf128, PatFrag pf256> {
5462 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5463 (ins VR128:$src1, f128mem:$src2),
5464 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5465 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
5467 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5468 (ins VR256:$src1, f256mem:$src2),
5469 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5470 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
5472 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5473 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5474 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5475 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
5476 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5477 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5478 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5479 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
5482 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
5483 int_x86_avx_maskload_ps,
5484 int_x86_avx_maskload_ps_256,
5485 int_x86_avx_maskstore_ps,
5486 int_x86_avx_maskstore_ps_256,
5487 memopv4f32, memopv8f32>;
5488 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
5489 int_x86_avx_maskload_pd,
5490 int_x86_avx_maskload_pd_256,
5491 int_x86_avx_maskstore_pd,
5492 int_x86_avx_maskstore_pd_256,
5493 memopv2f64, memopv4f64>;
5495 //===----------------------------------------------------------------------===//
5496 // VPERM - Permute Floating-Point Values
5498 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5499 RegisterClass RC, X86MemOperand x86memop_f,
5500 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5501 Intrinsic IntVar, Intrinsic IntImm> {
5502 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5503 (ins RC:$src1, RC:$src2),
5504 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5505 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5506 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5507 (ins RC:$src1, x86memop_i:$src2),
5508 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5509 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5511 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5512 (ins RC:$src1, i8imm:$src2),
5513 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5514 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5515 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5516 (ins x86memop_f:$src1, i8imm:$src2),
5517 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5518 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5521 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5522 memopv4f32, memopv4i32,
5523 int_x86_avx_vpermilvar_ps,
5524 int_x86_avx_vpermil_ps>;
5525 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5526 memopv8f32, memopv8i32,
5527 int_x86_avx_vpermilvar_ps_256,
5528 int_x86_avx_vpermil_ps_256>;
5529 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5530 memopv2f64, memopv2i64,
5531 int_x86_avx_vpermilvar_pd,
5532 int_x86_avx_vpermil_pd>;
5533 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5534 memopv4f64, memopv4i64,
5535 int_x86_avx_vpermilvar_pd_256,
5536 int_x86_avx_vpermil_pd_256>;
5538 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5539 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5540 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5542 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5543 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5544 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5547 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5548 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5549 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5550 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5551 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5552 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5554 def : Pat<(int_x86_avx_vperm2f128_ps_256
5555 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5556 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5557 def : Pat<(int_x86_avx_vperm2f128_pd_256
5558 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5559 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5560 def : Pat<(int_x86_avx_vperm2f128_si_256
5561 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5562 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5564 // Shuffle with VPERMIL instructions
5565 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
5566 (VPERMILPSYri VR256:$src1, imm:$imm)>;
5567 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
5568 (VPERMILPDYri VR256:$src1, imm:$imm)>;
5570 //===----------------------------------------------------------------------===//
5571 // VZERO - Zero YMM registers
5573 // Zero All YMM registers
5574 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
5575 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
5577 // Zero Upper bits of YMM registers
5578 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
5579 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
5581 //===----------------------------------------------------------------------===//
5582 // SSE Shuffle pattern fragments
5583 //===----------------------------------------------------------------------===//
5585 // This is part of a "work in progress" refactoring. The idea is that all
5586 // vector shuffles are going to be translated into target specific nodes and
5587 // directly matched by the patterns below (which can be changed along the way)
5588 // The AVX version of some but not all of them are described here, and more
5589 // should come in a near future.
5591 // Shuffle with PSHUFD instruction folding loads. The first two patterns match
5592 // SSE2 loads, which are always promoted to v2i64. The last one should match
5593 // the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD
5594 // in SSE2, how does it ever worked? Anyway, the pattern will remain here until
5595 // we investigate further.
5596 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5598 (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
5599 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5601 (PSHUFDmi addr:$src1, imm:$imm)>;
5602 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
5604 (PSHUFDmi addr:$src1, imm:$imm)>; // FIXME: has this ever worked?
5606 // Shuffle with PSHUFD instruction.
5607 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5608 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5609 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5610 (PSHUFDri VR128:$src1, imm:$imm)>;
5612 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5613 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5614 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5615 (PSHUFDri VR128:$src1, imm:$imm)>;
5617 // Shuffle with SHUFPD instruction.
5618 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5619 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5620 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5621 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5622 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5623 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
5625 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5626 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5627 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5628 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5630 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5631 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5632 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5633 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5635 // Shuffle with SHUFPS instruction.
5636 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5637 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5638 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5639 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5640 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5641 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5643 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5644 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5645 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5646 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5648 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5649 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5650 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5651 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5652 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5653 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5655 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5656 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5657 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5658 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5660 // Shuffle with MOVHLPS instruction
5661 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
5662 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5663 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
5664 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5666 // Shuffle with MOVDDUP instruction
5667 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5668 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5669 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5670 (MOVDDUPrm addr:$src)>;
5672 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5673 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5674 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5675 (MOVDDUPrm addr:$src)>;
5677 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5678 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5679 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5680 (MOVDDUPrm addr:$src)>;
5682 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5683 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5684 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5685 (MOVDDUPrm addr:$src)>;
5687 def : Pat<(X86Movddup (bc_v2f64
5688 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5689 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5690 def : Pat<(X86Movddup (bc_v2f64
5691 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5692 (MOVDDUPrm addr:$src)>;
5695 // Shuffle with UNPCKLPS
5696 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5697 (VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5698 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
5699 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5700 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5701 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
5703 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5704 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5705 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
5706 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5707 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5708 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
5710 // Shuffle with UNPCKHPS
5711 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5712 (VUNPCKHPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5713 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5714 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
5716 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5717 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5718 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5719 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
5721 // Shuffle with VUNPCKHPSY
5722 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
5723 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5724 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
5725 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5727 // Shuffle with UNPCKLPD
5728 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5729 (VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5730 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
5731 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5732 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5733 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
5735 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5736 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5737 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
5738 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5739 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5740 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
5742 // Shuffle with UNPCKHPD
5743 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5744 (VUNPCKHPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5745 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5746 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
5748 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5749 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5750 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5751 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
5753 // Shuffle with VUNPCKHPDY
5754 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
5755 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5756 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
5757 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5759 // Shuffle with MOVLHPS
5760 def : Pat<(X86Movlhps VR128:$src1,
5761 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5762 (MOVHPSrm VR128:$src1, addr:$src2)>;
5763 def : Pat<(X86Movlhps VR128:$src1,
5764 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
5765 (MOVHPSrm VR128:$src1, addr:$src2)>;
5766 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
5767 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5768 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
5769 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5770 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
5771 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
5773 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem
5774 // is during lowering, where it's not possible to recognize the load fold cause
5775 // it has two uses through a bitcast. One use disappears at isel time and the
5776 // fold opportunity reappears.
5777 def : Pat<(v2f64 (X86Movddup VR128:$src)),
5778 (UNPCKLPDrr VR128:$src, VR128:$src)>;
5780 // Shuffle with MOVLHPD
5781 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
5782 (scalar_to_vector (loadf64 addr:$src2)))),
5783 (MOVHPDrm VR128:$src1, addr:$src2)>;
5785 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
5786 // is during lowering, where it's not possible to recognize the load fold cause
5787 // it has two uses through a bitcast. One use disappears at isel time and the
5788 // fold opportunity reappears.
5789 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
5790 (scalar_to_vector (loadf64 addr:$src2)))),
5791 (MOVHPDrm VR128:$src1, addr:$src2)>;
5793 // Shuffle with MOVSS
5794 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
5795 (MOVSSrr VR128:$src1, FR32:$src2)>;
5796 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
5797 (MOVSSrr (v4i32 VR128:$src1),
5798 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
5799 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
5800 (MOVSSrr (v4f32 VR128:$src1),
5801 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
5802 // FIXME: Instead of a X86Movss there should be a X86Movlps here, the problem
5803 // is during lowering, where it's not possible to recognize the load fold cause
5804 // it has two uses through a bitcast. One use disappears at isel time and the
5805 // fold opportunity reappears.
5806 def : Pat<(X86Movss VR128:$src1,
5807 (bc_v4i32 (v2i64 (load addr:$src2)))),
5808 (MOVLPSrm VR128:$src1, addr:$src2)>;
5810 // Shuffle with MOVSD
5811 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
5812 (MOVSDrr VR128:$src1, FR64:$src2)>;
5813 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
5814 (MOVSDrr (v2i64 VR128:$src1),
5815 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
5816 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
5817 (MOVSDrr (v2f64 VR128:$src1),
5818 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
5819 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
5820 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5821 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
5822 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5824 // Shuffle with PSHUFHW
5825 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
5826 (PSHUFHWri VR128:$src, imm:$imm)>;
5827 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5828 (PSHUFHWmi addr:$src, imm:$imm)>;
5830 // Shuffle with PSHUFLW
5831 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
5832 (PSHUFLWri VR128:$src, imm:$imm)>;
5833 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5834 (PSHUFLWmi addr:$src, imm:$imm)>;
5836 // Shuffle with PALIGN
5837 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5838 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5839 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5840 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5841 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5842 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5843 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5844 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5846 // Shuffle with MOVLPS
5847 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
5848 (MOVLPSrm VR128:$src1, addr:$src2)>;
5849 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
5850 (MOVLPSrm VR128:$src1, addr:$src2)>;
5851 def : Pat<(X86Movlps VR128:$src1,
5852 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5853 (MOVLPSrm VR128:$src1, addr:$src2)>;
5854 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
5855 // is during lowering, where it's not possible to recognize the load fold cause
5856 // it has two uses through a bitcast. One use disappears at isel time and the
5857 // fold opportunity reappears.
5858 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
5859 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5861 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
5862 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5864 // Shuffle with MOVLPD
5865 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5866 (MOVLPDrm VR128:$src1, addr:$src2)>;
5867 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5868 (MOVLPDrm VR128:$src1, addr:$src2)>;
5869 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
5870 (scalar_to_vector (loadf64 addr:$src2)))),
5871 (MOVLPDrm VR128:$src1, addr:$src2)>;
5873 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
5874 def : Pat<(store (f64 (vector_extract
5875 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5876 (MOVHPSmr addr:$dst, VR128:$src)>;
5877 def : Pat<(store (f64 (vector_extract
5878 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5879 (MOVHPDmr addr:$dst, VR128:$src)>;
5881 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
5882 (MOVLPSmr addr:$src1, VR128:$src2)>;
5883 def : Pat<(store (v4i32 (X86Movlps
5884 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
5885 (MOVLPSmr addr:$src1, VR128:$src2)>;
5887 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5888 (MOVLPDmr addr:$src1, VR128:$src2)>;
5889 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5890 (MOVLPDmr addr:$src1, VR128:$src2)>;