1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 bit rr_hasSideEffects = 0> {
85 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
86 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
88 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
89 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
91 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
93 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
94 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
98 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
99 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
100 string asm, string SSEVer, string FPSizeStr,
101 X86MemOperand x86memop, PatFrag mem_frag,
102 Domain d, bit Is2Addr = 1> {
103 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
105 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
106 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
107 [(set RC:$dst, (!cast<Intrinsic>(
108 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
109 RC:$src1, RC:$src2))], d>;
110 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
112 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
113 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
114 [(set RC:$dst, (!cast<Intrinsic>(
115 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
116 RC:$src1, (mem_frag addr:$src2)))], d>;
119 //===----------------------------------------------------------------------===//
120 // Non-instruction patterns
121 //===----------------------------------------------------------------------===//
123 // A vector extract of the first f32/f64 position is a subregister copy
124 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
125 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
126 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
127 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
129 // A 128-bit subvector extract from the first 256-bit vector position
130 // is a subregister copy that needs no instruction.
131 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
132 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
133 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
134 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
136 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
137 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
138 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
139 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
141 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
142 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
143 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
144 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
146 // A 128-bit subvector insert to the first 256-bit vector position
147 // is a subregister copy that needs no instruction.
148 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
149 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
150 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
151 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
152 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
153 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
154 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
155 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
156 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
157 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
158 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
159 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
161 // Implicitly promote a 32-bit scalar to a vector.
162 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
163 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
164 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
165 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
166 // Implicitly promote a 64-bit scalar to a vector.
167 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
168 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
169 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
170 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
172 // Bitcasts between 128-bit vector types. Return the original type since
173 // no instruction is needed for the conversion
174 let Predicates = [HasSSE2] in {
175 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
176 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
178 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
179 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
180 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
183 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
184 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
185 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
188 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
189 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
190 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
193 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
194 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
195 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
198 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
199 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
200 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
202 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
203 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
204 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
207 // Bitcasts between 256-bit vector types. Return the original type since
208 // no instruction is needed for the conversion
209 let Predicates = [HasAVX] in {
210 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
211 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
213 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
214 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
215 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
218 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
219 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
220 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
223 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
224 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
225 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
228 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
229 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
230 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
233 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
234 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
235 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
237 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
238 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
239 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
242 // Alias instructions that map fld0 to pxor for sse.
243 // This is expanded by ExpandPostRAPseudos.
244 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
246 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
247 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
248 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
249 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
252 //===----------------------------------------------------------------------===//
253 // AVX & SSE - Zero/One Vectors
254 //===----------------------------------------------------------------------===//
256 // Alias instruction that maps zero vector to pxor / xorp* for sse.
257 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
258 // swizzled by ExecutionDepsFix to pxor.
259 // We set canFoldAsLoad because this can be converted to a constant-pool
260 // load of an all-zeros value if folding it would be beneficial.
261 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
262 isPseudo = 1, neverHasSideEffects = 1 in {
263 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
266 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
267 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
268 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
269 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
270 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
271 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
274 // The same as done above but for AVX. The 256-bit ISA does not support PI,
275 // and doesn't need it because on sandy bridge the register is set to zero
276 // at the rename stage without using any execution unit, so SET0PSY
277 // and SET0PDY can be used for vector int instructions without penalty
278 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
279 // JIT implementatioan, it does not expand the instructions below like
280 // X86MCInstLower does.
281 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
282 isCodeGenOnly = 1, Predicates = [HasAVX] in {
283 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
284 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
285 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
286 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
290 // AVX has no support for 256-bit integer instructions, but since the 128-bit
291 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
292 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
293 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
294 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
296 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
297 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
298 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
300 // We set canFoldAsLoad because this can be converted to a constant-pool
301 // load of an all-ones value if folding it would be beneficial.
302 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
303 // JIT implementation, it does not expand the instructions below like
304 // X86MCInstLower does.
305 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
306 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
307 let Predicates = [HasAVX] in
308 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
309 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
310 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
311 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
312 let Predicates = [HasAVX2] in
313 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
314 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
318 //===----------------------------------------------------------------------===//
319 // SSE 1 & 2 - Move FP Scalar Instructions
321 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
322 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
323 // is used instead. Register-to-register movss/movsd is not modeled as an
324 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
325 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
326 //===----------------------------------------------------------------------===//
328 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
329 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
330 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
332 // Loading from memory automatically zeroing upper bits.
333 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
334 PatFrag mem_pat, string OpcodeStr> :
335 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
336 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
337 [(set RC:$dst, (mem_pat addr:$src))]>;
340 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
341 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
343 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
344 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
347 // For the disassembler
348 let isCodeGenOnly = 1 in {
349 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
350 (ins VR128:$src1, FR32:$src2),
351 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
353 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
354 (ins VR128:$src1, FR64:$src2),
355 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
359 let canFoldAsLoad = 1, isReMaterializable = 1 in {
360 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
362 let AddedComplexity = 20 in
363 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
367 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
368 "movss\t{$src, $dst|$dst, $src}",
369 [(store FR32:$src, addr:$dst)]>, XS, VEX, VEX_LIG;
370 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
371 "movsd\t{$src, $dst|$dst, $src}",
372 [(store FR64:$src, addr:$dst)]>, XD, VEX, VEX_LIG;
375 let Constraints = "$src1 = $dst" in {
376 def MOVSSrr : sse12_move_rr<FR32, v4f32,
377 "movss\t{$src2, $dst|$dst, $src2}">, XS;
378 def MOVSDrr : sse12_move_rr<FR64, v2f64,
379 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
381 // For the disassembler
382 let isCodeGenOnly = 1 in {
383 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
384 (ins VR128:$src1, FR32:$src2),
385 "movss\t{$src2, $dst|$dst, $src2}", []>, XS;
386 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
387 (ins VR128:$src1, FR64:$src2),
388 "movsd\t{$src2, $dst|$dst, $src2}", []>, XD;
392 let canFoldAsLoad = 1, isReMaterializable = 1 in {
393 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
395 let AddedComplexity = 20 in
396 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
399 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
400 "movss\t{$src, $dst|$dst, $src}",
401 [(store FR32:$src, addr:$dst)]>;
402 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
403 "movsd\t{$src, $dst|$dst, $src}",
404 [(store FR64:$src, addr:$dst)]>;
407 let Predicates = [HasAVX] in {
408 let AddedComplexity = 15 in {
409 // Extract the low 32-bit value from one vector and insert it into another.
410 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
411 (VMOVSSrr (v4f32 VR128:$src1),
412 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
413 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
414 (VMOVSSrr (v4i32 VR128:$src1),
415 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
417 // Extract the low 64-bit value from one vector and insert it into another.
418 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
419 (VMOVSDrr (v2f64 VR128:$src1),
420 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
421 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
422 (VMOVSDrr (v2i64 VR128:$src1),
423 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
425 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
426 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
427 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
428 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
429 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
431 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
432 // MOVS{S,D} to the lower bits.
433 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
434 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
435 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
436 (VMOVSSrr (v4f32 (V_SET0)),
437 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
438 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
439 (VMOVSSrr (v4i32 (V_SET0)),
440 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
441 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
442 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
444 // Move low f32 and clear high bits.
445 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
446 (SUBREG_TO_REG (i32 0),
447 (VMOVSSrr (v4f32 (V_SET0)),
448 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_ss)), sub_xmm)>;
449 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
450 (SUBREG_TO_REG (i32 0),
451 (VMOVSSrr (v4i32 (V_SET0)),
452 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_ss)), sub_xmm)>;
455 let AddedComplexity = 20 in {
456 // MOVSSrm zeros the high parts of the register; represent this
457 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
458 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
459 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
460 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
461 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
462 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
463 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
465 // MOVSDrm zeros the high parts of the register; represent this
466 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
467 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
468 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
469 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
470 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
471 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
472 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
473 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
474 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
475 def : Pat<(v2f64 (X86vzload addr:$src)),
476 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
478 // Represent the same patterns above but in the form they appear for
480 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
481 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
482 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
483 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
484 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
485 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
486 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
487 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
488 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
490 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
491 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
492 (SUBREG_TO_REG (i32 0),
493 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
495 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
496 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
497 (SUBREG_TO_REG (i64 0),
498 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
500 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
501 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
502 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
504 // Move low f64 and clear high bits.
505 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
506 (SUBREG_TO_REG (i32 0),
507 (VMOVSDrr (v2f64 (V_SET0)),
508 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_sd)), sub_xmm)>;
510 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
511 (SUBREG_TO_REG (i32 0),
512 (VMOVSDrr (v2i64 (V_SET0)),
513 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_sd)), sub_xmm)>;
515 // Extract and store.
516 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
519 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
520 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
523 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
525 // Shuffle with VMOVSS
526 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
527 (VMOVSSrr VR128:$src1, FR32:$src2)>;
528 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
529 (VMOVSSrr (v4i32 VR128:$src1),
530 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
531 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
532 (VMOVSSrr (v4f32 VR128:$src1),
533 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
536 def : Pat<(v8i32 (X86Movsd VR256:$src1, VR256:$src2)),
537 (SUBREG_TO_REG (i32 0),
538 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_ss),
539 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_ss)), sub_xmm)>;
540 def : Pat<(v8f32 (X86Movsd VR256:$src1, VR256:$src2)),
541 (SUBREG_TO_REG (i32 0),
542 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_ss),
543 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_ss)), sub_xmm)>;
545 // Shuffle with VMOVSD
546 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
547 (VMOVSDrr VR128:$src1, FR64:$src2)>;
548 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
549 (VMOVSDrr (v2i64 VR128:$src1),
550 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
551 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
552 (VMOVSDrr (v2f64 VR128:$src1),
553 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
554 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
555 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
557 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
558 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
562 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
563 (SUBREG_TO_REG (i32 0),
564 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_sd),
565 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_sd)), sub_xmm)>;
566 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
567 (SUBREG_TO_REG (i32 0),
568 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_sd),
569 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_sd)), sub_xmm)>;
572 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
573 // is during lowering, where it's not possible to recognize the fold cause
574 // it has two uses through a bitcast. One use disappears at isel time and the
575 // fold opportunity reappears.
576 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
577 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
579 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
580 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),
582 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
583 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
585 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
586 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
590 let Predicates = [HasSSE1] in {
591 let AddedComplexity = 15 in {
592 // Extract the low 32-bit value from one vector and insert it into another.
593 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
594 (MOVSSrr (v4f32 VR128:$src1),
595 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
596 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
597 (MOVSSrr (v4i32 VR128:$src1),
598 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
600 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
601 // MOVSS to the lower bits.
602 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
603 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
604 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
605 (MOVSSrr (v4f32 (V_SET0)),
606 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
607 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
608 (MOVSSrr (v4i32 (V_SET0)),
609 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
612 let AddedComplexity = 20 in {
613 // MOVSSrm zeros the high parts of the register; represent this
614 // with SUBREG_TO_REG.
615 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
616 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
617 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
618 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
619 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
620 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
623 // Extract and store.
624 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
627 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
629 // Shuffle with MOVSS
630 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
631 (MOVSSrr VR128:$src1, FR32:$src2)>;
632 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
633 (MOVSSrr (v4i32 VR128:$src1),
634 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
635 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
636 (MOVSSrr (v4f32 VR128:$src1),
637 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
640 let Predicates = [HasSSE2] in {
641 let AddedComplexity = 15 in {
642 // Extract the low 64-bit value from one vector and insert it into another.
643 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
644 (MOVSDrr (v2f64 VR128:$src1),
645 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
646 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
647 (MOVSDrr (v2i64 VR128:$src1),
648 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
650 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
651 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
652 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
653 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
654 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
656 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
657 // MOVSD to the lower bits.
658 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
659 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
662 let AddedComplexity = 20 in {
663 // MOVSDrm zeros the high parts of the register; represent this
664 // with SUBREG_TO_REG.
665 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
666 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
667 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
668 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
669 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
670 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
671 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
672 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
673 def : Pat<(v2f64 (X86vzload addr:$src)),
674 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
677 // Extract and store.
678 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
681 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
683 // Shuffle with MOVSD
684 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
685 (MOVSDrr VR128:$src1, FR64:$src2)>;
686 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
687 (MOVSDrr (v2i64 VR128:$src1),
688 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
689 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
690 (MOVSDrr (v2f64 VR128:$src1),
691 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
692 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
693 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
694 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
695 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
697 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
698 // is during lowering, where it's not possible to recognize the fold cause
699 // it has two uses through a bitcast. One use disappears at isel time and the
700 // fold opportunity reappears.
701 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
702 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
703 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
704 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
705 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
706 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
707 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
708 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
711 //===----------------------------------------------------------------------===//
712 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
713 //===----------------------------------------------------------------------===//
715 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
716 X86MemOperand x86memop, PatFrag ld_frag,
717 string asm, Domain d,
718 bit IsReMaterializable = 1> {
719 let neverHasSideEffects = 1 in
720 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
721 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
722 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
723 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
724 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
725 [(set RC:$dst, (ld_frag addr:$src))], d>;
728 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
729 "movaps", SSEPackedSingle>, TB, VEX;
730 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
731 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
732 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
733 "movups", SSEPackedSingle>, TB, VEX;
734 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
735 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
737 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
738 "movaps", SSEPackedSingle>, TB, VEX;
739 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
740 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
741 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
742 "movups", SSEPackedSingle>, TB, VEX;
743 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
744 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
745 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
746 "movaps", SSEPackedSingle>, TB;
747 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
748 "movapd", SSEPackedDouble>, TB, OpSize;
749 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
750 "movups", SSEPackedSingle>, TB;
751 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
752 "movupd", SSEPackedDouble, 0>, TB, OpSize;
754 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
755 "movaps\t{$src, $dst|$dst, $src}",
756 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
757 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
758 "movapd\t{$src, $dst|$dst, $src}",
759 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
760 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
761 "movups\t{$src, $dst|$dst, $src}",
762 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
763 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
764 "movupd\t{$src, $dst|$dst, $src}",
765 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
766 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
767 "movaps\t{$src, $dst|$dst, $src}",
768 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)]>, VEX;
769 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
770 "movapd\t{$src, $dst|$dst, $src}",
771 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)]>, VEX;
772 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
773 "movups\t{$src, $dst|$dst, $src}",
774 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
775 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
776 "movupd\t{$src, $dst|$dst, $src}",
777 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
780 let isCodeGenOnly = 1 in {
781 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
783 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
784 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
786 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
787 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
789 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
790 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
792 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
793 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
795 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
796 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
798 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
799 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
801 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
802 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
804 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
807 let Predicates = [HasAVX] in {
808 def : Pat<(v8i32 (X86vzmovl
809 (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
810 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
811 def : Pat<(v4i64 (X86vzmovl
812 (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
813 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
814 def : Pat<(v8f32 (X86vzmovl
815 (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
816 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
817 def : Pat<(v4f64 (X86vzmovl
818 (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
819 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
823 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
824 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
825 (VMOVUPSYmr addr:$dst, VR256:$src)>;
827 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
828 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
829 (VMOVUPDYmr addr:$dst, VR256:$src)>;
831 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
832 "movaps\t{$src, $dst|$dst, $src}",
833 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
834 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
835 "movapd\t{$src, $dst|$dst, $src}",
836 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
837 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
838 "movups\t{$src, $dst|$dst, $src}",
839 [(store (v4f32 VR128:$src), addr:$dst)]>;
840 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
841 "movupd\t{$src, $dst|$dst, $src}",
842 [(store (v2f64 VR128:$src), addr:$dst)]>;
845 let isCodeGenOnly = 1 in {
846 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
847 "movaps\t{$src, $dst|$dst, $src}", []>;
848 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
849 "movapd\t{$src, $dst|$dst, $src}", []>;
850 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
851 "movups\t{$src, $dst|$dst, $src}", []>;
852 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
853 "movupd\t{$src, $dst|$dst, $src}", []>;
856 let Predicates = [HasAVX] in {
857 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
858 (VMOVUPSmr addr:$dst, VR128:$src)>;
859 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
860 (VMOVUPDmr addr:$dst, VR128:$src)>;
863 let Predicates = [HasSSE1] in
864 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
865 (MOVUPSmr addr:$dst, VR128:$src)>;
866 let Predicates = [HasSSE2] in
867 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
868 (MOVUPDmr addr:$dst, VR128:$src)>;
870 // Use vmovaps/vmovups for AVX integer load/store.
871 let Predicates = [HasAVX] in {
872 // 128-bit load/store
873 def : Pat<(alignedloadv4i32 addr:$src),
874 (VMOVAPSrm addr:$src)>;
875 def : Pat<(loadv4i32 addr:$src),
876 (VMOVUPSrm addr:$src)>;
877 def : Pat<(alignedloadv2i64 addr:$src),
878 (VMOVAPSrm addr:$src)>;
879 def : Pat<(loadv2i64 addr:$src),
880 (VMOVUPSrm addr:$src)>;
882 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
883 (VMOVAPSmr addr:$dst, VR128:$src)>;
884 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
885 (VMOVAPSmr addr:$dst, VR128:$src)>;
886 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
887 (VMOVAPSmr addr:$dst, VR128:$src)>;
888 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
889 (VMOVAPSmr addr:$dst, VR128:$src)>;
890 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
891 (VMOVUPSmr addr:$dst, VR128:$src)>;
892 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
893 (VMOVUPSmr addr:$dst, VR128:$src)>;
894 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
895 (VMOVUPSmr addr:$dst, VR128:$src)>;
896 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
897 (VMOVUPSmr addr:$dst, VR128:$src)>;
899 // 256-bit load/store
900 def : Pat<(alignedloadv4i64 addr:$src),
901 (VMOVAPSYrm addr:$src)>;
902 def : Pat<(loadv4i64 addr:$src),
903 (VMOVUPSYrm addr:$src)>;
904 def : Pat<(alignedloadv8i32 addr:$src),
905 (VMOVAPSYrm addr:$src)>;
906 def : Pat<(loadv8i32 addr:$src),
907 (VMOVUPSYrm addr:$src)>;
908 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
909 (VMOVAPSYmr addr:$dst, VR256:$src)>;
910 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
911 (VMOVAPSYmr addr:$dst, VR256:$src)>;
912 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
913 (VMOVAPSYmr addr:$dst, VR256:$src)>;
914 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
915 (VMOVAPSYmr addr:$dst, VR256:$src)>;
916 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
917 (VMOVUPSYmr addr:$dst, VR256:$src)>;
918 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
919 (VMOVUPSYmr addr:$dst, VR256:$src)>;
920 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
921 (VMOVUPSYmr addr:$dst, VR256:$src)>;
922 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
923 (VMOVUPSYmr addr:$dst, VR256:$src)>;
926 // Use movaps / movups for SSE integer load / store (one byte shorter).
927 // The instructions selected below are then converted to MOVDQA/MOVDQU
928 // during the SSE domain pass.
929 let Predicates = [HasSSE1] in {
930 def : Pat<(alignedloadv4i32 addr:$src),
931 (MOVAPSrm addr:$src)>;
932 def : Pat<(loadv4i32 addr:$src),
933 (MOVUPSrm addr:$src)>;
934 def : Pat<(alignedloadv2i64 addr:$src),
935 (MOVAPSrm addr:$src)>;
936 def : Pat<(loadv2i64 addr:$src),
937 (MOVUPSrm addr:$src)>;
939 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
940 (MOVAPSmr addr:$dst, VR128:$src)>;
941 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
942 (MOVAPSmr addr:$dst, VR128:$src)>;
943 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
944 (MOVAPSmr addr:$dst, VR128:$src)>;
945 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
946 (MOVAPSmr addr:$dst, VR128:$src)>;
947 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
948 (MOVUPSmr addr:$dst, VR128:$src)>;
949 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
950 (MOVUPSmr addr:$dst, VR128:$src)>;
951 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
952 (MOVUPSmr addr:$dst, VR128:$src)>;
953 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
954 (MOVUPSmr addr:$dst, VR128:$src)>;
957 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
958 // bits are disregarded. FIXME: Set encoding to pseudo!
959 let neverHasSideEffects = 1 in {
960 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
961 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
962 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
963 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
964 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
965 "movaps\t{$src, $dst|$dst, $src}", []>;
966 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
967 "movapd\t{$src, $dst|$dst, $src}", []>;
970 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
971 // bits are disregarded. FIXME: Set encoding to pseudo!
972 let canFoldAsLoad = 1, isReMaterializable = 1 in {
973 let isCodeGenOnly = 1 in {
974 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
975 "movaps\t{$src, $dst|$dst, $src}",
976 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
977 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
978 "movapd\t{$src, $dst|$dst, $src}",
979 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
981 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
982 "movaps\t{$src, $dst|$dst, $src}",
983 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
984 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
985 "movapd\t{$src, $dst|$dst, $src}",
986 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
989 //===----------------------------------------------------------------------===//
990 // SSE 1 & 2 - Move Low packed FP Instructions
991 //===----------------------------------------------------------------------===//
993 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
994 PatFrag mov_frag, string base_opc,
996 def PSrm : PI<opc, MRMSrcMem,
997 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
998 !strconcat(base_opc, "s", asm_opr),
1001 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1002 SSEPackedSingle>, TB;
1004 def PDrm : PI<opc, MRMSrcMem,
1005 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1006 !strconcat(base_opc, "d", asm_opr),
1007 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
1008 (scalar_to_vector (loadf64 addr:$src2)))))],
1009 SSEPackedDouble>, TB, OpSize;
1012 let AddedComplexity = 20 in {
1013 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
1014 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1016 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1017 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
1018 "\t{$src2, $dst|$dst, $src2}">;
1021 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1022 "movlps\t{$src, $dst|$dst, $src}",
1023 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1024 (iPTR 0))), addr:$dst)]>, VEX;
1025 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1026 "movlpd\t{$src, $dst|$dst, $src}",
1027 [(store (f64 (vector_extract (v2f64 VR128:$src),
1028 (iPTR 0))), addr:$dst)]>, VEX;
1029 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1030 "movlps\t{$src, $dst|$dst, $src}",
1031 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1032 (iPTR 0))), addr:$dst)]>;
1033 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1034 "movlpd\t{$src, $dst|$dst, $src}",
1035 [(store (f64 (vector_extract (v2f64 VR128:$src),
1036 (iPTR 0))), addr:$dst)]>;
1038 let Predicates = [HasAVX] in {
1039 let AddedComplexity = 20 in {
1040 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1041 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1042 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1043 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1044 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1045 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1046 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1047 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1048 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1049 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1052 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1053 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1054 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1055 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1056 VR128:$src2)), addr:$src1),
1057 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1059 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1060 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1061 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1062 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1063 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1065 // Shuffle with VMOVLPS
1066 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1067 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1068 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1069 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1070 def : Pat<(X86Movlps VR128:$src1,
1071 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1072 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1074 // Shuffle with VMOVLPD
1075 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1076 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1077 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1078 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1079 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1080 (scalar_to_vector (loadf64 addr:$src2)))),
1081 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1084 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1086 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1087 def : Pat<(store (v4i32 (X86Movlps
1088 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1089 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1090 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1092 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1093 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1095 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1098 let Predicates = [HasSSE1] in {
1099 let AddedComplexity = 20 in {
1100 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1101 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1102 (MOVLPSrm VR128:$src1, addr:$src2)>;
1103 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1104 (MOVLPSrm VR128:$src1, addr:$src2)>;
1107 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1108 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1109 (iPTR 0))), addr:$src1),
1110 (MOVLPSmr addr:$src1, VR128:$src2)>;
1111 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1112 (MOVLPSmr addr:$src1, VR128:$src2)>;
1113 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1114 VR128:$src2)), addr:$src1),
1115 (MOVLPSmr addr:$src1, VR128:$src2)>;
1117 // Shuffle with MOVLPS
1118 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1119 (MOVLPSrm VR128:$src1, addr:$src2)>;
1120 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1121 (MOVLPSrm VR128:$src1, addr:$src2)>;
1122 def : Pat<(X86Movlps VR128:$src1,
1123 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1124 (MOVLPSrm VR128:$src1, addr:$src2)>;
1125 def : Pat<(X86Movlps VR128:$src1,
1126 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1127 (MOVLPSrm VR128:$src1, addr:$src2)>;
1130 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1132 (MOVLPSmr addr:$src1, VR128:$src2)>;
1133 def : Pat<(store (v4i32 (X86Movlps
1134 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1136 (MOVLPSmr addr:$src1, VR128:$src2)>;
1139 let Predicates = [HasSSE2] in {
1140 let AddedComplexity = 20 in {
1141 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1142 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1143 (MOVLPDrm VR128:$src1, addr:$src2)>;
1144 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1145 (MOVLPDrm VR128:$src1, addr:$src2)>;
1148 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1149 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1150 (MOVLPDmr addr:$src1, VR128:$src2)>;
1151 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1152 (MOVLPDmr addr:$src1, VR128:$src2)>;
1154 // Shuffle with MOVLPD
1155 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1156 (MOVLPDrm VR128:$src1, addr:$src2)>;
1157 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1158 (MOVLPDrm VR128:$src1, addr:$src2)>;
1159 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1160 (scalar_to_vector (loadf64 addr:$src2)))),
1161 (MOVLPDrm VR128:$src1, addr:$src2)>;
1164 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1166 (MOVLPDmr addr:$src1, VR128:$src2)>;
1167 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1169 (MOVLPDmr addr:$src1, VR128:$src2)>;
1172 //===----------------------------------------------------------------------===//
1173 // SSE 1 & 2 - Move Hi packed FP Instructions
1174 //===----------------------------------------------------------------------===//
1176 let AddedComplexity = 20 in {
1177 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1178 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1180 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1181 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1182 "\t{$src2, $dst|$dst, $src2}">;
1185 // v2f64 extract element 1 is always custom lowered to unpack high to low
1186 // and extract element 0 so the non-store version isn't too horrible.
1187 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1188 "movhps\t{$src, $dst|$dst, $src}",
1189 [(store (f64 (vector_extract
1190 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1191 (undef)), (iPTR 0))), addr:$dst)]>,
1193 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1194 "movhpd\t{$src, $dst|$dst, $src}",
1195 [(store (f64 (vector_extract
1196 (v2f64 (unpckh VR128:$src, (undef))),
1197 (iPTR 0))), addr:$dst)]>,
1199 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1200 "movhps\t{$src, $dst|$dst, $src}",
1201 [(store (f64 (vector_extract
1202 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1203 (undef)), (iPTR 0))), addr:$dst)]>;
1204 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1205 "movhpd\t{$src, $dst|$dst, $src}",
1206 [(store (f64 (vector_extract
1207 (v2f64 (unpckh VR128:$src, (undef))),
1208 (iPTR 0))), addr:$dst)]>;
1210 let Predicates = [HasAVX] in {
1212 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1213 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1214 def : Pat<(X86Movlhps VR128:$src1,
1215 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1216 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(X86Movlhps VR128:$src1,
1218 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1219 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1220 def : Pat<(X86Movlhps VR128:$src1,
1221 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1222 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1224 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1225 // is during lowering, where it's not possible to recognize the load fold
1226 // cause it has two uses through a bitcast. One use disappears at isel time
1227 // and the fold opportunity reappears.
1228 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1229 (scalar_to_vector (loadf64 addr:$src2)))),
1230 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1232 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1233 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1234 (scalar_to_vector (loadf64 addr:$src2)))),
1235 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1238 def : Pat<(store (f64 (vector_extract
1239 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1240 (bc_v2f64 (v4f32 VR128:$src))), (iPTR 0))), addr:$dst),
1241 (VMOVHPSmr addr:$dst, VR128:$src)>;
1242 def : Pat<(store (f64 (vector_extract
1243 (v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))), addr:$dst),
1244 (VMOVHPDmr addr:$dst, VR128:$src)>;
1247 let Predicates = [HasSSE1] in {
1249 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1250 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1251 def : Pat<(X86Movlhps VR128:$src1,
1252 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1253 (MOVHPSrm VR128:$src1, addr:$src2)>;
1254 def : Pat<(X86Movlhps VR128:$src1,
1255 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1256 (MOVHPSrm VR128:$src1, addr:$src2)>;
1257 def : Pat<(X86Movlhps VR128:$src1,
1258 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1259 (MOVHPSrm VR128:$src1, addr:$src2)>;
1262 def : Pat<(store (f64 (vector_extract
1263 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1264 (bc_v2f64 (v4f32 VR128:$src))), (iPTR 0))), addr:$dst),
1265 (MOVHPSmr addr:$dst, VR128:$src)>;
1268 let Predicates = [HasSSE2] in {
1269 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1270 // is during lowering, where it's not possible to recognize the load fold
1271 // cause it has two uses through a bitcast. One use disappears at isel time
1272 // and the fold opportunity reappears.
1273 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1274 (scalar_to_vector (loadf64 addr:$src2)))),
1275 (MOVHPDrm VR128:$src1, addr:$src2)>;
1277 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1278 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1279 (scalar_to_vector (loadf64 addr:$src2)))),
1280 (MOVHPDrm VR128:$src1, addr:$src2)>;
1283 def : Pat<(store (f64 (vector_extract
1284 (v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))),addr:$dst),
1285 (MOVHPDmr addr:$dst, VR128:$src)>;
1288 //===----------------------------------------------------------------------===//
1289 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1290 //===----------------------------------------------------------------------===//
1292 let AddedComplexity = 20 in {
1293 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1294 (ins VR128:$src1, VR128:$src2),
1295 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1297 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
1299 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1300 (ins VR128:$src1, VR128:$src2),
1301 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1303 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
1306 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1307 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1308 (ins VR128:$src1, VR128:$src2),
1309 "movlhps\t{$src2, $dst|$dst, $src2}",
1311 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
1312 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1313 (ins VR128:$src1, VR128:$src2),
1314 "movhlps\t{$src2, $dst|$dst, $src2}",
1316 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
1319 let Predicates = [HasAVX] in {
1321 let AddedComplexity = 20 in {
1322 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1323 (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1324 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1325 (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1327 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1328 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1329 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1331 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1332 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1333 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1334 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1335 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1336 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1339 let AddedComplexity = 20 in {
1340 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1341 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1342 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1344 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1345 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1346 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1347 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1348 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1351 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1352 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1353 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1354 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1357 let Predicates = [HasSSE1] in {
1359 let AddedComplexity = 20 in {
1360 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1361 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1362 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1363 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1365 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1366 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1367 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1369 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1370 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1371 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1372 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1373 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1374 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1377 let AddedComplexity = 20 in {
1378 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1379 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1380 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1382 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1383 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1384 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1385 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1386 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1389 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1390 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1391 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1392 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1395 //===----------------------------------------------------------------------===//
1396 // SSE 1 & 2 - Conversion Instructions
1397 //===----------------------------------------------------------------------===//
1399 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1400 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1402 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1403 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
1404 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1405 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
1408 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1409 X86MemOperand x86memop, string asm> {
1410 let neverHasSideEffects = 1 in {
1411 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, []>;
1413 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, []>;
1414 } // neverHasSideEffects = 1
1417 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1418 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1419 string asm, Domain d> {
1420 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1421 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
1422 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1423 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
1426 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1427 X86MemOperand x86memop, string asm> {
1428 let neverHasSideEffects = 1 in {
1429 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1430 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1432 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1433 (ins DstRC:$src1, x86memop:$src),
1434 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1435 } // neverHasSideEffects = 1
1438 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1439 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1441 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1442 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1444 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1445 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX,
1447 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1448 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
1449 VEX, VEX_W, VEX_LIG;
1451 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1452 // register, but the same isn't true when only using memory operands,
1453 // provide other assembly "l" and "q" forms to address this explicitly
1454 // where appropriate to do so.
1455 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
1457 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
1458 VEX_4V, VEX_W, VEX_LIG;
1459 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
1461 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
1463 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
1464 VEX_4V, VEX_W, VEX_LIG;
1466 let Predicates = [HasAVX], AddedComplexity = 1 in {
1467 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1468 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1469 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1470 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1471 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1472 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1473 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1474 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1476 def : Pat<(f32 (sint_to_fp GR32:$src)),
1477 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1478 def : Pat<(f32 (sint_to_fp GR64:$src)),
1479 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1480 def : Pat<(f64 (sint_to_fp GR32:$src)),
1481 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1482 def : Pat<(f64 (sint_to_fp GR64:$src)),
1483 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1486 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1487 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
1488 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1489 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1490 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1491 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
1492 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1493 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1494 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1495 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
1496 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1497 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1498 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1499 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
1500 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1501 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1503 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1504 // and/or XMM operand(s).
1506 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1507 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1509 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1510 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1511 [(set DstRC:$dst, (Int SrcRC:$src))]>;
1512 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1513 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1514 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
1517 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1518 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1519 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
1520 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1522 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1523 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1524 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
1525 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1526 (ins DstRC:$src1, x86memop:$src2),
1528 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1529 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1530 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
1533 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1534 f128mem, load, "cvtsd2si">, XD, VEX;
1535 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1536 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
1539 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
1540 // Get rid of this hack or rename the intrinsics, there are several
1541 // intructions that only match with the intrinsic form, why create duplicates
1542 // to let them be recognized by the assembler?
1543 defm VCVTSD2SI : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
1544 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_LIG;
1545 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
1546 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W,
1549 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1550 f128mem, load, "cvtsd2si{l}">, XD;
1551 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1552 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
1555 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1556 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
1557 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1558 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
1560 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1561 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
1562 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1563 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
1566 let Constraints = "$src1 = $dst" in {
1567 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1568 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1570 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1571 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1572 "cvtsi2ss{q}">, XS, REX_W;
1573 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1574 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1576 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1577 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1578 "cvtsi2sd">, XD, REX_W;
1583 // Aliases for intrinsics
1584 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1585 f32mem, load, "cvttss2si">, XS, VEX;
1586 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1587 int_x86_sse_cvttss2si64, f32mem, load,
1588 "cvttss2si">, XS, VEX, VEX_W;
1589 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1590 f128mem, load, "cvttsd2si">, XD, VEX;
1591 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1592 int_x86_sse2_cvttsd2si64, f128mem, load,
1593 "cvttsd2si">, XD, VEX, VEX_W;
1594 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1595 f32mem, load, "cvttss2si">, XS;
1596 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1597 int_x86_sse_cvttss2si64, f32mem, load,
1598 "cvttss2si{q}">, XS, REX_W;
1599 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1600 f128mem, load, "cvttsd2si">, XD;
1601 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1602 int_x86_sse2_cvttsd2si64, f128mem, load,
1603 "cvttsd2si{q}">, XD, REX_W;
1605 let Pattern = []<dag> in {
1606 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1607 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS,
1609 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1610 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1612 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1613 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1614 SSEPackedSingle>, TB, VEX;
1615 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1616 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1617 SSEPackedSingle>, TB, VEX;
1620 let Pattern = []<dag> in {
1621 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1622 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
1623 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1624 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1625 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1626 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1627 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
1630 let Predicates = [HasAVX] in {
1631 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1632 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1633 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1634 (VCVTSS2SIrm addr:$src)>;
1635 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1636 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1637 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1638 (VCVTSS2SI64rm addr:$src)>;
1641 let Predicates = [HasSSE1] in {
1642 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1643 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1644 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1645 (CVTSS2SIrm addr:$src)>;
1646 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1647 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1648 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1649 (CVTSS2SI64rm addr:$src)>;
1654 // Convert scalar double to scalar single
1655 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1656 (ins FR64:$src1, FR64:$src2),
1657 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1660 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1661 (ins FR64:$src1, f64mem:$src2),
1662 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1663 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1665 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1668 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1669 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1670 [(set FR32:$dst, (fround FR64:$src))]>;
1671 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1672 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1673 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1674 Requires<[HasSSE2, OptForSize]>;
1676 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1677 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1679 let Constraints = "$src1 = $dst" in
1680 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1681 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1683 // Convert scalar single to scalar double
1684 // SSE2 instructions with XS prefix
1685 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1686 (ins FR32:$src1, FR32:$src2),
1687 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1688 []>, XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1690 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1691 (ins FR32:$src1, f32mem:$src2),
1692 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1693 []>, XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1695 let Predicates = [HasAVX] in {
1696 def : Pat<(f64 (fextend FR32:$src)),
1697 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1698 def : Pat<(fextend (loadf32 addr:$src)),
1699 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1700 def : Pat<(extloadf32 addr:$src),
1701 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1704 def : Pat<(extloadf32 addr:$src),
1705 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1706 Requires<[HasAVX, OptForSpeed]>;
1708 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1709 "cvtss2sd\t{$src, $dst|$dst, $src}",
1710 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1711 Requires<[HasSSE2]>;
1712 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1713 "cvtss2sd\t{$src, $dst|$dst, $src}",
1714 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1715 Requires<[HasSSE2, OptForSize]>;
1717 // extload f32 -> f64. This matches load+fextend because we have a hack in
1718 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1720 // Since these loads aren't folded into the fextend, we have to match it
1722 def : Pat<(fextend (loadf32 addr:$src)),
1723 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1724 def : Pat<(extloadf32 addr:$src),
1725 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1727 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1728 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1729 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1730 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1731 VR128:$src2))]>, XS, VEX_4V,
1733 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1734 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1735 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1736 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1737 (load addr:$src2)))]>, XS, VEX_4V,
1739 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1740 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1741 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1742 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1743 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1744 VR128:$src2))]>, XS,
1745 Requires<[HasSSE2]>;
1746 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1747 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1748 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1749 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1750 (load addr:$src2)))]>, XS,
1751 Requires<[HasSSE2]>;
1754 // Convert doubleword to packed single/double fp
1755 // SSE2 instructions without OpSize prefix
1756 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1757 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1758 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1759 TB, VEX, Requires<[HasAVX]>;
1760 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1761 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1762 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1763 (bitconvert (memopv2i64 addr:$src))))]>,
1764 TB, VEX, Requires<[HasAVX]>;
1765 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1766 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1767 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1768 TB, Requires<[HasSSE2]>;
1769 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1770 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1771 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1772 (bitconvert (memopv2i64 addr:$src))))]>,
1773 TB, Requires<[HasSSE2]>;
1775 // FIXME: why the non-intrinsic version is described as SSE3?
1776 // SSE2 instructions with XS prefix
1777 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1778 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1779 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1780 XS, VEX, Requires<[HasAVX]>;
1781 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1782 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1783 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1784 (bitconvert (memopv2i64 addr:$src))))]>,
1785 XS, VEX, Requires<[HasAVX]>;
1786 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1787 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1788 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1789 XS, Requires<[HasSSE2]>;
1790 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1791 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1792 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1793 (bitconvert (memopv2i64 addr:$src))))]>,
1794 XS, Requires<[HasSSE2]>;
1797 // Convert packed single/double fp to doubleword
1798 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1799 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1800 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1801 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1802 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1803 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1804 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1805 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1806 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1807 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1808 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1809 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1811 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1812 "cvtps2dq\t{$src, $dst|$dst, $src}",
1813 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1815 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1817 "cvtps2dq\t{$src, $dst|$dst, $src}",
1818 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1819 (memop addr:$src)))]>, VEX;
1820 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1821 "cvtps2dq\t{$src, $dst|$dst, $src}",
1822 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1823 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1824 "cvtps2dq\t{$src, $dst|$dst, $src}",
1825 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1826 (memop addr:$src)))]>;
1828 // SSE2 packed instructions with XD prefix
1829 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1830 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1831 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1832 XD, VEX, Requires<[HasAVX]>;
1833 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1834 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1835 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1836 (memop addr:$src)))]>,
1837 XD, VEX, Requires<[HasAVX]>;
1838 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1839 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1840 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1841 XD, Requires<[HasSSE2]>;
1842 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1843 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1844 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1845 (memop addr:$src)))]>,
1846 XD, Requires<[HasSSE2]>;
1849 // Convert with truncation packed single/double fp to doubleword
1850 // SSE2 packed instructions with XS prefix
1851 let neverHasSideEffects = 1 in {
1852 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1853 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1855 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1856 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1857 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1858 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1860 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1861 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1862 } // neverHasSideEffects = 1
1864 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1865 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1867 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1868 XS, VEX, Requires<[HasAVX]>;
1869 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1870 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1871 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1872 (memop addr:$src)))]>,
1873 XS, VEX, Requires<[HasAVX]>;
1875 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1876 "cvttps2dq\t{$src, $dst|$dst, $src}",
1878 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1879 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1880 "cvttps2dq\t{$src, $dst|$dst, $src}",
1882 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1884 let Predicates = [HasAVX] in {
1885 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1886 (Int_VCVTDQ2PSrr VR128:$src)>;
1887 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1888 (VCVTTPS2DQrr VR128:$src)>;
1889 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1890 (VCVTDQ2PSYrr VR256:$src)>;
1891 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1892 (VCVTTPS2DQYrr VR256:$src)>;
1895 let Predicates = [HasSSE2] in {
1896 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1897 (Int_CVTDQ2PSrr VR128:$src)>;
1898 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1899 (CVTTPS2DQrr VR128:$src)>;
1902 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1903 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1905 (int_x86_sse2_cvttpd2dq VR128:$src))]>, VEX;
1906 let isCodeGenOnly = 1 in
1907 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1908 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1909 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1910 (memop addr:$src)))]>, VEX;
1911 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1912 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1913 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1914 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1915 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1916 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1917 (memop addr:$src)))]>;
1919 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1920 // register, but the same isn't true when using memory operands instead.
1921 // Provide other assembly rr and rm forms to address this explicitly.
1922 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1923 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1926 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1927 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1928 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1929 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1932 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1933 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1934 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1935 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1937 // Convert packed single to packed double
1938 let Predicates = [HasAVX] in {
1939 // SSE2 instructions without OpSize prefix
1940 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1941 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1942 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1943 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1944 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1945 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1946 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1947 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1949 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1950 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1951 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1952 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1954 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1955 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1956 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1957 TB, VEX, Requires<[HasAVX]>;
1958 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1959 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1960 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1961 (load addr:$src)))]>,
1962 TB, VEX, Requires<[HasAVX]>;
1963 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1964 "cvtps2pd\t{$src, $dst|$dst, $src}",
1965 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1966 TB, Requires<[HasSSE2]>;
1967 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1968 "cvtps2pd\t{$src, $dst|$dst, $src}",
1969 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1970 (load addr:$src)))]>,
1971 TB, Requires<[HasSSE2]>;
1973 // Convert packed double to packed single
1974 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1975 // register, but the same isn't true when using memory operands instead.
1976 // Provide other assembly rr and rm forms to address this explicitly.
1977 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1978 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1979 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1980 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1983 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1984 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1985 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1986 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1989 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1990 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1991 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1992 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1993 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1994 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1995 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1996 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1999 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2000 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2001 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
2002 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
2004 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2005 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
2006 (memop addr:$src)))]>;
2007 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2008 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2009 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
2010 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2011 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2012 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
2013 (memop addr:$src)))]>;
2015 // AVX 256-bit register conversion intrinsics
2016 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2017 // whenever possible to avoid declaring two versions of each one.
2018 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2019 (VCVTDQ2PSYrr VR256:$src)>;
2020 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2021 (VCVTDQ2PSYrm addr:$src)>;
2023 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
2024 (VCVTPD2PSYrr VR256:$src)>;
2025 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
2026 (VCVTPD2PSYrm addr:$src)>;
2028 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
2029 (VCVTPS2DQYrr VR256:$src)>;
2030 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
2031 (VCVTPS2DQYrm addr:$src)>;
2033 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
2034 (VCVTPS2PDYrr VR128:$src)>;
2035 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
2036 (VCVTPS2PDYrm addr:$src)>;
2038 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
2039 (VCVTTPD2DQYrr VR256:$src)>;
2040 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
2041 (VCVTTPD2DQYrm addr:$src)>;
2043 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
2044 (VCVTTPS2DQYrr VR256:$src)>;
2045 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
2046 (VCVTTPS2DQYrm addr:$src)>;
2048 // Match fround and fextend for 128/256-bit conversions
2049 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2050 (VCVTPD2PSYrr VR256:$src)>;
2051 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2052 (VCVTPD2PSYrm addr:$src)>;
2054 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2055 (VCVTPS2PDYrr VR128:$src)>;
2056 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
2057 (VCVTPS2PDYrm addr:$src)>;
2059 //===----------------------------------------------------------------------===//
2060 // SSE 1 & 2 - Compare Instructions
2061 //===----------------------------------------------------------------------===//
2063 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2064 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2065 SDNode OpNode, ValueType VT, PatFrag ld_frag,
2066 string asm, string asm_alt> {
2067 def rr : SIi8<0xC2, MRMSrcReg,
2068 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2069 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))]>;
2070 def rm : SIi8<0xC2, MRMSrcMem,
2071 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
2072 [(set RC:$dst, (OpNode (VT RC:$src1),
2073 (ld_frag addr:$src2), imm:$cc))]>;
2075 // Accept explicit immediate argument form instead of comparison code.
2076 let neverHasSideEffects = 1 in {
2077 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2078 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, []>;
2080 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2081 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, []>;
2085 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2086 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2087 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2088 XS, VEX_4V, VEX_LIG;
2089 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2090 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2091 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2092 XD, VEX_4V, VEX_LIG;
2094 let Constraints = "$src1 = $dst" in {
2095 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2096 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2097 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2099 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2100 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2101 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2105 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
2106 Intrinsic Int, string asm> {
2107 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2108 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
2109 [(set VR128:$dst, (Int VR128:$src1,
2110 VR128:$src, imm:$cc))]>;
2111 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2112 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
2113 [(set VR128:$dst, (Int VR128:$src1,
2114 (load addr:$src), imm:$cc))]>;
2117 // Aliases to match intrinsics which expect XMM operand(s).
2118 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2119 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
2121 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2122 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
2124 let Constraints = "$src1 = $dst" in {
2125 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2126 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
2127 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2128 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
2132 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2133 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2134 ValueType vt, X86MemOperand x86memop,
2135 PatFrag ld_frag, string OpcodeStr, Domain d> {
2136 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2137 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2138 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
2139 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2140 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2141 [(set EFLAGS, (OpNode (vt RC:$src1),
2142 (ld_frag addr:$src2)))], d>;
2145 let Defs = [EFLAGS] in {
2146 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2147 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2148 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2149 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2151 let Pattern = []<dag> in {
2152 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2153 "comiss", SSEPackedSingle>, TB, VEX,
2155 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2156 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2160 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2161 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2162 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2163 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2165 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2166 load, "comiss", SSEPackedSingle>, TB, VEX;
2167 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2168 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2169 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2170 "ucomiss", SSEPackedSingle>, TB;
2171 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2172 "ucomisd", SSEPackedDouble>, TB, OpSize;
2174 let Pattern = []<dag> in {
2175 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2176 "comiss", SSEPackedSingle>, TB;
2177 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2178 "comisd", SSEPackedDouble>, TB, OpSize;
2181 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2182 load, "ucomiss", SSEPackedSingle>, TB;
2183 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2184 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2186 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2187 "comiss", SSEPackedSingle>, TB;
2188 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2189 "comisd", SSEPackedDouble>, TB, OpSize;
2190 } // Defs = [EFLAGS]
2192 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
2193 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2194 Intrinsic Int, string asm, string asm_alt,
2196 let isAsmParserOnly = 1 in {
2197 def rri : PIi8<0xC2, MRMSrcReg,
2198 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2199 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], d>;
2200 def rmi : PIi8<0xC2, MRMSrcMem,
2201 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, SSECC:$cc), asm,
2202 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))], d>;
2205 // Accept explicit immediate argument form instead of comparison code.
2206 def rri_alt : PIi8<0xC2, MRMSrcReg,
2207 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2209 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2210 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, i8imm:$cc),
2214 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2215 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2216 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2217 SSEPackedSingle>, TB, VEX_4V;
2218 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2219 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2220 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2221 SSEPackedDouble>, TB, OpSize, VEX_4V;
2222 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
2223 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2224 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2225 SSEPackedSingle>, TB, VEX_4V;
2226 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
2227 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2228 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2229 SSEPackedDouble>, TB, OpSize, VEX_4V;
2230 let Constraints = "$src1 = $dst" in {
2231 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2232 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2233 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2234 SSEPackedSingle>, TB;
2235 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2236 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2237 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2238 SSEPackedDouble>, TB, OpSize;
2241 let Predicates = [HasAVX] in {
2242 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2243 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2244 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2245 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2246 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2247 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2248 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2249 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2251 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2252 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2253 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2254 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2255 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2256 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2257 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2258 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2261 let Predicates = [HasSSE1] in {
2262 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2263 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2264 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2265 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2268 let Predicates = [HasSSE2] in {
2269 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2270 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2271 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2272 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2275 //===----------------------------------------------------------------------===//
2276 // SSE 1 & 2 - Shuffle Instructions
2277 //===----------------------------------------------------------------------===//
2279 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2280 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2281 ValueType vt, string asm, PatFrag mem_frag,
2282 Domain d, bit IsConvertibleToThreeAddress = 0> {
2283 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2284 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
2285 [(set RC:$dst, (vt (shufp:$src3
2286 RC:$src1, (mem_frag addr:$src2))))], d>;
2287 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2288 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2289 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2291 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
2294 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2295 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2296 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2297 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2298 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2299 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2300 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2301 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2302 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2303 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2304 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2305 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2307 let Constraints = "$src1 = $dst" in {
2308 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2309 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2310 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2312 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2313 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2314 memopv2f64, SSEPackedDouble>, TB, OpSize;
2317 let Predicates = [HasAVX] in {
2318 def : Pat<(v4f32 (X86Shufp VR128:$src1,
2319 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2320 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2321 def : Pat<(v4f32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2322 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2323 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2324 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2325 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2326 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2327 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2328 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2329 // fall back to this for SSE1)
2330 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2331 (VSHUFPSrri VR128:$src2, VR128:$src1,
2332 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2333 // Special unary SHUFPSrri case.
2334 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2335 (VSHUFPSrri VR128:$src1, VR128:$src1,
2336 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2337 // Special binary v4i32 shuffle cases with SHUFPS.
2338 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2339 (VSHUFPSrri VR128:$src1, VR128:$src2,
2340 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2341 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2342 (bc_v4i32 (memopv2i64 addr:$src2)))),
2343 (VSHUFPSrmi VR128:$src1, addr:$src2,
2344 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2345 // Special unary SHUFPDrri cases.
2346 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2347 (VSHUFPDrri VR128:$src1, VR128:$src1,
2348 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2349 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2350 (VSHUFPDrri VR128:$src1, VR128:$src1,
2351 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2352 // Special binary v2i64 shuffle cases using SHUFPDrri.
2353 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2354 (VSHUFPDrri VR128:$src1, VR128:$src2,
2355 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2357 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2358 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2359 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2360 def : Pat<(v2f64 (X86Shufp VR128:$src1,
2361 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2362 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2363 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2364 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2365 def : Pat<(v2f64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2366 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2369 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2370 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2371 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2372 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2373 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2375 def : Pat<(v8f32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2376 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2377 def : Pat<(v8f32 (X86Shufp VR256:$src1,
2378 (memopv8f32 addr:$src2), (i8 imm:$imm))),
2379 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2381 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2382 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2383 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2384 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2385 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2387 def : Pat<(v4f64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2388 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2389 def : Pat<(v4f64 (X86Shufp VR256:$src1,
2390 (memopv4f64 addr:$src2), (i8 imm:$imm))),
2391 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2394 let Predicates = [HasSSE1] in {
2395 def : Pat<(v4f32 (X86Shufp VR128:$src1,
2396 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2397 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2398 def : Pat<(v4f32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2399 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2400 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2401 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2402 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2403 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2404 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2405 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2406 // fall back to this for SSE1)
2407 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2408 (SHUFPSrri VR128:$src2, VR128:$src1,
2409 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2410 // Special unary SHUFPSrri case.
2411 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2412 (SHUFPSrri VR128:$src1, VR128:$src1,
2413 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2416 let Predicates = [HasSSE2] in {
2417 // Special binary v4i32 shuffle cases with SHUFPS.
2418 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2419 (SHUFPSrri VR128:$src1, VR128:$src2,
2420 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2421 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2422 (bc_v4i32 (memopv2i64 addr:$src2)))),
2423 (SHUFPSrmi VR128:$src1, addr:$src2,
2424 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2425 // Special unary SHUFPDrri cases.
2426 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2427 (SHUFPDrri VR128:$src1, VR128:$src1,
2428 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2429 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2430 (SHUFPDrri VR128:$src1, VR128:$src1,
2431 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2432 // Special binary v2i64 shuffle cases using SHUFPDrri.
2433 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2434 (SHUFPDrri VR128:$src1, VR128:$src2,
2435 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2436 // Generic SHUFPD patterns
2437 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2438 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2439 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2440 def : Pat<(v2f64 (X86Shufp VR128:$src1,
2441 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2442 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2443 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2444 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2445 def : Pat<(v2f64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2446 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2449 //===----------------------------------------------------------------------===//
2450 // SSE 1 & 2 - Unpack Instructions
2451 //===----------------------------------------------------------------------===//
2453 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2454 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
2455 PatFrag mem_frag, RegisterClass RC,
2456 X86MemOperand x86memop, string asm,
2458 def rr : PI<opc, MRMSrcReg,
2459 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2461 (vt (OpNode RC:$src1, RC:$src2)))], d>;
2462 def rm : PI<opc, MRMSrcMem,
2463 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2465 (vt (OpNode RC:$src1,
2466 (mem_frag addr:$src2))))], d>;
2469 let AddedComplexity = 10 in {
2470 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2471 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2472 SSEPackedSingle>, TB, VEX_4V;
2473 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2474 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2475 SSEPackedDouble>, TB, OpSize, VEX_4V;
2476 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2477 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2478 SSEPackedSingle>, TB, VEX_4V;
2479 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2480 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2481 SSEPackedDouble>, TB, OpSize, VEX_4V;
2483 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
2484 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2485 SSEPackedSingle>, TB, VEX_4V;
2486 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
2487 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2488 SSEPackedDouble>, TB, OpSize, VEX_4V;
2489 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
2490 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2491 SSEPackedSingle>, TB, VEX_4V;
2492 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
2493 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2494 SSEPackedDouble>, TB, OpSize, VEX_4V;
2496 let Constraints = "$src1 = $dst" in {
2497 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2498 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2499 SSEPackedSingle>, TB;
2500 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2501 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2502 SSEPackedDouble>, TB, OpSize;
2503 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2504 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2505 SSEPackedSingle>, TB;
2506 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2507 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2508 SSEPackedDouble>, TB, OpSize;
2509 } // Constraints = "$src1 = $dst"
2510 } // AddedComplexity
2512 let Predicates = [HasSSE1] in {
2513 def : Pat<(v4f32 (X86Unpckl VR128:$src1, (memopv4f32 addr:$src2))),
2514 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
2515 def : Pat<(v4f32 (X86Unpckl VR128:$src1, VR128:$src2)),
2516 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
2517 def : Pat<(v4f32 (X86Unpckh VR128:$src1, (memopv4f32 addr:$src2))),
2518 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
2519 def : Pat<(v4f32 (X86Unpckh VR128:$src1, VR128:$src2)),
2520 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
2523 let Predicates = [HasSSE2] in {
2524 def : Pat<(v2f64 (X86Unpckl VR128:$src1, (memopv2f64 addr:$src2))),
2525 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
2526 def : Pat<(v2f64 (X86Unpckl VR128:$src1, VR128:$src2)),
2527 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
2528 def : Pat<(v2f64 (X86Unpckh VR128:$src1, (memopv2f64 addr:$src2))),
2529 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
2530 def : Pat<(v2f64 (X86Unpckh VR128:$src1, VR128:$src2)),
2531 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
2533 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2534 // problem is during lowering, where it's not possible to recognize the load
2535 // fold cause it has two uses through a bitcast. One use disappears at isel
2536 // time and the fold opportunity reappears.
2537 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2538 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2540 let AddedComplexity = 10 in
2541 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2542 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2545 let Predicates = [HasAVX] in {
2546 def : Pat<(v4f32 (X86Unpckl VR128:$src1, (memopv4f32 addr:$src2))),
2547 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
2548 def : Pat<(v4f32 (X86Unpckl VR128:$src1, VR128:$src2)),
2549 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
2550 def : Pat<(v4f32 (X86Unpckh VR128:$src1, (memopv4f32 addr:$src2))),
2551 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
2552 def : Pat<(v4f32 (X86Unpckh VR128:$src1, VR128:$src2)),
2553 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
2555 def : Pat<(v8f32 (X86Unpckl VR256:$src1, (memopv8f32 addr:$src2))),
2556 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2557 def : Pat<(v8f32 (X86Unpckl VR256:$src1, VR256:$src2)),
2558 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2559 def : Pat<(v8f32 (X86Unpckh VR256:$src1, (memopv8f32 addr:$src2))),
2560 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2561 def : Pat<(v8f32 (X86Unpckh VR256:$src1, VR256:$src2)),
2562 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2564 def : Pat<(v2f64 (X86Unpckl VR128:$src1, (memopv2f64 addr:$src2))),
2565 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
2566 def : Pat<(v2f64 (X86Unpckl VR128:$src1, VR128:$src2)),
2567 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
2568 def : Pat<(v2f64 (X86Unpckh VR128:$src1, (memopv2f64 addr:$src2))),
2569 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
2570 def : Pat<(v2f64 (X86Unpckh VR128:$src1, VR128:$src2)),
2571 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
2573 def : Pat<(v4f64 (X86Unpckl VR256:$src1, (memopv4f64 addr:$src2))),
2574 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2575 def : Pat<(v4f64 (X86Unpckl VR256:$src1, VR256:$src2)),
2576 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2577 def : Pat<(v4f64 (X86Unpckh VR256:$src1, (memopv4f64 addr:$src2))),
2578 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2579 def : Pat<(v4f64 (X86Unpckh VR256:$src1, VR256:$src2)),
2580 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2582 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2583 // problem is during lowering, where it's not possible to recognize the load
2584 // fold cause it has two uses through a bitcast. One use disappears at isel
2585 // time and the fold opportunity reappears.
2586 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2587 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2588 let AddedComplexity = 10 in
2589 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2590 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2593 //===----------------------------------------------------------------------===//
2594 // SSE 1 & 2 - Extract Floating-Point Sign mask
2595 //===----------------------------------------------------------------------===//
2597 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2598 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2600 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2601 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2602 [(set GR32:$dst, (Int RC:$src))], d>;
2603 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2604 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
2607 let Predicates = [HasAVX] in {
2608 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2609 "movmskps", SSEPackedSingle>, TB, VEX;
2610 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2611 "movmskpd", SSEPackedDouble>, TB,
2613 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2614 "movmskps", SSEPackedSingle>, TB, VEX;
2615 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2616 "movmskpd", SSEPackedDouble>, TB,
2619 def : Pat<(i32 (X86fgetsign FR32:$src)),
2620 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2622 def : Pat<(i64 (X86fgetsign FR32:$src)),
2623 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2625 def : Pat<(i32 (X86fgetsign FR64:$src)),
2626 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2628 def : Pat<(i64 (X86fgetsign FR64:$src)),
2629 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2633 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2634 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2635 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2636 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2638 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2639 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2640 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2641 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2645 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2646 SSEPackedSingle>, TB;
2647 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2648 SSEPackedDouble>, TB, OpSize;
2650 def : Pat<(i32 (X86fgetsign FR32:$src)),
2651 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2652 sub_ss))>, Requires<[HasSSE1]>;
2653 def : Pat<(i64 (X86fgetsign FR32:$src)),
2654 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2655 sub_ss))>, Requires<[HasSSE1]>;
2656 def : Pat<(i32 (X86fgetsign FR64:$src)),
2657 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2658 sub_sd))>, Requires<[HasSSE2]>;
2659 def : Pat<(i64 (X86fgetsign FR64:$src)),
2660 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2661 sub_sd))>, Requires<[HasSSE2]>;
2663 //===---------------------------------------------------------------------===//
2664 // SSE2 - Packed Integer Logical Instructions
2665 //===---------------------------------------------------------------------===//
2667 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2669 /// PDI_binop_rm - Simple SSE2 binary operator.
2670 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2671 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2672 X86MemOperand x86memop, bit IsCommutable = 0,
2674 let isCommutable = IsCommutable in
2675 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2676 (ins RC:$src1, RC:$src2),
2678 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2679 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2680 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
2681 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2682 (ins RC:$src1, x86memop:$src2),
2684 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2685 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2686 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2687 (bitconvert (memop_frag addr:$src2)))))]>;
2689 } // ExeDomain = SSEPackedInt
2691 // These are ordered here for pattern ordering requirements with the fp versions
2693 let Predicates = [HasAVX] in {
2694 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2695 i128mem, 1, 0>, VEX_4V;
2696 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2697 i128mem, 1, 0>, VEX_4V;
2698 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2699 i128mem, 1, 0>, VEX_4V;
2700 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2701 i128mem, 0, 0>, VEX_4V;
2704 let Constraints = "$src1 = $dst" in {
2705 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2707 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2709 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2711 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2713 } // Constraints = "$src1 = $dst"
2715 let Predicates = [HasAVX2] in {
2716 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2717 i256mem, 1, 0>, VEX_4V;
2718 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2719 i256mem, 1, 0>, VEX_4V;
2720 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2721 i256mem, 1, 0>, VEX_4V;
2722 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2723 i256mem, 0, 0>, VEX_4V;
2726 //===----------------------------------------------------------------------===//
2727 // SSE 1 & 2 - Logical Instructions
2728 //===----------------------------------------------------------------------===//
2730 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2732 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2734 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2735 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2737 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2738 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2740 let Constraints = "$src1 = $dst" in {
2741 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2742 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2744 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2745 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2749 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2750 let mayLoad = 0 in {
2751 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2752 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2753 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2756 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2757 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2759 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2761 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2763 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2764 // are all promoted to v2i64, and the patterns are covered by the int
2765 // version. This is needed in SSE only, because v2i64 isn't supported on
2766 // SSE1, but only on SSE2.
2767 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2768 !strconcat(OpcodeStr, "ps"), f128mem, [],
2769 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2770 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2772 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2773 !strconcat(OpcodeStr, "pd"), f128mem,
2774 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2775 (bc_v2i64 (v2f64 VR128:$src2))))],
2776 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2777 (memopv2i64 addr:$src2)))], 0>,
2779 let Constraints = "$src1 = $dst" in {
2780 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2781 !strconcat(OpcodeStr, "ps"), f128mem,
2782 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2783 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2784 (memopv2i64 addr:$src2)))]>, TB;
2786 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2787 !strconcat(OpcodeStr, "pd"), f128mem,
2788 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2789 (bc_v2i64 (v2f64 VR128:$src2))))],
2790 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2791 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2795 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2797 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2799 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2800 !strconcat(OpcodeStr, "ps"), f256mem,
2801 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2802 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2803 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2805 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2806 !strconcat(OpcodeStr, "pd"), f256mem,
2807 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2808 (bc_v4i64 (v4f64 VR256:$src2))))],
2809 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2810 (memopv4i64 addr:$src2)))], 0>,
2814 // AVX 256-bit packed logical ops forms
2815 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2816 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2817 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2818 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2820 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2821 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2822 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2823 let isCommutable = 0 in
2824 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2826 //===----------------------------------------------------------------------===//
2827 // SSE 1 & 2 - Arithmetic Instructions
2828 //===----------------------------------------------------------------------===//
2830 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2833 /// In addition, we also have a special variant of the scalar form here to
2834 /// represent the associated intrinsic operation. This form is unlike the
2835 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2836 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2838 /// These three forms can each be reg+reg or reg+mem.
2841 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2843 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2845 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2846 OpNode, FR32, f32mem, Is2Addr>, XS;
2847 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2848 OpNode, FR64, f64mem, Is2Addr>, XD;
2851 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2853 let mayLoad = 0 in {
2854 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2855 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2856 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2857 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2861 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2863 let mayLoad = 0 in {
2864 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2865 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2866 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2867 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2871 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2873 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2874 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2875 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2876 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2879 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2881 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2882 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2883 SSEPackedSingle, Is2Addr>, TB;
2885 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2886 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2887 SSEPackedDouble, Is2Addr>, TB, OpSize;
2890 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2891 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2892 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2893 SSEPackedSingle, 0>, TB;
2895 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2896 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2897 SSEPackedDouble, 0>, TB, OpSize;
2900 // Binary Arithmetic instructions
2901 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2902 basic_sse12_fp_binop_s_int<0x58, "add", 0>, VEX_4V, VEX_LIG;
2903 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2904 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2905 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2906 basic_sse12_fp_binop_s_int<0x59, "mul", 0>, VEX_4V, VEX_LIG;
2907 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2908 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2910 let isCommutable = 0 in {
2911 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2912 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>, VEX_4V, VEX_LIG;
2913 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2914 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2915 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2916 basic_sse12_fp_binop_s_int<0x5E, "div", 0>, VEX_4V, VEX_LIG;
2917 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2918 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2919 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2920 basic_sse12_fp_binop_s_int<0x5F, "max", 0>, VEX_4V, VEX_LIG;
2921 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2922 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2923 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2924 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2925 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2926 basic_sse12_fp_binop_s_int<0x5D, "min", 0>, VEX_4V, VEX_LIG;
2927 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2928 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2929 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2930 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2933 let Constraints = "$src1 = $dst" in {
2934 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2935 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2936 basic_sse12_fp_binop_s_int<0x58, "add">;
2937 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2938 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2939 basic_sse12_fp_binop_s_int<0x59, "mul">;
2941 let isCommutable = 0 in {
2942 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2943 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2944 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2945 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2946 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2947 basic_sse12_fp_binop_s_int<0x5E, "div">;
2948 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2949 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2950 basic_sse12_fp_binop_s_int<0x5F, "max">,
2951 basic_sse12_fp_binop_p_int<0x5F, "max">;
2952 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2953 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2954 basic_sse12_fp_binop_s_int<0x5D, "min">,
2955 basic_sse12_fp_binop_p_int<0x5D, "min">;
2960 /// In addition, we also have a special variant of the scalar form here to
2961 /// represent the associated intrinsic operation. This form is unlike the
2962 /// plain scalar form, in that it takes an entire vector (instead of a
2963 /// scalar) and leaves the top elements undefined.
2965 /// And, we have a special variant form for a full-vector intrinsic form.
2967 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2968 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2969 SDNode OpNode, Intrinsic F32Int> {
2970 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2971 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2972 [(set FR32:$dst, (OpNode FR32:$src))]>;
2973 // For scalar unary operations, fold a load into the operation
2974 // only in OptForSize mode. It eliminates an instruction, but it also
2975 // eliminates a whole-register clobber (the load), so it introduces a
2976 // partial register update condition.
2977 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2978 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2979 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2980 Requires<[HasSSE1, OptForSize]>;
2981 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2982 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2983 [(set VR128:$dst, (F32Int VR128:$src))]>;
2984 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2985 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2986 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2989 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2990 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2991 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2992 !strconcat(OpcodeStr,
2993 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2995 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2996 !strconcat(OpcodeStr,
2997 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2998 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2999 (ins VR128:$src1, ssmem:$src2),
3000 !strconcat(OpcodeStr,
3001 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3004 /// sse1_fp_unop_p - SSE1 unops in packed form.
3005 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3006 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3007 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3008 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
3009 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3010 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3011 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
3014 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3015 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3016 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3017 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3018 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
3019 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3020 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3021 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
3024 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3025 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3026 Intrinsic V4F32Int> {
3027 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3028 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3029 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
3030 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3031 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3032 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
3035 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3036 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3037 Intrinsic V4F32Int> {
3038 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3039 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3040 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
3041 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3042 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3043 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
3046 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3047 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3048 SDNode OpNode, Intrinsic F64Int> {
3049 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3050 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3051 [(set FR64:$dst, (OpNode FR64:$src))]>;
3052 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3053 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3054 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3055 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
3056 Requires<[HasSSE2, OptForSize]>;
3057 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3058 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3059 [(set VR128:$dst, (F64Int VR128:$src))]>;
3060 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3061 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3062 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
3065 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3066 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3067 let neverHasSideEffects = 1 in {
3068 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3069 !strconcat(OpcodeStr,
3070 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3072 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3073 !strconcat(OpcodeStr,
3074 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3076 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3077 (ins VR128:$src1, sdmem:$src2),
3078 !strconcat(OpcodeStr,
3079 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3082 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3083 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3085 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3086 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3087 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
3088 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3089 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3090 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
3093 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3094 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
3095 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3096 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3097 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
3098 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3099 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3100 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
3103 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3104 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3105 Intrinsic V2F64Int> {
3106 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3107 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3108 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
3109 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3110 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3111 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
3114 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3115 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3116 Intrinsic V2F64Int> {
3117 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3118 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3119 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
3120 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3121 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3122 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
3125 let Predicates = [HasAVX] in {
3127 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3128 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3130 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
3131 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
3132 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
3133 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
3134 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
3135 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
3136 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
3137 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
3140 // Reciprocal approximations. Note that these typically require refinement
3141 // in order to obtain suitable precision.
3142 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3143 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
3144 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
3145 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
3146 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
3148 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3149 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
3150 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
3151 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
3152 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
3155 let AddedComplexity = 1 in {
3156 def : Pat<(f32 (fsqrt FR32:$src)),
3157 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3158 def : Pat<(f32 (fsqrt (load addr:$src))),
3159 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3160 Requires<[HasAVX, OptForSize]>;
3161 def : Pat<(f64 (fsqrt FR64:$src)),
3162 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3163 def : Pat<(f64 (fsqrt (load addr:$src))),
3164 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3165 Requires<[HasAVX, OptForSize]>;
3167 def : Pat<(f32 (X86frsqrt FR32:$src)),
3168 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3169 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3170 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3171 Requires<[HasAVX, OptForSize]>;
3173 def : Pat<(f32 (X86frcp FR32:$src)),
3174 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3175 def : Pat<(f32 (X86frcp (load addr:$src))),
3176 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3177 Requires<[HasAVX, OptForSize]>;
3180 let Predicates = [HasAVX], AddedComplexity = 1 in {
3181 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3182 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3183 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3184 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3186 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3187 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3189 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3190 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3191 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3192 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3194 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3195 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3197 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3198 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3199 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3200 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3202 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3203 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3205 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3206 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3207 (VRCPSSr (f32 (IMPLICIT_DEF)),
3208 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3210 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3211 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3215 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
3216 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
3217 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
3218 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
3219 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
3220 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
3222 // Reciprocal approximations. Note that these typically require refinement
3223 // in order to obtain suitable precision.
3224 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
3225 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
3226 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
3227 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
3228 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
3229 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
3231 // There is no f64 version of the reciprocal approximation instructions.
3233 //===----------------------------------------------------------------------===//
3234 // SSE 1 & 2 - Non-temporal stores
3235 //===----------------------------------------------------------------------===//
3237 let AddedComplexity = 400 in { // Prefer non-temporal versions
3238 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3239 (ins f128mem:$dst, VR128:$src),
3240 "movntps\t{$src, $dst|$dst, $src}",
3241 [(alignednontemporalstore (v4f32 VR128:$src),
3243 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3244 (ins f128mem:$dst, VR128:$src),
3245 "movntpd\t{$src, $dst|$dst, $src}",
3246 [(alignednontemporalstore (v2f64 VR128:$src),
3249 let ExeDomain = SSEPackedInt in
3250 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3251 (ins f128mem:$dst, VR128:$src),
3252 "movntdq\t{$src, $dst|$dst, $src}",
3253 [(alignednontemporalstore (v2i64 VR128:$src),
3256 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3257 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3259 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3260 (ins f256mem:$dst, VR256:$src),
3261 "movntps\t{$src, $dst|$dst, $src}",
3262 [(alignednontemporalstore (v8f32 VR256:$src),
3264 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3265 (ins f256mem:$dst, VR256:$src),
3266 "movntpd\t{$src, $dst|$dst, $src}",
3267 [(alignednontemporalstore (v4f64 VR256:$src),
3269 let ExeDomain = SSEPackedInt in
3270 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3271 (ins f256mem:$dst, VR256:$src),
3272 "movntdq\t{$src, $dst|$dst, $src}",
3273 [(alignednontemporalstore (v4i64 VR256:$src),
3277 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
3278 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3279 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
3280 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
3281 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
3282 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
3284 let AddedComplexity = 400 in { // Prefer non-temporal versions
3285 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3286 "movntps\t{$src, $dst|$dst, $src}",
3287 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3288 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3289 "movntpd\t{$src, $dst|$dst, $src}",
3290 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
3292 let ExeDomain = SSEPackedInt in
3293 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3294 "movntdq\t{$src, $dst|$dst, $src}",
3295 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)]>;
3297 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3298 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3300 // There is no AVX form for instructions below this point
3301 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3302 "movnti{l}\t{$src, $dst|$dst, $src}",
3303 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
3304 TB, Requires<[HasSSE2]>;
3305 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3306 "movnti{q}\t{$src, $dst|$dst, $src}",
3307 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
3308 TB, Requires<[HasSSE2]>;
3311 //===----------------------------------------------------------------------===//
3312 // SSE 1 & 2 - Prefetch and memory fence
3313 //===----------------------------------------------------------------------===//
3315 // Prefetch intrinsic.
3316 let Predicates = [HasSSE1] in {
3317 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3318 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>, TB;
3319 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3320 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>, TB;
3321 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3322 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>, TB;
3323 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3324 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>, TB;
3328 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3329 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3330 TB, Requires<[HasSSE2]>;
3332 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3333 // was introduced with SSE2, it's backward compatible.
3334 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3336 // Load, store, and memory fence
3337 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3338 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
3339 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3340 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3341 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3342 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3344 def : Pat<(X86SFence), (SFENCE)>;
3345 def : Pat<(X86LFence), (LFENCE)>;
3346 def : Pat<(X86MFence), (MFENCE)>;
3348 //===----------------------------------------------------------------------===//
3349 // SSE 1 & 2 - Load/Store XCSR register
3350 //===----------------------------------------------------------------------===//
3352 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3353 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
3354 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3355 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
3357 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3358 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
3359 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3360 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
3362 //===---------------------------------------------------------------------===//
3363 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3364 //===---------------------------------------------------------------------===//
3366 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3368 let neverHasSideEffects = 1 in {
3369 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3370 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3371 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3372 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3374 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3375 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3376 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3377 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3380 let isCodeGenOnly = 1 in {
3381 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3382 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3383 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3384 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3385 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3386 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3387 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3388 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3391 let canFoldAsLoad = 1, mayLoad = 1 in {
3392 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3393 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3394 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3395 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3396 let Predicates = [HasAVX] in {
3397 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3398 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3399 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3400 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3404 let mayStore = 1 in {
3405 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3406 (ins i128mem:$dst, VR128:$src),
3407 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3408 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3409 (ins i256mem:$dst, VR256:$src),
3410 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3411 let Predicates = [HasAVX] in {
3412 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3413 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3414 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3415 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3419 let neverHasSideEffects = 1 in
3420 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3421 "movdqa\t{$src, $dst|$dst, $src}", []>;
3423 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3424 "movdqu\t{$src, $dst|$dst, $src}",
3425 []>, XS, Requires<[HasSSE2]>;
3428 let isCodeGenOnly = 1 in {
3429 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3430 "movdqa\t{$src, $dst|$dst, $src}", []>;
3432 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3433 "movdqu\t{$src, $dst|$dst, $src}",
3434 []>, XS, Requires<[HasSSE2]>;
3437 let canFoldAsLoad = 1, mayLoad = 1 in {
3438 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3439 "movdqa\t{$src, $dst|$dst, $src}",
3440 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
3441 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3442 "movdqu\t{$src, $dst|$dst, $src}",
3443 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
3444 XS, Requires<[HasSSE2]>;
3447 let mayStore = 1 in {
3448 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3449 "movdqa\t{$src, $dst|$dst, $src}",
3450 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
3451 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3452 "movdqu\t{$src, $dst|$dst, $src}",
3453 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
3454 XS, Requires<[HasSSE2]>;
3457 // Intrinsic forms of MOVDQU load and store
3458 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3459 "vmovdqu\t{$src, $dst|$dst, $src}",
3460 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3461 XS, VEX, Requires<[HasAVX]>;
3463 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3464 "movdqu\t{$src, $dst|$dst, $src}",
3465 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3466 XS, Requires<[HasSSE2]>;
3468 } // ExeDomain = SSEPackedInt
3470 let Predicates = [HasAVX] in {
3471 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
3472 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3473 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3476 //===---------------------------------------------------------------------===//
3477 // SSE2 - Packed Integer Arithmetic Instructions
3478 //===---------------------------------------------------------------------===//
3480 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3482 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3483 RegisterClass RC, PatFrag memop_frag,
3484 X86MemOperand x86memop, bit IsCommutable = 0,
3486 let isCommutable = IsCommutable in
3487 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3488 (ins RC:$src1, RC:$src2),
3490 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3491 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3492 [(set RC:$dst, (IntId RC:$src1, RC:$src2))]>;
3493 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3494 (ins RC:$src1, x86memop:$src2),
3496 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3497 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3498 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))]>;
3501 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
3502 string OpcodeStr, Intrinsic IntId,
3503 Intrinsic IntId2, RegisterClass RC,
3505 // src2 is always 128-bit
3506 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3507 (ins RC:$src1, VR128:$src2),
3509 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3510 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3511 [(set RC:$dst, (IntId RC:$src1, VR128:$src2))]>;
3512 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3513 (ins RC:$src1, i128mem:$src2),
3515 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3516 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3517 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memopv2i64 addr:$src2))))]>;
3518 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3519 (ins RC:$src1, i32i8imm:$src2),
3521 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3522 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3523 [(set RC:$dst, (IntId2 RC:$src1, (i32 imm:$src2)))]>;
3526 } // ExeDomain = SSEPackedInt
3528 // 128-bit Integer Arithmetic
3530 let Predicates = [HasAVX] in {
3531 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3532 i128mem, 1, 0 /*3addr*/>, VEX_4V;
3533 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3534 i128mem, 1, 0>, VEX_4V;
3535 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3536 i128mem, 1, 0>, VEX_4V;
3537 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3538 i128mem, 1, 0>, VEX_4V;
3539 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3540 i128mem, 1, 0>, VEX_4V;
3541 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3542 i128mem, 0, 0>, VEX_4V;
3543 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3544 i128mem, 0, 0>, VEX_4V;
3545 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3546 i128mem, 0, 0>, VEX_4V;
3547 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3548 i128mem, 0, 0>, VEX_4V;
3551 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3552 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3553 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3554 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3555 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3556 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3557 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3558 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3559 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3560 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3561 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3562 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3563 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3564 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3565 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3566 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3567 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3568 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3569 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3570 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3571 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq,
3572 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3573 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3574 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3575 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3576 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3577 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3578 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3579 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3580 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3581 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3582 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3583 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3584 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3585 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3586 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3587 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3588 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3591 let Predicates = [HasAVX2] in {
3592 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3593 i256mem, 1, 0>, VEX_4V;
3594 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3595 i256mem, 1, 0>, VEX_4V;
3596 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3597 i256mem, 1, 0>, VEX_4V;
3598 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3599 i256mem, 1, 0>, VEX_4V;
3600 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3601 i256mem, 1, 0>, VEX_4V;
3602 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3603 i256mem, 0, 0>, VEX_4V;
3604 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3605 i256mem, 0, 0>, VEX_4V;
3606 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3607 i256mem, 0, 0>, VEX_4V;
3608 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3609 i256mem, 0, 0>, VEX_4V;
3612 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3613 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3614 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3615 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3616 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3617 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3618 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3619 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3620 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3621 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3622 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3623 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3624 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3625 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3626 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3627 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3628 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3629 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3630 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3631 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3632 defm VPMULUDQY : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_avx2_pmulu_dq,
3633 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3634 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3635 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3636 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3637 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3638 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3639 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3640 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3641 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3642 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3643 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3644 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3645 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3646 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3647 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3648 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3649 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3652 let Constraints = "$src1 = $dst" in {
3653 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3655 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3657 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3659 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3661 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3663 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3665 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3667 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3669 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3673 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3674 VR128, memopv2i64, i128mem>;
3675 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3676 VR128, memopv2i64, i128mem>;
3677 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3678 VR128, memopv2i64, i128mem>;
3679 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3680 VR128, memopv2i64, i128mem>;
3681 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3682 VR128, memopv2i64, i128mem, 1>;
3683 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3684 VR128, memopv2i64, i128mem, 1>;
3685 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3686 VR128, memopv2i64, i128mem, 1>;
3687 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3688 VR128, memopv2i64, i128mem, 1>;
3689 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3690 VR128, memopv2i64, i128mem, 1>;
3691 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3692 VR128, memopv2i64, i128mem, 1>;
3693 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq,
3694 VR128, memopv2i64, i128mem, 1>;
3695 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3696 VR128, memopv2i64, i128mem, 1>;
3697 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3698 VR128, memopv2i64, i128mem, 1>;
3699 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3700 VR128, memopv2i64, i128mem, 1>;
3701 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3702 VR128, memopv2i64, i128mem, 1>;
3703 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3704 VR128, memopv2i64, i128mem, 1>;
3705 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3706 VR128, memopv2i64, i128mem, 1>;
3707 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3708 VR128, memopv2i64, i128mem, 1>;
3709 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3710 VR128, memopv2i64, i128mem, 1>;
3712 } // Constraints = "$src1 = $dst"
3714 //===---------------------------------------------------------------------===//
3715 // SSE2 - Packed Integer Logical Instructions
3716 //===---------------------------------------------------------------------===//
3718 let Predicates = [HasAVX] in {
3719 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3720 int_x86_sse2_psll_w, int_x86_sse2_pslli_w,
3722 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3723 int_x86_sse2_psll_d, int_x86_sse2_pslli_d,
3725 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3726 int_x86_sse2_psll_q, int_x86_sse2_pslli_q,
3729 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3730 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w,
3732 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3733 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d,
3735 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3736 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q,
3739 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3740 int_x86_sse2_psra_w, int_x86_sse2_psrai_w,
3742 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3743 int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
3746 let ExeDomain = SSEPackedInt in {
3747 let neverHasSideEffects = 1 in {
3748 // 128-bit logical shifts.
3749 def VPSLLDQri : PDIi8<0x73, MRM7r,
3750 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3751 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3753 def VPSRLDQri : PDIi8<0x73, MRM3r,
3754 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3755 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3757 // PSRADQri doesn't exist in SSE[1-3].
3762 let Predicates = [HasAVX2] in {
3763 defm VPSLLWY : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3764 int_x86_avx2_psll_w, int_x86_avx2_pslli_w,
3766 defm VPSLLDY : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3767 int_x86_avx2_psll_d, int_x86_avx2_pslli_d,
3769 defm VPSLLQY : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3770 int_x86_avx2_psll_q, int_x86_avx2_pslli_q,
3773 defm VPSRLWY : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3774 int_x86_avx2_psrl_w, int_x86_avx2_psrli_w,
3776 defm VPSRLDY : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3777 int_x86_avx2_psrl_d, int_x86_avx2_psrli_d,
3779 defm VPSRLQY : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3780 int_x86_avx2_psrl_q, int_x86_avx2_psrli_q,
3783 defm VPSRAWY : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3784 int_x86_avx2_psra_w, int_x86_avx2_psrai_w,
3786 defm VPSRADY : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3787 int_x86_avx2_psra_d, int_x86_avx2_psrai_d,
3790 let ExeDomain = SSEPackedInt in {
3791 let neverHasSideEffects = 1 in {
3792 // 128-bit logical shifts.
3793 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3794 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3795 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3797 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3798 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3799 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3801 // PSRADQYri doesn't exist in SSE[1-3].
3806 let Constraints = "$src1 = $dst" in {
3807 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
3808 int_x86_sse2_psll_w, int_x86_sse2_pslli_w,
3810 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
3811 int_x86_sse2_psll_d, int_x86_sse2_pslli_d,
3813 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
3814 int_x86_sse2_psll_q, int_x86_sse2_pslli_q,
3817 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
3818 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w,
3820 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
3821 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d,
3823 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
3824 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q,
3827 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
3828 int_x86_sse2_psra_w, int_x86_sse2_psrai_w,
3830 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
3831 int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
3834 let ExeDomain = SSEPackedInt in {
3835 let neverHasSideEffects = 1 in {
3836 // 128-bit logical shifts.
3837 def PSLLDQri : PDIi8<0x73, MRM7r,
3838 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3839 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
3840 def PSRLDQri : PDIi8<0x73, MRM3r,
3841 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3842 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
3843 // PSRADQri doesn't exist in SSE[1-3].
3846 } // Constraints = "$src1 = $dst"
3848 let Predicates = [HasAVX] in {
3849 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3850 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3851 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3852 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3853 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3854 (VPSLLDQri VR128:$src1, imm:$src2)>;
3855 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3856 (VPSRLDQri VR128:$src1, imm:$src2)>;
3857 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3858 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3860 // Shift up / down and insert zero's.
3861 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3862 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3863 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3864 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3867 let Predicates = [HasAVX2] in {
3868 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
3869 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3870 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
3871 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3872 def : Pat<(int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2),
3873 (VPSLLDQYri VR256:$src1, imm:$src2)>;
3874 def : Pat<(int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2),
3875 (VPSRLDQYri VR256:$src1, imm:$src2)>;
3878 let Predicates = [HasSSE2] in {
3879 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3880 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3881 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3882 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3883 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3884 (PSLLDQri VR128:$src1, imm:$src2)>;
3885 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3886 (PSRLDQri VR128:$src1, imm:$src2)>;
3887 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3888 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3890 // Shift up / down and insert zero's.
3891 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3892 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3893 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3894 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3897 //===---------------------------------------------------------------------===//
3898 // SSE2 - Packed Integer Comparison Instructions
3899 //===---------------------------------------------------------------------===//
3901 let Predicates = [HasAVX] in {
3902 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b,
3903 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3904 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w,
3905 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3906 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d,
3907 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3908 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b,
3909 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3910 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w,
3911 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3912 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d,
3913 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3915 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3916 (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
3917 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1,
3918 (bc_v16i8 (memopv2i64 addr:$src2)))),
3919 (VPCMPEQBrm VR128:$src1, addr:$src2)>;
3920 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3921 (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
3922 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1,
3923 (bc_v8i16 (memopv2i64 addr:$src2)))),
3924 (VPCMPEQWrm VR128:$src1, addr:$src2)>;
3925 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3926 (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
3927 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1,
3928 (bc_v4i32 (memopv2i64 addr:$src2)))),
3929 (VPCMPEQDrm VR128:$src1, addr:$src2)>;
3931 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3932 (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
3933 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1,
3934 (bc_v16i8 (memopv2i64 addr:$src2)))),
3935 (VPCMPGTBrm VR128:$src1, addr:$src2)>;
3936 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3937 (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
3938 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1,
3939 (bc_v8i16 (memopv2i64 addr:$src2)))),
3940 (VPCMPGTWrm VR128:$src1, addr:$src2)>;
3941 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3942 (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
3943 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1,
3944 (bc_v4i32 (memopv2i64 addr:$src2)))),
3945 (VPCMPGTDrm VR128:$src1, addr:$src2)>;
3948 let Predicates = [HasAVX2] in {
3949 defm VPCMPEQBY : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_avx2_pcmpeq_b,
3950 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3951 defm VPCMPEQWY : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_avx2_pcmpeq_w,
3952 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3953 defm VPCMPEQDY : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_avx2_pcmpeq_d,
3954 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3955 defm VPCMPGTBY : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_avx2_pcmpgt_b,
3956 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3957 defm VPCMPGTWY : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_avx2_pcmpgt_w,
3958 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3959 defm VPCMPGTDY : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_avx2_pcmpgt_d,
3960 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3962 def : Pat<(v32i8 (X86pcmpeqb VR256:$src1, VR256:$src2)),
3963 (VPCMPEQBYrr VR256:$src1, VR256:$src2)>;
3964 def : Pat<(v32i8 (X86pcmpeqb VR256:$src1,
3965 (bc_v32i8 (memopv4i64 addr:$src2)))),
3966 (VPCMPEQBYrm VR256:$src1, addr:$src2)>;
3967 def : Pat<(v16i16 (X86pcmpeqw VR256:$src1, VR256:$src2)),
3968 (VPCMPEQWYrr VR256:$src1, VR256:$src2)>;
3969 def : Pat<(v16i16 (X86pcmpeqw VR256:$src1,
3970 (bc_v16i16 (memopv4i64 addr:$src2)))),
3971 (VPCMPEQWYrm VR256:$src1, addr:$src2)>;
3972 def : Pat<(v8i32 (X86pcmpeqd VR256:$src1, VR256:$src2)),
3973 (VPCMPEQDYrr VR256:$src1, VR256:$src2)>;
3974 def : Pat<(v8i32 (X86pcmpeqd VR256:$src1,
3975 (bc_v8i32 (memopv4i64 addr:$src2)))),
3976 (VPCMPEQDYrm VR256:$src1, addr:$src2)>;
3978 def : Pat<(v32i8 (X86pcmpgtb VR256:$src1, VR256:$src2)),
3979 (VPCMPGTBYrr VR256:$src1, VR256:$src2)>;
3980 def : Pat<(v32i8 (X86pcmpgtb VR256:$src1,
3981 (bc_v32i8 (memopv4i64 addr:$src2)))),
3982 (VPCMPGTBYrm VR256:$src1, addr:$src2)>;
3983 def : Pat<(v16i16 (X86pcmpgtw VR256:$src1, VR256:$src2)),
3984 (VPCMPGTWYrr VR256:$src1, VR256:$src2)>;
3985 def : Pat<(v16i16 (X86pcmpgtw VR256:$src1,
3986 (bc_v16i16 (memopv4i64 addr:$src2)))),
3987 (VPCMPGTWYrm VR256:$src1, addr:$src2)>;
3988 def : Pat<(v8i32 (X86pcmpgtd VR256:$src1, VR256:$src2)),
3989 (VPCMPGTDYrr VR256:$src1, VR256:$src2)>;
3990 def : Pat<(v8i32 (X86pcmpgtd VR256:$src1,
3991 (bc_v8i32 (memopv4i64 addr:$src2)))),
3992 (VPCMPGTDYrm VR256:$src1, addr:$src2)>;
3995 let Constraints = "$src1 = $dst" in {
3996 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b,
3997 VR128, memopv2i64, i128mem, 1>;
3998 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w,
3999 VR128, memopv2i64, i128mem, 1>;
4000 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d,
4001 VR128, memopv2i64, i128mem, 1>;
4002 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b,
4003 VR128, memopv2i64, i128mem>;
4004 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w,
4005 VR128, memopv2i64, i128mem>;
4006 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d,
4007 VR128, memopv2i64, i128mem>;
4008 } // Constraints = "$src1 = $dst"
4010 let Predicates = [HasSSE2] in {
4011 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
4012 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
4013 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1,
4014 (bc_v16i8 (memopv2i64 addr:$src2)))),
4015 (PCMPEQBrm VR128:$src1, addr:$src2)>;
4016 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
4017 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
4018 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1,
4019 (bc_v8i16 (memopv2i64 addr:$src2)))),
4020 (PCMPEQWrm VR128:$src1, addr:$src2)>;
4021 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
4022 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
4023 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1,
4024 (bc_v4i32 (memopv2i64 addr:$src2)))),
4025 (PCMPEQDrm VR128:$src1, addr:$src2)>;
4027 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
4028 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
4029 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1,
4030 (bc_v16i8 (memopv2i64 addr:$src2)))),
4031 (PCMPGTBrm VR128:$src1, addr:$src2)>;
4032 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
4033 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
4034 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1,
4035 (bc_v8i16 (memopv2i64 addr:$src2)))),
4036 (PCMPGTWrm VR128:$src1, addr:$src2)>;
4037 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
4038 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
4039 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1,
4040 (bc_v4i32 (memopv2i64 addr:$src2)))),
4041 (PCMPGTDrm VR128:$src1, addr:$src2)>;
4044 //===---------------------------------------------------------------------===//
4045 // SSE2 - Packed Integer Pack Instructions
4046 //===---------------------------------------------------------------------===//
4048 let Predicates = [HasAVX] in {
4049 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4050 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
4051 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4052 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
4053 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4054 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
4057 let Predicates = [HasAVX2] in {
4058 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4059 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
4060 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4061 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
4062 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4063 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
4066 let Constraints = "$src1 = $dst" in {
4067 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4068 VR128, memopv2i64, i128mem>;
4069 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4070 VR128, memopv2i64, i128mem>;
4071 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4072 VR128, memopv2i64, i128mem>;
4073 } // Constraints = "$src1 = $dst"
4075 //===---------------------------------------------------------------------===//
4076 // SSE2 - Packed Integer Shuffle Instructions
4077 //===---------------------------------------------------------------------===//
4079 let ExeDomain = SSEPackedInt in {
4080 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
4082 def ri : Ii8<0x70, MRMSrcReg,
4083 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4084 !strconcat(OpcodeStr,
4085 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4086 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
4088 def mi : Ii8<0x70, MRMSrcMem,
4089 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4090 !strconcat(OpcodeStr,
4091 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4092 [(set VR128:$dst, (vt (pshuf_frag:$src2
4093 (bc_frag (memopv2i64 addr:$src1)),
4097 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
4099 def Yri : Ii8<0x70, MRMSrcReg,
4100 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4101 !strconcat(OpcodeStr,
4102 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4103 [(set VR256:$dst, (vt (pshuf_frag:$src2 VR256:$src1,
4105 def Ymi : Ii8<0x70, MRMSrcMem,
4106 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4107 !strconcat(OpcodeStr,
4108 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4109 [(set VR256:$dst, (vt (pshuf_frag:$src2
4110 (bc_frag (memopv4i64 addr:$src1)),
4113 } // ExeDomain = SSEPackedInt
4115 let Predicates = [HasAVX] in {
4116 let AddedComplexity = 5 in
4117 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
4120 // SSE2 with ImmT == Imm8 and XS prefix.
4121 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
4124 // SSE2 with ImmT == Imm8 and XD prefix.
4125 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
4128 let AddedComplexity = 5 in
4129 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
4130 (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4131 // Unary v4f32 shuffle with VPSHUF* in order to fold a load.
4132 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
4133 (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4135 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
4137 (VPSHUFDmi addr:$src1, imm:$imm)>;
4138 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
4140 (VPSHUFDmi addr:$src1, imm:$imm)>;
4141 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4142 (VPSHUFDri VR128:$src1, imm:$imm)>;
4143 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4144 (VPSHUFDri VR128:$src1, imm:$imm)>;
4145 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
4146 (VPSHUFHWri VR128:$src, imm:$imm)>;
4147 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
4149 (VPSHUFHWmi addr:$src, imm:$imm)>;
4150 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
4151 (VPSHUFLWri VR128:$src, imm:$imm)>;
4152 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
4154 (VPSHUFLWmi addr:$src, imm:$imm)>;
4157 let Predicates = [HasAVX2] in {
4158 let AddedComplexity = 5 in
4159 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, pshufd, bc_v8i32>, TB,
4162 // SSE2 with ImmT == Imm8 and XS prefix.
4163 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, pshufhw, bc_v16i16>, XS,
4166 // SSE2 with ImmT == Imm8 and XD prefix.
4167 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, pshuflw, bc_v16i16>, XD,
4171 let Predicates = [HasSSE2] in {
4172 let AddedComplexity = 5 in
4173 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
4175 // SSE2 with ImmT == Imm8 and XS prefix.
4176 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
4178 // SSE2 with ImmT == Imm8 and XD prefix.
4179 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
4181 let AddedComplexity = 5 in
4182 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
4183 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4184 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
4185 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
4186 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4188 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
4190 (PSHUFDmi addr:$src1, imm:$imm)>;
4191 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
4193 (PSHUFDmi addr:$src1, imm:$imm)>;
4194 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4195 (PSHUFDri VR128:$src1, imm:$imm)>;
4196 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4197 (PSHUFDri VR128:$src1, imm:$imm)>;
4198 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
4199 (PSHUFHWri VR128:$src, imm:$imm)>;
4200 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
4202 (PSHUFHWmi addr:$src, imm:$imm)>;
4203 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
4204 (PSHUFLWri VR128:$src, imm:$imm)>;
4205 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
4207 (PSHUFLWmi addr:$src, imm:$imm)>;
4210 //===---------------------------------------------------------------------===//
4211 // SSE2 - Packed Integer Unpack Instructions
4212 //===---------------------------------------------------------------------===//
4214 let ExeDomain = SSEPackedInt in {
4215 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4216 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4217 def rr : PDI<opc, MRMSrcReg,
4218 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4220 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4221 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4222 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
4223 def rm : PDI<opc, MRMSrcMem,
4224 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4226 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4227 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4228 [(set VR128:$dst, (OpNode VR128:$src1,
4229 (bc_frag (memopv2i64
4233 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4234 SDNode OpNode, PatFrag bc_frag> {
4235 def Yrr : PDI<opc, MRMSrcReg,
4236 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4237 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4238 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4239 def Yrm : PDI<opc, MRMSrcMem,
4240 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4241 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4242 [(set VR256:$dst, (OpNode VR256:$src1,
4243 (bc_frag (memopv4i64 addr:$src2))))]>;
4246 let Predicates = [HasAVX] in {
4247 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4248 bc_v16i8, 0>, VEX_4V;
4249 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4250 bc_v8i16, 0>, VEX_4V;
4251 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4252 bc_v4i32, 0>, VEX_4V;
4253 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4254 bc_v2i64, 0>, VEX_4V;
4256 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4257 bc_v16i8, 0>, VEX_4V;
4258 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4259 bc_v8i16, 0>, VEX_4V;
4260 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4261 bc_v4i32, 0>, VEX_4V;
4262 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4263 bc_v2i64, 0>, VEX_4V;
4266 let Predicates = [HasAVX2] in {
4267 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4269 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4271 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4273 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4276 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4278 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4280 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4282 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4286 let Constraints = "$src1 = $dst" in {
4287 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4289 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4291 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4293 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4296 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4298 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4300 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4302 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4305 } // ExeDomain = SSEPackedInt
4307 // Patterns for using AVX1 instructions with integer vectors
4308 // Here to give AVX2 priority
4309 let Predicates = [HasAVX] in {
4310 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4311 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
4312 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
4313 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
4314 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4315 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
4316 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
4317 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
4319 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
4320 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
4321 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
4322 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
4323 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
4324 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
4325 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
4326 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
4329 // Splat v2f64 / v2i64
4330 let AddedComplexity = 10 in {
4331 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
4332 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
4333 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
4334 (VPUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasAVX]>;
4337 //===---------------------------------------------------------------------===//
4338 // SSE2 - Packed Integer Extract and Insert
4339 //===---------------------------------------------------------------------===//
4341 let ExeDomain = SSEPackedInt in {
4342 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4343 def rri : Ii8<0xC4, MRMSrcReg,
4344 (outs VR128:$dst), (ins VR128:$src1,
4345 GR32:$src2, i32i8imm:$src3),
4347 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4348 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4350 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
4351 def rmi : Ii8<0xC4, MRMSrcMem,
4352 (outs VR128:$dst), (ins VR128:$src1,
4353 i16mem:$src2, i32i8imm:$src3),
4355 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4356 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4358 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4363 let Predicates = [HasAVX] in
4364 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4365 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4366 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4367 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4368 imm:$src2))]>, TB, OpSize, VEX;
4369 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4370 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4371 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4372 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4376 let Predicates = [HasAVX] in {
4377 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4378 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4379 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4380 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4381 []>, TB, OpSize, VEX_4V;
4384 let Constraints = "$src1 = $dst" in
4385 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4387 } // ExeDomain = SSEPackedInt
4389 //===---------------------------------------------------------------------===//
4390 // SSE2 - Packed Mask Creation
4391 //===---------------------------------------------------------------------===//
4393 let ExeDomain = SSEPackedInt in {
4395 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4396 "pmovmskb\t{$src, $dst|$dst, $src}",
4397 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
4398 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4399 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4401 let Predicates = [HasAVX2] in {
4402 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4403 "pmovmskb\t{$src, $dst|$dst, $src}",
4404 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4405 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4406 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4409 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4410 "pmovmskb\t{$src, $dst|$dst, $src}",
4411 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
4413 } // ExeDomain = SSEPackedInt
4415 //===---------------------------------------------------------------------===//
4416 // SSE2 - Conditional Store
4417 //===---------------------------------------------------------------------===//
4419 let ExeDomain = SSEPackedInt in {
4422 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4423 (ins VR128:$src, VR128:$mask),
4424 "maskmovdqu\t{$mask, $src|$src, $mask}",
4425 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
4427 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4428 (ins VR128:$src, VR128:$mask),
4429 "maskmovdqu\t{$mask, $src|$src, $mask}",
4430 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
4433 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4434 "maskmovdqu\t{$mask, $src|$src, $mask}",
4435 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
4437 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4438 "maskmovdqu\t{$mask, $src|$src, $mask}",
4439 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
4441 } // ExeDomain = SSEPackedInt
4443 //===---------------------------------------------------------------------===//
4444 // SSE2 - Move Doubleword
4445 //===---------------------------------------------------------------------===//
4447 //===---------------------------------------------------------------------===//
4448 // Move Int Doubleword to Packed Double Int
4450 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4451 "movd\t{$src, $dst|$dst, $src}",
4453 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
4454 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4455 "movd\t{$src, $dst|$dst, $src}",
4457 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
4459 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4460 "mov{d|q}\t{$src, $dst|$dst, $src}",
4462 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
4463 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4464 "mov{d|q}\t{$src, $dst|$dst, $src}",
4465 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
4467 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4468 "movd\t{$src, $dst|$dst, $src}",
4470 (v4i32 (scalar_to_vector GR32:$src)))]>;
4471 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4472 "movd\t{$src, $dst|$dst, $src}",
4474 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
4475 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4476 "mov{d|q}\t{$src, $dst|$dst, $src}",
4478 (v2i64 (scalar_to_vector GR64:$src)))]>;
4479 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4480 "mov{d|q}\t{$src, $dst|$dst, $src}",
4481 [(set FR64:$dst, (bitconvert GR64:$src))]>;
4483 //===---------------------------------------------------------------------===//
4484 // Move Int Doubleword to Single Scalar
4486 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4487 "movd\t{$src, $dst|$dst, $src}",
4488 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
4490 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4491 "movd\t{$src, $dst|$dst, $src}",
4492 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4494 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4495 "movd\t{$src, $dst|$dst, $src}",
4496 [(set FR32:$dst, (bitconvert GR32:$src))]>;
4498 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4499 "movd\t{$src, $dst|$dst, $src}",
4500 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
4502 //===---------------------------------------------------------------------===//
4503 // Move Packed Doubleword Int to Packed Double Int
4505 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4506 "movd\t{$src, $dst|$dst, $src}",
4507 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4509 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4510 (ins i32mem:$dst, VR128:$src),
4511 "movd\t{$src, $dst|$dst, $src}",
4512 [(store (i32 (vector_extract (v4i32 VR128:$src),
4513 (iPTR 0))), addr:$dst)]>, VEX;
4514 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4515 "movd\t{$src, $dst|$dst, $src}",
4516 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4518 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4519 "movd\t{$src, $dst|$dst, $src}",
4520 [(store (i32 (vector_extract (v4i32 VR128:$src),
4521 (iPTR 0))), addr:$dst)]>;
4523 //===---------------------------------------------------------------------===//
4524 // Move Packed Doubleword Int first element to Doubleword Int
4526 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4527 "mov{d|q}\t{$src, $dst|$dst, $src}",
4528 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4530 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4532 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4533 "mov{d|q}\t{$src, $dst|$dst, $src}",
4534 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4537 //===---------------------------------------------------------------------===//
4538 // Bitcast FR64 <-> GR64
4540 let Predicates = [HasAVX] in
4541 def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4542 "vmovq\t{$src, $dst|$dst, $src}",
4543 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4545 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4546 "mov{d|q}\t{$src, $dst|$dst, $src}",
4547 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4548 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4549 "movq\t{$src, $dst|$dst, $src}",
4550 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4552 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4553 "movq\t{$src, $dst|$dst, $src}",
4554 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
4555 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4556 "mov{d|q}\t{$src, $dst|$dst, $src}",
4557 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4558 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4559 "movq\t{$src, $dst|$dst, $src}",
4560 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4562 //===---------------------------------------------------------------------===//
4563 // Move Scalar Single to Double Int
4565 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4566 "movd\t{$src, $dst|$dst, $src}",
4567 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
4568 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4569 "movd\t{$src, $dst|$dst, $src}",
4570 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
4571 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4572 "movd\t{$src, $dst|$dst, $src}",
4573 [(set GR32:$dst, (bitconvert FR32:$src))]>;
4574 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4575 "movd\t{$src, $dst|$dst, $src}",
4576 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
4578 //===---------------------------------------------------------------------===//
4579 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4581 let AddedComplexity = 15 in {
4582 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4583 "movd\t{$src, $dst|$dst, $src}",
4584 [(set VR128:$dst, (v4i32 (X86vzmovl
4585 (v4i32 (scalar_to_vector GR32:$src)))))]>,
4587 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4588 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4589 [(set VR128:$dst, (v2i64 (X86vzmovl
4590 (v2i64 (scalar_to_vector GR64:$src)))))]>,
4593 let AddedComplexity = 15 in {
4594 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4595 "movd\t{$src, $dst|$dst, $src}",
4596 [(set VR128:$dst, (v4i32 (X86vzmovl
4597 (v4i32 (scalar_to_vector GR32:$src)))))]>;
4598 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4599 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4600 [(set VR128:$dst, (v2i64 (X86vzmovl
4601 (v2i64 (scalar_to_vector GR64:$src)))))]>;
4604 let AddedComplexity = 20 in {
4605 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4606 "movd\t{$src, $dst|$dst, $src}",
4608 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4609 (loadi32 addr:$src))))))]>,
4611 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4612 "movd\t{$src, $dst|$dst, $src}",
4614 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4615 (loadi32 addr:$src))))))]>;
4618 let Predicates = [HasAVX] in {
4619 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4620 let AddedComplexity = 20 in {
4621 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4622 (VMOVZDI2PDIrm addr:$src)>;
4623 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4624 (VMOVZDI2PDIrm addr:$src)>;
4625 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4626 (VMOVZDI2PDIrm addr:$src)>;
4628 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4629 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4630 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4631 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4632 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4633 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4634 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4637 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4638 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4639 (MOVZDI2PDIrm addr:$src)>;
4640 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4641 (MOVZDI2PDIrm addr:$src)>;
4642 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4643 (MOVZDI2PDIrm addr:$src)>;
4646 // These are the correct encodings of the instructions so that we know how to
4647 // read correct assembly, even though we continue to emit the wrong ones for
4648 // compatibility with Darwin's buggy assembler.
4649 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4650 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4651 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4652 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4653 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4654 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4655 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4656 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4657 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4658 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4659 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4660 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4662 //===---------------------------------------------------------------------===//
4663 // SSE2 - Move Quadword
4664 //===---------------------------------------------------------------------===//
4666 //===---------------------------------------------------------------------===//
4667 // Move Quadword Int to Packed Quadword Int
4669 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4670 "vmovq\t{$src, $dst|$dst, $src}",
4672 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4673 VEX, Requires<[HasAVX]>;
4674 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4675 "movq\t{$src, $dst|$dst, $src}",
4677 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4678 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4680 //===---------------------------------------------------------------------===//
4681 // Move Packed Quadword Int to Quadword Int
4683 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4684 "movq\t{$src, $dst|$dst, $src}",
4685 [(store (i64 (vector_extract (v2i64 VR128:$src),
4686 (iPTR 0))), addr:$dst)]>, VEX;
4687 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4688 "movq\t{$src, $dst|$dst, $src}",
4689 [(store (i64 (vector_extract (v2i64 VR128:$src),
4690 (iPTR 0))), addr:$dst)]>;
4692 //===---------------------------------------------------------------------===//
4693 // Store / copy lower 64-bits of a XMM register.
4695 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4696 "movq\t{$src, $dst|$dst, $src}",
4697 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4698 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4699 "movq\t{$src, $dst|$dst, $src}",
4700 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
4702 let AddedComplexity = 20 in
4703 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4704 "vmovq\t{$src, $dst|$dst, $src}",
4706 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4707 (loadi64 addr:$src))))))]>,
4708 XS, VEX, Requires<[HasAVX]>;
4710 let AddedComplexity = 20 in
4711 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4712 "movq\t{$src, $dst|$dst, $src}",
4714 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4715 (loadi64 addr:$src))))))]>,
4716 XS, Requires<[HasSSE2]>;
4718 let Predicates = [HasAVX], AddedComplexity = 20 in {
4719 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4720 (VMOVZQI2PQIrm addr:$src)>;
4721 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4722 (VMOVZQI2PQIrm addr:$src)>;
4723 def : Pat<(v2i64 (X86vzload addr:$src)),
4724 (VMOVZQI2PQIrm addr:$src)>;
4727 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4728 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4729 (MOVZQI2PQIrm addr:$src)>;
4730 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4731 (MOVZQI2PQIrm addr:$src)>;
4732 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4735 let Predicates = [HasAVX] in {
4736 def : Pat<(v4i64 (X86vzload addr:$src)),
4737 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4740 //===---------------------------------------------------------------------===//
4741 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4742 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4744 let AddedComplexity = 15 in
4745 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4746 "vmovq\t{$src, $dst|$dst, $src}",
4747 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4748 XS, VEX, Requires<[HasAVX]>;
4749 let AddedComplexity = 15 in
4750 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4751 "movq\t{$src, $dst|$dst, $src}",
4752 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4753 XS, Requires<[HasSSE2]>;
4755 let AddedComplexity = 20 in
4756 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4757 "vmovq\t{$src, $dst|$dst, $src}",
4758 [(set VR128:$dst, (v2i64 (X86vzmovl
4759 (loadv2i64 addr:$src))))]>,
4760 XS, VEX, Requires<[HasAVX]>;
4761 let AddedComplexity = 20 in {
4762 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4763 "movq\t{$src, $dst|$dst, $src}",
4764 [(set VR128:$dst, (v2i64 (X86vzmovl
4765 (loadv2i64 addr:$src))))]>,
4766 XS, Requires<[HasSSE2]>;
4769 let AddedComplexity = 20 in {
4770 let Predicates = [HasAVX] in {
4771 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4772 (VMOVZPQILo2PQIrm addr:$src)>;
4773 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4774 (VMOVZPQILo2PQIrr VR128:$src)>;
4776 let Predicates = [HasSSE2] in {
4777 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4778 (MOVZPQILo2PQIrm addr:$src)>;
4779 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4780 (MOVZPQILo2PQIrr VR128:$src)>;
4784 // Instructions to match in the assembler
4785 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4786 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4787 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4788 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4789 // Recognize "movd" with GR64 destination, but encode as a "movq"
4790 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4791 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4793 // Instructions for the disassembler
4794 // xr = XMM register
4797 let Predicates = [HasAVX] in
4798 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4799 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4800 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4801 "movq\t{$src, $dst|$dst, $src}", []>, XS;
4803 //===---------------------------------------------------------------------===//
4804 // SSE3 - Conversion Instructions
4805 //===---------------------------------------------------------------------===//
4807 // Convert Packed Double FP to Packed DW Integers
4808 let Predicates = [HasAVX] in {
4809 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4810 // register, but the same isn't true when using memory operands instead.
4811 // Provide other assembly rr and rm forms to address this explicitly.
4812 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4813 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4814 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4815 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4818 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4819 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4820 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4821 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4824 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4825 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4826 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4827 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4830 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4831 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4832 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4833 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4835 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4836 (VCVTPD2DQYrr VR256:$src)>;
4837 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4838 (VCVTPD2DQYrm addr:$src)>;
4840 // Convert Packed DW Integers to Packed Double FP
4841 let Predicates = [HasAVX] in {
4842 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4843 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4844 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4845 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4846 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4847 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4848 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4849 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4852 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4853 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4854 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4855 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4857 // AVX 256-bit register conversion intrinsics
4858 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4859 (VCVTDQ2PDYrr VR128:$src)>;
4860 def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
4861 (VCVTDQ2PDYrm addr:$src)>;
4863 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4864 (VCVTPD2DQYrr VR256:$src)>;
4865 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4866 (VCVTPD2DQYrm addr:$src)>;
4868 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4869 (VCVTDQ2PDYrr VR128:$src)>;
4870 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
4871 (VCVTDQ2PDYrm addr:$src)>;
4873 //===---------------------------------------------------------------------===//
4874 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4875 //===---------------------------------------------------------------------===//
4876 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4877 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4878 X86MemOperand x86memop> {
4879 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4880 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4881 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
4882 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4883 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4884 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
4887 let Predicates = [HasAVX] in {
4888 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4889 v4f32, VR128, memopv4f32, f128mem>, VEX;
4890 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4891 v4f32, VR128, memopv4f32, f128mem>, VEX;
4892 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4893 v8f32, VR256, memopv8f32, f256mem>, VEX;
4894 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4895 v8f32, VR256, memopv8f32, f256mem>, VEX;
4897 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4898 memopv4f32, f128mem>;
4899 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4900 memopv4f32, f128mem>;
4902 let Predicates = [HasAVX] in {
4903 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4904 (VMOVSHDUPrr VR128:$src)>;
4905 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4906 (VMOVSHDUPrm addr:$src)>;
4907 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4908 (VMOVSLDUPrr VR128:$src)>;
4909 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4910 (VMOVSLDUPrm addr:$src)>;
4911 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4912 (VMOVSHDUPYrr VR256:$src)>;
4913 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4914 (VMOVSHDUPYrm addr:$src)>;
4915 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4916 (VMOVSLDUPYrr VR256:$src)>;
4917 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4918 (VMOVSLDUPYrm addr:$src)>;
4921 let Predicates = [HasSSE3] in {
4922 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4923 (MOVSHDUPrr VR128:$src)>;
4924 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4925 (MOVSHDUPrm addr:$src)>;
4926 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4927 (MOVSLDUPrr VR128:$src)>;
4928 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4929 (MOVSLDUPrm addr:$src)>;
4932 //===---------------------------------------------------------------------===//
4933 // SSE3 - Replicate Double FP - MOVDDUP
4934 //===---------------------------------------------------------------------===//
4936 multiclass sse3_replicate_dfp<string OpcodeStr> {
4937 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4938 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4939 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
4940 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4941 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4943 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
4947 // FIXME: Merge with above classe when there're patterns for the ymm version
4948 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4949 let Predicates = [HasAVX] in {
4950 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4951 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4953 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4954 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4959 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4960 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4961 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4963 let Predicates = [HasAVX] in {
4964 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4966 (VMOVDDUPrm addr:$src)>;
4967 let AddedComplexity = 5 in {
4968 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4969 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4970 (VMOVDDUPrm addr:$src)>;
4971 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4972 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4973 (VMOVDDUPrm addr:$src)>;
4975 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4976 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4977 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4978 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4979 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4980 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4981 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4982 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4983 def : Pat<(X86Movddup (bc_v2f64
4984 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4985 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4988 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4989 (VMOVDDUPYrm addr:$src)>;
4990 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4991 (VMOVDDUPYrm addr:$src)>;
4992 def : Pat<(X86Movddup (v4f64 (scalar_to_vector (loadf64 addr:$src)))),
4993 (VMOVDDUPYrm addr:$src)>;
4994 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4995 (VMOVDDUPYrm addr:$src)>;
4996 def : Pat<(X86Movddup (v4f64 VR256:$src)),
4997 (VMOVDDUPYrr VR256:$src)>;
4998 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4999 (VMOVDDUPYrr VR256:$src)>;
5002 let Predicates = [HasSSE3] in {
5003 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
5005 (MOVDDUPrm addr:$src)>;
5006 let AddedComplexity = 5 in {
5007 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
5008 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
5009 (MOVDDUPrm addr:$src)>;
5010 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
5011 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
5012 (MOVDDUPrm addr:$src)>;
5014 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5015 (MOVDDUPrm addr:$src)>;
5016 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5017 (MOVDDUPrm addr:$src)>;
5018 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5019 (MOVDDUPrm addr:$src)>;
5020 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5021 (MOVDDUPrm addr:$src)>;
5022 def : Pat<(X86Movddup (bc_v2f64
5023 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5024 (MOVDDUPrm addr:$src)>;
5027 //===---------------------------------------------------------------------===//
5028 // SSE3 - Move Unaligned Integer
5029 //===---------------------------------------------------------------------===//
5031 let Predicates = [HasAVX] in {
5032 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5033 "vlddqu\t{$src, $dst|$dst, $src}",
5034 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5035 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5036 "vlddqu\t{$src, $dst|$dst, $src}",
5037 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
5039 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5040 "lddqu\t{$src, $dst|$dst, $src}",
5041 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
5043 //===---------------------------------------------------------------------===//
5044 // SSE3 - Arithmetic
5045 //===---------------------------------------------------------------------===//
5047 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5048 X86MemOperand x86memop, bit Is2Addr = 1> {
5049 def rr : I<0xD0, MRMSrcReg,
5050 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5052 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5053 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5054 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
5055 def rm : I<0xD0, MRMSrcMem,
5056 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5058 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5059 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5060 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
5063 let Predicates = [HasAVX] in {
5064 let ExeDomain = SSEPackedSingle in {
5065 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5066 f128mem, 0>, TB, XD, VEX_4V;
5067 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5068 f256mem, 0>, TB, XD, VEX_4V;
5070 let ExeDomain = SSEPackedDouble in {
5071 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5072 f128mem, 0>, TB, OpSize, VEX_4V;
5073 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5074 f256mem, 0>, TB, OpSize, VEX_4V;
5077 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
5078 let ExeDomain = SSEPackedSingle in
5079 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5081 let ExeDomain = SSEPackedDouble in
5082 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5083 f128mem>, TB, OpSize;
5086 //===---------------------------------------------------------------------===//
5087 // SSE3 Instructions
5088 //===---------------------------------------------------------------------===//
5091 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5092 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5093 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5095 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5096 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5097 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
5099 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5101 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5102 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5103 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
5105 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5106 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5107 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5109 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5110 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5111 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
5113 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5115 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5116 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5117 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
5120 let Predicates = [HasAVX] in {
5121 let ExeDomain = SSEPackedSingle in {
5122 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5123 X86fhadd, 0>, VEX_4V;
5124 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5125 X86fhsub, 0>, VEX_4V;
5126 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5127 X86fhadd, 0>, VEX_4V;
5128 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5129 X86fhsub, 0>, VEX_4V;
5131 let ExeDomain = SSEPackedDouble in {
5132 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5133 X86fhadd, 0>, VEX_4V;
5134 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5135 X86fhsub, 0>, VEX_4V;
5136 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5137 X86fhadd, 0>, VEX_4V;
5138 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5139 X86fhsub, 0>, VEX_4V;
5143 let Constraints = "$src1 = $dst" in {
5144 let ExeDomain = SSEPackedSingle in {
5145 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5146 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5148 let ExeDomain = SSEPackedDouble in {
5149 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5150 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5154 //===---------------------------------------------------------------------===//
5155 // SSSE3 - Packed Absolute Instructions
5156 //===---------------------------------------------------------------------===//
5159 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5160 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5161 Intrinsic IntId128> {
5162 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5164 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5165 [(set VR128:$dst, (IntId128 VR128:$src))]>,
5168 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5170 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5173 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
5176 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5177 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5178 Intrinsic IntId256> {
5179 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5181 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5182 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5185 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5187 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5190 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5193 let Predicates = [HasAVX] in {
5194 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5195 int_x86_ssse3_pabs_b_128>, VEX;
5196 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5197 int_x86_ssse3_pabs_w_128>, VEX;
5198 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5199 int_x86_ssse3_pabs_d_128>, VEX;
5202 let Predicates = [HasAVX2] in {
5203 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5204 int_x86_avx2_pabs_b>, VEX;
5205 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5206 int_x86_avx2_pabs_w>, VEX;
5207 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5208 int_x86_avx2_pabs_d>, VEX;
5211 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5212 int_x86_ssse3_pabs_b_128>;
5213 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5214 int_x86_ssse3_pabs_w_128>;
5215 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5216 int_x86_ssse3_pabs_d_128>;
5218 //===---------------------------------------------------------------------===//
5219 // SSSE3 - Packed Binary Operator Instructions
5220 //===---------------------------------------------------------------------===//
5222 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5223 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5224 Intrinsic IntId128, bit Is2Addr = 1> {
5225 let isCommutable = 1 in
5226 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5227 (ins VR128:$src1, VR128:$src2),
5229 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5230 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5231 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5233 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5234 (ins VR128:$src1, i128mem:$src2),
5236 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5237 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5239 (IntId128 VR128:$src1,
5240 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5243 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5244 Intrinsic IntId256> {
5245 let isCommutable = 1 in
5246 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5247 (ins VR256:$src1, VR256:$src2),
5248 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5249 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5251 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5252 (ins VR256:$src1, i256mem:$src2),
5253 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5255 (IntId256 VR256:$src1,
5256 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5259 let ImmT = NoImm, Predicates = [HasAVX] in {
5260 let isCommutable = 0 in {
5261 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw",
5262 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
5263 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd",
5264 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
5265 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5266 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
5267 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw",
5268 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
5269 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd",
5270 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
5271 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5272 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
5273 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5274 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
5275 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb",
5276 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
5277 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb",
5278 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
5279 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw",
5280 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
5281 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd",
5282 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
5284 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5285 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
5288 let ImmT = NoImm, Predicates = [HasAVX2] in {
5289 let isCommutable = 0 in {
5290 defm VPHADDW : SS3I_binop_rm_int_y<0x01, "vphaddw",
5291 int_x86_avx2_phadd_w>, VEX_4V;
5292 defm VPHADDD : SS3I_binop_rm_int_y<0x02, "vphaddd",
5293 int_x86_avx2_phadd_d>, VEX_4V;
5294 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5295 int_x86_avx2_phadd_sw>, VEX_4V;
5296 defm VPHSUBW : SS3I_binop_rm_int_y<0x05, "vphsubw",
5297 int_x86_avx2_phsub_w>, VEX_4V;
5298 defm VPHSUBD : SS3I_binop_rm_int_y<0x06, "vphsubd",
5299 int_x86_avx2_phsub_d>, VEX_4V;
5300 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5301 int_x86_avx2_phsub_sw>, VEX_4V;
5302 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5303 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5304 defm VPSHUFB : SS3I_binop_rm_int_y<0x00, "vpshufb",
5305 int_x86_avx2_pshuf_b>, VEX_4V;
5306 defm VPSIGNB : SS3I_binop_rm_int_y<0x08, "vpsignb",
5307 int_x86_avx2_psign_b>, VEX_4V;
5308 defm VPSIGNW : SS3I_binop_rm_int_y<0x09, "vpsignw",
5309 int_x86_avx2_psign_w>, VEX_4V;
5310 defm VPSIGND : SS3I_binop_rm_int_y<0x0A, "vpsignd",
5311 int_x86_avx2_psign_d>, VEX_4V;
5313 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5314 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5317 // None of these have i8 immediate fields.
5318 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5319 let isCommutable = 0 in {
5320 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw",
5321 int_x86_ssse3_phadd_w_128>;
5322 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd",
5323 int_x86_ssse3_phadd_d_128>;
5324 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5325 int_x86_ssse3_phadd_sw_128>;
5326 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw",
5327 int_x86_ssse3_phsub_w_128>;
5328 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd",
5329 int_x86_ssse3_phsub_d_128>;
5330 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5331 int_x86_ssse3_phsub_sw_128>;
5332 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5333 int_x86_ssse3_pmadd_ub_sw_128>;
5334 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb",
5335 int_x86_ssse3_pshuf_b_128>;
5336 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb",
5337 int_x86_ssse3_psign_b_128>;
5338 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw",
5339 int_x86_ssse3_psign_w_128>;
5340 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd",
5341 int_x86_ssse3_psign_d_128>;
5343 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5344 int_x86_ssse3_pmul_hr_sw_128>;
5347 let Predicates = [HasAVX] in {
5348 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
5349 (VPSHUFBrr128 VR128:$src, VR128:$mask)>;
5350 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
5351 (VPSHUFBrm128 VR128:$src, addr:$mask)>;
5353 def : Pat<(v16i8 (X86psign VR128:$src1, VR128:$src2)),
5354 (VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
5355 def : Pat<(v8i16 (X86psign VR128:$src1, VR128:$src2)),
5356 (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
5357 def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
5358 (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
5360 def : Pat<(v8i16 (X86hadd VR128:$src1, VR128:$src2)),
5361 (VPHADDWrr128 VR128:$src1, VR128:$src2)>;
5362 def : Pat<(v4i32 (X86hadd VR128:$src1, VR128:$src2)),
5363 (VPHADDDrr128 VR128:$src1, VR128:$src2)>;
5364 def : Pat<(v8i16 (X86hsub VR128:$src1, VR128:$src2)),
5365 (VPHSUBWrr128 VR128:$src1, VR128:$src2)>;
5366 def : Pat<(v4i32 (X86hsub VR128:$src1, VR128:$src2)),
5367 (VPHSUBDrr128 VR128:$src1, VR128:$src2)>;
5370 let Predicates = [HasAVX2] in {
5371 def : Pat<(v32i8 (X86psign VR256:$src1, VR256:$src2)),
5372 (VPSIGNBrr256 VR256:$src1, VR256:$src2)>;
5373 def : Pat<(v16i16 (X86psign VR256:$src1, VR256:$src2)),
5374 (VPSIGNWrr256 VR256:$src1, VR256:$src2)>;
5375 def : Pat<(v8i32 (X86psign VR256:$src1, VR256:$src2)),
5376 (VPSIGNDrr256 VR256:$src1, VR256:$src2)>;
5378 def : Pat<(v16i16 (X86hadd VR256:$src1, VR256:$src2)),
5379 (VPHADDWrr256 VR256:$src1, VR256:$src2)>;
5380 def : Pat<(v8i32 (X86hadd VR256:$src1, VR256:$src2)),
5381 (VPHADDDrr256 VR256:$src1, VR256:$src2)>;
5382 def : Pat<(v16i16 (X86hsub VR256:$src1, VR256:$src2)),
5383 (VPHSUBWrr256 VR256:$src1, VR256:$src2)>;
5384 def : Pat<(v8i32 (X86hsub VR256:$src1, VR256:$src2)),
5385 (VPHSUBDrr256 VR256:$src1, VR256:$src2)>;
5388 let Predicates = [HasSSSE3] in {
5389 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
5390 (PSHUFBrr128 VR128:$src, VR128:$mask)>;
5391 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
5392 (PSHUFBrm128 VR128:$src, addr:$mask)>;
5394 def : Pat<(v16i8 (X86psign VR128:$src1, VR128:$src2)),
5395 (PSIGNBrr128 VR128:$src1, VR128:$src2)>;
5396 def : Pat<(v8i16 (X86psign VR128:$src1, VR128:$src2)),
5397 (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
5398 def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
5399 (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
5401 def : Pat<(v8i16 (X86hadd VR128:$src1, VR128:$src2)),
5402 (PHADDWrr128 VR128:$src1, VR128:$src2)>;
5403 def : Pat<(v4i32 (X86hadd VR128:$src1, VR128:$src2)),
5404 (PHADDDrr128 VR128:$src1, VR128:$src2)>;
5405 def : Pat<(v8i16 (X86hsub VR128:$src1, VR128:$src2)),
5406 (PHSUBWrr128 VR128:$src1, VR128:$src2)>;
5407 def : Pat<(v4i32 (X86hsub VR128:$src1, VR128:$src2)),
5408 (PHSUBDrr128 VR128:$src1, VR128:$src2)>;
5411 //===---------------------------------------------------------------------===//
5412 // SSSE3 - Packed Align Instruction Patterns
5413 //===---------------------------------------------------------------------===//
5415 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5416 let neverHasSideEffects = 1 in {
5417 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5418 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5420 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5422 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5425 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5426 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5428 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5430 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5435 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5436 let neverHasSideEffects = 1 in {
5437 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5438 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5440 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5443 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5444 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5446 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5451 let Predicates = [HasAVX] in
5452 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5453 let Predicates = [HasAVX2] in
5454 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5455 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5456 defm PALIGN : ssse3_palign<"palignr">;
5458 let Predicates = [HasAVX] in {
5459 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5460 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5461 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5462 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5463 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5464 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5465 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5466 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5469 let Predicates = [HasSSSE3] in {
5470 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5471 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5472 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5473 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5474 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5475 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5476 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5477 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5480 //===---------------------------------------------------------------------===//
5481 // SSSE3 - Thread synchronization
5482 //===---------------------------------------------------------------------===//
5484 let usesCustomInserter = 1 in {
5485 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5486 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5487 Requires<[HasSSE3]>;
5488 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5489 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>,
5490 Requires<[HasSSE3]>;
5493 let Uses = [EAX, ECX, EDX] in
5494 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
5495 Requires<[HasSSE3]>;
5496 let Uses = [ECX, EAX] in
5497 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
5498 Requires<[HasSSE3]>;
5500 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5501 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5503 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5504 Requires<[In32BitMode]>;
5505 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5506 Requires<[In64BitMode]>;
5508 //===----------------------------------------------------------------------===//
5509 // SSE4.1 - Packed Move with Sign/Zero Extend
5510 //===----------------------------------------------------------------------===//
5512 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5513 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5514 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5515 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5517 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5518 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5520 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5524 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5526 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5527 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5528 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5530 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5531 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5532 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5535 let Predicates = [HasAVX] in {
5536 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5538 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5540 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5542 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5544 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5546 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5550 let Predicates = [HasAVX2] in {
5551 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5552 int_x86_avx2_pmovsxbw>, VEX;
5553 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5554 int_x86_avx2_pmovsxwd>, VEX;
5555 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5556 int_x86_avx2_pmovsxdq>, VEX;
5557 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5558 int_x86_avx2_pmovzxbw>, VEX;
5559 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5560 int_x86_avx2_pmovzxwd>, VEX;
5561 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5562 int_x86_avx2_pmovzxdq>, VEX;
5565 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5566 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5567 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5568 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5569 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5570 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5572 let Predicates = [HasAVX] in {
5573 // Common patterns involving scalar load.
5574 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5575 (VPMOVSXBWrm addr:$src)>;
5576 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5577 (VPMOVSXBWrm addr:$src)>;
5579 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5580 (VPMOVSXWDrm addr:$src)>;
5581 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5582 (VPMOVSXWDrm addr:$src)>;
5584 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5585 (VPMOVSXDQrm addr:$src)>;
5586 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5587 (VPMOVSXDQrm addr:$src)>;
5589 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5590 (VPMOVZXBWrm addr:$src)>;
5591 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5592 (VPMOVZXBWrm addr:$src)>;
5594 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5595 (VPMOVZXWDrm addr:$src)>;
5596 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5597 (VPMOVZXWDrm addr:$src)>;
5599 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5600 (VPMOVZXDQrm addr:$src)>;
5601 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5602 (VPMOVZXDQrm addr:$src)>;
5605 let Predicates = [HasSSE41] in {
5606 // Common patterns involving scalar load.
5607 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5608 (PMOVSXBWrm addr:$src)>;
5609 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5610 (PMOVSXBWrm addr:$src)>;
5612 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5613 (PMOVSXWDrm addr:$src)>;
5614 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5615 (PMOVSXWDrm addr:$src)>;
5617 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5618 (PMOVSXDQrm addr:$src)>;
5619 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5620 (PMOVSXDQrm addr:$src)>;
5622 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5623 (PMOVZXBWrm addr:$src)>;
5624 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5625 (PMOVZXBWrm addr:$src)>;
5627 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5628 (PMOVZXWDrm addr:$src)>;
5629 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5630 (PMOVZXWDrm addr:$src)>;
5632 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5633 (PMOVZXDQrm addr:$src)>;
5634 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5635 (PMOVZXDQrm addr:$src)>;
5639 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5640 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5641 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5642 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5644 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5645 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5647 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5651 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5653 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5654 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5655 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5657 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5658 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5660 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5664 let Predicates = [HasAVX] in {
5665 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5667 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5669 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5671 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5675 let Predicates = [HasAVX2] in {
5676 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5677 int_x86_avx2_pmovsxbd>, VEX;
5678 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5679 int_x86_avx2_pmovsxwq>, VEX;
5680 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5681 int_x86_avx2_pmovzxbd>, VEX;
5682 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5683 int_x86_avx2_pmovzxwq>, VEX;
5686 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5687 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5688 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5689 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5691 let Predicates = [HasAVX] in {
5692 // Common patterns involving scalar load
5693 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5694 (VPMOVSXBDrm addr:$src)>;
5695 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5696 (VPMOVSXWQrm addr:$src)>;
5698 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5699 (VPMOVZXBDrm addr:$src)>;
5700 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5701 (VPMOVZXWQrm addr:$src)>;
5704 let Predicates = [HasSSE41] in {
5705 // Common patterns involving scalar load
5706 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5707 (PMOVSXBDrm addr:$src)>;
5708 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5709 (PMOVSXWQrm addr:$src)>;
5711 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5712 (PMOVZXBDrm addr:$src)>;
5713 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5714 (PMOVZXWQrm addr:$src)>;
5717 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5718 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5719 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5720 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5722 // Expecting a i16 load any extended to i32 value.
5723 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5724 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5725 [(set VR128:$dst, (IntId (bitconvert
5726 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5730 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5732 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5733 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5734 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5736 // Expecting a i16 load any extended to i32 value.
5737 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5738 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5739 [(set VR256:$dst, (IntId (bitconvert
5740 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5744 let Predicates = [HasAVX] in {
5745 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5747 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5750 let Predicates = [HasAVX2] in {
5751 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5752 int_x86_avx2_pmovsxbq>, VEX;
5753 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5754 int_x86_avx2_pmovzxbq>, VEX;
5756 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5757 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5759 let Predicates = [HasAVX] in {
5760 // Common patterns involving scalar load
5761 def : Pat<(int_x86_sse41_pmovsxbq
5762 (bitconvert (v4i32 (X86vzmovl
5763 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5764 (VPMOVSXBQrm addr:$src)>;
5766 def : Pat<(int_x86_sse41_pmovzxbq
5767 (bitconvert (v4i32 (X86vzmovl
5768 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5769 (VPMOVZXBQrm addr:$src)>;
5772 let Predicates = [HasSSE41] in {
5773 // Common patterns involving scalar load
5774 def : Pat<(int_x86_sse41_pmovsxbq
5775 (bitconvert (v4i32 (X86vzmovl
5776 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5777 (PMOVSXBQrm addr:$src)>;
5779 def : Pat<(int_x86_sse41_pmovzxbq
5780 (bitconvert (v4i32 (X86vzmovl
5781 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5782 (PMOVZXBQrm addr:$src)>;
5785 //===----------------------------------------------------------------------===//
5786 // SSE4.1 - Extract Instructions
5787 //===----------------------------------------------------------------------===//
5789 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5790 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5791 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5792 (ins VR128:$src1, i32i8imm:$src2),
5793 !strconcat(OpcodeStr,
5794 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5795 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5797 let neverHasSideEffects = 1, mayStore = 1 in
5798 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5799 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5800 !strconcat(OpcodeStr,
5801 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5804 // There's an AssertZext in the way of writing the store pattern
5805 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5808 let Predicates = [HasAVX] in {
5809 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5810 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5811 (ins VR128:$src1, i32i8imm:$src2),
5812 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5815 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5818 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5819 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5820 let neverHasSideEffects = 1, mayStore = 1 in
5821 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5822 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5823 !strconcat(OpcodeStr,
5824 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5827 // There's an AssertZext in the way of writing the store pattern
5828 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5831 let Predicates = [HasAVX] in
5832 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5834 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5837 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5838 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5839 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5840 (ins VR128:$src1, i32i8imm:$src2),
5841 !strconcat(OpcodeStr,
5842 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5844 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5845 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5846 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5847 !strconcat(OpcodeStr,
5848 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5849 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5850 addr:$dst)]>, OpSize;
5853 let Predicates = [HasAVX] in
5854 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5856 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5858 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5859 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5860 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5861 (ins VR128:$src1, i32i8imm:$src2),
5862 !strconcat(OpcodeStr,
5863 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5865 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5866 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5867 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5868 !strconcat(OpcodeStr,
5869 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5870 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5871 addr:$dst)]>, OpSize, REX_W;
5874 let Predicates = [HasAVX] in
5875 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5877 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5879 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5881 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5882 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5883 (ins VR128:$src1, i32i8imm:$src2),
5884 !strconcat(OpcodeStr,
5885 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5887 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5889 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5890 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5891 !strconcat(OpcodeStr,
5892 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5893 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5894 addr:$dst)]>, OpSize;
5897 let ExeDomain = SSEPackedSingle in {
5898 let Predicates = [HasAVX] in {
5899 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5900 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5901 (ins VR128:$src1, i32i8imm:$src2),
5902 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5905 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5908 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5909 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5912 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5914 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5917 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5918 Requires<[HasSSE41]>;
5920 //===----------------------------------------------------------------------===//
5921 // SSE4.1 - Insert Instructions
5922 //===----------------------------------------------------------------------===//
5924 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5925 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5926 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5928 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5930 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5932 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5933 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5934 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5936 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5938 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5940 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5941 imm:$src3))]>, OpSize;
5944 let Predicates = [HasAVX] in
5945 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5946 let Constraints = "$src1 = $dst" in
5947 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5949 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5950 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5951 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5953 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5955 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5957 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5959 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5960 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5962 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5964 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5966 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5967 imm:$src3)))]>, OpSize;
5970 let Predicates = [HasAVX] in
5971 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5972 let Constraints = "$src1 = $dst" in
5973 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5975 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5976 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5977 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5979 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5981 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5983 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5985 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5986 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5988 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5990 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5992 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5993 imm:$src3)))]>, OpSize;
5996 let Predicates = [HasAVX] in
5997 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5998 let Constraints = "$src1 = $dst" in
5999 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6001 // insertps has a few different modes, there's the first two here below which
6002 // are optimized inserts that won't zero arbitrary elements in the destination
6003 // vector. The next one matches the intrinsic and could zero arbitrary elements
6004 // in the target vector.
6005 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6006 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6007 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6009 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6011 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6013 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6015 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6016 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6018 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6020 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6022 (X86insrtps VR128:$src1,
6023 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6024 imm:$src3))]>, OpSize;
6027 let ExeDomain = SSEPackedSingle in {
6028 let Predicates = [HasAVX] in
6029 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6030 let Constraints = "$src1 = $dst" in
6031 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6034 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
6035 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
6037 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
6038 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
6039 Requires<[HasSSE41]>;
6041 //===----------------------------------------------------------------------===//
6042 // SSE4.1 - Round Instructions
6043 //===----------------------------------------------------------------------===//
6045 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6046 X86MemOperand x86memop, RegisterClass RC,
6047 PatFrag mem_frag32, PatFrag mem_frag64,
6048 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6049 let ExeDomain = SSEPackedSingle in {
6050 // Intrinsic operation, reg.
6051 // Vector intrinsic operation, reg
6052 def PSr : SS4AIi8<opcps, MRMSrcReg,
6053 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6054 !strconcat(OpcodeStr,
6055 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6056 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6059 // Vector intrinsic operation, mem
6060 def PSm : SS4AIi8<opcps, MRMSrcMem,
6061 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6062 !strconcat(OpcodeStr,
6063 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6065 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6067 } // ExeDomain = SSEPackedSingle
6069 let ExeDomain = SSEPackedDouble in {
6070 // Vector intrinsic operation, reg
6071 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6072 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6073 !strconcat(OpcodeStr,
6074 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6075 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6078 // Vector intrinsic operation, mem
6079 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6080 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6081 !strconcat(OpcodeStr,
6082 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6084 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6086 } // ExeDomain = SSEPackedDouble
6089 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6092 Intrinsic F64Int, bit Is2Addr = 1> {
6093 let ExeDomain = GenericDomain in {
6095 def SSr : SS4AIi8<opcss, MRMSrcReg,
6096 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6098 !strconcat(OpcodeStr,
6099 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6100 !strconcat(OpcodeStr,
6101 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6104 // Intrinsic operation, reg.
6105 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6106 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6108 !strconcat(OpcodeStr,
6109 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6110 !strconcat(OpcodeStr,
6111 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6112 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6115 // Intrinsic operation, mem.
6116 def SSm : SS4AIi8<opcss, MRMSrcMem,
6117 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6119 !strconcat(OpcodeStr,
6120 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6121 !strconcat(OpcodeStr,
6122 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6124 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6128 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6129 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6131 !strconcat(OpcodeStr,
6132 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6133 !strconcat(OpcodeStr,
6134 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6137 // Intrinsic operation, reg.
6138 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6139 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6141 !strconcat(OpcodeStr,
6142 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6143 !strconcat(OpcodeStr,
6144 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6145 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6148 // Intrinsic operation, mem.
6149 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6150 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6152 !strconcat(OpcodeStr,
6153 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6154 !strconcat(OpcodeStr,
6155 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6157 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6159 } // ExeDomain = GenericDomain
6162 // FP round - roundss, roundps, roundsd, roundpd
6163 let Predicates = [HasAVX] in {
6165 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6166 memopv4f32, memopv2f64,
6167 int_x86_sse41_round_ps,
6168 int_x86_sse41_round_pd>, VEX;
6169 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6170 memopv8f32, memopv4f64,
6171 int_x86_avx_round_ps_256,
6172 int_x86_avx_round_pd_256>, VEX;
6173 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6174 int_x86_sse41_round_ss,
6175 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6177 def : Pat<(ffloor FR32:$src),
6178 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6179 def : Pat<(f64 (ffloor FR64:$src)),
6180 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6181 def : Pat<(f32 (fnearbyint FR32:$src)),
6182 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6183 def : Pat<(f64 (fnearbyint FR64:$src)),
6184 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6185 def : Pat<(f32 (fceil FR32:$src)),
6186 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6187 def : Pat<(f64 (fceil FR64:$src)),
6188 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6189 def : Pat<(f32 (frint FR32:$src)),
6190 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6191 def : Pat<(f64 (frint FR64:$src)),
6192 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6193 def : Pat<(f32 (ftrunc FR32:$src)),
6194 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6195 def : Pat<(f64 (ftrunc FR64:$src)),
6196 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6199 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6200 memopv4f32, memopv2f64,
6201 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6202 let Constraints = "$src1 = $dst" in
6203 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6204 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6206 def : Pat<(ffloor FR32:$src),
6207 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6208 def : Pat<(f64 (ffloor FR64:$src)),
6209 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6210 def : Pat<(f32 (fnearbyint FR32:$src)),
6211 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6212 def : Pat<(f64 (fnearbyint FR64:$src)),
6213 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6214 def : Pat<(f32 (fceil FR32:$src)),
6215 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6216 def : Pat<(f64 (fceil FR64:$src)),
6217 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6218 def : Pat<(f32 (frint FR32:$src)),
6219 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6220 def : Pat<(f64 (frint FR64:$src)),
6221 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6222 def : Pat<(f32 (ftrunc FR32:$src)),
6223 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6224 def : Pat<(f64 (ftrunc FR64:$src)),
6225 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6227 //===----------------------------------------------------------------------===//
6228 // SSE4.1 - Packed Bit Test
6229 //===----------------------------------------------------------------------===//
6231 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6232 // the intel intrinsic that corresponds to this.
6233 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6234 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6235 "vptest\t{$src2, $src1|$src1, $src2}",
6236 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
6238 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6239 "vptest\t{$src2, $src1|$src1, $src2}",
6240 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
6243 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6244 "vptest\t{$src2, $src1|$src1, $src2}",
6245 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6247 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6248 "vptest\t{$src2, $src1|$src1, $src2}",
6249 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6253 let Defs = [EFLAGS] in {
6254 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6255 "ptest\t{$src2, $src1|$src1, $src2}",
6256 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
6258 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6259 "ptest\t{$src2, $src1|$src1, $src2}",
6260 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
6264 // The bit test instructions below are AVX only
6265 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6266 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6267 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6268 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6269 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6270 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6271 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6272 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6276 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6277 let ExeDomain = SSEPackedSingle in {
6278 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6279 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6281 let ExeDomain = SSEPackedDouble in {
6282 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6283 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6287 //===----------------------------------------------------------------------===//
6288 // SSE4.1 - Misc Instructions
6289 //===----------------------------------------------------------------------===//
6291 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6292 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6293 "popcnt{w}\t{$src, $dst|$dst, $src}",
6294 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6296 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6297 "popcnt{w}\t{$src, $dst|$dst, $src}",
6298 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6299 (implicit EFLAGS)]>, OpSize, XS;
6301 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6302 "popcnt{l}\t{$src, $dst|$dst, $src}",
6303 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6305 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6306 "popcnt{l}\t{$src, $dst|$dst, $src}",
6307 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6308 (implicit EFLAGS)]>, XS;
6310 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6311 "popcnt{q}\t{$src, $dst|$dst, $src}",
6312 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6314 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6315 "popcnt{q}\t{$src, $dst|$dst, $src}",
6316 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6317 (implicit EFLAGS)]>, XS;
6322 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6323 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6324 Intrinsic IntId128> {
6325 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6327 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6328 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6329 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6331 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6334 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6337 let Predicates = [HasAVX] in
6338 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6339 int_x86_sse41_phminposuw>, VEX;
6340 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6341 int_x86_sse41_phminposuw>;
6343 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6344 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6345 Intrinsic IntId128, bit Is2Addr = 1> {
6346 let isCommutable = 1 in
6347 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6348 (ins VR128:$src1, VR128:$src2),
6350 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6351 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6352 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6353 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6354 (ins VR128:$src1, i128mem:$src2),
6356 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6357 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6359 (IntId128 VR128:$src1,
6360 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6363 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6364 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6365 Intrinsic IntId256> {
6366 let isCommutable = 1 in
6367 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6368 (ins VR256:$src1, VR256:$src2),
6369 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6370 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6371 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6372 (ins VR256:$src1, i256mem:$src2),
6373 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6375 (IntId256 VR256:$src1,
6376 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6379 let Predicates = [HasAVX] in {
6380 let isCommutable = 0 in
6381 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6383 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
6385 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6387 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6389 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6391 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6393 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6395 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6397 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6399 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6401 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6404 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
6405 (VPCMPEQQrr VR128:$src1, VR128:$src2)>;
6406 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
6407 (VPCMPEQQrm VR128:$src1, addr:$src2)>;
6410 let Predicates = [HasAVX2] in {
6411 let isCommutable = 0 in
6412 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6413 int_x86_avx2_packusdw>, VEX_4V;
6414 defm VPCMPEQQ : SS41I_binop_rm_int_y<0x29, "vpcmpeqq",
6415 int_x86_avx2_pcmpeq_q>, VEX_4V;
6416 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6417 int_x86_avx2_pmins_b>, VEX_4V;
6418 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6419 int_x86_avx2_pmins_d>, VEX_4V;
6420 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6421 int_x86_avx2_pminu_d>, VEX_4V;
6422 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6423 int_x86_avx2_pminu_w>, VEX_4V;
6424 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6425 int_x86_avx2_pmaxs_b>, VEX_4V;
6426 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6427 int_x86_avx2_pmaxs_d>, VEX_4V;
6428 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6429 int_x86_avx2_pmaxu_d>, VEX_4V;
6430 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6431 int_x86_avx2_pmaxu_w>, VEX_4V;
6432 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6433 int_x86_avx2_pmul_dq>, VEX_4V;
6435 def : Pat<(v4i64 (X86pcmpeqq VR256:$src1, VR256:$src2)),
6436 (VPCMPEQQYrr VR256:$src1, VR256:$src2)>;
6437 def : Pat<(v4i64 (X86pcmpeqq VR256:$src1, (memop addr:$src2))),
6438 (VPCMPEQQYrm VR256:$src1, addr:$src2)>;
6441 let Constraints = "$src1 = $dst" in {
6442 let isCommutable = 0 in
6443 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6444 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
6445 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6446 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6447 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6448 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6449 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6450 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6451 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6452 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6453 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6456 let Predicates = [HasSSE41] in {
6457 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
6458 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
6459 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
6460 (PCMPEQQrm VR128:$src1, addr:$src2)>;
6463 /// SS48I_binop_rm - Simple SSE41 binary operator.
6464 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6465 ValueType OpVT, bit Is2Addr = 1> {
6466 let isCommutable = 1 in
6467 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6468 (ins VR128:$src1, VR128:$src2),
6470 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6471 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6472 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
6474 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6475 (ins VR128:$src1, i128mem:$src2),
6477 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6478 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6479 [(set VR128:$dst, (OpNode VR128:$src1,
6480 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
6484 /// SS48I_binop_rm - Simple SSE41 binary operator.
6485 multiclass SS48I_binop_rm_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
6487 let isCommutable = 1 in
6488 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6489 (ins VR256:$src1, VR256:$src2),
6490 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6491 [(set VR256:$dst, (OpVT (OpNode VR256:$src1, VR256:$src2)))]>,
6493 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6494 (ins VR256:$src1, i256mem:$src2),
6495 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6496 [(set VR256:$dst, (OpNode VR256:$src1,
6497 (bc_v8i32 (memopv4i64 addr:$src2))))]>,
6501 let Predicates = [HasAVX] in
6502 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
6503 let Predicates = [HasAVX2] in
6504 defm VPMULLD : SS48I_binop_rm_y<0x40, "vpmulld", mul, v8i32>, VEX_4V;
6505 let Constraints = "$src1 = $dst" in
6506 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
6508 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6509 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6510 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6511 X86MemOperand x86memop, bit Is2Addr = 1> {
6512 let isCommutable = 1 in
6513 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6514 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6516 !strconcat(OpcodeStr,
6517 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6518 !strconcat(OpcodeStr,
6519 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6520 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6522 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6523 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6525 !strconcat(OpcodeStr,
6526 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6527 !strconcat(OpcodeStr,
6528 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6531 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6535 let Predicates = [HasAVX] in {
6536 let isCommutable = 0 in {
6537 let ExeDomain = SSEPackedSingle in {
6538 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6539 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6540 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6541 int_x86_avx_blend_ps_256, VR256, memopv8f32, i256mem, 0>, VEX_4V;
6543 let ExeDomain = SSEPackedDouble in {
6544 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6545 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6546 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6547 int_x86_avx_blend_pd_256, VR256, memopv4f64, i256mem, 0>, VEX_4V;
6549 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6550 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6551 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6552 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6554 let ExeDomain = SSEPackedSingle in
6555 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6556 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6557 let ExeDomain = SSEPackedDouble in
6558 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6559 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6560 let ExeDomain = SSEPackedSingle in
6561 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6562 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6565 let Predicates = [HasAVX2] in {
6566 let isCommutable = 0 in {
6567 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6568 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6569 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6570 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6574 let Constraints = "$src1 = $dst" in {
6575 let isCommutable = 0 in {
6576 let ExeDomain = SSEPackedSingle in
6577 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6578 VR128, memopv4f32, i128mem>;
6579 let ExeDomain = SSEPackedDouble in
6580 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6581 VR128, memopv2f64, i128mem>;
6582 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6583 VR128, memopv2i64, i128mem>;
6584 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6585 VR128, memopv2i64, i128mem>;
6587 let ExeDomain = SSEPackedSingle in
6588 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6589 VR128, memopv4f32, i128mem>;
6590 let ExeDomain = SSEPackedDouble in
6591 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6592 VR128, memopv2f64, i128mem>;
6595 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6596 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6597 RegisterClass RC, X86MemOperand x86memop,
6598 PatFrag mem_frag, Intrinsic IntId> {
6599 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6600 (ins RC:$src1, RC:$src2, RC:$src3),
6601 !strconcat(OpcodeStr,
6602 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6603 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6604 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6606 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6607 (ins RC:$src1, x86memop:$src2, RC:$src3),
6608 !strconcat(OpcodeStr,
6609 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6611 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6613 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6616 let Predicates = [HasAVX] in {
6617 let ExeDomain = SSEPackedDouble in {
6618 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
6619 memopv2f64, int_x86_sse41_blendvpd>;
6620 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
6621 memopv4f64, int_x86_avx_blendv_pd_256>;
6622 } // ExeDomain = SSEPackedDouble
6623 let ExeDomain = SSEPackedSingle in {
6624 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
6625 memopv4f32, int_x86_sse41_blendvps>;
6626 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
6627 memopv8f32, int_x86_avx_blendv_ps_256>;
6628 } // ExeDomain = SSEPackedSingle
6629 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6630 memopv2i64, int_x86_sse41_pblendvb>;
6633 let Predicates = [HasAVX2] in {
6634 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6635 memopv4i64, int_x86_avx2_pblendvb>;
6638 let Predicates = [HasAVX] in {
6639 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6640 (v16i8 VR128:$src2))),
6641 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6642 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6643 (v4i32 VR128:$src2))),
6644 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6645 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6646 (v4f32 VR128:$src2))),
6647 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6648 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6649 (v2i64 VR128:$src2))),
6650 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6651 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6652 (v2f64 VR128:$src2))),
6653 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6654 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6655 (v8i32 VR256:$src2))),
6656 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6657 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6658 (v8f32 VR256:$src2))),
6659 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6660 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6661 (v4i64 VR256:$src2))),
6662 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6663 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6664 (v4f64 VR256:$src2))),
6665 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6668 let Predicates = [HasAVX2] in {
6669 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6670 (v32i8 VR256:$src2))),
6671 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6674 /// SS41I_ternary_int - SSE 4.1 ternary operator
6675 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6676 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6678 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6679 (ins VR128:$src1, VR128:$src2),
6680 !strconcat(OpcodeStr,
6681 "\t{$src2, $dst|$dst, $src2}"),
6682 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6685 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6686 (ins VR128:$src1, i128mem:$src2),
6687 !strconcat(OpcodeStr,
6688 "\t{$src2, $dst|$dst, $src2}"),
6691 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6695 let ExeDomain = SSEPackedDouble in
6696 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64,
6697 int_x86_sse41_blendvpd>;
6698 let ExeDomain = SSEPackedSingle in
6699 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32,
6700 int_x86_sse41_blendvps>;
6701 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64,
6702 int_x86_sse41_pblendvb>;
6704 let Predicates = [HasSSE41] in {
6705 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6706 (v16i8 VR128:$src2))),
6707 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6708 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6709 (v4i32 VR128:$src2))),
6710 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6711 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6712 (v4f32 VR128:$src2))),
6713 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6714 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6715 (v2i64 VR128:$src2))),
6716 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6717 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6718 (v2f64 VR128:$src2))),
6719 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6722 let Predicates = [HasAVX] in
6723 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6724 "vmovntdqa\t{$src, $dst|$dst, $src}",
6725 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6727 let Predicates = [HasAVX2] in
6728 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6729 "vmovntdqa\t{$src, $dst|$dst, $src}",
6730 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6732 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6733 "movntdqa\t{$src, $dst|$dst, $src}",
6734 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6737 //===----------------------------------------------------------------------===//
6738 // SSE4.2 - Compare Instructions
6739 //===----------------------------------------------------------------------===//
6741 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
6742 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
6743 Intrinsic IntId128, bit Is2Addr = 1> {
6744 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
6745 (ins VR128:$src1, VR128:$src2),
6747 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6748 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6749 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6751 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
6752 (ins VR128:$src1, i128mem:$src2),
6754 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6755 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6757 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
6760 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
6761 multiclass SS42I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6762 Intrinsic IntId256> {
6763 def Yrr : SS428I<opc, MRMSrcReg, (outs VR256:$dst),
6764 (ins VR256:$src1, VR256:$src2),
6765 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6766 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
6768 def Yrm : SS428I<opc, MRMSrcMem, (outs VR256:$dst),
6769 (ins VR256:$src1, i256mem:$src2),
6770 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6772 (IntId256 VR256:$src1, (memopv4i64 addr:$src2)))]>, OpSize;
6775 let Predicates = [HasAVX] in {
6776 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
6779 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6780 (VPCMPGTQrr VR128:$src1, VR128:$src2)>;
6781 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6782 (VPCMPGTQrm VR128:$src1, addr:$src2)>;
6785 let Predicates = [HasAVX2] in {
6786 defm VPCMPGTQ : SS42I_binop_rm_int_y<0x37, "vpcmpgtq", int_x86_avx2_pcmpgt_q>,
6789 def : Pat<(v4i64 (X86pcmpgtq VR256:$src1, VR256:$src2)),
6790 (VPCMPGTQYrr VR256:$src1, VR256:$src2)>;
6791 def : Pat<(v4i64 (X86pcmpgtq VR256:$src1, (memop addr:$src2))),
6792 (VPCMPGTQYrm VR256:$src1, addr:$src2)>;
6795 let Constraints = "$src1 = $dst" in
6796 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
6798 let Predicates = [HasSSE42] in {
6799 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6800 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
6801 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6802 (PCMPGTQrm VR128:$src1, addr:$src2)>;
6805 //===----------------------------------------------------------------------===//
6806 // SSE4.2 - String/text Processing Instructions
6807 //===----------------------------------------------------------------------===//
6809 // Packed Compare Implicit Length Strings, Return Mask
6810 multiclass pseudo_pcmpistrm<string asm> {
6811 def REG : PseudoI<(outs VR128:$dst),
6812 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6813 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6815 def MEM : PseudoI<(outs VR128:$dst),
6816 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6817 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6818 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6821 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6822 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6823 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6826 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6827 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6828 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6829 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6831 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6832 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6833 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6836 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6837 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6838 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6839 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6841 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6842 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6843 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6846 // Packed Compare Explicit Length Strings, Return Mask
6847 multiclass pseudo_pcmpestrm<string asm> {
6848 def REG : PseudoI<(outs VR128:$dst),
6849 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6850 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6851 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6852 def MEM : PseudoI<(outs VR128:$dst),
6853 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6854 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6855 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6858 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6859 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6860 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6863 let Predicates = [HasAVX],
6864 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6865 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6866 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6867 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6869 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6870 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6871 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6874 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6875 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6876 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6877 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6879 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6880 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6881 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6884 // Packed Compare Implicit Length Strings, Return Index
6885 let Defs = [ECX, EFLAGS] in {
6886 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6887 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6888 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6889 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6890 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6891 (implicit EFLAGS)]>, OpSize;
6892 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6893 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6894 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6895 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6896 (implicit EFLAGS)]>, OpSize;
6900 let Predicates = [HasAVX] in {
6901 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6903 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6905 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6907 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6909 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6911 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6915 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6916 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6917 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6918 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6919 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6920 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6922 // Packed Compare Explicit Length Strings, Return Index
6923 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6924 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6925 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6926 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6927 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6928 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6929 (implicit EFLAGS)]>, OpSize;
6930 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6931 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6932 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6934 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6935 (implicit EFLAGS)]>, OpSize;
6939 let Predicates = [HasAVX] in {
6940 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6942 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6944 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6946 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6948 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6950 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6954 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6955 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6956 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6957 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6958 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6959 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6961 //===----------------------------------------------------------------------===//
6962 // SSE4.2 - CRC Instructions
6963 //===----------------------------------------------------------------------===//
6965 // No CRC instructions have AVX equivalents
6967 // crc intrinsic instruction
6968 // This set of instructions are only rm, the only difference is the size
6970 let Constraints = "$src1 = $dst" in {
6971 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6972 (ins GR32:$src1, i8mem:$src2),
6973 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6975 (int_x86_sse42_crc32_32_8 GR32:$src1,
6976 (load addr:$src2)))]>;
6977 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6978 (ins GR32:$src1, GR8:$src2),
6979 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6981 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6982 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6983 (ins GR32:$src1, i16mem:$src2),
6984 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6986 (int_x86_sse42_crc32_32_16 GR32:$src1,
6987 (load addr:$src2)))]>,
6989 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6990 (ins GR32:$src1, GR16:$src2),
6991 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6993 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6995 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6996 (ins GR32:$src1, i32mem:$src2),
6997 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6999 (int_x86_sse42_crc32_32_32 GR32:$src1,
7000 (load addr:$src2)))]>;
7001 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7002 (ins GR32:$src1, GR32:$src2),
7003 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7005 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7006 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7007 (ins GR64:$src1, i8mem:$src2),
7008 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7010 (int_x86_sse42_crc32_64_8 GR64:$src1,
7011 (load addr:$src2)))]>,
7013 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7014 (ins GR64:$src1, GR8:$src2),
7015 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7017 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7019 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7020 (ins GR64:$src1, i64mem:$src2),
7021 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7023 (int_x86_sse42_crc32_64_64 GR64:$src1,
7024 (load addr:$src2)))]>,
7026 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7027 (ins GR64:$src1, GR64:$src2),
7028 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7030 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7034 //===----------------------------------------------------------------------===//
7035 // AES-NI Instructions
7036 //===----------------------------------------------------------------------===//
7038 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7039 Intrinsic IntId128, bit Is2Addr = 1> {
7040 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7041 (ins VR128:$src1, VR128:$src2),
7043 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7044 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7045 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7047 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7048 (ins VR128:$src1, i128mem:$src2),
7050 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7051 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7053 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7056 // Perform One Round of an AES Encryption/Decryption Flow
7057 let Predicates = [HasAVX, HasAES] in {
7058 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7059 int_x86_aesni_aesenc, 0>, VEX_4V;
7060 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7061 int_x86_aesni_aesenclast, 0>, VEX_4V;
7062 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7063 int_x86_aesni_aesdec, 0>, VEX_4V;
7064 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7065 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7068 let Constraints = "$src1 = $dst" in {
7069 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7070 int_x86_aesni_aesenc>;
7071 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7072 int_x86_aesni_aesenclast>;
7073 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7074 int_x86_aesni_aesdec>;
7075 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7076 int_x86_aesni_aesdeclast>;
7079 // Perform the AES InvMixColumn Transformation
7080 let Predicates = [HasAVX, HasAES] in {
7081 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7083 "vaesimc\t{$src1, $dst|$dst, $src1}",
7085 (int_x86_aesni_aesimc VR128:$src1))]>,
7087 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7088 (ins i128mem:$src1),
7089 "vaesimc\t{$src1, $dst|$dst, $src1}",
7090 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7093 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7095 "aesimc\t{$src1, $dst|$dst, $src1}",
7097 (int_x86_aesni_aesimc VR128:$src1))]>,
7099 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7100 (ins i128mem:$src1),
7101 "aesimc\t{$src1, $dst|$dst, $src1}",
7102 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7105 // AES Round Key Generation Assist
7106 let Predicates = [HasAVX, HasAES] in {
7107 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7108 (ins VR128:$src1, i8imm:$src2),
7109 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7111 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7113 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7114 (ins i128mem:$src1, i8imm:$src2),
7115 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7117 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7120 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7121 (ins VR128:$src1, i8imm:$src2),
7122 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7124 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7126 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7127 (ins i128mem:$src1, i8imm:$src2),
7128 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7130 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7133 //===----------------------------------------------------------------------===//
7134 // CLMUL Instructions
7135 //===----------------------------------------------------------------------===//
7137 // Carry-less Multiplication instructions
7138 let neverHasSideEffects = 1 in {
7139 // AVX carry-less Multiplication instructions
7140 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7141 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7142 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7146 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7147 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7148 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7151 let Constraints = "$src1 = $dst" in {
7152 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7153 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7154 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7158 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7159 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7160 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7162 } // Constraints = "$src1 = $dst"
7163 } // neverHasSideEffects = 1
7166 multiclass pclmul_alias<string asm, int immop> {
7167 def : InstAlias<!strconcat("pclmul", asm,
7168 "dq {$src, $dst|$dst, $src}"),
7169 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7171 def : InstAlias<!strconcat("pclmul", asm,
7172 "dq {$src, $dst|$dst, $src}"),
7173 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7175 def : InstAlias<!strconcat("vpclmul", asm,
7176 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7177 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7179 def : InstAlias<!strconcat("vpclmul", asm,
7180 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7181 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7183 defm : pclmul_alias<"hqhq", 0x11>;
7184 defm : pclmul_alias<"hqlq", 0x01>;
7185 defm : pclmul_alias<"lqhq", 0x10>;
7186 defm : pclmul_alias<"lqlq", 0x00>;
7188 //===----------------------------------------------------------------------===//
7190 //===----------------------------------------------------------------------===//
7192 //===----------------------------------------------------------------------===//
7193 // VBROADCAST - Load from memory and broadcast to all elements of the
7194 // destination operand
7196 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7197 X86MemOperand x86memop, Intrinsic Int> :
7198 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7199 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7200 [(set RC:$dst, (Int addr:$src))]>, VEX;
7202 // AVX2 adds register forms
7203 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7205 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7206 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7207 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7209 let ExeDomain = SSEPackedSingle in {
7210 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7211 int_x86_avx_vbroadcast_ss>;
7212 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7213 int_x86_avx_vbroadcast_ss_256>;
7215 let ExeDomain = SSEPackedDouble in
7216 def VBROADCASTSDrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7217 int_x86_avx_vbroadcast_sd_256>;
7218 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7219 int_x86_avx_vbroadcastf128_pd_256>;
7221 let ExeDomain = SSEPackedSingle in {
7222 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7223 int_x86_avx2_vbroadcast_ss_ps>;
7224 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7225 int_x86_avx2_vbroadcast_ss_ps_256>;
7227 let ExeDomain = SSEPackedDouble in
7228 def VBROADCASTSDrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7229 int_x86_avx2_vbroadcast_sd_pd_256>;
7231 let Predicates = [HasAVX2] in
7232 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7233 int_x86_avx2_vbroadcasti128>;
7235 let Predicates = [HasAVX] in
7236 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7237 (VBROADCASTF128 addr:$src)>;
7240 //===----------------------------------------------------------------------===//
7241 // VINSERTF128 - Insert packed floating-point values
7243 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7244 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7245 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7246 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7249 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7250 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7251 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7255 let Predicates = [HasAVX] in {
7256 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
7257 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
7258 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
7259 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
7260 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
7261 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
7264 //===----------------------------------------------------------------------===//
7265 // VEXTRACTF128 - Extract packed floating-point values
7267 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7268 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7269 (ins VR256:$src1, i8imm:$src2),
7270 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7273 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7274 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7275 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7279 let Predicates = [HasAVX] in {
7280 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
7281 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7282 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
7283 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7284 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
7285 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7288 //===----------------------------------------------------------------------===//
7289 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7291 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7292 Intrinsic IntLd, Intrinsic IntLd256,
7293 Intrinsic IntSt, Intrinsic IntSt256> {
7294 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7295 (ins VR128:$src1, f128mem:$src2),
7296 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7297 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7299 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7300 (ins VR256:$src1, f256mem:$src2),
7301 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7302 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7304 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7305 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7306 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7307 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7308 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7309 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7310 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7311 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7314 let ExeDomain = SSEPackedSingle in
7315 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7316 int_x86_avx_maskload_ps,
7317 int_x86_avx_maskload_ps_256,
7318 int_x86_avx_maskstore_ps,
7319 int_x86_avx_maskstore_ps_256>;
7320 let ExeDomain = SSEPackedDouble in
7321 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7322 int_x86_avx_maskload_pd,
7323 int_x86_avx_maskload_pd_256,
7324 int_x86_avx_maskstore_pd,
7325 int_x86_avx_maskstore_pd_256>;
7327 //===----------------------------------------------------------------------===//
7328 // VPERMIL - Permute Single and Double Floating-Point Values
7330 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7331 RegisterClass RC, X86MemOperand x86memop_f,
7332 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
7333 Intrinsic IntVar, Intrinsic IntImm> {
7334 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7335 (ins RC:$src1, RC:$src2),
7336 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7337 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7338 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7339 (ins RC:$src1, x86memop_i:$src2),
7340 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7341 [(set RC:$dst, (IntVar RC:$src1,
7342 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7344 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7345 (ins RC:$src1, i8imm:$src2),
7346 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7347 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
7348 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7349 (ins x86memop_f:$src1, i8imm:$src2),
7350 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7351 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
7354 let ExeDomain = SSEPackedSingle in {
7355 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7356 memopv4f32, memopv2i64,
7357 int_x86_avx_vpermilvar_ps,
7358 int_x86_avx_vpermil_ps>;
7359 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7360 memopv8f32, memopv4i64,
7361 int_x86_avx_vpermilvar_ps_256,
7362 int_x86_avx_vpermil_ps_256>;
7364 let ExeDomain = SSEPackedDouble in {
7365 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7366 memopv2f64, memopv2i64,
7367 int_x86_avx_vpermilvar_pd,
7368 int_x86_avx_vpermil_pd>;
7369 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7370 memopv4f64, memopv4i64,
7371 int_x86_avx_vpermilvar_pd_256,
7372 int_x86_avx_vpermil_pd_256>;
7375 let Predicates = [HasAVX] in {
7376 def : Pat<(v8f32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7377 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7378 def : Pat<(v4f64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7379 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7380 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7381 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7382 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7383 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7384 def : Pat<(v8f32 (X86VPermilp (memopv8f32 addr:$src1), (i8 imm:$imm))),
7385 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7386 def : Pat<(v4f64 (X86VPermilp (memopv4f64 addr:$src1), (i8 imm:$imm))),
7387 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7388 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7390 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7391 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7392 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7395 //===----------------------------------------------------------------------===//
7396 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7398 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7399 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7400 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7401 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7404 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7405 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7406 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7410 let Predicates = [HasAVX] in {
7411 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
7412 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
7413 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
7414 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
7415 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
7416 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
7418 def : Pat<(int_x86_avx_vperm2f128_ps_256
7419 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
7420 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
7421 def : Pat<(int_x86_avx_vperm2f128_pd_256
7422 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
7423 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
7424 def : Pat<(int_x86_avx_vperm2f128_si_256
7425 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)), imm:$src3),
7426 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
7429 //===----------------------------------------------------------------------===//
7430 // VZERO - Zero YMM registers
7432 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7433 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7434 // Zero All YMM registers
7435 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7436 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7438 // Zero Upper bits of YMM registers
7439 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7440 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7443 //===----------------------------------------------------------------------===//
7444 // Half precision conversion instructions
7445 //===----------------------------------------------------------------------===//
7446 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7447 let Predicates = [HasAVX, HasF16C] in {
7448 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7449 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7450 [(set RC:$dst, (Int VR128:$src))]>,
7452 let neverHasSideEffects = 1, mayLoad = 1 in
7453 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7454 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7458 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7459 let Predicates = [HasAVX, HasF16C] in {
7460 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7461 (ins RC:$src1, i32i8imm:$src2),
7462 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7463 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7465 let neverHasSideEffects = 1, mayLoad = 1 in
7466 def mr : Ii8<0x1D, MRMDestMem, (outs x86memop:$dst),
7467 (ins RC:$src1, i32i8imm:$src2),
7468 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7473 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7474 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7475 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7476 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7478 //===----------------------------------------------------------------------===//
7479 // AVX2 Instructions
7480 //===----------------------------------------------------------------------===//
7482 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7483 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7484 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7485 X86MemOperand x86memop> {
7486 let isCommutable = 1 in
7487 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7488 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7489 !strconcat(OpcodeStr,
7490 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7491 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7493 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7494 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7495 !strconcat(OpcodeStr,
7496 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7499 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7503 let isCommutable = 0 in {
7504 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7505 VR128, memopv2i64, i128mem>;
7506 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7507 VR256, memopv4i64, i256mem>;
7510 //===----------------------------------------------------------------------===//
7511 // VPBROADCAST - Load from memory and broadcast to all elements of the
7512 // destination operand
7514 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7515 X86MemOperand x86memop, PatFrag ld_frag,
7516 Intrinsic Int128, Intrinsic Int256> {
7517 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7518 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7519 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7520 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7521 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7523 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7524 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7525 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7526 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7527 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7528 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7530 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7533 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7534 int_x86_avx2_pbroadcastb_128,
7535 int_x86_avx2_pbroadcastb_256>;
7536 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7537 int_x86_avx2_pbroadcastw_128,
7538 int_x86_avx2_pbroadcastw_256>;
7539 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7540 int_x86_avx2_pbroadcastd_128,
7541 int_x86_avx2_pbroadcastd_256>;
7542 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7543 int_x86_avx2_pbroadcastq_128,
7544 int_x86_avx2_pbroadcastq_256>;
7546 let Predicates = [HasAVX2] in {
7547 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7548 (VPBROADCASTBrm addr:$src)>;
7549 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7550 (VPBROADCASTBYrm addr:$src)>;
7551 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7552 (VPBROADCASTWrm addr:$src)>;
7553 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7554 (VPBROADCASTWYrm addr:$src)>;
7555 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7556 (VPBROADCASTDrm addr:$src)>;
7557 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7558 (VPBROADCASTDYrm addr:$src)>;
7559 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7560 (VPBROADCASTQrm addr:$src)>;
7561 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7562 (VPBROADCASTQYrm addr:$src)>;
7565 // AVX1 broadcast patterns
7566 let Predicates = [HasAVX] in {
7567 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7568 (VBROADCASTSSYrm addr:$src)>;
7569 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7570 (VBROADCASTSDrm addr:$src)>;
7571 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7572 (VBROADCASTSSYrm addr:$src)>;
7573 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7574 (VBROADCASTSDrm addr:$src)>;
7576 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7577 (VBROADCASTSSrm addr:$src)>;
7578 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7579 (VBROADCASTSSrm addr:$src)>;
7582 //===----------------------------------------------------------------------===//
7583 // VPERM - Permute instructions
7586 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7588 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7589 (ins VR256:$src1, VR256:$src2),
7590 !strconcat(OpcodeStr,
7591 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7592 [(set VR256:$dst, (Int VR256:$src1, VR256:$src2))]>, VEX_4V;
7593 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7594 (ins VR256:$src1, i256mem:$src2),
7595 !strconcat(OpcodeStr,
7596 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7597 [(set VR256:$dst, (Int VR256:$src1,
7598 (bitconvert (mem_frag addr:$src2))))]>,
7602 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, int_x86_avx2_permd>;
7603 let ExeDomain = SSEPackedSingle in
7604 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, int_x86_avx2_permps>;
7606 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7608 def Yrr : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7609 (ins VR256:$src1, i8imm:$src2),
7610 !strconcat(OpcodeStr,
7611 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7612 [(set VR256:$dst, (Int VR256:$src1, imm:$src2))]>, VEX;
7613 def Yrm : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7614 (ins i256mem:$src1, i8imm:$src2),
7615 !strconcat(OpcodeStr,
7616 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7617 [(set VR256:$dst, (Int (mem_frag addr:$src1), imm:$src2))]>,
7621 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, int_x86_avx2_permq>,
7623 let ExeDomain = SSEPackedDouble in
7624 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, int_x86_avx2_permpd>,
7627 //===----------------------------------------------------------------------===//
7628 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7630 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7631 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7632 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7634 (int_x86_avx2_vperm2i128 VR256:$src1, VR256:$src2, imm:$src3))]>,
7636 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7637 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7638 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7640 (int_x86_avx2_vperm2i128 VR256:$src1, (memopv4i64 addr:$src2),
7644 let Predicates = [HasAVX2] in {
7645 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7646 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7647 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7648 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7649 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7650 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7651 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7652 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7654 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7656 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7657 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7658 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7659 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7660 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7662 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7663 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7665 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7669 let Predicates = [HasAVX] in {
7670 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7671 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7672 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7673 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7674 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7675 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7676 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7677 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7678 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7679 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7680 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7681 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7683 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1,
7684 (memopv8f32 addr:$src2), (i8 imm:$imm))),
7685 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7686 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7687 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7688 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7689 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7690 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7691 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7692 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7693 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7694 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7695 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7696 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7697 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7698 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7699 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7700 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7704 //===----------------------------------------------------------------------===//
7705 // VINSERTI128 - Insert packed integer values
7707 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7708 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7709 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7711 (int_x86_avx2_vinserti128 VR256:$src1, VR128:$src2, imm:$src3))]>,
7713 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7714 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7715 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7717 (int_x86_avx2_vinserti128 VR256:$src1, (memopv2i64 addr:$src2),
7718 imm:$src3))]>, VEX_4V;
7720 let Predicates = [HasAVX2] in {
7721 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7723 (VINSERTI128rr VR256:$src1, VR128:$src2,
7724 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7725 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7727 (VINSERTI128rr VR256:$src1, VR128:$src2,
7728 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7729 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7731 (VINSERTI128rr VR256:$src1, VR128:$src2,
7732 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7733 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7735 (VINSERTI128rr VR256:$src1, VR128:$src2,
7736 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7740 let Predicates = [HasAVX] in {
7741 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7743 (VINSERTF128rr VR256:$src1, VR128:$src2,
7744 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7745 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7747 (VINSERTF128rr VR256:$src1, VR128:$src2,
7748 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7749 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7751 (VINSERTF128rr VR256:$src1, VR128:$src2,
7752 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7753 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7755 (VINSERTF128rr VR256:$src1, VR128:$src2,
7756 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7757 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7759 (VINSERTF128rr VR256:$src1, VR128:$src2,
7760 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7761 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7763 (VINSERTF128rr VR256:$src1, VR128:$src2,
7764 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7767 //===----------------------------------------------------------------------===//
7768 // VEXTRACTI128 - Extract packed integer values
7770 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7771 (ins VR256:$src1, i8imm:$src2),
7772 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7774 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7776 let neverHasSideEffects = 1, mayStore = 1 in
7777 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7778 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7779 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7781 let Predicates = [HasAVX2] in {
7782 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7783 (v2i64 (VEXTRACTI128rr
7784 (v4i64 VR256:$src1),
7785 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7786 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7787 (v4i32 (VEXTRACTI128rr
7788 (v8i32 VR256:$src1),
7789 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7790 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7791 (v8i16 (VEXTRACTI128rr
7792 (v16i16 VR256:$src1),
7793 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7794 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7795 (v16i8 (VEXTRACTI128rr
7796 (v32i8 VR256:$src1),
7797 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7801 let Predicates = [HasAVX] in {
7802 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7803 (v4f32 (VEXTRACTF128rr
7804 (v8f32 VR256:$src1),
7805 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7806 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7807 (v2f64 (VEXTRACTF128rr
7808 (v4f64 VR256:$src1),
7809 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7810 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7811 (v2i64 (VEXTRACTF128rr
7812 (v4i64 VR256:$src1),
7813 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7814 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7815 (v4i32 (VEXTRACTF128rr
7816 (v8i32 VR256:$src1),
7817 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7818 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7819 (v8i16 (VEXTRACTF128rr
7820 (v16i16 VR256:$src1),
7821 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7822 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7823 (v16i8 (VEXTRACTF128rr
7824 (v32i8 VR256:$src1),
7825 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7828 //===----------------------------------------------------------------------===//
7829 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7831 multiclass avx2_pmovmask<string OpcodeStr,
7832 Intrinsic IntLd128, Intrinsic IntLd256,
7833 Intrinsic IntSt128, Intrinsic IntSt256> {
7834 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7835 (ins VR128:$src1, i128mem:$src2),
7836 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7837 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7838 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7839 (ins VR256:$src1, i256mem:$src2),
7840 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7841 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7842 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7843 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7844 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7845 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7846 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7847 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7848 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7849 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7852 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
7853 int_x86_avx2_maskload_d,
7854 int_x86_avx2_maskload_d_256,
7855 int_x86_avx2_maskstore_d,
7856 int_x86_avx2_maskstore_d_256>;
7857 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
7858 int_x86_avx2_maskload_q,
7859 int_x86_avx2_maskload_q_256,
7860 int_x86_avx2_maskstore_q,
7861 int_x86_avx2_maskstore_q_256>, VEX_W;
7864 //===----------------------------------------------------------------------===//
7865 // Variable Bit Shifts
7867 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
7868 ValueType vt128, ValueType vt256> {
7869 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7870 (ins VR128:$src1, VR128:$src2),
7871 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7873 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
7875 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
7876 (ins VR128:$src1, i128mem:$src2),
7877 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7879 (vt128 (OpNode VR128:$src1,
7880 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
7882 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7883 (ins VR256:$src1, VR256:$src2),
7884 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7886 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
7888 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7889 (ins VR256:$src1, i256mem:$src2),
7890 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7892 (vt256 (OpNode VR256:$src1,
7893 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
7897 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
7898 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
7899 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
7900 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
7901 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;