1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 bit rr_hasSideEffects = 0> {
208 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 pat_rr, IIC_DEFAULT, d>;
214 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 pat_rm, IIC_DEFAULT, d>;
221 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
222 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 string asm, string SSEVer, string FPSizeStr,
224 X86MemOperand x86memop, PatFrag mem_frag,
225 Domain d, OpndItins itins, bit Is2Addr = 1> {
226 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
228 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
229 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
230 [(set RC:$dst, (!cast<Intrinsic>(
231 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
232 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
233 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
235 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
236 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
237 [(set RC:$dst, (!cast<Intrinsic>(
238 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
239 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
242 //===----------------------------------------------------------------------===//
243 // Non-instruction patterns
244 //===----------------------------------------------------------------------===//
246 // A vector extract of the first f32/f64 position is a subregister copy
247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
249 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
250 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
252 // A 128-bit subvector extract from the first 256-bit vector position
253 // is a subregister copy that needs no instruction.
254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
261 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
264 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
266 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
269 // A 128-bit subvector insert to the first 256-bit vector position
270 // is a subregister copy that needs no instruction.
271 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
272 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
273 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
274 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
275 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
276 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
278 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
280 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
282 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
284 // Implicitly promote a 32-bit scalar to a vector.
285 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
286 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
287 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
288 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
289 // Implicitly promote a 64-bit scalar to a vector.
290 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
291 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
292 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
293 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
295 // Bitcasts between 128-bit vector types. Return the original type since
296 // no instruction is needed for the conversion
297 let Predicates = [HasSSE2] in {
298 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
299 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
300 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
304 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
309 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
314 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
319 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
324 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
330 // Bitcasts between 256-bit vector types. Return the original type since
331 // no instruction is needed for the conversion
332 let Predicates = [HasAVX] in {
333 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
334 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
335 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
339 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
344 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
349 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
354 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
359 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
365 // Alias instructions that map fld0 to pxor for sse.
366 // This is expanded by ExpandPostRAPseudos.
367 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
369 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
370 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
371 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
372 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
375 //===----------------------------------------------------------------------===//
376 // AVX & SSE - Zero/One Vectors
377 //===----------------------------------------------------------------------===//
379 // Alias instruction that maps zero vector to pxor / xorp* for sse.
380 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
381 // swizzled by ExecutionDepsFix to pxor.
382 // We set canFoldAsLoad because this can be converted to a constant-pool
383 // load of an all-zeros value if folding it would be beneficial.
384 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
385 isPseudo = 1, neverHasSideEffects = 1 in {
386 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
389 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
390 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
391 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
392 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
393 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
394 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
397 // The same as done above but for AVX. The 256-bit ISA does not support PI,
398 // and doesn't need it because on sandy bridge the register is set to zero
399 // at the rename stage without using any execution unit, so SET0PSY
400 // and SET0PDY can be used for vector int instructions without penalty
401 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
402 // JIT implementatioan, it does not expand the instructions below like
403 // X86MCInstLower does.
404 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
405 isCodeGenOnly = 1 in {
406 let Predicates = [HasAVX] in {
407 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
408 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
409 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
410 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
412 let Predicates = [HasAVX2], neverHasSideEffects = 1 in
413 def AVX2_SET0 : PDI<0xef, MRMInitReg, (outs VR256:$dst), (ins), "",
417 let Predicates = [HasAVX2], AddedComplexity = 5 in {
418 def : Pat<(v4i64 immAllZerosV), (AVX2_SET0)>;
419 def : Pat<(v8i32 immAllZerosV), (AVX2_SET0)>;
420 def : Pat<(v16i16 immAllZerosV), (AVX2_SET0)>;
421 def : Pat<(v32i8 immAllZerosV), (AVX2_SET0)>;
424 // AVX has no support for 256-bit integer instructions, but since the 128-bit
425 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
426 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
427 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
428 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
430 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
431 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
432 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
434 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
435 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
436 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
438 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
439 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
440 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
442 // We set canFoldAsLoad because this can be converted to a constant-pool
443 // load of an all-ones value if folding it would be beneficial.
444 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
445 // JIT implementation, it does not expand the instructions below like
446 // X86MCInstLower does.
447 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
448 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
449 let Predicates = [HasAVX] in
450 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
451 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
452 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
453 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
454 let Predicates = [HasAVX2] in
455 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
456 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
460 //===----------------------------------------------------------------------===//
461 // SSE 1 & 2 - Move FP Scalar Instructions
463 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
464 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
465 // is used instead. Register-to-register movss/movsd is not modeled as an
466 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
467 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
468 //===----------------------------------------------------------------------===//
470 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
471 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
472 [(set VR128:$dst, (vt (OpNode VR128:$src1,
473 (scalar_to_vector RC:$src2))))],
476 // Loading from memory automatically zeroing upper bits.
477 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
478 PatFrag mem_pat, string OpcodeStr> :
479 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
480 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
481 [(set RC:$dst, (mem_pat addr:$src))],
485 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
486 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
488 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
489 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
492 // For the disassembler
493 let isCodeGenOnly = 1 in {
494 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
495 (ins VR128:$src1, FR32:$src2),
496 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
499 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
500 (ins VR128:$src1, FR64:$src2),
501 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
506 let canFoldAsLoad = 1, isReMaterializable = 1 in {
507 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
509 let AddedComplexity = 20 in
510 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
514 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
515 "movss\t{$src, $dst|$dst, $src}",
516 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
518 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
519 "movsd\t{$src, $dst|$dst, $src}",
520 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
524 let Constraints = "$src1 = $dst" in {
525 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
526 "movss\t{$src2, $dst|$dst, $src2}">, XS;
527 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
528 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
530 // For the disassembler
531 let isCodeGenOnly = 1 in {
532 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
533 (ins VR128:$src1, FR32:$src2),
534 "movss\t{$src2, $dst|$dst, $src2}", [],
535 IIC_SSE_MOV_S_RR>, XS;
536 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
537 (ins VR128:$src1, FR64:$src2),
538 "movsd\t{$src2, $dst|$dst, $src2}", [],
539 IIC_SSE_MOV_S_RR>, XD;
543 let canFoldAsLoad = 1, isReMaterializable = 1 in {
544 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
546 let AddedComplexity = 20 in
547 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
550 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
551 "movss\t{$src, $dst|$dst, $src}",
552 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
553 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
554 "movsd\t{$src, $dst|$dst, $src}",
555 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
558 let Predicates = [HasAVX] in {
559 let AddedComplexity = 15 in {
560 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
561 // MOVS{S,D} to the lower bits.
562 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
563 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
564 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
565 (VMOVSSrr (v4f32 (V_SET0)),
566 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
567 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
568 (VMOVSSrr (v4i32 (V_SET0)),
569 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
570 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
571 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
573 // Move low f32 and clear high bits.
574 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
575 (SUBREG_TO_REG (i32 0),
576 (VMOVSSrr (v4f32 (V_SET0)),
577 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_ss)), sub_xmm)>;
578 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
579 (SUBREG_TO_REG (i32 0),
580 (VMOVSSrr (v4i32 (V_SET0)),
581 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_ss)), sub_xmm)>;
584 let AddedComplexity = 20 in {
585 // MOVSSrm zeros the high parts of the register; represent this
586 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
587 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
588 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
589 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
590 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
591 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
592 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
594 // MOVSDrm zeros the high parts of the register; represent this
595 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
596 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
597 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
598 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
599 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
600 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
601 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
602 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
603 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
604 def : Pat<(v2f64 (X86vzload addr:$src)),
605 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
607 // Represent the same patterns above but in the form they appear for
609 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
610 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
611 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
612 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
613 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
614 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
615 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
616 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
617 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
619 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
620 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
621 (SUBREG_TO_REG (i32 0),
622 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
624 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
625 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
626 (SUBREG_TO_REG (i64 0),
627 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
629 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
630 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
631 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
633 // Move low f64 and clear high bits.
634 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
635 (SUBREG_TO_REG (i32 0),
636 (VMOVSDrr (v2f64 (V_SET0)),
637 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_sd)), sub_xmm)>;
639 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
640 (SUBREG_TO_REG (i32 0),
641 (VMOVSDrr (v2i64 (V_SET0)),
642 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_sd)), sub_xmm)>;
644 // Extract and store.
645 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
648 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
649 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
652 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
654 // Shuffle with VMOVSS
655 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
656 (VMOVSSrr (v4i32 VR128:$src1),
657 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
658 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
659 (VMOVSSrr (v4f32 VR128:$src1),
660 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
663 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
664 (SUBREG_TO_REG (i32 0),
665 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_ss),
666 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_ss)), sub_xmm)>;
667 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
668 (SUBREG_TO_REG (i32 0),
669 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_ss),
670 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_ss)), sub_xmm)>;
672 // Shuffle with VMOVSD
673 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
674 (VMOVSDrr (v2i64 VR128:$src1),
675 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
676 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
677 (VMOVSDrr (v2f64 VR128:$src1),
678 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
679 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
680 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
682 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
683 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
687 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
688 (SUBREG_TO_REG (i32 0),
689 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_sd),
690 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_sd)), sub_xmm)>;
691 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_sd),
694 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_sd)), sub_xmm)>;
697 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
698 // is during lowering, where it's not possible to recognize the fold cause
699 // it has two uses through a bitcast. One use disappears at isel time and the
700 // fold opportunity reappears.
701 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
702 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
704 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
705 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),
707 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
708 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
710 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
715 let Predicates = [HasSSE1] in {
716 let AddedComplexity = 15 in {
717 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
718 // MOVSS to the lower bits.
719 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
720 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
721 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
722 (MOVSSrr (v4f32 (V_SET0)),
723 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)),
726 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
729 let AddedComplexity = 20 in {
730 // MOVSSrm zeros the high parts of the register; represent this
731 // with SUBREG_TO_REG.
732 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
733 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
734 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
735 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
736 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
737 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
740 // Extract and store.
741 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
744 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
746 // Shuffle with MOVSS
747 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
748 (MOVSSrr (v4i32 VR128:$src1),
749 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
750 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
751 (MOVSSrr (v4f32 VR128:$src1),
752 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
755 let Predicates = [HasSSE2] in {
756 let AddedComplexity = 15 in {
757 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
758 // MOVSD to the lower bits.
759 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
760 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
763 let AddedComplexity = 20 in {
764 // MOVSDrm zeros the high parts of the register; represent this
765 // with SUBREG_TO_REG.
766 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
767 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
768 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
769 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
770 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
771 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
772 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
773 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
774 def : Pat<(v2f64 (X86vzload addr:$src)),
775 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
778 // Extract and store.
779 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
782 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
784 // Shuffle with MOVSD
785 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
786 (MOVSDrr (v2i64 VR128:$src1),
787 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
788 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
789 (MOVSDrr (v2f64 VR128:$src1),
790 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
791 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
793 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
796 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
797 // is during lowering, where it's not possible to recognize the fold cause
798 // it has two uses through a bitcast. One use disappears at isel time and the
799 // fold opportunity reappears.
800 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
801 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
802 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
803 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
804 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
805 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
806 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
807 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
810 //===----------------------------------------------------------------------===//
811 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
812 //===----------------------------------------------------------------------===//
814 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
815 X86MemOperand x86memop, PatFrag ld_frag,
816 string asm, Domain d,
818 bit IsReMaterializable = 1> {
819 let neverHasSideEffects = 1 in
820 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
821 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
822 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
823 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
824 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
825 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
828 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
829 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
831 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
832 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
834 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
835 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
837 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
838 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
841 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
842 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
844 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
845 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
847 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
848 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
850 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
851 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
853 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
854 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
856 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
857 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
859 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
860 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
862 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
863 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
867 "movaps\t{$src, $dst|$dst, $src}",
868 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
869 IIC_SSE_MOVA_P_MR>, VEX;
870 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
871 "movapd\t{$src, $dst|$dst, $src}",
872 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
873 IIC_SSE_MOVA_P_MR>, VEX;
874 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
875 "movups\t{$src, $dst|$dst, $src}",
876 [(store (v4f32 VR128:$src), addr:$dst)],
877 IIC_SSE_MOVU_P_MR>, VEX;
878 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
879 "movupd\t{$src, $dst|$dst, $src}",
880 [(store (v2f64 VR128:$src), addr:$dst)],
881 IIC_SSE_MOVU_P_MR>, VEX;
882 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
883 "movaps\t{$src, $dst|$dst, $src}",
884 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
885 IIC_SSE_MOVA_P_MR>, VEX;
886 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
887 "movapd\t{$src, $dst|$dst, $src}",
888 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
889 IIC_SSE_MOVA_P_MR>, VEX;
890 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
891 "movups\t{$src, $dst|$dst, $src}",
892 [(store (v8f32 VR256:$src), addr:$dst)],
893 IIC_SSE_MOVU_P_MR>, VEX;
894 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
895 "movupd\t{$src, $dst|$dst, $src}",
896 [(store (v4f64 VR256:$src), addr:$dst)],
897 IIC_SSE_MOVU_P_MR>, VEX;
900 let isCodeGenOnly = 1 in {
901 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
903 "movaps\t{$src, $dst|$dst, $src}", [],
904 IIC_SSE_MOVA_P_RR>, VEX;
905 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
907 "movapd\t{$src, $dst|$dst, $src}", [],
908 IIC_SSE_MOVA_P_RR>, VEX;
909 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
911 "movups\t{$src, $dst|$dst, $src}", [],
912 IIC_SSE_MOVU_P_RR>, VEX;
913 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
915 "movupd\t{$src, $dst|$dst, $src}", [],
916 IIC_SSE_MOVU_P_RR>, VEX;
917 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
919 "movaps\t{$src, $dst|$dst, $src}", [],
920 IIC_SSE_MOVA_P_RR>, VEX;
921 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
923 "movapd\t{$src, $dst|$dst, $src}", [],
924 IIC_SSE_MOVA_P_RR>, VEX;
925 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
927 "movups\t{$src, $dst|$dst, $src}", [],
928 IIC_SSE_MOVU_P_RR>, VEX;
929 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
931 "movupd\t{$src, $dst|$dst, $src}", [],
932 IIC_SSE_MOVU_P_RR>, VEX;
935 let Predicates = [HasAVX] in {
936 def : Pat<(v8i32 (X86vzmovl
937 (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
938 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
939 def : Pat<(v4i64 (X86vzmovl
940 (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v8f32 (X86vzmovl
943 (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v4f64 (X86vzmovl
946 (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
951 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
952 (VMOVUPSYmr addr:$dst, VR256:$src)>;
953 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
954 (VMOVUPDYmr addr:$dst, VR256:$src)>;
956 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
957 "movaps\t{$src, $dst|$dst, $src}",
958 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
960 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movapd\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
964 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movups\t{$src, $dst|$dst, $src}",
966 [(store (v4f32 VR128:$src), addr:$dst)],
968 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movupd\t{$src, $dst|$dst, $src}",
970 [(store (v2f64 VR128:$src), addr:$dst)],
974 let isCodeGenOnly = 1 in {
975 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
976 "movaps\t{$src, $dst|$dst, $src}", [],
978 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
979 "movapd\t{$src, $dst|$dst, $src}", [],
981 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movups\t{$src, $dst|$dst, $src}", [],
984 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movupd\t{$src, $dst|$dst, $src}", [],
989 let Predicates = [HasAVX] in {
990 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
991 (VMOVUPSmr addr:$dst, VR128:$src)>;
992 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
993 (VMOVUPDmr addr:$dst, VR128:$src)>;
996 let Predicates = [HasSSE1] in
997 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
998 (MOVUPSmr addr:$dst, VR128:$src)>;
999 let Predicates = [HasSSE2] in
1000 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1001 (MOVUPDmr addr:$dst, VR128:$src)>;
1003 // Use vmovaps/vmovups for AVX integer load/store.
1004 let Predicates = [HasAVX] in {
1005 // 128-bit load/store
1006 def : Pat<(alignedloadv2i64 addr:$src),
1007 (VMOVAPSrm addr:$src)>;
1008 def : Pat<(loadv2i64 addr:$src),
1009 (VMOVUPSrm addr:$src)>;
1011 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1012 (VMOVAPSmr addr:$dst, VR128:$src)>;
1013 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1014 (VMOVAPSmr addr:$dst, VR128:$src)>;
1015 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1016 (VMOVAPSmr addr:$dst, VR128:$src)>;
1017 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1020 (VMOVUPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1022 (VMOVUPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1024 (VMOVUPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1028 // 256-bit load/store
1029 def : Pat<(alignedloadv4i64 addr:$src),
1030 (VMOVAPSYrm addr:$src)>;
1031 def : Pat<(loadv4i64 addr:$src),
1032 (VMOVUPSYrm addr:$src)>;
1033 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1034 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1035 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1036 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1037 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1038 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1039 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1042 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1044 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1046 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 // Use movaps / movups for SSE integer load / store (one byte shorter).
1052 // The instructions selected below are then converted to MOVDQA/MOVDQU
1053 // during the SSE domain pass.
1054 let Predicates = [HasSSE1] in {
1055 def : Pat<(alignedloadv2i64 addr:$src),
1056 (MOVAPSrm addr:$src)>;
1057 def : Pat<(loadv2i64 addr:$src),
1058 (MOVUPSrm addr:$src)>;
1060 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1061 (MOVAPSmr addr:$dst, VR128:$src)>;
1062 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1063 (MOVAPSmr addr:$dst, VR128:$src)>;
1064 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1065 (MOVAPSmr addr:$dst, VR128:$src)>;
1066 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1067 (MOVAPSmr addr:$dst, VR128:$src)>;
1068 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1069 (MOVUPSmr addr:$dst, VR128:$src)>;
1070 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1071 (MOVUPSmr addr:$dst, VR128:$src)>;
1072 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1073 (MOVUPSmr addr:$dst, VR128:$src)>;
1074 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1075 (MOVUPSmr addr:$dst, VR128:$src)>;
1078 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1079 // bits are disregarded. FIXME: Set encoding to pseudo!
1080 let neverHasSideEffects = 1 in {
1081 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1082 "movaps\t{$src, $dst|$dst, $src}", [],
1083 IIC_SSE_MOVA_P_RR>, VEX;
1084 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1085 "movapd\t{$src, $dst|$dst, $src}", [],
1086 IIC_SSE_MOVA_P_RR>, VEX;
1087 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1088 "movaps\t{$src, $dst|$dst, $src}", [],
1090 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1091 "movapd\t{$src, $dst|$dst, $src}", [],
1095 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1096 // bits are disregarded. FIXME: Set encoding to pseudo!
1097 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1098 let isCodeGenOnly = 1 in {
1099 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1100 "movaps\t{$src, $dst|$dst, $src}",
1101 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1102 IIC_SSE_MOVA_P_RM>, VEX;
1103 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1104 "movapd\t{$src, $dst|$dst, $src}",
1105 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1106 IIC_SSE_MOVA_P_RM>, VEX;
1108 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1109 "movaps\t{$src, $dst|$dst, $src}",
1110 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1112 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1113 "movapd\t{$src, $dst|$dst, $src}",
1114 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1118 //===----------------------------------------------------------------------===//
1119 // SSE 1 & 2 - Move Low packed FP Instructions
1120 //===----------------------------------------------------------------------===//
1122 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1123 SDNode psnode, SDNode pdnode, string base_opc,
1124 string asm_opr, InstrItinClass itin> {
1125 def PSrm : PI<opc, MRMSrcMem,
1126 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1127 !strconcat(base_opc, "s", asm_opr),
1130 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1131 itin, SSEPackedSingle>, TB;
1133 def PDrm : PI<opc, MRMSrcMem,
1134 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1135 !strconcat(base_opc, "d", asm_opr),
1136 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1137 (scalar_to_vector (loadf64 addr:$src2)))))],
1138 itin, SSEPackedDouble>, TB, OpSize;
1141 let AddedComplexity = 20 in {
1142 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1143 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1144 IIC_SSE_MOV_LH>, VEX_4V;
1146 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1147 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1148 "\t{$src2, $dst|$dst, $src2}",
1152 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1153 "movlps\t{$src, $dst|$dst, $src}",
1154 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1155 (iPTR 0))), addr:$dst)],
1156 IIC_SSE_MOV_LH>, VEX;
1157 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1158 "movlpd\t{$src, $dst|$dst, $src}",
1159 [(store (f64 (vector_extract (v2f64 VR128:$src),
1160 (iPTR 0))), addr:$dst)],
1161 IIC_SSE_MOV_LH>, VEX;
1162 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1163 "movlps\t{$src, $dst|$dst, $src}",
1164 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1165 (iPTR 0))), addr:$dst)],
1167 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1168 "movlpd\t{$src, $dst|$dst, $src}",
1169 [(store (f64 (vector_extract (v2f64 VR128:$src),
1170 (iPTR 0))), addr:$dst)],
1173 let Predicates = [HasAVX] in {
1174 // Shuffle with VMOVLPS
1175 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1176 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1177 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1178 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1180 // Shuffle with VMOVLPD
1181 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1182 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1183 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1184 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1187 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1189 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1190 def : Pat<(store (v4i32 (X86Movlps
1191 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1192 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1193 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1195 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1196 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1198 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1201 let Predicates = [HasSSE1] in {
1202 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1203 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1204 (iPTR 0))), addr:$src1),
1205 (MOVLPSmr addr:$src1, VR128:$src2)>;
1207 // Shuffle with MOVLPS
1208 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1209 (MOVLPSrm VR128:$src1, addr:$src2)>;
1210 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1211 (MOVLPSrm VR128:$src1, addr:$src2)>;
1212 def : Pat<(X86Movlps VR128:$src1,
1213 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1214 (MOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1219 (MOVLPSmr addr:$src1, VR128:$src2)>;
1220 def : Pat<(store (v4i32 (X86Movlps
1221 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1223 (MOVLPSmr addr:$src1, VR128:$src2)>;
1226 let Predicates = [HasSSE2] in {
1227 // Shuffle with MOVLPD
1228 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1229 (MOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1231 (MOVLPDrm VR128:$src1, addr:$src2)>;
1234 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1236 (MOVLPDmr addr:$src1, VR128:$src2)>;
1237 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1239 (MOVLPDmr addr:$src1, VR128:$src2)>;
1242 //===----------------------------------------------------------------------===//
1243 // SSE 1 & 2 - Move Hi packed FP Instructions
1244 //===----------------------------------------------------------------------===//
1246 let AddedComplexity = 20 in {
1247 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1248 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1249 IIC_SSE_MOV_LH>, VEX_4V;
1251 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1252 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1253 "\t{$src2, $dst|$dst, $src2}",
1257 // v2f64 extract element 1 is always custom lowered to unpack high to low
1258 // and extract element 0 so the non-store version isn't too horrible.
1259 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1260 "movhps\t{$src, $dst|$dst, $src}",
1261 [(store (f64 (vector_extract
1262 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1263 (bc_v2f64 (v4f32 VR128:$src))),
1264 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1265 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1266 "movhpd\t{$src, $dst|$dst, $src}",
1267 [(store (f64 (vector_extract
1268 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1269 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1270 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1271 "movhps\t{$src, $dst|$dst, $src}",
1272 [(store (f64 (vector_extract
1273 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1274 (bc_v2f64 (v4f32 VR128:$src))),
1275 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1276 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1277 "movhpd\t{$src, $dst|$dst, $src}",
1278 [(store (f64 (vector_extract
1279 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1280 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1282 let Predicates = [HasAVX] in {
1284 def : Pat<(X86Movlhps VR128:$src1,
1285 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1286 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1287 def : Pat<(X86Movlhps VR128:$src1,
1288 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1289 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1291 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1292 // is during lowering, where it's not possible to recognize the load fold
1293 // cause it has two uses through a bitcast. One use disappears at isel time
1294 // and the fold opportunity reappears.
1295 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1296 (scalar_to_vector (loadf64 addr:$src2)))),
1297 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1300 let Predicates = [HasSSE1] in {
1302 def : Pat<(X86Movlhps VR128:$src1,
1303 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1304 (MOVHPSrm VR128:$src1, addr:$src2)>;
1305 def : Pat<(X86Movlhps VR128:$src1,
1306 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1307 (MOVHPSrm VR128:$src1, addr:$src2)>;
1310 let Predicates = [HasSSE2] in {
1311 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1312 // is during lowering, where it's not possible to recognize the load fold
1313 // cause it has two uses through a bitcast. One use disappears at isel time
1314 // and the fold opportunity reappears.
1315 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1316 (scalar_to_vector (loadf64 addr:$src2)))),
1317 (MOVHPDrm VR128:$src1, addr:$src2)>;
1320 //===----------------------------------------------------------------------===//
1321 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1322 //===----------------------------------------------------------------------===//
1324 let AddedComplexity = 20 in {
1325 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1326 (ins VR128:$src1, VR128:$src2),
1327 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1329 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1332 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1333 (ins VR128:$src1, VR128:$src2),
1334 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1336 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1340 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1341 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1342 (ins VR128:$src1, VR128:$src2),
1343 "movlhps\t{$src2, $dst|$dst, $src2}",
1345 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1347 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1348 (ins VR128:$src1, VR128:$src2),
1349 "movhlps\t{$src2, $dst|$dst, $src2}",
1351 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1355 let Predicates = [HasAVX] in {
1357 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1358 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1359 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1360 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1363 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1364 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1367 let Predicates = [HasSSE1] in {
1369 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1370 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1371 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1372 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1375 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1376 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1379 //===----------------------------------------------------------------------===//
1380 // SSE 1 & 2 - Conversion Instructions
1381 //===----------------------------------------------------------------------===//
1383 def SSE_CVT_PD : OpndItins<
1384 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1387 def SSE_CVT_PS : OpndItins<
1388 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1391 def SSE_CVT_Scalar : OpndItins<
1392 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1395 def SSE_CVT_SS2SI_32 : OpndItins<
1396 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1399 def SSE_CVT_SS2SI_64 : OpndItins<
1400 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1403 def SSE_CVT_SD2SI : OpndItins<
1404 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1407 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1408 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1409 string asm, OpndItins itins> {
1410 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1411 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1413 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1414 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1418 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1419 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1420 string asm, Domain d, OpndItins itins> {
1421 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1422 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1424 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1425 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1429 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1430 X86MemOperand x86memop, string asm> {
1431 let neverHasSideEffects = 1 in {
1432 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1433 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1435 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1436 (ins DstRC:$src1, x86memop:$src),
1437 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1438 } // neverHasSideEffects = 1
1441 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1442 "cvttss2si\t{$src, $dst|$dst, $src}",
1445 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1446 "cvttss2si\t{$src, $dst|$dst, $src}",
1448 XS, VEX, VEX_W, VEX_LIG;
1449 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1450 "cvttsd2si\t{$src, $dst|$dst, $src}",
1453 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1454 "cvttsd2si\t{$src, $dst|$dst, $src}",
1456 XD, VEX, VEX_W, VEX_LIG;
1458 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1459 // register, but the same isn't true when only using memory operands,
1460 // provide other assembly "l" and "q" forms to address this explicitly
1461 // where appropriate to do so.
1462 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1463 XS, VEX_4V, VEX_LIG;
1464 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1465 XS, VEX_4V, VEX_W, VEX_LIG;
1466 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1467 XD, VEX_4V, VEX_LIG;
1468 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1469 XD, VEX_4V, VEX_LIG;
1470 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1471 XD, VEX_4V, VEX_W, VEX_LIG;
1473 let Predicates = [HasAVX], AddedComplexity = 1 in {
1474 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1475 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1476 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1477 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1478 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1479 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1480 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1481 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1483 def : Pat<(f32 (sint_to_fp GR32:$src)),
1484 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1485 def : Pat<(f32 (sint_to_fp GR64:$src)),
1486 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1487 def : Pat<(f64 (sint_to_fp GR32:$src)),
1488 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1489 def : Pat<(f64 (sint_to_fp GR64:$src)),
1490 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1493 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1494 "cvttss2si\t{$src, $dst|$dst, $src}",
1495 SSE_CVT_SS2SI_32>, XS;
1496 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1497 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1498 SSE_CVT_SS2SI_64>, XS, REX_W;
1499 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1500 "cvttsd2si\t{$src, $dst|$dst, $src}",
1502 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1503 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1504 SSE_CVT_SD2SI>, XD, REX_W;
1505 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1506 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1507 SSE_CVT_Scalar>, XS;
1508 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1509 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1510 SSE_CVT_Scalar>, XS, REX_W;
1511 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1512 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1513 SSE_CVT_Scalar>, XD;
1514 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1515 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1516 SSE_CVT_Scalar>, XD, REX_W;
1518 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1519 // and/or XMM operand(s).
1521 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1522 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1523 string asm, OpndItins itins> {
1524 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1525 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1526 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1527 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1528 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1529 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm>;
1532 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1533 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1534 PatFrag ld_frag, string asm, OpndItins itins,
1536 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1538 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1539 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1540 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1542 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1543 (ins DstRC:$src1, x86memop:$src2),
1545 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1546 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1547 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1551 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1552 f128mem, load, "cvtsd2si", SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1553 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1554 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si",
1555 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1557 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1558 f128mem, load, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1559 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1560 f128mem, load, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1563 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1564 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1565 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1566 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1567 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss",
1568 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1570 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1571 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1572 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1573 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1574 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd",
1575 SSE_CVT_Scalar, 0>, XD,
1578 let Constraints = "$src1 = $dst" in {
1579 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1580 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1581 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1582 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1583 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1584 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1585 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1586 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1587 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1588 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1589 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1590 "cvtsi2sd", SSE_CVT_Scalar>, XD, REX_W;
1595 // Aliases for intrinsics
1596 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1597 f32mem, load, "cvttss2si",
1598 SSE_CVT_SS2SI_32>, XS, VEX;
1599 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1600 int_x86_sse_cvttss2si64, f32mem, load,
1601 "cvttss2si", SSE_CVT_SS2SI_64>,
1603 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1604 f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
1606 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1607 int_x86_sse2_cvttsd2si64, f128mem, load,
1608 "cvttsd2si", SSE_CVT_SD2SI>,
1610 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1611 f32mem, load, "cvttss2si",
1612 SSE_CVT_SS2SI_32>, XS;
1613 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1614 int_x86_sse_cvttss2si64, f32mem, load,
1615 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1617 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1618 f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
1620 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1621 int_x86_sse2_cvttsd2si64, f128mem, load,
1622 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1625 let Pattern = []<dag> in {
1626 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1627 "cvtss2si{l}\t{$src, $dst|$dst, $src}",
1628 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1629 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1630 "cvtss2si\t{$src, $dst|$dst, $src}",
1631 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1632 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1633 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1634 SSEPackedSingle, SSE_CVT_PS>, TB, VEX;
1635 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1636 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1637 SSEPackedSingle, SSE_CVT_PS>, TB, VEX;
1640 let Pattern = []<dag> in {
1641 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1642 "cvtss2si{l}\t{$src, $dst|$dst, $src}",
1643 SSE_CVT_SS2SI_32>, XS;
1644 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1645 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1646 SSE_CVT_SS2SI_64>, XS, REX_W;
1647 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1648 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1649 SSEPackedSingle, SSE_CVT_PS>,
1650 TB; /* PD SSE3 form is avaiable */
1653 let Predicates = [HasAVX] in {
1654 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1655 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1656 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1657 (VCVTSS2SIrm addr:$src)>;
1658 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1659 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1660 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1661 (VCVTSS2SI64rm addr:$src)>;
1664 let Predicates = [HasSSE1] in {
1665 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1666 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1667 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1668 (CVTSS2SIrm addr:$src)>;
1669 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1670 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1671 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1672 (CVTSS2SI64rm addr:$src)>;
1677 // Convert scalar double to scalar single
1678 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1679 (ins FR64:$src1, FR64:$src2),
1680 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1681 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1683 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1684 (ins FR64:$src1, f64mem:$src2),
1685 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1686 [], IIC_SSE_CVT_Scalar_RM>,
1687 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1689 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1692 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1693 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1694 [(set FR32:$dst, (fround FR64:$src))],
1695 IIC_SSE_CVT_Scalar_RR>;
1696 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1697 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1698 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1699 IIC_SSE_CVT_Scalar_RM>,
1701 Requires<[HasSSE2, OptForSize]>;
1703 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1704 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss",
1707 let Constraints = "$src1 = $dst" in
1708 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1709 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss",
1710 SSE_CVT_Scalar>, XS;
1712 // Convert scalar single to scalar double
1713 // SSE2 instructions with XS prefix
1714 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1715 (ins FR32:$src1, FR32:$src2),
1716 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1717 [], IIC_SSE_CVT_Scalar_RR>,
1718 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1720 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1721 (ins FR32:$src1, f32mem:$src2),
1722 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1723 [], IIC_SSE_CVT_Scalar_RM>,
1724 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1726 let Predicates = [HasAVX] in {
1727 def : Pat<(f64 (fextend FR32:$src)),
1728 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1729 def : Pat<(fextend (loadf32 addr:$src)),
1730 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1731 def : Pat<(extloadf32 addr:$src),
1732 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1735 def : Pat<(extloadf32 addr:$src),
1736 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1737 Requires<[HasAVX, OptForSpeed]>;
1739 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1740 "cvtss2sd\t{$src, $dst|$dst, $src}",
1741 [(set FR64:$dst, (fextend FR32:$src))],
1742 IIC_SSE_CVT_Scalar_RR>, XS,
1743 Requires<[HasSSE2]>;
1744 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1745 "cvtss2sd\t{$src, $dst|$dst, $src}",
1746 [(set FR64:$dst, (extloadf32 addr:$src))],
1747 IIC_SSE_CVT_Scalar_RM>, XS,
1748 Requires<[HasSSE2, OptForSize]>;
1750 // extload f32 -> f64. This matches load+fextend because we have a hack in
1751 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1753 // Since these loads aren't folded into the fextend, we have to match it
1755 def : Pat<(fextend (loadf32 addr:$src)),
1756 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1757 def : Pat<(extloadf32 addr:$src),
1758 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1760 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1761 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1762 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1763 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1765 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V,
1767 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1768 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1769 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1770 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1771 (load addr:$src2)))],
1772 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V,
1774 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1775 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1776 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1777 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1778 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1780 IIC_SSE_CVT_Scalar_RR>, XS,
1781 Requires<[HasSSE2]>;
1782 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1783 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1784 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1785 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1786 (load addr:$src2)))],
1787 IIC_SSE_CVT_Scalar_RM>, XS,
1788 Requires<[HasSSE2]>;
1791 // Convert doubleword to packed single/double fp
1792 // SSE2 instructions without OpSize prefix
1793 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1794 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1795 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))],
1797 TB, VEX, Requires<[HasAVX]>;
1798 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1799 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1800 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1801 (bitconvert (memopv2i64 addr:$src))))],
1803 TB, VEX, Requires<[HasAVX]>;
1804 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1805 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1806 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))],
1808 TB, Requires<[HasSSE2]>;
1809 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1810 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1811 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1812 (bitconvert (memopv2i64 addr:$src))))],
1814 TB, Requires<[HasSSE2]>;
1817 // Convert packed single/double fp to doubleword
1818 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1819 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1820 IIC_SSE_CVT_PS_RR>, VEX;
1821 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1822 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1823 IIC_SSE_CVT_PS_RM>, VEX;
1824 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1825 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1826 IIC_SSE_CVT_PS_RR>, VEX;
1827 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1828 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1829 IIC_SSE_CVT_PS_RM>, VEX;
1830 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1831 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1833 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1834 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1837 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1838 "cvtps2dq\t{$src, $dst|$dst, $src}",
1839 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1842 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1844 "cvtps2dq\t{$src, $dst|$dst, $src}",
1845 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1846 (memop addr:$src)))],
1847 IIC_SSE_CVT_PS_RM>, VEX;
1848 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1849 "cvtps2dq\t{$src, $dst|$dst, $src}",
1850 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1852 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1853 "cvtps2dq\t{$src, $dst|$dst, $src}",
1854 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1855 (memop addr:$src)))],
1858 // Convert Packed Double FP to Packed DW Integers
1859 let Predicates = [HasAVX] in {
1860 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1861 // register, but the same isn't true when using memory operands instead.
1862 // Provide other assembly rr and rm forms to address this explicitly.
1863 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1864 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1865 def VCVTPD2DQXrYr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1866 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1869 def VCVTPD2DQXrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1870 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1871 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1872 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1875 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1876 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX;
1877 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1878 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1881 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1882 "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
1884 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1885 "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
1888 // SSE2 packed instructions with XD prefix
1889 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1890 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1891 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1893 XD, VEX, Requires<[HasAVX]>;
1894 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1895 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1896 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1897 (memop addr:$src)))],
1899 XD, VEX, Requires<[HasAVX]>;
1900 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1901 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1902 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1904 XD, Requires<[HasSSE2]>;
1905 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1906 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1907 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1908 (memop addr:$src)))],
1910 XD, Requires<[HasSSE2]>;
1913 // Convert with truncation packed single/double fp to doubleword
1914 // SSE2 packed instructions with XS prefix
1915 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1916 "cvttps2dq\t{$src, $dst|$dst, $src}",
1918 (int_x86_sse2_cvttps2dq VR128:$src))],
1919 IIC_SSE_CVT_PS_RR>, VEX;
1920 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1921 "cvttps2dq\t{$src, $dst|$dst, $src}",
1922 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1923 (memop addr:$src)))],
1924 IIC_SSE_CVT_PS_RM>, VEX;
1925 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1926 "cvttps2dq\t{$src, $dst|$dst, $src}",
1928 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1929 IIC_SSE_CVT_PS_RR>, VEX;
1930 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1931 "cvttps2dq\t{$src, $dst|$dst, $src}",
1932 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1933 (memopv8f32 addr:$src)))],
1934 IIC_SSE_CVT_PS_RM>, VEX;
1936 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1937 "cvttps2dq\t{$src, $dst|$dst, $src}",
1939 (int_x86_sse2_cvttps2dq VR128:$src))],
1941 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1942 "cvttps2dq\t{$src, $dst|$dst, $src}",
1944 (int_x86_sse2_cvttps2dq (memop addr:$src)))],
1947 let Predicates = [HasAVX] in {
1948 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1949 (Int_VCVTDQ2PSrr VR128:$src)>;
1950 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1951 (Int_VCVTDQ2PSrm addr:$src)>;
1953 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1954 (VCVTTPS2DQrr VR128:$src)>;
1955 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1956 (VCVTTPS2DQrm addr:$src)>;
1958 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1959 (VCVTDQ2PSYrr VR256:$src)>;
1960 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1961 (VCVTDQ2PSYrm addr:$src)>;
1963 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1964 (VCVTTPS2DQYrr VR256:$src)>;
1965 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1966 (VCVTTPS2DQYrm addr:$src)>;
1969 let Predicates = [HasSSE2] in {
1970 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1971 (Int_CVTDQ2PSrr VR128:$src)>;
1972 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1973 (Int_CVTDQ2PSrm addr:$src)>;
1975 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1976 (CVTTPS2DQrr VR128:$src)>;
1977 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1978 (CVTTPS2DQrm addr:$src)>;
1981 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1982 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1984 (int_x86_sse2_cvttpd2dq VR128:$src))],
1985 IIC_SSE_CVT_PD_RR>, VEX;
1986 let isCodeGenOnly = 1 in
1987 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1988 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1989 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1990 (memop addr:$src)))],
1991 IIC_SSE_CVT_PD_RM>, VEX;
1992 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1993 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1994 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1996 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1997 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1998 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1999 (memop addr:$src)))],
2002 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2003 // register, but the same isn't true when using memory operands instead.
2004 // Provide other assembly rr and rm forms to address this explicitly.
2005 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2006 "cvttpd2dq\t{$src, $dst|$dst, $src}", [],
2007 IIC_SSE_CVT_PD_RR>, VEX;
2010 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2011 "cvttpd2dqx\t{$src, $dst|$dst, $src}", [],
2012 IIC_SSE_CVT_PD_RR>, VEX;
2013 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2014 "cvttpd2dqx\t{$src, $dst|$dst, $src}", [],
2015 IIC_SSE_CVT_PD_RM>, VEX;
2018 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2019 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [],
2020 IIC_SSE_CVT_PD_RR>, VEX;
2021 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2022 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [],
2023 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2025 let Predicates = [HasAVX] in {
2026 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2027 (VCVTTPD2DQYrr VR256:$src)>;
2028 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
2029 (VCVTTPD2DQYrm addr:$src)>;
2030 } // Predicates = [HasAVX]
2032 // Convert packed single to packed double
2033 let Predicates = [HasAVX] in {
2034 // SSE2 instructions without OpSize prefix
2035 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2036 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2037 IIC_SSE_CVT_PD_RR>, TB, VEX;
2038 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2039 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2040 IIC_SSE_CVT_PD_RM>, TB, VEX;
2041 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2042 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2043 IIC_SSE_CVT_PD_RR>, TB, VEX;
2044 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2045 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2046 IIC_SSE_CVT_PD_RM>, TB, VEX;
2048 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2049 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2050 IIC_SSE_CVT_PD_RR>, TB;
2051 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2052 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2053 IIC_SSE_CVT_PD_RM>, TB;
2055 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2056 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2057 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2059 TB, VEX, Requires<[HasAVX]>;
2060 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2061 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2062 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
2063 (load addr:$src)))],
2065 TB, VEX, Requires<[HasAVX]>;
2066 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2067 "cvtps2pd\t{$src, $dst|$dst, $src}",
2068 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2070 TB, Requires<[HasSSE2]>;
2071 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2072 "cvtps2pd\t{$src, $dst|$dst, $src}",
2073 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
2074 (load addr:$src)))],
2076 TB, Requires<[HasSSE2]>;
2078 // Convert Packed DW Integers to Packed Double FP
2079 let Predicates = [HasAVX] in {
2080 def VCVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2081 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
2082 def VCVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2083 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
2084 def VCVTDQ2PDYrm : SSDI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2085 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
2086 def VCVTDQ2PDYrr : SSDI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2087 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
2090 def CVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2091 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2093 def CVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2094 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2097 // 128 bit register conversion intrinsics
2098 let Predicates = [HasAVX] in
2099 def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),
2100 (VCVTDQ2PDrr VR128:$src)>;
2102 let Predicates = [HasSSE2] in
2103 def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),
2104 (CVTDQ2PDrr VR128:$src)>;
2106 // AVX 256-bit register conversion intrinsics
2107 let Predicates = [HasAVX] in {
2108 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
2109 (VCVTDQ2PDYrr VR128:$src)>;
2110 def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
2111 (VCVTDQ2PDYrm addr:$src)>;
2113 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
2114 (VCVTPD2DQYrr VR256:$src)>;
2115 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
2116 (VCVTPD2DQYrm addr:$src)>;
2118 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2119 (VCVTDQ2PDYrr VR128:$src)>;
2120 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2121 (VCVTDQ2PDYrm addr:$src)>;
2122 } // Predicates = [HasAVX]
2124 // Convert packed double to packed single
2125 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2126 // register, but the same isn't true when using memory operands instead.
2127 // Provide other assembly rr and rm forms to address this explicitly.
2128 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2129 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2130 IIC_SSE_CVT_PD_RR>, VEX;
2131 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2132 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2133 IIC_SSE_CVT_PD_RR>, VEX;
2136 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2137 "cvtpd2psx\t{$src, $dst|$dst, $src}", [],
2138 IIC_SSE_CVT_PD_RR>, VEX;
2139 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2140 "cvtpd2psx\t{$src, $dst|$dst, $src}", [],
2141 IIC_SSE_CVT_PD_RM>, VEX;
2144 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2145 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", [],
2146 IIC_SSE_CVT_PD_RR>, VEX;
2147 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2148 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", [],
2149 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2150 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2151 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2153 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2154 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2158 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2159 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2160 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2162 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
2164 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2165 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
2166 (memop addr:$src)))],
2168 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2169 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2170 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2172 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2173 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2174 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
2175 (memop addr:$src)))],
2178 // AVX 256-bit register conversion intrinsics
2179 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2180 // whenever possible to avoid declaring two versions of each one.
2181 let Predicates = [HasAVX] in {
2182 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2183 (VCVTDQ2PSYrr VR256:$src)>;
2184 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2185 (VCVTDQ2PSYrm addr:$src)>;
2187 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
2188 (VCVTPD2PSYrr VR256:$src)>;
2189 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
2190 (VCVTPD2PSYrm addr:$src)>;
2192 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
2193 (VCVTPS2DQYrr VR256:$src)>;
2194 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
2195 (VCVTPS2DQYrm addr:$src)>;
2197 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
2198 (VCVTPS2PDYrr VR128:$src)>;
2199 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
2200 (VCVTPS2PDYrm addr:$src)>;
2202 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
2203 (VCVTTPD2DQYrr VR256:$src)>;
2204 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
2205 (VCVTTPD2DQYrm addr:$src)>;
2207 // Match fround and fextend for 128/256-bit conversions
2208 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2209 (VCVTPD2PSYrr VR256:$src)>;
2210 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2211 (VCVTPD2PSYrm addr:$src)>;
2213 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2214 (VCVTPS2PDYrr VR128:$src)>;
2215 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
2216 (VCVTPS2PDYrm addr:$src)>;
2219 //===----------------------------------------------------------------------===//
2220 // SSE 1 & 2 - Compare Instructions
2221 //===----------------------------------------------------------------------===//
2223 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2224 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2225 Operand CC, SDNode OpNode, ValueType VT,
2226 PatFrag ld_frag, string asm, string asm_alt,
2228 def rr : SIi8<0xC2, MRMSrcReg,
2229 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2230 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2232 def rm : SIi8<0xC2, MRMSrcMem,
2233 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2234 [(set RC:$dst, (OpNode (VT RC:$src1),
2235 (ld_frag addr:$src2), imm:$cc))],
2238 // Accept explicit immediate argument form instead of comparison code.
2239 let neverHasSideEffects = 1 in {
2240 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2241 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2242 IIC_SSE_ALU_F32S_RR>;
2244 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2245 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2246 IIC_SSE_ALU_F32S_RM>;
2250 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2251 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2252 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2254 XS, VEX_4V, VEX_LIG;
2255 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2256 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2257 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2258 SSE_ALU_F32S>, // same latency as 32 bit compare
2259 XD, VEX_4V, VEX_LIG;
2261 let Constraints = "$src1 = $dst" in {
2262 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2263 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2264 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2266 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2267 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2268 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2269 SSE_ALU_F32S>, // same latency as 32 bit compare
2273 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2274 Intrinsic Int, string asm, OpndItins itins> {
2275 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2276 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2277 [(set VR128:$dst, (Int VR128:$src1,
2278 VR128:$src, imm:$cc))],
2280 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2281 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2282 [(set VR128:$dst, (Int VR128:$src1,
2283 (load addr:$src), imm:$cc))],
2287 // Aliases to match intrinsics which expect XMM operand(s).
2288 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2289 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2292 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2293 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2294 SSE_ALU_F32S>, // same latency as f32
2296 let Constraints = "$src1 = $dst" in {
2297 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2298 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2300 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2301 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2302 SSE_ALU_F32S>, // same latency as f32
2307 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2308 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2309 ValueType vt, X86MemOperand x86memop,
2310 PatFrag ld_frag, string OpcodeStr, Domain d> {
2311 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2312 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2313 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2314 IIC_SSE_COMIS_RR, d>;
2315 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2316 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2317 [(set EFLAGS, (OpNode (vt RC:$src1),
2318 (ld_frag addr:$src2)))],
2319 IIC_SSE_COMIS_RM, d>;
2322 let Defs = [EFLAGS] in {
2323 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2324 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2325 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2326 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2328 let Pattern = []<dag> in {
2329 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2330 "comiss", SSEPackedSingle>, TB, VEX,
2332 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2333 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2337 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2338 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2339 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2340 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2342 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2343 load, "comiss", SSEPackedSingle>, TB, VEX;
2344 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2345 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2346 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2347 "ucomiss", SSEPackedSingle>, TB;
2348 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2349 "ucomisd", SSEPackedDouble>, TB, OpSize;
2351 let Pattern = []<dag> in {
2352 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2353 "comiss", SSEPackedSingle>, TB;
2354 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2355 "comisd", SSEPackedDouble>, TB, OpSize;
2358 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2359 load, "ucomiss", SSEPackedSingle>, TB;
2360 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2361 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2363 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2364 "comiss", SSEPackedSingle>, TB;
2365 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2366 "comisd", SSEPackedDouble>, TB, OpSize;
2367 } // Defs = [EFLAGS]
2369 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2370 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2371 Operand CC, Intrinsic Int, string asm,
2372 string asm_alt, Domain d> {
2373 def rri : PIi8<0xC2, MRMSrcReg,
2374 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2375 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2376 IIC_SSE_CMPP_RR, d>;
2377 def rmi : PIi8<0xC2, MRMSrcMem,
2378 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2379 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2380 IIC_SSE_CMPP_RM, d>;
2382 // Accept explicit immediate argument form instead of comparison code.
2383 let neverHasSideEffects = 1 in {
2384 def rri_alt : PIi8<0xC2, MRMSrcReg,
2385 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2386 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2387 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2388 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2389 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2393 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2394 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2395 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2396 SSEPackedSingle>, TB, VEX_4V;
2397 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2398 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2399 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2400 SSEPackedDouble>, TB, OpSize, VEX_4V;
2401 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2402 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2403 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2404 SSEPackedSingle>, TB, VEX_4V;
2405 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2406 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2407 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2408 SSEPackedDouble>, TB, OpSize, VEX_4V;
2409 let Constraints = "$src1 = $dst" in {
2410 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2411 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2412 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2413 SSEPackedSingle>, TB;
2414 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2415 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2416 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2417 SSEPackedDouble>, TB, OpSize;
2420 let Predicates = [HasAVX] in {
2421 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2422 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2423 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2424 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2425 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2426 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2427 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2428 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2430 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2431 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2432 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2433 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2434 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2435 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2436 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2437 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2440 let Predicates = [HasSSE1] in {
2441 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2442 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2443 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2444 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2447 let Predicates = [HasSSE2] in {
2448 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2449 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2450 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2451 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2454 //===----------------------------------------------------------------------===//
2455 // SSE 1 & 2 - Shuffle Instructions
2456 //===----------------------------------------------------------------------===//
2458 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2459 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2460 ValueType vt, string asm, PatFrag mem_frag,
2461 Domain d, bit IsConvertibleToThreeAddress = 0> {
2462 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2463 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2464 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2465 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2466 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2467 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2468 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2469 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2470 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2473 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2474 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2475 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2476 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2477 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2478 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2479 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2480 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2481 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2482 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2483 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2484 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2486 let Constraints = "$src1 = $dst" in {
2487 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2488 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2489 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2491 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2492 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2493 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2497 let Predicates = [HasAVX] in {
2498 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2499 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2500 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2501 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2502 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2504 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2505 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2506 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2507 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2508 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2511 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2512 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2513 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2514 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2515 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2517 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2518 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2519 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2520 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2521 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2524 let Predicates = [HasSSE1] in {
2525 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2526 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2527 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2528 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2529 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2532 let Predicates = [HasSSE2] in {
2533 // Generic SHUFPD patterns
2534 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2535 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2536 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2537 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2538 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2541 //===----------------------------------------------------------------------===//
2542 // SSE 1 & 2 - Unpack Instructions
2543 //===----------------------------------------------------------------------===//
2545 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2546 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2547 PatFrag mem_frag, RegisterClass RC,
2548 X86MemOperand x86memop, string asm,
2550 def rr : PI<opc, MRMSrcReg,
2551 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2553 (vt (OpNode RC:$src1, RC:$src2)))],
2555 def rm : PI<opc, MRMSrcMem,
2556 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2558 (vt (OpNode RC:$src1,
2559 (mem_frag addr:$src2))))],
2563 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2564 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2565 SSEPackedSingle>, TB, VEX_4V;
2566 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2567 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2568 SSEPackedDouble>, TB, OpSize, VEX_4V;
2569 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2570 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2571 SSEPackedSingle>, TB, VEX_4V;
2572 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2573 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2574 SSEPackedDouble>, TB, OpSize, VEX_4V;
2576 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2577 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2578 SSEPackedSingle>, TB, VEX_4V;
2579 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2580 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2581 SSEPackedDouble>, TB, OpSize, VEX_4V;
2582 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2583 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2584 SSEPackedSingle>, TB, VEX_4V;
2585 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2586 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2587 SSEPackedDouble>, TB, OpSize, VEX_4V;
2589 let Constraints = "$src1 = $dst" in {
2590 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2591 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2592 SSEPackedSingle>, TB;
2593 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2594 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2595 SSEPackedDouble>, TB, OpSize;
2596 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2597 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2598 SSEPackedSingle>, TB;
2599 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2600 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2601 SSEPackedDouble>, TB, OpSize;
2602 } // Constraints = "$src1 = $dst"
2604 let Predicates = [HasAVX], AddedComplexity = 1 in {
2605 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2606 // problem is during lowering, where it's not possible to recognize the load
2607 // fold cause it has two uses through a bitcast. One use disappears at isel
2608 // time and the fold opportunity reappears.
2609 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2610 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2613 let Predicates = [HasSSE2] in {
2614 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2615 // problem is during lowering, where it's not possible to recognize the load
2616 // fold cause it has two uses through a bitcast. One use disappears at isel
2617 // time and the fold opportunity reappears.
2618 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2619 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2622 //===----------------------------------------------------------------------===//
2623 // SSE 1 & 2 - Extract Floating-Point Sign mask
2624 //===----------------------------------------------------------------------===//
2626 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2627 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2629 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2630 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2631 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2632 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2633 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2634 IIC_SSE_MOVMSK, d>, REX_W;
2637 let Predicates = [HasAVX] in {
2638 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2639 "movmskps", SSEPackedSingle>, TB, VEX;
2640 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2641 "movmskpd", SSEPackedDouble>, TB,
2643 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2644 "movmskps", SSEPackedSingle>, TB, VEX;
2645 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2646 "movmskpd", SSEPackedDouble>, TB,
2649 def : Pat<(i32 (X86fgetsign FR32:$src)),
2650 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2652 def : Pat<(i64 (X86fgetsign FR32:$src)),
2653 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2655 def : Pat<(i32 (X86fgetsign FR64:$src)),
2656 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2658 def : Pat<(i64 (X86fgetsign FR64:$src)),
2659 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2663 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2664 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2665 SSEPackedSingle>, TB, VEX;
2666 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2667 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2668 SSEPackedDouble>, TB,
2670 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2671 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2672 SSEPackedSingle>, TB, VEX;
2673 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2674 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2675 SSEPackedDouble>, TB,
2679 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2680 SSEPackedSingle>, TB;
2681 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2682 SSEPackedDouble>, TB, OpSize;
2684 def : Pat<(i32 (X86fgetsign FR32:$src)),
2685 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2686 sub_ss))>, Requires<[HasSSE1]>;
2687 def : Pat<(i64 (X86fgetsign FR32:$src)),
2688 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2689 sub_ss))>, Requires<[HasSSE1]>;
2690 def : Pat<(i32 (X86fgetsign FR64:$src)),
2691 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2692 sub_sd))>, Requires<[HasSSE2]>;
2693 def : Pat<(i64 (X86fgetsign FR64:$src)),
2694 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2695 sub_sd))>, Requires<[HasSSE2]>;
2697 //===---------------------------------------------------------------------===//
2698 // SSE2 - Packed Integer Logical Instructions
2699 //===---------------------------------------------------------------------===//
2701 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2703 /// PDI_binop_rm - Simple SSE2 binary operator.
2704 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2705 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2706 X86MemOperand x86memop,
2708 bit IsCommutable = 0,
2710 let isCommutable = IsCommutable in
2711 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2712 (ins RC:$src1, RC:$src2),
2714 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2715 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2716 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2717 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2718 (ins RC:$src1, x86memop:$src2),
2720 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2721 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2722 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2723 (bitconvert (memop_frag addr:$src2)))))],
2726 } // ExeDomain = SSEPackedInt
2728 // These are ordered here for pattern ordering requirements with the fp versions
2730 let Predicates = [HasAVX] in {
2731 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2732 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2733 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2734 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2735 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2736 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2737 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2738 i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2741 let Constraints = "$src1 = $dst" in {
2742 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2743 i128mem, SSE_BIT_ITINS_P, 1>;
2744 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2745 i128mem, SSE_BIT_ITINS_P, 1>;
2746 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2747 i128mem, SSE_BIT_ITINS_P, 1>;
2748 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2749 i128mem, SSE_BIT_ITINS_P, 0>;
2750 } // Constraints = "$src1 = $dst"
2752 let Predicates = [HasAVX2] in {
2753 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2754 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2755 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2756 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2757 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2758 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2759 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2760 i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2763 //===----------------------------------------------------------------------===//
2764 // SSE 1 & 2 - Logical Instructions
2765 //===----------------------------------------------------------------------===//
2767 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2769 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2770 SDNode OpNode, OpndItins itins> {
2771 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2772 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2775 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2776 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2779 let Constraints = "$src1 = $dst" in {
2780 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2781 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2784 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2785 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2790 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2791 let mayLoad = 0 in {
2792 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2794 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2796 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2800 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2801 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2804 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2806 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2808 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2809 // are all promoted to v2i64, and the patterns are covered by the int
2810 // version. This is needed in SSE only, because v2i64 isn't supported on
2811 // SSE1, but only on SSE2.
2812 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2813 !strconcat(OpcodeStr, "ps"), f128mem, [],
2814 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2815 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2817 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2818 !strconcat(OpcodeStr, "pd"), f128mem,
2819 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2820 (bc_v2i64 (v2f64 VR128:$src2))))],
2821 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2822 (memopv2i64 addr:$src2)))], 0>,
2824 let Constraints = "$src1 = $dst" in {
2825 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2826 !strconcat(OpcodeStr, "ps"), f128mem,
2827 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2828 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2829 (memopv2i64 addr:$src2)))]>, TB;
2831 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2832 !strconcat(OpcodeStr, "pd"), f128mem,
2833 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2834 (bc_v2i64 (v2f64 VR128:$src2))))],
2835 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2836 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2840 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2842 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2844 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2845 !strconcat(OpcodeStr, "ps"), f256mem,
2846 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2847 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2848 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2850 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2851 !strconcat(OpcodeStr, "pd"), f256mem,
2852 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2853 (bc_v4i64 (v4f64 VR256:$src2))))],
2854 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2855 (memopv4i64 addr:$src2)))], 0>,
2859 // AVX 256-bit packed logical ops forms
2860 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2861 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2862 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2863 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2865 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2866 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2867 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2868 let isCommutable = 0 in
2869 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2871 //===----------------------------------------------------------------------===//
2872 // SSE 1 & 2 - Arithmetic Instructions
2873 //===----------------------------------------------------------------------===//
2875 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2878 /// In addition, we also have a special variant of the scalar form here to
2879 /// represent the associated intrinsic operation. This form is unlike the
2880 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2881 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2883 /// These three forms can each be reg+reg or reg+mem.
2886 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2888 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2891 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2892 OpNode, FR32, f32mem,
2893 itins.s, Is2Addr>, XS;
2894 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2895 OpNode, FR64, f64mem,
2896 itins.d, Is2Addr>, XD;
2899 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2902 let mayLoad = 0 in {
2903 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2904 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2906 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2907 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2912 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2915 let mayLoad = 0 in {
2916 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2917 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2919 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2920 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2925 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2928 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2929 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2930 itins.s, Is2Addr>, XS;
2931 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2932 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2933 itins.d, Is2Addr>, XD;
2936 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2939 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2940 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2941 SSEPackedSingle, itins.s, Is2Addr>,
2944 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2945 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2946 SSEPackedDouble, itins.d, Is2Addr>,
2950 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2952 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2953 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2954 SSEPackedSingle, itins.s, 0>, TB;
2956 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2957 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2958 SSEPackedDouble, itins.d, 0>, TB, OpSize;
2961 // Binary Arithmetic instructions
2962 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2963 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2965 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2966 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2968 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2969 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2971 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2972 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2975 let isCommutable = 0 in {
2976 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2977 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2979 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2980 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>, VEX_4V;
2981 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2982 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2984 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2985 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2987 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2988 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2990 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2991 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2992 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2993 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2995 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2996 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2998 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2999 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
3000 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
3001 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3005 let Constraints = "$src1 = $dst" in {
3006 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3007 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3008 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3009 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3010 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3011 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3013 let isCommutable = 0 in {
3014 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3015 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3016 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3017 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3018 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3019 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3020 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3021 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3022 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
3023 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
3024 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3025 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3026 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
3027 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
3032 /// In addition, we also have a special variant of the scalar form here to
3033 /// represent the associated intrinsic operation. This form is unlike the
3034 /// plain scalar form, in that it takes an entire vector (instead of a
3035 /// scalar) and leaves the top elements undefined.
3037 /// And, we have a special variant form for a full-vector intrinsic form.
3039 def SSE_SQRTP : OpndItins<
3040 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
3043 def SSE_SQRTS : OpndItins<
3044 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
3047 def SSE_RCPP : OpndItins<
3048 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3051 def SSE_RCPS : OpndItins<
3052 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3055 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3056 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3057 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3058 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3059 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3060 [(set FR32:$dst, (OpNode FR32:$src))]>;
3061 // For scalar unary operations, fold a load into the operation
3062 // only in OptForSize mode. It eliminates an instruction, but it also
3063 // eliminates a whole-register clobber (the load), so it introduces a
3064 // partial register update condition.
3065 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3066 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3067 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3068 Requires<[HasSSE1, OptForSize]>;
3069 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3070 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3071 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
3072 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3073 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3074 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
3077 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
3078 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3079 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
3080 !strconcat(OpcodeStr,
3081 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3083 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
3084 !strconcat(OpcodeStr,
3085 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3086 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3087 (ins VR128:$src1, ssmem:$src2),
3088 !strconcat(OpcodeStr,
3089 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3092 /// sse1_fp_unop_p - SSE1 unops in packed form.
3093 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3095 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3096 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3097 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3098 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3099 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3100 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3103 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3104 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3106 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3107 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3108 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3110 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3111 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3112 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3116 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3117 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3118 Intrinsic V4F32Int, OpndItins itins> {
3119 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3120 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3121 [(set VR128:$dst, (V4F32Int VR128:$src))],
3123 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3124 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3125 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3129 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3130 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3131 Intrinsic V4F32Int, OpndItins itins> {
3132 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3133 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3134 [(set VR256:$dst, (V4F32Int VR256:$src))],
3136 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3137 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3138 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3142 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3143 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3144 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3145 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3146 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3147 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3148 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3149 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3150 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3151 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3152 Requires<[HasSSE2, OptForSize]>;
3153 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3154 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3155 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3156 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3157 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3158 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3161 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3162 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3163 let neverHasSideEffects = 1 in {
3164 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3165 !strconcat(OpcodeStr,
3166 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3168 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3169 !strconcat(OpcodeStr,
3170 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3172 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3173 (ins VR128:$src1, sdmem:$src2),
3174 !strconcat(OpcodeStr,
3175 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3178 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3179 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3180 SDNode OpNode, OpndItins itins> {
3181 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3182 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3183 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3184 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3185 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3186 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3189 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3190 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3192 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3193 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3194 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3196 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3197 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3198 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3202 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3203 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3204 Intrinsic V2F64Int, OpndItins itins> {
3205 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3206 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3207 [(set VR128:$dst, (V2F64Int VR128:$src))],
3209 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3210 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3211 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3215 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3216 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3217 Intrinsic V2F64Int, OpndItins itins> {
3218 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3219 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3220 [(set VR256:$dst, (V2F64Int VR256:$src))],
3222 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3223 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3224 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3228 let Predicates = [HasAVX] in {
3230 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3231 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3233 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3234 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3235 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3236 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3237 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3239 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3241 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3243 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3247 // Reciprocal approximations. Note that these typically require refinement
3248 // in order to obtain suitable precision.
3249 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3250 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3251 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3252 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3254 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3257 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3258 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3259 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3260 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3262 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3266 let AddedComplexity = 1 in {
3267 def : Pat<(f32 (fsqrt FR32:$src)),
3268 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3269 def : Pat<(f32 (fsqrt (load addr:$src))),
3270 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3271 Requires<[HasAVX, OptForSize]>;
3272 def : Pat<(f64 (fsqrt FR64:$src)),
3273 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3274 def : Pat<(f64 (fsqrt (load addr:$src))),
3275 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3276 Requires<[HasAVX, OptForSize]>;
3278 def : Pat<(f32 (X86frsqrt FR32:$src)),
3279 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3280 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3281 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3282 Requires<[HasAVX, OptForSize]>;
3284 def : Pat<(f32 (X86frcp FR32:$src)),
3285 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3286 def : Pat<(f32 (X86frcp (load addr:$src))),
3287 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3288 Requires<[HasAVX, OptForSize]>;
3291 let Predicates = [HasAVX], AddedComplexity = 1 in {
3292 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3293 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3294 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3295 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3297 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3298 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3300 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3301 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3302 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3303 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3305 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3306 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3308 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3309 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3310 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3311 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3313 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3314 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3316 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3317 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3318 (VRCPSSr (f32 (IMPLICIT_DEF)),
3319 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3321 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3322 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3326 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3328 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3329 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3330 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3332 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3333 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3335 // Reciprocal approximations. Note that these typically require refinement
3336 // in order to obtain suitable precision.
3337 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3339 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3340 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3342 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3344 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3345 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3347 // There is no f64 version of the reciprocal approximation instructions.
3349 //===----------------------------------------------------------------------===//
3350 // SSE 1 & 2 - Non-temporal stores
3351 //===----------------------------------------------------------------------===//
3353 let AddedComplexity = 400 in { // Prefer non-temporal versions
3354 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3355 (ins f128mem:$dst, VR128:$src),
3356 "movntps\t{$src, $dst|$dst, $src}",
3357 [(alignednontemporalstore (v4f32 VR128:$src),
3359 IIC_SSE_MOVNT>, VEX;
3360 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3361 (ins f128mem:$dst, VR128:$src),
3362 "movntpd\t{$src, $dst|$dst, $src}",
3363 [(alignednontemporalstore (v2f64 VR128:$src),
3365 IIC_SSE_MOVNT>, VEX;
3367 let ExeDomain = SSEPackedInt in
3368 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3369 (ins f128mem:$dst, VR128:$src),
3370 "movntdq\t{$src, $dst|$dst, $src}",
3371 [(alignednontemporalstore (v2i64 VR128:$src),
3373 IIC_SSE_MOVNT>, VEX;
3375 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3376 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3378 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3379 (ins f256mem:$dst, VR256:$src),
3380 "movntps\t{$src, $dst|$dst, $src}",
3381 [(alignednontemporalstore (v8f32 VR256:$src),
3383 IIC_SSE_MOVNT>, VEX;
3384 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3385 (ins f256mem:$dst, VR256:$src),
3386 "movntpd\t{$src, $dst|$dst, $src}",
3387 [(alignednontemporalstore (v4f64 VR256:$src),
3389 IIC_SSE_MOVNT>, VEX;
3390 let ExeDomain = SSEPackedInt in
3391 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3392 (ins f256mem:$dst, VR256:$src),
3393 "movntdq\t{$src, $dst|$dst, $src}",
3394 [(alignednontemporalstore (v4i64 VR256:$src),
3396 IIC_SSE_MOVNT>, VEX;
3399 let AddedComplexity = 400 in { // Prefer non-temporal versions
3400 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3401 "movntps\t{$src, $dst|$dst, $src}",
3402 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3404 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3405 "movntpd\t{$src, $dst|$dst, $src}",
3406 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3409 let ExeDomain = SSEPackedInt in
3410 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3411 "movntdq\t{$src, $dst|$dst, $src}",
3412 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3415 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3416 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3418 // There is no AVX form for instructions below this point
3419 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3420 "movnti{l}\t{$src, $dst|$dst, $src}",
3421 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3423 TB, Requires<[HasSSE2]>;
3424 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3425 "movnti{q}\t{$src, $dst|$dst, $src}",
3426 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3428 TB, Requires<[HasSSE2]>;
3431 //===----------------------------------------------------------------------===//
3432 // SSE 1 & 2 - Prefetch and memory fence
3433 //===----------------------------------------------------------------------===//
3435 // Prefetch intrinsic.
3436 let Predicates = [HasSSE1] in {
3437 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3438 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3439 IIC_SSE_PREFETCH>, TB;
3440 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3441 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3442 IIC_SSE_PREFETCH>, TB;
3443 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3444 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3445 IIC_SSE_PREFETCH>, TB;
3446 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3447 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3448 IIC_SSE_PREFETCH>, TB;
3452 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3453 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3454 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3456 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3457 // was introduced with SSE2, it's backward compatible.
3458 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3460 // Load, store, and memory fence
3461 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3462 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3463 TB, Requires<[HasSSE1]>;
3464 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3465 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3466 TB, Requires<[HasSSE2]>;
3467 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3468 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3469 TB, Requires<[HasSSE2]>;
3471 def : Pat<(X86SFence), (SFENCE)>;
3472 def : Pat<(X86LFence), (LFENCE)>;
3473 def : Pat<(X86MFence), (MFENCE)>;
3475 //===----------------------------------------------------------------------===//
3476 // SSE 1 & 2 - Load/Store XCSR register
3477 //===----------------------------------------------------------------------===//
3479 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3480 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3481 IIC_SSE_LDMXCSR>, VEX;
3482 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3483 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3484 IIC_SSE_STMXCSR>, VEX;
3486 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3487 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3489 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3490 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3493 //===---------------------------------------------------------------------===//
3494 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3495 //===---------------------------------------------------------------------===//
3497 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3499 let neverHasSideEffects = 1 in {
3500 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3501 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3503 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3504 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3507 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3508 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3510 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3511 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3515 let isCodeGenOnly = 1 in {
3516 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3517 "movdqa\t{$src, $dst|$dst, $src}", [],
3520 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3521 "movdqa\t{$src, $dst|$dst, $src}", [],
3524 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3525 "movdqu\t{$src, $dst|$dst, $src}", [],
3528 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3529 "movdqu\t{$src, $dst|$dst, $src}", [],
3534 let canFoldAsLoad = 1, mayLoad = 1 in {
3535 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3536 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3538 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3539 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3541 let Predicates = [HasAVX] in {
3542 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3543 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3545 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3546 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3551 let mayStore = 1 in {
3552 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3553 (ins i128mem:$dst, VR128:$src),
3554 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3556 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3557 (ins i256mem:$dst, VR256:$src),
3558 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3560 let Predicates = [HasAVX] in {
3561 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3562 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3564 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3565 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3570 let neverHasSideEffects = 1 in
3571 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3572 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3574 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3575 "movdqu\t{$src, $dst|$dst, $src}",
3576 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3579 let isCodeGenOnly = 1 in {
3580 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3581 "movdqa\t{$src, $dst|$dst, $src}", [],
3584 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3585 "movdqu\t{$src, $dst|$dst, $src}",
3586 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3589 let canFoldAsLoad = 1, mayLoad = 1 in {
3590 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3591 "movdqa\t{$src, $dst|$dst, $src}",
3592 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3594 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3595 "movdqu\t{$src, $dst|$dst, $src}",
3596 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3598 XS, Requires<[HasSSE2]>;
3601 let mayStore = 1 in {
3602 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3603 "movdqa\t{$src, $dst|$dst, $src}",
3604 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3606 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3607 "movdqu\t{$src, $dst|$dst, $src}",
3608 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3610 XS, Requires<[HasSSE2]>;
3613 // Intrinsic forms of MOVDQU load and store
3614 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3615 "vmovdqu\t{$src, $dst|$dst, $src}",
3616 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3618 XS, VEX, Requires<[HasAVX]>;
3620 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3621 "movdqu\t{$src, $dst|$dst, $src}",
3622 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3624 XS, Requires<[HasSSE2]>;
3626 } // ExeDomain = SSEPackedInt
3628 let Predicates = [HasAVX] in {
3629 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3630 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3633 //===---------------------------------------------------------------------===//
3634 // SSE2 - Packed Integer Arithmetic Instructions
3635 //===---------------------------------------------------------------------===//
3637 def SSE_PMADD : OpndItins<
3638 IIC_SSE_PMADD, IIC_SSE_PMADD
3641 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3643 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3644 RegisterClass RC, PatFrag memop_frag,
3645 X86MemOperand x86memop,
3647 bit IsCommutable = 0,
3649 let isCommutable = IsCommutable in
3650 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3651 (ins RC:$src1, RC:$src2),
3653 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3654 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3655 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3656 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3657 (ins RC:$src1, x86memop:$src2),
3659 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3660 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3661 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3665 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3666 string OpcodeStr, SDNode OpNode,
3667 SDNode OpNode2, RegisterClass RC,
3668 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3669 ShiftOpndItins itins,
3671 // src2 is always 128-bit
3672 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3673 (ins RC:$src1, VR128:$src2),
3675 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3676 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3677 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3679 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3680 (ins RC:$src1, i128mem:$src2),
3682 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3683 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3684 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3685 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3686 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3687 (ins RC:$src1, i32i8imm:$src2),
3689 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3690 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3691 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3694 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3695 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3696 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3697 PatFrag memop_frag, X86MemOperand x86memop,
3699 bit IsCommutable = 0, bit Is2Addr = 1> {
3700 let isCommutable = IsCommutable in
3701 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3702 (ins RC:$src1, RC:$src2),
3704 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3705 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3706 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3707 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3708 (ins RC:$src1, x86memop:$src2),
3710 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3711 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3712 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3713 (bitconvert (memop_frag addr:$src2)))))]>;
3715 } // ExeDomain = SSEPackedInt
3717 // 128-bit Integer Arithmetic
3719 let Predicates = [HasAVX] in {
3720 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3721 i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
3723 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3724 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3725 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3726 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3727 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3728 i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3729 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3730 i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3731 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3732 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3733 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3734 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3735 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3736 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3737 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3738 i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3739 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3740 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3744 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3745 VR128, memopv2i64, i128mem,
3746 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3747 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3748 VR128, memopv2i64, i128mem,
3749 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3750 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3751 VR128, memopv2i64, i128mem,
3752 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3753 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3754 VR128, memopv2i64, i128mem,
3755 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3756 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3757 VR128, memopv2i64, i128mem,
3758 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3759 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3760 VR128, memopv2i64, i128mem,
3761 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3762 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3763 VR128, memopv2i64, i128mem,
3764 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3765 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3766 VR128, memopv2i64, i128mem,
3767 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3768 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3769 VR128, memopv2i64, i128mem,
3770 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3771 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3772 VR128, memopv2i64, i128mem,
3773 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3774 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3775 VR128, memopv2i64, i128mem,
3776 SSE_PMADD, 1, 0>, VEX_4V;
3777 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3778 VR128, memopv2i64, i128mem,
3779 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3780 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3781 VR128, memopv2i64, i128mem,
3782 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3783 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3784 VR128, memopv2i64, i128mem,
3785 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3786 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3787 VR128, memopv2i64, i128mem,
3788 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3789 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3790 VR128, memopv2i64, i128mem,
3791 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3792 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3793 VR128, memopv2i64, i128mem,
3794 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3795 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3796 VR128, memopv2i64, i128mem,
3797 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3800 let Predicates = [HasAVX2] in {
3801 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3802 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3803 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3804 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3805 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3806 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3807 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3808 i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3809 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3810 i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3811 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3812 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3813 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3814 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3815 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3816 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3817 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3818 i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3819 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3820 VR256, memopv4i64, i256mem,
3821 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3824 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3825 VR256, memopv4i64, i256mem,
3826 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3827 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3828 VR256, memopv4i64, i256mem,
3829 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3830 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3831 VR256, memopv4i64, i256mem,
3832 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3833 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3834 VR256, memopv4i64, i256mem,
3835 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3836 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3837 VR256, memopv4i64, i256mem,
3838 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3839 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3840 VR256, memopv4i64, i256mem,
3841 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3842 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3843 VR256, memopv4i64, i256mem,
3844 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3845 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3846 VR256, memopv4i64, i256mem,
3847 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3848 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3849 VR256, memopv4i64, i256mem,
3850 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3851 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3852 VR256, memopv4i64, i256mem,
3853 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3854 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3855 VR256, memopv4i64, i256mem,
3856 SSE_PMADD, 1, 0>, VEX_4V;
3857 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3858 VR256, memopv4i64, i256mem,
3859 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3860 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3861 VR256, memopv4i64, i256mem,
3862 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3863 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3864 VR256, memopv4i64, i256mem,
3865 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3866 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3867 VR256, memopv4i64, i256mem,
3868 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3869 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3870 VR256, memopv4i64, i256mem,
3871 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3872 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3873 VR256, memopv4i64, i256mem,
3874 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3875 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3876 VR256, memopv4i64, i256mem,
3877 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3880 let Constraints = "$src1 = $dst" in {
3881 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3882 i128mem, SSE_INTALU_ITINS_P, 1>;
3883 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3884 i128mem, SSE_INTALU_ITINS_P, 1>;
3885 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3886 i128mem, SSE_INTALU_ITINS_P, 1>;
3887 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3888 i128mem, SSE_INTALUQ_ITINS_P, 1>;
3889 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3890 i128mem, SSE_INTMUL_ITINS_P, 1>;
3891 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3892 i128mem, SSE_INTALU_ITINS_P>;
3893 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3894 i128mem, SSE_INTALU_ITINS_P>;
3895 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3896 i128mem, SSE_INTALU_ITINS_P>;
3897 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3898 i128mem, SSE_INTALUQ_ITINS_P>;
3899 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3900 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3903 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3904 VR128, memopv2i64, i128mem,
3905 SSE_INTALU_ITINS_P>;
3906 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3907 VR128, memopv2i64, i128mem,
3908 SSE_INTALU_ITINS_P>;
3909 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3910 VR128, memopv2i64, i128mem,
3911 SSE_INTALU_ITINS_P>;
3912 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3913 VR128, memopv2i64, i128mem,
3914 SSE_INTALU_ITINS_P>;
3915 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3916 VR128, memopv2i64, i128mem,
3917 SSE_INTALU_ITINS_P, 1>;
3918 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3919 VR128, memopv2i64, i128mem,
3920 SSE_INTALU_ITINS_P, 1>;
3921 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3922 VR128, memopv2i64, i128mem,
3923 SSE_INTALU_ITINS_P, 1>;
3924 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3925 VR128, memopv2i64, i128mem,
3926 SSE_INTALU_ITINS_P, 1>;
3927 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3928 VR128, memopv2i64, i128mem,
3929 SSE_INTMUL_ITINS_P, 1>;
3930 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3931 VR128, memopv2i64, i128mem,
3932 SSE_INTMUL_ITINS_P, 1>;
3933 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3934 VR128, memopv2i64, i128mem,
3936 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3937 VR128, memopv2i64, i128mem,
3938 SSE_INTALU_ITINS_P, 1>;
3939 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3940 VR128, memopv2i64, i128mem,
3941 SSE_INTALU_ITINS_P, 1>;
3942 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3943 VR128, memopv2i64, i128mem,
3944 SSE_INTALU_ITINS_P, 1>;
3945 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3946 VR128, memopv2i64, i128mem,
3947 SSE_INTALU_ITINS_P, 1>;
3948 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3949 VR128, memopv2i64, i128mem,
3950 SSE_INTALU_ITINS_P, 1>;
3951 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3952 VR128, memopv2i64, i128mem,
3953 SSE_INTALU_ITINS_P, 1>;
3954 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3955 VR128, memopv2i64, i128mem,
3956 SSE_INTALU_ITINS_P, 1>;
3958 } // Constraints = "$src1 = $dst"
3960 //===---------------------------------------------------------------------===//
3961 // SSE2 - Packed Integer Logical Instructions
3962 //===---------------------------------------------------------------------===//
3964 let Predicates = [HasAVX] in {
3965 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3966 VR128, v8i16, v8i16, bc_v8i16,
3967 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3968 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3969 VR128, v4i32, v4i32, bc_v4i32,
3970 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3971 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3972 VR128, v2i64, v2i64, bc_v2i64,
3973 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3975 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3976 VR128, v8i16, v8i16, bc_v8i16,
3977 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3978 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3979 VR128, v4i32, v4i32, bc_v4i32,
3980 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3981 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3982 VR128, v2i64, v2i64, bc_v2i64,
3983 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3985 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3986 VR128, v8i16, v8i16, bc_v8i16,
3987 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3988 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3989 VR128, v4i32, v4i32, bc_v4i32,
3990 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3992 let ExeDomain = SSEPackedInt in {
3993 // 128-bit logical shifts.
3994 def VPSLLDQri : PDIi8<0x73, MRM7r,
3995 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3996 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3998 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
4000 def VPSRLDQri : PDIi8<0x73, MRM3r,
4001 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4002 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4004 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
4006 // PSRADQri doesn't exist in SSE[1-3].
4008 } // Predicates = [HasAVX]
4010 let Predicates = [HasAVX2] in {
4011 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4012 VR256, v16i16, v8i16, bc_v8i16,
4013 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4014 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4015 VR256, v8i32, v4i32, bc_v4i32,
4016 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4017 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4018 VR256, v4i64, v2i64, bc_v2i64,
4019 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4021 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4022 VR256, v16i16, v8i16, bc_v8i16,
4023 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4024 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4025 VR256, v8i32, v4i32, bc_v4i32,
4026 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4027 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4028 VR256, v4i64, v2i64, bc_v2i64,
4029 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4031 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4032 VR256, v16i16, v8i16, bc_v8i16,
4033 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4034 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4035 VR256, v8i32, v4i32, bc_v4i32,
4036 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4038 let ExeDomain = SSEPackedInt in {
4039 // 256-bit logical shifts.
4040 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4041 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4042 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4044 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4046 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4047 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4048 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4050 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4052 // PSRADQYri doesn't exist in SSE[1-3].
4054 } // Predicates = [HasAVX2]
4056 let Constraints = "$src1 = $dst" in {
4057 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4058 VR128, v8i16, v8i16, bc_v8i16,
4059 SSE_INTSHIFT_ITINS_P>;
4060 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4061 VR128, v4i32, v4i32, bc_v4i32,
4062 SSE_INTSHIFT_ITINS_P>;
4063 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4064 VR128, v2i64, v2i64, bc_v2i64,
4065 SSE_INTSHIFT_ITINS_P>;
4067 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4068 VR128, v8i16, v8i16, bc_v8i16,
4069 SSE_INTSHIFT_ITINS_P>;
4070 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4071 VR128, v4i32, v4i32, bc_v4i32,
4072 SSE_INTSHIFT_ITINS_P>;
4073 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4074 VR128, v2i64, v2i64, bc_v2i64,
4075 SSE_INTSHIFT_ITINS_P>;
4077 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4078 VR128, v8i16, v8i16, bc_v8i16,
4079 SSE_INTSHIFT_ITINS_P>;
4080 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4081 VR128, v4i32, v4i32, bc_v4i32,
4082 SSE_INTSHIFT_ITINS_P>;
4084 let ExeDomain = SSEPackedInt in {
4085 // 128-bit logical shifts.
4086 def PSLLDQri : PDIi8<0x73, MRM7r,
4087 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4088 "pslldq\t{$src2, $dst|$dst, $src2}",
4090 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
4091 def PSRLDQri : PDIi8<0x73, MRM3r,
4092 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4093 "psrldq\t{$src2, $dst|$dst, $src2}",
4095 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4096 // PSRADQri doesn't exist in SSE[1-3].
4098 } // Constraints = "$src1 = $dst"
4100 let Predicates = [HasAVX] in {
4101 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4102 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4103 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4104 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4105 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4106 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4108 // Shift up / down and insert zero's.
4109 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4110 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4111 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4112 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4115 let Predicates = [HasAVX2] in {
4116 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4117 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4118 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4119 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4122 let Predicates = [HasSSE2] in {
4123 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4124 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4125 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4126 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4127 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4128 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4130 // Shift up / down and insert zero's.
4131 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4132 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4133 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4134 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4137 //===---------------------------------------------------------------------===//
4138 // SSE2 - Packed Integer Comparison Instructions
4139 //===---------------------------------------------------------------------===//
4141 let Predicates = [HasAVX] in {
4142 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
4143 VR128, memopv2i64, i128mem,
4144 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4145 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
4146 VR128, memopv2i64, i128mem,
4147 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4148 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
4149 VR128, memopv2i64, i128mem,
4150 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4151 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
4152 VR128, memopv2i64, i128mem,
4153 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4154 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
4155 VR128, memopv2i64, i128mem,
4156 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4157 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
4158 VR128, memopv2i64, i128mem,
4159 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4162 let Predicates = [HasAVX2] in {
4163 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
4164 VR256, memopv4i64, i256mem,
4165 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4166 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
4167 VR256, memopv4i64, i256mem,
4168 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4169 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
4170 VR256, memopv4i64, i256mem,
4171 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4172 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
4173 VR256, memopv4i64, i256mem,
4174 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4175 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
4176 VR256, memopv4i64, i256mem,
4177 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4178 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
4179 VR256, memopv4i64, i256mem,
4180 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4183 let Constraints = "$src1 = $dst" in {
4184 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
4185 VR128, memopv2i64, i128mem,
4186 SSE_INTALU_ITINS_P, 1>;
4187 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
4188 VR128, memopv2i64, i128mem,
4189 SSE_INTALU_ITINS_P, 1>;
4190 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
4191 VR128, memopv2i64, i128mem,
4192 SSE_INTALU_ITINS_P, 1>;
4193 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
4194 VR128, memopv2i64, i128mem,
4195 SSE_INTALU_ITINS_P>;
4196 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
4197 VR128, memopv2i64, i128mem,
4198 SSE_INTALU_ITINS_P>;
4199 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
4200 VR128, memopv2i64, i128mem,
4201 SSE_INTALU_ITINS_P>;
4202 } // Constraints = "$src1 = $dst"
4204 //===---------------------------------------------------------------------===//
4205 // SSE2 - Packed Integer Pack Instructions
4206 //===---------------------------------------------------------------------===//
4208 let Predicates = [HasAVX] in {
4209 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4210 VR128, memopv2i64, i128mem,
4211 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4212 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4213 VR128, memopv2i64, i128mem,
4214 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4215 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4216 VR128, memopv2i64, i128mem,
4217 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4220 let Predicates = [HasAVX2] in {
4221 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4222 VR256, memopv4i64, i256mem,
4223 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4224 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4225 VR256, memopv4i64, i256mem,
4226 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4227 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4228 VR256, memopv4i64, i256mem,
4229 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4232 let Constraints = "$src1 = $dst" in {
4233 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4234 VR128, memopv2i64, i128mem,
4235 SSE_INTALU_ITINS_P>;
4236 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4237 VR128, memopv2i64, i128mem,
4238 SSE_INTALU_ITINS_P>;
4239 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4240 VR128, memopv2i64, i128mem,
4241 SSE_INTALU_ITINS_P>;
4242 } // Constraints = "$src1 = $dst"
4244 //===---------------------------------------------------------------------===//
4245 // SSE2 - Packed Integer Shuffle Instructions
4246 //===---------------------------------------------------------------------===//
4248 let ExeDomain = SSEPackedInt in {
4249 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
4250 def ri : Ii8<0x70, MRMSrcReg,
4251 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4252 !strconcat(OpcodeStr,
4253 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4254 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
4256 def mi : Ii8<0x70, MRMSrcMem,
4257 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4258 !strconcat(OpcodeStr,
4259 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4261 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
4266 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
4267 def Yri : Ii8<0x70, MRMSrcReg,
4268 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4269 !strconcat(OpcodeStr,
4270 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4271 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4272 def Ymi : Ii8<0x70, MRMSrcMem,
4273 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4274 !strconcat(OpcodeStr,
4275 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4277 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4278 (i8 imm:$src2))))]>;
4280 } // ExeDomain = SSEPackedInt
4282 let Predicates = [HasAVX] in {
4283 let AddedComplexity = 5 in
4284 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4286 // SSE2 with ImmT == Imm8 and XS prefix.
4287 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4289 // SSE2 with ImmT == Imm8 and XD prefix.
4290 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4292 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4293 (VPSHUFDmi addr:$src1, imm:$imm)>;
4294 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4295 (VPSHUFDri VR128:$src1, imm:$imm)>;
4298 let Predicates = [HasAVX2] in {
4299 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
4300 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>, XS, VEX;
4301 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>, XD, VEX;
4304 let Predicates = [HasSSE2] in {
4305 let AddedComplexity = 5 in
4306 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4308 // SSE2 with ImmT == Imm8 and XS prefix.
4309 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4311 // SSE2 with ImmT == Imm8 and XD prefix.
4312 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4314 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4315 (PSHUFDmi addr:$src1, imm:$imm)>;
4316 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4317 (PSHUFDri VR128:$src1, imm:$imm)>;
4320 //===---------------------------------------------------------------------===//
4321 // SSE2 - Packed Integer Unpack Instructions
4322 //===---------------------------------------------------------------------===//
4324 let ExeDomain = SSEPackedInt in {
4325 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4326 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4327 def rr : PDI<opc, MRMSrcReg,
4328 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4330 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4331 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4332 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4334 def rm : PDI<opc, MRMSrcMem,
4335 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4337 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4338 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4339 [(set VR128:$dst, (OpNode VR128:$src1,
4340 (bc_frag (memopv2i64
4345 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4346 SDNode OpNode, PatFrag bc_frag> {
4347 def Yrr : PDI<opc, MRMSrcReg,
4348 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4349 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4350 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4351 def Yrm : PDI<opc, MRMSrcMem,
4352 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4353 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4354 [(set VR256:$dst, (OpNode VR256:$src1,
4355 (bc_frag (memopv4i64 addr:$src2))))]>;
4358 let Predicates = [HasAVX] in {
4359 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4360 bc_v16i8, 0>, VEX_4V;
4361 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4362 bc_v8i16, 0>, VEX_4V;
4363 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4364 bc_v4i32, 0>, VEX_4V;
4365 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4366 bc_v2i64, 0>, VEX_4V;
4368 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4369 bc_v16i8, 0>, VEX_4V;
4370 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4371 bc_v8i16, 0>, VEX_4V;
4372 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4373 bc_v4i32, 0>, VEX_4V;
4374 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4375 bc_v2i64, 0>, VEX_4V;
4378 let Predicates = [HasAVX2] in {
4379 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4381 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4383 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4385 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4388 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4390 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4392 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4394 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4398 let Constraints = "$src1 = $dst" in {
4399 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4401 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4403 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4405 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4408 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4410 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4412 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4414 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4417 } // ExeDomain = SSEPackedInt
4419 // Patterns for using AVX1 instructions with integer vectors
4420 // Here to give AVX2 priority
4421 let Predicates = [HasAVX] in {
4422 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4423 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
4424 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
4425 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
4426 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4427 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
4428 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
4429 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
4431 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
4432 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
4433 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
4434 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
4435 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
4436 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
4437 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
4438 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
4441 //===---------------------------------------------------------------------===//
4442 // SSE2 - Packed Integer Extract and Insert
4443 //===---------------------------------------------------------------------===//
4445 let ExeDomain = SSEPackedInt in {
4446 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4447 def rri : Ii8<0xC4, MRMSrcReg,
4448 (outs VR128:$dst), (ins VR128:$src1,
4449 GR32:$src2, i32i8imm:$src3),
4451 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4452 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4454 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4455 def rmi : Ii8<0xC4, MRMSrcMem,
4456 (outs VR128:$dst), (ins VR128:$src1,
4457 i16mem:$src2, i32i8imm:$src3),
4459 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4460 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4462 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4463 imm:$src3))], IIC_SSE_PINSRW>;
4467 let Predicates = [HasAVX] in
4468 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4469 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4470 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4471 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4472 imm:$src2))]>, TB, OpSize, VEX;
4473 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4474 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4475 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4476 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4477 imm:$src2))], IIC_SSE_PEXTRW>;
4480 let Predicates = [HasAVX] in {
4481 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4482 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4483 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4484 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4485 []>, TB, OpSize, VEX_4V;
4488 let Constraints = "$src1 = $dst" in
4489 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4491 } // ExeDomain = SSEPackedInt
4493 //===---------------------------------------------------------------------===//
4494 // SSE2 - Packed Mask Creation
4495 //===---------------------------------------------------------------------===//
4497 let ExeDomain = SSEPackedInt in {
4499 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4500 "pmovmskb\t{$src, $dst|$dst, $src}",
4501 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4502 IIC_SSE_MOVMSK>, VEX;
4503 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4504 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4506 let Predicates = [HasAVX2] in {
4507 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4508 "pmovmskb\t{$src, $dst|$dst, $src}",
4509 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4510 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4511 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4514 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4515 "pmovmskb\t{$src, $dst|$dst, $src}",
4516 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4519 } // ExeDomain = SSEPackedInt
4521 //===---------------------------------------------------------------------===//
4522 // SSE2 - Conditional Store
4523 //===---------------------------------------------------------------------===//
4525 let ExeDomain = SSEPackedInt in {
4528 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4529 (ins VR128:$src, VR128:$mask),
4530 "maskmovdqu\t{$mask, $src|$src, $mask}",
4531 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4532 IIC_SSE_MASKMOV>, VEX;
4534 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4535 (ins VR128:$src, VR128:$mask),
4536 "maskmovdqu\t{$mask, $src|$src, $mask}",
4537 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4538 IIC_SSE_MASKMOV>, VEX;
4541 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4542 "maskmovdqu\t{$mask, $src|$src, $mask}",
4543 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4546 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4547 "maskmovdqu\t{$mask, $src|$src, $mask}",
4548 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4551 } // ExeDomain = SSEPackedInt
4553 //===---------------------------------------------------------------------===//
4554 // SSE2 - Move Doubleword
4555 //===---------------------------------------------------------------------===//
4557 //===---------------------------------------------------------------------===//
4558 // Move Int Doubleword to Packed Double Int
4560 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4561 "movd\t{$src, $dst|$dst, $src}",
4563 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4565 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4566 "movd\t{$src, $dst|$dst, $src}",
4568 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4571 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4572 "mov{d|q}\t{$src, $dst|$dst, $src}",
4574 (v2i64 (scalar_to_vector GR64:$src)))],
4575 IIC_SSE_MOVDQ>, VEX;
4576 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4577 "mov{d|q}\t{$src, $dst|$dst, $src}",
4578 [(set FR64:$dst, (bitconvert GR64:$src))],
4579 IIC_SSE_MOVDQ>, VEX;
4581 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4582 "movd\t{$src, $dst|$dst, $src}",
4584 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4585 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4586 "movd\t{$src, $dst|$dst, $src}",
4588 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4590 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4591 "mov{d|q}\t{$src, $dst|$dst, $src}",
4593 (v2i64 (scalar_to_vector GR64:$src)))],
4595 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4596 "mov{d|q}\t{$src, $dst|$dst, $src}",
4597 [(set FR64:$dst, (bitconvert GR64:$src))],
4600 //===---------------------------------------------------------------------===//
4601 // Move Int Doubleword to Single Scalar
4603 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4604 "movd\t{$src, $dst|$dst, $src}",
4605 [(set FR32:$dst, (bitconvert GR32:$src))],
4606 IIC_SSE_MOVDQ>, VEX;
4608 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4609 "movd\t{$src, $dst|$dst, $src}",
4610 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4613 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4614 "movd\t{$src, $dst|$dst, $src}",
4615 [(set FR32:$dst, (bitconvert GR32:$src))],
4618 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4619 "movd\t{$src, $dst|$dst, $src}",
4620 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4623 //===---------------------------------------------------------------------===//
4624 // Move Packed Doubleword Int to Packed Double Int
4626 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4627 "movd\t{$src, $dst|$dst, $src}",
4628 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4629 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4630 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4631 (ins i32mem:$dst, VR128:$src),
4632 "movd\t{$src, $dst|$dst, $src}",
4633 [(store (i32 (vector_extract (v4i32 VR128:$src),
4634 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4636 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4637 "movd\t{$src, $dst|$dst, $src}",
4638 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4639 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4640 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4641 "movd\t{$src, $dst|$dst, $src}",
4642 [(store (i32 (vector_extract (v4i32 VR128:$src),
4643 (iPTR 0))), addr:$dst)],
4646 //===---------------------------------------------------------------------===//
4647 // Move Packed Doubleword Int first element to Doubleword Int
4649 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4650 "mov{d|q}\t{$src, $dst|$dst, $src}",
4651 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4654 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4656 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4657 "mov{d|q}\t{$src, $dst|$dst, $src}",
4658 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4662 //===---------------------------------------------------------------------===//
4663 // Bitcast FR64 <-> GR64
4665 let Predicates = [HasAVX] in
4666 def VMOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4667 "vmovq\t{$src, $dst|$dst, $src}",
4668 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4670 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4671 "mov{d|q}\t{$src, $dst|$dst, $src}",
4672 [(set GR64:$dst, (bitconvert FR64:$src))],
4673 IIC_SSE_MOVDQ>, VEX;
4674 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4675 "movq\t{$src, $dst|$dst, $src}",
4676 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4677 IIC_SSE_MOVDQ>, VEX;
4679 def MOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4680 "movq\t{$src, $dst|$dst, $src}",
4681 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4683 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4684 "mov{d|q}\t{$src, $dst|$dst, $src}",
4685 [(set GR64:$dst, (bitconvert FR64:$src))],
4687 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4688 "movq\t{$src, $dst|$dst, $src}",
4689 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4692 //===---------------------------------------------------------------------===//
4693 // Move Scalar Single to Double Int
4695 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4696 "movd\t{$src, $dst|$dst, $src}",
4697 [(set GR32:$dst, (bitconvert FR32:$src))],
4698 IIC_SSE_MOVD_ToGP>, VEX;
4699 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4700 "movd\t{$src, $dst|$dst, $src}",
4701 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4702 IIC_SSE_MOVDQ>, VEX;
4703 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4704 "movd\t{$src, $dst|$dst, $src}",
4705 [(set GR32:$dst, (bitconvert FR32:$src))],
4707 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4708 "movd\t{$src, $dst|$dst, $src}",
4709 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4712 //===---------------------------------------------------------------------===//
4713 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4715 let AddedComplexity = 15 in {
4716 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4717 "movd\t{$src, $dst|$dst, $src}",
4718 [(set VR128:$dst, (v4i32 (X86vzmovl
4719 (v4i32 (scalar_to_vector GR32:$src)))))],
4720 IIC_SSE_MOVDQ>, VEX;
4721 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4722 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4723 [(set VR128:$dst, (v2i64 (X86vzmovl
4724 (v2i64 (scalar_to_vector GR64:$src)))))],
4728 let AddedComplexity = 15 in {
4729 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4730 "movd\t{$src, $dst|$dst, $src}",
4731 [(set VR128:$dst, (v4i32 (X86vzmovl
4732 (v4i32 (scalar_to_vector GR32:$src)))))],
4734 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4735 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4736 [(set VR128:$dst, (v2i64 (X86vzmovl
4737 (v2i64 (scalar_to_vector GR64:$src)))))],
4741 let AddedComplexity = 20 in {
4742 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4743 "movd\t{$src, $dst|$dst, $src}",
4745 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4746 (loadi32 addr:$src))))))],
4747 IIC_SSE_MOVDQ>, VEX;
4748 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4749 "movd\t{$src, $dst|$dst, $src}",
4751 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4752 (loadi32 addr:$src))))))],
4756 let Predicates = [HasAVX] in {
4757 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4758 let AddedComplexity = 20 in {
4759 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4760 (VMOVZDI2PDIrm addr:$src)>;
4761 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4762 (VMOVZDI2PDIrm addr:$src)>;
4764 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4765 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4766 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4767 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4768 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4769 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4770 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4773 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4774 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4775 (MOVZDI2PDIrm addr:$src)>;
4776 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4777 (MOVZDI2PDIrm addr:$src)>;
4780 // These are the correct encodings of the instructions so that we know how to
4781 // read correct assembly, even though we continue to emit the wrong ones for
4782 // compatibility with Darwin's buggy assembler.
4783 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4784 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4785 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4786 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4787 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4788 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4789 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4790 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4791 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4792 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4793 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4794 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4796 //===---------------------------------------------------------------------===//
4797 // SSE2 - Move Quadword
4798 //===---------------------------------------------------------------------===//
4800 //===---------------------------------------------------------------------===//
4801 // Move Quadword Int to Packed Quadword Int
4803 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4804 "vmovq\t{$src, $dst|$dst, $src}",
4806 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4807 VEX, Requires<[HasAVX]>;
4808 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4809 "movq\t{$src, $dst|$dst, $src}",
4811 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4813 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4815 //===---------------------------------------------------------------------===//
4816 // Move Packed Quadword Int to Quadword Int
4818 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4819 "movq\t{$src, $dst|$dst, $src}",
4820 [(store (i64 (vector_extract (v2i64 VR128:$src),
4821 (iPTR 0))), addr:$dst)],
4822 IIC_SSE_MOVDQ>, VEX;
4823 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4824 "movq\t{$src, $dst|$dst, $src}",
4825 [(store (i64 (vector_extract (v2i64 VR128:$src),
4826 (iPTR 0))), addr:$dst)],
4829 //===---------------------------------------------------------------------===//
4830 // Store / copy lower 64-bits of a XMM register.
4832 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4833 "movq\t{$src, $dst|$dst, $src}",
4834 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4835 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4836 "movq\t{$src, $dst|$dst, $src}",
4837 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4840 let AddedComplexity = 20 in
4841 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4842 "vmovq\t{$src, $dst|$dst, $src}",
4844 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4845 (loadi64 addr:$src))))))],
4847 XS, VEX, Requires<[HasAVX]>;
4849 let AddedComplexity = 20 in
4850 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4851 "movq\t{$src, $dst|$dst, $src}",
4853 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4854 (loadi64 addr:$src))))))],
4856 XS, Requires<[HasSSE2]>;
4858 let Predicates = [HasAVX], AddedComplexity = 20 in {
4859 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4860 (VMOVZQI2PQIrm addr:$src)>;
4861 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4862 (VMOVZQI2PQIrm addr:$src)>;
4863 def : Pat<(v2i64 (X86vzload addr:$src)),
4864 (VMOVZQI2PQIrm addr:$src)>;
4867 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4868 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4869 (MOVZQI2PQIrm addr:$src)>;
4870 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4871 (MOVZQI2PQIrm addr:$src)>;
4872 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4875 let Predicates = [HasAVX] in {
4876 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4877 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4878 def : Pat<(v4i64 (X86vzload addr:$src)),
4879 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4882 //===---------------------------------------------------------------------===//
4883 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4884 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4886 let AddedComplexity = 15 in
4887 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4888 "vmovq\t{$src, $dst|$dst, $src}",
4889 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4891 XS, VEX, Requires<[HasAVX]>;
4892 let AddedComplexity = 15 in
4893 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4894 "movq\t{$src, $dst|$dst, $src}",
4895 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4897 XS, Requires<[HasSSE2]>;
4899 let AddedComplexity = 20 in
4900 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4901 "vmovq\t{$src, $dst|$dst, $src}",
4902 [(set VR128:$dst, (v2i64 (X86vzmovl
4903 (loadv2i64 addr:$src))))],
4905 XS, VEX, Requires<[HasAVX]>;
4906 let AddedComplexity = 20 in {
4907 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4908 "movq\t{$src, $dst|$dst, $src}",
4909 [(set VR128:$dst, (v2i64 (X86vzmovl
4910 (loadv2i64 addr:$src))))],
4912 XS, Requires<[HasSSE2]>;
4915 let AddedComplexity = 20 in {
4916 let Predicates = [HasAVX] in {
4917 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4918 (VMOVZPQILo2PQIrm addr:$src)>;
4919 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4920 (VMOVZPQILo2PQIrr VR128:$src)>;
4922 let Predicates = [HasSSE2] in {
4923 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4924 (MOVZPQILo2PQIrm addr:$src)>;
4925 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4926 (MOVZPQILo2PQIrr VR128:$src)>;
4930 // Instructions to match in the assembler
4931 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4932 "movq\t{$src, $dst|$dst, $src}", [],
4933 IIC_SSE_MOVDQ>, VEX, VEX_W;
4934 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4935 "movq\t{$src, $dst|$dst, $src}", [],
4936 IIC_SSE_MOVDQ>, VEX, VEX_W;
4937 // Recognize "movd" with GR64 destination, but encode as a "movq"
4938 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4939 "movd\t{$src, $dst|$dst, $src}", [],
4940 IIC_SSE_MOVDQ>, VEX, VEX_W;
4942 // Instructions for the disassembler
4943 // xr = XMM register
4946 let Predicates = [HasAVX] in
4947 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4948 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4949 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4950 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4952 //===---------------------------------------------------------------------===//
4953 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4954 //===---------------------------------------------------------------------===//
4955 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4956 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4957 X86MemOperand x86memop> {
4958 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4959 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4960 [(set RC:$dst, (vt (OpNode RC:$src)))],
4962 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4963 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4964 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4968 let Predicates = [HasAVX] in {
4969 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4970 v4f32, VR128, memopv4f32, f128mem>, VEX;
4971 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4972 v4f32, VR128, memopv4f32, f128mem>, VEX;
4973 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4974 v8f32, VR256, memopv8f32, f256mem>, VEX;
4975 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4976 v8f32, VR256, memopv8f32, f256mem>, VEX;
4978 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4979 memopv4f32, f128mem>;
4980 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4981 memopv4f32, f128mem>;
4983 let Predicates = [HasAVX] in {
4984 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4985 (VMOVSHDUPrr VR128:$src)>;
4986 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4987 (VMOVSHDUPrm addr:$src)>;
4988 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4989 (VMOVSLDUPrr VR128:$src)>;
4990 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4991 (VMOVSLDUPrm addr:$src)>;
4992 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4993 (VMOVSHDUPYrr VR256:$src)>;
4994 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4995 (VMOVSHDUPYrm addr:$src)>;
4996 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4997 (VMOVSLDUPYrr VR256:$src)>;
4998 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4999 (VMOVSLDUPYrm addr:$src)>;
5002 let Predicates = [HasSSE3] in {
5003 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5004 (MOVSHDUPrr VR128:$src)>;
5005 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5006 (MOVSHDUPrm addr:$src)>;
5007 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5008 (MOVSLDUPrr VR128:$src)>;
5009 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5010 (MOVSLDUPrm addr:$src)>;
5013 //===---------------------------------------------------------------------===//
5014 // SSE3 - Replicate Double FP - MOVDDUP
5015 //===---------------------------------------------------------------------===//
5017 multiclass sse3_replicate_dfp<string OpcodeStr> {
5018 let neverHasSideEffects = 1 in
5019 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5020 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5021 [], IIC_SSE_MOV_LH>;
5022 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5023 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5026 (scalar_to_vector (loadf64 addr:$src)))))],
5030 // FIXME: Merge with above classe when there're patterns for the ymm version
5031 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5032 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5033 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5034 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
5035 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5036 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5039 (scalar_to_vector (loadf64 addr:$src)))))]>;
5042 let Predicates = [HasAVX] in {
5043 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5044 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
5047 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5049 let Predicates = [HasAVX] in {
5050 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5051 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5052 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5053 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5054 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5055 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5056 def : Pat<(X86Movddup (bc_v2f64
5057 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5058 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5061 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
5062 (VMOVDDUPYrm addr:$src)>;
5063 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
5064 (VMOVDDUPYrm addr:$src)>;
5065 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5066 (VMOVDDUPYrm addr:$src)>;
5067 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5068 (VMOVDDUPYrr VR256:$src)>;
5071 let Predicates = [HasSSE3] in {
5072 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5073 (MOVDDUPrm addr:$src)>;
5074 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5075 (MOVDDUPrm addr:$src)>;
5076 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5077 (MOVDDUPrm addr:$src)>;
5078 def : Pat<(X86Movddup (bc_v2f64
5079 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5080 (MOVDDUPrm addr:$src)>;
5083 //===---------------------------------------------------------------------===//
5084 // SSE3 - Move Unaligned Integer
5085 //===---------------------------------------------------------------------===//
5087 let Predicates = [HasAVX] in {
5088 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5089 "vlddqu\t{$src, $dst|$dst, $src}",
5090 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5091 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5092 "vlddqu\t{$src, $dst|$dst, $src}",
5093 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
5095 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5096 "lddqu\t{$src, $dst|$dst, $src}",
5097 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5100 //===---------------------------------------------------------------------===//
5101 // SSE3 - Arithmetic
5102 //===---------------------------------------------------------------------===//
5104 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5105 X86MemOperand x86memop, OpndItins itins,
5107 def rr : I<0xD0, MRMSrcReg,
5108 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5110 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5111 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5112 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
5113 def rm : I<0xD0, MRMSrcMem,
5114 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5116 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5117 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5118 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
5121 let Predicates = [HasAVX] in {
5122 let ExeDomain = SSEPackedSingle in {
5123 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5124 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5125 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5126 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5128 let ExeDomain = SSEPackedDouble in {
5129 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5130 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5131 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5132 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5135 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
5136 let ExeDomain = SSEPackedSingle in
5137 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5138 f128mem, SSE_ALU_F32P>, TB, XD;
5139 let ExeDomain = SSEPackedDouble in
5140 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5141 f128mem, SSE_ALU_F64P>, TB, OpSize;
5144 //===---------------------------------------------------------------------===//
5145 // SSE3 Instructions
5146 //===---------------------------------------------------------------------===//
5149 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5150 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5151 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5153 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5154 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5155 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5157 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5159 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5160 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5161 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5162 IIC_SSE_HADDSUB_RM>;
5164 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5165 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5166 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5168 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5169 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5170 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5172 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5174 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5175 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5176 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5177 IIC_SSE_HADDSUB_RM>;
5180 let Predicates = [HasAVX] in {
5181 let ExeDomain = SSEPackedSingle in {
5182 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5183 X86fhadd, 0>, VEX_4V;
5184 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5185 X86fhsub, 0>, VEX_4V;
5186 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5187 X86fhadd, 0>, VEX_4V;
5188 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5189 X86fhsub, 0>, VEX_4V;
5191 let ExeDomain = SSEPackedDouble in {
5192 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5193 X86fhadd, 0>, VEX_4V;
5194 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5195 X86fhsub, 0>, VEX_4V;
5196 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5197 X86fhadd, 0>, VEX_4V;
5198 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5199 X86fhsub, 0>, VEX_4V;
5203 let Constraints = "$src1 = $dst" in {
5204 let ExeDomain = SSEPackedSingle in {
5205 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5206 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5208 let ExeDomain = SSEPackedDouble in {
5209 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5210 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5214 //===---------------------------------------------------------------------===//
5215 // SSSE3 - Packed Absolute Instructions
5216 //===---------------------------------------------------------------------===//
5219 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5220 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5221 Intrinsic IntId128> {
5222 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5224 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5225 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5228 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5230 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5233 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5237 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5238 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5239 Intrinsic IntId256> {
5240 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5242 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5243 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5246 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5248 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5251 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5254 let Predicates = [HasAVX] in {
5255 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5256 int_x86_ssse3_pabs_b_128>, VEX;
5257 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5258 int_x86_ssse3_pabs_w_128>, VEX;
5259 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5260 int_x86_ssse3_pabs_d_128>, VEX;
5263 let Predicates = [HasAVX2] in {
5264 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5265 int_x86_avx2_pabs_b>, VEX;
5266 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5267 int_x86_avx2_pabs_w>, VEX;
5268 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5269 int_x86_avx2_pabs_d>, VEX;
5272 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5273 int_x86_ssse3_pabs_b_128>;
5274 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5275 int_x86_ssse3_pabs_w_128>;
5276 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5277 int_x86_ssse3_pabs_d_128>;
5279 //===---------------------------------------------------------------------===//
5280 // SSSE3 - Packed Binary Operator Instructions
5281 //===---------------------------------------------------------------------===//
5283 def SSE_PHADDSUBD : OpndItins<
5284 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5286 def SSE_PHADDSUBSW : OpndItins<
5287 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5289 def SSE_PHADDSUBW : OpndItins<
5290 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5292 def SSE_PSHUFB : OpndItins<
5293 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5295 def SSE_PSIGN : OpndItins<
5296 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5298 def SSE_PMULHRSW : OpndItins<
5299 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5302 /// SS3I_binop_rm - Simple SSSE3 bin op
5303 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5304 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5305 X86MemOperand x86memop, OpndItins itins,
5307 let isCommutable = 1 in
5308 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5309 (ins RC:$src1, RC:$src2),
5311 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5312 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5313 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5315 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5316 (ins RC:$src1, x86memop:$src2),
5318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5321 (OpVT (OpNode RC:$src1,
5322 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5325 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5326 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5327 Intrinsic IntId128, OpndItins itins,
5329 let isCommutable = 1 in
5330 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5331 (ins VR128:$src1, VR128:$src2),
5333 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5334 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5335 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5337 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5338 (ins VR128:$src1, i128mem:$src2),
5340 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5341 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5343 (IntId128 VR128:$src1,
5344 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5347 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5348 Intrinsic IntId256> {
5349 let isCommutable = 1 in
5350 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5351 (ins VR256:$src1, VR256:$src2),
5352 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5353 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5355 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5356 (ins VR256:$src1, i256mem:$src2),
5357 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5359 (IntId256 VR256:$src1,
5360 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5363 let ImmT = NoImm, Predicates = [HasAVX] in {
5364 let isCommutable = 0 in {
5365 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5366 memopv2i64, i128mem,
5367 SSE_PHADDSUBW, 0>, VEX_4V;
5368 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5369 memopv2i64, i128mem,
5370 SSE_PHADDSUBD, 0>, VEX_4V;
5371 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5372 memopv2i64, i128mem,
5373 SSE_PHADDSUBW, 0>, VEX_4V;
5374 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5375 memopv2i64, i128mem,
5376 SSE_PHADDSUBD, 0>, VEX_4V;
5377 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5378 memopv2i64, i128mem,
5379 SSE_PSIGN, 0>, VEX_4V;
5380 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5381 memopv2i64, i128mem,
5382 SSE_PSIGN, 0>, VEX_4V;
5383 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5384 memopv2i64, i128mem,
5385 SSE_PSIGN, 0>, VEX_4V;
5386 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5387 memopv2i64, i128mem,
5388 SSE_PSHUFB, 0>, VEX_4V;
5389 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5390 int_x86_ssse3_phadd_sw_128,
5391 SSE_PHADDSUBSW, 0>, VEX_4V;
5392 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5393 int_x86_ssse3_phsub_sw_128,
5394 SSE_PHADDSUBSW, 0>, VEX_4V;
5395 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5396 int_x86_ssse3_pmadd_ub_sw_128,
5397 SSE_PMADD, 0>, VEX_4V;
5399 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5400 int_x86_ssse3_pmul_hr_sw_128,
5401 SSE_PMULHRSW, 0>, VEX_4V;
5404 let ImmT = NoImm, Predicates = [HasAVX2] in {
5405 let isCommutable = 0 in {
5406 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5407 memopv4i64, i256mem,
5408 SSE_PHADDSUBW, 0>, VEX_4V;
5409 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5410 memopv4i64, i256mem,
5411 SSE_PHADDSUBW, 0>, VEX_4V;
5412 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5413 memopv4i64, i256mem,
5414 SSE_PHADDSUBW, 0>, VEX_4V;
5415 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5416 memopv4i64, i256mem,
5417 SSE_PHADDSUBW, 0>, VEX_4V;
5418 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5419 memopv4i64, i256mem,
5420 SSE_PHADDSUBW, 0>, VEX_4V;
5421 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5422 memopv4i64, i256mem,
5423 SSE_PHADDSUBW, 0>, VEX_4V;
5424 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5425 memopv4i64, i256mem,
5426 SSE_PHADDSUBW, 0>, VEX_4V;
5427 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5428 memopv4i64, i256mem,
5429 SSE_PHADDSUBW, 0>, VEX_4V;
5430 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5431 int_x86_avx2_phadd_sw>, VEX_4V;
5432 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5433 int_x86_avx2_phsub_sw>, VEX_4V;
5434 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5435 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5437 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5438 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5441 // None of these have i8 immediate fields.
5442 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5443 let isCommutable = 0 in {
5444 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5445 memopv2i64, i128mem, SSE_PHADDSUBW>;
5446 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5447 memopv2i64, i128mem, SSE_PHADDSUBD>;
5448 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5449 memopv2i64, i128mem, SSE_PHADDSUBW>;
5450 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5451 memopv2i64, i128mem, SSE_PHADDSUBD>;
5452 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5453 memopv2i64, i128mem, SSE_PSIGN>;
5454 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5455 memopv2i64, i128mem, SSE_PSIGN>;
5456 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5457 memopv2i64, i128mem, SSE_PSIGN>;
5458 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5459 memopv2i64, i128mem, SSE_PSHUFB>;
5460 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5461 int_x86_ssse3_phadd_sw_128,
5463 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5464 int_x86_ssse3_phsub_sw_128,
5466 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5467 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5469 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5470 int_x86_ssse3_pmul_hr_sw_128,
5474 //===---------------------------------------------------------------------===//
5475 // SSSE3 - Packed Align Instruction Patterns
5476 //===---------------------------------------------------------------------===//
5478 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5479 let neverHasSideEffects = 1 in {
5480 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5481 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5483 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5485 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5486 [], IIC_SSE_PALIGNR>, OpSize;
5488 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5489 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5491 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5493 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5494 [], IIC_SSE_PALIGNR>, OpSize;
5498 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5499 let neverHasSideEffects = 1 in {
5500 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5501 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5503 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5506 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5507 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5509 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5514 let Predicates = [HasAVX] in
5515 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5516 let Predicates = [HasAVX2] in
5517 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5518 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5519 defm PALIGN : ssse3_palign<"palignr">;
5521 let Predicates = [HasAVX2] in {
5522 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5523 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5524 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5525 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5526 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5527 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5528 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5529 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5532 let Predicates = [HasAVX] in {
5533 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5534 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5535 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5536 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5537 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5538 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5539 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5540 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5543 let Predicates = [HasSSSE3] in {
5544 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5545 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5546 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5547 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5548 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5549 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5550 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5551 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5554 //===---------------------------------------------------------------------===//
5555 // SSSE3 - Thread synchronization
5556 //===---------------------------------------------------------------------===//
5558 let usesCustomInserter = 1 in {
5559 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5560 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5561 Requires<[HasSSE3]>;
5562 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5563 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>,
5564 Requires<[HasSSE3]>;
5567 let Uses = [EAX, ECX, EDX] in
5568 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5569 TB, Requires<[HasSSE3]>;
5570 let Uses = [ECX, EAX] in
5571 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", [], IIC_SSE_MWAIT>,
5572 TB, Requires<[HasSSE3]>;
5574 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5575 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5577 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5578 Requires<[In32BitMode]>;
5579 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5580 Requires<[In64BitMode]>;
5582 //===----------------------------------------------------------------------===//
5583 // SSE4.1 - Packed Move with Sign/Zero Extend
5584 //===----------------------------------------------------------------------===//
5586 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5587 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5588 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5589 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5591 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5592 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5594 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5598 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5600 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5601 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5602 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5604 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5605 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5606 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5609 let Predicates = [HasAVX] in {
5610 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5612 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5614 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5616 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5618 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5620 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5624 let Predicates = [HasAVX2] in {
5625 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5626 int_x86_avx2_pmovsxbw>, VEX;
5627 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5628 int_x86_avx2_pmovsxwd>, VEX;
5629 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5630 int_x86_avx2_pmovsxdq>, VEX;
5631 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5632 int_x86_avx2_pmovzxbw>, VEX;
5633 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5634 int_x86_avx2_pmovzxwd>, VEX;
5635 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5636 int_x86_avx2_pmovzxdq>, VEX;
5639 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5640 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5641 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5642 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5643 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5644 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5646 let Predicates = [HasAVX] in {
5647 // Common patterns involving scalar load.
5648 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5649 (VPMOVSXBWrm addr:$src)>;
5650 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5651 (VPMOVSXBWrm addr:$src)>;
5653 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5654 (VPMOVSXWDrm addr:$src)>;
5655 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5656 (VPMOVSXWDrm addr:$src)>;
5658 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5659 (VPMOVSXDQrm addr:$src)>;
5660 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5661 (VPMOVSXDQrm addr:$src)>;
5663 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5664 (VPMOVZXBWrm addr:$src)>;
5665 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5666 (VPMOVZXBWrm addr:$src)>;
5668 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5669 (VPMOVZXWDrm addr:$src)>;
5670 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5671 (VPMOVZXWDrm addr:$src)>;
5673 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5674 (VPMOVZXDQrm addr:$src)>;
5675 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5676 (VPMOVZXDQrm addr:$src)>;
5679 let Predicates = [HasSSE41] in {
5680 // Common patterns involving scalar load.
5681 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5682 (PMOVSXBWrm addr:$src)>;
5683 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5684 (PMOVSXBWrm addr:$src)>;
5686 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5687 (PMOVSXWDrm addr:$src)>;
5688 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5689 (PMOVSXWDrm addr:$src)>;
5691 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5692 (PMOVSXDQrm addr:$src)>;
5693 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5694 (PMOVSXDQrm addr:$src)>;
5696 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5697 (PMOVZXBWrm addr:$src)>;
5698 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5699 (PMOVZXBWrm addr:$src)>;
5701 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5702 (PMOVZXWDrm addr:$src)>;
5703 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5704 (PMOVZXWDrm addr:$src)>;
5706 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5707 (PMOVZXDQrm addr:$src)>;
5708 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5709 (PMOVZXDQrm addr:$src)>;
5712 let Predicates = [HasAVX2] in {
5713 let AddedComplexity = 15 in {
5714 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5715 (VPMOVZXDQYrr VR128:$src)>;
5716 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5717 (VPMOVZXWDYrr VR128:$src)>;
5720 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5721 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5724 let Predicates = [HasAVX] in {
5725 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5726 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5729 let Predicates = [HasSSE41] in {
5730 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5731 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5735 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5736 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5737 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5738 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5740 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5741 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5743 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5747 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5749 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5750 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5751 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5753 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5754 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5756 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5760 let Predicates = [HasAVX] in {
5761 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5763 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5765 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5767 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5771 let Predicates = [HasAVX2] in {
5772 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5773 int_x86_avx2_pmovsxbd>, VEX;
5774 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5775 int_x86_avx2_pmovsxwq>, VEX;
5776 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5777 int_x86_avx2_pmovzxbd>, VEX;
5778 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5779 int_x86_avx2_pmovzxwq>, VEX;
5782 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5783 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5784 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5785 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5787 let Predicates = [HasAVX] in {
5788 // Common patterns involving scalar load
5789 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5790 (VPMOVSXBDrm addr:$src)>;
5791 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5792 (VPMOVSXWQrm addr:$src)>;
5794 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5795 (VPMOVZXBDrm addr:$src)>;
5796 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5797 (VPMOVZXWQrm addr:$src)>;
5800 let Predicates = [HasSSE41] in {
5801 // Common patterns involving scalar load
5802 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5803 (PMOVSXBDrm addr:$src)>;
5804 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5805 (PMOVSXWQrm addr:$src)>;
5807 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5808 (PMOVZXBDrm addr:$src)>;
5809 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5810 (PMOVZXWQrm addr:$src)>;
5813 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5814 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5815 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5816 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5818 // Expecting a i16 load any extended to i32 value.
5819 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5820 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5821 [(set VR128:$dst, (IntId (bitconvert
5822 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5826 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5828 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5829 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5830 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5832 // Expecting a i16 load any extended to i32 value.
5833 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5834 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5835 [(set VR256:$dst, (IntId (bitconvert
5836 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5840 let Predicates = [HasAVX] in {
5841 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5843 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5846 let Predicates = [HasAVX2] in {
5847 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5848 int_x86_avx2_pmovsxbq>, VEX;
5849 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5850 int_x86_avx2_pmovzxbq>, VEX;
5852 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5853 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5855 let Predicates = [HasAVX] in {
5856 // Common patterns involving scalar load
5857 def : Pat<(int_x86_sse41_pmovsxbq
5858 (bitconvert (v4i32 (X86vzmovl
5859 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5860 (VPMOVSXBQrm addr:$src)>;
5862 def : Pat<(int_x86_sse41_pmovzxbq
5863 (bitconvert (v4i32 (X86vzmovl
5864 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5865 (VPMOVZXBQrm addr:$src)>;
5868 let Predicates = [HasSSE41] in {
5869 // Common patterns involving scalar load
5870 def : Pat<(int_x86_sse41_pmovsxbq
5871 (bitconvert (v4i32 (X86vzmovl
5872 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5873 (PMOVSXBQrm addr:$src)>;
5875 def : Pat<(int_x86_sse41_pmovzxbq
5876 (bitconvert (v4i32 (X86vzmovl
5877 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5878 (PMOVZXBQrm addr:$src)>;
5881 //===----------------------------------------------------------------------===//
5882 // SSE4.1 - Extract Instructions
5883 //===----------------------------------------------------------------------===//
5885 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5886 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5887 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5888 (ins VR128:$src1, i32i8imm:$src2),
5889 !strconcat(OpcodeStr,
5890 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5891 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5893 let neverHasSideEffects = 1, mayStore = 1 in
5894 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5895 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5896 !strconcat(OpcodeStr,
5897 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5900 // There's an AssertZext in the way of writing the store pattern
5901 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5904 let Predicates = [HasAVX] in {
5905 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5906 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5907 (ins VR128:$src1, i32i8imm:$src2),
5908 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5911 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5914 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5915 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5916 let neverHasSideEffects = 1, mayStore = 1 in
5917 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5918 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5919 !strconcat(OpcodeStr,
5920 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5923 // There's an AssertZext in the way of writing the store pattern
5924 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5927 let Predicates = [HasAVX] in
5928 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5930 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5933 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5934 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5935 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5936 (ins VR128:$src1, i32i8imm:$src2),
5937 !strconcat(OpcodeStr,
5938 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5940 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5941 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5942 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5943 !strconcat(OpcodeStr,
5944 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5945 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5946 addr:$dst)]>, OpSize;
5949 let Predicates = [HasAVX] in
5950 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5952 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5954 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5955 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5956 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5957 (ins VR128:$src1, i32i8imm:$src2),
5958 !strconcat(OpcodeStr,
5959 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5961 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5962 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5963 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5964 !strconcat(OpcodeStr,
5965 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5966 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5967 addr:$dst)]>, OpSize, REX_W;
5970 let Predicates = [HasAVX] in
5971 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5973 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5975 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5977 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5978 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5979 (ins VR128:$src1, i32i8imm:$src2),
5980 !strconcat(OpcodeStr,
5981 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5983 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5985 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5986 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5987 !strconcat(OpcodeStr,
5988 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5989 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5990 addr:$dst)]>, OpSize;
5993 let ExeDomain = SSEPackedSingle in {
5994 let Predicates = [HasAVX] in {
5995 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5996 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5997 (ins VR128:$src1, i32i8imm:$src2),
5998 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
6001 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
6004 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6005 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6008 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6010 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6013 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6014 Requires<[HasSSE41]>;
6016 //===----------------------------------------------------------------------===//
6017 // SSE4.1 - Insert Instructions
6018 //===----------------------------------------------------------------------===//
6020 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6021 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6022 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6024 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6026 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6028 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
6029 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6030 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6032 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6034 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6036 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6037 imm:$src3))]>, OpSize;
6040 let Predicates = [HasAVX] in
6041 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6042 let Constraints = "$src1 = $dst" in
6043 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6045 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6046 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6047 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6049 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6051 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6053 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6055 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6056 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6058 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6060 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6062 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6063 imm:$src3)))]>, OpSize;
6066 let Predicates = [HasAVX] in
6067 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6068 let Constraints = "$src1 = $dst" in
6069 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6071 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6072 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6073 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6075 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6077 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6079 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6081 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6082 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6084 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6086 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6088 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6089 imm:$src3)))]>, OpSize;
6092 let Predicates = [HasAVX] in
6093 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6094 let Constraints = "$src1 = $dst" in
6095 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6097 // insertps has a few different modes, there's the first two here below which
6098 // are optimized inserts that won't zero arbitrary elements in the destination
6099 // vector. The next one matches the intrinsic and could zero arbitrary elements
6100 // in the target vector.
6101 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6102 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6103 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6105 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6107 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6109 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6111 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6112 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6114 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6116 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6118 (X86insrtps VR128:$src1,
6119 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6120 imm:$src3))]>, OpSize;
6123 let ExeDomain = SSEPackedSingle in {
6124 let Predicates = [HasAVX] in
6125 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6126 let Constraints = "$src1 = $dst" in
6127 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6130 //===----------------------------------------------------------------------===//
6131 // SSE4.1 - Round Instructions
6132 //===----------------------------------------------------------------------===//
6134 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6135 X86MemOperand x86memop, RegisterClass RC,
6136 PatFrag mem_frag32, PatFrag mem_frag64,
6137 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6138 let ExeDomain = SSEPackedSingle in {
6139 // Intrinsic operation, reg.
6140 // Vector intrinsic operation, reg
6141 def PSr : SS4AIi8<opcps, MRMSrcReg,
6142 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6143 !strconcat(OpcodeStr,
6144 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6145 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6148 // Vector intrinsic operation, mem
6149 def PSm : SS4AIi8<opcps, MRMSrcMem,
6150 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6151 !strconcat(OpcodeStr,
6152 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6154 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6156 } // ExeDomain = SSEPackedSingle
6158 let ExeDomain = SSEPackedDouble in {
6159 // Vector intrinsic operation, reg
6160 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6161 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6162 !strconcat(OpcodeStr,
6163 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6164 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6167 // Vector intrinsic operation, mem
6168 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6169 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6170 !strconcat(OpcodeStr,
6171 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6173 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6175 } // ExeDomain = SSEPackedDouble
6178 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6181 Intrinsic F64Int, bit Is2Addr = 1> {
6182 let ExeDomain = GenericDomain in {
6184 def SSr : SS4AIi8<opcss, MRMSrcReg,
6185 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6187 !strconcat(OpcodeStr,
6188 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6189 !strconcat(OpcodeStr,
6190 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6193 // Intrinsic operation, reg.
6194 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6195 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6197 !strconcat(OpcodeStr,
6198 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6199 !strconcat(OpcodeStr,
6200 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6201 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6204 // Intrinsic operation, mem.
6205 def SSm : SS4AIi8<opcss, MRMSrcMem,
6206 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6208 !strconcat(OpcodeStr,
6209 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6210 !strconcat(OpcodeStr,
6211 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6213 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6217 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6218 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6220 !strconcat(OpcodeStr,
6221 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6222 !strconcat(OpcodeStr,
6223 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6226 // Intrinsic operation, reg.
6227 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6228 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6230 !strconcat(OpcodeStr,
6231 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6232 !strconcat(OpcodeStr,
6233 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6234 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6237 // Intrinsic operation, mem.
6238 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6239 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6241 !strconcat(OpcodeStr,
6242 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6243 !strconcat(OpcodeStr,
6244 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6246 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6248 } // ExeDomain = GenericDomain
6251 // FP round - roundss, roundps, roundsd, roundpd
6252 let Predicates = [HasAVX] in {
6254 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6255 memopv4f32, memopv2f64,
6256 int_x86_sse41_round_ps,
6257 int_x86_sse41_round_pd>, VEX;
6258 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6259 memopv8f32, memopv4f64,
6260 int_x86_avx_round_ps_256,
6261 int_x86_avx_round_pd_256>, VEX;
6262 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6263 int_x86_sse41_round_ss,
6264 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6266 def : Pat<(ffloor FR32:$src),
6267 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6268 def : Pat<(f64 (ffloor FR64:$src)),
6269 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6270 def : Pat<(f32 (fnearbyint FR32:$src)),
6271 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6272 def : Pat<(f64 (fnearbyint FR64:$src)),
6273 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6274 def : Pat<(f32 (fceil FR32:$src)),
6275 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6276 def : Pat<(f64 (fceil FR64:$src)),
6277 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6278 def : Pat<(f32 (frint FR32:$src)),
6279 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6280 def : Pat<(f64 (frint FR64:$src)),
6281 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6282 def : Pat<(f32 (ftrunc FR32:$src)),
6283 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6284 def : Pat<(f64 (ftrunc FR64:$src)),
6285 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6288 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6289 memopv4f32, memopv2f64,
6290 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6291 let Constraints = "$src1 = $dst" in
6292 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6293 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6295 def : Pat<(ffloor FR32:$src),
6296 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6297 def : Pat<(f64 (ffloor FR64:$src)),
6298 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6299 def : Pat<(f32 (fnearbyint FR32:$src)),
6300 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6301 def : Pat<(f64 (fnearbyint FR64:$src)),
6302 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6303 def : Pat<(f32 (fceil FR32:$src)),
6304 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6305 def : Pat<(f64 (fceil FR64:$src)),
6306 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6307 def : Pat<(f32 (frint FR32:$src)),
6308 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6309 def : Pat<(f64 (frint FR64:$src)),
6310 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6311 def : Pat<(f32 (ftrunc FR32:$src)),
6312 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6313 def : Pat<(f64 (ftrunc FR64:$src)),
6314 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6316 //===----------------------------------------------------------------------===//
6317 // SSE4.1 - Packed Bit Test
6318 //===----------------------------------------------------------------------===//
6320 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6321 // the intel intrinsic that corresponds to this.
6322 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6323 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6324 "vptest\t{$src2, $src1|$src1, $src2}",
6325 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6327 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6328 "vptest\t{$src2, $src1|$src1, $src2}",
6329 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6332 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6333 "vptest\t{$src2, $src1|$src1, $src2}",
6334 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6336 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6337 "vptest\t{$src2, $src1|$src1, $src2}",
6338 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6342 let Defs = [EFLAGS] in {
6343 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6344 "ptest\t{$src2, $src1|$src1, $src2}",
6345 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6347 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6348 "ptest\t{$src2, $src1|$src1, $src2}",
6349 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6353 // The bit test instructions below are AVX only
6354 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6355 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6356 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6357 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6358 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6359 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6360 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6361 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6365 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6366 let ExeDomain = SSEPackedSingle in {
6367 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6368 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6370 let ExeDomain = SSEPackedDouble in {
6371 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6372 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6376 //===----------------------------------------------------------------------===//
6377 // SSE4.1 - Misc Instructions
6378 //===----------------------------------------------------------------------===//
6380 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6381 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6382 "popcnt{w}\t{$src, $dst|$dst, $src}",
6383 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6385 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6386 "popcnt{w}\t{$src, $dst|$dst, $src}",
6387 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6388 (implicit EFLAGS)]>, OpSize, XS;
6390 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6391 "popcnt{l}\t{$src, $dst|$dst, $src}",
6392 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6394 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6395 "popcnt{l}\t{$src, $dst|$dst, $src}",
6396 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6397 (implicit EFLAGS)]>, XS;
6399 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6400 "popcnt{q}\t{$src, $dst|$dst, $src}",
6401 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6403 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6404 "popcnt{q}\t{$src, $dst|$dst, $src}",
6405 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6406 (implicit EFLAGS)]>, XS;
6411 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6412 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6413 Intrinsic IntId128> {
6414 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6416 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6417 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6418 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6420 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6423 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6426 let Predicates = [HasAVX] in
6427 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6428 int_x86_sse41_phminposuw>, VEX;
6429 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6430 int_x86_sse41_phminposuw>;
6432 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6433 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6434 Intrinsic IntId128, bit Is2Addr = 1> {
6435 let isCommutable = 1 in
6436 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6437 (ins VR128:$src1, VR128:$src2),
6439 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6440 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6441 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6442 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6443 (ins VR128:$src1, i128mem:$src2),
6445 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6446 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6448 (IntId128 VR128:$src1,
6449 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6452 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6453 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6454 Intrinsic IntId256> {
6455 let isCommutable = 1 in
6456 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6457 (ins VR256:$src1, VR256:$src2),
6458 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6459 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6460 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6461 (ins VR256:$src1, i256mem:$src2),
6462 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6464 (IntId256 VR256:$src1,
6465 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6468 let Predicates = [HasAVX] in {
6469 let isCommutable = 0 in
6470 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6472 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6474 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6476 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6478 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6480 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6482 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6484 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6486 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6488 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6492 let Predicates = [HasAVX2] in {
6493 let isCommutable = 0 in
6494 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6495 int_x86_avx2_packusdw>, VEX_4V;
6496 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6497 int_x86_avx2_pmins_b>, VEX_4V;
6498 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6499 int_x86_avx2_pmins_d>, VEX_4V;
6500 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6501 int_x86_avx2_pminu_d>, VEX_4V;
6502 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6503 int_x86_avx2_pminu_w>, VEX_4V;
6504 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6505 int_x86_avx2_pmaxs_b>, VEX_4V;
6506 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6507 int_x86_avx2_pmaxs_d>, VEX_4V;
6508 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6509 int_x86_avx2_pmaxu_d>, VEX_4V;
6510 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6511 int_x86_avx2_pmaxu_w>, VEX_4V;
6512 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6513 int_x86_avx2_pmul_dq>, VEX_4V;
6516 let Constraints = "$src1 = $dst" in {
6517 let isCommutable = 0 in
6518 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6519 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6520 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6521 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6522 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6523 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6524 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6525 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6526 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6527 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6530 /// SS48I_binop_rm - Simple SSE41 binary operator.
6531 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6532 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6533 X86MemOperand x86memop, bit Is2Addr = 1> {
6534 let isCommutable = 1 in
6535 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6536 (ins RC:$src1, RC:$src2),
6538 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6539 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6540 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6541 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6542 (ins RC:$src1, x86memop:$src2),
6544 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6545 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6547 (OpVT (OpNode RC:$src1,
6548 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6551 let Predicates = [HasAVX] in {
6552 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6553 memopv2i64, i128mem, 0>, VEX_4V;
6554 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6555 memopv2i64, i128mem, 0>, VEX_4V;
6557 let Predicates = [HasAVX2] in {
6558 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6559 memopv4i64, i256mem, 0>, VEX_4V;
6560 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6561 memopv4i64, i256mem, 0>, VEX_4V;
6564 let Constraints = "$src1 = $dst" in {
6565 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6566 memopv2i64, i128mem>;
6567 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6568 memopv2i64, i128mem>;
6571 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6572 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6573 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6574 X86MemOperand x86memop, bit Is2Addr = 1> {
6575 let isCommutable = 1 in
6576 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6577 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6579 !strconcat(OpcodeStr,
6580 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6581 !strconcat(OpcodeStr,
6582 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6583 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6585 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6586 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6588 !strconcat(OpcodeStr,
6589 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6590 !strconcat(OpcodeStr,
6591 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6594 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6598 let Predicates = [HasAVX] in {
6599 let isCommutable = 0 in {
6600 let ExeDomain = SSEPackedSingle in {
6601 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6602 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6603 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6604 int_x86_avx_blend_ps_256, VR256, memopv8f32, i256mem, 0>, VEX_4V;
6606 let ExeDomain = SSEPackedDouble in {
6607 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6608 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6609 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6610 int_x86_avx_blend_pd_256, VR256, memopv4f64, i256mem, 0>, VEX_4V;
6612 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6613 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6614 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6615 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6617 let ExeDomain = SSEPackedSingle in
6618 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6619 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6620 let ExeDomain = SSEPackedDouble in
6621 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6622 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6623 let ExeDomain = SSEPackedSingle in
6624 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6625 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6628 let Predicates = [HasAVX2] in {
6629 let isCommutable = 0 in {
6630 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6631 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6632 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6633 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6637 let Constraints = "$src1 = $dst" in {
6638 let isCommutable = 0 in {
6639 let ExeDomain = SSEPackedSingle in
6640 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6641 VR128, memopv4f32, i128mem>;
6642 let ExeDomain = SSEPackedDouble in
6643 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6644 VR128, memopv2f64, i128mem>;
6645 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6646 VR128, memopv2i64, i128mem>;
6647 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6648 VR128, memopv2i64, i128mem>;
6650 let ExeDomain = SSEPackedSingle in
6651 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6652 VR128, memopv4f32, i128mem>;
6653 let ExeDomain = SSEPackedDouble in
6654 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6655 VR128, memopv2f64, i128mem>;
6658 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6659 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6660 RegisterClass RC, X86MemOperand x86memop,
6661 PatFrag mem_frag, Intrinsic IntId> {
6662 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6663 (ins RC:$src1, RC:$src2, RC:$src3),
6664 !strconcat(OpcodeStr,
6665 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6666 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6667 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6669 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6670 (ins RC:$src1, x86memop:$src2, RC:$src3),
6671 !strconcat(OpcodeStr,
6672 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6674 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6676 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6679 let Predicates = [HasAVX] in {
6680 let ExeDomain = SSEPackedDouble in {
6681 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
6682 memopv2f64, int_x86_sse41_blendvpd>;
6683 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
6684 memopv4f64, int_x86_avx_blendv_pd_256>;
6685 } // ExeDomain = SSEPackedDouble
6686 let ExeDomain = SSEPackedSingle in {
6687 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
6688 memopv4f32, int_x86_sse41_blendvps>;
6689 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
6690 memopv8f32, int_x86_avx_blendv_ps_256>;
6691 } // ExeDomain = SSEPackedSingle
6692 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6693 memopv2i64, int_x86_sse41_pblendvb>;
6696 let Predicates = [HasAVX2] in {
6697 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6698 memopv4i64, int_x86_avx2_pblendvb>;
6701 let Predicates = [HasAVX] in {
6702 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6703 (v16i8 VR128:$src2))),
6704 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6705 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6706 (v4i32 VR128:$src2))),
6707 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6708 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6709 (v4f32 VR128:$src2))),
6710 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6711 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6712 (v2i64 VR128:$src2))),
6713 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6714 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6715 (v2f64 VR128:$src2))),
6716 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6717 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6718 (v8i32 VR256:$src2))),
6719 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6720 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6721 (v8f32 VR256:$src2))),
6722 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6723 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6724 (v4i64 VR256:$src2))),
6725 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6726 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6727 (v4f64 VR256:$src2))),
6728 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6730 def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6732 (VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6733 def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6735 (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6737 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6739 (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6740 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6742 (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6743 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6745 (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6748 let Predicates = [HasAVX2] in {
6749 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6750 (v32i8 VR256:$src2))),
6751 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6752 def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6754 (VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6757 /// SS41I_ternary_int - SSE 4.1 ternary operator
6758 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6759 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6761 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6762 (ins VR128:$src1, VR128:$src2),
6763 !strconcat(OpcodeStr,
6764 "\t{$src2, $dst|$dst, $src2}"),
6765 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6768 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6769 (ins VR128:$src1, i128mem:$src2),
6770 !strconcat(OpcodeStr,
6771 "\t{$src2, $dst|$dst, $src2}"),
6774 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6778 let ExeDomain = SSEPackedDouble in
6779 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64,
6780 int_x86_sse41_blendvpd>;
6781 let ExeDomain = SSEPackedSingle in
6782 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32,
6783 int_x86_sse41_blendvps>;
6784 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64,
6785 int_x86_sse41_pblendvb>;
6787 let Predicates = [HasSSE41] in {
6788 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6789 (v16i8 VR128:$src2))),
6790 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6791 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6792 (v4i32 VR128:$src2))),
6793 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6794 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6795 (v4f32 VR128:$src2))),
6796 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6797 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6798 (v2i64 VR128:$src2))),
6799 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6800 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6801 (v2f64 VR128:$src2))),
6802 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6804 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6806 (PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6807 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6809 (BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6810 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6812 (BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6816 let Predicates = [HasAVX] in
6817 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6818 "vmovntdqa\t{$src, $dst|$dst, $src}",
6819 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6821 let Predicates = [HasAVX2] in
6822 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6823 "vmovntdqa\t{$src, $dst|$dst, $src}",
6824 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6826 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6827 "movntdqa\t{$src, $dst|$dst, $src}",
6828 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6831 //===----------------------------------------------------------------------===//
6832 // SSE4.2 - Compare Instructions
6833 //===----------------------------------------------------------------------===//
6835 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6836 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6837 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6838 X86MemOperand x86memop, bit Is2Addr = 1> {
6839 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6840 (ins RC:$src1, RC:$src2),
6842 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6843 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6844 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6846 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6847 (ins RC:$src1, x86memop:$src2),
6849 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6850 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6852 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6855 let Predicates = [HasAVX] in
6856 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6857 memopv2i64, i128mem, 0>, VEX_4V;
6859 let Predicates = [HasAVX2] in
6860 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6861 memopv4i64, i256mem, 0>, VEX_4V;
6863 let Constraints = "$src1 = $dst" in
6864 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6865 memopv2i64, i128mem>;
6867 //===----------------------------------------------------------------------===//
6868 // SSE4.2 - String/text Processing Instructions
6869 //===----------------------------------------------------------------------===//
6871 // Packed Compare Implicit Length Strings, Return Mask
6872 multiclass pseudo_pcmpistrm<string asm> {
6873 def REG : PseudoI<(outs VR128:$dst),
6874 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6875 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6877 def MEM : PseudoI<(outs VR128:$dst),
6878 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6879 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6880 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6883 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6884 let AddedComplexity = 1 in
6885 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6886 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6889 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6890 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6891 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6892 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6894 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6895 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6896 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6899 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6900 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6901 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6902 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6904 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6905 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6906 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6909 // Packed Compare Explicit Length Strings, Return Mask
6910 multiclass pseudo_pcmpestrm<string asm> {
6911 def REG : PseudoI<(outs VR128:$dst),
6912 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6913 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6914 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6915 def MEM : PseudoI<(outs VR128:$dst),
6916 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6917 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6918 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6921 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6922 let AddedComplexity = 1 in
6923 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6924 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6927 let Predicates = [HasAVX],
6928 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6929 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6930 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6931 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6933 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6934 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6935 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6938 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6939 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6940 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6941 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6943 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6944 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6945 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6948 // Packed Compare Implicit Length Strings, Return Index
6949 let Defs = [ECX, EFLAGS] in {
6950 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6951 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6952 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6953 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6954 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6955 (implicit EFLAGS)]>, OpSize;
6956 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6957 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6958 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6959 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6960 (implicit EFLAGS)]>, OpSize;
6964 let Predicates = [HasAVX] in {
6965 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6967 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6969 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6971 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6973 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6975 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6979 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6980 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6981 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6982 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6983 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6984 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6986 // Packed Compare Explicit Length Strings, Return Index
6987 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6988 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6989 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6990 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6991 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6992 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6993 (implicit EFLAGS)]>, OpSize;
6994 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6995 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6996 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6998 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6999 (implicit EFLAGS)]>, OpSize;
7003 let Predicates = [HasAVX] in {
7004 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
7006 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
7008 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
7010 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
7012 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
7014 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
7018 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
7019 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
7020 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
7021 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
7022 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
7023 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
7025 //===----------------------------------------------------------------------===//
7026 // SSE4.2 - CRC Instructions
7027 //===----------------------------------------------------------------------===//
7029 // No CRC instructions have AVX equivalents
7031 // crc intrinsic instruction
7032 // This set of instructions are only rm, the only difference is the size
7034 let Constraints = "$src1 = $dst" in {
7035 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7036 (ins GR32:$src1, i8mem:$src2),
7037 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7039 (int_x86_sse42_crc32_32_8 GR32:$src1,
7040 (load addr:$src2)))]>;
7041 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7042 (ins GR32:$src1, GR8:$src2),
7043 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7045 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
7046 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7047 (ins GR32:$src1, i16mem:$src2),
7048 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7050 (int_x86_sse42_crc32_32_16 GR32:$src1,
7051 (load addr:$src2)))]>,
7053 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7054 (ins GR32:$src1, GR16:$src2),
7055 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7057 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7059 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7060 (ins GR32:$src1, i32mem:$src2),
7061 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7063 (int_x86_sse42_crc32_32_32 GR32:$src1,
7064 (load addr:$src2)))]>;
7065 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7066 (ins GR32:$src1, GR32:$src2),
7067 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7069 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7070 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7071 (ins GR64:$src1, i8mem:$src2),
7072 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7074 (int_x86_sse42_crc32_64_8 GR64:$src1,
7075 (load addr:$src2)))]>,
7077 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7078 (ins GR64:$src1, GR8:$src2),
7079 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7081 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7083 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7084 (ins GR64:$src1, i64mem:$src2),
7085 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7087 (int_x86_sse42_crc32_64_64 GR64:$src1,
7088 (load addr:$src2)))]>,
7090 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7091 (ins GR64:$src1, GR64:$src2),
7092 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7094 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7098 //===----------------------------------------------------------------------===//
7099 // AES-NI Instructions
7100 //===----------------------------------------------------------------------===//
7102 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7103 Intrinsic IntId128, bit Is2Addr = 1> {
7104 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7105 (ins VR128:$src1, VR128:$src2),
7107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7108 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7109 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7111 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7112 (ins VR128:$src1, i128mem:$src2),
7114 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7115 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7117 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7120 // Perform One Round of an AES Encryption/Decryption Flow
7121 let Predicates = [HasAVX, HasAES] in {
7122 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7123 int_x86_aesni_aesenc, 0>, VEX_4V;
7124 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7125 int_x86_aesni_aesenclast, 0>, VEX_4V;
7126 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7127 int_x86_aesni_aesdec, 0>, VEX_4V;
7128 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7129 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7132 let Constraints = "$src1 = $dst" in {
7133 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7134 int_x86_aesni_aesenc>;
7135 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7136 int_x86_aesni_aesenclast>;
7137 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7138 int_x86_aesni_aesdec>;
7139 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7140 int_x86_aesni_aesdeclast>;
7143 // Perform the AES InvMixColumn Transformation
7144 let Predicates = [HasAVX, HasAES] in {
7145 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7147 "vaesimc\t{$src1, $dst|$dst, $src1}",
7149 (int_x86_aesni_aesimc VR128:$src1))]>,
7151 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7152 (ins i128mem:$src1),
7153 "vaesimc\t{$src1, $dst|$dst, $src1}",
7154 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7157 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7159 "aesimc\t{$src1, $dst|$dst, $src1}",
7161 (int_x86_aesni_aesimc VR128:$src1))]>,
7163 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7164 (ins i128mem:$src1),
7165 "aesimc\t{$src1, $dst|$dst, $src1}",
7166 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7169 // AES Round Key Generation Assist
7170 let Predicates = [HasAVX, HasAES] in {
7171 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7172 (ins VR128:$src1, i8imm:$src2),
7173 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7175 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7177 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7178 (ins i128mem:$src1, i8imm:$src2),
7179 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7181 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7184 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7185 (ins VR128:$src1, i8imm:$src2),
7186 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7188 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7190 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7191 (ins i128mem:$src1, i8imm:$src2),
7192 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7194 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7197 //===----------------------------------------------------------------------===//
7198 // PCLMUL Instructions
7199 //===----------------------------------------------------------------------===//
7201 // AVX carry-less Multiplication instructions
7202 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7203 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7204 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7206 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7208 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7209 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7210 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7211 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7212 (memopv2i64 addr:$src2), imm:$src3))]>;
7214 // Carry-less Multiplication instructions
7215 let Constraints = "$src1 = $dst" in {
7216 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7217 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7218 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7220 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7222 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7223 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7224 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7225 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7226 (memopv2i64 addr:$src2), imm:$src3))]>;
7227 } // Constraints = "$src1 = $dst"
7230 multiclass pclmul_alias<string asm, int immop> {
7231 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7232 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7234 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7235 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7237 def : InstAlias<!strconcat("vpclmul", asm,
7238 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7239 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7241 def : InstAlias<!strconcat("vpclmul", asm,
7242 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7243 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7245 defm : pclmul_alias<"hqhq", 0x11>;
7246 defm : pclmul_alias<"hqlq", 0x01>;
7247 defm : pclmul_alias<"lqhq", 0x10>;
7248 defm : pclmul_alias<"lqlq", 0x00>;
7250 //===----------------------------------------------------------------------===//
7251 // SSE4A Instructions
7252 //===----------------------------------------------------------------------===//
7254 let Predicates = [HasSSE4A] in {
7256 let Constraints = "$src = $dst" in {
7257 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7258 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7259 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7260 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7261 imm:$idx))]>, TB, OpSize;
7262 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7263 (ins VR128:$src, VR128:$mask),
7264 "extrq\t{$mask, $src|$src, $mask}",
7265 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7266 VR128:$mask))]>, TB, OpSize;
7268 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7269 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7270 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7271 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7272 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7273 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7274 (ins VR128:$src, VR128:$mask),
7275 "insertq\t{$mask, $src|$src, $mask}",
7276 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7277 VR128:$mask))]>, XD;
7280 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7281 "movntss\t{$src, $dst|$dst, $src}",
7282 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7284 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7285 "movntsd\t{$src, $dst|$dst, $src}",
7286 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7289 //===----------------------------------------------------------------------===//
7291 //===----------------------------------------------------------------------===//
7293 //===----------------------------------------------------------------------===//
7294 // VBROADCAST - Load from memory and broadcast to all elements of the
7295 // destination operand
7297 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7298 X86MemOperand x86memop, Intrinsic Int> :
7299 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7300 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7301 [(set RC:$dst, (Int addr:$src))]>, VEX;
7303 // AVX2 adds register forms
7304 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7306 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7307 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7308 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7310 let ExeDomain = SSEPackedSingle in {
7311 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7312 int_x86_avx_vbroadcast_ss>;
7313 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7314 int_x86_avx_vbroadcast_ss_256>;
7316 let ExeDomain = SSEPackedDouble in
7317 def VBROADCASTSDrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7318 int_x86_avx_vbroadcast_sd_256>;
7319 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7320 int_x86_avx_vbroadcastf128_pd_256>;
7322 let ExeDomain = SSEPackedSingle in {
7323 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7324 int_x86_avx2_vbroadcast_ss_ps>;
7325 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7326 int_x86_avx2_vbroadcast_ss_ps_256>;
7328 let ExeDomain = SSEPackedDouble in
7329 def VBROADCASTSDrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7330 int_x86_avx2_vbroadcast_sd_pd_256>;
7332 let Predicates = [HasAVX2] in
7333 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7334 int_x86_avx2_vbroadcasti128>;
7336 let Predicates = [HasAVX] in
7337 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7338 (VBROADCASTF128 addr:$src)>;
7341 //===----------------------------------------------------------------------===//
7342 // VINSERTF128 - Insert packed floating-point values
7344 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7345 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7346 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7347 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7350 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7351 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7352 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7356 let Predicates = [HasAVX] in {
7357 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7359 (VINSERTF128rr VR256:$src1, VR128:$src2,
7360 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7361 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7363 (VINSERTF128rr VR256:$src1, VR128:$src2,
7364 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7365 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7367 (VINSERTF128rr VR256:$src1, VR128:$src2,
7368 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7369 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7371 (VINSERTF128rr VR256:$src1, VR128:$src2,
7372 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7373 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7375 (VINSERTF128rr VR256:$src1, VR128:$src2,
7376 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7377 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7379 (VINSERTF128rr VR256:$src1, VR128:$src2,
7380 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7382 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7384 (VINSERTF128rm VR256:$src1, addr:$src2,
7385 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7386 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7388 (VINSERTF128rm VR256:$src1, addr:$src2,
7389 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7390 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7392 (VINSERTF128rm VR256:$src1, addr:$src2,
7393 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7396 //===----------------------------------------------------------------------===//
7397 // VEXTRACTF128 - Extract packed floating-point values
7399 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7400 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7401 (ins VR256:$src1, i8imm:$src2),
7402 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7405 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7406 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7407 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7411 // Extract and store.
7412 let Predicates = [HasAVX] in {
7413 def : Pat<(alignedstore (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2), addr:$dst),
7414 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7415 def : Pat<(alignedstore (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2), addr:$dst),
7416 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7417 def : Pat<(alignedstore (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2), addr:$dst),
7418 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7420 def : Pat<(int_x86_sse_storeu_ps addr:$dst, (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2)),
7421 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7422 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2)),
7423 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7424 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, (bc_v16i8 (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2))),
7425 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7429 let Predicates = [HasAVX] in {
7430 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
7431 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7432 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
7433 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7434 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
7435 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7437 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7438 (v4f32 (VEXTRACTF128rr
7439 (v8f32 VR256:$src1),
7440 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7441 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7442 (v2f64 (VEXTRACTF128rr
7443 (v4f64 VR256:$src1),
7444 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7445 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7446 (v2i64 (VEXTRACTF128rr
7447 (v4i64 VR256:$src1),
7448 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7449 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7450 (v4i32 (VEXTRACTF128rr
7451 (v8i32 VR256:$src1),
7452 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7453 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7454 (v8i16 (VEXTRACTF128rr
7455 (v16i16 VR256:$src1),
7456 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7457 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7458 (v16i8 (VEXTRACTF128rr
7459 (v32i8 VR256:$src1),
7460 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7463 //===----------------------------------------------------------------------===//
7464 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7466 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7467 Intrinsic IntLd, Intrinsic IntLd256,
7468 Intrinsic IntSt, Intrinsic IntSt256> {
7469 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7470 (ins VR128:$src1, f128mem:$src2),
7471 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7472 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7474 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7475 (ins VR256:$src1, f256mem:$src2),
7476 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7477 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7479 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7480 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7481 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7482 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7483 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7484 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7485 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7486 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7489 let ExeDomain = SSEPackedSingle in
7490 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7491 int_x86_avx_maskload_ps,
7492 int_x86_avx_maskload_ps_256,
7493 int_x86_avx_maskstore_ps,
7494 int_x86_avx_maskstore_ps_256>;
7495 let ExeDomain = SSEPackedDouble in
7496 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7497 int_x86_avx_maskload_pd,
7498 int_x86_avx_maskload_pd_256,
7499 int_x86_avx_maskstore_pd,
7500 int_x86_avx_maskstore_pd_256>;
7502 //===----------------------------------------------------------------------===//
7503 // VPERMIL - Permute Single and Double Floating-Point Values
7505 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7506 RegisterClass RC, X86MemOperand x86memop_f,
7507 X86MemOperand x86memop_i, PatFrag i_frag,
7508 Intrinsic IntVar, ValueType vt> {
7509 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7510 (ins RC:$src1, RC:$src2),
7511 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7512 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7513 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7514 (ins RC:$src1, x86memop_i:$src2),
7515 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7516 [(set RC:$dst, (IntVar RC:$src1,
7517 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7519 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7520 (ins RC:$src1, i8imm:$src2),
7521 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7522 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7523 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7524 (ins x86memop_f:$src1, i8imm:$src2),
7525 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7527 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7530 let ExeDomain = SSEPackedSingle in {
7531 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7532 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7533 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7534 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>;
7536 let ExeDomain = SSEPackedDouble in {
7537 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7538 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7539 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7540 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>;
7543 let Predicates = [HasAVX] in {
7544 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7545 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7546 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7547 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7548 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7550 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7551 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7552 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7554 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7555 (VPERMILPDri VR128:$src1, imm:$imm)>;
7556 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7557 (VPERMILPDmi addr:$src1, imm:$imm)>;
7560 //===----------------------------------------------------------------------===//
7561 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7563 let ExeDomain = SSEPackedSingle in {
7564 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7565 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7566 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7567 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7568 (i8 imm:$src3))))]>, VEX_4V;
7569 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7570 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7571 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7572 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7573 (i8 imm:$src3)))]>, VEX_4V;
7576 let Predicates = [HasAVX] in {
7577 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7578 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7579 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7580 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7581 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7582 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7583 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7584 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7585 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7586 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7588 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1,
7589 (memopv8f32 addr:$src2), (i8 imm:$imm))),
7590 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7591 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7592 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7593 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7594 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7595 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7596 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7597 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7598 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7599 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7600 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7601 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7602 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7603 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7604 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7605 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7608 //===----------------------------------------------------------------------===//
7609 // VZERO - Zero YMM registers
7611 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7612 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7613 // Zero All YMM registers
7614 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7615 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7617 // Zero Upper bits of YMM registers
7618 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7619 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7622 //===----------------------------------------------------------------------===//
7623 // Half precision conversion instructions
7624 //===----------------------------------------------------------------------===//
7625 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7626 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7627 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7628 [(set RC:$dst, (Int VR128:$src))]>,
7630 let neverHasSideEffects = 1, mayLoad = 1 in
7631 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7632 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7635 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7636 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7637 (ins RC:$src1, i32i8imm:$src2),
7638 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7639 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7641 let neverHasSideEffects = 1, mayStore = 1 in
7642 def mr : Ii8<0x1D, MRMDestMem, (outs),
7643 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7644 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7648 let Predicates = [HasAVX, HasF16C] in {
7649 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7650 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7651 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7652 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7655 //===----------------------------------------------------------------------===//
7656 // AVX2 Instructions
7657 //===----------------------------------------------------------------------===//
7659 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7660 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7661 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7662 X86MemOperand x86memop> {
7663 let isCommutable = 1 in
7664 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7665 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7666 !strconcat(OpcodeStr,
7667 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7668 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7670 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7671 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7672 !strconcat(OpcodeStr,
7673 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7676 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7680 let isCommutable = 0 in {
7681 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7682 VR128, memopv2i64, i128mem>;
7683 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7684 VR256, memopv4i64, i256mem>;
7687 //===----------------------------------------------------------------------===//
7688 // VPBROADCAST - Load from memory and broadcast to all elements of the
7689 // destination operand
7691 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7692 X86MemOperand x86memop, PatFrag ld_frag,
7693 Intrinsic Int128, Intrinsic Int256> {
7694 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7695 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7696 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7697 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7698 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7700 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7701 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7702 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7703 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7704 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7705 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7707 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7710 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7711 int_x86_avx2_pbroadcastb_128,
7712 int_x86_avx2_pbroadcastb_256>;
7713 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7714 int_x86_avx2_pbroadcastw_128,
7715 int_x86_avx2_pbroadcastw_256>;
7716 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7717 int_x86_avx2_pbroadcastd_128,
7718 int_x86_avx2_pbroadcastd_256>;
7719 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7720 int_x86_avx2_pbroadcastq_128,
7721 int_x86_avx2_pbroadcastq_256>;
7723 let Predicates = [HasAVX2] in {
7724 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7725 (VPBROADCASTBrm addr:$src)>;
7726 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7727 (VPBROADCASTBYrm addr:$src)>;
7728 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7729 (VPBROADCASTWrm addr:$src)>;
7730 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7731 (VPBROADCASTWYrm addr:$src)>;
7732 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7733 (VPBROADCASTDrm addr:$src)>;
7734 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7735 (VPBROADCASTDYrm addr:$src)>;
7736 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7737 (VPBROADCASTQrm addr:$src)>;
7738 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7739 (VPBROADCASTQYrm addr:$src)>;
7741 // Provide fallback in case the load node that is used in the patterns above
7742 // is used by additional users, which prevents the pattern selection.
7743 let AddedComplexity = 20 in {
7744 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7746 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
7747 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7749 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
7750 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7752 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd))>;
7754 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7756 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
7757 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7759 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
7760 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7762 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd))>;
7766 // AVX1 broadcast patterns
7767 let Predicates = [HasAVX] in {
7768 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7769 (VBROADCASTSSYrm addr:$src)>;
7770 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7771 (VBROADCASTSDrm addr:$src)>;
7772 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7773 (VBROADCASTSSYrm addr:$src)>;
7774 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7775 (VBROADCASTSDrm addr:$src)>;
7776 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7777 (VBROADCASTSSrm addr:$src)>;
7778 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7779 (VBROADCASTSSrm addr:$src)>;
7781 // Provide fallback in case the load node that is used in the patterns above
7782 // is used by additional users, which prevents the pattern selection.
7783 let AddedComplexity = 20 in {
7784 // 128bit broadcasts:
7785 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7787 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0)>;
7788 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7789 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7791 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0),
7794 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss),
7796 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7797 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7799 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd), 0),
7802 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd),
7805 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7807 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0)>;
7808 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7809 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7811 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0),
7814 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss),
7816 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7817 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7819 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd), 0),
7822 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd),
7827 //===----------------------------------------------------------------------===//
7828 // VPERM - Permute instructions
7831 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7833 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7834 (ins VR256:$src1, VR256:$src2),
7835 !strconcat(OpcodeStr,
7836 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7838 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>, VEX_4V;
7839 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7840 (ins VR256:$src1, i256mem:$src2),
7841 !strconcat(OpcodeStr,
7842 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7844 (OpVT (X86VPermv VR256:$src1,
7845 (bitconvert (mem_frag addr:$src2)))))]>,
7849 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7850 let ExeDomain = SSEPackedSingle in
7851 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7853 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7855 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7856 (ins VR256:$src1, i8imm:$src2),
7857 !strconcat(OpcodeStr,
7858 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7860 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>, VEX;
7861 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7862 (ins i256mem:$src1, i8imm:$src2),
7863 !strconcat(OpcodeStr,
7864 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7866 (OpVT (X86VPermi (mem_frag addr:$src1),
7867 (i8 imm:$src2))))]>, VEX;
7870 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7871 let ExeDomain = SSEPackedDouble in
7872 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7874 //===----------------------------------------------------------------------===//
7875 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7877 let AddedComplexity = 1 in {
7878 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7879 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7880 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7881 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7882 (i8 imm:$src3))))]>, VEX_4V;
7883 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7884 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7885 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7886 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7887 (i8 imm:$src3)))]>, VEX_4V;
7890 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7891 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7892 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7893 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7894 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7895 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7896 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7898 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7900 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7901 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7902 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7903 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7904 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7906 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7910 //===----------------------------------------------------------------------===//
7911 // VINSERTI128 - Insert packed integer values
7913 let neverHasSideEffects = 1 in {
7914 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7915 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7916 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7919 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7920 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7921 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7925 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7926 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7928 (VINSERTI128rr VR256:$src1, VR128:$src2,
7929 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7930 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7932 (VINSERTI128rr VR256:$src1, VR128:$src2,
7933 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7934 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7936 (VINSERTI128rr VR256:$src1, VR128:$src2,
7937 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7938 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7940 (VINSERTI128rr VR256:$src1, VR128:$src2,
7941 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7944 //===----------------------------------------------------------------------===//
7945 // VEXTRACTI128 - Extract packed integer values
7947 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7948 (ins VR256:$src1, i8imm:$src2),
7949 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7951 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7953 let neverHasSideEffects = 1, mayStore = 1 in
7954 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7955 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7956 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7958 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7959 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7960 (v2i64 (VEXTRACTI128rr
7961 (v4i64 VR256:$src1),
7962 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7963 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7964 (v4i32 (VEXTRACTI128rr
7965 (v8i32 VR256:$src1),
7966 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7967 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7968 (v8i16 (VEXTRACTI128rr
7969 (v16i16 VR256:$src1),
7970 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7971 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7972 (v16i8 (VEXTRACTI128rr
7973 (v32i8 VR256:$src1),
7974 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7977 //===----------------------------------------------------------------------===//
7978 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7980 multiclass avx2_pmovmask<string OpcodeStr,
7981 Intrinsic IntLd128, Intrinsic IntLd256,
7982 Intrinsic IntSt128, Intrinsic IntSt256> {
7983 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7984 (ins VR128:$src1, i128mem:$src2),
7985 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7986 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7987 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7988 (ins VR256:$src1, i256mem:$src2),
7989 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7990 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7991 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7992 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7993 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7994 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7995 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7996 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7997 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7998 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
8001 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8002 int_x86_avx2_maskload_d,
8003 int_x86_avx2_maskload_d_256,
8004 int_x86_avx2_maskstore_d,
8005 int_x86_avx2_maskstore_d_256>;
8006 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8007 int_x86_avx2_maskload_q,
8008 int_x86_avx2_maskload_q_256,
8009 int_x86_avx2_maskstore_q,
8010 int_x86_avx2_maskstore_q_256>, VEX_W;
8013 //===----------------------------------------------------------------------===//
8014 // Variable Bit Shifts
8016 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8017 ValueType vt128, ValueType vt256> {
8018 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8019 (ins VR128:$src1, VR128:$src2),
8020 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8022 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8024 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8025 (ins VR128:$src1, i128mem:$src2),
8026 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8028 (vt128 (OpNode VR128:$src1,
8029 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8031 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8032 (ins VR256:$src1, VR256:$src2),
8033 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8035 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8037 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8038 (ins VR256:$src1, i256mem:$src2),
8039 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8041 (vt256 (OpNode VR256:$src1,
8042 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8046 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8047 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8048 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8049 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8050 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;