1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 bit rr_hasSideEffects = 0> {
85 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
86 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
88 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
89 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
91 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
93 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
94 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
98 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
99 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
100 string asm, string SSEVer, string FPSizeStr,
101 X86MemOperand x86memop, PatFrag mem_frag,
102 Domain d, bit Is2Addr = 1> {
103 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
105 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
106 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
107 [(set RC:$dst, (!cast<Intrinsic>(
108 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
109 RC:$src1, RC:$src2))], d>;
110 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
112 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
113 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
114 [(set RC:$dst, (!cast<Intrinsic>(
115 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
116 RC:$src1, (mem_frag addr:$src2)))], d>;
119 //===----------------------------------------------------------------------===//
120 // Non-instruction patterns
121 //===----------------------------------------------------------------------===//
123 // A vector extract of the first f32/f64 position is a subregister copy
124 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
125 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
126 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
127 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
129 // A 128-bit subvector extract from the first 256-bit vector position
130 // is a subregister copy that needs no instruction.
131 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
132 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
133 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
134 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
136 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
137 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
138 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
139 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
141 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
142 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
143 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
144 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
146 // A 128-bit subvector insert to the first 256-bit vector position
147 // is a subregister copy that needs no instruction.
148 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
149 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
150 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
151 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
152 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
153 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
154 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
155 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
156 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
157 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
158 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
159 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
161 // Implicitly promote a 32-bit scalar to a vector.
162 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
163 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
164 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
165 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
166 // Implicitly promote a 64-bit scalar to a vector.
167 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
168 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
169 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
170 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
172 // Bitcasts between 128-bit vector types. Return the original type since
173 // no instruction is needed for the conversion
174 let Predicates = [HasXMMInt] in {
175 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
176 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
178 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
179 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
180 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
183 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
184 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
185 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
188 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
189 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
190 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
193 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
194 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
195 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
198 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
199 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
200 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
202 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
203 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
204 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
207 // Bitcasts between 256-bit vector types. Return the original type since
208 // no instruction is needed for the conversion
209 let Predicates = [HasAVX] in {
210 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
211 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
213 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
214 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
215 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
218 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
219 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
220 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
223 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
224 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
225 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
228 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
229 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
230 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
233 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
234 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
235 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
237 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
238 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
239 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
242 // Alias instructions that map fld0 to pxor for sse.
243 // This is expanded by ExpandPostRAPseudos.
244 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
246 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
247 [(set FR32:$dst, fp32imm0)]>, Requires<[HasXMM]>;
248 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
249 [(set FR64:$dst, fpimm0)]>, Requires<[HasXMMInt]>;
252 //===----------------------------------------------------------------------===//
253 // AVX & SSE - Zero/One Vectors
254 //===----------------------------------------------------------------------===//
256 // Alias instruction that maps zero vector to pxor / xorp* for sse.
257 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
258 // swizzled by ExecutionDepsFix to pxor.
259 // We set canFoldAsLoad because this can be converted to a constant-pool
260 // load of an all-zeros value if folding it would be beneficial.
261 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
262 isPseudo = 1, neverHasSideEffects = 1 in {
263 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
266 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
267 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
268 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
269 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
270 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
271 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
274 // The same as done above but for AVX. The 256-bit ISA does not support PI,
275 // and doesn't need it because on sandy bridge the register is set to zero
276 // at the rename stage without using any execution unit, so SET0PSY
277 // and SET0PDY can be used for vector int instructions without penalty
278 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
279 // JIT implementatioan, it does not expand the instructions below like
280 // X86MCInstLower does.
281 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
282 isCodeGenOnly = 1, Predicates = [HasAVX] in {
283 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
284 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
285 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
286 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
290 // AVX has no support for 256-bit integer instructions, but since the 128-bit
291 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
292 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
293 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
294 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
296 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
297 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
298 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
300 // We set canFoldAsLoad because this can be converted to a constant-pool
301 // load of an all-ones value if folding it would be beneficial.
302 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
303 // JIT implementation, it does not expand the instructions below like
304 // X86MCInstLower does.
305 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
306 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
307 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
308 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
309 let Predicates = [HasAVX] in
310 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
311 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
312 let Predicates = [HasAVX2] in
313 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
314 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
318 //===----------------------------------------------------------------------===//
319 // SSE 1 & 2 - Move FP Scalar Instructions
321 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
322 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
323 // is used instead. Register-to-register movss/movsd is not modeled as an
324 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
325 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
326 //===----------------------------------------------------------------------===//
328 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
329 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
330 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
332 // Loading from memory automatically zeroing upper bits.
333 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
334 PatFrag mem_pat, string OpcodeStr> :
335 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
336 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
337 [(set RC:$dst, (mem_pat addr:$src))]>;
340 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
341 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
343 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
344 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
347 // For the disassembler
348 let isCodeGenOnly = 1 in {
349 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
350 (ins VR128:$src1, FR32:$src2),
351 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
353 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
354 (ins VR128:$src1, FR64:$src2),
355 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
359 let canFoldAsLoad = 1, isReMaterializable = 1 in {
360 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
362 let AddedComplexity = 20 in
363 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
367 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
368 "movss\t{$src, $dst|$dst, $src}",
369 [(store FR32:$src, addr:$dst)]>, XS, VEX, VEX_LIG;
370 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
371 "movsd\t{$src, $dst|$dst, $src}",
372 [(store FR64:$src, addr:$dst)]>, XD, VEX, VEX_LIG;
375 let Constraints = "$src1 = $dst" in {
376 def MOVSSrr : sse12_move_rr<FR32, v4f32,
377 "movss\t{$src2, $dst|$dst, $src2}">, XS;
378 def MOVSDrr : sse12_move_rr<FR64, v2f64,
379 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
381 // For the disassembler
382 let isCodeGenOnly = 1 in {
383 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
384 (ins VR128:$src1, FR32:$src2),
385 "movss\t{$src2, $dst|$dst, $src2}", []>, XS;
386 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
387 (ins VR128:$src1, FR64:$src2),
388 "movsd\t{$src2, $dst|$dst, $src2}", []>, XD;
392 let canFoldAsLoad = 1, isReMaterializable = 1 in {
393 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
395 let AddedComplexity = 20 in
396 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
399 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
400 "movss\t{$src, $dst|$dst, $src}",
401 [(store FR32:$src, addr:$dst)]>;
402 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
403 "movsd\t{$src, $dst|$dst, $src}",
404 [(store FR64:$src, addr:$dst)]>;
407 let Predicates = [HasSSE1] in {
408 let AddedComplexity = 15 in {
409 // Extract the low 32-bit value from one vector and insert it into another.
410 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
411 (MOVSSrr (v4f32 VR128:$src1),
412 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
413 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
414 (MOVSSrr (v4i32 VR128:$src1),
415 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
417 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
418 // MOVSS to the lower bits.
419 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
420 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
421 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
422 (MOVSSrr (v4f32 (V_SET0)),
423 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
424 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
425 (MOVSSrr (v4i32 (V_SET0)),
426 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
429 let AddedComplexity = 20 in {
430 // MOVSSrm zeros the high parts of the register; represent this
431 // with SUBREG_TO_REG.
432 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
433 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
434 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
435 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
436 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
437 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
440 // Extract and store.
441 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
444 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
446 // Shuffle with MOVSS
447 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
448 (MOVSSrr VR128:$src1, FR32:$src2)>;
449 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
450 (MOVSSrr (v4i32 VR128:$src1),
451 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
452 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
453 (MOVSSrr (v4f32 VR128:$src1),
454 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
457 let Predicates = [HasSSE2] in {
458 let AddedComplexity = 15 in {
459 // Extract the low 64-bit value from one vector and insert it into another.
460 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
461 (MOVSDrr (v2f64 VR128:$src1),
462 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
463 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
464 (MOVSDrr (v2i64 VR128:$src1),
465 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
467 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
468 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
469 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
470 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
471 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
473 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
474 // MOVSD to the lower bits.
475 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
476 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
479 let AddedComplexity = 20 in {
480 // MOVSDrm zeros the high parts of the register; represent this
481 // with SUBREG_TO_REG.
482 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
483 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
484 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
485 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
486 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
487 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
488 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
489 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
490 def : Pat<(v2f64 (X86vzload addr:$src)),
491 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
494 // Extract and store.
495 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
498 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
500 // Shuffle with MOVSD
501 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
502 (MOVSDrr VR128:$src1, FR64:$src2)>;
503 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
504 (MOVSDrr (v2i64 VR128:$src1),
505 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
506 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
507 (MOVSDrr (v2f64 VR128:$src1),
508 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
509 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
510 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
511 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
512 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
514 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
515 // is during lowering, where it's not possible to recognize the fold cause
516 // it has two uses through a bitcast. One use disappears at isel time and the
517 // fold opportunity reappears.
518 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
519 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
520 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
521 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
522 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
523 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
524 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
525 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
528 let Predicates = [HasAVX] in {
529 let AddedComplexity = 15 in {
530 // Extract the low 32-bit value from one vector and insert it into another.
531 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
532 (VMOVSSrr (v4f32 VR128:$src1),
533 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
534 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
535 (VMOVSSrr (v4i32 VR128:$src1),
536 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
538 // Extract the low 64-bit value from one vector and insert it into another.
539 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
540 (VMOVSDrr (v2f64 VR128:$src1),
541 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
542 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
543 (VMOVSDrr (v2i64 VR128:$src1),
544 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
546 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
547 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
548 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
549 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
550 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
552 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
553 // MOVS{S,D} to the lower bits.
554 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
555 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
556 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
557 (VMOVSSrr (v4f32 (V_SET0)),
558 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
559 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
560 (VMOVSSrr (v4i32 (V_SET0)),
561 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
562 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
563 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
566 let AddedComplexity = 20 in {
567 // MOVSSrm zeros the high parts of the register; represent this
568 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
569 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
570 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
571 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
572 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
573 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
574 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
576 // MOVSDrm zeros the high parts of the register; represent this
577 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
578 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
579 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
580 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
581 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
582 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
583 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
584 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
585 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
586 def : Pat<(v2f64 (X86vzload addr:$src)),
587 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
589 // Represent the same patterns above but in the form they appear for
591 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
592 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
593 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
594 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
595 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
596 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
598 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
599 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
600 (SUBREG_TO_REG (i32 0),
601 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
603 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
604 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
605 (SUBREG_TO_REG (i64 0),
606 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
609 // Extract and store.
610 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
613 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
614 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
617 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
619 // Shuffle with VMOVSS
620 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
621 (VMOVSSrr VR128:$src1, FR32:$src2)>;
622 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
623 (VMOVSSrr (v4i32 VR128:$src1),
624 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
625 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
626 (VMOVSSrr (v4f32 VR128:$src1),
627 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
629 // Shuffle with VMOVSD
630 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
631 (VMOVSDrr VR128:$src1, FR64:$src2)>;
632 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
633 (VMOVSDrr (v2i64 VR128:$src1),
634 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
635 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
636 (VMOVSDrr (v2f64 VR128:$src1),
637 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
638 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
639 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
641 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
642 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
645 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
646 // is during lowering, where it's not possible to recognize the fold cause
647 // it has two uses through a bitcast. One use disappears at isel time and the
648 // fold opportunity reappears.
649 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
650 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
652 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
653 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),
655 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
656 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
658 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
659 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
663 //===----------------------------------------------------------------------===//
664 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
665 //===----------------------------------------------------------------------===//
667 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
668 X86MemOperand x86memop, PatFrag ld_frag,
669 string asm, Domain d,
670 bit IsReMaterializable = 1> {
671 let neverHasSideEffects = 1 in
672 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
673 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
674 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
675 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
676 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
677 [(set RC:$dst, (ld_frag addr:$src))], d>;
680 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
681 "movaps", SSEPackedSingle>, TB, VEX;
682 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
683 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
684 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
685 "movups", SSEPackedSingle>, TB, VEX;
686 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
687 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
689 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
690 "movaps", SSEPackedSingle>, TB, VEX;
691 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
692 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
693 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
694 "movups", SSEPackedSingle>, TB, VEX;
695 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
696 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
697 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
698 "movaps", SSEPackedSingle>, TB;
699 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
700 "movapd", SSEPackedDouble>, TB, OpSize;
701 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
702 "movups", SSEPackedSingle>, TB;
703 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
704 "movupd", SSEPackedDouble, 0>, TB, OpSize;
706 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
707 "movaps\t{$src, $dst|$dst, $src}",
708 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
709 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
710 "movapd\t{$src, $dst|$dst, $src}",
711 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
712 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
713 "movups\t{$src, $dst|$dst, $src}",
714 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
715 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
716 "movupd\t{$src, $dst|$dst, $src}",
717 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
718 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
719 "movaps\t{$src, $dst|$dst, $src}",
720 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)]>, VEX;
721 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
722 "movapd\t{$src, $dst|$dst, $src}",
723 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)]>, VEX;
724 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
725 "movups\t{$src, $dst|$dst, $src}",
726 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
727 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
728 "movupd\t{$src, $dst|$dst, $src}",
729 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
732 let isCodeGenOnly = 1 in {
733 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
735 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
736 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
738 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
739 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
741 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
742 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
744 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
745 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
747 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
748 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
750 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
751 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
753 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
754 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
756 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
759 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
760 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
761 (VMOVUPSYmr addr:$dst, VR256:$src)>;
763 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
764 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
765 (VMOVUPDYmr addr:$dst, VR256:$src)>;
767 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
768 "movaps\t{$src, $dst|$dst, $src}",
769 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
770 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
771 "movapd\t{$src, $dst|$dst, $src}",
772 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
773 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
774 "movups\t{$src, $dst|$dst, $src}",
775 [(store (v4f32 VR128:$src), addr:$dst)]>;
776 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
777 "movupd\t{$src, $dst|$dst, $src}",
778 [(store (v2f64 VR128:$src), addr:$dst)]>;
781 let isCodeGenOnly = 1 in {
782 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
783 "movaps\t{$src, $dst|$dst, $src}", []>;
784 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
785 "movapd\t{$src, $dst|$dst, $src}", []>;
786 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
787 "movups\t{$src, $dst|$dst, $src}", []>;
788 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
789 "movupd\t{$src, $dst|$dst, $src}", []>;
792 let Predicates = [HasAVX] in {
793 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
794 (VMOVUPSmr addr:$dst, VR128:$src)>;
795 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
796 (VMOVUPDmr addr:$dst, VR128:$src)>;
799 let Predicates = [HasSSE1] in
800 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
801 (MOVUPSmr addr:$dst, VR128:$src)>;
802 let Predicates = [HasSSE2] in
803 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
804 (MOVUPDmr addr:$dst, VR128:$src)>;
806 // Use movaps / movups for SSE integer load / store (one byte shorter).
807 // The instructions selected below are then converted to MOVDQA/MOVDQU
808 // during the SSE domain pass.
809 let Predicates = [HasSSE1] in {
810 def : Pat<(alignedloadv4i32 addr:$src),
811 (MOVAPSrm addr:$src)>;
812 def : Pat<(loadv4i32 addr:$src),
813 (MOVUPSrm addr:$src)>;
814 def : Pat<(alignedloadv2i64 addr:$src),
815 (MOVAPSrm addr:$src)>;
816 def : Pat<(loadv2i64 addr:$src),
817 (MOVUPSrm addr:$src)>;
819 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
820 (MOVAPSmr addr:$dst, VR128:$src)>;
821 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
822 (MOVAPSmr addr:$dst, VR128:$src)>;
823 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
824 (MOVAPSmr addr:$dst, VR128:$src)>;
825 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
826 (MOVAPSmr addr:$dst, VR128:$src)>;
827 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
828 (MOVUPSmr addr:$dst, VR128:$src)>;
829 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
830 (MOVUPSmr addr:$dst, VR128:$src)>;
831 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
832 (MOVUPSmr addr:$dst, VR128:$src)>;
833 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
834 (MOVUPSmr addr:$dst, VR128:$src)>;
837 // Use vmovaps/vmovups for AVX integer load/store.
838 let Predicates = [HasAVX] in {
839 // 128-bit load/store
840 def : Pat<(alignedloadv4i32 addr:$src),
841 (VMOVAPSrm addr:$src)>;
842 def : Pat<(loadv4i32 addr:$src),
843 (VMOVUPSrm addr:$src)>;
844 def : Pat<(alignedloadv2i64 addr:$src),
845 (VMOVAPSrm addr:$src)>;
846 def : Pat<(loadv2i64 addr:$src),
847 (VMOVUPSrm addr:$src)>;
849 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
850 (VMOVAPSmr addr:$dst, VR128:$src)>;
851 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
852 (VMOVAPSmr addr:$dst, VR128:$src)>;
853 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
854 (VMOVAPSmr addr:$dst, VR128:$src)>;
855 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
856 (VMOVAPSmr addr:$dst, VR128:$src)>;
857 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
858 (VMOVUPSmr addr:$dst, VR128:$src)>;
859 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
860 (VMOVUPSmr addr:$dst, VR128:$src)>;
861 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
862 (VMOVUPSmr addr:$dst, VR128:$src)>;
863 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
864 (VMOVUPSmr addr:$dst, VR128:$src)>;
866 // 256-bit load/store
867 def : Pat<(alignedloadv4i64 addr:$src),
868 (VMOVAPSYrm addr:$src)>;
869 def : Pat<(loadv4i64 addr:$src),
870 (VMOVUPSYrm addr:$src)>;
871 def : Pat<(alignedloadv8i32 addr:$src),
872 (VMOVAPSYrm addr:$src)>;
873 def : Pat<(loadv8i32 addr:$src),
874 (VMOVUPSYrm addr:$src)>;
875 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
876 (VMOVAPSYmr addr:$dst, VR256:$src)>;
877 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
878 (VMOVAPSYmr addr:$dst, VR256:$src)>;
879 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
880 (VMOVAPSYmr addr:$dst, VR256:$src)>;
881 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
882 (VMOVAPSYmr addr:$dst, VR256:$src)>;
883 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
884 (VMOVUPSYmr addr:$dst, VR256:$src)>;
885 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
886 (VMOVUPSYmr addr:$dst, VR256:$src)>;
887 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
888 (VMOVUPSYmr addr:$dst, VR256:$src)>;
889 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
890 (VMOVUPSYmr addr:$dst, VR256:$src)>;
893 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
894 // bits are disregarded. FIXME: Set encoding to pseudo!
895 let neverHasSideEffects = 1 in {
896 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
897 "movaps\t{$src, $dst|$dst, $src}", []>;
898 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
899 "movapd\t{$src, $dst|$dst, $src}", []>;
900 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
901 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
902 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
903 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
906 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
907 // bits are disregarded. FIXME: Set encoding to pseudo!
908 let canFoldAsLoad = 1, isReMaterializable = 1 in {
909 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
910 "movaps\t{$src, $dst|$dst, $src}",
911 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
912 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
913 "movapd\t{$src, $dst|$dst, $src}",
914 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
915 let isCodeGenOnly = 1 in {
916 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
917 "movaps\t{$src, $dst|$dst, $src}",
918 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
919 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
920 "movapd\t{$src, $dst|$dst, $src}",
921 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
925 //===----------------------------------------------------------------------===//
926 // SSE 1 & 2 - Move Low packed FP Instructions
927 //===----------------------------------------------------------------------===//
929 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
930 PatFrag mov_frag, string base_opc,
932 def PSrm : PI<opc, MRMSrcMem,
933 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
934 !strconcat(base_opc, "s", asm_opr),
937 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
938 SSEPackedSingle>, TB;
940 def PDrm : PI<opc, MRMSrcMem,
941 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
942 !strconcat(base_opc, "d", asm_opr),
943 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
944 (scalar_to_vector (loadf64 addr:$src2)))))],
945 SSEPackedDouble>, TB, OpSize;
948 let AddedComplexity = 20 in {
949 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
950 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
952 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
953 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
954 "\t{$src2, $dst|$dst, $src2}">;
957 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
958 "movlps\t{$src, $dst|$dst, $src}",
959 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
960 (iPTR 0))), addr:$dst)]>, VEX;
961 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
962 "movlpd\t{$src, $dst|$dst, $src}",
963 [(store (f64 (vector_extract (v2f64 VR128:$src),
964 (iPTR 0))), addr:$dst)]>, VEX;
965 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
966 "movlps\t{$src, $dst|$dst, $src}",
967 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
968 (iPTR 0))), addr:$dst)]>;
969 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
970 "movlpd\t{$src, $dst|$dst, $src}",
971 [(store (f64 (vector_extract (v2f64 VR128:$src),
972 (iPTR 0))), addr:$dst)]>;
974 let Predicates = [HasAVX] in {
975 let AddedComplexity = 20 in {
976 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
977 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
978 (VMOVLPSrm VR128:$src1, addr:$src2)>;
979 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
980 (VMOVLPSrm VR128:$src1, addr:$src2)>;
981 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
982 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
983 (VMOVLPDrm VR128:$src1, addr:$src2)>;
984 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
985 (VMOVLPDrm VR128:$src1, addr:$src2)>;
988 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
989 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
990 (VMOVLPSmr addr:$src1, VR128:$src2)>;
991 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
992 VR128:$src2)), addr:$src1),
993 (VMOVLPSmr addr:$src1, VR128:$src2)>;
995 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
996 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
997 (VMOVLPDmr addr:$src1, VR128:$src2)>;
998 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
999 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1001 // Shuffle with VMOVLPS
1002 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1003 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1004 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1005 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1006 def : Pat<(X86Movlps VR128:$src1,
1007 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1008 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1010 // Shuffle with VMOVLPD
1011 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1012 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1013 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1014 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1015 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1016 (scalar_to_vector (loadf64 addr:$src2)))),
1017 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1020 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1022 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1023 def : Pat<(store (v4i32 (X86Movlps
1024 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1025 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1026 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1028 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1029 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1031 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1034 let Predicates = [HasSSE1] in {
1035 let AddedComplexity = 20 in {
1036 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1037 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1038 (MOVLPSrm VR128:$src1, addr:$src2)>;
1039 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1040 (MOVLPSrm VR128:$src1, addr:$src2)>;
1043 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1044 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1045 (iPTR 0))), addr:$src1),
1046 (MOVLPSmr addr:$src1, VR128:$src2)>;
1047 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1048 (MOVLPSmr addr:$src1, VR128:$src2)>;
1049 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1050 VR128:$src2)), addr:$src1),
1051 (MOVLPSmr addr:$src1, VR128:$src2)>;
1053 // Shuffle with MOVLPS
1054 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1055 (MOVLPSrm VR128:$src1, addr:$src2)>;
1056 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1057 (MOVLPSrm VR128:$src1, addr:$src2)>;
1058 def : Pat<(X86Movlps VR128:$src1,
1059 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1060 (MOVLPSrm VR128:$src1, addr:$src2)>;
1061 def : Pat<(X86Movlps VR128:$src1,
1062 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1063 (MOVLPSrm VR128:$src1, addr:$src2)>;
1066 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1068 (MOVLPSmr addr:$src1, VR128:$src2)>;
1069 def : Pat<(store (v4i32 (X86Movlps
1070 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1072 (MOVLPSmr addr:$src1, VR128:$src2)>;
1075 let Predicates = [HasSSE2] in {
1076 let AddedComplexity = 20 in {
1077 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1078 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1079 (MOVLPDrm VR128:$src1, addr:$src2)>;
1080 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1081 (MOVLPDrm VR128:$src1, addr:$src2)>;
1084 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1085 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1086 (MOVLPDmr addr:$src1, VR128:$src2)>;
1087 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1088 (MOVLPDmr addr:$src1, VR128:$src2)>;
1090 // Shuffle with MOVLPD
1091 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1092 (MOVLPDrm VR128:$src1, addr:$src2)>;
1093 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1094 (MOVLPDrm VR128:$src1, addr:$src2)>;
1095 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1096 (scalar_to_vector (loadf64 addr:$src2)))),
1097 (MOVLPDrm VR128:$src1, addr:$src2)>;
1100 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1102 (MOVLPDmr addr:$src1, VR128:$src2)>;
1103 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1105 (MOVLPDmr addr:$src1, VR128:$src2)>;
1108 //===----------------------------------------------------------------------===//
1109 // SSE 1 & 2 - Move Hi packed FP Instructions
1110 //===----------------------------------------------------------------------===//
1112 let AddedComplexity = 20 in {
1113 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1114 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1116 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1117 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1118 "\t{$src2, $dst|$dst, $src2}">;
1121 // v2f64 extract element 1 is always custom lowered to unpack high to low
1122 // and extract element 0 so the non-store version isn't too horrible.
1123 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1124 "movhps\t{$src, $dst|$dst, $src}",
1125 [(store (f64 (vector_extract
1126 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1127 (undef)), (iPTR 0))), addr:$dst)]>,
1129 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1130 "movhpd\t{$src, $dst|$dst, $src}",
1131 [(store (f64 (vector_extract
1132 (v2f64 (unpckh VR128:$src, (undef))),
1133 (iPTR 0))), addr:$dst)]>,
1135 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1136 "movhps\t{$src, $dst|$dst, $src}",
1137 [(store (f64 (vector_extract
1138 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1139 (undef)), (iPTR 0))), addr:$dst)]>;
1140 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1141 "movhpd\t{$src, $dst|$dst, $src}",
1142 [(store (f64 (vector_extract
1143 (v2f64 (unpckh VR128:$src, (undef))),
1144 (iPTR 0))), addr:$dst)]>;
1146 let Predicates = [HasAVX] in {
1148 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1149 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1150 def : Pat<(X86Movlhps VR128:$src1,
1151 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1152 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1153 def : Pat<(X86Movlhps VR128:$src1,
1154 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1155 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1156 def : Pat<(X86Movlhps VR128:$src1,
1157 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1158 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1160 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1161 // is during lowering, where it's not possible to recognize the load fold cause
1162 // it has two uses through a bitcast. One use disappears at isel time and the
1163 // fold opportunity reappears.
1164 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1165 (scalar_to_vector (loadf64 addr:$src2)))),
1166 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1168 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1169 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1170 (scalar_to_vector (loadf64 addr:$src2)))),
1171 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1174 def : Pat<(store (f64 (vector_extract
1175 (v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1176 (VMOVHPSmr addr:$dst, VR128:$src)>;
1177 def : Pat<(store (f64 (vector_extract
1178 (v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1179 (VMOVHPDmr addr:$dst, VR128:$src)>;
1182 let Predicates = [HasSSE1] in {
1184 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1185 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1186 def : Pat<(X86Movlhps VR128:$src1,
1187 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1188 (MOVHPSrm VR128:$src1, addr:$src2)>;
1189 def : Pat<(X86Movlhps VR128:$src1,
1190 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1191 (MOVHPSrm VR128:$src1, addr:$src2)>;
1192 def : Pat<(X86Movlhps VR128:$src1,
1193 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1194 (MOVHPSrm VR128:$src1, addr:$src2)>;
1197 def : Pat<(store (f64 (vector_extract
1198 (v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1199 (MOVHPSmr addr:$dst, VR128:$src)>;
1202 let Predicates = [HasSSE2] in {
1203 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1204 // is during lowering, where it's not possible to recognize the load fold cause
1205 // it has two uses through a bitcast. One use disappears at isel time and the
1206 // fold opportunity reappears.
1207 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1208 (scalar_to_vector (loadf64 addr:$src2)))),
1209 (MOVHPDrm VR128:$src1, addr:$src2)>;
1211 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1212 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1213 (scalar_to_vector (loadf64 addr:$src2)))),
1214 (MOVHPDrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(store (f64 (vector_extract
1218 (v2f64 (X86Unpckh VR128:$src, (undef))), (iPTR 0))),addr:$dst),
1219 (MOVHPDmr addr:$dst, VR128:$src)>;
1222 //===----------------------------------------------------------------------===//
1223 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1224 //===----------------------------------------------------------------------===//
1226 let AddedComplexity = 20 in {
1227 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1228 (ins VR128:$src1, VR128:$src2),
1229 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1231 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
1233 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1234 (ins VR128:$src1, VR128:$src2),
1235 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1237 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
1240 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1241 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1242 (ins VR128:$src1, VR128:$src2),
1243 "movlhps\t{$src2, $dst|$dst, $src2}",
1245 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
1246 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1247 (ins VR128:$src1, VR128:$src2),
1248 "movhlps\t{$src2, $dst|$dst, $src2}",
1250 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
1253 let Predicates = [HasAVX] in {
1255 let AddedComplexity = 20 in {
1256 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1257 (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1258 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1259 (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1261 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1262 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1263 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1265 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1266 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1267 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1268 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1269 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1270 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1273 let AddedComplexity = 20 in {
1274 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1275 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1276 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1278 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1279 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1280 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1281 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1282 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1285 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1286 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1287 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1288 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1291 let Predicates = [HasSSE1] in {
1293 let AddedComplexity = 20 in {
1294 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1295 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1296 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1297 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1299 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1300 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1301 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1303 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1304 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1305 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1306 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1307 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1308 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1311 let AddedComplexity = 20 in {
1312 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1313 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1314 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1316 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1317 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1318 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1319 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1320 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1323 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1324 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1325 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1326 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1329 //===----------------------------------------------------------------------===//
1330 // SSE 1 & 2 - Conversion Instructions
1331 //===----------------------------------------------------------------------===//
1333 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1334 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1336 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1337 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
1338 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1339 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
1342 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1343 X86MemOperand x86memop, string asm> {
1344 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, []>;
1346 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, []>;
1349 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1350 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1351 string asm, Domain d> {
1352 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1353 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
1354 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1355 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
1358 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1359 X86MemOperand x86memop, string asm> {
1360 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1361 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1363 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1364 (ins DstRC:$src1, x86memop:$src),
1365 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1368 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1369 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1371 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1372 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1374 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1375 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX,
1377 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1378 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
1379 VEX, VEX_W, VEX_LIG;
1381 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1382 // register, but the same isn't true when only using memory operands,
1383 // provide other assembly "l" and "q" forms to address this explicitly
1384 // where appropriate to do so.
1385 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
1387 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
1388 VEX_4V, VEX_W, VEX_LIG;
1389 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
1391 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
1393 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
1394 VEX_4V, VEX_W, VEX_LIG;
1396 let Predicates = [HasAVX] in {
1397 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1398 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1399 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1400 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1401 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1402 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1403 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1404 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1406 def : Pat<(f32 (sint_to_fp GR32:$src)),
1407 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1408 def : Pat<(f32 (sint_to_fp GR64:$src)),
1409 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1410 def : Pat<(f64 (sint_to_fp GR32:$src)),
1411 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1412 def : Pat<(f64 (sint_to_fp GR64:$src)),
1413 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1416 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1417 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
1418 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1419 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1420 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1421 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
1422 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1423 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1424 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1425 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
1426 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1427 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1428 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1429 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
1430 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1431 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1433 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1434 // and/or XMM operand(s).
1436 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1437 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1439 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1440 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1441 [(set DstRC:$dst, (Int SrcRC:$src))]>;
1442 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1443 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1444 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
1447 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1448 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1449 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
1450 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1452 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1453 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1454 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
1455 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1456 (ins DstRC:$src1, x86memop:$src2),
1458 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1459 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1460 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
1463 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1464 f128mem, load, "cvtsd2si">, XD, VEX;
1465 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1466 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
1469 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
1470 // Get rid of this hack or rename the intrinsics, there are several
1471 // intructions that only match with the intrinsic form, why create duplicates
1472 // to let them be recognized by the assembler?
1473 defm VCVTSD2SI : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
1474 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_LIG;
1475 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
1476 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W,
1479 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1480 f128mem, load, "cvtsd2si{l}">, XD;
1481 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1482 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
1485 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1486 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
1487 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1488 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
1490 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1491 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
1492 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1493 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
1496 let Constraints = "$src1 = $dst" in {
1497 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1498 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1500 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1501 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1502 "cvtsi2ss{q}">, XS, REX_W;
1503 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1504 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1506 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1507 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1508 "cvtsi2sd">, XD, REX_W;
1513 // Aliases for intrinsics
1514 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1515 f32mem, load, "cvttss2si">, XS, VEX;
1516 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1517 int_x86_sse_cvttss2si64, f32mem, load,
1518 "cvttss2si">, XS, VEX, VEX_W;
1519 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1520 f128mem, load, "cvttsd2si">, XD, VEX;
1521 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1522 int_x86_sse2_cvttsd2si64, f128mem, load,
1523 "cvttsd2si">, XD, VEX, VEX_W;
1524 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1525 f32mem, load, "cvttss2si">, XS;
1526 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1527 int_x86_sse_cvttss2si64, f32mem, load,
1528 "cvttss2si{q}">, XS, REX_W;
1529 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1530 f128mem, load, "cvttsd2si">, XD;
1531 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1532 int_x86_sse2_cvttsd2si64, f128mem, load,
1533 "cvttsd2si{q}">, XD, REX_W;
1535 let Pattern = []<dag> in {
1536 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1537 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS,
1539 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1540 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1542 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1543 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1544 SSEPackedSingle>, TB, VEX;
1545 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1546 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1547 SSEPackedSingle>, TB, VEX;
1550 let Pattern = []<dag> in {
1551 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1552 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
1553 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1554 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1555 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1556 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1557 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
1560 let Predicates = [HasSSE1] in {
1561 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1562 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1563 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1564 (CVTSS2SIrm addr:$src)>;
1565 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1566 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1567 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1568 (CVTSS2SI64rm addr:$src)>;
1571 let Predicates = [HasAVX] in {
1572 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1573 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1574 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1575 (VCVTSS2SIrm addr:$src)>;
1576 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1577 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1578 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1579 (VCVTSS2SI64rm addr:$src)>;
1584 // Convert scalar double to scalar single
1585 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1586 (ins FR64:$src1, FR64:$src2),
1587 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1590 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1591 (ins FR64:$src1, f64mem:$src2),
1592 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1593 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1595 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1598 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1599 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1600 [(set FR32:$dst, (fround FR64:$src))]>;
1601 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1602 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1603 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1604 Requires<[HasSSE2, OptForSize]>;
1606 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1607 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1609 let Constraints = "$src1 = $dst" in
1610 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1611 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1613 // Convert scalar single to scalar double
1614 // SSE2 instructions with XS prefix
1615 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1616 (ins FR32:$src1, FR32:$src2),
1617 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1618 []>, XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1620 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1621 (ins FR32:$src1, f32mem:$src2),
1622 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1623 []>, XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1625 let Predicates = [HasAVX] in {
1626 def : Pat<(f64 (fextend FR32:$src)),
1627 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1628 def : Pat<(fextend (loadf32 addr:$src)),
1629 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1630 def : Pat<(extloadf32 addr:$src),
1631 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1634 def : Pat<(extloadf32 addr:$src),
1635 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1636 Requires<[HasAVX, OptForSpeed]>;
1638 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1639 "cvtss2sd\t{$src, $dst|$dst, $src}",
1640 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1641 Requires<[HasSSE2]>;
1642 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1643 "cvtss2sd\t{$src, $dst|$dst, $src}",
1644 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1645 Requires<[HasSSE2, OptForSize]>;
1647 // extload f32 -> f64. This matches load+fextend because we have a hack in
1648 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1650 // Since these loads aren't folded into the fextend, we have to match it
1652 def : Pat<(fextend (loadf32 addr:$src)),
1653 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1654 def : Pat<(extloadf32 addr:$src),
1655 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1657 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1658 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1659 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1660 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1661 VR128:$src2))]>, XS, VEX_4V,
1663 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1664 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1665 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1666 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1667 (load addr:$src2)))]>, XS, VEX_4V,
1669 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1670 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1671 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1672 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1673 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1674 VR128:$src2))]>, XS,
1675 Requires<[HasSSE2]>;
1676 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1677 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1678 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1679 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1680 (load addr:$src2)))]>, XS,
1681 Requires<[HasSSE2]>;
1684 // Convert doubleword to packed single/double fp
1685 // SSE2 instructions without OpSize prefix
1686 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1687 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1688 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1689 TB, VEX, Requires<[HasAVX]>;
1690 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1691 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1692 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1693 (bitconvert (memopv2i64 addr:$src))))]>,
1694 TB, VEX, Requires<[HasAVX]>;
1695 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1696 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1697 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1698 TB, Requires<[HasSSE2]>;
1699 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1700 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1701 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1702 (bitconvert (memopv2i64 addr:$src))))]>,
1703 TB, Requires<[HasSSE2]>;
1705 // FIXME: why the non-intrinsic version is described as SSE3?
1706 // SSE2 instructions with XS prefix
1707 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1708 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1709 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1710 XS, VEX, Requires<[HasAVX]>;
1711 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1712 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1713 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1714 (bitconvert (memopv2i64 addr:$src))))]>,
1715 XS, VEX, Requires<[HasAVX]>;
1716 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1717 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1718 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1719 XS, Requires<[HasSSE2]>;
1720 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1721 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1722 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1723 (bitconvert (memopv2i64 addr:$src))))]>,
1724 XS, Requires<[HasSSE2]>;
1727 // Convert packed single/double fp to doubleword
1728 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1729 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1730 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1731 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1732 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1733 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1734 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1735 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1736 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1737 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1738 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1739 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1741 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1742 "cvtps2dq\t{$src, $dst|$dst, $src}",
1743 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1745 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1747 "cvtps2dq\t{$src, $dst|$dst, $src}",
1748 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1749 (memop addr:$src)))]>, VEX;
1750 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1751 "cvtps2dq\t{$src, $dst|$dst, $src}",
1752 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1753 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1754 "cvtps2dq\t{$src, $dst|$dst, $src}",
1755 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1756 (memop addr:$src)))]>;
1758 // SSE2 packed instructions with XD prefix
1759 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1760 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1761 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1762 XD, VEX, Requires<[HasAVX]>;
1763 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1764 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1765 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1766 (memop addr:$src)))]>,
1767 XD, VEX, Requires<[HasAVX]>;
1768 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1769 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1770 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1771 XD, Requires<[HasSSE2]>;
1772 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1773 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1774 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1775 (memop addr:$src)))]>,
1776 XD, Requires<[HasSSE2]>;
1779 // Convert with truncation packed single/double fp to doubleword
1780 // SSE2 packed instructions with XS prefix
1781 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1782 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1784 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1785 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1786 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1787 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1789 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1790 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1791 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1792 "cvttps2dq\t{$src, $dst|$dst, $src}",
1794 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1795 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1796 "cvttps2dq\t{$src, $dst|$dst, $src}",
1798 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1800 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1801 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1803 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1804 XS, VEX, Requires<[HasAVX]>;
1805 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1806 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1807 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1808 (memop addr:$src)))]>,
1809 XS, VEX, Requires<[HasAVX]>;
1811 let Predicates = [HasSSE2] in {
1812 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1813 (Int_CVTDQ2PSrr VR128:$src)>;
1814 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1815 (CVTTPS2DQrr VR128:$src)>;
1818 let Predicates = [HasAVX] in {
1819 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1820 (Int_VCVTDQ2PSrr VR128:$src)>;
1821 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1822 (VCVTTPS2DQrr VR128:$src)>;
1823 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1824 (VCVTDQ2PSYrr VR256:$src)>;
1825 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1826 (VCVTTPS2DQYrr VR256:$src)>;
1829 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1830 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1832 (int_x86_sse2_cvttpd2dq VR128:$src))]>, VEX;
1833 let isCodeGenOnly = 1 in
1834 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1835 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1836 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1837 (memop addr:$src)))]>, VEX;
1838 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1839 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1840 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1841 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1842 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1843 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1844 (memop addr:$src)))]>;
1846 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1847 // register, but the same isn't true when using memory operands instead.
1848 // Provide other assembly rr and rm forms to address this explicitly.
1849 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1850 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1853 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1854 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1855 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1856 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1859 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1860 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1861 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1862 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1864 // Convert packed single to packed double
1865 let Predicates = [HasAVX] in {
1866 // SSE2 instructions without OpSize prefix
1867 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1868 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1869 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1870 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1871 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1872 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1873 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1874 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1876 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1877 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1878 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1879 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1881 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1882 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1883 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1884 TB, VEX, Requires<[HasAVX]>;
1885 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1886 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1887 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1888 (load addr:$src)))]>,
1889 TB, VEX, Requires<[HasAVX]>;
1890 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1891 "cvtps2pd\t{$src, $dst|$dst, $src}",
1892 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1893 TB, Requires<[HasSSE2]>;
1894 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1895 "cvtps2pd\t{$src, $dst|$dst, $src}",
1896 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1897 (load addr:$src)))]>,
1898 TB, Requires<[HasSSE2]>;
1900 // Convert packed double to packed single
1901 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1902 // register, but the same isn't true when using memory operands instead.
1903 // Provide other assembly rr and rm forms to address this explicitly.
1904 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1905 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1906 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1907 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1910 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1911 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1912 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1913 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1916 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1917 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1918 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1919 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1920 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1921 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1922 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1923 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1926 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1927 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1928 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1929 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1931 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1932 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1933 (memop addr:$src)))]>;
1934 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1935 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1936 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1937 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1938 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1939 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1940 (memop addr:$src)))]>;
1942 // AVX 256-bit register conversion intrinsics
1943 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1944 // whenever possible to avoid declaring two versions of each one.
1945 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1946 (VCVTDQ2PSYrr VR256:$src)>;
1947 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
1948 (VCVTDQ2PSYrm addr:$src)>;
1950 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1951 (VCVTPD2PSYrr VR256:$src)>;
1952 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1953 (VCVTPD2PSYrm addr:$src)>;
1955 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1956 (VCVTPS2DQYrr VR256:$src)>;
1957 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1958 (VCVTPS2DQYrm addr:$src)>;
1960 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1961 (VCVTPS2PDYrr VR128:$src)>;
1962 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1963 (VCVTPS2PDYrm addr:$src)>;
1965 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1966 (VCVTTPD2DQYrr VR256:$src)>;
1967 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1968 (VCVTTPD2DQYrm addr:$src)>;
1970 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1971 (VCVTTPS2DQYrr VR256:$src)>;
1972 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1973 (VCVTTPS2DQYrm addr:$src)>;
1975 // Match fround and fextend for 128/256-bit conversions
1976 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1977 (VCVTPD2PSYrr VR256:$src)>;
1978 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1979 (VCVTPD2PSYrm addr:$src)>;
1981 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1982 (VCVTPS2PDYrr VR128:$src)>;
1983 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1984 (VCVTPS2PDYrm addr:$src)>;
1986 //===----------------------------------------------------------------------===//
1987 // SSE 1 & 2 - Compare Instructions
1988 //===----------------------------------------------------------------------===//
1990 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1991 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1992 SDNode OpNode, ValueType VT, PatFrag ld_frag,
1993 string asm, string asm_alt> {
1994 def rr : SIi8<0xC2, MRMSrcReg,
1995 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
1996 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))]>;
1997 def rm : SIi8<0xC2, MRMSrcMem,
1998 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
1999 [(set RC:$dst, (OpNode (VT RC:$src1),
2000 (ld_frag addr:$src2), imm:$cc))]>;
2002 // Accept explicit immediate argument form instead of comparison code.
2003 let neverHasSideEffects = 1 in {
2004 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2005 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, []>;
2007 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2008 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, []>;
2012 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2013 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2014 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2015 XS, VEX_4V, VEX_LIG;
2016 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2017 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2018 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2019 XD, VEX_4V, VEX_LIG;
2021 let Constraints = "$src1 = $dst" in {
2022 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2023 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2024 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2026 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2027 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2028 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2032 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
2033 Intrinsic Int, string asm> {
2034 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2035 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
2036 [(set VR128:$dst, (Int VR128:$src1,
2037 VR128:$src, imm:$cc))]>;
2038 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2039 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
2040 [(set VR128:$dst, (Int VR128:$src1,
2041 (load addr:$src), imm:$cc))]>;
2044 // Aliases to match intrinsics which expect XMM operand(s).
2045 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2046 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
2048 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2049 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
2051 let Constraints = "$src1 = $dst" in {
2052 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2053 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
2054 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2055 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
2059 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2060 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2061 ValueType vt, X86MemOperand x86memop,
2062 PatFrag ld_frag, string OpcodeStr, Domain d> {
2063 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2064 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2065 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
2066 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2067 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2068 [(set EFLAGS, (OpNode (vt RC:$src1),
2069 (ld_frag addr:$src2)))], d>;
2072 let Defs = [EFLAGS] in {
2073 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2074 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2075 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2076 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2078 let Pattern = []<dag> in {
2079 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2080 "comiss", SSEPackedSingle>, TB, VEX,
2082 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2083 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2087 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2088 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2089 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2090 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2092 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2093 load, "comiss", SSEPackedSingle>, TB, VEX;
2094 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2095 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2096 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2097 "ucomiss", SSEPackedSingle>, TB;
2098 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2099 "ucomisd", SSEPackedDouble>, TB, OpSize;
2101 let Pattern = []<dag> in {
2102 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2103 "comiss", SSEPackedSingle>, TB;
2104 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2105 "comisd", SSEPackedDouble>, TB, OpSize;
2108 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2109 load, "ucomiss", SSEPackedSingle>, TB;
2110 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2111 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2113 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2114 "comiss", SSEPackedSingle>, TB;
2115 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2116 "comisd", SSEPackedDouble>, TB, OpSize;
2117 } // Defs = [EFLAGS]
2119 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
2120 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2121 Intrinsic Int, string asm, string asm_alt,
2123 let isAsmParserOnly = 1 in {
2124 def rri : PIi8<0xC2, MRMSrcReg,
2125 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2126 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], d>;
2127 def rmi : PIi8<0xC2, MRMSrcMem,
2128 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, SSECC:$cc), asm,
2129 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))], d>;
2132 // Accept explicit immediate argument form instead of comparison code.
2133 def rri_alt : PIi8<0xC2, MRMSrcReg,
2134 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2136 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2137 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, i8imm:$cc),
2141 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2142 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2143 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2144 SSEPackedSingle>, TB, VEX_4V;
2145 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2146 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2147 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2148 SSEPackedDouble>, TB, OpSize, VEX_4V;
2149 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
2150 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2151 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2152 SSEPackedSingle>, TB, VEX_4V;
2153 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
2154 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2155 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2156 SSEPackedDouble>, TB, OpSize, VEX_4V;
2157 let Constraints = "$src1 = $dst" in {
2158 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2159 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2160 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2161 SSEPackedSingle>, TB;
2162 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2163 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2164 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2165 SSEPackedDouble>, TB, OpSize;
2168 let Predicates = [HasSSE1] in {
2169 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2170 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2171 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2172 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2175 let Predicates = [HasSSE2] in {
2176 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2177 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2178 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2179 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2182 let Predicates = [HasAVX] in {
2183 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2184 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2185 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2186 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2187 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2188 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2189 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2190 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2192 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2193 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2194 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2195 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2196 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2197 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2198 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2199 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2202 //===----------------------------------------------------------------------===//
2203 // SSE 1 & 2 - Shuffle Instructions
2204 //===----------------------------------------------------------------------===//
2206 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2207 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2208 ValueType vt, string asm, PatFrag mem_frag,
2209 Domain d, bit IsConvertibleToThreeAddress = 0> {
2210 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2211 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
2212 [(set RC:$dst, (vt (shufp:$src3
2213 RC:$src1, (mem_frag addr:$src2))))], d>;
2214 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2215 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2216 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2218 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
2221 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2222 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2223 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2224 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2225 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2226 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2227 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2228 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2229 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2230 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2231 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2232 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2234 let Constraints = "$src1 = $dst" in {
2235 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2236 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2237 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2239 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2240 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2241 memopv2f64, SSEPackedDouble>, TB, OpSize;
2244 let Predicates = [HasSSE1] in {
2245 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2246 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2247 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2248 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2249 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2250 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2251 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2252 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2253 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2254 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2255 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2256 // fall back to this for SSE1)
2257 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2258 (SHUFPSrri VR128:$src2, VR128:$src1,
2259 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2260 // Special unary SHUFPSrri case.
2261 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2262 (SHUFPSrri VR128:$src1, VR128:$src1,
2263 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2266 let Predicates = [HasSSE2] in {
2267 // Special binary v4i32 shuffle cases with SHUFPS.
2268 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2269 (SHUFPSrri VR128:$src1, VR128:$src2,
2270 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2271 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2272 (bc_v4i32 (memopv2i64 addr:$src2)))),
2273 (SHUFPSrmi VR128:$src1, addr:$src2,
2274 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2275 // Special unary SHUFPDrri cases.
2276 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2277 (SHUFPDrri VR128:$src1, VR128:$src1,
2278 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2279 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2280 (SHUFPDrri VR128:$src1, VR128:$src1,
2281 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2282 // Special binary v2i64 shuffle cases using SHUFPDrri.
2283 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2284 (SHUFPDrri VR128:$src1, VR128:$src2,
2285 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2286 // Generic SHUFPD patterns
2287 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2288 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2289 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2290 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2291 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2292 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2293 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2296 let Predicates = [HasAVX] in {
2297 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2298 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2299 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2300 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2301 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2302 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2303 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2304 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2305 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2306 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2307 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2308 // fall back to this for SSE1)
2309 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2310 (VSHUFPSrri VR128:$src2, VR128:$src1,
2311 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2312 // Special unary SHUFPSrri case.
2313 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2314 (VSHUFPSrri VR128:$src1, VR128:$src1,
2315 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2316 // Special binary v4i32 shuffle cases with SHUFPS.
2317 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2318 (VSHUFPSrri VR128:$src1, VR128:$src2,
2319 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2320 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2321 (bc_v4i32 (memopv2i64 addr:$src2)))),
2322 (VSHUFPSrmi VR128:$src1, addr:$src2,
2323 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2324 // Special unary SHUFPDrri cases.
2325 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2326 (VSHUFPDrri VR128:$src1, VR128:$src1,
2327 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2328 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2329 (VSHUFPDrri VR128:$src1, VR128:$src1,
2330 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2331 // Special binary v2i64 shuffle cases using SHUFPDrri.
2332 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2333 (VSHUFPDrri VR128:$src1, VR128:$src2,
2334 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2336 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2337 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2338 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2339 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2340 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2341 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2342 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2345 def : Pat<(v8i32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2346 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2347 def : Pat<(v8i32 (X86Shufps VR256:$src1,
2348 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2349 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2351 def : Pat<(v8f32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2352 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2353 def : Pat<(v8f32 (X86Shufps VR256:$src1,
2354 (memopv8f32 addr:$src2), (i8 imm:$imm))),
2355 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2357 def : Pat<(v4i64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2358 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2359 def : Pat<(v4i64 (X86Shufpd VR256:$src1,
2360 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2361 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2363 def : Pat<(v4f64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2364 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2365 def : Pat<(v4f64 (X86Shufpd VR256:$src1,
2366 (memopv4f64 addr:$src2), (i8 imm:$imm))),
2367 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2370 //===----------------------------------------------------------------------===//
2371 // SSE 1 & 2 - Unpack Instructions
2372 //===----------------------------------------------------------------------===//
2374 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2375 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
2376 PatFrag mem_frag, RegisterClass RC,
2377 X86MemOperand x86memop, string asm,
2379 def rr : PI<opc, MRMSrcReg,
2380 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2382 (vt (OpNode RC:$src1, RC:$src2)))], d>;
2383 def rm : PI<opc, MRMSrcMem,
2384 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2386 (vt (OpNode RC:$src1,
2387 (mem_frag addr:$src2))))], d>;
2390 let AddedComplexity = 10 in {
2391 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2392 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2393 SSEPackedSingle>, TB, VEX_4V;
2394 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2395 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2396 SSEPackedDouble>, TB, OpSize, VEX_4V;
2397 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2398 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2399 SSEPackedSingle>, TB, VEX_4V;
2400 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2401 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2402 SSEPackedDouble>, TB, OpSize, VEX_4V;
2404 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
2405 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2406 SSEPackedSingle>, TB, VEX_4V;
2407 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
2408 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2409 SSEPackedDouble>, TB, OpSize, VEX_4V;
2410 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
2411 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2412 SSEPackedSingle>, TB, VEX_4V;
2413 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
2414 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2415 SSEPackedDouble>, TB, OpSize, VEX_4V;
2417 let Constraints = "$src1 = $dst" in {
2418 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2419 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2420 SSEPackedSingle>, TB;
2421 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2422 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2423 SSEPackedDouble>, TB, OpSize;
2424 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2425 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2426 SSEPackedSingle>, TB;
2427 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2428 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2429 SSEPackedDouble>, TB, OpSize;
2430 } // Constraints = "$src1 = $dst"
2431 } // AddedComplexity
2433 let Predicates = [HasSSE1] in {
2434 def : Pat<(v4f32 (X86Unpckl VR128:$src1, (memopv4f32 addr:$src2))),
2435 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
2436 def : Pat<(v4f32 (X86Unpckl VR128:$src1, VR128:$src2)),
2437 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
2438 def : Pat<(v4f32 (X86Unpckh VR128:$src1, (memopv4f32 addr:$src2))),
2439 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
2440 def : Pat<(v4f32 (X86Unpckh VR128:$src1, VR128:$src2)),
2441 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
2444 let Predicates = [HasSSE2] in {
2445 def : Pat<(v2f64 (X86Unpckl VR128:$src1, (memopv2f64 addr:$src2))),
2446 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
2447 def : Pat<(v2f64 (X86Unpckl VR128:$src1, VR128:$src2)),
2448 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
2449 def : Pat<(v2f64 (X86Unpckh VR128:$src1, (memopv2f64 addr:$src2))),
2450 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
2451 def : Pat<(v2f64 (X86Unpckh VR128:$src1, VR128:$src2)),
2452 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
2454 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2455 // problem is during lowering, where it's not possible to recognize the load
2456 // fold cause it has two uses through a bitcast. One use disappears at isel
2457 // time and the fold opportunity reappears.
2458 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2459 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2461 let AddedComplexity = 10 in
2462 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2463 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2466 let Predicates = [HasAVX] in {
2467 def : Pat<(v4f32 (X86Unpckl VR128:$src1, (memopv4f32 addr:$src2))),
2468 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
2469 def : Pat<(v4f32 (X86Unpckl VR128:$src1, VR128:$src2)),
2470 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
2471 def : Pat<(v4f32 (X86Unpckh VR128:$src1, (memopv4f32 addr:$src2))),
2472 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
2473 def : Pat<(v4f32 (X86Unpckh VR128:$src1, VR128:$src2)),
2474 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
2476 def : Pat<(v8f32 (X86Unpckl VR256:$src1, (memopv8f32 addr:$src2))),
2477 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2478 def : Pat<(v8f32 (X86Unpckl VR256:$src1, VR256:$src2)),
2479 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2480 def : Pat<(v8f32 (X86Unpckh VR256:$src1, (memopv8f32 addr:$src2))),
2481 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2482 def : Pat<(v8f32 (X86Unpckh VR256:$src1, VR256:$src2)),
2483 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2485 def : Pat<(v2f64 (X86Unpckl VR128:$src1, (memopv2f64 addr:$src2))),
2486 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
2487 def : Pat<(v2f64 (X86Unpckl VR128:$src1, VR128:$src2)),
2488 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
2489 def : Pat<(v2f64 (X86Unpckh VR128:$src1, (memopv2f64 addr:$src2))),
2490 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
2491 def : Pat<(v2f64 (X86Unpckh VR128:$src1, VR128:$src2)),
2492 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
2494 def : Pat<(v4f64 (X86Unpckl VR256:$src1, (memopv4f64 addr:$src2))),
2495 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2496 def : Pat<(v4f64 (X86Unpckl VR256:$src1, VR256:$src2)),
2497 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2498 def : Pat<(v4f64 (X86Unpckh VR256:$src1, (memopv4f64 addr:$src2))),
2499 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2500 def : Pat<(v4f64 (X86Unpckh VR256:$src1, VR256:$src2)),
2501 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2503 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2504 // problem is during lowering, where it's not possible to recognize the load
2505 // fold cause it has two uses through a bitcast. One use disappears at isel
2506 // time and the fold opportunity reappears.
2507 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2508 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2509 let AddedComplexity = 10 in
2510 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2511 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2514 //===----------------------------------------------------------------------===//
2515 // SSE 1 & 2 - Extract Floating-Point Sign mask
2516 //===----------------------------------------------------------------------===//
2518 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2519 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2521 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2522 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2523 [(set GR32:$dst, (Int RC:$src))], d>;
2524 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2525 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
2528 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2529 SSEPackedSingle>, TB;
2530 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2531 SSEPackedDouble>, TB, OpSize;
2533 def : Pat<(i32 (X86fgetsign FR32:$src)),
2534 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2535 sub_ss))>, Requires<[HasSSE1]>;
2536 def : Pat<(i64 (X86fgetsign FR32:$src)),
2537 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2538 sub_ss))>, Requires<[HasSSE1]>;
2539 def : Pat<(i32 (X86fgetsign FR64:$src)),
2540 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2541 sub_sd))>, Requires<[HasSSE2]>;
2542 def : Pat<(i64 (X86fgetsign FR64:$src)),
2543 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2544 sub_sd))>, Requires<[HasSSE2]>;
2546 let Predicates = [HasAVX] in {
2547 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2548 "movmskps", SSEPackedSingle>, TB, VEX;
2549 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2550 "movmskpd", SSEPackedDouble>, TB,
2552 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2553 "movmskps", SSEPackedSingle>, TB, VEX;
2554 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2555 "movmskpd", SSEPackedDouble>, TB,
2558 def : Pat<(i32 (X86fgetsign FR32:$src)),
2559 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2561 def : Pat<(i64 (X86fgetsign FR32:$src)),
2562 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2564 def : Pat<(i32 (X86fgetsign FR64:$src)),
2565 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2567 def : Pat<(i64 (X86fgetsign FR64:$src)),
2568 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2572 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2573 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2574 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2575 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2577 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2578 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2579 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2580 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2584 //===----------------------------------------------------------------------===//
2585 // SSE 1 & 2 - Logical Instructions
2586 //===----------------------------------------------------------------------===//
2588 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2590 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2592 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2593 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2595 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2596 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2598 let Constraints = "$src1 = $dst" in {
2599 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2600 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2602 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2603 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2607 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2608 let mayLoad = 0 in {
2609 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2610 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2611 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2614 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2615 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2617 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2619 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2621 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2622 // are all promoted to v2i64, and the patterns are covered by the int
2623 // version. This is needed in SSE only, because v2i64 isn't supported on
2624 // SSE1, but only on SSE2.
2625 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2626 !strconcat(OpcodeStr, "ps"), f128mem, [],
2627 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2628 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2630 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2631 !strconcat(OpcodeStr, "pd"), f128mem,
2632 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2633 (bc_v2i64 (v2f64 VR128:$src2))))],
2634 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2635 (memopv2i64 addr:$src2)))], 0>,
2637 let Constraints = "$src1 = $dst" in {
2638 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2639 !strconcat(OpcodeStr, "ps"), f128mem,
2640 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2641 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2642 (memopv2i64 addr:$src2)))]>, TB;
2644 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2645 !strconcat(OpcodeStr, "pd"), f128mem,
2646 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2647 (bc_v2i64 (v2f64 VR128:$src2))))],
2648 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2649 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2653 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2655 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2657 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2658 !strconcat(OpcodeStr, "ps"), f256mem,
2659 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2660 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2661 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2663 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2664 !strconcat(OpcodeStr, "pd"), f256mem,
2665 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2666 (bc_v4i64 (v4f64 VR256:$src2))))],
2667 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2668 (memopv4i64 addr:$src2)))], 0>,
2672 // AVX 256-bit packed logical ops forms
2673 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2674 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2675 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2676 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2678 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2679 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2680 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2681 let isCommutable = 0 in
2682 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2684 //===----------------------------------------------------------------------===//
2685 // SSE 1 & 2 - Arithmetic Instructions
2686 //===----------------------------------------------------------------------===//
2688 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2691 /// In addition, we also have a special variant of the scalar form here to
2692 /// represent the associated intrinsic operation. This form is unlike the
2693 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2694 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2696 /// These three forms can each be reg+reg or reg+mem.
2699 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2701 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2703 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2704 OpNode, FR32, f32mem, Is2Addr>, XS;
2705 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2706 OpNode, FR64, f64mem, Is2Addr>, XD;
2709 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2711 let mayLoad = 0 in {
2712 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2713 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2714 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2715 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2719 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2721 let mayLoad = 0 in {
2722 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2723 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2724 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2725 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2729 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2731 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2732 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2733 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2734 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2737 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2739 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2740 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2741 SSEPackedSingle, Is2Addr>, TB;
2743 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2744 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2745 SSEPackedDouble, Is2Addr>, TB, OpSize;
2748 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2749 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2750 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2751 SSEPackedSingle, 0>, TB;
2753 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2754 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2755 SSEPackedDouble, 0>, TB, OpSize;
2758 // Binary Arithmetic instructions
2759 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2760 basic_sse12_fp_binop_s_int<0x58, "add", 0>, VEX_4V, VEX_LIG;
2761 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2762 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2763 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2764 basic_sse12_fp_binop_s_int<0x59, "mul", 0>, VEX_4V, VEX_LIG;
2765 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2766 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2768 let isCommutable = 0 in {
2769 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2770 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>, VEX_4V, VEX_LIG;
2771 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2772 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2773 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2774 basic_sse12_fp_binop_s_int<0x5E, "div", 0>, VEX_4V, VEX_LIG;
2775 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2776 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2777 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2778 basic_sse12_fp_binop_s_int<0x5F, "max", 0>, VEX_4V, VEX_LIG;
2779 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2780 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2781 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2782 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2783 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2784 basic_sse12_fp_binop_s_int<0x5D, "min", 0>, VEX_4V, VEX_LIG;
2785 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2786 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2787 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2788 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2791 let Constraints = "$src1 = $dst" in {
2792 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2793 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2794 basic_sse12_fp_binop_s_int<0x58, "add">;
2795 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2796 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2797 basic_sse12_fp_binop_s_int<0x59, "mul">;
2799 let isCommutable = 0 in {
2800 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2801 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2802 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2803 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2804 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2805 basic_sse12_fp_binop_s_int<0x5E, "div">;
2806 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2807 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2808 basic_sse12_fp_binop_s_int<0x5F, "max">,
2809 basic_sse12_fp_binop_p_int<0x5F, "max">;
2810 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2811 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2812 basic_sse12_fp_binop_s_int<0x5D, "min">,
2813 basic_sse12_fp_binop_p_int<0x5D, "min">;
2818 /// In addition, we also have a special variant of the scalar form here to
2819 /// represent the associated intrinsic operation. This form is unlike the
2820 /// plain scalar form, in that it takes an entire vector (instead of a
2821 /// scalar) and leaves the top elements undefined.
2823 /// And, we have a special variant form for a full-vector intrinsic form.
2825 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2826 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2827 SDNode OpNode, Intrinsic F32Int> {
2828 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2829 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2830 [(set FR32:$dst, (OpNode FR32:$src))]>;
2831 // For scalar unary operations, fold a load into the operation
2832 // only in OptForSize mode. It eliminates an instruction, but it also
2833 // eliminates a whole-register clobber (the load), so it introduces a
2834 // partial register update condition.
2835 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2836 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2837 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2838 Requires<[HasSSE1, OptForSize]>;
2839 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2840 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2841 [(set VR128:$dst, (F32Int VR128:$src))]>;
2842 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2843 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2844 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2847 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2848 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2849 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2850 !strconcat(OpcodeStr,
2851 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2853 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2854 !strconcat(OpcodeStr,
2855 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2856 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2857 (ins VR128:$src1, ssmem:$src2),
2858 !strconcat(OpcodeStr,
2859 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2862 /// sse1_fp_unop_p - SSE1 unops in packed form.
2863 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2864 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2865 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2866 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2867 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2868 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2869 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2872 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2873 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2874 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2875 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2876 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2877 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2878 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2879 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2882 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2883 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2884 Intrinsic V4F32Int> {
2885 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2886 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2887 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2888 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2889 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2890 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2893 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2894 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2895 Intrinsic V4F32Int> {
2896 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2897 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2898 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2899 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2900 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2901 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2904 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2905 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2906 SDNode OpNode, Intrinsic F64Int> {
2907 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2908 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2909 [(set FR64:$dst, (OpNode FR64:$src))]>;
2910 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2911 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2912 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2913 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2914 Requires<[HasSSE2, OptForSize]>;
2915 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2916 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2917 [(set VR128:$dst, (F64Int VR128:$src))]>;
2918 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2919 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2920 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2923 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2924 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2925 let neverHasSideEffects = 1 in {
2926 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2927 !strconcat(OpcodeStr,
2928 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2930 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2931 !strconcat(OpcodeStr,
2932 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2934 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2935 (ins VR128:$src1, sdmem:$src2),
2936 !strconcat(OpcodeStr,
2937 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2940 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2941 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2943 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2944 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2945 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2946 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2947 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2948 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2951 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2952 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2953 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2954 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2955 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2956 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2957 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2958 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2961 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2962 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2963 Intrinsic V2F64Int> {
2964 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2965 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2966 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2967 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2968 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2969 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2972 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2973 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2974 Intrinsic V2F64Int> {
2975 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2976 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2977 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2978 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2979 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2980 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2983 let Predicates = [HasAVX] in {
2985 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
2986 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
2988 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
2989 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
2990 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2991 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2992 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
2993 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
2994 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
2995 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
2998 // Reciprocal approximations. Note that these typically require refinement
2999 // in order to obtain suitable precision.
3000 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3001 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
3002 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
3003 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
3004 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
3006 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3007 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
3008 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
3009 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
3010 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
3013 def : Pat<(f32 (fsqrt FR32:$src)),
3014 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3015 def : Pat<(f32 (fsqrt (load addr:$src))),
3016 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3017 Requires<[HasAVX, OptForSize]>;
3018 def : Pat<(f64 (fsqrt FR64:$src)),
3019 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3020 def : Pat<(f64 (fsqrt (load addr:$src))),
3021 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3022 Requires<[HasAVX, OptForSize]>;
3024 def : Pat<(f32 (X86frsqrt FR32:$src)),
3025 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3026 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3027 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3028 Requires<[HasAVX, OptForSize]>;
3030 def : Pat<(f32 (X86frcp FR32:$src)),
3031 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3032 def : Pat<(f32 (X86frcp (load addr:$src))),
3033 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3034 Requires<[HasAVX, OptForSize]>;
3036 let Predicates = [HasAVX] in {
3037 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3038 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3039 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3040 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3042 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3043 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3045 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3046 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3047 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3048 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3050 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3051 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3053 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3054 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3055 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3056 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3058 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3059 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3061 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3062 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3063 (VRCPSSr (f32 (IMPLICIT_DEF)),
3064 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3066 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3067 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3071 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
3072 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
3073 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
3074 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
3075 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
3076 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
3078 // Reciprocal approximations. Note that these typically require refinement
3079 // in order to obtain suitable precision.
3080 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
3081 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
3082 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
3083 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
3084 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
3085 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
3087 // There is no f64 version of the reciprocal approximation instructions.
3089 //===----------------------------------------------------------------------===//
3090 // SSE 1 & 2 - Non-temporal stores
3091 //===----------------------------------------------------------------------===//
3093 let AddedComplexity = 400 in { // Prefer non-temporal versions
3094 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3095 (ins f128mem:$dst, VR128:$src),
3096 "movntps\t{$src, $dst|$dst, $src}",
3097 [(alignednontemporalstore (v4f32 VR128:$src),
3099 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3100 (ins f128mem:$dst, VR128:$src),
3101 "movntpd\t{$src, $dst|$dst, $src}",
3102 [(alignednontemporalstore (v2f64 VR128:$src),
3104 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
3105 (ins f128mem:$dst, VR128:$src),
3106 "movntdq\t{$src, $dst|$dst, $src}",
3107 [(alignednontemporalstore (v2f64 VR128:$src),
3110 let ExeDomain = SSEPackedInt in
3111 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3112 (ins f128mem:$dst, VR128:$src),
3113 "movntdq\t{$src, $dst|$dst, $src}",
3114 [(alignednontemporalstore (v4f32 VR128:$src),
3117 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3118 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3120 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3121 (ins f256mem:$dst, VR256:$src),
3122 "movntps\t{$src, $dst|$dst, $src}",
3123 [(alignednontemporalstore (v8f32 VR256:$src),
3125 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3126 (ins f256mem:$dst, VR256:$src),
3127 "movntpd\t{$src, $dst|$dst, $src}",
3128 [(alignednontemporalstore (v4f64 VR256:$src),
3130 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
3131 (ins f256mem:$dst, VR256:$src),
3132 "movntdq\t{$src, $dst|$dst, $src}",
3133 [(alignednontemporalstore (v4f64 VR256:$src),
3135 let ExeDomain = SSEPackedInt in
3136 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3137 (ins f256mem:$dst, VR256:$src),
3138 "movntdq\t{$src, $dst|$dst, $src}",
3139 [(alignednontemporalstore (v8f32 VR256:$src),
3143 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
3144 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3145 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
3146 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
3147 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
3148 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
3150 let AddedComplexity = 400 in { // Prefer non-temporal versions
3151 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3152 "movntps\t{$src, $dst|$dst, $src}",
3153 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3154 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3155 "movntpd\t{$src, $dst|$dst, $src}",
3156 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
3158 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3159 "movntdq\t{$src, $dst|$dst, $src}",
3160 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
3162 let ExeDomain = SSEPackedInt in
3163 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3164 "movntdq\t{$src, $dst|$dst, $src}",
3165 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3167 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3168 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3170 // There is no AVX form for instructions below this point
3171 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3172 "movnti{l}\t{$src, $dst|$dst, $src}",
3173 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
3174 TB, Requires<[HasSSE2]>;
3175 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3176 "movnti{q}\t{$src, $dst|$dst, $src}",
3177 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
3178 TB, Requires<[HasSSE2]>;
3181 //===----------------------------------------------------------------------===//
3182 // SSE 1 & 2 - Prefetch and memory fence
3183 //===----------------------------------------------------------------------===//
3185 // Prefetch intrinsic.
3186 def PREFETCHT0 : VoPSI<0x18, MRM1m, (outs), (ins i8mem:$src),
3187 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
3188 def PREFETCHT1 : VoPSI<0x18, MRM2m, (outs), (ins i8mem:$src),
3189 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
3190 def PREFETCHT2 : VoPSI<0x18, MRM3m, (outs), (ins i8mem:$src),
3191 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
3192 def PREFETCHNTA : VoPSI<0x18, MRM0m, (outs), (ins i8mem:$src),
3193 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
3196 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3197 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3198 TB, Requires<[HasSSE2]>;
3200 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3201 // was introduced with SSE2, it's backward compatible.
3202 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3204 // Load, store, and memory fence
3205 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3206 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
3207 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3208 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3209 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3210 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3212 def : Pat<(X86SFence), (SFENCE)>;
3213 def : Pat<(X86LFence), (LFENCE)>;
3214 def : Pat<(X86MFence), (MFENCE)>;
3216 //===----------------------------------------------------------------------===//
3217 // SSE 1 & 2 - Load/Store XCSR register
3218 //===----------------------------------------------------------------------===//
3220 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3221 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
3222 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3223 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
3225 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3226 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
3227 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3228 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
3230 //===---------------------------------------------------------------------===//
3231 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3232 //===---------------------------------------------------------------------===//
3234 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3236 let neverHasSideEffects = 1 in {
3237 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3238 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3239 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3240 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3242 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3243 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3244 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3245 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3248 let isCodeGenOnly = 1 in {
3249 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3250 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3251 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3252 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3253 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3254 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3255 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3256 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3259 let canFoldAsLoad = 1, mayLoad = 1 in {
3260 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3261 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3262 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3263 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3264 let Predicates = [HasAVX] in {
3265 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3266 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3267 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3268 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3272 let mayStore = 1 in {
3273 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3274 (ins i128mem:$dst, VR128:$src),
3275 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3276 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3277 (ins i256mem:$dst, VR256:$src),
3278 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3279 let Predicates = [HasAVX] in {
3280 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3281 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3282 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3283 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3287 let neverHasSideEffects = 1 in
3288 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3289 "movdqa\t{$src, $dst|$dst, $src}", []>;
3291 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3292 "movdqu\t{$src, $dst|$dst, $src}",
3293 []>, XS, Requires<[HasSSE2]>;
3296 let isCodeGenOnly = 1 in {
3297 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3298 "movdqa\t{$src, $dst|$dst, $src}", []>;
3300 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3301 "movdqu\t{$src, $dst|$dst, $src}",
3302 []>, XS, Requires<[HasSSE2]>;
3305 let canFoldAsLoad = 1, mayLoad = 1 in {
3306 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3307 "movdqa\t{$src, $dst|$dst, $src}",
3308 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
3309 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3310 "movdqu\t{$src, $dst|$dst, $src}",
3311 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
3312 XS, Requires<[HasSSE2]>;
3315 let mayStore = 1 in {
3316 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3317 "movdqa\t{$src, $dst|$dst, $src}",
3318 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
3319 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3320 "movdqu\t{$src, $dst|$dst, $src}",
3321 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
3322 XS, Requires<[HasSSE2]>;
3325 // Intrinsic forms of MOVDQU load and store
3326 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3327 "vmovdqu\t{$src, $dst|$dst, $src}",
3328 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3329 XS, VEX, Requires<[HasAVX]>;
3331 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3332 "movdqu\t{$src, $dst|$dst, $src}",
3333 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3334 XS, Requires<[HasSSE2]>;
3336 } // ExeDomain = SSEPackedInt
3338 let Predicates = [HasAVX] in {
3339 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
3340 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3341 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3344 //===---------------------------------------------------------------------===//
3345 // SSE2 - Packed Integer Arithmetic Instructions
3346 //===---------------------------------------------------------------------===//
3348 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3350 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3351 RegisterClass RC, PatFrag memop_frag,
3352 X86MemOperand x86memop, bit IsCommutable = 0,
3354 let isCommutable = IsCommutable in
3355 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3356 (ins RC:$src1, RC:$src2),
3358 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3359 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3360 [(set RC:$dst, (IntId RC:$src1, RC:$src2))]>;
3361 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3362 (ins RC:$src1, x86memop:$src2),
3364 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3365 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3366 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))]>;
3369 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
3370 string OpcodeStr, Intrinsic IntId,
3371 Intrinsic IntId2, RegisterClass RC,
3373 // src2 is always 128-bit
3374 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3375 (ins RC:$src1, VR128:$src2),
3377 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3378 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3379 [(set RC:$dst, (IntId RC:$src1, VR128:$src2))]>;
3380 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3381 (ins RC:$src1, i128mem:$src2),
3383 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3384 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3385 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memopv2i64 addr:$src2))))]>;
3386 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3387 (ins RC:$src1, i32i8imm:$src2),
3389 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3390 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3391 [(set RC:$dst, (IntId2 RC:$src1, (i32 imm:$src2)))]>;
3394 /// PDI_binop_rm - Simple SSE2 binary operator.
3395 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3396 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
3397 X86MemOperand x86memop, bit IsCommutable = 0,
3399 let isCommutable = IsCommutable in
3400 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3401 (ins RC:$src1, RC:$src2),
3403 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3404 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3405 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
3406 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3407 (ins RC:$src1, x86memop:$src2),
3409 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3410 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3411 [(set RC:$dst, (OpVT (OpNode RC:$src1,
3412 (bitconvert (memop_frag addr:$src2)))))]>;
3414 } // ExeDomain = SSEPackedInt
3416 // 128-bit Integer Arithmetic
3418 let Predicates = [HasAVX] in {
3419 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3420 i128mem, 1, 0 /*3addr*/>, VEX_4V;
3421 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3422 i128mem, 1, 0>, VEX_4V;
3423 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3424 i128mem, 1, 0>, VEX_4V;
3425 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3426 i128mem, 1, 0>, VEX_4V;
3427 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3428 i128mem, 1, 0>, VEX_4V;
3429 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3430 i128mem, 0, 0>, VEX_4V;
3431 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3432 i128mem, 0, 0>, VEX_4V;
3433 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3434 i128mem, 0, 0>, VEX_4V;
3435 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3436 i128mem, 0, 0>, VEX_4V;
3439 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3440 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3441 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3442 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3443 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3444 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3445 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3446 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3447 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3448 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3449 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3450 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3451 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3452 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3453 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3454 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3455 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3456 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3457 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3458 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3459 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq,
3460 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3461 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3462 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3463 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3464 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3465 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3466 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3467 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3468 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3469 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3470 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3471 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3472 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3473 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3474 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3475 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3476 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3479 let Predicates = [HasAVX2] in {
3480 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3481 i256mem, 1, 0>, VEX_4V;
3482 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3483 i256mem, 1, 0>, VEX_4V;
3484 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3485 i256mem, 1, 0>, VEX_4V;
3486 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3487 i256mem, 1, 0>, VEX_4V;
3488 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3489 i256mem, 1, 0>, VEX_4V;
3490 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3491 i256mem, 0, 0>, VEX_4V;
3492 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3493 i256mem, 0, 0>, VEX_4V;
3494 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3495 i256mem, 0, 0>, VEX_4V;
3496 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3497 i256mem, 0, 0>, VEX_4V;
3500 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3501 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3502 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3503 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3504 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3505 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3506 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3507 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3508 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3509 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3510 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3511 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3512 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3513 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3514 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3515 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3516 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3517 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3518 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3519 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3520 defm VPMULUDQY : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_avx2_pmulu_dq,
3521 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3522 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3523 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3524 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3525 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3526 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3527 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3528 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3529 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3530 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3531 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3532 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3533 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3534 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3535 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3536 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3537 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3540 let Constraints = "$src1 = $dst" in {
3541 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3543 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3545 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3547 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3549 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3551 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3553 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3555 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3557 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3561 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3562 VR128, memopv2i64, i128mem>;
3563 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3564 VR128, memopv2i64, i128mem>;
3565 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3566 VR128, memopv2i64, i128mem>;
3567 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3568 VR128, memopv2i64, i128mem>;
3569 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3570 VR128, memopv2i64, i128mem, 1>;
3571 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3572 VR128, memopv2i64, i128mem, 1>;
3573 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3574 VR128, memopv2i64, i128mem, 1>;
3575 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3576 VR128, memopv2i64, i128mem, 1>;
3577 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3578 VR128, memopv2i64, i128mem, 1>;
3579 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3580 VR128, memopv2i64, i128mem, 1>;
3581 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq,
3582 VR128, memopv2i64, i128mem, 1>;
3583 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3584 VR128, memopv2i64, i128mem, 1>;
3585 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3586 VR128, memopv2i64, i128mem, 1>;
3587 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3588 VR128, memopv2i64, i128mem, 1>;
3589 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3590 VR128, memopv2i64, i128mem, 1>;
3591 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3592 VR128, memopv2i64, i128mem, 1>;
3593 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3594 VR128, memopv2i64, i128mem, 1>;
3595 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3596 VR128, memopv2i64, i128mem, 1>;
3597 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3598 VR128, memopv2i64, i128mem, 1>;
3600 } // Constraints = "$src1 = $dst"
3602 //===---------------------------------------------------------------------===//
3603 // SSE2 - Packed Integer Logical Instructions
3604 //===---------------------------------------------------------------------===//
3606 let Predicates = [HasAVX] in {
3607 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3608 int_x86_sse2_psll_w, int_x86_sse2_pslli_w,
3610 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3611 int_x86_sse2_psll_d, int_x86_sse2_pslli_d,
3613 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3614 int_x86_sse2_psll_q, int_x86_sse2_pslli_q,
3617 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3618 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w,
3620 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3621 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d,
3623 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3624 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q,
3627 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3628 int_x86_sse2_psra_w, int_x86_sse2_psrai_w,
3630 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3631 int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
3634 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
3635 i128mem, 1, 0>, VEX_4V;
3636 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
3637 i128mem, 1, 0>, VEX_4V;
3638 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
3639 i128mem, 1, 0>, VEX_4V;
3640 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
3641 i128mem, 0, 0>, VEX_4V;
3643 let ExeDomain = SSEPackedInt in {
3644 let neverHasSideEffects = 1 in {
3645 // 128-bit logical shifts.
3646 def VPSLLDQri : PDIi8<0x73, MRM7r,
3647 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3648 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3650 def VPSRLDQri : PDIi8<0x73, MRM3r,
3651 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3652 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3654 // PSRADQri doesn't exist in SSE[1-3].
3659 let Predicates = [HasAVX2] in {
3660 defm VPSLLWY : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3661 int_x86_avx2_psll_w, int_x86_avx2_pslli_w,
3663 defm VPSLLDY : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3664 int_x86_avx2_psll_d, int_x86_avx2_pslli_d,
3666 defm VPSLLQY : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3667 int_x86_avx2_psll_q, int_x86_avx2_pslli_q,
3670 defm VPSRLWY : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3671 int_x86_avx2_psrl_w, int_x86_avx2_psrli_w,
3673 defm VPSRLDY : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3674 int_x86_avx2_psrl_d, int_x86_avx2_psrli_d,
3676 defm VPSRLQY : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3677 int_x86_avx2_psrl_q, int_x86_avx2_psrli_q,
3680 defm VPSRAWY : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3681 int_x86_avx2_psra_w, int_x86_avx2_psrai_w,
3683 defm VPSRADY : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3684 int_x86_avx2_psra_d, int_x86_avx2_psrai_d,
3687 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
3688 i256mem, 1, 0>, VEX_4V;
3689 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
3690 i256mem, 1, 0>, VEX_4V;
3691 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
3692 i256mem, 1, 0>, VEX_4V;
3693 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
3694 i256mem, 0, 0>, VEX_4V;
3696 let ExeDomain = SSEPackedInt in {
3697 let neverHasSideEffects = 1 in {
3698 // 128-bit logical shifts.
3699 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3700 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3701 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3703 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3704 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3705 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3707 // PSRADQYri doesn't exist in SSE[1-3].
3712 let Constraints = "$src1 = $dst" in {
3713 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
3714 int_x86_sse2_psll_w, int_x86_sse2_pslli_w,
3716 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
3717 int_x86_sse2_psll_d, int_x86_sse2_pslli_d,
3719 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
3720 int_x86_sse2_psll_q, int_x86_sse2_pslli_q,
3723 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
3724 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w,
3726 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
3727 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d,
3729 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
3730 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q,
3733 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
3734 int_x86_sse2_psra_w, int_x86_sse2_psrai_w,
3736 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
3737 int_x86_sse2_psra_d, int_x86_sse2_psrai_d,
3740 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
3742 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
3744 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
3746 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
3749 let ExeDomain = SSEPackedInt in {
3750 let neverHasSideEffects = 1 in {
3751 // 128-bit logical shifts.
3752 def PSLLDQri : PDIi8<0x73, MRM7r,
3753 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3754 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
3755 def PSRLDQri : PDIi8<0x73, MRM3r,
3756 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3757 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
3758 // PSRADQri doesn't exist in SSE[1-3].
3761 } // Constraints = "$src1 = $dst"
3763 let Predicates = [HasAVX] in {
3764 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3765 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3766 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3767 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3768 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3769 (VPSLLDQri VR128:$src1, imm:$src2)>;
3770 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3771 (VPSRLDQri VR128:$src1, imm:$src2)>;
3772 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3773 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3775 // Shift up / down and insert zero's.
3776 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3777 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3778 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3779 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3782 let Predicates = [HasAVX2] in {
3783 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
3784 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3785 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
3786 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3787 def : Pat<(int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2),
3788 (VPSLLDQYri VR256:$src1, imm:$src2)>;
3789 def : Pat<(int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2),
3790 (VPSRLDQYri VR256:$src1, imm:$src2)>;
3793 let Predicates = [HasSSE2] in {
3794 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3795 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3796 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3797 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3798 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3799 (PSLLDQri VR128:$src1, imm:$src2)>;
3800 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3801 (PSRLDQri VR128:$src1, imm:$src2)>;
3802 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3803 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3805 // Shift up / down and insert zero's.
3806 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3807 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3808 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3809 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3812 //===---------------------------------------------------------------------===//
3813 // SSE2 - Packed Integer Comparison Instructions
3814 //===---------------------------------------------------------------------===//
3816 let Predicates = [HasAVX] in {
3817 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b,
3818 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3819 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w,
3820 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3821 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d,
3822 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3823 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b,
3824 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3825 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w,
3826 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3827 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d,
3828 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3830 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3831 (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
3832 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1,
3833 (bc_v16i8 (memopv2i64 addr:$src2)))),
3834 (VPCMPEQBrm VR128:$src1, addr:$src2)>;
3835 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3836 (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
3837 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1,
3838 (bc_v8i16 (memopv2i64 addr:$src2)))),
3839 (VPCMPEQWrm VR128:$src1, addr:$src2)>;
3840 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3841 (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
3842 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1,
3843 (bc_v4i32 (memopv2i64 addr:$src2)))),
3844 (VPCMPEQDrm VR128:$src1, addr:$src2)>;
3846 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3847 (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
3848 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1,
3849 (bc_v16i8 (memopv2i64 addr:$src2)))),
3850 (VPCMPGTBrm VR128:$src1, addr:$src2)>;
3851 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3852 (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
3853 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1,
3854 (bc_v8i16 (memopv2i64 addr:$src2)))),
3855 (VPCMPGTWrm VR128:$src1, addr:$src2)>;
3856 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3857 (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
3858 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1,
3859 (bc_v4i32 (memopv2i64 addr:$src2)))),
3860 (VPCMPGTDrm VR128:$src1, addr:$src2)>;
3863 let Predicates = [HasAVX2] in {
3864 defm VPCMPEQBY : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_avx2_pcmpeq_b,
3865 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3866 defm VPCMPEQWY : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_avx2_pcmpeq_w,
3867 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3868 defm VPCMPEQDY : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_avx2_pcmpeq_d,
3869 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3870 defm VPCMPGTBY : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_avx2_pcmpgt_b,
3871 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3872 defm VPCMPGTWY : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_avx2_pcmpgt_w,
3873 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3874 defm VPCMPGTDY : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_avx2_pcmpgt_d,
3875 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3877 def : Pat<(v32i8 (X86pcmpeqb VR256:$src1, VR256:$src2)),
3878 (VPCMPEQBYrr VR256:$src1, VR256:$src2)>;
3879 def : Pat<(v32i8 (X86pcmpeqb VR256:$src1,
3880 (bc_v32i8 (memopv4i64 addr:$src2)))),
3881 (VPCMPEQBYrm VR256:$src1, addr:$src2)>;
3882 def : Pat<(v16i16 (X86pcmpeqw VR256:$src1, VR256:$src2)),
3883 (VPCMPEQWYrr VR256:$src1, VR256:$src2)>;
3884 def : Pat<(v16i16 (X86pcmpeqw VR256:$src1,
3885 (bc_v16i16 (memopv4i64 addr:$src2)))),
3886 (VPCMPEQWYrm VR256:$src1, addr:$src2)>;
3887 def : Pat<(v8i32 (X86pcmpeqd VR256:$src1, VR256:$src2)),
3888 (VPCMPEQDYrr VR256:$src1, VR256:$src2)>;
3889 def : Pat<(v8i32 (X86pcmpeqd VR256:$src1,
3890 (bc_v8i32 (memopv4i64 addr:$src2)))),
3891 (VPCMPEQDYrm VR256:$src1, addr:$src2)>;
3893 def : Pat<(v32i8 (X86pcmpgtb VR256:$src1, VR256:$src2)),
3894 (VPCMPGTBYrr VR256:$src1, VR256:$src2)>;
3895 def : Pat<(v32i8 (X86pcmpgtb VR256:$src1,
3896 (bc_v32i8 (memopv4i64 addr:$src2)))),
3897 (VPCMPGTBYrm VR256:$src1, addr:$src2)>;
3898 def : Pat<(v16i16 (X86pcmpgtw VR256:$src1, VR256:$src2)),
3899 (VPCMPGTWYrr VR256:$src1, VR256:$src2)>;
3900 def : Pat<(v16i16 (X86pcmpgtw VR256:$src1,
3901 (bc_v16i16 (memopv4i64 addr:$src2)))),
3902 (VPCMPGTWYrm VR256:$src1, addr:$src2)>;
3903 def : Pat<(v8i32 (X86pcmpgtd VR256:$src1, VR256:$src2)),
3904 (VPCMPGTDYrr VR256:$src1, VR256:$src2)>;
3905 def : Pat<(v8i32 (X86pcmpgtd VR256:$src1,
3906 (bc_v8i32 (memopv4i64 addr:$src2)))),
3907 (VPCMPGTDYrm VR256:$src1, addr:$src2)>;
3910 let Constraints = "$src1 = $dst" in {
3911 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b,
3912 VR128, memopv2i64, i128mem, 1>;
3913 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w,
3914 VR128, memopv2i64, i128mem, 1>;
3915 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d,
3916 VR128, memopv2i64, i128mem, 1>;
3917 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b,
3918 VR128, memopv2i64, i128mem>;
3919 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w,
3920 VR128, memopv2i64, i128mem>;
3921 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d,
3922 VR128, memopv2i64, i128mem>;
3923 } // Constraints = "$src1 = $dst"
3925 let Predicates = [HasSSE2] in {
3926 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3927 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
3928 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1,
3929 (bc_v16i8 (memopv2i64 addr:$src2)))),
3930 (PCMPEQBrm VR128:$src1, addr:$src2)>;
3931 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3932 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
3933 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1,
3934 (bc_v8i16 (memopv2i64 addr:$src2)))),
3935 (PCMPEQWrm VR128:$src1, addr:$src2)>;
3936 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3937 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
3938 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1,
3939 (bc_v4i32 (memopv2i64 addr:$src2)))),
3940 (PCMPEQDrm VR128:$src1, addr:$src2)>;
3942 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3943 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
3944 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1,
3945 (bc_v16i8 (memopv2i64 addr:$src2)))),
3946 (PCMPGTBrm VR128:$src1, addr:$src2)>;
3947 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3948 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
3949 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1,
3950 (bc_v8i16 (memopv2i64 addr:$src2)))),
3951 (PCMPGTWrm VR128:$src1, addr:$src2)>;
3952 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3953 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
3954 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1,
3955 (bc_v4i32 (memopv2i64 addr:$src2)))),
3956 (PCMPGTDrm VR128:$src1, addr:$src2)>;
3959 //===---------------------------------------------------------------------===//
3960 // SSE2 - Packed Integer Pack Instructions
3961 //===---------------------------------------------------------------------===//
3963 let Predicates = [HasAVX] in {
3964 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
3965 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3966 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
3967 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3968 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
3969 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3972 let Predicates = [HasAVX2] in {
3973 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
3974 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3975 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
3976 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3977 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
3978 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3981 let Constraints = "$src1 = $dst" in {
3982 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
3983 VR128, memopv2i64, i128mem>;
3984 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
3985 VR128, memopv2i64, i128mem>;
3986 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
3987 VR128, memopv2i64, i128mem>;
3988 } // Constraints = "$src1 = $dst"
3990 //===---------------------------------------------------------------------===//
3991 // SSE2 - Packed Integer Shuffle Instructions
3992 //===---------------------------------------------------------------------===//
3994 let ExeDomain = SSEPackedInt in {
3995 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
3997 def ri : Ii8<0x70, MRMSrcReg,
3998 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3999 !strconcat(OpcodeStr,
4000 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4001 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
4003 def mi : Ii8<0x70, MRMSrcMem,
4004 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4005 !strconcat(OpcodeStr,
4006 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4007 [(set VR128:$dst, (vt (pshuf_frag:$src2
4008 (bc_frag (memopv2i64 addr:$src1)),
4012 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
4014 def Yri : Ii8<0x70, MRMSrcReg,
4015 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4016 !strconcat(OpcodeStr,
4017 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4018 [(set VR256:$dst, (vt (pshuf_frag:$src2 VR256:$src1,
4020 def Ymi : Ii8<0x70, MRMSrcMem,
4021 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4022 !strconcat(OpcodeStr,
4023 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4024 [(set VR256:$dst, (vt (pshuf_frag:$src2
4025 (bc_frag (memopv4i64 addr:$src1)),
4028 } // ExeDomain = SSEPackedInt
4030 let Predicates = [HasAVX] in {
4031 let AddedComplexity = 5 in
4032 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
4035 // SSE2 with ImmT == Imm8 and XS prefix.
4036 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
4039 // SSE2 with ImmT == Imm8 and XD prefix.
4040 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
4043 let AddedComplexity = 5 in
4044 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
4045 (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4046 // Unary v4f32 shuffle with VPSHUF* in order to fold a load.
4047 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
4048 (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4050 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
4052 (VPSHUFDmi addr:$src1, imm:$imm)>;
4053 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
4055 (VPSHUFDmi addr:$src1, imm:$imm)>;
4056 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4057 (VPSHUFDri VR128:$src1, imm:$imm)>;
4058 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4059 (VPSHUFDri VR128:$src1, imm:$imm)>;
4060 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
4061 (VPSHUFHWri VR128:$src, imm:$imm)>;
4062 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
4064 (VPSHUFHWmi addr:$src, imm:$imm)>;
4065 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
4066 (VPSHUFLWri VR128:$src, imm:$imm)>;
4067 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
4069 (VPSHUFLWmi addr:$src, imm:$imm)>;
4072 let Predicates = [HasAVX2] in {
4073 let AddedComplexity = 5 in
4074 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, pshufd, bc_v8i32>, TB,
4077 // SSE2 with ImmT == Imm8 and XS prefix.
4078 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, pshufhw, bc_v16i16>, XS,
4081 // SSE2 with ImmT == Imm8 and XD prefix.
4082 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, pshuflw, bc_v16i16>, XD,
4086 let Predicates = [HasSSE2] in {
4087 let AddedComplexity = 5 in
4088 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
4090 // SSE2 with ImmT == Imm8 and XS prefix.
4091 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
4093 // SSE2 with ImmT == Imm8 and XD prefix.
4094 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
4096 let AddedComplexity = 5 in
4097 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
4098 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4099 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
4100 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
4101 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
4103 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
4105 (PSHUFDmi addr:$src1, imm:$imm)>;
4106 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
4108 (PSHUFDmi addr:$src1, imm:$imm)>;
4109 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4110 (PSHUFDri VR128:$src1, imm:$imm)>;
4111 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4112 (PSHUFDri VR128:$src1, imm:$imm)>;
4113 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
4114 (PSHUFHWri VR128:$src, imm:$imm)>;
4115 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
4117 (PSHUFHWmi addr:$src, imm:$imm)>;
4118 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
4119 (PSHUFLWri VR128:$src, imm:$imm)>;
4120 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
4122 (PSHUFLWmi addr:$src, imm:$imm)>;
4125 //===---------------------------------------------------------------------===//
4126 // SSE2 - Packed Integer Unpack Instructions
4127 //===---------------------------------------------------------------------===//
4129 let ExeDomain = SSEPackedInt in {
4130 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4131 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4132 def rr : PDI<opc, MRMSrcReg,
4133 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4135 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4136 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4137 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
4138 def rm : PDI<opc, MRMSrcMem,
4139 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4141 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4142 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4143 [(set VR128:$dst, (OpNode VR128:$src1,
4144 (bc_frag (memopv2i64
4148 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4149 SDNode OpNode, PatFrag bc_frag> {
4150 def Yrr : PDI<opc, MRMSrcReg,
4151 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4152 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4153 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4154 def Yrm : PDI<opc, MRMSrcMem,
4155 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4156 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4157 [(set VR256:$dst, (OpNode VR256:$src1,
4158 (bc_frag (memopv4i64 addr:$src2))))]>;
4161 let Predicates = [HasAVX] in {
4162 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4163 bc_v16i8, 0>, VEX_4V;
4164 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4165 bc_v8i16, 0>, VEX_4V;
4166 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4167 bc_v4i32, 0>, VEX_4V;
4168 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4169 bc_v2i64, 0>, VEX_4V;
4171 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4172 bc_v16i8, 0>, VEX_4V;
4173 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4174 bc_v8i16, 0>, VEX_4V;
4175 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4176 bc_v4i32, 0>, VEX_4V;
4177 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4178 bc_v2i64, 0>, VEX_4V;
4181 let Predicates = [HasAVX2] in {
4182 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4184 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4186 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4188 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4191 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4193 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4195 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4197 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4201 let Constraints = "$src1 = $dst" in {
4202 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4204 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4206 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4208 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4211 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4213 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4215 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4217 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4220 } // ExeDomain = SSEPackedInt
4222 // Patterns for using AVX1 instructions with integer vectors
4223 // Here to give AVX2 priority
4224 let Predicates = [HasAVX] in {
4225 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4226 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
4227 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
4228 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
4229 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4230 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
4231 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
4232 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
4234 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
4235 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
4236 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
4237 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
4238 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
4239 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
4240 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
4241 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
4244 // Splat v2f64 / v2i64
4245 let AddedComplexity = 10 in {
4246 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
4247 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
4248 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
4249 (VPUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasAVX]>;
4252 //===---------------------------------------------------------------------===//
4253 // SSE2 - Packed Integer Extract and Insert
4254 //===---------------------------------------------------------------------===//
4256 let ExeDomain = SSEPackedInt in {
4257 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4258 def rri : Ii8<0xC4, MRMSrcReg,
4259 (outs VR128:$dst), (ins VR128:$src1,
4260 GR32:$src2, i32i8imm:$src3),
4262 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4263 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4265 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
4266 def rmi : Ii8<0xC4, MRMSrcMem,
4267 (outs VR128:$dst), (ins VR128:$src1,
4268 i16mem:$src2, i32i8imm:$src3),
4270 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4271 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4273 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4278 let Predicates = [HasAVX] in
4279 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4280 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4281 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4282 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4283 imm:$src2))]>, TB, OpSize, VEX;
4284 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4285 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4286 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4287 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4291 let Predicates = [HasAVX] in {
4292 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4293 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4294 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4295 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4296 []>, TB, OpSize, VEX_4V;
4299 let Constraints = "$src1 = $dst" in
4300 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4302 } // ExeDomain = SSEPackedInt
4304 //===---------------------------------------------------------------------===//
4305 // SSE2 - Packed Mask Creation
4306 //===---------------------------------------------------------------------===//
4308 let ExeDomain = SSEPackedInt in {
4310 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4311 "pmovmskb\t{$src, $dst|$dst, $src}",
4312 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
4313 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4314 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4316 let Predicates = [HasAVX2] in {
4317 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4318 "pmovmskb\t{$src, $dst|$dst, $src}",
4319 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4320 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4321 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4324 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4325 "pmovmskb\t{$src, $dst|$dst, $src}",
4326 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
4328 } // ExeDomain = SSEPackedInt
4330 //===---------------------------------------------------------------------===//
4331 // SSE2 - Conditional Store
4332 //===---------------------------------------------------------------------===//
4334 let ExeDomain = SSEPackedInt in {
4337 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4338 (ins VR128:$src, VR128:$mask),
4339 "maskmovdqu\t{$mask, $src|$src, $mask}",
4340 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
4342 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4343 (ins VR128:$src, VR128:$mask),
4344 "maskmovdqu\t{$mask, $src|$src, $mask}",
4345 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
4348 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4349 "maskmovdqu\t{$mask, $src|$src, $mask}",
4350 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
4352 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4353 "maskmovdqu\t{$mask, $src|$src, $mask}",
4354 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
4356 } // ExeDomain = SSEPackedInt
4358 //===---------------------------------------------------------------------===//
4359 // SSE2 - Move Doubleword
4360 //===---------------------------------------------------------------------===//
4362 //===---------------------------------------------------------------------===//
4363 // Move Int Doubleword to Packed Double Int
4365 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4366 "movd\t{$src, $dst|$dst, $src}",
4368 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
4369 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4370 "movd\t{$src, $dst|$dst, $src}",
4372 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
4374 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4375 "mov{d|q}\t{$src, $dst|$dst, $src}",
4377 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
4378 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4379 "mov{d|q}\t{$src, $dst|$dst, $src}",
4380 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
4382 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4383 "movd\t{$src, $dst|$dst, $src}",
4385 (v4i32 (scalar_to_vector GR32:$src)))]>;
4386 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4387 "movd\t{$src, $dst|$dst, $src}",
4389 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
4390 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4391 "mov{d|q}\t{$src, $dst|$dst, $src}",
4393 (v2i64 (scalar_to_vector GR64:$src)))]>;
4394 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4395 "mov{d|q}\t{$src, $dst|$dst, $src}",
4396 [(set FR64:$dst, (bitconvert GR64:$src))]>;
4398 //===---------------------------------------------------------------------===//
4399 // Move Int Doubleword to Single Scalar
4401 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4402 "movd\t{$src, $dst|$dst, $src}",
4403 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
4405 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4406 "movd\t{$src, $dst|$dst, $src}",
4407 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4409 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4410 "movd\t{$src, $dst|$dst, $src}",
4411 [(set FR32:$dst, (bitconvert GR32:$src))]>;
4413 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4414 "movd\t{$src, $dst|$dst, $src}",
4415 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
4417 //===---------------------------------------------------------------------===//
4418 // Move Packed Doubleword Int to Packed Double Int
4420 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4421 "movd\t{$src, $dst|$dst, $src}",
4422 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4424 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4425 (ins i32mem:$dst, VR128:$src),
4426 "movd\t{$src, $dst|$dst, $src}",
4427 [(store (i32 (vector_extract (v4i32 VR128:$src),
4428 (iPTR 0))), addr:$dst)]>, VEX;
4429 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4430 "movd\t{$src, $dst|$dst, $src}",
4431 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4433 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4434 "movd\t{$src, $dst|$dst, $src}",
4435 [(store (i32 (vector_extract (v4i32 VR128:$src),
4436 (iPTR 0))), addr:$dst)]>;
4438 //===---------------------------------------------------------------------===//
4439 // Move Packed Doubleword Int first element to Doubleword Int
4441 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4442 "mov{d|q}\t{$src, $dst|$dst, $src}",
4443 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4445 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4447 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4448 "mov{d|q}\t{$src, $dst|$dst, $src}",
4449 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4452 //===---------------------------------------------------------------------===//
4453 // Bitcast FR64 <-> GR64
4455 let Predicates = [HasAVX] in
4456 def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4457 "vmovq\t{$src, $dst|$dst, $src}",
4458 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4460 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4461 "mov{d|q}\t{$src, $dst|$dst, $src}",
4462 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4463 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4464 "movq\t{$src, $dst|$dst, $src}",
4465 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4467 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4468 "movq\t{$src, $dst|$dst, $src}",
4469 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
4470 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4471 "mov{d|q}\t{$src, $dst|$dst, $src}",
4472 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4473 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4474 "movq\t{$src, $dst|$dst, $src}",
4475 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4477 //===---------------------------------------------------------------------===//
4478 // Move Scalar Single to Double Int
4480 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4481 "movd\t{$src, $dst|$dst, $src}",
4482 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
4483 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4484 "movd\t{$src, $dst|$dst, $src}",
4485 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
4486 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4487 "movd\t{$src, $dst|$dst, $src}",
4488 [(set GR32:$dst, (bitconvert FR32:$src))]>;
4489 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4490 "movd\t{$src, $dst|$dst, $src}",
4491 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
4493 //===---------------------------------------------------------------------===//
4494 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4496 let AddedComplexity = 15 in {
4497 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4498 "movd\t{$src, $dst|$dst, $src}",
4499 [(set VR128:$dst, (v4i32 (X86vzmovl
4500 (v4i32 (scalar_to_vector GR32:$src)))))]>,
4502 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4503 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4504 [(set VR128:$dst, (v2i64 (X86vzmovl
4505 (v2i64 (scalar_to_vector GR64:$src)))))]>,
4508 let AddedComplexity = 15 in {
4509 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4510 "movd\t{$src, $dst|$dst, $src}",
4511 [(set VR128:$dst, (v4i32 (X86vzmovl
4512 (v4i32 (scalar_to_vector GR32:$src)))))]>;
4513 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4514 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4515 [(set VR128:$dst, (v2i64 (X86vzmovl
4516 (v2i64 (scalar_to_vector GR64:$src)))))]>;
4519 let AddedComplexity = 20 in {
4520 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4521 "movd\t{$src, $dst|$dst, $src}",
4523 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4524 (loadi32 addr:$src))))))]>,
4526 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4527 "movd\t{$src, $dst|$dst, $src}",
4529 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4530 (loadi32 addr:$src))))))]>;
4533 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4534 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4535 (MOVZDI2PDIrm addr:$src)>;
4536 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4537 (MOVZDI2PDIrm addr:$src)>;
4538 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4539 (MOVZDI2PDIrm addr:$src)>;
4542 let Predicates = [HasAVX] in {
4543 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4544 let AddedComplexity = 20 in {
4545 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4546 (VMOVZDI2PDIrm addr:$src)>;
4547 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4548 (VMOVZDI2PDIrm addr:$src)>;
4549 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4550 (VMOVZDI2PDIrm addr:$src)>;
4552 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4553 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4554 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4555 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4556 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4557 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4558 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4561 // These are the correct encodings of the instructions so that we know how to
4562 // read correct assembly, even though we continue to emit the wrong ones for
4563 // compatibility with Darwin's buggy assembler.
4564 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4565 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4566 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4567 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4568 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4569 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4570 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4571 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4572 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4573 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4574 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4575 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4577 //===---------------------------------------------------------------------===//
4578 // SSE2 - Move Quadword
4579 //===---------------------------------------------------------------------===//
4581 //===---------------------------------------------------------------------===//
4582 // Move Quadword Int to Packed Quadword Int
4584 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4585 "vmovq\t{$src, $dst|$dst, $src}",
4587 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4588 VEX, Requires<[HasAVX]>;
4589 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4590 "movq\t{$src, $dst|$dst, $src}",
4592 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4593 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4595 //===---------------------------------------------------------------------===//
4596 // Move Packed Quadword Int to Quadword Int
4598 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4599 "movq\t{$src, $dst|$dst, $src}",
4600 [(store (i64 (vector_extract (v2i64 VR128:$src),
4601 (iPTR 0))), addr:$dst)]>, VEX;
4602 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4603 "movq\t{$src, $dst|$dst, $src}",
4604 [(store (i64 (vector_extract (v2i64 VR128:$src),
4605 (iPTR 0))), addr:$dst)]>;
4607 //===---------------------------------------------------------------------===//
4608 // Store / copy lower 64-bits of a XMM register.
4610 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4611 "movq\t{$src, $dst|$dst, $src}",
4612 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4613 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4614 "movq\t{$src, $dst|$dst, $src}",
4615 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
4617 let AddedComplexity = 20 in
4618 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4619 "vmovq\t{$src, $dst|$dst, $src}",
4621 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4622 (loadi64 addr:$src))))))]>,
4623 XS, VEX, Requires<[HasAVX]>;
4625 let AddedComplexity = 20 in
4626 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4627 "movq\t{$src, $dst|$dst, $src}",
4629 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4630 (loadi64 addr:$src))))))]>,
4631 XS, Requires<[HasSSE2]>;
4633 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4634 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4635 (MOVZQI2PQIrm addr:$src)>;
4636 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4637 (MOVZQI2PQIrm addr:$src)>;
4638 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4641 let Predicates = [HasAVX], AddedComplexity = 20 in {
4642 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4643 (VMOVZQI2PQIrm addr:$src)>;
4644 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4645 (VMOVZQI2PQIrm addr:$src)>;
4646 def : Pat<(v2i64 (X86vzload addr:$src)),
4647 (VMOVZQI2PQIrm addr:$src)>;
4650 //===---------------------------------------------------------------------===//
4651 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4652 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4654 let AddedComplexity = 15 in
4655 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4656 "vmovq\t{$src, $dst|$dst, $src}",
4657 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4658 XS, VEX, Requires<[HasAVX]>;
4659 let AddedComplexity = 15 in
4660 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4661 "movq\t{$src, $dst|$dst, $src}",
4662 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4663 XS, Requires<[HasSSE2]>;
4665 let AddedComplexity = 20 in
4666 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4667 "vmovq\t{$src, $dst|$dst, $src}",
4668 [(set VR128:$dst, (v2i64 (X86vzmovl
4669 (loadv2i64 addr:$src))))]>,
4670 XS, VEX, Requires<[HasAVX]>;
4671 let AddedComplexity = 20 in {
4672 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4673 "movq\t{$src, $dst|$dst, $src}",
4674 [(set VR128:$dst, (v2i64 (X86vzmovl
4675 (loadv2i64 addr:$src))))]>,
4676 XS, Requires<[HasSSE2]>;
4679 let AddedComplexity = 20 in {
4680 let Predicates = [HasSSE2] in {
4681 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4682 (MOVZPQILo2PQIrm addr:$src)>;
4683 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4684 (MOVZPQILo2PQIrr VR128:$src)>;
4686 let Predicates = [HasAVX] in {
4687 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4688 (VMOVZPQILo2PQIrm addr:$src)>;
4689 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4690 (VMOVZPQILo2PQIrr VR128:$src)>;
4694 // Instructions to match in the assembler
4695 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4696 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4697 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4698 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4699 // Recognize "movd" with GR64 destination, but encode as a "movq"
4700 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4701 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4703 // Instructions for the disassembler
4704 // xr = XMM register
4707 let Predicates = [HasAVX] in
4708 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4709 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4710 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4711 "movq\t{$src, $dst|$dst, $src}", []>, XS;
4713 //===---------------------------------------------------------------------===//
4714 // SSE3 - Conversion Instructions
4715 //===---------------------------------------------------------------------===//
4717 // Convert Packed Double FP to Packed DW Integers
4718 let Predicates = [HasAVX] in {
4719 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4720 // register, but the same isn't true when using memory operands instead.
4721 // Provide other assembly rr and rm forms to address this explicitly.
4722 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4723 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4724 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4725 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4728 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4729 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4730 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4731 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4734 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4735 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4736 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4737 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4740 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4741 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4742 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4743 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4745 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4746 (VCVTPD2DQYrr VR256:$src)>;
4747 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4748 (VCVTPD2DQYrm addr:$src)>;
4750 // Convert Packed DW Integers to Packed Double FP
4751 let Predicates = [HasAVX] in {
4752 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4753 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4754 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4755 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4756 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4757 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4758 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4759 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4762 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4763 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4764 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4765 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4767 // AVX 256-bit register conversion intrinsics
4768 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4769 (VCVTDQ2PDYrr VR128:$src)>;
4770 def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
4771 (VCVTDQ2PDYrm addr:$src)>;
4773 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4774 (VCVTPD2DQYrr VR256:$src)>;
4775 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4776 (VCVTPD2DQYrm addr:$src)>;
4778 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4779 (VCVTDQ2PDYrr VR128:$src)>;
4780 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
4781 (VCVTDQ2PDYrm addr:$src)>;
4783 //===---------------------------------------------------------------------===//
4784 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4785 //===---------------------------------------------------------------------===//
4786 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4787 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4788 X86MemOperand x86memop> {
4789 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4790 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4791 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
4792 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4793 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4794 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
4797 let Predicates = [HasAVX] in {
4798 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4799 v4f32, VR128, memopv4f32, f128mem>, VEX;
4800 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4801 v4f32, VR128, memopv4f32, f128mem>, VEX;
4802 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4803 v8f32, VR256, memopv8f32, f256mem>, VEX;
4804 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4805 v8f32, VR256, memopv8f32, f256mem>, VEX;
4807 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4808 memopv4f32, f128mem>;
4809 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4810 memopv4f32, f128mem>;
4812 let Predicates = [HasSSE3] in {
4813 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4814 (MOVSHDUPrr VR128:$src)>;
4815 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4816 (MOVSHDUPrm addr:$src)>;
4817 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4818 (MOVSLDUPrr VR128:$src)>;
4819 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4820 (MOVSLDUPrm addr:$src)>;
4823 let Predicates = [HasAVX] in {
4824 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4825 (VMOVSHDUPrr VR128:$src)>;
4826 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4827 (VMOVSHDUPrm addr:$src)>;
4828 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4829 (VMOVSLDUPrr VR128:$src)>;
4830 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4831 (VMOVSLDUPrm addr:$src)>;
4832 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4833 (VMOVSHDUPYrr VR256:$src)>;
4834 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4835 (VMOVSHDUPYrm addr:$src)>;
4836 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4837 (VMOVSLDUPYrr VR256:$src)>;
4838 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4839 (VMOVSLDUPYrm addr:$src)>;
4842 //===---------------------------------------------------------------------===//
4843 // SSE3 - Replicate Double FP - MOVDDUP
4844 //===---------------------------------------------------------------------===//
4846 multiclass sse3_replicate_dfp<string OpcodeStr> {
4847 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4848 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4849 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
4850 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4851 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4853 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
4857 // FIXME: Merge with above classe when there're patterns for the ymm version
4858 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4859 let Predicates = [HasAVX] in {
4860 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4861 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4863 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4864 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4869 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4870 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4871 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4873 let Predicates = [HasSSE3] in {
4874 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4876 (MOVDDUPrm addr:$src)>;
4877 let AddedComplexity = 5 in {
4878 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4879 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4880 (MOVDDUPrm addr:$src)>;
4881 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4882 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4883 (MOVDDUPrm addr:$src)>;
4885 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4886 (MOVDDUPrm addr:$src)>;
4887 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4888 (MOVDDUPrm addr:$src)>;
4889 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4890 (MOVDDUPrm addr:$src)>;
4891 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4892 (MOVDDUPrm addr:$src)>;
4893 def : Pat<(X86Movddup (bc_v2f64
4894 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4895 (MOVDDUPrm addr:$src)>;
4898 let Predicates = [HasAVX] in {
4899 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4901 (VMOVDDUPrm addr:$src)>;
4902 let AddedComplexity = 5 in {
4903 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4904 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4905 (VMOVDDUPrm addr:$src)>;
4906 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4907 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4908 (VMOVDDUPrm addr:$src)>;
4910 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4911 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4912 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4913 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4914 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4915 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4916 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4917 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4918 def : Pat<(X86Movddup (bc_v2f64
4919 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4920 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4923 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4924 (VMOVDDUPYrm addr:$src)>;
4925 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4926 (VMOVDDUPYrm addr:$src)>;
4927 def : Pat<(X86Movddup (v4f64 (scalar_to_vector (loadf64 addr:$src)))),
4928 (VMOVDDUPYrm addr:$src)>;
4929 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4930 (VMOVDDUPYrm addr:$src)>;
4931 def : Pat<(X86Movddup (v4f64 VR256:$src)),
4932 (VMOVDDUPYrr VR256:$src)>;
4933 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4934 (VMOVDDUPYrr VR256:$src)>;
4937 //===---------------------------------------------------------------------===//
4938 // SSE3 - Move Unaligned Integer
4939 //===---------------------------------------------------------------------===//
4941 let Predicates = [HasAVX] in {
4942 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4943 "vlddqu\t{$src, $dst|$dst, $src}",
4944 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4945 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4946 "vlddqu\t{$src, $dst|$dst, $src}",
4947 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4949 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4950 "lddqu\t{$src, $dst|$dst, $src}",
4951 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
4953 //===---------------------------------------------------------------------===//
4954 // SSE3 - Arithmetic
4955 //===---------------------------------------------------------------------===//
4957 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4958 X86MemOperand x86memop, bit Is2Addr = 1> {
4959 def rr : I<0xD0, MRMSrcReg,
4960 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4962 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4963 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4964 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
4965 def rm : I<0xD0, MRMSrcMem,
4966 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4968 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4969 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4970 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
4973 let Predicates = [HasAVX] in {
4974 let ExeDomain = SSEPackedSingle in {
4975 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4976 f128mem, 0>, TB, XD, VEX_4V;
4977 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4978 f256mem, 0>, TB, XD, VEX_4V;
4980 let ExeDomain = SSEPackedDouble in {
4981 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4982 f128mem, 0>, TB, OpSize, VEX_4V;
4983 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4984 f256mem, 0>, TB, OpSize, VEX_4V;
4987 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
4988 let ExeDomain = SSEPackedSingle in
4989 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4991 let ExeDomain = SSEPackedDouble in
4992 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4993 f128mem>, TB, OpSize;
4996 //===---------------------------------------------------------------------===//
4997 // SSE3 Instructions
4998 //===---------------------------------------------------------------------===//
5001 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5002 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5003 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5005 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5006 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5007 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
5009 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5011 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5012 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5013 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
5015 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5016 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5017 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5019 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5020 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5021 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
5023 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5025 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5026 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5027 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
5030 let Predicates = [HasAVX] in {
5031 let ExeDomain = SSEPackedSingle in {
5032 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5033 X86fhadd, 0>, VEX_4V;
5034 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5035 X86fhsub, 0>, VEX_4V;
5036 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5037 X86fhadd, 0>, VEX_4V;
5038 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5039 X86fhsub, 0>, VEX_4V;
5041 let ExeDomain = SSEPackedDouble in {
5042 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5043 X86fhadd, 0>, VEX_4V;
5044 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5045 X86fhsub, 0>, VEX_4V;
5046 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5047 X86fhadd, 0>, VEX_4V;
5048 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5049 X86fhsub, 0>, VEX_4V;
5053 let Constraints = "$src1 = $dst" in {
5054 let ExeDomain = SSEPackedSingle in {
5055 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5056 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5058 let ExeDomain = SSEPackedDouble in {
5059 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5060 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5064 //===---------------------------------------------------------------------===//
5065 // SSSE3 - Packed Absolute Instructions
5066 //===---------------------------------------------------------------------===//
5069 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5070 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5071 Intrinsic IntId128> {
5072 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5074 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5075 [(set VR128:$dst, (IntId128 VR128:$src))]>,
5078 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5080 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5083 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
5086 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5087 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5088 Intrinsic IntId256> {
5089 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5091 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5092 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5095 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5097 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5100 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5103 let Predicates = [HasAVX] in {
5104 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5105 int_x86_ssse3_pabs_b_128>, VEX;
5106 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5107 int_x86_ssse3_pabs_w_128>, VEX;
5108 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5109 int_x86_ssse3_pabs_d_128>, VEX;
5112 let Predicates = [HasAVX2] in {
5113 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5114 int_x86_avx2_pabs_b>, VEX;
5115 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5116 int_x86_avx2_pabs_w>, VEX;
5117 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5118 int_x86_avx2_pabs_d>, VEX;
5121 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5122 int_x86_ssse3_pabs_b_128>;
5123 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5124 int_x86_ssse3_pabs_w_128>;
5125 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5126 int_x86_ssse3_pabs_d_128>;
5128 //===---------------------------------------------------------------------===//
5129 // SSSE3 - Packed Binary Operator Instructions
5130 //===---------------------------------------------------------------------===//
5132 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5133 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5134 Intrinsic IntId128, bit Is2Addr = 1> {
5135 let isCommutable = 1 in
5136 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5137 (ins VR128:$src1, VR128:$src2),
5139 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5140 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5141 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5143 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5144 (ins VR128:$src1, i128mem:$src2),
5146 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5147 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5149 (IntId128 VR128:$src1,
5150 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5153 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5154 Intrinsic IntId256> {
5155 let isCommutable = 1 in
5156 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5157 (ins VR256:$src1, VR256:$src2),
5158 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5159 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5161 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5162 (ins VR256:$src1, i256mem:$src2),
5163 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5165 (IntId256 VR256:$src1,
5166 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5169 let ImmT = NoImm, Predicates = [HasAVX] in {
5170 let isCommutable = 0 in {
5171 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw",
5172 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
5173 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd",
5174 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
5175 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5176 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
5177 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw",
5178 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
5179 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd",
5180 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
5181 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5182 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
5183 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5184 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
5185 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb",
5186 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
5187 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb",
5188 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
5189 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw",
5190 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
5191 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd",
5192 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
5194 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5195 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
5198 let ImmT = NoImm, Predicates = [HasAVX2] in {
5199 let isCommutable = 0 in {
5200 defm VPHADDW : SS3I_binop_rm_int_y<0x01, "vphaddw",
5201 int_x86_avx2_phadd_w>, VEX_4V;
5202 defm VPHADDD : SS3I_binop_rm_int_y<0x02, "vphaddd",
5203 int_x86_avx2_phadd_d>, VEX_4V;
5204 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5205 int_x86_avx2_phadd_sw>, VEX_4V;
5206 defm VPHSUBW : SS3I_binop_rm_int_y<0x05, "vphsubw",
5207 int_x86_avx2_phsub_w>, VEX_4V;
5208 defm VPHSUBD : SS3I_binop_rm_int_y<0x06, "vphsubd",
5209 int_x86_avx2_phsub_d>, VEX_4V;
5210 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5211 int_x86_avx2_phsub_sw>, VEX_4V;
5212 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5213 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5214 defm VPSHUFB : SS3I_binop_rm_int_y<0x00, "vpshufb",
5215 int_x86_avx2_pshuf_b>, VEX_4V;
5216 defm VPSIGNB : SS3I_binop_rm_int_y<0x08, "vpsignb",
5217 int_x86_avx2_psign_b>, VEX_4V;
5218 defm VPSIGNW : SS3I_binop_rm_int_y<0x09, "vpsignw",
5219 int_x86_avx2_psign_w>, VEX_4V;
5220 defm VPSIGND : SS3I_binop_rm_int_y<0x0A, "vpsignd",
5221 int_x86_avx2_psign_d>, VEX_4V;
5223 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5224 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5227 // None of these have i8 immediate fields.
5228 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5229 let isCommutable = 0 in {
5230 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw",
5231 int_x86_ssse3_phadd_w_128>;
5232 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd",
5233 int_x86_ssse3_phadd_d_128>;
5234 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5235 int_x86_ssse3_phadd_sw_128>;
5236 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw",
5237 int_x86_ssse3_phsub_w_128>;
5238 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd",
5239 int_x86_ssse3_phsub_d_128>;
5240 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5241 int_x86_ssse3_phsub_sw_128>;
5242 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5243 int_x86_ssse3_pmadd_ub_sw_128>;
5244 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb",
5245 int_x86_ssse3_pshuf_b_128>;
5246 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb",
5247 int_x86_ssse3_psign_b_128>;
5248 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw",
5249 int_x86_ssse3_psign_w_128>;
5250 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd",
5251 int_x86_ssse3_psign_d_128>;
5253 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5254 int_x86_ssse3_pmul_hr_sw_128>;
5257 let Predicates = [HasSSSE3] in {
5258 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
5259 (PSHUFBrr128 VR128:$src, VR128:$mask)>;
5260 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
5261 (PSHUFBrm128 VR128:$src, addr:$mask)>;
5263 def : Pat<(v16i8 (X86psign VR128:$src1, VR128:$src2)),
5264 (PSIGNBrr128 VR128:$src1, VR128:$src2)>;
5265 def : Pat<(v8i16 (X86psign VR128:$src1, VR128:$src2)),
5266 (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
5267 def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
5268 (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
5270 def : Pat<(v8i16 (X86hadd VR128:$src1, VR128:$src2)),
5271 (PHADDWrr128 VR128:$src1, VR128:$src2)>;
5272 def : Pat<(v4i32 (X86hadd VR128:$src1, VR128:$src2)),
5273 (PHADDDrr128 VR128:$src1, VR128:$src2)>;
5274 def : Pat<(v8i16 (X86hsub VR128:$src1, VR128:$src2)),
5275 (PHSUBWrr128 VR128:$src1, VR128:$src2)>;
5276 def : Pat<(v4i32 (X86hsub VR128:$src1, VR128:$src2)),
5277 (PHSUBDrr128 VR128:$src1, VR128:$src2)>;
5280 let Predicates = [HasAVX] in {
5281 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
5282 (VPSHUFBrr128 VR128:$src, VR128:$mask)>;
5283 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
5284 (VPSHUFBrm128 VR128:$src, addr:$mask)>;
5286 def : Pat<(v16i8 (X86psign VR128:$src1, VR128:$src2)),
5287 (VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
5288 def : Pat<(v8i16 (X86psign VR128:$src1, VR128:$src2)),
5289 (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
5290 def : Pat<(v4i32 (X86psign VR128:$src1, VR128:$src2)),
5291 (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
5293 def : Pat<(v8i16 (X86hadd VR128:$src1, VR128:$src2)),
5294 (VPHADDWrr128 VR128:$src1, VR128:$src2)>;
5295 def : Pat<(v4i32 (X86hadd VR128:$src1, VR128:$src2)),
5296 (VPHADDDrr128 VR128:$src1, VR128:$src2)>;
5297 def : Pat<(v8i16 (X86hsub VR128:$src1, VR128:$src2)),
5298 (VPHSUBWrr128 VR128:$src1, VR128:$src2)>;
5299 def : Pat<(v4i32 (X86hsub VR128:$src1, VR128:$src2)),
5300 (VPHSUBDrr128 VR128:$src1, VR128:$src2)>;
5303 let Predicates = [HasAVX2] in {
5304 def : Pat<(v32i8 (X86psign VR256:$src1, VR256:$src2)),
5305 (VPSIGNBrr256 VR256:$src1, VR256:$src2)>;
5306 def : Pat<(v16i16 (X86psign VR256:$src1, VR256:$src2)),
5307 (VPSIGNWrr256 VR256:$src1, VR256:$src2)>;
5308 def : Pat<(v8i32 (X86psign VR256:$src1, VR256:$src2)),
5309 (VPSIGNDrr256 VR256:$src1, VR256:$src2)>;
5311 def : Pat<(v16i16 (X86hadd VR256:$src1, VR256:$src2)),
5312 (VPHADDWrr256 VR256:$src1, VR256:$src2)>;
5313 def : Pat<(v8i32 (X86hadd VR256:$src1, VR256:$src2)),
5314 (VPHADDDrr256 VR256:$src1, VR256:$src2)>;
5315 def : Pat<(v16i16 (X86hsub VR256:$src1, VR256:$src2)),
5316 (VPHSUBWrr256 VR256:$src1, VR256:$src2)>;
5317 def : Pat<(v8i32 (X86hsub VR256:$src1, VR256:$src2)),
5318 (VPHSUBDrr256 VR256:$src1, VR256:$src2)>;
5321 //===---------------------------------------------------------------------===//
5322 // SSSE3 - Packed Align Instruction Patterns
5323 //===---------------------------------------------------------------------===//
5325 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5326 let neverHasSideEffects = 1 in {
5327 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5328 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5330 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5332 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5335 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5336 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5338 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5340 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5345 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5346 let neverHasSideEffects = 1 in {
5347 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5348 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5350 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5353 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5354 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5356 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5361 let Predicates = [HasAVX] in
5362 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5363 let Predicates = [HasAVX2] in
5364 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5365 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5366 defm PALIGN : ssse3_palign<"palignr">;
5368 let Predicates = [HasSSSE3] in {
5369 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5370 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5371 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5372 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5373 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5374 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5375 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5376 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5379 let Predicates = [HasAVX] in {
5380 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5381 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5382 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5383 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5384 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5385 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5386 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5387 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5390 //===---------------------------------------------------------------------===//
5391 // SSSE3 - Thread synchronization
5392 //===---------------------------------------------------------------------===//
5394 let usesCustomInserter = 1 in {
5395 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5396 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
5397 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5398 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
5401 let Uses = [EAX, ECX, EDX] in
5402 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
5403 Requires<[HasSSE3]>;
5404 let Uses = [ECX, EAX] in
5405 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
5406 Requires<[HasSSE3]>;
5408 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5409 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5411 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5412 Requires<[In32BitMode]>;
5413 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5414 Requires<[In64BitMode]>;
5416 //===----------------------------------------------------------------------===//
5417 // SSE4.1 - Packed Move with Sign/Zero Extend
5418 //===----------------------------------------------------------------------===//
5420 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5421 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5422 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5423 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5425 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5426 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5428 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5432 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5434 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5435 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5436 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5438 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5439 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5440 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5443 let Predicates = [HasAVX] in {
5444 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5446 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5448 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5450 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5452 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5454 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5458 let Predicates = [HasAVX2] in {
5459 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5460 int_x86_avx2_pmovsxbw>, VEX;
5461 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5462 int_x86_avx2_pmovsxwd>, VEX;
5463 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5464 int_x86_avx2_pmovsxdq>, VEX;
5465 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5466 int_x86_avx2_pmovzxbw>, VEX;
5467 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5468 int_x86_avx2_pmovzxwd>, VEX;
5469 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5470 int_x86_avx2_pmovzxdq>, VEX;
5473 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5474 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5475 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5476 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5477 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5478 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5480 let Predicates = [HasSSE41] in {
5481 // Common patterns involving scalar load.
5482 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5483 (PMOVSXBWrm addr:$src)>;
5484 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5485 (PMOVSXBWrm addr:$src)>;
5487 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5488 (PMOVSXWDrm addr:$src)>;
5489 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5490 (PMOVSXWDrm addr:$src)>;
5492 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5493 (PMOVSXDQrm addr:$src)>;
5494 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5495 (PMOVSXDQrm addr:$src)>;
5497 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5498 (PMOVZXBWrm addr:$src)>;
5499 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5500 (PMOVZXBWrm addr:$src)>;
5502 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5503 (PMOVZXWDrm addr:$src)>;
5504 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5505 (PMOVZXWDrm addr:$src)>;
5507 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5508 (PMOVZXDQrm addr:$src)>;
5509 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5510 (PMOVZXDQrm addr:$src)>;
5513 let Predicates = [HasAVX] in {
5514 // Common patterns involving scalar load.
5515 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5516 (VPMOVSXBWrm addr:$src)>;
5517 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5518 (VPMOVSXBWrm addr:$src)>;
5520 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5521 (VPMOVSXWDrm addr:$src)>;
5522 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5523 (VPMOVSXWDrm addr:$src)>;
5525 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5526 (VPMOVSXDQrm addr:$src)>;
5527 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5528 (VPMOVSXDQrm addr:$src)>;
5530 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5531 (VPMOVZXBWrm addr:$src)>;
5532 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5533 (VPMOVZXBWrm addr:$src)>;
5535 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5536 (VPMOVZXWDrm addr:$src)>;
5537 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5538 (VPMOVZXWDrm addr:$src)>;
5540 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5541 (VPMOVZXDQrm addr:$src)>;
5542 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5543 (VPMOVZXDQrm addr:$src)>;
5547 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5548 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5549 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5550 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5552 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5553 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5555 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5559 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5561 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5562 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5563 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5565 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5566 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5568 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5572 let Predicates = [HasAVX] in {
5573 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5575 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5577 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5579 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5583 let Predicates = [HasAVX2] in {
5584 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5585 int_x86_avx2_pmovsxbd>, VEX;
5586 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5587 int_x86_avx2_pmovsxwq>, VEX;
5588 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5589 int_x86_avx2_pmovzxbd>, VEX;
5590 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5591 int_x86_avx2_pmovzxwq>, VEX;
5594 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5595 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5596 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5597 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5599 let Predicates = [HasSSE41] in {
5600 // Common patterns involving scalar load
5601 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5602 (PMOVSXBDrm addr:$src)>;
5603 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5604 (PMOVSXWQrm addr:$src)>;
5606 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5607 (PMOVZXBDrm addr:$src)>;
5608 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5609 (PMOVZXWQrm addr:$src)>;
5612 let Predicates = [HasAVX] in {
5613 // Common patterns involving scalar load
5614 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5615 (VPMOVSXBDrm addr:$src)>;
5616 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5617 (VPMOVSXWQrm addr:$src)>;
5619 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5620 (VPMOVZXBDrm addr:$src)>;
5621 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5622 (VPMOVZXWQrm addr:$src)>;
5625 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5626 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5627 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5628 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5630 // Expecting a i16 load any extended to i32 value.
5631 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5632 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5633 [(set VR128:$dst, (IntId (bitconvert
5634 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5638 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5640 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5641 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5642 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5644 // Expecting a i16 load any extended to i32 value.
5645 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5646 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5647 [(set VR256:$dst, (IntId (bitconvert
5648 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5652 let Predicates = [HasAVX] in {
5653 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5655 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5658 let Predicates = [HasAVX2] in {
5659 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5660 int_x86_avx2_pmovsxbq>, VEX;
5661 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5662 int_x86_avx2_pmovzxbq>, VEX;
5664 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5665 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5667 let Predicates = [HasSSE41] in {
5668 // Common patterns involving scalar load
5669 def : Pat<(int_x86_sse41_pmovsxbq
5670 (bitconvert (v4i32 (X86vzmovl
5671 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5672 (PMOVSXBQrm addr:$src)>;
5674 def : Pat<(int_x86_sse41_pmovzxbq
5675 (bitconvert (v4i32 (X86vzmovl
5676 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5677 (PMOVZXBQrm addr:$src)>;
5680 let Predicates = [HasAVX] in {
5681 // Common patterns involving scalar load
5682 def : Pat<(int_x86_sse41_pmovsxbq
5683 (bitconvert (v4i32 (X86vzmovl
5684 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5685 (VPMOVSXBQrm addr:$src)>;
5687 def : Pat<(int_x86_sse41_pmovzxbq
5688 (bitconvert (v4i32 (X86vzmovl
5689 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5690 (VPMOVZXBQrm addr:$src)>;
5693 //===----------------------------------------------------------------------===//
5694 // SSE4.1 - Extract Instructions
5695 //===----------------------------------------------------------------------===//
5697 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5698 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5699 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5700 (ins VR128:$src1, i32i8imm:$src2),
5701 !strconcat(OpcodeStr,
5702 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5703 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5705 let neverHasSideEffects = 1, mayStore = 1 in
5706 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5707 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5708 !strconcat(OpcodeStr,
5709 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5712 // There's an AssertZext in the way of writing the store pattern
5713 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5716 let Predicates = [HasAVX] in {
5717 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5718 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5719 (ins VR128:$src1, i32i8imm:$src2),
5720 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5723 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5726 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5727 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5728 let neverHasSideEffects = 1, mayStore = 1 in
5729 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5730 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5731 !strconcat(OpcodeStr,
5732 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5735 // There's an AssertZext in the way of writing the store pattern
5736 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5739 let Predicates = [HasAVX] in
5740 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5742 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5745 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5746 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5747 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5748 (ins VR128:$src1, i32i8imm:$src2),
5749 !strconcat(OpcodeStr,
5750 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5752 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5753 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5754 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5755 !strconcat(OpcodeStr,
5756 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5757 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5758 addr:$dst)]>, OpSize;
5761 let Predicates = [HasAVX] in
5762 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5764 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5766 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5767 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5768 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5769 (ins VR128:$src1, i32i8imm:$src2),
5770 !strconcat(OpcodeStr,
5771 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5773 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5774 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5775 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5776 !strconcat(OpcodeStr,
5777 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5778 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5779 addr:$dst)]>, OpSize, REX_W;
5782 let Predicates = [HasAVX] in
5783 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5785 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5787 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5789 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5790 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5791 (ins VR128:$src1, i32i8imm:$src2),
5792 !strconcat(OpcodeStr,
5793 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5795 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5797 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5798 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5799 !strconcat(OpcodeStr,
5800 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5801 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5802 addr:$dst)]>, OpSize;
5805 let ExeDomain = SSEPackedSingle in {
5806 let Predicates = [HasAVX] in {
5807 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5808 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5809 (ins VR128:$src1, i32i8imm:$src2),
5810 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5813 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5816 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5817 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5820 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5821 Requires<[HasSSE41]>;
5822 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5825 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5828 //===----------------------------------------------------------------------===//
5829 // SSE4.1 - Insert Instructions
5830 //===----------------------------------------------------------------------===//
5832 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5833 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5834 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5836 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5838 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5840 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5841 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5842 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5844 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5846 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5848 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5849 imm:$src3))]>, OpSize;
5852 let Predicates = [HasAVX] in
5853 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5854 let Constraints = "$src1 = $dst" in
5855 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5857 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5858 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5859 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5861 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5863 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5865 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5867 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5868 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5870 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5872 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5874 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5875 imm:$src3)))]>, OpSize;
5878 let Predicates = [HasAVX] in
5879 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5880 let Constraints = "$src1 = $dst" in
5881 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5883 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5884 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5885 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5887 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5889 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5891 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5893 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5894 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5896 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5898 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5900 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5901 imm:$src3)))]>, OpSize;
5904 let Predicates = [HasAVX] in
5905 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5906 let Constraints = "$src1 = $dst" in
5907 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5909 // insertps has a few different modes, there's the first two here below which
5910 // are optimized inserts that won't zero arbitrary elements in the destination
5911 // vector. The next one matches the intrinsic and could zero arbitrary elements
5912 // in the target vector.
5913 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5914 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5915 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5917 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5919 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5921 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5923 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5924 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5926 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5928 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5930 (X86insrtps VR128:$src1,
5931 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
5932 imm:$src3))]>, OpSize;
5935 let ExeDomain = SSEPackedSingle in {
5936 let Constraints = "$src1 = $dst" in
5937 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
5938 let Predicates = [HasAVX] in
5939 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
5942 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5943 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5945 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5946 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5947 Requires<[HasSSE41]>;
5949 //===----------------------------------------------------------------------===//
5950 // SSE4.1 - Round Instructions
5951 //===----------------------------------------------------------------------===//
5953 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
5954 X86MemOperand x86memop, RegisterClass RC,
5955 PatFrag mem_frag32, PatFrag mem_frag64,
5956 Intrinsic V4F32Int, Intrinsic V2F64Int> {
5957 let ExeDomain = SSEPackedSingle in {
5958 // Intrinsic operation, reg.
5959 // Vector intrinsic operation, reg
5960 def PSr : SS4AIi8<opcps, MRMSrcReg,
5961 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5962 !strconcat(OpcodeStr,
5963 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5964 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
5967 // Vector intrinsic operation, mem
5968 def PSm : SS4AIi8<opcps, MRMSrcMem,
5969 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5970 !strconcat(OpcodeStr,
5971 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5973 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
5975 } // ExeDomain = SSEPackedSingle
5977 let ExeDomain = SSEPackedDouble in {
5978 // Vector intrinsic operation, reg
5979 def PDr : SS4AIi8<opcpd, MRMSrcReg,
5980 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5981 !strconcat(OpcodeStr,
5982 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5983 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
5986 // Vector intrinsic operation, mem
5987 def PDm : SS4AIi8<opcpd, MRMSrcMem,
5988 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5989 !strconcat(OpcodeStr,
5990 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5992 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
5994 } // ExeDomain = SSEPackedDouble
5997 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6000 Intrinsic F64Int, bit Is2Addr = 1> {
6001 let ExeDomain = GenericDomain in {
6002 // Intrinsic operation, reg.
6003 def SSr : SS4AIi8<opcss, MRMSrcReg,
6004 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6006 !strconcat(OpcodeStr,
6007 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6008 !strconcat(OpcodeStr,
6009 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6010 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6013 // Intrinsic operation, mem.
6014 def SSm : SS4AIi8<opcss, MRMSrcMem,
6015 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6017 !strconcat(OpcodeStr,
6018 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6019 !strconcat(OpcodeStr,
6020 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6022 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6025 // Intrinsic operation, reg.
6026 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6027 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6029 !strconcat(OpcodeStr,
6030 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6031 !strconcat(OpcodeStr,
6032 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6033 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6036 // Intrinsic operation, mem.
6037 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6038 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6040 !strconcat(OpcodeStr,
6041 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6042 !strconcat(OpcodeStr,
6043 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6045 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6047 } // ExeDomain = GenericDomain
6050 // FP round - roundss, roundps, roundsd, roundpd
6051 let Predicates = [HasAVX] in {
6053 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6054 memopv4f32, memopv2f64,
6055 int_x86_sse41_round_ps,
6056 int_x86_sse41_round_pd>, VEX;
6057 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6058 memopv8f32, memopv4f64,
6059 int_x86_avx_round_ps_256,
6060 int_x86_avx_round_pd_256>, VEX;
6061 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6062 int_x86_sse41_round_ss,
6063 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6066 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6067 memopv4f32, memopv2f64,
6068 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6069 let Constraints = "$src1 = $dst" in
6070 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6071 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6073 //===----------------------------------------------------------------------===//
6074 // SSE4.1 - Packed Bit Test
6075 //===----------------------------------------------------------------------===//
6077 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6078 // the intel intrinsic that corresponds to this.
6079 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6080 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6081 "vptest\t{$src2, $src1|$src1, $src2}",
6082 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
6084 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6085 "vptest\t{$src2, $src1|$src1, $src2}",
6086 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
6089 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6090 "vptest\t{$src2, $src1|$src1, $src2}",
6091 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6093 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6094 "vptest\t{$src2, $src1|$src1, $src2}",
6095 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6099 let Defs = [EFLAGS] in {
6100 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6101 "ptest\t{$src2, $src1|$src1, $src2}",
6102 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
6104 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6105 "ptest\t{$src2, $src1|$src1, $src2}",
6106 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
6110 // The bit test instructions below are AVX only
6111 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6112 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6113 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6114 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6115 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6116 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6117 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6118 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6122 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6123 let ExeDomain = SSEPackedSingle in {
6124 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6125 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6127 let ExeDomain = SSEPackedDouble in {
6128 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6129 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6133 //===----------------------------------------------------------------------===//
6134 // SSE4.1 - Misc Instructions
6135 //===----------------------------------------------------------------------===//
6137 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6138 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6139 "popcnt{w}\t{$src, $dst|$dst, $src}",
6140 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6142 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6143 "popcnt{w}\t{$src, $dst|$dst, $src}",
6144 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6145 (implicit EFLAGS)]>, OpSize, XS;
6147 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6148 "popcnt{l}\t{$src, $dst|$dst, $src}",
6149 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6151 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6152 "popcnt{l}\t{$src, $dst|$dst, $src}",
6153 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6154 (implicit EFLAGS)]>, XS;
6156 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6157 "popcnt{q}\t{$src, $dst|$dst, $src}",
6158 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6160 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6161 "popcnt{q}\t{$src, $dst|$dst, $src}",
6162 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6163 (implicit EFLAGS)]>, XS;
6168 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6169 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6170 Intrinsic IntId128> {
6171 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6173 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6174 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6175 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6177 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6180 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6183 let Predicates = [HasAVX] in
6184 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6185 int_x86_sse41_phminposuw>, VEX;
6186 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6187 int_x86_sse41_phminposuw>;
6189 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6190 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6191 Intrinsic IntId128, bit Is2Addr = 1> {
6192 let isCommutable = 1 in
6193 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6194 (ins VR128:$src1, VR128:$src2),
6196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6198 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6199 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6200 (ins VR128:$src1, i128mem:$src2),
6202 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6203 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6205 (IntId128 VR128:$src1,
6206 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6209 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6210 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6211 Intrinsic IntId256> {
6212 let isCommutable = 1 in
6213 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6214 (ins VR256:$src1, VR256:$src2),
6215 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6216 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6217 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6218 (ins VR256:$src1, i256mem:$src2),
6219 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6221 (IntId256 VR256:$src1,
6222 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6225 let Predicates = [HasAVX] in {
6226 let isCommutable = 0 in
6227 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6229 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
6231 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6233 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6235 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6237 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6239 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6241 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6243 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6245 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6247 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6250 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
6251 (VPCMPEQQrr VR128:$src1, VR128:$src2)>;
6252 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
6253 (VPCMPEQQrm VR128:$src1, addr:$src2)>;
6256 let Predicates = [HasAVX2] in {
6257 let isCommutable = 0 in
6258 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6259 int_x86_avx2_packusdw>, VEX_4V;
6260 defm VPCMPEQQ : SS41I_binop_rm_int_y<0x29, "vpcmpeqq",
6261 int_x86_avx2_pcmpeq_q>, VEX_4V;
6262 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6263 int_x86_avx2_pmins_b>, VEX_4V;
6264 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6265 int_x86_avx2_pmins_d>, VEX_4V;
6266 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6267 int_x86_avx2_pminu_d>, VEX_4V;
6268 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6269 int_x86_avx2_pminu_w>, VEX_4V;
6270 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6271 int_x86_avx2_pmaxs_b>, VEX_4V;
6272 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6273 int_x86_avx2_pmaxs_d>, VEX_4V;
6274 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6275 int_x86_avx2_pmaxu_d>, VEX_4V;
6276 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6277 int_x86_avx2_pmaxu_w>, VEX_4V;
6278 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6279 int_x86_avx2_pmul_dq>, VEX_4V;
6281 def : Pat<(v4i64 (X86pcmpeqq VR256:$src1, VR256:$src2)),
6282 (VPCMPEQQYrr VR256:$src1, VR256:$src2)>;
6283 def : Pat<(v4i64 (X86pcmpeqq VR256:$src1, (memop addr:$src2))),
6284 (VPCMPEQQYrm VR256:$src1, addr:$src2)>;
6287 let Constraints = "$src1 = $dst" in {
6288 let isCommutable = 0 in
6289 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6290 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
6291 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6292 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6293 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6294 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6295 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6296 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6297 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6298 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6299 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6302 let Predicates = [HasSSE41] in {
6303 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
6304 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
6305 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
6306 (PCMPEQQrm VR128:$src1, addr:$src2)>;
6309 /// SS48I_binop_rm - Simple SSE41 binary operator.
6310 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6311 ValueType OpVT, bit Is2Addr = 1> {
6312 let isCommutable = 1 in
6313 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6314 (ins VR128:$src1, VR128:$src2),
6316 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6318 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
6320 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6321 (ins VR128:$src1, i128mem:$src2),
6323 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6324 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6325 [(set VR128:$dst, (OpNode VR128:$src1,
6326 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
6330 /// SS48I_binop_rm - Simple SSE41 binary operator.
6331 multiclass SS48I_binop_rm_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
6333 let isCommutable = 1 in
6334 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6335 (ins VR256:$src1, VR256:$src2),
6336 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6337 [(set VR256:$dst, (OpVT (OpNode VR256:$src1, VR256:$src2)))]>,
6339 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6340 (ins VR256:$src1, i256mem:$src2),
6341 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6342 [(set VR256:$dst, (OpNode VR256:$src1,
6343 (bc_v8i32 (memopv4i64 addr:$src2))))]>,
6347 let Predicates = [HasAVX] in
6348 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
6349 let Predicates = [HasAVX2] in
6350 defm VPMULLD : SS48I_binop_rm_y<0x40, "vpmulld", mul, v8i32>, VEX_4V;
6351 let Constraints = "$src1 = $dst" in
6352 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
6354 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6355 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6356 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6357 X86MemOperand x86memop, bit Is2Addr = 1> {
6358 let isCommutable = 1 in
6359 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6360 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6362 !strconcat(OpcodeStr,
6363 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6364 !strconcat(OpcodeStr,
6365 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6366 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6368 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6369 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6371 !strconcat(OpcodeStr,
6372 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6373 !strconcat(OpcodeStr,
6374 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6377 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6381 let Predicates = [HasAVX] in {
6382 let isCommutable = 0 in {
6383 let ExeDomain = SSEPackedSingle in {
6384 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6385 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6386 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6387 int_x86_avx_blend_ps_256, VR256, memopv8f32, i256mem, 0>, VEX_4V;
6389 let ExeDomain = SSEPackedDouble in {
6390 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6391 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6392 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6393 int_x86_avx_blend_pd_256, VR256, memopv4f64, i256mem, 0>, VEX_4V;
6395 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6396 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6397 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6398 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6400 let ExeDomain = SSEPackedSingle in
6401 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6402 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6403 let ExeDomain = SSEPackedDouble in
6404 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6405 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6406 let ExeDomain = SSEPackedSingle in
6407 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6408 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6411 let Predicates = [HasAVX2] in {
6412 let isCommutable = 0 in {
6413 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6414 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6415 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6416 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6420 let Constraints = "$src1 = $dst" in {
6421 let isCommutable = 0 in {
6422 let ExeDomain = SSEPackedSingle in
6423 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6424 VR128, memopv4f32, i128mem>;
6425 let ExeDomain = SSEPackedDouble in
6426 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6427 VR128, memopv2f64, i128mem>;
6428 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6429 VR128, memopv2i64, i128mem>;
6430 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6431 VR128, memopv2i64, i128mem>;
6433 let ExeDomain = SSEPackedSingle in
6434 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6435 VR128, memopv4f32, i128mem>;
6436 let ExeDomain = SSEPackedDouble in
6437 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6438 VR128, memopv2f64, i128mem>;
6441 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6442 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6443 RegisterClass RC, X86MemOperand x86memop,
6444 PatFrag mem_frag, Intrinsic IntId> {
6445 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
6446 (ins RC:$src1, RC:$src2, RC:$src3),
6447 !strconcat(OpcodeStr,
6448 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6449 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6450 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6452 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
6453 (ins RC:$src1, x86memop:$src2, RC:$src3),
6454 !strconcat(OpcodeStr,
6455 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6457 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6459 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6462 let Predicates = [HasAVX] in {
6463 let ExeDomain = SSEPackedDouble in {
6464 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
6465 memopv2f64, int_x86_sse41_blendvpd>;
6466 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
6467 memopv4f64, int_x86_avx_blendv_pd_256>;
6468 } // ExeDomain = SSEPackedDouble
6469 let ExeDomain = SSEPackedSingle in {
6470 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
6471 memopv4f32, int_x86_sse41_blendvps>;
6472 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
6473 memopv8f32, int_x86_avx_blendv_ps_256>;
6474 } // ExeDomain = SSEPackedSingle
6475 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6476 memopv2i64, int_x86_sse41_pblendvb>;
6479 let Predicates = [HasAVX2] in {
6480 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6481 memopv4i64, int_x86_avx2_pblendvb>;
6484 let Predicates = [HasAVX] in {
6485 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6486 (v16i8 VR128:$src2))),
6487 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6488 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6489 (v4i32 VR128:$src2))),
6490 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6491 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6492 (v4f32 VR128:$src2))),
6493 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6494 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6495 (v2i64 VR128:$src2))),
6496 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6497 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6498 (v2f64 VR128:$src2))),
6499 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6500 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6501 (v8i32 VR256:$src2))),
6502 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6503 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6504 (v8f32 VR256:$src2))),
6505 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6506 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6507 (v4i64 VR256:$src2))),
6508 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6509 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6510 (v4f64 VR256:$src2))),
6511 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6514 let Predicates = [HasAVX2] in {
6515 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6516 (v32i8 VR256:$src2))),
6517 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6520 /// SS41I_ternary_int - SSE 4.1 ternary operator
6521 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6522 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6524 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6525 (ins VR128:$src1, VR128:$src2),
6526 !strconcat(OpcodeStr,
6527 "\t{$src2, $dst|$dst, $src2}"),
6528 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6531 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6532 (ins VR128:$src1, i128mem:$src2),
6533 !strconcat(OpcodeStr,
6534 "\t{$src2, $dst|$dst, $src2}"),
6537 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6541 let ExeDomain = SSEPackedDouble in
6542 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64,
6543 int_x86_sse41_blendvpd>;
6544 let ExeDomain = SSEPackedSingle in
6545 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32,
6546 int_x86_sse41_blendvps>;
6547 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64,
6548 int_x86_sse41_pblendvb>;
6550 let Predicates = [HasSSE41] in {
6551 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6552 (v16i8 VR128:$src2))),
6553 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6554 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6555 (v4i32 VR128:$src2))),
6556 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6557 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6558 (v4f32 VR128:$src2))),
6559 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6560 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6561 (v2i64 VR128:$src2))),
6562 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6563 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6564 (v2f64 VR128:$src2))),
6565 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6568 let Predicates = [HasAVX] in
6569 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6570 "vmovntdqa\t{$src, $dst|$dst, $src}",
6571 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6573 let Predicates = [HasAVX2] in
6574 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6575 "vmovntdqa\t{$src, $dst|$dst, $src}",
6576 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6578 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6579 "movntdqa\t{$src, $dst|$dst, $src}",
6580 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6583 //===----------------------------------------------------------------------===//
6584 // SSE4.2 - Compare Instructions
6585 //===----------------------------------------------------------------------===//
6587 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
6588 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
6589 Intrinsic IntId128, bit Is2Addr = 1> {
6590 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
6591 (ins VR128:$src1, VR128:$src2),
6593 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6594 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6595 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6597 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
6598 (ins VR128:$src1, i128mem:$src2),
6600 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6601 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6603 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
6606 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
6607 multiclass SS42I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6608 Intrinsic IntId256> {
6609 def Yrr : SS428I<opc, MRMSrcReg, (outs VR256:$dst),
6610 (ins VR256:$src1, VR256:$src2),
6611 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6612 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
6614 def Yrm : SS428I<opc, MRMSrcMem, (outs VR256:$dst),
6615 (ins VR256:$src1, i256mem:$src2),
6616 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6618 (IntId256 VR256:$src1, (memopv4i64 addr:$src2)))]>, OpSize;
6621 let Predicates = [HasAVX] in {
6622 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
6625 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6626 (VPCMPGTQrr VR128:$src1, VR128:$src2)>;
6627 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6628 (VPCMPGTQrm VR128:$src1, addr:$src2)>;
6631 let Predicates = [HasAVX2] in {
6632 defm VPCMPGTQ : SS42I_binop_rm_int_y<0x37, "vpcmpgtq", int_x86_avx2_pcmpgt_q>,
6635 def : Pat<(v4i64 (X86pcmpgtq VR256:$src1, VR256:$src2)),
6636 (VPCMPGTQYrr VR256:$src1, VR256:$src2)>;
6637 def : Pat<(v4i64 (X86pcmpgtq VR256:$src1, (memop addr:$src2))),
6638 (VPCMPGTQYrm VR256:$src1, addr:$src2)>;
6641 let Constraints = "$src1 = $dst" in
6642 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
6644 let Predicates = [HasSSE42] in {
6645 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6646 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
6647 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6648 (PCMPGTQrm VR128:$src1, addr:$src2)>;
6651 //===----------------------------------------------------------------------===//
6652 // SSE4.2 - String/text Processing Instructions
6653 //===----------------------------------------------------------------------===//
6655 // Packed Compare Implicit Length Strings, Return Mask
6656 multiclass pseudo_pcmpistrm<string asm> {
6657 def REG : PseudoI<(outs VR128:$dst),
6658 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6659 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6661 def MEM : PseudoI<(outs VR128:$dst),
6662 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6663 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6664 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6667 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6668 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6669 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6672 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6673 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6674 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6675 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6677 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6678 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6679 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6682 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6683 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6684 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6685 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6687 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6688 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6689 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6692 // Packed Compare Explicit Length Strings, Return Mask
6693 multiclass pseudo_pcmpestrm<string asm> {
6694 def REG : PseudoI<(outs VR128:$dst),
6695 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6696 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6697 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6698 def MEM : PseudoI<(outs VR128:$dst),
6699 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6700 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6701 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6704 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6705 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6706 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6709 let Predicates = [HasAVX],
6710 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6711 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6712 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6713 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6715 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6716 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6717 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6720 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6721 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6722 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6723 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6725 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6726 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6727 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6730 // Packed Compare Implicit Length Strings, Return Index
6731 let Defs = [ECX, EFLAGS] in {
6732 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6733 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6734 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6735 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6736 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6737 (implicit EFLAGS)]>, OpSize;
6738 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6739 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6740 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6741 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6742 (implicit EFLAGS)]>, OpSize;
6746 let Predicates = [HasAVX] in {
6747 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6749 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6751 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6753 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6755 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6757 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6761 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6762 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6763 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6764 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6765 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6766 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6768 // Packed Compare Explicit Length Strings, Return Index
6769 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6770 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6771 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6772 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6773 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6774 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6775 (implicit EFLAGS)]>, OpSize;
6776 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6777 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6778 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6780 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6781 (implicit EFLAGS)]>, OpSize;
6785 let Predicates = [HasAVX] in {
6786 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6788 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6790 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6792 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6794 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6796 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6800 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6801 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6802 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6803 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6804 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6805 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6807 //===----------------------------------------------------------------------===//
6808 // SSE4.2 - CRC Instructions
6809 //===----------------------------------------------------------------------===//
6811 // No CRC instructions have AVX equivalents
6813 // crc intrinsic instruction
6814 // This set of instructions are only rm, the only difference is the size
6816 let Constraints = "$src1 = $dst" in {
6817 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6818 (ins GR32:$src1, i8mem:$src2),
6819 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6821 (int_x86_sse42_crc32_32_8 GR32:$src1,
6822 (load addr:$src2)))]>;
6823 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6824 (ins GR32:$src1, GR8:$src2),
6825 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6827 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6828 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6829 (ins GR32:$src1, i16mem:$src2),
6830 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6832 (int_x86_sse42_crc32_32_16 GR32:$src1,
6833 (load addr:$src2)))]>,
6835 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6836 (ins GR32:$src1, GR16:$src2),
6837 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6839 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6841 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6842 (ins GR32:$src1, i32mem:$src2),
6843 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6845 (int_x86_sse42_crc32_32_32 GR32:$src1,
6846 (load addr:$src2)))]>;
6847 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6848 (ins GR32:$src1, GR32:$src2),
6849 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6851 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6852 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6853 (ins GR64:$src1, i8mem:$src2),
6854 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6856 (int_x86_sse42_crc32_64_8 GR64:$src1,
6857 (load addr:$src2)))]>,
6859 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6860 (ins GR64:$src1, GR8:$src2),
6861 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6863 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6865 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6866 (ins GR64:$src1, i64mem:$src2),
6867 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6869 (int_x86_sse42_crc32_64_64 GR64:$src1,
6870 (load addr:$src2)))]>,
6872 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6873 (ins GR64:$src1, GR64:$src2),
6874 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6876 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6880 //===----------------------------------------------------------------------===//
6881 // AES-NI Instructions
6882 //===----------------------------------------------------------------------===//
6884 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
6885 Intrinsic IntId128, bit Is2Addr = 1> {
6886 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
6887 (ins VR128:$src1, VR128:$src2),
6889 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6890 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6891 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6893 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
6894 (ins VR128:$src1, i128mem:$src2),
6896 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6897 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6899 (IntId128 VR128:$src1,
6900 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6903 // Perform One Round of an AES Encryption/Decryption Flow
6904 let Predicates = [HasAVX, HasAES] in {
6905 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
6906 int_x86_aesni_aesenc, 0>, VEX_4V;
6907 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
6908 int_x86_aesni_aesenclast, 0>, VEX_4V;
6909 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
6910 int_x86_aesni_aesdec, 0>, VEX_4V;
6911 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
6912 int_x86_aesni_aesdeclast, 0>, VEX_4V;
6915 let Constraints = "$src1 = $dst" in {
6916 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
6917 int_x86_aesni_aesenc>;
6918 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
6919 int_x86_aesni_aesenclast>;
6920 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
6921 int_x86_aesni_aesdec>;
6922 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
6923 int_x86_aesni_aesdeclast>;
6926 let Predicates = [HasAES] in {
6927 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6928 (AESENCrr VR128:$src1, VR128:$src2)>;
6929 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6930 (AESENCrm VR128:$src1, addr:$src2)>;
6931 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6932 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
6933 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6934 (AESENCLASTrm VR128:$src1, addr:$src2)>;
6935 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6936 (AESDECrr VR128:$src1, VR128:$src2)>;
6937 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6938 (AESDECrm VR128:$src1, addr:$src2)>;
6939 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6940 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
6941 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6942 (AESDECLASTrm VR128:$src1, addr:$src2)>;
6945 let Predicates = [HasAVX, HasAES], AddedComplexity = 20 in {
6946 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6947 (VAESENCrr VR128:$src1, VR128:$src2)>;
6948 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6949 (VAESENCrm VR128:$src1, addr:$src2)>;
6950 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6951 (VAESENCLASTrr VR128:$src1, VR128:$src2)>;
6952 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6953 (VAESENCLASTrm VR128:$src1, addr:$src2)>;
6954 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6955 (VAESDECrr VR128:$src1, VR128:$src2)>;
6956 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6957 (VAESDECrm VR128:$src1, addr:$src2)>;
6958 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6959 (VAESDECLASTrr VR128:$src1, VR128:$src2)>;
6960 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6961 (VAESDECLASTrm VR128:$src1, addr:$src2)>;
6964 // Perform the AES InvMixColumn Transformation
6965 let Predicates = [HasAVX, HasAES] in {
6966 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6968 "vaesimc\t{$src1, $dst|$dst, $src1}",
6970 (int_x86_aesni_aesimc VR128:$src1))]>,
6972 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6973 (ins i128mem:$src1),
6974 "vaesimc\t{$src1, $dst|$dst, $src1}",
6976 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6979 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6981 "aesimc\t{$src1, $dst|$dst, $src1}",
6983 (int_x86_aesni_aesimc VR128:$src1))]>,
6985 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6986 (ins i128mem:$src1),
6987 "aesimc\t{$src1, $dst|$dst, $src1}",
6989 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6992 // AES Round Key Generation Assist
6993 let Predicates = [HasAVX, HasAES] in {
6994 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6995 (ins VR128:$src1, i8imm:$src2),
6996 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6998 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7000 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7001 (ins i128mem:$src1, i8imm:$src2),
7002 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7004 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
7008 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7009 (ins VR128:$src1, i8imm:$src2),
7010 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7012 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7014 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7015 (ins i128mem:$src1, i8imm:$src2),
7016 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7018 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
7022 //===----------------------------------------------------------------------===//
7023 // CLMUL Instructions
7024 //===----------------------------------------------------------------------===//
7026 // Carry-less Multiplication instructions
7027 let neverHasSideEffects = 1 in {
7028 let Constraints = "$src1 = $dst" in {
7029 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7030 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7031 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7035 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7036 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7037 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7041 // AVX carry-less Multiplication instructions
7042 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7043 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7044 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7048 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7049 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7050 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7055 multiclass pclmul_alias<string asm, int immop> {
7056 def : InstAlias<!strconcat("pclmul", asm,
7057 "dq {$src, $dst|$dst, $src}"),
7058 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7060 def : InstAlias<!strconcat("pclmul", asm,
7061 "dq {$src, $dst|$dst, $src}"),
7062 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7064 def : InstAlias<!strconcat("vpclmul", asm,
7065 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7066 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7068 def : InstAlias<!strconcat("vpclmul", asm,
7069 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7070 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7072 defm : pclmul_alias<"hqhq", 0x11>;
7073 defm : pclmul_alias<"hqlq", 0x01>;
7074 defm : pclmul_alias<"lqhq", 0x10>;
7075 defm : pclmul_alias<"lqlq", 0x00>;
7077 //===----------------------------------------------------------------------===//
7079 //===----------------------------------------------------------------------===//
7081 //===----------------------------------------------------------------------===//
7082 // VBROADCAST - Load from memory and broadcast to all elements of the
7083 // destination operand
7085 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7086 X86MemOperand x86memop, Intrinsic Int> :
7087 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7088 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7089 [(set RC:$dst, (Int addr:$src))]>, VEX;
7091 // AVX2 adds register forms
7092 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7094 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7095 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7096 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7098 let ExeDomain = SSEPackedSingle in {
7099 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7100 int_x86_avx_vbroadcast_ss>;
7101 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7102 int_x86_avx_vbroadcast_ss_256>;
7104 let ExeDomain = SSEPackedDouble in
7105 def VBROADCASTSDrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7106 int_x86_avx_vbroadcast_sd_256>;
7107 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7108 int_x86_avx_vbroadcastf128_pd_256>;
7110 let ExeDomain = SSEPackedSingle in {
7111 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7112 int_x86_avx2_vbroadcast_ss_ps>;
7113 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7114 int_x86_avx2_vbroadcast_ss_ps_256>;
7116 let ExeDomain = SSEPackedDouble in
7117 def VBROADCASTSDrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7118 int_x86_avx2_vbroadcast_sd_pd_256>;
7120 let Predicates = [HasAVX2] in
7121 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7122 int_x86_avx2_vbroadcasti128>;
7124 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7125 (VBROADCASTF128 addr:$src)>;
7128 //===----------------------------------------------------------------------===//
7129 // VINSERTF128 - Insert packed floating-point values
7131 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7132 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7133 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7134 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7137 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7138 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7139 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7143 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
7144 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
7145 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
7146 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
7147 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
7148 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
7150 //===----------------------------------------------------------------------===//
7151 // VEXTRACTF128 - Extract packed floating-point values
7153 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7154 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7155 (ins VR256:$src1, i8imm:$src2),
7156 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7159 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7160 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7161 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7165 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
7166 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7167 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
7168 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7169 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
7170 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7172 //===----------------------------------------------------------------------===//
7173 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7175 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7176 Intrinsic IntLd, Intrinsic IntLd256,
7177 Intrinsic IntSt, Intrinsic IntSt256> {
7178 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7179 (ins VR128:$src1, f128mem:$src2),
7180 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7181 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7183 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7184 (ins VR256:$src1, f256mem:$src2),
7185 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7186 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7188 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7189 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7190 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7191 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7192 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7193 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7194 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7195 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7198 let ExeDomain = SSEPackedSingle in
7199 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7200 int_x86_avx_maskload_ps,
7201 int_x86_avx_maskload_ps_256,
7202 int_x86_avx_maskstore_ps,
7203 int_x86_avx_maskstore_ps_256>;
7204 let ExeDomain = SSEPackedDouble in
7205 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7206 int_x86_avx_maskload_pd,
7207 int_x86_avx_maskload_pd_256,
7208 int_x86_avx_maskstore_pd,
7209 int_x86_avx_maskstore_pd_256>;
7211 //===----------------------------------------------------------------------===//
7212 // VPERMIL - Permute Single and Double Floating-Point Values
7214 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7215 RegisterClass RC, X86MemOperand x86memop_f,
7216 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
7217 Intrinsic IntVar, Intrinsic IntImm> {
7218 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7219 (ins RC:$src1, RC:$src2),
7220 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7221 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7222 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7223 (ins RC:$src1, x86memop_i:$src2),
7224 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7225 [(set RC:$dst, (IntVar RC:$src1,
7226 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7228 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7229 (ins RC:$src1, i8imm:$src2),
7230 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7231 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
7232 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7233 (ins x86memop_f:$src1, i8imm:$src2),
7234 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7235 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
7238 let ExeDomain = SSEPackedSingle in {
7239 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7240 memopv4f32, memopv2i64,
7241 int_x86_avx_vpermilvar_ps,
7242 int_x86_avx_vpermil_ps>;
7243 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7244 memopv8f32, memopv4i64,
7245 int_x86_avx_vpermilvar_ps_256,
7246 int_x86_avx_vpermil_ps_256>;
7248 let ExeDomain = SSEPackedDouble in {
7249 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7250 memopv2f64, memopv2i64,
7251 int_x86_avx_vpermilvar_pd,
7252 int_x86_avx_vpermil_pd>;
7253 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7254 memopv4f64, memopv4i64,
7255 int_x86_avx_vpermilvar_pd_256,
7256 int_x86_avx_vpermil_pd_256>;
7259 def : Pat<(v8f32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7260 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7261 def : Pat<(v4f64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7262 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7263 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7264 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7265 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7266 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7267 def : Pat<(v8f32 (X86VPermilp (memopv8f32 addr:$src1), (i8 imm:$imm))),
7268 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7269 def : Pat<(v4f64 (X86VPermilp (memopv4f64 addr:$src1), (i8 imm:$imm))),
7270 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7271 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7273 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7274 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7275 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7277 //===----------------------------------------------------------------------===//
7278 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7280 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7281 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7282 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7283 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7286 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7287 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7288 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7292 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
7293 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
7294 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
7295 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
7296 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
7297 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
7299 def : Pat<(int_x86_avx_vperm2f128_ps_256
7300 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
7301 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
7302 def : Pat<(int_x86_avx_vperm2f128_pd_256
7303 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
7304 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
7305 def : Pat<(int_x86_avx_vperm2f128_si_256
7306 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)), imm:$src3),
7307 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
7309 //===----------------------------------------------------------------------===//
7310 // VZERO - Zero YMM registers
7312 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7313 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7314 // Zero All YMM registers
7315 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7316 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7318 // Zero Upper bits of YMM registers
7319 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7320 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7323 //===----------------------------------------------------------------------===//
7324 // Half precision conversion instructions
7325 //===----------------------------------------------------------------------===//
7326 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7327 let Predicates = [HasAVX, HasF16C] in {
7328 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7329 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7330 [(set RC:$dst, (Int VR128:$src))]>,
7332 let neverHasSideEffects = 1, mayLoad = 1 in
7333 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7334 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7338 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7339 let Predicates = [HasAVX, HasF16C] in {
7340 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7341 (ins RC:$src1, i32i8imm:$src2),
7342 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7343 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7345 let neverHasSideEffects = 1, mayLoad = 1 in
7346 def mr : Ii8<0x1D, MRMDestMem, (outs x86memop:$dst),
7347 (ins RC:$src1, i32i8imm:$src2),
7348 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7353 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7354 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7355 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7356 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7358 //===----------------------------------------------------------------------===//
7359 // AVX2 Instructions
7360 //===----------------------------------------------------------------------===//
7362 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7363 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7364 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7365 X86MemOperand x86memop> {
7366 let isCommutable = 1 in
7367 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7368 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7369 !strconcat(OpcodeStr,
7370 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7371 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7373 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7374 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7375 !strconcat(OpcodeStr,
7376 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7379 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7383 let isCommutable = 0 in {
7384 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7385 VR128, memopv2i64, i128mem>;
7386 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7387 VR256, memopv4i64, i256mem>;
7390 //===----------------------------------------------------------------------===//
7391 // VPBROADCAST - Load from memory and broadcast to all elements of the
7392 // destination operand
7394 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7395 X86MemOperand x86memop, PatFrag ld_frag,
7396 Intrinsic Int128, Intrinsic Int256> {
7397 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7398 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7399 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7400 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7401 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7403 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7404 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7405 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7406 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7407 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7408 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7410 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7413 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7414 int_x86_avx2_pbroadcastb_128,
7415 int_x86_avx2_pbroadcastb_256>;
7416 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7417 int_x86_avx2_pbroadcastw_128,
7418 int_x86_avx2_pbroadcastw_256>;
7419 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7420 int_x86_avx2_pbroadcastd_128,
7421 int_x86_avx2_pbroadcastd_256>;
7422 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7423 int_x86_avx2_pbroadcastq_128,
7424 int_x86_avx2_pbroadcastq_256>;
7426 let Predicates = [HasAVX2] in {
7427 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7428 (VPBROADCASTBrm addr:$src)>;
7429 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7430 (VPBROADCASTBYrm addr:$src)>;
7431 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7432 (VPBROADCASTWrm addr:$src)>;
7433 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7434 (VPBROADCASTWYrm addr:$src)>;
7435 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7436 (VPBROADCASTDrm addr:$src)>;
7437 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7438 (VPBROADCASTDYrm addr:$src)>;
7439 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7440 (VPBROADCASTQrm addr:$src)>;
7441 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7442 (VPBROADCASTQYrm addr:$src)>;
7445 // AVX1 broadcast patterns
7446 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7447 (VBROADCASTSSYrm addr:$src)>;
7448 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7449 (VBROADCASTSDrm addr:$src)>;
7450 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7451 (VBROADCASTSSYrm addr:$src)>;
7452 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7453 (VBROADCASTSDrm addr:$src)>;
7455 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7456 (VBROADCASTSSrm addr:$src)>;
7457 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7458 (VBROADCASTSSrm addr:$src)>;
7460 //===----------------------------------------------------------------------===//
7461 // VPERM - Permute instructions
7464 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7466 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7467 (ins VR256:$src1, VR256:$src2),
7468 !strconcat(OpcodeStr,
7469 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7470 [(set VR256:$dst, (Int VR256:$src1, VR256:$src2))]>, VEX_4V;
7471 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7472 (ins VR256:$src1, i256mem:$src2),
7473 !strconcat(OpcodeStr,
7474 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7475 [(set VR256:$dst, (Int VR256:$src1,
7476 (bitconvert (mem_frag addr:$src2))))]>,
7480 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, int_x86_avx2_permd>;
7481 let ExeDomain = SSEPackedSingle in
7482 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, int_x86_avx2_permps>;
7484 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7486 def Yrr : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7487 (ins VR256:$src1, i8imm:$src2),
7488 !strconcat(OpcodeStr,
7489 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7490 [(set VR256:$dst, (Int VR256:$src1, imm:$src2))]>, VEX;
7491 def Yrm : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7492 (ins i256mem:$src1, i8imm:$src2),
7493 !strconcat(OpcodeStr,
7494 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7495 [(set VR256:$dst, (Int (mem_frag addr:$src1), imm:$src2))]>,
7499 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, int_x86_avx2_permq>,
7501 let ExeDomain = SSEPackedDouble in
7502 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, int_x86_avx2_permpd>,
7505 //===----------------------------------------------------------------------===//
7506 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7508 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7509 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7510 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7512 (int_x86_avx2_vperm2i128 VR256:$src1, VR256:$src2, imm:$src3))]>,
7514 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7515 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7516 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7518 (int_x86_avx2_vperm2i128 VR256:$src1, (memopv4i64 addr:$src2),
7522 let Predicates = [HasAVX2] in {
7523 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7524 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7525 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7526 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7527 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7528 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7529 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7530 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7532 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7534 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7535 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7536 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7537 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7538 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7540 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7541 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7543 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7547 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7548 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7549 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7550 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7551 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7552 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7553 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7554 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7555 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7556 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7557 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7558 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7560 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1,
7561 (memopv8f32 addr:$src2), (i8 imm:$imm))),
7562 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7563 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7564 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7565 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7566 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7567 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7568 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7569 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7570 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7571 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7572 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7573 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7574 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7575 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7576 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7577 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7580 //===----------------------------------------------------------------------===//
7581 // VINSERTI128 - Insert packed integer values
7583 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7584 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7585 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7587 (int_x86_avx2_vinserti128 VR256:$src1, VR128:$src2, imm:$src3))]>,
7589 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7590 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7591 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7593 (int_x86_avx2_vinserti128 VR256:$src1, (memopv2i64 addr:$src2),
7594 imm:$src3))]>, VEX_4V;
7596 let Predicates = [HasAVX2] in {
7597 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7599 (VINSERTI128rr VR256:$src1, VR128:$src2,
7600 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7601 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7603 (VINSERTI128rr VR256:$src1, VR128:$src2,
7604 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7605 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7607 (VINSERTI128rr VR256:$src1, VR128:$src2,
7608 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7609 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7611 (VINSERTI128rr VR256:$src1, VR128:$src2,
7612 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7616 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7618 (VINSERTF128rr VR256:$src1, VR128:$src2,
7619 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7620 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7622 (VINSERTF128rr VR256:$src1, VR128:$src2,
7623 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7624 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7626 (VINSERTF128rr VR256:$src1, VR128:$src2,
7627 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7628 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7630 (VINSERTF128rr VR256:$src1, VR128:$src2,
7631 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7632 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7634 (VINSERTF128rr VR256:$src1, VR128:$src2,
7635 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7636 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7638 (VINSERTF128rr VR256:$src1, VR128:$src2,
7639 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7641 //===----------------------------------------------------------------------===//
7642 // VEXTRACTI128 - Extract packed integer values
7644 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7645 (ins VR256:$src1, i8imm:$src2),
7646 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7648 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7650 let neverHasSideEffects = 1, mayStore = 1 in
7651 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7652 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7653 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7655 let Predicates = [HasAVX2] in {
7656 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7657 (v2i64 (VEXTRACTI128rr
7658 (v4i64 VR256:$src1),
7659 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7660 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7661 (v4i32 (VEXTRACTI128rr
7662 (v8i32 VR256:$src1),
7663 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7664 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7665 (v8i16 (VEXTRACTI128rr
7666 (v16i16 VR256:$src1),
7667 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7668 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7669 (v16i8 (VEXTRACTI128rr
7670 (v32i8 VR256:$src1),
7671 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7675 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7676 (v4f32 (VEXTRACTF128rr
7677 (v8f32 VR256:$src1),
7678 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7679 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7680 (v2f64 (VEXTRACTF128rr
7681 (v4f64 VR256:$src1),
7682 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7683 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7684 (v2i64 (VEXTRACTF128rr
7685 (v4i64 VR256:$src1),
7686 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7687 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7688 (v4i32 (VEXTRACTF128rr
7689 (v8i32 VR256:$src1),
7690 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7691 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7692 (v8i16 (VEXTRACTF128rr
7693 (v16i16 VR256:$src1),
7694 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7695 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7696 (v16i8 (VEXTRACTF128rr
7697 (v32i8 VR256:$src1),
7698 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7700 //===----------------------------------------------------------------------===//
7701 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7703 multiclass avx2_pmovmask<string OpcodeStr,
7704 Intrinsic IntLd128, Intrinsic IntLd256,
7705 Intrinsic IntSt128, Intrinsic IntSt256> {
7706 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7707 (ins VR128:$src1, i128mem:$src2),
7708 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7709 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7710 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7711 (ins VR256:$src1, i256mem:$src2),
7712 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7713 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7714 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7715 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7716 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7717 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7718 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7719 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7720 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7721 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7724 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
7725 int_x86_avx2_maskload_d,
7726 int_x86_avx2_maskload_d_256,
7727 int_x86_avx2_maskstore_d,
7728 int_x86_avx2_maskstore_d_256>;
7729 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
7730 int_x86_avx2_maskload_q,
7731 int_x86_avx2_maskload_q_256,
7732 int_x86_avx2_maskstore_q,
7733 int_x86_avx2_maskstore_q_256>, VEX_W;
7736 //===----------------------------------------------------------------------===//
7737 // Variable Bit Shifts
7739 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
7740 ValueType vt128, ValueType vt256> {
7741 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7742 (ins VR128:$src1, VR128:$src2),
7743 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7745 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
7747 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
7748 (ins VR128:$src1, i128mem:$src2),
7749 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7751 (vt128 (OpNode VR128:$src1,
7752 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
7754 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7755 (ins VR256:$src1, VR256:$src2),
7756 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7758 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
7760 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7761 (ins VR256:$src1, i256mem:$src2),
7762 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7764 (vt256 (OpNode VR256:$src1,
7765 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
7769 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
7770 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
7771 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
7772 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
7773 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;