1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
244 Domain d, OpndItins itins, bit Is2Addr = 1> {
245 let isCommutable = 1 in {
246 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
250 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr, d>,
251 Sched<[itins.Sched]>;
253 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
255 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
257 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm, d>,
258 Sched<[itins.Sched.Folded, ReadAfterLd]>;
261 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
262 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
263 string asm, string SSEVer, string FPSizeStr,
264 Operand memopr, ComplexPattern mem_cpat,
265 Domain d, OpndItins itins, bit Is2Addr = 1> {
266 let isCodeGenOnly = 1 in {
267 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
269 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
271 [(set RC:$dst, (!cast<Intrinsic>(
272 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
273 RC:$src1, RC:$src2))], itins.rr, d>,
274 Sched<[itins.Sched]>;
275 def rm_Int : SI_Int<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
277 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
278 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
279 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
280 SSEVer, "_", OpcodeStr, FPSizeStr))
281 RC:$src1, mem_cpat:$src2))], itins.rm, d>,
282 Sched<[itins.Sched.Folded, ReadAfterLd]>;
286 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
287 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
288 RegisterClass RC, ValueType vt,
289 X86MemOperand x86memop, PatFrag mem_frag,
290 Domain d, OpndItins itins, bit Is2Addr = 1> {
291 let isCommutable = 1 in
292 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
296 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
297 Sched<[itins.Sched]>;
299 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
301 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
302 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
303 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
305 Sched<[itins.Sched.Folded, ReadAfterLd]>;
308 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
309 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
310 string OpcodeStr, X86MemOperand x86memop,
311 list<dag> pat_rr, list<dag> pat_rm,
313 let isCommutable = 1, hasSideEffects = 0 in
314 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
316 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
318 pat_rr, NoItinerary, d>,
319 Sched<[WriteVecLogic]>;
320 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
324 pat_rm, NoItinerary, d>,
325 Sched<[WriteVecLogicLd, ReadAfterLd]>;
328 //===----------------------------------------------------------------------===//
329 // Non-instruction patterns
330 //===----------------------------------------------------------------------===//
332 // A vector extract of the first f32/f64 position is a subregister copy
333 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
335 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
338 // A 128-bit subvector extract from the first 256-bit vector position
339 // is a subregister copy that needs no instruction.
340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
341 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
343 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
346 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
348 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
351 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
353 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
355 // A 128-bit subvector insert to the first 256-bit vector position
356 // is a subregister copy that needs no instruction.
357 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
372 // Implicitly promote a 32-bit scalar to a vector.
373 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
374 (COPY_TO_REGCLASS FR32:$src, VR128)>;
375 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 // Implicitly promote a 64-bit scalar to a vector.
378 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
379 (COPY_TO_REGCLASS FR64:$src, VR128)>;
380 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
383 // Bitcasts between 128-bit vector types. Return the original type since
384 // no instruction is needed for the conversion
385 let Predicates = [HasSSE2] in {
386 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
387 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
388 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
392 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
397 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
402 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
407 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
412 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
418 // Bitcasts between 256-bit vector types. Return the original type since
419 // no instruction is needed for the conversion
420 let Predicates = [HasAVX] in {
421 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
422 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
423 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
427 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
432 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
437 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
442 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
447 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
453 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
454 // This is expanded by ExpandPostRAPseudos.
455 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
456 isPseudo = 1, SchedRW = [WriteZero] in {
457 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
458 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
459 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
460 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
463 //===----------------------------------------------------------------------===//
464 // AVX & SSE - Zero/One Vectors
465 //===----------------------------------------------------------------------===//
467 // Alias instruction that maps zero vector to pxor / xorp* for sse.
468 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
469 // swizzled by ExecutionDepsFix to pxor.
470 // We set canFoldAsLoad because this can be converted to a constant-pool
471 // load of an all-zeros value if folding it would be beneficial.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
473 isPseudo = 1, SchedRW = [WriteZero] in {
474 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
475 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
478 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
479 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
480 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
482 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
485 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
486 // and doesn't need it because on sandy bridge the register is set to zero
487 // at the rename stage without using any execution unit, so SET0PSY
488 // and SET0PDY can be used for vector int instructions without penalty
489 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
490 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
491 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
492 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
495 let Predicates = [HasAVX] in
496 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
498 let Predicates = [HasAVX2] in {
499 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
500 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
501 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
505 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
506 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
507 let Predicates = [HasAVX1Only] in {
508 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
509 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
510 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
512 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
513 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
514 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
516 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
517 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
518 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
520 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
521 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
522 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
525 // We set canFoldAsLoad because this can be converted to a constant-pool
526 // load of an all-ones value if folding it would be beneficial.
527 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
528 isPseudo = 1, SchedRW = [WriteZero] in {
529 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
530 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
531 let Predicates = [HasAVX2] in
532 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
533 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
537 //===----------------------------------------------------------------------===//
538 // SSE 1 & 2 - Move FP Scalar Instructions
540 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
541 // register copies because it's a partial register update; Register-to-register
542 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
543 // that the insert be implementable in terms of a copy, and just mentioned, we
544 // don't use movss/movsd for copies.
545 //===----------------------------------------------------------------------===//
547 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
548 X86MemOperand x86memop, string base_opc,
549 string asm_opr, Domain d = GenericDomain> {
550 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
551 (ins VR128:$src1, RC:$src2),
552 !strconcat(base_opc, asm_opr),
553 [(set VR128:$dst, (vt (OpNode VR128:$src1,
554 (scalar_to_vector RC:$src2))))],
555 IIC_SSE_MOV_S_RR, d>, Sched<[WriteFShuffle]>;
557 // For the disassembler
558 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
559 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
560 (ins VR128:$src1, RC:$src2),
561 !strconcat(base_opc, asm_opr),
562 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
565 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
566 X86MemOperand x86memop, string OpcodeStr,
567 Domain d = GenericDomain> {
569 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
570 "\t{$src2, $src1, $dst|$dst, $src1, $src2}", d>,
573 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
575 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
576 VEX, VEX_LIG, Sched<[WriteStore]>;
578 let Constraints = "$src1 = $dst" in {
579 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
580 "\t{$src2, $dst|$dst, $src2}", d>;
583 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
585 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
589 // Loading from memory automatically zeroing upper bits.
590 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
591 PatFrag mem_pat, string OpcodeStr,
592 Domain d = GenericDomain> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM, d>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM, d>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
604 SSEPackedSingle>, XS;
605 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd",
606 SSEPackedDouble>, XD;
608 let canFoldAsLoad = 1, isReMaterializable = 1 in {
609 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss",
610 SSEPackedSingle>, XS;
612 let AddedComplexity = 20 in
613 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd",
614 SSEPackedDouble>, XD;
618 let Predicates = [UseAVX] in {
619 let AddedComplexity = 20 in {
620 // MOVSSrm zeros the high parts of the register; represent this
621 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
622 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
624 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
625 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
626 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
627 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
629 // MOVSDrm zeros the high parts of the register; represent this
630 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
631 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
633 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
637 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
638 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
639 def : Pat<(v2f64 (X86vzload addr:$src)),
640 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
642 // Represent the same patterns above but in the form they appear for
644 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
645 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
646 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
647 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
648 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
649 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
652 // Extract and store.
653 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
655 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
656 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
658 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
660 // Shuffle with VMOVSS
661 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
662 (VMOVSSrr (v4i32 VR128:$src1),
663 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
664 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
665 (VMOVSSrr (v4f32 VR128:$src1),
666 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
669 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
670 (SUBREG_TO_REG (i32 0),
671 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
672 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
674 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
675 (SUBREG_TO_REG (i32 0),
676 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
677 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
680 // Shuffle with VMOVSD
681 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
682 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
683 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
691 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
694 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
696 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
697 (SUBREG_TO_REG (i32 0),
698 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
699 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
702 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
703 // is during lowering, where it's not possible to recognize the fold cause
704 // it has two uses through a bitcast. One use disappears at isel time and the
705 // fold opportunity reappears.
706 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
707 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
708 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
716 let Predicates = [UseSSE1] in {
717 let Predicates = [NoSSE41], AddedComplexity = 15 in {
718 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
719 // MOVSS to the lower bits.
720 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
721 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
722 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
723 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
728 let AddedComplexity = 20 in {
729 // MOVSSrm already zeros the high parts of the register.
730 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
731 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
732 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
738 // Extract and store.
739 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
741 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
743 // Shuffle with MOVSS
744 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
745 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
746 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
750 let Predicates = [UseSSE2] in {
751 let Predicates = [NoSSE41], AddedComplexity = 15 in {
752 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
753 // MOVSD to the lower bits.
754 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
755 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
758 let AddedComplexity = 20 in {
759 // MOVSDrm already zeros the high parts of the register.
760 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
761 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
762 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzload addr:$src)),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
772 // Extract and store.
773 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
775 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
777 // Shuffle with MOVSD
778 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
779 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
780 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
788 // is during lowering, where it's not possible to recognize the fold because
789 // it has two uses through a bitcast. One use disappears at isel time and the
790 // fold opportunity reappears.
791 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
793 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
801 //===----------------------------------------------------------------------===//
802 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
803 //===----------------------------------------------------------------------===//
805 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
806 X86MemOperand x86memop, PatFrag ld_frag,
807 string asm, Domain d,
809 bit IsReMaterializable = 1> {
810 let hasSideEffects = 0 in
811 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
812 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
813 Sched<[WriteFShuffle]>;
814 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
815 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
816 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
817 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
821 let Predicates = [HasAVX, NoVLX] in {
822 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
823 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
825 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
826 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
828 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
829 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
831 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
832 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
836 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
838 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
839 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
841 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
842 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
844 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
845 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
849 let Predicates = [UseSSE1] in {
850 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
851 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
853 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
854 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
857 let Predicates = [UseSSE2] in {
858 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
859 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
861 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
862 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
867 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
868 "movaps\t{$src, $dst|$dst, $src}",
869 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
870 IIC_SSE_MOVA_P_MR>, VEX;
871 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
872 "movapd\t{$src, $dst|$dst, $src}",
873 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
874 IIC_SSE_MOVA_P_MR>, VEX;
875 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
876 "movups\t{$src, $dst|$dst, $src}",
877 [(store (v4f32 VR128:$src), addr:$dst)],
878 IIC_SSE_MOVU_P_MR>, VEX;
879 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
880 "movupd\t{$src, $dst|$dst, $src}",
881 [(store (v2f64 VR128:$src), addr:$dst)],
882 IIC_SSE_MOVU_P_MR>, VEX;
883 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
884 "movaps\t{$src, $dst|$dst, $src}",
885 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
886 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
887 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
888 "movapd\t{$src, $dst|$dst, $src}",
889 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
890 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
891 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
892 "movups\t{$src, $dst|$dst, $src}",
893 [(store (v8f32 VR256:$src), addr:$dst)],
894 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
895 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
896 "movupd\t{$src, $dst|$dst, $src}",
897 [(store (v4f64 VR256:$src), addr:$dst)],
898 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
902 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
903 SchedRW = [WriteFShuffle] in {
904 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
906 "movaps\t{$src, $dst|$dst, $src}", [],
907 IIC_SSE_MOVA_P_RR>, VEX;
908 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
910 "movapd\t{$src, $dst|$dst, $src}", [],
911 IIC_SSE_MOVA_P_RR>, VEX;
912 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
914 "movups\t{$src, $dst|$dst, $src}", [],
915 IIC_SSE_MOVU_P_RR>, VEX;
916 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
918 "movupd\t{$src, $dst|$dst, $src}", [],
919 IIC_SSE_MOVU_P_RR>, VEX;
920 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
922 "movaps\t{$src, $dst|$dst, $src}", [],
923 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
924 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
926 "movapd\t{$src, $dst|$dst, $src}", [],
927 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
928 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
930 "movups\t{$src, $dst|$dst, $src}", [],
931 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
932 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
934 "movupd\t{$src, $dst|$dst, $src}", [],
935 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
938 let Predicates = [HasAVX] in {
939 def : Pat<(v8i32 (X86vzmovl
940 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v4i64 (X86vzmovl
943 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v8f32 (X86vzmovl
946 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
948 def : Pat<(v4f64 (X86vzmovl
949 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
950 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
954 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
955 (VMOVUPSYmr addr:$dst, VR256:$src)>;
956 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
957 (VMOVUPDYmr addr:$dst, VR256:$src)>;
959 let SchedRW = [WriteStore] in {
960 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movaps\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
964 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movapd\t{$src, $dst|$dst, $src}",
966 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
968 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movups\t{$src, $dst|$dst, $src}",
970 [(store (v4f32 VR128:$src), addr:$dst)],
972 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
973 "movupd\t{$src, $dst|$dst, $src}",
974 [(store (v2f64 VR128:$src), addr:$dst)],
979 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
980 SchedRW = [WriteFShuffle] in {
981 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movaps\t{$src, $dst|$dst, $src}", [],
984 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movapd\t{$src, $dst|$dst, $src}", [],
987 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
988 "movups\t{$src, $dst|$dst, $src}", [],
990 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
991 "movupd\t{$src, $dst|$dst, $src}", [],
995 let Predicates = [HasAVX] in {
996 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
997 (VMOVUPSmr addr:$dst, VR128:$src)>;
998 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
999 (VMOVUPDmr addr:$dst, VR128:$src)>;
1002 let Predicates = [UseSSE1] in
1003 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1004 (MOVUPSmr addr:$dst, VR128:$src)>;
1005 let Predicates = [UseSSE2] in
1006 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1007 (MOVUPDmr addr:$dst, VR128:$src)>;
1009 // Use vmovaps/vmovups for AVX integer load/store.
1010 let Predicates = [HasAVX, NoVLX] in {
1011 // 128-bit load/store
1012 def : Pat<(alignedloadv2i64 addr:$src),
1013 (VMOVAPSrm addr:$src)>;
1014 def : Pat<(loadv2i64 addr:$src),
1015 (VMOVUPSrm addr:$src)>;
1017 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1020 (VMOVAPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1022 (VMOVAPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1024 (VMOVAPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1028 (VMOVUPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1030 (VMOVUPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1032 (VMOVUPSmr addr:$dst, VR128:$src)>;
1034 // 256-bit load/store
1035 def : Pat<(alignedloadv4i64 addr:$src),
1036 (VMOVAPSYrm addr:$src)>;
1037 def : Pat<(loadv4i64 addr:$src),
1038 (VMOVUPSYrm addr:$src)>;
1039 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1042 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1044 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1046 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1050 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1052 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1054 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1056 // Special patterns for storing subvector extracts of lower 128-bits
1057 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1058 def : Pat<(alignedstore (v2f64 (extract_subvector
1059 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1061 def : Pat<(alignedstore (v4f32 (extract_subvector
1062 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1063 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 def : Pat<(alignedstore (v2i64 (extract_subvector
1065 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1066 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1067 def : Pat<(alignedstore (v4i32 (extract_subvector
1068 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1069 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1070 def : Pat<(alignedstore (v8i16 (extract_subvector
1071 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1072 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1073 def : Pat<(alignedstore (v16i8 (extract_subvector
1074 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1075 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1077 def : Pat<(store (v2f64 (extract_subvector
1078 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1079 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1080 def : Pat<(store (v4f32 (extract_subvector
1081 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1082 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1083 def : Pat<(store (v2i64 (extract_subvector
1084 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1085 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1086 def : Pat<(store (v4i32 (extract_subvector
1087 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1088 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1089 def : Pat<(store (v8i16 (extract_subvector
1090 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1091 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1092 def : Pat<(store (v16i8 (extract_subvector
1093 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1094 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1097 // Use movaps / movups for SSE integer load / store (one byte shorter).
1098 // The instructions selected below are then converted to MOVDQA/MOVDQU
1099 // during the SSE domain pass.
1100 let Predicates = [UseSSE1] in {
1101 def : Pat<(alignedloadv2i64 addr:$src),
1102 (MOVAPSrm addr:$src)>;
1103 def : Pat<(loadv2i64 addr:$src),
1104 (MOVUPSrm addr:$src)>;
1106 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1107 (MOVAPSmr addr:$dst, VR128:$src)>;
1108 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1109 (MOVAPSmr addr:$dst, VR128:$src)>;
1110 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1111 (MOVAPSmr addr:$dst, VR128:$src)>;
1112 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1113 (MOVAPSmr addr:$dst, VR128:$src)>;
1114 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1115 (MOVUPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1117 (MOVUPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1119 (MOVUPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1121 (MOVUPSmr addr:$dst, VR128:$src)>;
1124 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1125 // bits are disregarded. FIXME: Set encoding to pseudo!
1126 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1127 let isCodeGenOnly = 1 in {
1128 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1129 "movaps\t{$src, $dst|$dst, $src}",
1130 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1131 IIC_SSE_MOVA_P_RM>, VEX;
1132 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1133 "movapd\t{$src, $dst|$dst, $src}",
1134 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1135 IIC_SSE_MOVA_P_RM>, VEX;
1136 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1137 "movaps\t{$src, $dst|$dst, $src}",
1138 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1140 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1141 "movapd\t{$src, $dst|$dst, $src}",
1142 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1147 //===----------------------------------------------------------------------===//
1148 // SSE 1 & 2 - Move Low packed FP Instructions
1149 //===----------------------------------------------------------------------===//
1151 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1152 string base_opc, string asm_opr,
1153 InstrItinClass itin> {
1154 def PSrm : PI<opc, MRMSrcMem,
1155 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1156 !strconcat(base_opc, "s", asm_opr),
1158 (psnode VR128:$src1,
1159 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1160 itin, SSEPackedSingle>, PS,
1161 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1163 def PDrm : PI<opc, MRMSrcMem,
1164 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1165 !strconcat(base_opc, "d", asm_opr),
1166 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1167 (scalar_to_vector (loadf64 addr:$src2)))))],
1168 itin, SSEPackedDouble>, PD,
1169 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1173 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1174 string base_opc, InstrItinClass itin> {
1175 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1176 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1179 let Constraints = "$src1 = $dst" in
1180 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1181 "\t{$src2, $dst|$dst, $src2}",
1185 let AddedComplexity = 20 in {
1186 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1190 let SchedRW = [WriteStore] in {
1191 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1192 "movlps\t{$src, $dst|$dst, $src}",
1193 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1194 (iPTR 0))), addr:$dst)],
1195 IIC_SSE_MOV_LH>, VEX;
1196 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1197 "movlpd\t{$src, $dst|$dst, $src}",
1198 [(store (f64 (vector_extract (v2f64 VR128:$src),
1199 (iPTR 0))), addr:$dst)],
1200 IIC_SSE_MOV_LH>, VEX;
1201 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1202 "movlps\t{$src, $dst|$dst, $src}",
1203 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1204 (iPTR 0))), addr:$dst)],
1206 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1207 "movlpd\t{$src, $dst|$dst, $src}",
1208 [(store (f64 (vector_extract (v2f64 VR128:$src),
1209 (iPTR 0))), addr:$dst)],
1213 let Predicates = [HasAVX] in {
1214 // Shuffle with VMOVLPS
1215 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1216 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1218 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1220 // Shuffle with VMOVLPD
1221 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1222 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1223 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1224 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1226 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1227 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1232 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1233 def : Pat<(store (v4i32 (X86Movlps
1234 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1235 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1236 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1238 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1239 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1241 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1244 let Predicates = [UseSSE1] in {
1245 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1246 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1247 (iPTR 0))), addr:$src1),
1248 (MOVLPSmr addr:$src1, VR128:$src2)>;
1250 // Shuffle with MOVLPS
1251 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1252 (MOVLPSrm VR128:$src1, addr:$src2)>;
1253 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1254 (MOVLPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(X86Movlps VR128:$src1,
1256 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1257 (MOVLPSrm VR128:$src1, addr:$src2)>;
1260 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1262 (MOVLPSmr addr:$src1, VR128:$src2)>;
1263 def : Pat<(store (v4i32 (X86Movlps
1264 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1266 (MOVLPSmr addr:$src1, VR128:$src2)>;
1269 let Predicates = [UseSSE2] in {
1270 // Shuffle with MOVLPD
1271 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1272 (MOVLPDrm VR128:$src1, addr:$src2)>;
1273 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1274 (MOVLPDrm VR128:$src1, addr:$src2)>;
1275 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1276 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1277 (MOVLPDrm VR128:$src1, addr:$src2)>;
1280 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1282 (MOVLPDmr addr:$src1, VR128:$src2)>;
1283 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1285 (MOVLPDmr addr:$src1, VR128:$src2)>;
1288 //===----------------------------------------------------------------------===//
1289 // SSE 1 & 2 - Move Hi packed FP Instructions
1290 //===----------------------------------------------------------------------===//
1292 let AddedComplexity = 20 in {
1293 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1297 let SchedRW = [WriteStore] in {
1298 // v2f64 extract element 1 is always custom lowered to unpack high to low
1299 // and extract element 0 so the non-store version isn't too horrible.
1300 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1301 "movhps\t{$src, $dst|$dst, $src}",
1302 [(store (f64 (vector_extract
1303 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1304 (bc_v2f64 (v4f32 VR128:$src))),
1305 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1306 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1307 "movhpd\t{$src, $dst|$dst, $src}",
1308 [(store (f64 (vector_extract
1309 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1310 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1311 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1312 "movhps\t{$src, $dst|$dst, $src}",
1313 [(store (f64 (vector_extract
1314 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1315 (bc_v2f64 (v4f32 VR128:$src))),
1316 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1317 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1318 "movhpd\t{$src, $dst|$dst, $src}",
1319 [(store (f64 (vector_extract
1320 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1321 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1324 let Predicates = [HasAVX] in {
1326 def : Pat<(X86Movlhps VR128:$src1,
1327 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1328 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1329 def : Pat<(X86Movlhps VR128:$src1,
1330 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1331 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1335 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1336 // is during lowering, where it's not possible to recognize the load fold
1337 // cause it has two uses through a bitcast. One use disappears at isel time
1338 // and the fold opportunity reappears.
1339 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1340 (scalar_to_vector (loadf64 addr:$src2)))),
1341 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1342 // Also handle an i64 load because that may get selected as a faster way to
1344 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1345 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1346 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1348 def : Pat<(store (f64 (vector_extract
1349 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1350 (iPTR 0))), addr:$dst),
1351 (VMOVHPDmr addr:$dst, VR128:$src)>;
1354 let Predicates = [UseSSE1] in {
1356 def : Pat<(X86Movlhps VR128:$src1,
1357 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1358 (MOVHPSrm VR128:$src1, addr:$src2)>;
1359 def : Pat<(X86Movlhps VR128:$src1,
1360 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1361 (MOVHPSrm VR128:$src1, addr:$src2)>;
1364 let Predicates = [UseSSE2] in {
1367 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1368 // is during lowering, where it's not possible to recognize the load fold
1369 // cause it has two uses through a bitcast. One use disappears at isel time
1370 // and the fold opportunity reappears.
1371 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1372 (scalar_to_vector (loadf64 addr:$src2)))),
1373 (MOVHPDrm VR128:$src1, addr:$src2)>;
1374 // Also handle an i64 load because that may get selected as a faster way to
1376 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1377 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1378 (MOVHPDrm VR128:$src1, addr:$src2)>;
1380 def : Pat<(store (f64 (vector_extract
1381 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1382 (iPTR 0))), addr:$dst),
1383 (MOVHPDmr addr:$dst, VR128:$src)>;
1386 //===----------------------------------------------------------------------===//
1387 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1388 //===----------------------------------------------------------------------===//
1390 let AddedComplexity = 20, Predicates = [UseAVX] in {
1391 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1392 (ins VR128:$src1, VR128:$src2),
1393 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1395 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1397 VEX_4V, Sched<[WriteFShuffle]>;
1398 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1399 (ins VR128:$src1, VR128:$src2),
1400 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1402 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1404 VEX_4V, Sched<[WriteFShuffle]>;
1406 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1407 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1408 (ins VR128:$src1, VR128:$src2),
1409 "movlhps\t{$src2, $dst|$dst, $src2}",
1411 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1412 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1413 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1414 (ins VR128:$src1, VR128:$src2),
1415 "movhlps\t{$src2, $dst|$dst, $src2}",
1417 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1418 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1421 let Predicates = [UseAVX] in {
1423 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1424 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1425 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1426 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1429 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1430 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1433 let Predicates = [UseSSE1] in {
1435 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1436 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1437 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1438 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1441 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1442 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1445 //===----------------------------------------------------------------------===//
1446 // SSE 1 & 2 - Conversion Instructions
1447 //===----------------------------------------------------------------------===//
1449 def SSE_CVT_PD : OpndItins<
1450 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1453 let Sched = WriteCvtI2F in
1454 def SSE_CVT_PS : OpndItins<
1455 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1458 let Sched = WriteCvtI2F in
1459 def SSE_CVT_Scalar : OpndItins<
1460 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1463 let Sched = WriteCvtF2I in
1464 def SSE_CVT_SS2SI_32 : OpndItins<
1465 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1468 let Sched = WriteCvtF2I in
1469 def SSE_CVT_SS2SI_64 : OpndItins<
1470 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1473 let Sched = WriteCvtF2I in
1474 def SSE_CVT_SD2SI : OpndItins<
1475 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1478 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1479 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1480 string asm, OpndItins itins> {
1481 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1482 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1483 itins.rr>, Sched<[itins.Sched]>;
1484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1485 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1486 itins.rm>, Sched<[itins.Sched.Folded]>;
1489 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1490 X86MemOperand x86memop, string asm, Domain d,
1492 let hasSideEffects = 0 in {
1493 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1494 [], itins.rr, d>, Sched<[itins.Sched]>;
1496 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1497 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1501 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1502 X86MemOperand x86memop, string asm> {
1503 let hasSideEffects = 0, Predicates = [UseAVX] in {
1504 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1505 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1506 Sched<[WriteCvtI2F]>;
1508 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1509 (ins DstRC:$src1, x86memop:$src),
1510 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1511 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1512 } // hasSideEffects = 0
1515 let Predicates = [UseAVX] in {
1516 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1517 "cvttss2si\t{$src, $dst|$dst, $src}",
1520 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1521 "cvttss2si\t{$src, $dst|$dst, $src}",
1523 XS, VEX, VEX_W, VEX_LIG;
1524 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1525 "cvttsd2si\t{$src, $dst|$dst, $src}",
1528 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1529 "cvttsd2si\t{$src, $dst|$dst, $src}",
1531 XD, VEX, VEX_W, VEX_LIG;
1533 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1534 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1535 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1536 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1537 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1538 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1539 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1540 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1541 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1542 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1543 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1545 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1550 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1551 // register, but the same isn't true when only using memory operands,
1552 // provide other assembly "l" and "q" forms to address this explicitly
1553 // where appropriate to do so.
1554 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1555 XS, VEX_4V, VEX_LIG;
1556 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1557 XS, VEX_4V, VEX_W, VEX_LIG;
1558 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1559 XD, VEX_4V, VEX_LIG;
1560 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1561 XD, VEX_4V, VEX_W, VEX_LIG;
1563 let Predicates = [UseAVX] in {
1564 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1565 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1566 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1567 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1569 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1570 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1571 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1572 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1573 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1574 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1575 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1576 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1578 def : Pat<(f32 (sint_to_fp GR32:$src)),
1579 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1580 def : Pat<(f32 (sint_to_fp GR64:$src)),
1581 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1582 def : Pat<(f64 (sint_to_fp GR32:$src)),
1583 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1584 def : Pat<(f64 (sint_to_fp GR64:$src)),
1585 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1588 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1589 "cvttss2si\t{$src, $dst|$dst, $src}",
1590 SSE_CVT_SS2SI_32>, XS;
1591 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1592 "cvttss2si\t{$src, $dst|$dst, $src}",
1593 SSE_CVT_SS2SI_64>, XS, REX_W;
1594 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1595 "cvttsd2si\t{$src, $dst|$dst, $src}",
1597 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1598 "cvttsd2si\t{$src, $dst|$dst, $src}",
1599 SSE_CVT_SD2SI>, XD, REX_W;
1600 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1601 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1602 SSE_CVT_Scalar>, XS;
1603 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1604 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1605 SSE_CVT_Scalar>, XS, REX_W;
1606 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1607 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1608 SSE_CVT_Scalar>, XD;
1609 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1610 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1611 SSE_CVT_Scalar>, XD, REX_W;
1613 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1614 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1615 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1616 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1617 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1618 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1619 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1620 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1621 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1622 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1623 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1625 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1626 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1627 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1630 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1631 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1632 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1633 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1635 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1636 // and/or XMM operand(s).
1638 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1639 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1640 string asm, OpndItins itins> {
1641 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1642 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1643 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1644 Sched<[itins.Sched]>;
1645 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1646 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1647 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1648 Sched<[itins.Sched.Folded]>;
1651 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1652 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1653 PatFrag ld_frag, string asm, OpndItins itins,
1655 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1657 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1658 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1659 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1660 itins.rr>, Sched<[itins.Sched]>;
1661 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1662 (ins DstRC:$src1, x86memop:$src2),
1664 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1665 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1666 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1667 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1670 let Predicates = [UseAVX] in {
1671 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1672 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1673 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1674 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1675 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1676 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1678 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1679 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1680 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1681 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1684 let isCodeGenOnly = 1 in {
1685 let Predicates = [UseAVX] in {
1686 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1687 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1688 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1689 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1690 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1691 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1693 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1694 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1695 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1696 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1697 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1698 SSE_CVT_Scalar, 0>, XD,
1701 let Constraints = "$src1 = $dst" in {
1702 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1703 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1704 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1705 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1706 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1707 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1708 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1709 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1710 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1711 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1712 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1713 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1715 } // isCodeGenOnly = 1
1719 // Aliases for intrinsics
1720 let isCodeGenOnly = 1 in {
1721 let Predicates = [UseAVX] in {
1722 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1723 ssmem, sse_load_f32, "cvttss2si",
1724 SSE_CVT_SS2SI_32>, XS, VEX;
1725 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1726 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1727 "cvttss2si", SSE_CVT_SS2SI_64>,
1729 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1730 sdmem, sse_load_f64, "cvttsd2si",
1731 SSE_CVT_SD2SI>, XD, VEX;
1732 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1733 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1734 "cvttsd2si", SSE_CVT_SD2SI>,
1737 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1738 ssmem, sse_load_f32, "cvttss2si",
1739 SSE_CVT_SS2SI_32>, XS;
1740 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1741 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1742 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1743 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1744 sdmem, sse_load_f64, "cvttsd2si",
1746 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1747 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1748 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1749 } // isCodeGenOnly = 1
1751 let Predicates = [UseAVX] in {
1752 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1753 ssmem, sse_load_f32, "cvtss2si",
1754 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1755 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1756 ssmem, sse_load_f32, "cvtss2si",
1757 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1759 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1760 ssmem, sse_load_f32, "cvtss2si",
1761 SSE_CVT_SS2SI_32>, XS;
1762 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1763 ssmem, sse_load_f32, "cvtss2si",
1764 SSE_CVT_SS2SI_64>, XS, REX_W;
1766 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1767 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1768 SSEPackedSingle, SSE_CVT_PS>,
1769 PS, VEX, Requires<[HasAVX]>;
1770 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1771 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1772 SSEPackedSingle, SSE_CVT_PS>,
1773 PS, VEX, VEX_L, Requires<[HasAVX]>;
1775 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1776 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1777 SSEPackedSingle, SSE_CVT_PS>,
1778 PS, Requires<[UseSSE2]>;
1780 let Predicates = [UseAVX] in {
1781 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1782 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1783 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1784 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1785 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1786 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1787 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1788 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1789 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1790 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1791 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1793 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1794 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1799 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1800 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1801 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1802 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1803 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1804 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1805 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1806 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1807 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1808 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1809 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1811 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1812 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1813 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1818 // Convert scalar double to scalar single
1819 let hasSideEffects = 0, Predicates = [UseAVX] in {
1820 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1821 (ins FR64:$src1, FR64:$src2),
1822 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1823 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1824 Sched<[WriteCvtF2F]>;
1826 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1827 (ins FR64:$src1, f64mem:$src2),
1828 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1829 [], IIC_SSE_CVT_Scalar_RM>,
1830 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1831 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1834 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1837 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1838 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1839 [(set FR32:$dst, (fround FR64:$src))],
1840 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1841 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1842 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1843 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1844 IIC_SSE_CVT_Scalar_RM>,
1846 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1848 let isCodeGenOnly = 1 in {
1849 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1850 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1851 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1853 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1854 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,
1855 Sched<[WriteCvtF2F]>;
1856 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1857 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1858 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1859 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1860 VR128:$src1, sse_load_f64:$src2))],
1861 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>,
1862 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1864 let Constraints = "$src1 = $dst" in {
1865 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1866 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1867 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1869 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1870 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1871 Sched<[WriteCvtF2F]>;
1872 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1873 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1874 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1875 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1876 VR128:$src1, sse_load_f64:$src2))],
1877 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1878 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1880 } // isCodeGenOnly = 1
1882 // Convert scalar single to scalar double
1883 // SSE2 instructions with XS prefix
1884 let hasSideEffects = 0, Predicates = [UseAVX] in {
1885 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1886 (ins FR32:$src1, FR32:$src2),
1887 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1888 [], IIC_SSE_CVT_Scalar_RR>,
1889 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1890 Sched<[WriteCvtF2F]>;
1892 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1893 (ins FR32:$src1, f32mem:$src2),
1894 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1895 [], IIC_SSE_CVT_Scalar_RM>,
1896 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1897 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1900 def : Pat<(f64 (fextend FR32:$src)),
1901 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1902 def : Pat<(fextend (loadf32 addr:$src)),
1903 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1905 def : Pat<(extloadf32 addr:$src),
1906 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1907 Requires<[UseAVX, OptForSize]>;
1908 def : Pat<(extloadf32 addr:$src),
1909 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1910 Requires<[UseAVX, OptForSpeed]>;
1912 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1913 "cvtss2sd\t{$src, $dst|$dst, $src}",
1914 [(set FR64:$dst, (fextend FR32:$src))],
1915 IIC_SSE_CVT_Scalar_RR>, XS,
1916 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1917 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1918 "cvtss2sd\t{$src, $dst|$dst, $src}",
1919 [(set FR64:$dst, (extloadf32 addr:$src))],
1920 IIC_SSE_CVT_Scalar_RM>, XS,
1921 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1923 // extload f32 -> f64. This matches load+fextend because we have a hack in
1924 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1926 // Since these loads aren't folded into the fextend, we have to match it
1928 def : Pat<(fextend (loadf32 addr:$src)),
1929 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1930 def : Pat<(extloadf32 addr:$src),
1931 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1933 let isCodeGenOnly = 1 in {
1934 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1935 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1936 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1938 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1939 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>,
1940 Sched<[WriteCvtF2F]>;
1941 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1942 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1943 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1945 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1946 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>,
1947 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1948 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1949 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1950 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1951 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1953 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1954 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1955 Sched<[WriteCvtF2F]>;
1956 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1957 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1958 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1960 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1961 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1962 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1964 } // isCodeGenOnly = 1
1966 // Convert packed single/double fp to doubleword
1967 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1968 "cvtps2dq\t{$src, $dst|$dst, $src}",
1969 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1970 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1971 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1972 "cvtps2dq\t{$src, $dst|$dst, $src}",
1974 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1975 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1976 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1977 "cvtps2dq\t{$src, $dst|$dst, $src}",
1979 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1980 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1981 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1982 "cvtps2dq\t{$src, $dst|$dst, $src}",
1984 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1985 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1986 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 "cvtps2dq\t{$src, $dst|$dst, $src}",
1988 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1989 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1990 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1991 "cvtps2dq\t{$src, $dst|$dst, $src}",
1993 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1994 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1997 // Convert Packed Double FP to Packed DW Integers
1998 let Predicates = [HasAVX] in {
1999 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2000 // register, but the same isn't true when using memory operands instead.
2001 // Provide other assembly rr and rm forms to address this explicitly.
2002 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2003 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2004 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2005 VEX, Sched<[WriteCvtF2I]>;
2008 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2009 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2010 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2011 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2013 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2014 Sched<[WriteCvtF2ILd]>;
2017 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2018 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2020 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2021 Sched<[WriteCvtF2I]>;
2022 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2023 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2025 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2026 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2027 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2028 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2031 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2032 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2034 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2035 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2036 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2037 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2038 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2039 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2041 // Convert with truncation packed single/double fp to doubleword
2042 // SSE2 packed instructions with XS prefix
2043 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "cvttps2dq\t{$src, $dst|$dst, $src}",
2046 (int_x86_sse2_cvttps2dq VR128:$src))],
2047 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2048 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2049 "cvttps2dq\t{$src, $dst|$dst, $src}",
2050 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2051 (loadv4f32 addr:$src)))],
2052 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2053 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2054 "cvttps2dq\t{$src, $dst|$dst, $src}",
2056 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2057 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2058 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2059 "cvttps2dq\t{$src, $dst|$dst, $src}",
2060 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2061 (loadv8f32 addr:$src)))],
2062 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2063 Sched<[WriteCvtF2ILd]>;
2065 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2066 "cvttps2dq\t{$src, $dst|$dst, $src}",
2067 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2068 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2069 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2070 "cvttps2dq\t{$src, $dst|$dst, $src}",
2072 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2073 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2075 let Predicates = [HasAVX] in {
2076 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2077 (VCVTDQ2PSrr VR128:$src)>;
2078 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2079 (VCVTDQ2PSrm addr:$src)>;
2082 let Predicates = [HasAVX, NoVLX] in {
2083 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2084 (VCVTDQ2PSrr VR128:$src)>;
2085 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2086 (VCVTDQ2PSrm addr:$src)>;
2088 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2089 (VCVTTPS2DQrr VR128:$src)>;
2090 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2091 (VCVTTPS2DQrm addr:$src)>;
2093 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2094 (VCVTDQ2PSYrr VR256:$src)>;
2095 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2096 (VCVTDQ2PSYrm addr:$src)>;
2098 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2099 (VCVTTPS2DQYrr VR256:$src)>;
2100 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2101 (VCVTTPS2DQYrm addr:$src)>;
2104 let Predicates = [UseSSE2] in {
2105 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2106 (CVTDQ2PSrr VR128:$src)>;
2107 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2108 (CVTDQ2PSrm addr:$src)>;
2110 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2111 (CVTDQ2PSrr VR128:$src)>;
2112 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2113 (CVTDQ2PSrm addr:$src)>;
2115 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2116 (CVTTPS2DQrr VR128:$src)>;
2117 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2118 (CVTTPS2DQrm addr:$src)>;
2121 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2122 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2124 (int_x86_sse2_cvttpd2dq VR128:$src))],
2125 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2127 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2128 // register, but the same isn't true when using memory operands instead.
2129 // Provide other assembly rr and rm forms to address this explicitly.
2132 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2133 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2134 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2135 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2136 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2137 (loadv2f64 addr:$src)))],
2138 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2141 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2142 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2144 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2145 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2146 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2147 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2149 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2150 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2151 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2152 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2154 let Predicates = [HasAVX, NoVLX] in {
2155 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2156 (VCVTTPD2DQYrr VR256:$src)>;
2157 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2158 (VCVTTPD2DQYrm addr:$src)>;
2159 } // Predicates = [HasAVX]
2161 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2162 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2163 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2164 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2165 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2166 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2167 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2168 (memopv2f64 addr:$src)))],
2170 Sched<[WriteCvtF2ILd]>;
2172 // Convert packed single to packed double
2173 let Predicates = [HasAVX] in {
2174 // SSE2 instructions without OpSize prefix
2175 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2176 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2177 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2178 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2179 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2180 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2181 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2182 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2183 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2184 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2186 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2187 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2188 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2189 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2191 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2192 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2195 let Predicates = [UseSSE2] in {
2196 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2197 "cvtps2pd\t{$src, $dst|$dst, $src}",
2198 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2199 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2200 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2201 "cvtps2pd\t{$src, $dst|$dst, $src}",
2202 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2203 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2206 // Convert Packed DW Integers to Packed Double FP
2207 let Predicates = [HasAVX] in {
2208 let hasSideEffects = 0, mayLoad = 1 in
2209 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2210 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2211 []>, VEX, Sched<[WriteCvtI2FLd]>;
2212 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2213 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2215 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2216 Sched<[WriteCvtI2F]>;
2217 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2218 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2220 (int_x86_avx_cvtdq2_pd_256
2221 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2222 Sched<[WriteCvtI2FLd]>;
2223 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2224 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2226 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2227 Sched<[WriteCvtI2F]>;
2230 let hasSideEffects = 0, mayLoad = 1 in
2231 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2232 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2233 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2234 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2235 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2236 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2237 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2239 // AVX register conversion intrinsics
2240 let Predicates = [HasAVX] in {
2241 def : Pat<(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))),
2242 (VCVTDQ2PDrr VR128:$src)>;
2243 def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))),
2244 (VCVTDQ2PDrm addr:$src)>;
2246 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2247 (VCVTDQ2PDYrr VR128:$src)>;
2248 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2249 (VCVTDQ2PDYrm addr:$src)>;
2250 } // Predicates = [HasAVX]
2252 // SSE2 register conversion intrinsics
2253 let Predicates = [HasSSE2] in {
2254 def : Pat<(v2f64 (X86cvtdq2pd (v4i32 VR128:$src))),
2255 (CVTDQ2PDrr VR128:$src)>;
2256 def : Pat<(v2f64 (X86cvtdq2pd (bc_v4i32 (loadv2i64 addr:$src)))),
2257 (CVTDQ2PDrm addr:$src)>;
2258 } // Predicates = [HasSSE2]
2260 // Convert packed double to packed single
2261 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2262 // register, but the same isn't true when using memory operands instead.
2263 // Provide other assembly rr and rm forms to address this explicitly.
2264 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2265 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2266 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2267 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2270 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2271 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2272 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2273 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2275 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2276 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2279 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2280 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2282 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2283 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2284 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2285 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2287 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2288 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2289 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2290 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2292 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2293 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2294 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2295 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2296 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2297 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2299 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2300 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2303 // AVX 256-bit register conversion intrinsics
2304 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2305 // whenever possible to avoid declaring two versions of each one.
2306 let Predicates = [HasAVX] in {
2307 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2308 (VCVTDQ2PSYrr VR256:$src)>;
2309 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2310 (VCVTDQ2PSYrm addr:$src)>;
2313 let Predicates = [HasAVX, NoVLX] in {
2314 // Match fround and fextend for 128/256-bit conversions
2315 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2316 (VCVTPD2PSrr VR128:$src)>;
2317 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2318 (VCVTPD2PSXrm addr:$src)>;
2319 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2320 (VCVTPD2PSYrr VR256:$src)>;
2321 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2322 (VCVTPD2PSYrm addr:$src)>;
2324 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2325 (VCVTPS2PDrr VR128:$src)>;
2326 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2327 (VCVTPS2PDYrr VR128:$src)>;
2328 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2329 (VCVTPS2PDYrm addr:$src)>;
2332 let Predicates = [UseSSE2] in {
2333 // Match fround and fextend for 128 conversions
2334 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2335 (CVTPD2PSrr VR128:$src)>;
2336 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2337 (CVTPD2PSrm addr:$src)>;
2339 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2340 (CVTPS2PDrr VR128:$src)>;
2343 //===----------------------------------------------------------------------===//
2344 // SSE 1 & 2 - Compare Instructions
2345 //===----------------------------------------------------------------------===//
2347 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2348 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2349 Operand CC, SDNode OpNode, ValueType VT,
2350 PatFrag ld_frag, string asm, string asm_alt,
2351 OpndItins itins, ImmLeaf immLeaf> {
2352 def rr : SIi8<0xC2, MRMSrcReg,
2353 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2354 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))],
2355 itins.rr>, Sched<[itins.Sched]>;
2356 def rm : SIi8<0xC2, MRMSrcMem,
2357 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2358 [(set RC:$dst, (OpNode (VT RC:$src1),
2359 (ld_frag addr:$src2), immLeaf:$cc))],
2361 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2363 // Accept explicit immediate argument form instead of comparison code.
2364 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2365 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2366 (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, [],
2367 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2369 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2370 (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, [],
2371 IIC_SSE_ALU_F32S_RM>,
2372 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2376 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2377 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2378 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2379 SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG;
2380 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2381 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2382 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2383 SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare
2384 XD, VEX_4V, VEX_LIG;
2386 let Constraints = "$src1 = $dst" in {
2387 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2388 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2389 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S,
2391 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2392 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2393 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2394 SSE_ALU_F64S, i8immZExt3>, XD;
2397 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2398 Intrinsic Int, string asm, OpndItins itins,
2400 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2401 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2402 [(set VR128:$dst, (Int VR128:$src1,
2403 VR128:$src, immLeaf:$cc))],
2405 Sched<[itins.Sched]>;
2406 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2407 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2408 [(set VR128:$dst, (Int VR128:$src1,
2409 (load addr:$src), immLeaf:$cc))],
2411 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2414 let isCodeGenOnly = 1 in {
2415 // Aliases to match intrinsics which expect XMM operand(s).
2416 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2417 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2418 SSE_ALU_F32S, i8immZExt5>,
2420 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2421 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2422 SSE_ALU_F32S, i8immZExt5>, // same latency as f32
2424 let Constraints = "$src1 = $dst" in {
2425 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2426 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2427 SSE_ALU_F32S, i8immZExt3>, XS;
2428 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2429 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2430 SSE_ALU_F64S, i8immZExt3>,
2436 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2437 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2438 ValueType vt, X86MemOperand x86memop,
2439 PatFrag ld_frag, string OpcodeStr> {
2440 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2441 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2442 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2445 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2446 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2447 [(set EFLAGS, (OpNode (vt RC:$src1),
2448 (ld_frag addr:$src2)))],
2450 Sched<[WriteFAddLd, ReadAfterLd]>;
2453 let Defs = [EFLAGS] in {
2454 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2455 "ucomiss">, PS, VEX, VEX_LIG;
2456 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2457 "ucomisd">, PD, VEX, VEX_LIG;
2458 let Pattern = []<dag> in {
2459 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2460 "comiss">, PS, VEX, VEX_LIG;
2461 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2462 "comisd">, PD, VEX, VEX_LIG;
2465 let isCodeGenOnly = 1 in {
2466 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2467 load, "ucomiss">, PS, VEX;
2468 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2469 load, "ucomisd">, PD, VEX;
2471 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2472 load, "comiss">, PS, VEX;
2473 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2474 load, "comisd">, PD, VEX;
2476 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2478 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2481 let Pattern = []<dag> in {
2482 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2484 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2488 let isCodeGenOnly = 1 in {
2489 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2490 load, "ucomiss">, PS;
2491 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2492 load, "ucomisd">, PD;
2494 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2496 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2499 } // Defs = [EFLAGS]
2501 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2502 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2503 Operand CC, Intrinsic Int, string asm,
2504 string asm_alt, Domain d, ImmLeaf immLeaf,
2505 PatFrag ld_frag, OpndItins itins = SSE_ALU_F32P> {
2506 let isCommutable = 1 in
2507 def rri : PIi8<0xC2, MRMSrcReg,
2508 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2509 [(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
2512 def rmi : PIi8<0xC2, MRMSrcMem,
2513 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2514 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2), immLeaf:$cc))],
2516 Sched<[WriteFAddLd, ReadAfterLd]>;
2518 // Accept explicit immediate argument form instead of comparison code.
2519 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2520 def rri_alt : PIi8<0xC2, MRMSrcReg,
2521 (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
2522 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2524 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2525 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
2526 asm_alt, [], itins.rm, d>,
2527 Sched<[WriteFAddLd, ReadAfterLd]>;
2531 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2532 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2533 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2534 SSEPackedSingle, i8immZExt5, loadv4f32>, PS, VEX_4V;
2535 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2536 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2537 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2538 SSEPackedDouble, i8immZExt5, loadv2f64>, PD, VEX_4V;
2539 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2540 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2541 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2542 SSEPackedSingle, i8immZExt5, loadv8f32>, PS, VEX_4V, VEX_L;
2543 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2544 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2545 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2546 SSEPackedDouble, i8immZExt5, loadv4f64>, PD, VEX_4V, VEX_L;
2547 let Constraints = "$src1 = $dst" in {
2548 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2549 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2550 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2551 SSEPackedSingle, i8immZExt5, memopv4f32, SSE_ALU_F32P>, PS;
2552 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2553 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2554 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2555 SSEPackedDouble, i8immZExt5, memopv2f64, SSE_ALU_F64P>, PD;
2558 let Predicates = [HasAVX] in {
2559 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2560 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2561 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (loadv4f32 addr:$src2), imm:$cc)),
2562 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2563 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2564 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2565 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (loadv2f64 addr:$src2), imm:$cc)),
2566 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2568 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2569 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2570 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (loadv8f32 addr:$src2), imm:$cc)),
2571 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2572 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2573 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2574 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (loadv4f64 addr:$src2), imm:$cc)),
2575 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2578 let Predicates = [UseSSE1] in {
2579 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2580 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2581 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memopv4f32 addr:$src2), imm:$cc)),
2582 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2585 let Predicates = [UseSSE2] in {
2586 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2587 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2588 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memopv2f64 addr:$src2), imm:$cc)),
2589 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2592 //===----------------------------------------------------------------------===//
2593 // SSE 1 & 2 - Shuffle Instructions
2594 //===----------------------------------------------------------------------===//
2596 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2597 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2598 ValueType vt, string asm, PatFrag mem_frag,
2600 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2601 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2602 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2603 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2604 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2605 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2606 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2607 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2608 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2609 Sched<[WriteFShuffle]>;
2612 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2613 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2614 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2615 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2616 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2617 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2618 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2619 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2620 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2621 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2622 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2623 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2625 let Constraints = "$src1 = $dst" in {
2626 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2627 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2628 memopv4f32, SSEPackedSingle>, PS;
2629 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2630 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2631 memopv2f64, SSEPackedDouble>, PD;
2634 let Predicates = [HasAVX] in {
2635 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2636 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2637 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2638 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2639 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2641 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2642 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2643 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2644 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2645 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2648 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2649 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2650 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2651 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2652 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2654 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2655 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2656 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2657 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2658 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2661 let Predicates = [UseSSE1] in {
2662 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2663 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2664 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2665 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2666 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2669 let Predicates = [UseSSE2] in {
2670 // Generic SHUFPD patterns
2671 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2672 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2673 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2674 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2675 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2678 //===----------------------------------------------------------------------===//
2679 // SSE 1 & 2 - Unpack FP Instructions
2680 //===----------------------------------------------------------------------===//
2682 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2683 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2684 PatFrag mem_frag, RegisterClass RC,
2685 X86MemOperand x86memop, string asm,
2687 def rr : PI<opc, MRMSrcReg,
2688 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2690 (vt (OpNode RC:$src1, RC:$src2)))],
2691 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2692 def rm : PI<opc, MRMSrcMem,
2693 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2695 (vt (OpNode RC:$src1,
2696 (mem_frag addr:$src2))))],
2698 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2701 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2702 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2703 SSEPackedSingle>, PS, VEX_4V;
2704 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2705 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2706 SSEPackedDouble>, PD, VEX_4V;
2707 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2708 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2709 SSEPackedSingle>, PS, VEX_4V;
2710 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2711 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2712 SSEPackedDouble>, PD, VEX_4V;
2714 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2715 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2716 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2717 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2718 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2719 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2720 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2721 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2722 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2723 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2724 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2725 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2727 let Constraints = "$src1 = $dst" in {
2728 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2729 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2730 SSEPackedSingle>, PS;
2731 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2732 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2733 SSEPackedDouble>, PD;
2734 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2735 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2736 SSEPackedSingle>, PS;
2737 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2738 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2739 SSEPackedDouble>, PD;
2740 } // Constraints = "$src1 = $dst"
2742 let Predicates = [HasAVX1Only] in {
2743 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2744 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2745 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2746 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2747 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2748 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2749 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2750 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2752 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2753 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2754 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2755 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2756 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2757 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2758 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2759 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2762 //===----------------------------------------------------------------------===//
2763 // SSE 1 & 2 - Extract Floating-Point Sign mask
2764 //===----------------------------------------------------------------------===//
2766 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2767 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2769 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2770 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2771 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2772 Sched<[WriteVecLogic]>;
2775 let Predicates = [HasAVX] in {
2776 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2777 "movmskps", SSEPackedSingle>, PS, VEX;
2778 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2779 "movmskpd", SSEPackedDouble>, PD, VEX;
2780 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2781 "movmskps", SSEPackedSingle>, PS,
2783 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2784 "movmskpd", SSEPackedDouble>, PD,
2787 def : Pat<(i32 (X86fgetsign FR32:$src)),
2788 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2789 def : Pat<(i64 (X86fgetsign FR32:$src)),
2790 (SUBREG_TO_REG (i64 0),
2791 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2792 def : Pat<(i32 (X86fgetsign FR64:$src)),
2793 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2794 def : Pat<(i64 (X86fgetsign FR64:$src)),
2795 (SUBREG_TO_REG (i64 0),
2796 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2799 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2800 SSEPackedSingle>, PS;
2801 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2802 SSEPackedDouble>, PD;
2804 def : Pat<(i32 (X86fgetsign FR32:$src)),
2805 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2806 Requires<[UseSSE1]>;
2807 def : Pat<(i64 (X86fgetsign FR32:$src)),
2808 (SUBREG_TO_REG (i64 0),
2809 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2810 Requires<[UseSSE1]>;
2811 def : Pat<(i32 (X86fgetsign FR64:$src)),
2812 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2813 Requires<[UseSSE2]>;
2814 def : Pat<(i64 (X86fgetsign FR64:$src)),
2815 (SUBREG_TO_REG (i64 0),
2816 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2817 Requires<[UseSSE2]>;
2819 //===---------------------------------------------------------------------===//
2820 // SSE2 - Packed Integer Logical Instructions
2821 //===---------------------------------------------------------------------===//
2823 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2825 /// PDI_binop_rm - Simple SSE2 binary operator.
2826 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2827 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2828 X86MemOperand x86memop, OpndItins itins,
2829 bit IsCommutable, bit Is2Addr> {
2830 let isCommutable = IsCommutable in
2831 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2832 (ins RC:$src1, RC:$src2),
2834 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2835 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2836 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2837 Sched<[itins.Sched]>;
2838 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2839 (ins RC:$src1, x86memop:$src2),
2841 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2842 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2843 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2844 (bitconvert (memop_frag addr:$src2)))))],
2846 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2848 } // ExeDomain = SSEPackedInt
2850 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2851 ValueType OpVT128, ValueType OpVT256,
2852 OpndItins itins, bit IsCommutable = 0, Predicate prd> {
2853 let Predicates = [HasAVX, prd] in
2854 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2855 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2857 let Constraints = "$src1 = $dst" in
2858 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2859 memopv2i64, i128mem, itins, IsCommutable, 1>;
2861 let Predicates = [HasAVX2, prd] in
2862 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2863 OpVT256, VR256, loadv4i64, i256mem, itins,
2864 IsCommutable, 0>, VEX_4V, VEX_L;
2867 // These are ordered here for pattern ordering requirements with the fp versions
2869 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2870 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2871 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2872 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2873 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2874 SSE_VEC_BIT_ITINS_P, 1, NoVLX>;
2875 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2876 SSE_VEC_BIT_ITINS_P, 0, NoVLX>;
2878 //===----------------------------------------------------------------------===//
2879 // SSE 1 & 2 - Logical Instructions
2880 //===----------------------------------------------------------------------===//
2882 // Multiclass for scalars using the X86 logical operation aliases for FP.
2883 multiclass sse12_fp_packed_scalar_logical_alias<
2884 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2885 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2886 FR32, f32, f128mem, loadf32_128, SSEPackedSingle, itins, 0>,
2889 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2890 FR64, f64, f128mem, loadf64_128, SSEPackedDouble, itins, 0>,
2893 let Constraints = "$src1 = $dst" in {
2894 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2895 f32, f128mem, memopfsf32_128, SSEPackedSingle, itins>, PS;
2897 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2898 f64, f128mem, memopfsf64_128, SSEPackedDouble, itins>, PD;
2902 let isCodeGenOnly = 1 in {
2903 defm FsAND : sse12_fp_packed_scalar_logical_alias<0x54, "and", X86fand,
2905 defm FsOR : sse12_fp_packed_scalar_logical_alias<0x56, "or", X86for,
2907 defm FsXOR : sse12_fp_packed_scalar_logical_alias<0x57, "xor", X86fxor,
2910 let isCommutable = 0 in
2911 defm FsANDN : sse12_fp_packed_scalar_logical_alias<0x55, "andn", X86fandn,
2915 // Multiclass for vectors using the X86 logical operation aliases for FP.
2916 multiclass sse12_fp_packed_vector_logical_alias<
2917 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2918 let Predicates = [HasAVX, NoVLX] in {
2919 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2920 VR128, v4f32, f128mem, loadv4f32, SSEPackedSingle, itins, 0>,
2923 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2924 VR128, v2f64, f128mem, loadv2f64, SSEPackedDouble, itins, 0>,
2928 let Constraints = "$src1 = $dst" in {
2929 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2930 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins>,
2933 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2934 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins>,
2939 let isCodeGenOnly = 1 in {
2940 defm FvAND : sse12_fp_packed_vector_logical_alias<0x54, "and", X86fand,
2942 defm FvOR : sse12_fp_packed_vector_logical_alias<0x56, "or", X86for,
2944 defm FvXOR : sse12_fp_packed_vector_logical_alias<0x57, "xor", X86fxor,
2947 let isCommutable = 0 in
2948 defm FvANDN : sse12_fp_packed_vector_logical_alias<0x55, "andn", X86fandn,
2952 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2954 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2956 let Predicates = [HasAVX, NoVLX] in {
2957 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2958 !strconcat(OpcodeStr, "ps"), f256mem,
2959 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2960 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2961 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2963 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2964 !strconcat(OpcodeStr, "pd"), f256mem,
2965 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2966 (bc_v4i64 (v4f64 VR256:$src2))))],
2967 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2968 (loadv4i64 addr:$src2)))], 0>,
2971 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2972 // are all promoted to v2i64, and the patterns are covered by the int
2973 // version. This is needed in SSE only, because v2i64 isn't supported on
2974 // SSE1, but only on SSE2.
2975 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2976 !strconcat(OpcodeStr, "ps"), f128mem, [],
2977 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2978 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2980 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2981 !strconcat(OpcodeStr, "pd"), f128mem,
2982 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2983 (bc_v2i64 (v2f64 VR128:$src2))))],
2984 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2985 (loadv2i64 addr:$src2)))], 0>,
2989 let Constraints = "$src1 = $dst" in {
2990 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2991 !strconcat(OpcodeStr, "ps"), f128mem,
2992 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2993 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2994 (memopv2i64 addr:$src2)))]>, PS;
2996 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2997 !strconcat(OpcodeStr, "pd"), f128mem,
2998 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2999 (bc_v2i64 (v2f64 VR128:$src2))))],
3000 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
3001 (memopv2i64 addr:$src2)))]>, PD;
3005 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
3006 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
3007 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
3008 let isCommutable = 0 in
3009 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
3011 // AVX1 requires type coercions in order to fold loads directly into logical
3013 let Predicates = [HasAVX1Only] in {
3014 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
3015 (VANDPSYrm VR256:$src1, addr:$src2)>;
3016 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3017 (VORPSYrm VR256:$src1, addr:$src2)>;
3018 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3019 (VXORPSYrm VR256:$src1, addr:$src2)>;
3020 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3021 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3024 //===----------------------------------------------------------------------===//
3025 // SSE 1 & 2 - Arithmetic Instructions
3026 //===----------------------------------------------------------------------===//
3028 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3031 /// In addition, we also have a special variant of the scalar form here to
3032 /// represent the associated intrinsic operation. This form is unlike the
3033 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3034 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3036 /// These three forms can each be reg+reg or reg+mem.
3039 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3041 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3042 SDNode OpNode, SizeItins itins> {
3043 let Predicates = [HasAVX, NoVLX] in {
3044 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3045 VR128, v4f32, f128mem, loadv4f32,
3046 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3047 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3048 VR128, v2f64, f128mem, loadv2f64,
3049 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3051 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3052 OpNode, VR256, v8f32, f256mem, loadv8f32,
3053 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3054 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3055 OpNode, VR256, v4f64, f256mem, loadv4f64,
3056 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3059 let Constraints = "$src1 = $dst" in {
3060 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3061 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3063 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3064 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3069 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3071 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3072 OpNode, FR32, f32mem, SSEPackedSingle, itins.s, 0>,
3073 XS, VEX_4V, VEX_LIG;
3074 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3075 OpNode, FR64, f64mem, SSEPackedDouble, itins.d, 0>,
3076 XD, VEX_4V, VEX_LIG;
3078 let Constraints = "$src1 = $dst" in {
3079 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3080 OpNode, FR32, f32mem, SSEPackedSingle,
3082 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3083 OpNode, FR64, f64mem, SSEPackedDouble,
3088 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3090 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3091 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3092 SSEPackedSingle, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3093 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3094 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3095 SSEPackedDouble, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3097 let Constraints = "$src1 = $dst" in {
3098 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3099 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3100 SSEPackedSingle, itins.s>, XS;
3101 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3102 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3103 SSEPackedDouble, itins.d>, XD;
3107 // Binary Arithmetic instructions
3108 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3109 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3110 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3111 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3112 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3113 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3114 let isCommutable = 0 in {
3115 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3116 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3117 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3118 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3119 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3120 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3121 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3122 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3123 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3124 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3125 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3126 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3129 let isCodeGenOnly = 1 in {
3130 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3131 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3132 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3133 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3136 // Patterns used to select SSE scalar fp arithmetic instructions from
3139 // (1) a scalar fp operation followed by a blend
3141 // The effect is that the backend no longer emits unnecessary vector
3142 // insert instructions immediately after SSE scalar fp instructions
3143 // like addss or mulss.
3145 // For example, given the following code:
3146 // __m128 foo(__m128 A, __m128 B) {
3151 // Previously we generated:
3152 // addss %xmm0, %xmm1
3153 // movss %xmm1, %xmm0
3156 // addss %xmm1, %xmm0
3158 // (2) a vector packed single/double fp operation followed by a vector insert
3160 // The effect is that the backend converts the packed fp instruction
3161 // followed by a vector insert into a single SSE scalar fp instruction.
3163 // For example, given the following code:
3164 // __m128 foo(__m128 A, __m128 B) {
3165 // __m128 C = A + B;
3166 // return (__m128) {c[0], a[1], a[2], a[3]};
3169 // Previously we generated:
3170 // addps %xmm0, %xmm1
3171 // movss %xmm1, %xmm0
3174 // addss %xmm1, %xmm0
3176 // TODO: Some canonicalization in lowering would simplify the number of
3177 // patterns we have to try to match.
3178 multiclass scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {
3179 let Predicates = [UseSSE1] in {
3180 // extracted scalar math op with insert via movss
3181 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3182 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3184 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3185 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3187 // vector math op with insert via movss
3188 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3189 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3190 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3193 // With SSE 4.1, blendi is preferred to movsd, so match that too.
3194 let Predicates = [UseSSE41] in {
3195 // extracted scalar math op with insert via blend
3196 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3197 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3198 FR32:$src))), (i8 1))),
3199 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3200 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3202 // vector math op with insert via blend
3203 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3204 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3205 (!cast<I>(OpcPrefix#SSrr_Int)v4f32:$dst, v4f32:$src)>;
3209 // Repeat everything for AVX, except for the movss + scalar combo...
3210 // because that one shouldn't occur with AVX codegen?
3211 let Predicates = [HasAVX] in {
3212 // extracted scalar math op with insert via blend
3213 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3214 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3215 FR32:$src))), (i8 1))),
3216 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst,
3217 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3219 // vector math op with insert via movss
3220 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3221 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3222 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3224 // vector math op with insert via blend
3225 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3226 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3227 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3231 defm : scalar_math_f32_patterns<fadd, "ADD">;
3232 defm : scalar_math_f32_patterns<fsub, "SUB">;
3233 defm : scalar_math_f32_patterns<fmul, "MUL">;
3234 defm : scalar_math_f32_patterns<fdiv, "DIV">;
3236 multiclass scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {
3237 let Predicates = [UseSSE2] in {
3238 // extracted scalar math op with insert via movsd
3239 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3240 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3242 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3243 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3245 // vector math op with insert via movsd
3246 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3247 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3248 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3251 // With SSE 4.1, blendi is preferred to movsd, so match those too.
3252 let Predicates = [UseSSE41] in {
3253 // extracted scalar math op with insert via blend
3254 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3255 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3256 FR64:$src))), (i8 1))),
3257 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3258 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3260 // vector math op with insert via blend
3261 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3262 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3263 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3266 // Repeat everything for AVX.
3267 let Predicates = [HasAVX] in {
3268 // extracted scalar math op with insert via movsd
3269 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3270 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3272 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3273 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3275 // extracted scalar math op with insert via blend
3276 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3277 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3278 FR64:$src))), (i8 1))),
3279 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3280 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3282 // vector math op with insert via movsd
3283 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3284 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3285 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3287 // vector math op with insert via blend
3288 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3289 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3290 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3294 defm : scalar_math_f64_patterns<fadd, "ADD">;
3295 defm : scalar_math_f64_patterns<fsub, "SUB">;
3296 defm : scalar_math_f64_patterns<fmul, "MUL">;
3297 defm : scalar_math_f64_patterns<fdiv, "DIV">;
3301 /// In addition, we also have a special variant of the scalar form here to
3302 /// represent the associated intrinsic operation. This form is unlike the
3303 /// plain scalar form, in that it takes an entire vector (instead of a
3304 /// scalar) and leaves the top elements undefined.
3306 /// And, we have a special variant form for a full-vector intrinsic form.
3308 let Sched = WriteFSqrt in {
3309 def SSE_SQRTPS : OpndItins<
3310 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3313 def SSE_SQRTSS : OpndItins<
3314 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3317 def SSE_SQRTPD : OpndItins<
3318 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3321 def SSE_SQRTSD : OpndItins<
3322 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3326 let Sched = WriteFRsqrt in {
3327 def SSE_RSQRTPS : OpndItins<
3328 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3331 def SSE_RSQRTSS : OpndItins<
3332 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3336 let Sched = WriteFRcp in {
3337 def SSE_RCPP : OpndItins<
3338 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3341 def SSE_RCPS : OpndItins<
3342 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3346 /// sse_fp_unop_s - SSE1 unops in scalar form
3347 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3348 /// the HW instructions are 2 operand / destructive.
3349 multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3350 ValueType vt, ValueType ScalarVT,
3351 X86MemOperand x86memop, Operand vec_memop,
3352 ComplexPattern mem_cpat, Intrinsic Intr,
3353 SDNode OpNode, Domain d, OpndItins itins,
3354 Predicate target, string Suffix> {
3355 let hasSideEffects = 0 in {
3356 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
3357 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3358 [(set RC:$dst, (OpNode RC:$src1))], itins.rr, d>, Sched<[itins.Sched]>,
3361 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1),
3362 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3363 [(set RC:$dst, (OpNode (load addr:$src1)))], itins.rm, d>,
3364 Sched<[itins.Sched.Folded, ReadAfterLd]>,
3365 Requires<[target, OptForSize]>;
3367 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3368 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3369 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3370 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3372 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, vec_memop:$src2),
3373 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3374 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3378 let Predicates = [target] in {
3379 def : Pat<(vt (OpNode mem_cpat:$src)),
3380 (vt (COPY_TO_REGCLASS (vt (!cast<Instruction>(NAME#Suffix##m_Int)
3381 (vt (IMPLICIT_DEF)), mem_cpat:$src)), RC))>;
3382 // These are unary operations, but they are modeled as having 2 source operands
3383 // because the high elements of the destination are unchanged in SSE.
3384 def : Pat<(Intr VR128:$src),
3385 (!cast<Instruction>(NAME#Suffix##r_Int) VR128:$src, VR128:$src)>;
3386 def : Pat<(Intr (load addr:$src)),
3387 (vt (COPY_TO_REGCLASS(!cast<Instruction>(NAME#Suffix##m)
3388 addr:$src), VR128))>;
3389 def : Pat<(Intr mem_cpat:$src),
3390 (!cast<Instruction>(NAME#Suffix##m_Int)
3391 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3395 multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3396 ValueType vt, ValueType ScalarVT,
3397 X86MemOperand x86memop, Operand vec_memop,
3398 ComplexPattern mem_cpat,
3399 Intrinsic Intr, SDNode OpNode, Domain d,
3400 OpndItins itins, string Suffix> {
3401 let hasSideEffects = 0 in {
3402 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3403 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3404 [], itins.rr, d>, Sched<[itins.Sched]>;
3406 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3407 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3408 [], itins.rm, d>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3409 let isCodeGenOnly = 1 in {
3410 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
3411 (ins VR128:$src1, VR128:$src2),
3412 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3413 []>, Sched<[itins.Sched.Folded]>;
3415 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst),
3416 (ins VR128:$src1, vec_memop:$src2),
3417 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3418 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3422 let Predicates = [UseAVX] in {
3423 def : Pat<(OpNode RC:$src), (!cast<Instruction>("V"#NAME#Suffix##r)
3424 (ScalarVT (IMPLICIT_DEF)), RC:$src)>;
3426 def : Pat<(vt (OpNode mem_cpat:$src)),
3427 (!cast<Instruction>("V"#NAME#Suffix##m_Int) (vt (IMPLICIT_DEF)),
3431 let Predicates = [HasAVX] in {
3432 def : Pat<(Intr VR128:$src),
3433 (!cast<Instruction>("V"#NAME#Suffix##r_Int) (vt (IMPLICIT_DEF)),
3436 def : Pat<(Intr mem_cpat:$src),
3437 (!cast<Instruction>("V"#NAME#Suffix##m_Int)
3438 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3440 let Predicates = [UseAVX, OptForSize] in
3441 def : Pat<(ScalarVT (OpNode (load addr:$src))),
3442 (!cast<Instruction>("V"#NAME#Suffix##m) (ScalarVT (IMPLICIT_DEF)),
3446 /// sse1_fp_unop_p - SSE1 unops in packed form.
3447 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3449 let Predicates = [HasAVX] in {
3450 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3451 !strconcat("v", OpcodeStr,
3452 "ps\t{$src, $dst|$dst, $src}"),
3453 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3454 itins.rr>, VEX, Sched<[itins.Sched]>;
3455 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3456 !strconcat("v", OpcodeStr,
3457 "ps\t{$src, $dst|$dst, $src}"),
3458 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3459 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3460 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3461 !strconcat("v", OpcodeStr,
3462 "ps\t{$src, $dst|$dst, $src}"),
3463 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3464 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3465 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3466 !strconcat("v", OpcodeStr,
3467 "ps\t{$src, $dst|$dst, $src}"),
3468 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3469 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3472 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3473 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3474 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3475 Sched<[itins.Sched]>;
3476 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3477 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3478 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3479 Sched<[itins.Sched.Folded]>;
3482 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3483 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3484 SDNode OpNode, OpndItins itins> {
3485 let Predicates = [HasAVX] in {
3486 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3487 !strconcat("v", OpcodeStr,
3488 "pd\t{$src, $dst|$dst, $src}"),
3489 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3490 itins.rr>, VEX, Sched<[itins.Sched]>;
3491 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3492 !strconcat("v", OpcodeStr,
3493 "pd\t{$src, $dst|$dst, $src}"),
3494 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3495 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3496 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3497 !strconcat("v", OpcodeStr,
3498 "pd\t{$src, $dst|$dst, $src}"),
3499 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3500 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3501 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3502 !strconcat("v", OpcodeStr,
3503 "pd\t{$src, $dst|$dst, $src}"),
3504 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3505 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3508 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3509 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3510 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3511 Sched<[itins.Sched]>;
3512 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3513 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3514 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3515 Sched<[itins.Sched.Folded]>;
3518 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3520 defm SS : sse_fp_unop_s<opc, OpcodeStr##ss, FR32, v4f32, f32, f32mem,
3521 ssmem, sse_load_f32,
3522 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3523 SSEPackedSingle, itins, UseSSE1, "SS">, XS;
3524 defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr##ss, FR32, v4f32, f32,
3525 f32mem, ssmem, sse_load_f32,
3526 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3527 SSEPackedSingle, itins, "SS">, XS, VEX_4V, VEX_LIG;
3530 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3532 defm SD : sse_fp_unop_s<opc, OpcodeStr##sd, FR64, v2f64, f64, f64mem,
3533 sdmem, sse_load_f64,
3534 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3535 OpNode, SSEPackedDouble, itins, UseSSE2, "SD">, XD;
3536 defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr##sd, FR64, v2f64, f64,
3537 f64mem, sdmem, sse_load_f64,
3538 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3539 OpNode, SSEPackedDouble, itins, "SD">,
3540 XD, VEX_4V, VEX_LIG;
3544 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3545 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3546 sse2_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSD>,
3547 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3549 // Reciprocal approximations. Note that these typically require refinement
3550 // in order to obtain suitable precision.
3551 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3552 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>;
3553 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3554 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>;
3556 // There is no f64 version of the reciprocal approximation instructions.
3558 // TODO: We should add *scalar* op patterns for these just like we have for
3559 // the binops above. If the binop and unop patterns could all be unified
3560 // that would be even better.
3562 multiclass scalar_unary_math_patterns<Intrinsic Intr, string OpcPrefix,
3563 SDNode Move, ValueType VT,
3564 Predicate BasePredicate> {
3565 let Predicates = [BasePredicate] in {
3566 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3567 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3570 // With SSE 4.1, blendi is preferred to movs*, so match that too.
3571 let Predicates = [UseSSE41] in {
3572 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3573 (!cast<I>(OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3576 // Repeat for AVX versions of the instructions.
3577 let Predicates = [HasAVX] in {
3578 def : Pat<(VT (Move VT:$dst, (Intr VT:$src))),
3579 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3581 def : Pat<(VT (X86Blendi VT:$dst, (Intr VT:$src), (i8 1))),
3582 (!cast<I>("V"#OpcPrefix#r_Int) VT:$dst, VT:$src)>;
3586 defm : scalar_unary_math_patterns<int_x86_sse_rcp_ss, "RCPSS", X86Movss,
3588 defm : scalar_unary_math_patterns<int_x86_sse_rsqrt_ss, "RSQRTSS", X86Movss,
3590 defm : scalar_unary_math_patterns<int_x86_sse_sqrt_ss, "SQRTSS", X86Movss,
3592 defm : scalar_unary_math_patterns<int_x86_sse2_sqrt_sd, "SQRTSD", X86Movsd,
3596 //===----------------------------------------------------------------------===//
3597 // SSE 1 & 2 - Non-temporal stores
3598 //===----------------------------------------------------------------------===//
3600 let AddedComplexity = 400 in { // Prefer non-temporal versions
3601 let SchedRW = [WriteStore] in {
3602 let Predicates = [HasAVX, NoVLX] in {
3603 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3604 (ins f128mem:$dst, VR128:$src),
3605 "movntps\t{$src, $dst|$dst, $src}",
3606 [(alignednontemporalstore (v4f32 VR128:$src),
3608 IIC_SSE_MOVNT>, VEX;
3609 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3610 (ins f128mem:$dst, VR128:$src),
3611 "movntpd\t{$src, $dst|$dst, $src}",
3612 [(alignednontemporalstore (v2f64 VR128:$src),
3614 IIC_SSE_MOVNT>, VEX;
3616 let ExeDomain = SSEPackedInt in
3617 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3618 (ins f128mem:$dst, VR128:$src),
3619 "movntdq\t{$src, $dst|$dst, $src}",
3620 [(alignednontemporalstore (v2i64 VR128:$src),
3622 IIC_SSE_MOVNT>, VEX;
3624 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3625 (ins f256mem:$dst, VR256:$src),
3626 "movntps\t{$src, $dst|$dst, $src}",
3627 [(alignednontemporalstore (v8f32 VR256:$src),
3629 IIC_SSE_MOVNT>, VEX, VEX_L;
3630 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3631 (ins f256mem:$dst, VR256:$src),
3632 "movntpd\t{$src, $dst|$dst, $src}",
3633 [(alignednontemporalstore (v4f64 VR256:$src),
3635 IIC_SSE_MOVNT>, VEX, VEX_L;
3636 let ExeDomain = SSEPackedInt in
3637 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3638 (ins f256mem:$dst, VR256:$src),
3639 "movntdq\t{$src, $dst|$dst, $src}",
3640 [(alignednontemporalstore (v4i64 VR256:$src),
3642 IIC_SSE_MOVNT>, VEX, VEX_L;
3645 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3646 "movntps\t{$src, $dst|$dst, $src}",
3647 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3649 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3650 "movntpd\t{$src, $dst|$dst, $src}",
3651 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3654 let ExeDomain = SSEPackedInt in
3655 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3656 "movntdq\t{$src, $dst|$dst, $src}",
3657 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3660 // There is no AVX form for instructions below this point
3661 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3662 "movnti{l}\t{$src, $dst|$dst, $src}",
3663 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3665 PS, Requires<[HasSSE2]>;
3666 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3667 "movnti{q}\t{$src, $dst|$dst, $src}",
3668 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3670 PS, Requires<[HasSSE2]>;
3671 } // SchedRW = [WriteStore]
3673 let Predicates = [HasAVX2, NoVLX] in {
3674 def : Pat<(alignednontemporalstore (v8i32 VR256:$src), addr:$dst),
3675 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3676 def : Pat<(alignednontemporalstore (v16i16 VR256:$src), addr:$dst),
3677 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3678 def : Pat<(alignednontemporalstore (v32i8 VR256:$src), addr:$dst),
3679 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3682 let Predicates = [HasAVX, NoVLX] in {
3683 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3684 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3685 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3686 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3687 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3688 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3691 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3692 (MOVNTDQmr addr:$dst, VR128:$src)>;
3693 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3694 (MOVNTDQmr addr:$dst, VR128:$src)>;
3695 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3696 (MOVNTDQmr addr:$dst, VR128:$src)>;
3698 } // AddedComplexity
3700 //===----------------------------------------------------------------------===//
3701 // SSE 1 & 2 - Prefetch and memory fence
3702 //===----------------------------------------------------------------------===//
3704 // Prefetch intrinsic.
3705 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3706 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3707 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3708 IIC_SSE_PREFETCH>, TB;
3709 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3710 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3711 IIC_SSE_PREFETCH>, TB;
3712 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3713 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3714 IIC_SSE_PREFETCH>, TB;
3715 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3716 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3717 IIC_SSE_PREFETCH>, TB;
3720 // FIXME: How should flush instruction be modeled?
3721 let SchedRW = [WriteLoad] in {
3723 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3724 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3725 IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
3728 let SchedRW = [WriteNop] in {
3729 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3730 // was introduced with SSE2, it's backward compatible.
3731 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3732 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3733 OBXS, Requires<[HasSSE2]>;
3736 let SchedRW = [WriteFence] in {
3737 // Load, store, and memory fence
3738 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3739 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3740 PS, Requires<[HasSSE1]>;
3741 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3742 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3743 TB, Requires<[HasSSE2]>;
3744 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3745 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3746 TB, Requires<[HasSSE2]>;
3749 def : Pat<(X86SFence), (SFENCE)>;
3750 def : Pat<(X86LFence), (LFENCE)>;
3751 def : Pat<(X86MFence), (MFENCE)>;
3753 //===----------------------------------------------------------------------===//
3754 // SSE 1 & 2 - Load/Store XCSR register
3755 //===----------------------------------------------------------------------===//
3757 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3758 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3759 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3760 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3761 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3762 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3764 let Predicates = [UseSSE1] in {
3765 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
3766 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3767 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
3768 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3769 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3770 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
3773 //===---------------------------------------------------------------------===//
3774 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3775 //===---------------------------------------------------------------------===//
3777 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3779 let hasSideEffects = 0, SchedRW = [WriteMove] in {
3780 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3781 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3783 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3784 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3786 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3787 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3789 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3790 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3795 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3796 SchedRW = [WriteMove] in {
3797 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3798 "movdqa\t{$src, $dst|$dst, $src}", [],
3801 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3802 "movdqa\t{$src, $dst|$dst, $src}", [],
3803 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3804 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3805 "movdqu\t{$src, $dst|$dst, $src}", [],
3808 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3809 "movdqu\t{$src, $dst|$dst, $src}", [],
3810 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3813 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3814 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3815 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3816 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3818 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3819 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3821 let Predicates = [HasAVX] in {
3822 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3823 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3825 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3826 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3831 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3832 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3833 (ins i128mem:$dst, VR128:$src),
3834 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3836 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3837 (ins i256mem:$dst, VR256:$src),
3838 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3840 let Predicates = [HasAVX] in {
3841 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3842 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3844 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3845 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3850 let SchedRW = [WriteMove] in {
3851 let hasSideEffects = 0 in
3852 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3853 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3855 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3856 "movdqu\t{$src, $dst|$dst, $src}",
3857 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3860 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3861 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3862 "movdqa\t{$src, $dst|$dst, $src}", [],
3865 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3866 "movdqu\t{$src, $dst|$dst, $src}",
3867 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3871 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3872 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3873 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3874 "movdqa\t{$src, $dst|$dst, $src}",
3875 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3877 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3878 "movdqu\t{$src, $dst|$dst, $src}",
3879 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3881 XS, Requires<[UseSSE2]>;
3884 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3885 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3886 "movdqa\t{$src, $dst|$dst, $src}",
3887 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3889 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3890 "movdqu\t{$src, $dst|$dst, $src}",
3891 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3893 XS, Requires<[UseSSE2]>;
3896 } // ExeDomain = SSEPackedInt
3898 let Predicates = [HasAVX] in {
3899 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3900 (VMOVDQUmr addr:$dst, VR128:$src)>;
3901 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3902 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3904 let Predicates = [UseSSE2] in
3905 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3906 (MOVDQUmr addr:$dst, VR128:$src)>;
3908 //===---------------------------------------------------------------------===//
3909 // SSE2 - Packed Integer Arithmetic Instructions
3910 //===---------------------------------------------------------------------===//
3912 let Sched = WriteVecIMul in
3913 def SSE_PMADD : OpndItins<
3914 IIC_SSE_PMADD, IIC_SSE_PMADD
3917 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3919 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3920 RegisterClass RC, PatFrag memop_frag,
3921 X86MemOperand x86memop,
3923 bit IsCommutable = 0,
3925 let isCommutable = IsCommutable in
3926 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3927 (ins RC:$src1, RC:$src2),
3929 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3930 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3931 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3932 Sched<[itins.Sched]>;
3933 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3934 (ins RC:$src1, x86memop:$src2),
3936 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3937 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3938 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3939 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3942 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3943 Intrinsic IntId256, OpndItins itins,
3944 bit IsCommutable = 0> {
3945 let Predicates = [HasAVX] in
3946 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3947 VR128, loadv2i64, i128mem, itins,
3948 IsCommutable, 0>, VEX_4V;
3950 let Constraints = "$src1 = $dst" in
3951 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3952 i128mem, itins, IsCommutable, 1>;
3954 let Predicates = [HasAVX2] in
3955 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3956 VR256, loadv4i64, i256mem, itins,
3957 IsCommutable, 0>, VEX_4V, VEX_L;
3960 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3961 string OpcodeStr, SDNode OpNode,
3962 SDNode OpNode2, RegisterClass RC,
3963 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3964 PatFrag ld_frag, ShiftOpndItins itins,
3966 // src2 is always 128-bit
3967 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3968 (ins RC:$src1, VR128:$src2),
3970 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3971 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3972 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3973 itins.rr>, Sched<[WriteVecShift]>;
3974 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3975 (ins RC:$src1, i128mem:$src2),
3977 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3978 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3979 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3980 (bc_frag (ld_frag addr:$src2)))))], itins.rm>,
3981 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3982 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3983 (ins RC:$src1, u8imm:$src2),
3985 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3986 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3987 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3988 Sched<[WriteVecShift]>;
3991 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3992 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3993 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3994 PatFrag memop_frag, X86MemOperand x86memop,
3996 bit IsCommutable = 0, bit Is2Addr = 1> {
3997 let isCommutable = IsCommutable in
3998 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3999 (ins RC:$src1, RC:$src2),
4001 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4002 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4003 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4004 Sched<[itins.Sched]>;
4005 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4006 (ins RC:$src1, x86memop:$src2),
4008 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4009 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4010 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4011 (bitconvert (memop_frag addr:$src2)))))]>,
4012 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4014 } // ExeDomain = SSEPackedInt
4016 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4017 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4018 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4019 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4020 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4021 SSE_INTALU_ITINS_P, 1, NoVLX>;
4022 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4023 SSE_INTALUQ_ITINS_P, 1, NoVLX>;
4024 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4025 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4026 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4027 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4028 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4029 SSE_INTMUL_ITINS_P, 1, NoVLX_Or_NoBWI>;
4030 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4031 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4032 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4033 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4034 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4035 SSE_INTALU_ITINS_P, 0, NoVLX>;
4036 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4037 SSE_INTALUQ_ITINS_P, 0, NoVLX>;
4038 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4039 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4040 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4041 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4042 defm PMINUB : PDI_binop_all<0xDA, "pminub", umin, v16i8, v32i8,
4043 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4044 defm PMINSW : PDI_binop_all<0xEA, "pminsw", smin, v8i16, v16i16,
4045 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4046 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", umax, v16i8, v32i8,
4047 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4048 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", smax, v8i16, v16i16,
4049 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4052 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4053 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4054 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4055 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4056 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4057 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4058 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4059 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4060 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4061 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4062 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4063 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4064 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4065 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4066 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4067 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4068 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4069 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4070 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4071 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4073 let Predicates = [HasAVX2] in
4074 def : Pat<(v32i8 (X86psadbw (v32i8 VR256:$src1),
4075 (v32i8 VR256:$src2))),
4076 (VPSADBWYrr VR256:$src2, VR256:$src1)>;
4078 let Predicates = [HasAVX] in
4079 def : Pat<(v16i8 (X86psadbw (v16i8 VR128:$src1),
4080 (v16i8 VR128:$src2))),
4081 (VPSADBWrr VR128:$src2, VR128:$src1)>;
4083 def : Pat<(v16i8 (X86psadbw (v16i8 VR128:$src1),
4084 (v16i8 VR128:$src2))),
4085 (PSADBWrr VR128:$src2, VR128:$src1)>;
4087 let Predicates = [HasAVX] in
4088 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4089 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4091 let Predicates = [HasAVX2] in
4092 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4093 VR256, loadv4i64, i256mem,
4094 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4095 let Constraints = "$src1 = $dst" in
4096 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4097 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4099 //===---------------------------------------------------------------------===//
4100 // SSE2 - Packed Integer Logical Instructions
4101 //===---------------------------------------------------------------------===//
4103 let Predicates = [HasAVX, NoVLX] in {
4104 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4105 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4106 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4107 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4108 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4109 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4110 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4111 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4112 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4114 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4115 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4116 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4117 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4118 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4119 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4120 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4121 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4122 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4124 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4125 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4126 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4127 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4128 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4129 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4131 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4132 // 128-bit logical shifts.
4133 def VPSLLDQri : PDIi8<0x73, MRM7r,
4134 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4135 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4137 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))]>,
4139 def VPSRLDQri : PDIi8<0x73, MRM3r,
4140 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4141 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4143 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))]>,
4145 // PSRADQri doesn't exist in SSE[1-3].
4147 } // Predicates = [HasAVX]
4149 let Predicates = [HasAVX2, NoVLX] in {
4150 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4151 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4152 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4153 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4154 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4155 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4156 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4157 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4158 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4160 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4161 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4162 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4163 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4164 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4165 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4166 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4167 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4168 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4170 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4171 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4172 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4173 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4174 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4175 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4177 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4178 // 256-bit logical shifts.
4179 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4180 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4181 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4183 (v4i64 (X86vshldq VR256:$src1, (i8 imm:$src2))))]>,
4185 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4186 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4187 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4189 (v4i64 (X86vshrdq VR256:$src1, (i8 imm:$src2))))]>,
4191 // PSRADQYri doesn't exist in SSE[1-3].
4193 } // Predicates = [HasAVX2]
4195 let Constraints = "$src1 = $dst" in {
4196 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4197 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4198 SSE_INTSHIFT_ITINS_P>;
4199 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4200 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4201 SSE_INTSHIFT_ITINS_P>;
4202 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4203 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4204 SSE_INTSHIFT_ITINS_P>;
4206 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4207 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4208 SSE_INTSHIFT_ITINS_P>;
4209 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4210 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4211 SSE_INTSHIFT_ITINS_P>;
4212 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4213 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4214 SSE_INTSHIFT_ITINS_P>;
4216 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4217 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4218 SSE_INTSHIFT_ITINS_P>;
4219 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4220 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4221 SSE_INTSHIFT_ITINS_P>;
4223 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4224 // 128-bit logical shifts.
4225 def PSLLDQri : PDIi8<0x73, MRM7r,
4226 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4227 "pslldq\t{$src2, $dst|$dst, $src2}",
4229 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))],
4230 IIC_SSE_INTSHDQ_P_RI>;
4231 def PSRLDQri : PDIi8<0x73, MRM3r,
4232 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4233 "psrldq\t{$src2, $dst|$dst, $src2}",
4235 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))],
4236 IIC_SSE_INTSHDQ_P_RI>;
4237 // PSRADQri doesn't exist in SSE[1-3].
4239 } // Constraints = "$src1 = $dst"
4241 //===---------------------------------------------------------------------===//
4242 // SSE2 - Packed Integer Comparison Instructions
4243 //===---------------------------------------------------------------------===//
4245 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4246 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4247 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4248 SSE_INTALU_ITINS_P, 1, NoVLX_Or_NoBWI>;
4249 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4250 SSE_INTALU_ITINS_P, 1, NoVLX>;
4251 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4252 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4253 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4254 SSE_INTALU_ITINS_P, 0, NoVLX_Or_NoBWI>;
4255 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4256 SSE_INTALU_ITINS_P, 0, NoVLX>;
4258 //===---------------------------------------------------------------------===//
4259 // SSE2 - Packed Integer Shuffle Instructions
4260 //===---------------------------------------------------------------------===//
4262 let ExeDomain = SSEPackedInt in {
4263 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4265 let Predicates = [HasAVX] in {
4266 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4267 (ins VR128:$src1, u8imm:$src2),
4268 !strconcat("v", OpcodeStr,
4269 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4271 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4272 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4273 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4274 (ins i128mem:$src1, u8imm:$src2),
4275 !strconcat("v", OpcodeStr,
4276 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4278 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4279 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4280 Sched<[WriteShuffleLd]>;
4283 let Predicates = [HasAVX2] in {
4284 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4285 (ins VR256:$src1, u8imm:$src2),
4286 !strconcat("v", OpcodeStr,
4287 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4289 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4290 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4291 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4292 (ins i256mem:$src1, u8imm:$src2),
4293 !strconcat("v", OpcodeStr,
4294 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4296 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4297 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4298 Sched<[WriteShuffleLd]>;
4301 let Predicates = [UseSSE2] in {
4302 def ri : Ii8<0x70, MRMSrcReg,
4303 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4304 !strconcat(OpcodeStr,
4305 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4307 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4308 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4309 def mi : Ii8<0x70, MRMSrcMem,
4310 (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2),
4311 !strconcat(OpcodeStr,
4312 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4314 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4315 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4316 Sched<[WriteShuffleLd, ReadAfterLd]>;
4319 } // ExeDomain = SSEPackedInt
4321 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4322 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4323 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4325 let Predicates = [HasAVX] in {
4326 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4327 (VPSHUFDmi addr:$src1, imm:$imm)>;
4328 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4329 (VPSHUFDri VR128:$src1, imm:$imm)>;
4332 let Predicates = [UseSSE2] in {
4333 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4334 (PSHUFDmi addr:$src1, imm:$imm)>;
4335 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4336 (PSHUFDri VR128:$src1, imm:$imm)>;
4339 //===---------------------------------------------------------------------===//
4340 // Packed Integer Pack Instructions (SSE & AVX)
4341 //===---------------------------------------------------------------------===//
4343 let ExeDomain = SSEPackedInt in {
4344 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4345 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4346 PatFrag ld_frag, bit Is2Addr = 1> {
4347 def rr : PDI<opc, MRMSrcReg,
4348 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4350 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4351 !strconcat(OpcodeStr,
4352 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4354 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4355 Sched<[WriteShuffle]>;
4356 def rm : PDI<opc, MRMSrcMem,
4357 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4359 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4360 !strconcat(OpcodeStr,
4361 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4363 (OutVT (OpNode VR128:$src1,
4364 (bc_frag (ld_frag addr:$src2)))))]>,
4365 Sched<[WriteShuffleLd, ReadAfterLd]>;
4368 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4369 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4370 def Yrr : PDI<opc, MRMSrcReg,
4371 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4372 !strconcat(OpcodeStr,
4373 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4375 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4376 Sched<[WriteShuffle]>;
4377 def Yrm : PDI<opc, MRMSrcMem,
4378 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4379 !strconcat(OpcodeStr,
4380 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4382 (OutVT (OpNode VR256:$src1,
4383 (bc_frag (loadv4i64 addr:$src2)))))]>,
4384 Sched<[WriteShuffleLd, ReadAfterLd]>;
4387 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4388 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4389 PatFrag ld_frag, bit Is2Addr = 1> {
4390 def rr : SS48I<opc, MRMSrcReg,
4391 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4393 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4394 !strconcat(OpcodeStr,
4395 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4397 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4398 Sched<[WriteShuffle]>;
4399 def rm : SS48I<opc, MRMSrcMem,
4400 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4402 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4403 !strconcat(OpcodeStr,
4404 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4406 (OutVT (OpNode VR128:$src1,
4407 (bc_frag (ld_frag addr:$src2)))))]>,
4408 Sched<[WriteShuffleLd, ReadAfterLd]>;
4411 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4412 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4413 def Yrr : SS48I<opc, MRMSrcReg,
4414 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4415 !strconcat(OpcodeStr,
4416 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4418 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4419 Sched<[WriteShuffle]>;
4420 def Yrm : SS48I<opc, MRMSrcMem,
4421 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4422 !strconcat(OpcodeStr,
4423 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4425 (OutVT (OpNode VR256:$src1,
4426 (bc_frag (loadv4i64 addr:$src2)))))]>,
4427 Sched<[WriteShuffleLd, ReadAfterLd]>;
4430 let Predicates = [HasAVX] in {
4431 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4432 bc_v8i16, loadv2i64, 0>, VEX_4V;
4433 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4434 bc_v4i32, loadv2i64, 0>, VEX_4V;
4436 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4437 bc_v8i16, loadv2i64, 0>, VEX_4V;
4438 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4439 bc_v4i32, loadv2i64, 0>, VEX_4V;
4442 let Predicates = [HasAVX2] in {
4443 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4444 bc_v16i16>, VEX_4V, VEX_L;
4445 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4446 bc_v8i32>, VEX_4V, VEX_L;
4448 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4449 bc_v16i16>, VEX_4V, VEX_L;
4450 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4451 bc_v8i32>, VEX_4V, VEX_L;
4454 let Constraints = "$src1 = $dst" in {
4455 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4456 bc_v8i16, memopv2i64>;
4457 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4458 bc_v4i32, memopv2i64>;
4460 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4461 bc_v8i16, memopv2i64>;
4463 let Predicates = [HasSSE41] in
4464 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4465 bc_v4i32, memopv2i64>;
4467 } // ExeDomain = SSEPackedInt
4469 //===---------------------------------------------------------------------===//
4470 // SSE2 - Packed Integer Unpack Instructions
4471 //===---------------------------------------------------------------------===//
4473 let ExeDomain = SSEPackedInt in {
4474 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4475 SDNode OpNode, PatFrag bc_frag, PatFrag ld_frag,
4477 def rr : PDI<opc, MRMSrcReg,
4478 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4480 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4481 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4482 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4483 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4484 def rm : PDI<opc, MRMSrcMem,
4485 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4487 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4488 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4489 [(set VR128:$dst, (OpNode VR128:$src1,
4490 (bc_frag (ld_frag addr:$src2))))],
4492 Sched<[WriteShuffleLd, ReadAfterLd]>;
4495 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4496 SDNode OpNode, PatFrag bc_frag> {
4497 def Yrr : PDI<opc, MRMSrcReg,
4498 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4499 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4500 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4501 Sched<[WriteShuffle]>;
4502 def Yrm : PDI<opc, MRMSrcMem,
4503 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4504 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4505 [(set VR256:$dst, (OpNode VR256:$src1,
4506 (bc_frag (loadv4i64 addr:$src2))))]>,
4507 Sched<[WriteShuffleLd, ReadAfterLd]>;
4510 let Predicates = [HasAVX] in {
4511 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4512 bc_v16i8, loadv2i64, 0>, VEX_4V;
4513 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4514 bc_v8i16, loadv2i64, 0>, VEX_4V;
4515 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4516 bc_v4i32, loadv2i64, 0>, VEX_4V;
4517 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4518 bc_v2i64, loadv2i64, 0>, VEX_4V;
4520 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4521 bc_v16i8, loadv2i64, 0>, VEX_4V;
4522 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4523 bc_v8i16, loadv2i64, 0>, VEX_4V;
4524 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4525 bc_v4i32, loadv2i64, 0>, VEX_4V;
4526 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4527 bc_v2i64, loadv2i64, 0>, VEX_4V;
4530 let Predicates = [HasAVX2] in {
4531 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4532 bc_v32i8>, VEX_4V, VEX_L;
4533 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4534 bc_v16i16>, VEX_4V, VEX_L;
4535 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4536 bc_v8i32>, VEX_4V, VEX_L;
4537 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4538 bc_v4i64>, VEX_4V, VEX_L;
4540 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4541 bc_v32i8>, VEX_4V, VEX_L;
4542 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4543 bc_v16i16>, VEX_4V, VEX_L;
4544 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4545 bc_v8i32>, VEX_4V, VEX_L;
4546 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4547 bc_v4i64>, VEX_4V, VEX_L;
4550 let Constraints = "$src1 = $dst" in {
4551 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4552 bc_v16i8, memopv2i64>;
4553 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4554 bc_v8i16, memopv2i64>;
4555 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4556 bc_v4i32, memopv2i64>;
4557 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4558 bc_v2i64, memopv2i64>;
4560 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4561 bc_v16i8, memopv2i64>;
4562 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4563 bc_v8i16, memopv2i64>;
4564 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4565 bc_v4i32, memopv2i64>;
4566 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4567 bc_v2i64, memopv2i64>;
4569 } // ExeDomain = SSEPackedInt
4571 //===---------------------------------------------------------------------===//
4572 // SSE2 - Packed Integer Extract and Insert
4573 //===---------------------------------------------------------------------===//
4575 let ExeDomain = SSEPackedInt in {
4576 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4577 def rri : Ii8<0xC4, MRMSrcReg,
4578 (outs VR128:$dst), (ins VR128:$src1,
4579 GR32orGR64:$src2, u8imm:$src3),
4581 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4582 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4584 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4585 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4586 def rmi : Ii8<0xC4, MRMSrcMem,
4587 (outs VR128:$dst), (ins VR128:$src1,
4588 i16mem:$src2, u8imm:$src3),
4590 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4591 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4593 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4594 imm:$src3))], IIC_SSE_PINSRW>,
4595 Sched<[WriteShuffleLd, ReadAfterLd]>;
4599 let Predicates = [HasAVX] in
4600 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4601 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4602 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4603 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4604 imm:$src2))]>, PD, VEX,
4605 Sched<[WriteShuffle]>;
4606 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4607 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4608 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4609 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4610 imm:$src2))], IIC_SSE_PEXTRW>,
4611 Sched<[WriteShuffleLd, ReadAfterLd]>;
4614 let Predicates = [HasAVX] in
4615 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4617 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4618 defm PINSRW : sse2_pinsrw, PD;
4620 } // ExeDomain = SSEPackedInt
4622 //===---------------------------------------------------------------------===//
4623 // SSE2 - Packed Mask Creation
4624 //===---------------------------------------------------------------------===//
4626 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4628 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4630 "pmovmskb\t{$src, $dst|$dst, $src}",
4631 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4632 IIC_SSE_MOVMSK>, VEX;
4634 let Predicates = [HasAVX2] in {
4635 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4637 "pmovmskb\t{$src, $dst|$dst, $src}",
4638 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4642 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4643 "pmovmskb\t{$src, $dst|$dst, $src}",
4644 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4647 } // ExeDomain = SSEPackedInt
4649 //===---------------------------------------------------------------------===//
4650 // SSE2 - Conditional Store
4651 //===---------------------------------------------------------------------===//
4653 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4655 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4656 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4657 (ins VR128:$src, VR128:$mask),
4658 "maskmovdqu\t{$mask, $src|$src, $mask}",
4659 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4660 IIC_SSE_MASKMOV>, VEX;
4661 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4662 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4663 (ins VR128:$src, VR128:$mask),
4664 "maskmovdqu\t{$mask, $src|$src, $mask}",
4665 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4666 IIC_SSE_MASKMOV>, VEX;
4668 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4669 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4670 "maskmovdqu\t{$mask, $src|$src, $mask}",
4671 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4673 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4674 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4675 "maskmovdqu\t{$mask, $src|$src, $mask}",
4676 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4679 } // ExeDomain = SSEPackedInt
4681 //===---------------------------------------------------------------------===//
4682 // SSE2 - Move Doubleword
4683 //===---------------------------------------------------------------------===//
4685 //===---------------------------------------------------------------------===//
4686 // Move Int Doubleword to Packed Double Int
4688 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4689 "movd\t{$src, $dst|$dst, $src}",
4691 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4692 VEX, Sched<[WriteMove]>;
4693 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4694 "movd\t{$src, $dst|$dst, $src}",
4696 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4698 VEX, Sched<[WriteLoad]>;
4699 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4700 "movq\t{$src, $dst|$dst, $src}",
4702 (v2i64 (scalar_to_vector GR64:$src)))],
4703 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4704 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4705 def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4706 "movq\t{$src, $dst|$dst, $src}",
4707 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteLoad]>;
4708 let isCodeGenOnly = 1 in
4709 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4710 "movq\t{$src, $dst|$dst, $src}",
4711 [(set FR64:$dst, (bitconvert GR64:$src))],
4712 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4714 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4715 "movd\t{$src, $dst|$dst, $src}",
4717 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4719 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4720 "movd\t{$src, $dst|$dst, $src}",
4722 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4723 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4724 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4725 "mov{d|q}\t{$src, $dst|$dst, $src}",
4727 (v2i64 (scalar_to_vector GR64:$src)))],
4728 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4729 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4730 def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4731 "mov{d|q}\t{$src, $dst|$dst, $src}",
4732 [], IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4733 let isCodeGenOnly = 1 in
4734 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4735 "mov{d|q}\t{$src, $dst|$dst, $src}",
4736 [(set FR64:$dst, (bitconvert GR64:$src))],
4737 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4739 //===---------------------------------------------------------------------===//
4740 // Move Int Doubleword to Single Scalar
4742 let isCodeGenOnly = 1 in {
4743 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4744 "movd\t{$src, $dst|$dst, $src}",
4745 [(set FR32:$dst, (bitconvert GR32:$src))],
4746 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4748 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4749 "movd\t{$src, $dst|$dst, $src}",
4750 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4752 VEX, Sched<[WriteLoad]>;
4753 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4754 "movd\t{$src, $dst|$dst, $src}",
4755 [(set FR32:$dst, (bitconvert GR32:$src))],
4756 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4758 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4759 "movd\t{$src, $dst|$dst, $src}",
4760 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4761 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4764 //===---------------------------------------------------------------------===//
4765 // Move Packed Doubleword Int to Packed Double Int
4767 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4768 "movd\t{$src, $dst|$dst, $src}",
4769 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4770 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4772 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4773 (ins i32mem:$dst, VR128:$src),
4774 "movd\t{$src, $dst|$dst, $src}",
4775 [(store (i32 (vector_extract (v4i32 VR128:$src),
4776 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4777 VEX, Sched<[WriteStore]>;
4778 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4779 "movd\t{$src, $dst|$dst, $src}",
4780 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4781 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4783 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4784 "movd\t{$src, $dst|$dst, $src}",
4785 [(store (i32 (vector_extract (v4i32 VR128:$src),
4786 (iPTR 0))), addr:$dst)],
4787 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4789 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4790 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4792 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4793 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4795 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4796 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4798 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4799 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4801 //===---------------------------------------------------------------------===//
4802 // Move Packed Doubleword Int first element to Doubleword Int
4804 let SchedRW = [WriteMove] in {
4805 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4806 "movq\t{$src, $dst|$dst, $src}",
4807 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4812 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4813 "mov{d|q}\t{$src, $dst|$dst, $src}",
4814 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4819 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4820 def VMOVPQIto64rm : VRS2I<0x7E, MRMDestMem, (outs i64mem:$dst),
4821 (ins VR128:$src), "movq\t{$src, $dst|$dst, $src}",
4822 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4823 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4824 def MOVPQIto64rm : RS2I<0x7E, MRMDestMem, (outs i64mem:$dst), (ins VR128:$src),
4825 "mov{d|q}\t{$src, $dst|$dst, $src}",
4826 [], IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4828 //===---------------------------------------------------------------------===//
4829 // Bitcast FR64 <-> GR64
4831 let isCodeGenOnly = 1 in {
4832 let Predicates = [UseAVX] in
4833 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4834 "movq\t{$src, $dst|$dst, $src}",
4835 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4836 VEX, Sched<[WriteLoad]>;
4837 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4838 "movq\t{$src, $dst|$dst, $src}",
4839 [(set GR64:$dst, (bitconvert FR64:$src))],
4840 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4841 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4842 "movq\t{$src, $dst|$dst, $src}",
4843 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4844 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4846 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4847 "movq\t{$src, $dst|$dst, $src}",
4848 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4849 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4850 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4851 "mov{d|q}\t{$src, $dst|$dst, $src}",
4852 [(set GR64:$dst, (bitconvert FR64:$src))],
4853 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4854 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4855 "movq\t{$src, $dst|$dst, $src}",
4856 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4857 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4860 //===---------------------------------------------------------------------===//
4861 // Move Scalar Single to Double Int
4863 let isCodeGenOnly = 1 in {
4864 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4865 "movd\t{$src, $dst|$dst, $src}",
4866 [(set GR32:$dst, (bitconvert FR32:$src))],
4867 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4868 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4869 "movd\t{$src, $dst|$dst, $src}",
4870 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4871 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4872 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4873 "movd\t{$src, $dst|$dst, $src}",
4874 [(set GR32:$dst, (bitconvert FR32:$src))],
4875 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4876 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4877 "movd\t{$src, $dst|$dst, $src}",
4878 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4879 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4882 //===---------------------------------------------------------------------===//
4883 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4885 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4886 let AddedComplexity = 15 in {
4887 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4888 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4889 [(set VR128:$dst, (v2i64 (X86vzmovl
4890 (v2i64 (scalar_to_vector GR64:$src)))))],
4893 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4894 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4895 [(set VR128:$dst, (v2i64 (X86vzmovl
4896 (v2i64 (scalar_to_vector GR64:$src)))))],
4899 } // isCodeGenOnly, SchedRW
4901 let Predicates = [UseAVX] in {
4902 let AddedComplexity = 15 in
4903 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4904 (VMOVDI2PDIrr GR32:$src)>;
4906 // AVX 128-bit movd/movq instructions write zeros in the high 128-bit part.
4907 // These instructions also write zeros in the high part of a 256-bit register.
4908 let AddedComplexity = 20 in {
4909 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4910 (VMOVDI2PDIrm addr:$src)>;
4911 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4912 (VMOVDI2PDIrm addr:$src)>;
4913 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4914 (VMOVDI2PDIrm addr:$src)>;
4915 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4916 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
4917 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrm addr:$src), sub_xmm)>;
4919 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4920 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4921 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4922 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4923 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4924 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4925 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4928 let Predicates = [UseSSE2] in {
4929 let AddedComplexity = 15 in
4930 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4931 (MOVDI2PDIrr GR32:$src)>;
4933 let AddedComplexity = 20 in {
4934 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4935 (MOVDI2PDIrm addr:$src)>;
4936 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4937 (MOVDI2PDIrm addr:$src)>;
4938 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4939 (MOVDI2PDIrm addr:$src)>;
4943 // These are the correct encodings of the instructions so that we know how to
4944 // read correct assembly, even though we continue to emit the wrong ones for
4945 // compatibility with Darwin's buggy assembler.
4946 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4947 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4948 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4949 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4950 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4951 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4952 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4953 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4954 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4956 //===---------------------------------------------------------------------===//
4957 // SSE2 - Move Quadword
4958 //===---------------------------------------------------------------------===//
4960 //===---------------------------------------------------------------------===//
4961 // Move Quadword Int to Packed Quadword Int
4964 let ExeDomain = SSEPackedInt, SchedRW = [WriteLoad] in {
4965 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4966 "vmovq\t{$src, $dst|$dst, $src}",
4968 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4969 VEX, Requires<[UseAVX]>;
4970 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4971 "movq\t{$src, $dst|$dst, $src}",
4973 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4975 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4976 } // ExeDomain, SchedRW
4978 //===---------------------------------------------------------------------===//
4979 // Move Packed Quadword Int to Quadword Int
4981 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4982 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4983 "movq\t{$src, $dst|$dst, $src}",
4984 [(store (i64 (vector_extract (v2i64 VR128:$src),
4985 (iPTR 0))), addr:$dst)],
4986 IIC_SSE_MOVDQ>, VEX;
4987 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4988 "movq\t{$src, $dst|$dst, $src}",
4989 [(store (i64 (vector_extract (v2i64 VR128:$src),
4990 (iPTR 0))), addr:$dst)],
4992 } // ExeDomain, SchedRW
4994 // For disassembler only
4995 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4996 SchedRW = [WriteVecLogic] in {
4997 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4998 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
4999 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5000 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
5003 //===---------------------------------------------------------------------===//
5004 // Store / copy lower 64-bits of a XMM register.
5006 let Predicates = [HasAVX] in
5007 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5008 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5009 let Predicates = [UseSSE2] in
5010 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5011 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5013 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, AddedComplexity = 20 in {
5014 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5015 "vmovq\t{$src, $dst|$dst, $src}",
5017 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5018 (loadi64 addr:$src))))))],
5020 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5022 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5023 "movq\t{$src, $dst|$dst, $src}",
5025 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5026 (loadi64 addr:$src))))))],
5028 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5029 } // ExeDomain, isCodeGenOnly, AddedComplexity
5031 let Predicates = [UseAVX], AddedComplexity = 20 in {
5032 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5033 (VMOVZQI2PQIrm addr:$src)>;
5034 def : Pat<(v2i64 (X86vzload addr:$src)),
5035 (VMOVZQI2PQIrm addr:$src)>;
5036 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5037 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
5038 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
5041 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5042 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5043 (MOVZQI2PQIrm addr:$src)>;
5044 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5047 let Predicates = [HasAVX] in {
5048 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5049 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5050 def : Pat<(v4i64 (X86vzload addr:$src)),
5051 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5054 //===---------------------------------------------------------------------===//
5055 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5056 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5058 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
5059 let AddedComplexity = 15 in
5060 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5061 "vmovq\t{$src, $dst|$dst, $src}",
5062 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5064 XS, VEX, Requires<[UseAVX]>;
5065 let AddedComplexity = 15 in
5066 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5067 "movq\t{$src, $dst|$dst, $src}",
5068 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5070 XS, Requires<[UseSSE2]>;
5071 } // ExeDomain, SchedRW
5073 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5074 let AddedComplexity = 20 in
5075 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5076 "vmovq\t{$src, $dst|$dst, $src}",
5077 [(set VR128:$dst, (v2i64 (X86vzmovl
5078 (loadv2i64 addr:$src))))],
5080 XS, VEX, Requires<[UseAVX]>;
5081 let AddedComplexity = 20 in {
5082 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5083 "movq\t{$src, $dst|$dst, $src}",
5084 [(set VR128:$dst, (v2i64 (X86vzmovl
5085 (loadv2i64 addr:$src))))],
5087 XS, Requires<[UseSSE2]>;
5089 } // ExeDomain, isCodeGenOnly, SchedRW
5091 let AddedComplexity = 20 in {
5092 let Predicates = [UseAVX] in {
5093 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5094 (VMOVZPQILo2PQIrr VR128:$src)>;
5096 let Predicates = [UseSSE2] in {
5097 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5098 (MOVZPQILo2PQIrr VR128:$src)>;
5102 //===---------------------------------------------------------------------===//
5103 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5104 //===---------------------------------------------------------------------===//
5105 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5106 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5107 X86MemOperand x86memop> {
5108 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5109 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5110 [(set RC:$dst, (vt (OpNode RC:$src)))],
5111 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5112 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5113 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5114 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5115 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5118 let Predicates = [HasAVX] in {
5119 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5120 v4f32, VR128, loadv4f32, f128mem>, VEX;
5121 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5122 v4f32, VR128, loadv4f32, f128mem>, VEX;
5123 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5124 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5125 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5126 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5128 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5129 memopv4f32, f128mem>;
5130 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5131 memopv4f32, f128mem>;
5133 let Predicates = [HasAVX] in {
5134 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5135 (VMOVSHDUPrr VR128:$src)>;
5136 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5137 (VMOVSHDUPrm addr:$src)>;
5138 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5139 (VMOVSLDUPrr VR128:$src)>;
5140 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5141 (VMOVSLDUPrm addr:$src)>;
5142 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5143 (VMOVSHDUPYrr VR256:$src)>;
5144 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5145 (VMOVSHDUPYrm addr:$src)>;
5146 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5147 (VMOVSLDUPYrr VR256:$src)>;
5148 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5149 (VMOVSLDUPYrm addr:$src)>;
5152 let Predicates = [UseSSE3] in {
5153 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5154 (MOVSHDUPrr VR128:$src)>;
5155 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5156 (MOVSHDUPrm addr:$src)>;
5157 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5158 (MOVSLDUPrr VR128:$src)>;
5159 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5160 (MOVSLDUPrm addr:$src)>;
5163 //===---------------------------------------------------------------------===//
5164 // SSE3 - Replicate Double FP - MOVDDUP
5165 //===---------------------------------------------------------------------===//
5167 multiclass sse3_replicate_dfp<string OpcodeStr> {
5168 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5169 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5170 [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))],
5171 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5172 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5173 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5176 (scalar_to_vector (loadf64 addr:$src)))))],
5177 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5180 // FIXME: Merge with above classe when there're patterns for the ymm version
5181 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5182 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5183 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5184 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5185 Sched<[WriteFShuffle]>;
5186 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5187 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5190 (scalar_to_vector (loadf64 addr:$src)))))]>,
5194 let Predicates = [HasAVX] in {
5195 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5196 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5199 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5201 let Predicates = [HasAVX] in {
5202 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5203 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5204 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5205 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5206 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5207 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5208 def : Pat<(X86Movddup (bc_v2f64
5209 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5210 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5213 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5214 (VMOVDDUPYrm addr:$src)>;
5215 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5216 (VMOVDDUPYrm addr:$src)>;
5217 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5218 (VMOVDDUPYrm addr:$src)>;
5219 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5220 (VMOVDDUPYrr VR256:$src)>;
5223 let Predicates = [UseAVX, OptForSize] in {
5224 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5225 (VMOVDDUPrm addr:$src)>;
5226 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5227 (VMOVDDUPrm addr:$src)>;
5230 let Predicates = [UseSSE3] in {
5231 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5232 (MOVDDUPrm addr:$src)>;
5233 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5234 (MOVDDUPrm addr:$src)>;
5235 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5236 (MOVDDUPrm addr:$src)>;
5237 def : Pat<(X86Movddup (bc_v2f64
5238 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5239 (MOVDDUPrm addr:$src)>;
5242 //===---------------------------------------------------------------------===//
5243 // SSE3 - Move Unaligned Integer
5244 //===---------------------------------------------------------------------===//
5246 let SchedRW = [WriteLoad] in {
5247 let Predicates = [HasAVX] in {
5248 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5249 "vlddqu\t{$src, $dst|$dst, $src}",
5250 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5251 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5252 "vlddqu\t{$src, $dst|$dst, $src}",
5253 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5256 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5257 "lddqu\t{$src, $dst|$dst, $src}",
5258 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5262 //===---------------------------------------------------------------------===//
5263 // SSE3 - Arithmetic
5264 //===---------------------------------------------------------------------===//
5266 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5267 X86MemOperand x86memop, OpndItins itins,
5268 PatFrag ld_frag, bit Is2Addr = 1> {
5269 def rr : I<0xD0, MRMSrcReg,
5270 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5272 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5273 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5274 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5275 Sched<[itins.Sched]>;
5276 def rm : I<0xD0, MRMSrcMem,
5277 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5279 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5280 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5281 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))], itins.rr>,
5282 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5285 let Predicates = [HasAVX] in {
5286 let ExeDomain = SSEPackedSingle in {
5287 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5288 f128mem, SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V;
5289 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5290 f256mem, SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V, VEX_L;
5292 let ExeDomain = SSEPackedDouble in {
5293 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5294 f128mem, SSE_ALU_F64P, loadv2f64, 0>, PD, VEX_4V;
5295 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5296 f256mem, SSE_ALU_F64P, loadv4f64, 0>, PD, VEX_4V, VEX_L;
5299 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5300 let ExeDomain = SSEPackedSingle in
5301 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5302 f128mem, SSE_ALU_F32P, memopv4f32>, XD;
5303 let ExeDomain = SSEPackedDouble in
5304 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5305 f128mem, SSE_ALU_F64P, memopv2f64>, PD;
5308 // Patterns used to select 'addsub' instructions.
5309 let Predicates = [HasAVX] in {
5310 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5311 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5312 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (loadv4f32 addr:$rhs))),
5313 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5314 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5315 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5316 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (loadv2f64 addr:$rhs))),
5317 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5319 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5320 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5321 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (loadv8f32 addr:$rhs))),
5322 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5323 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5324 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5325 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (loadv4f64 addr:$rhs))),
5326 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5329 let Predicates = [UseSSE3] in {
5330 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5331 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5332 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (memopv4f32 addr:$rhs))),
5333 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5334 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5335 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5336 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (memopv2f64 addr:$rhs))),
5337 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5340 //===---------------------------------------------------------------------===//
5341 // SSE3 Instructions
5342 //===---------------------------------------------------------------------===//
5345 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5346 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5348 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5350 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5351 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5352 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5355 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5357 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5358 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5359 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5360 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5362 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5363 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5365 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5367 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5368 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5369 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5372 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5374 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5375 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5376 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5377 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5380 let Predicates = [HasAVX] in {
5381 let ExeDomain = SSEPackedSingle in {
5382 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5383 X86fhadd, loadv4f32, 0>, VEX_4V;
5384 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5385 X86fhsub, loadv4f32, 0>, VEX_4V;
5386 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5387 X86fhadd, loadv8f32, 0>, VEX_4V, VEX_L;
5388 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5389 X86fhsub, loadv8f32, 0>, VEX_4V, VEX_L;
5391 let ExeDomain = SSEPackedDouble in {
5392 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5393 X86fhadd, loadv2f64, 0>, VEX_4V;
5394 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5395 X86fhsub, loadv2f64, 0>, VEX_4V;
5396 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5397 X86fhadd, loadv4f64, 0>, VEX_4V, VEX_L;
5398 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5399 X86fhsub, loadv4f64, 0>, VEX_4V, VEX_L;
5403 let Constraints = "$src1 = $dst" in {
5404 let ExeDomain = SSEPackedSingle in {
5405 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd,
5407 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub,
5410 let ExeDomain = SSEPackedDouble in {
5411 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd,
5413 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub,
5418 //===---------------------------------------------------------------------===//
5419 // SSSE3 - Packed Absolute Instructions
5420 //===---------------------------------------------------------------------===//
5423 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5424 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
5426 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5428 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5429 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5430 Sched<[WriteVecALU]>;
5432 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5434 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5437 (bitconvert (ld_frag addr:$src))))], IIC_SSE_PABS_RM>,
5438 Sched<[WriteVecALULd]>;
5441 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5442 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5443 Intrinsic IntId256> {
5444 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5446 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5447 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5448 Sched<[WriteVecALU]>;
5450 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5455 (bitconvert (loadv4i64 addr:$src))))]>,
5456 Sched<[WriteVecALULd]>;
5459 // Helper fragments to match sext vXi1 to vXiY.
5460 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5462 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5463 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5464 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5466 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5467 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5469 let Predicates = [HasAVX] in {
5470 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", int_x86_ssse3_pabs_b_128,
5472 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", int_x86_ssse3_pabs_w_128,
5474 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", int_x86_ssse3_pabs_d_128,
5478 (bc_v2i64 (v16i1sextv16i8)),
5479 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5480 (VPABSBrr128 VR128:$src)>;
5482 (bc_v2i64 (v8i1sextv8i16)),
5483 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5484 (VPABSWrr128 VR128:$src)>;
5486 (bc_v2i64 (v4i1sextv4i32)),
5487 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5488 (VPABSDrr128 VR128:$src)>;
5491 let Predicates = [HasAVX2] in {
5492 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5493 int_x86_avx2_pabs_b>, VEX, VEX_L;
5494 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5495 int_x86_avx2_pabs_w>, VEX, VEX_L;
5496 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5497 int_x86_avx2_pabs_d>, VEX, VEX_L;
5500 (bc_v4i64 (v32i1sextv32i8)),
5501 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5502 (VPABSBrr256 VR256:$src)>;
5504 (bc_v4i64 (v16i1sextv16i16)),
5505 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5506 (VPABSWrr256 VR256:$src)>;
5508 (bc_v4i64 (v8i1sextv8i32)),
5509 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5510 (VPABSDrr256 VR256:$src)>;
5513 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", int_x86_ssse3_pabs_b_128,
5515 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", int_x86_ssse3_pabs_w_128,
5517 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", int_x86_ssse3_pabs_d_128,
5520 let Predicates = [HasSSSE3] in {
5522 (bc_v2i64 (v16i1sextv16i8)),
5523 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5524 (PABSBrr128 VR128:$src)>;
5526 (bc_v2i64 (v8i1sextv8i16)),
5527 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5528 (PABSWrr128 VR128:$src)>;
5530 (bc_v2i64 (v4i1sextv4i32)),
5531 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5532 (PABSDrr128 VR128:$src)>;
5535 //===---------------------------------------------------------------------===//
5536 // SSSE3 - Packed Binary Operator Instructions
5537 //===---------------------------------------------------------------------===//
5539 let Sched = WriteVecALU in {
5540 def SSE_PHADDSUBD : OpndItins<
5541 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5543 def SSE_PHADDSUBSW : OpndItins<
5544 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5546 def SSE_PHADDSUBW : OpndItins<
5547 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5550 let Sched = WriteShuffle in
5551 def SSE_PSHUFB : OpndItins<
5552 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5554 let Sched = WriteVecALU in
5555 def SSE_PSIGN : OpndItins<
5556 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5558 let Sched = WriteVecIMul in
5559 def SSE_PMULHRSW : OpndItins<
5560 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5563 /// SS3I_binop_rm - Simple SSSE3 bin op
5564 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5565 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5566 X86MemOperand x86memop, OpndItins itins,
5568 let isCommutable = 1 in
5569 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5570 (ins RC:$src1, RC:$src2),
5572 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5573 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5574 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5575 Sched<[itins.Sched]>;
5576 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5577 (ins RC:$src1, x86memop:$src2),
5579 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5580 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5582 (OpVT (OpNode RC:$src1,
5583 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5584 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5587 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5588 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5589 Intrinsic IntId128, OpndItins itins,
5590 PatFrag ld_frag, bit Is2Addr = 1> {
5591 let isCommutable = 1 in
5592 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5593 (ins VR128:$src1, VR128:$src2),
5595 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5596 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5597 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5598 Sched<[itins.Sched]>;
5599 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5600 (ins VR128:$src1, i128mem:$src2),
5602 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5603 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5605 (IntId128 VR128:$src1,
5606 (bitconvert (ld_frag addr:$src2))))]>,
5607 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5610 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5612 X86FoldableSchedWrite Sched> {
5613 let isCommutable = 1 in
5614 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5615 (ins VR256:$src1, VR256:$src2),
5616 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5617 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5619 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5620 (ins VR256:$src1, i256mem:$src2),
5621 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5623 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5624 Sched<[Sched.Folded, ReadAfterLd]>;
5627 let ImmT = NoImm, Predicates = [HasAVX] in {
5628 let isCommutable = 0 in {
5629 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5631 SSE_PHADDSUBW, 0>, VEX_4V;
5632 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5634 SSE_PHADDSUBD, 0>, VEX_4V;
5635 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5637 SSE_PHADDSUBW, 0>, VEX_4V;
5638 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5640 SSE_PHADDSUBD, 0>, VEX_4V;
5641 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5643 SSE_PSIGN, 0>, VEX_4V;
5644 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5646 SSE_PSIGN, 0>, VEX_4V;
5647 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5649 SSE_PSIGN, 0>, VEX_4V;
5650 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5652 SSE_PSHUFB, 0>, VEX_4V;
5653 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5654 int_x86_ssse3_phadd_sw_128,
5655 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5656 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5657 int_x86_ssse3_phsub_sw_128,
5658 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5659 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5660 int_x86_ssse3_pmadd_ub_sw_128,
5661 SSE_PMADD, loadv2i64, 0>, VEX_4V;
5663 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5664 int_x86_ssse3_pmul_hr_sw_128,
5665 SSE_PMULHRSW, loadv2i64, 0>, VEX_4V;
5668 let ImmT = NoImm, Predicates = [HasAVX2] in {
5669 let isCommutable = 0 in {
5670 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5672 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5673 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5675 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5676 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5678 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5679 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5681 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5682 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5684 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5685 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5687 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5688 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5690 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5691 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5693 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5694 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5695 int_x86_avx2_phadd_sw,
5696 WriteVecALU>, VEX_4V, VEX_L;
5697 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5698 int_x86_avx2_phsub_sw,
5699 WriteVecALU>, VEX_4V, VEX_L;
5700 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5701 int_x86_avx2_pmadd_ub_sw,
5702 WriteVecIMul>, VEX_4V, VEX_L;
5704 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5705 int_x86_avx2_pmul_hr_sw,
5706 WriteVecIMul>, VEX_4V, VEX_L;
5709 // None of these have i8 immediate fields.
5710 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5711 let isCommutable = 0 in {
5712 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5713 memopv2i64, i128mem, SSE_PHADDSUBW>;
5714 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5715 memopv2i64, i128mem, SSE_PHADDSUBD>;
5716 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5717 memopv2i64, i128mem, SSE_PHADDSUBW>;
5718 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5719 memopv2i64, i128mem, SSE_PHADDSUBD>;
5720 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5721 memopv2i64, i128mem, SSE_PSIGN>;
5722 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5723 memopv2i64, i128mem, SSE_PSIGN>;
5724 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5725 memopv2i64, i128mem, SSE_PSIGN>;
5726 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5727 memopv2i64, i128mem, SSE_PSHUFB>;
5728 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5729 int_x86_ssse3_phadd_sw_128,
5730 SSE_PHADDSUBSW, memopv2i64>;
5731 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5732 int_x86_ssse3_phsub_sw_128,
5733 SSE_PHADDSUBSW, memopv2i64>;
5734 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5735 int_x86_ssse3_pmadd_ub_sw_128,
5736 SSE_PMADD, memopv2i64>;
5738 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5739 int_x86_ssse3_pmul_hr_sw_128,
5740 SSE_PMULHRSW, memopv2i64>;
5743 //===---------------------------------------------------------------------===//
5744 // SSSE3 - Packed Align Instruction Patterns
5745 //===---------------------------------------------------------------------===//
5747 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5748 let hasSideEffects = 0 in {
5749 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5750 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
5752 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5754 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5755 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5757 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5758 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
5760 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5762 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5763 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5767 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5768 let hasSideEffects = 0 in {
5769 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5770 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
5772 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5773 []>, Sched<[WriteShuffle]>;
5775 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5776 (ins VR256:$src1, i256mem:$src2, u8imm:$src3),
5778 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5779 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5783 let Predicates = [HasAVX] in
5784 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5785 let Predicates = [HasAVX2] in
5786 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5787 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5788 defm PALIGN : ssse3_palignr<"palignr">;
5790 let Predicates = [HasAVX2] in {
5791 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5792 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5793 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5794 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5795 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5796 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5797 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5798 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5801 let Predicates = [HasAVX] in {
5802 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5803 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5804 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5805 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5806 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5807 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5808 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5809 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5812 let Predicates = [UseSSSE3] in {
5813 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5814 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5815 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5816 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5817 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5818 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5819 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5820 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5823 //===---------------------------------------------------------------------===//
5824 // SSSE3 - Thread synchronization
5825 //===---------------------------------------------------------------------===//
5827 let SchedRW = [WriteSystem] in {
5828 let usesCustomInserter = 1 in {
5829 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5830 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5831 Requires<[HasSSE3]>;
5834 let Uses = [EAX, ECX, EDX] in
5835 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5836 TB, Requires<[HasSSE3]>;
5837 let Uses = [ECX, EAX] in
5838 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5839 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5840 TB, Requires<[HasSSE3]>;
5843 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5844 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5846 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5847 Requires<[Not64BitMode]>;
5848 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5849 Requires<[In64BitMode]>;
5851 //===----------------------------------------------------------------------===//
5852 // SSE4.1 - Packed Move with Sign/Zero Extend
5853 //===----------------------------------------------------------------------===//
5855 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
5856 RegisterClass OutRC, RegisterClass InRC,
5858 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
5859 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5861 Sched<[itins.Sched]>;
5863 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
5864 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5866 itins.rm>, Sched<[itins.Sched.Folded]>;
5869 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
5870 X86MemOperand MemOp, X86MemOperand MemYOp,
5871 OpndItins SSEItins, OpndItins AVXItins,
5872 OpndItins AVX2Itins> {
5873 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
5874 let Predicates = [HasAVX, NoVLX] in
5875 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
5876 VR128, VR128, AVXItins>, VEX;
5877 let Predicates = [HasAVX2, NoVLX] in
5878 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
5879 VR256, VR128, AVX2Itins>, VEX, VEX_L;
5882 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
5883 X86MemOperand MemOp, X86MemOperand MemYOp> {
5884 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
5886 SSE_INTALU_ITINS_SHUFF_P,
5887 DEFAULT_ITINS_SHUFFLESCHED,
5888 DEFAULT_ITINS_SHUFFLESCHED>;
5889 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
5890 !strconcat("pmovzx", OpcodeStr),
5892 SSE_INTALU_ITINS_SHUFF_P,
5893 DEFAULT_ITINS_SHUFFLESCHED,
5894 DEFAULT_ITINS_SHUFFLESCHED>;
5897 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
5898 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
5899 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
5901 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
5902 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
5904 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
5907 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
5908 // Register-Register patterns
5909 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5910 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
5911 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
5912 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
5913 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
5914 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
5916 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5917 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
5918 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
5919 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
5921 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5922 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
5924 // On AVX2, we also support 256bit inputs.
5925 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
5926 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5927 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
5928 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5929 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
5930 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5932 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
5933 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5934 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
5935 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5937 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
5938 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5940 // Simple Register-Memory patterns
5941 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5942 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5943 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5944 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5945 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5946 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5948 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5949 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5950 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5951 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5953 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5954 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5956 // AVX2 Register-Memory patterns
5957 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5958 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5959 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5960 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5961 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5962 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5963 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5964 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5966 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5967 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5968 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5969 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5970 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5971 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5972 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5973 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5975 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
5976 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5977 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
5978 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5979 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5980 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5981 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5982 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5984 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5985 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5986 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5987 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5988 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5989 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5990 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5991 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5993 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5994 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5995 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5996 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5997 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5998 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5999 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6000 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
6002 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6003 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6004 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6005 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6006 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6007 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6008 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6009 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
6012 let Predicates = [HasAVX2, NoVLX] in {
6013 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
6014 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
6017 // SSE4.1/AVX patterns.
6018 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
6019 SDNode ExtOp, PatFrag ExtLoad16> {
6020 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6021 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6022 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6023 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6024 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6025 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6027 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6028 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6029 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6030 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6032 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6033 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6035 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6036 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6037 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6038 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6039 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6040 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6042 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6043 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6044 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6045 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6047 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6048 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6050 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6051 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6052 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6053 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6054 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6055 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6056 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6057 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6058 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6059 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6061 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6062 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6063 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6064 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6065 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6066 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6067 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6068 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6070 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6071 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6072 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6073 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6074 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6075 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6076 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6077 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6079 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6080 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6081 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6082 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6083 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6084 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6085 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6086 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6087 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6088 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6090 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6091 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6092 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6093 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6094 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6095 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6096 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6097 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6099 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6100 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6101 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6102 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6103 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6104 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6105 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6106 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6107 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6108 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6111 let Predicates = [HasAVX, NoVLX] in {
6112 defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
6113 defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
6116 let Predicates = [UseSSE41] in {
6117 defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
6118 defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
6121 //===----------------------------------------------------------------------===//
6122 // SSE4.1 - Extract Instructions
6123 //===----------------------------------------------------------------------===//
6125 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6126 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6127 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6128 (ins VR128:$src1, u8imm:$src2),
6129 !strconcat(OpcodeStr,
6130 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6131 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6133 Sched<[WriteShuffle]>;
6134 let hasSideEffects = 0, mayStore = 1,
6135 SchedRW = [WriteShuffleLd, WriteRMW] in
6136 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6137 (ins i8mem:$dst, VR128:$src1, u8imm:$src2),
6138 !strconcat(OpcodeStr,
6139 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6140 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6141 imm:$src2)))), addr:$dst)]>;
6144 let Predicates = [HasAVX] in
6145 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6147 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6150 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6151 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6152 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6153 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6154 (ins VR128:$src1, u8imm:$src2),
6155 !strconcat(OpcodeStr,
6156 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6157 []>, Sched<[WriteShuffle]>;
6159 let hasSideEffects = 0, mayStore = 1,
6160 SchedRW = [WriteShuffleLd, WriteRMW] in
6161 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6162 (ins i16mem:$dst, VR128:$src1, u8imm:$src2),
6163 !strconcat(OpcodeStr,
6164 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6165 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6166 imm:$src2)))), addr:$dst)]>;
6169 let Predicates = [HasAVX] in
6170 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6172 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6175 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6176 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6177 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6178 (ins VR128:$src1, u8imm:$src2),
6179 !strconcat(OpcodeStr,
6180 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6182 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6183 Sched<[WriteShuffle]>;
6184 let SchedRW = [WriteShuffleLd, WriteRMW] in
6185 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6186 (ins i32mem:$dst, VR128:$src1, u8imm:$src2),
6187 !strconcat(OpcodeStr,
6188 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6189 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6193 let Predicates = [HasAVX] in
6194 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6196 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6198 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6199 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6200 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6201 (ins VR128:$src1, u8imm:$src2),
6202 !strconcat(OpcodeStr,
6203 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6205 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6206 Sched<[WriteShuffle]>, REX_W;
6207 let SchedRW = [WriteShuffleLd, WriteRMW] in
6208 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6209 (ins i64mem:$dst, VR128:$src1, u8imm:$src2),
6210 !strconcat(OpcodeStr,
6211 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6212 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6213 addr:$dst)]>, REX_W;
6216 let Predicates = [HasAVX] in
6217 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6219 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6221 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6223 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6224 OpndItins itins = DEFAULT_ITINS> {
6225 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6226 (ins VR128:$src1, u8imm:$src2),
6227 !strconcat(OpcodeStr,
6228 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6229 [(set GR32orGR64:$dst,
6230 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6231 itins.rr>, Sched<[WriteFBlend]>;
6232 let SchedRW = [WriteFBlendLd, WriteRMW] in
6233 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6234 (ins f32mem:$dst, VR128:$src1, u8imm:$src2),
6235 !strconcat(OpcodeStr,
6236 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6237 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6238 addr:$dst)], itins.rm>;
6241 let ExeDomain = SSEPackedSingle in {
6242 let Predicates = [UseAVX] in
6243 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6244 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6247 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6248 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6251 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6253 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6256 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6257 Requires<[UseSSE41]>;
6259 //===----------------------------------------------------------------------===//
6260 // SSE4.1 - Insert Instructions
6261 //===----------------------------------------------------------------------===//
6263 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6264 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6265 (ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
6267 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6269 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6271 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6272 Sched<[WriteShuffle]>;
6273 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6274 (ins VR128:$src1, i8mem:$src2, u8imm:$src3),
6276 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6278 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6280 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6281 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6284 let Predicates = [HasAVX] in
6285 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6286 let Constraints = "$src1 = $dst" in
6287 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6289 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6290 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6291 (ins VR128:$src1, GR32:$src2, u8imm:$src3),
6293 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6297 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6298 Sched<[WriteShuffle]>;
6299 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6300 (ins VR128:$src1, i32mem:$src2, u8imm:$src3),
6302 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6304 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6306 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6307 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6310 let Predicates = [HasAVX] in
6311 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6312 let Constraints = "$src1 = $dst" in
6313 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6315 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6316 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6317 (ins VR128:$src1, GR64:$src2, u8imm:$src3),
6319 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6321 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6323 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6324 Sched<[WriteShuffle]>;
6325 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6326 (ins VR128:$src1, i64mem:$src2, u8imm:$src3),
6328 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6330 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6332 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6333 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6336 let Predicates = [HasAVX] in
6337 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6338 let Constraints = "$src1 = $dst" in
6339 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6341 // insertps has a few different modes, there's the first two here below which
6342 // are optimized inserts that won't zero arbitrary elements in the destination
6343 // vector. The next one matches the intrinsic and could zero arbitrary elements
6344 // in the target vector.
6345 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6346 OpndItins itins = DEFAULT_ITINS> {
6347 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6348 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
6350 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6352 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6354 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6355 Sched<[WriteFShuffle]>;
6356 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6357 (ins VR128:$src1, f32mem:$src2, u8imm:$src3),
6359 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6361 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6363 (X86insertps VR128:$src1,
6364 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6365 imm:$src3))], itins.rm>,
6366 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6369 let ExeDomain = SSEPackedSingle in {
6370 let Predicates = [UseAVX] in
6371 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6372 let Constraints = "$src1 = $dst" in
6373 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6376 let Predicates = [UseSSE41] in {
6377 // If we're inserting an element from a load or a null pshuf of a load,
6378 // fold the load into the insertps instruction.
6379 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6380 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6382 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6383 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6384 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6385 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6388 let Predicates = [UseAVX] in {
6389 // If we're inserting an element from a vbroadcast of a load, fold the
6390 // load into the X86insertps instruction.
6391 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6392 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6393 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6394 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6395 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6396 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6399 //===----------------------------------------------------------------------===//
6400 // SSE4.1 - Round Instructions
6401 //===----------------------------------------------------------------------===//
6403 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6404 X86MemOperand x86memop, RegisterClass RC,
6405 PatFrag mem_frag32, PatFrag mem_frag64,
6406 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6407 let ExeDomain = SSEPackedSingle in {
6408 // Intrinsic operation, reg.
6409 // Vector intrinsic operation, reg
6410 def PSr : SS4AIi8<opcps, MRMSrcReg,
6411 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6412 !strconcat(OpcodeStr,
6413 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6414 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6415 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6417 // Vector intrinsic operation, mem
6418 def PSm : SS4AIi8<opcps, MRMSrcMem,
6419 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6420 !strconcat(OpcodeStr,
6421 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6423 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6424 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6425 } // ExeDomain = SSEPackedSingle
6427 let ExeDomain = SSEPackedDouble in {
6428 // Vector intrinsic operation, reg
6429 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6430 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6431 !strconcat(OpcodeStr,
6432 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6433 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6434 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6436 // Vector intrinsic operation, mem
6437 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6438 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6439 !strconcat(OpcodeStr,
6440 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6442 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6443 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6444 } // ExeDomain = SSEPackedDouble
6447 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6450 Intrinsic F64Int, bit Is2Addr = 1> {
6451 let ExeDomain = GenericDomain in {
6453 let hasSideEffects = 0 in
6454 def SSr : SS4AIi8<opcss, MRMSrcReg,
6455 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3),
6457 !strconcat(OpcodeStr,
6458 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6459 !strconcat(OpcodeStr,
6460 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6461 []>, Sched<[WriteFAdd]>;
6463 // Intrinsic operation, reg.
6464 let isCodeGenOnly = 1 in
6465 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6466 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6468 !strconcat(OpcodeStr,
6469 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6470 !strconcat(OpcodeStr,
6471 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6472 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6475 // Intrinsic operation, mem.
6476 def SSm : SS4AIi8<opcss, MRMSrcMem,
6477 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32u8imm:$src3),
6479 !strconcat(OpcodeStr,
6480 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6481 !strconcat(OpcodeStr,
6482 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6484 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6485 Sched<[WriteFAddLd, ReadAfterLd]>;
6488 let hasSideEffects = 0 in
6489 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6490 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3),
6492 !strconcat(OpcodeStr,
6493 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6494 !strconcat(OpcodeStr,
6495 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6496 []>, Sched<[WriteFAdd]>;
6498 // Intrinsic operation, reg.
6499 let isCodeGenOnly = 1 in
6500 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6501 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6503 !strconcat(OpcodeStr,
6504 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6505 !strconcat(OpcodeStr,
6506 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6507 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6510 // Intrinsic operation, mem.
6511 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6512 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32u8imm:$src3),
6514 !strconcat(OpcodeStr,
6515 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6516 !strconcat(OpcodeStr,
6517 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6519 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6520 Sched<[WriteFAddLd, ReadAfterLd]>;
6521 } // ExeDomain = GenericDomain
6524 // FP round - roundss, roundps, roundsd, roundpd
6525 let Predicates = [HasAVX] in {
6527 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6528 loadv4f32, loadv2f64,
6529 int_x86_sse41_round_ps,
6530 int_x86_sse41_round_pd>, VEX;
6531 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6532 loadv8f32, loadv4f64,
6533 int_x86_avx_round_ps_256,
6534 int_x86_avx_round_pd_256>, VEX, VEX_L;
6535 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6536 int_x86_sse41_round_ss,
6537 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6540 let Predicates = [UseAVX] in {
6541 def : Pat<(ffloor FR32:$src),
6542 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6543 def : Pat<(f64 (ffloor FR64:$src)),
6544 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6545 def : Pat<(f32 (fnearbyint FR32:$src)),
6546 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6547 def : Pat<(f64 (fnearbyint FR64:$src)),
6548 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6549 def : Pat<(f32 (fceil FR32:$src)),
6550 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6551 def : Pat<(f64 (fceil FR64:$src)),
6552 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6553 def : Pat<(f32 (frint FR32:$src)),
6554 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6555 def : Pat<(f64 (frint FR64:$src)),
6556 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6557 def : Pat<(f32 (ftrunc FR32:$src)),
6558 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6559 def : Pat<(f64 (ftrunc FR64:$src)),
6560 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6563 let Predicates = [HasAVX] in {
6564 def : Pat<(v4f32 (ffloor VR128:$src)),
6565 (VROUNDPSr VR128:$src, (i32 0x1))>;
6566 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6567 (VROUNDPSr VR128:$src, (i32 0xC))>;
6568 def : Pat<(v4f32 (fceil VR128:$src)),
6569 (VROUNDPSr VR128:$src, (i32 0x2))>;
6570 def : Pat<(v4f32 (frint VR128:$src)),
6571 (VROUNDPSr VR128:$src, (i32 0x4))>;
6572 def : Pat<(v4f32 (ftrunc VR128:$src)),
6573 (VROUNDPSr VR128:$src, (i32 0x3))>;
6575 def : Pat<(v2f64 (ffloor VR128:$src)),
6576 (VROUNDPDr VR128:$src, (i32 0x1))>;
6577 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6578 (VROUNDPDr VR128:$src, (i32 0xC))>;
6579 def : Pat<(v2f64 (fceil VR128:$src)),
6580 (VROUNDPDr VR128:$src, (i32 0x2))>;
6581 def : Pat<(v2f64 (frint VR128:$src)),
6582 (VROUNDPDr VR128:$src, (i32 0x4))>;
6583 def : Pat<(v2f64 (ftrunc VR128:$src)),
6584 (VROUNDPDr VR128:$src, (i32 0x3))>;
6586 def : Pat<(v8f32 (ffloor VR256:$src)),
6587 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6588 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6589 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6590 def : Pat<(v8f32 (fceil VR256:$src)),
6591 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6592 def : Pat<(v8f32 (frint VR256:$src)),
6593 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6594 def : Pat<(v8f32 (ftrunc VR256:$src)),
6595 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6597 def : Pat<(v4f64 (ffloor VR256:$src)),
6598 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6599 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6600 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6601 def : Pat<(v4f64 (fceil VR256:$src)),
6602 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6603 def : Pat<(v4f64 (frint VR256:$src)),
6604 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6605 def : Pat<(v4f64 (ftrunc VR256:$src)),
6606 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6609 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6610 memopv4f32, memopv2f64,
6611 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6612 let Constraints = "$src1 = $dst" in
6613 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6614 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6616 let Predicates = [UseSSE41] in {
6617 def : Pat<(ffloor FR32:$src),
6618 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6619 def : Pat<(f64 (ffloor FR64:$src)),
6620 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6621 def : Pat<(f32 (fnearbyint FR32:$src)),
6622 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6623 def : Pat<(f64 (fnearbyint FR64:$src)),
6624 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6625 def : Pat<(f32 (fceil FR32:$src)),
6626 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6627 def : Pat<(f64 (fceil FR64:$src)),
6628 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6629 def : Pat<(f32 (frint FR32:$src)),
6630 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6631 def : Pat<(f64 (frint FR64:$src)),
6632 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6633 def : Pat<(f32 (ftrunc FR32:$src)),
6634 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6635 def : Pat<(f64 (ftrunc FR64:$src)),
6636 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6638 def : Pat<(v4f32 (ffloor VR128:$src)),
6639 (ROUNDPSr VR128:$src, (i32 0x1))>;
6640 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6641 (ROUNDPSr VR128:$src, (i32 0xC))>;
6642 def : Pat<(v4f32 (fceil VR128:$src)),
6643 (ROUNDPSr VR128:$src, (i32 0x2))>;
6644 def : Pat<(v4f32 (frint VR128:$src)),
6645 (ROUNDPSr VR128:$src, (i32 0x4))>;
6646 def : Pat<(v4f32 (ftrunc VR128:$src)),
6647 (ROUNDPSr VR128:$src, (i32 0x3))>;
6649 def : Pat<(v2f64 (ffloor VR128:$src)),
6650 (ROUNDPDr VR128:$src, (i32 0x1))>;
6651 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6652 (ROUNDPDr VR128:$src, (i32 0xC))>;
6653 def : Pat<(v2f64 (fceil VR128:$src)),
6654 (ROUNDPDr VR128:$src, (i32 0x2))>;
6655 def : Pat<(v2f64 (frint VR128:$src)),
6656 (ROUNDPDr VR128:$src, (i32 0x4))>;
6657 def : Pat<(v2f64 (ftrunc VR128:$src)),
6658 (ROUNDPDr VR128:$src, (i32 0x3))>;
6661 //===----------------------------------------------------------------------===//
6662 // SSE4.1 - Packed Bit Test
6663 //===----------------------------------------------------------------------===//
6665 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6666 // the intel intrinsic that corresponds to this.
6667 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6668 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6669 "vptest\t{$src2, $src1|$src1, $src2}",
6670 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6671 Sched<[WriteVecLogic]>, VEX;
6672 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6673 "vptest\t{$src2, $src1|$src1, $src2}",
6674 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6675 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6677 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6678 "vptest\t{$src2, $src1|$src1, $src2}",
6679 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6680 Sched<[WriteVecLogic]>, VEX, VEX_L;
6681 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6682 "vptest\t{$src2, $src1|$src1, $src2}",
6683 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6684 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6687 let Defs = [EFLAGS] in {
6688 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6689 "ptest\t{$src2, $src1|$src1, $src2}",
6690 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6691 Sched<[WriteVecLogic]>;
6692 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6693 "ptest\t{$src2, $src1|$src1, $src2}",
6694 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6695 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6698 // The bit test instructions below are AVX only
6699 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6700 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6701 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6702 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6703 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6704 Sched<[WriteVecLogic]>, VEX;
6705 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6706 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6707 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6708 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6711 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6712 let ExeDomain = SSEPackedSingle in {
6713 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6714 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6717 let ExeDomain = SSEPackedDouble in {
6718 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6719 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6724 //===----------------------------------------------------------------------===//
6725 // SSE4.1 - Misc Instructions
6726 //===----------------------------------------------------------------------===//
6728 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6729 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6730 "popcnt{w}\t{$src, $dst|$dst, $src}",
6731 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6732 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6734 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6735 "popcnt{w}\t{$src, $dst|$dst, $src}",
6736 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6737 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6738 Sched<[WriteFAddLd]>, OpSize16, XS;
6740 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6741 "popcnt{l}\t{$src, $dst|$dst, $src}",
6742 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6743 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6746 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6747 "popcnt{l}\t{$src, $dst|$dst, $src}",
6748 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6749 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6750 Sched<[WriteFAddLd]>, OpSize32, XS;
6752 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6753 "popcnt{q}\t{$src, $dst|$dst, $src}",
6754 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6755 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6756 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6757 "popcnt{q}\t{$src, $dst|$dst, $src}",
6758 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6759 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6760 Sched<[WriteFAddLd]>, XS;
6765 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6766 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6767 Intrinsic IntId128, PatFrag ld_frag,
6768 X86FoldableSchedWrite Sched> {
6769 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6771 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6772 [(set VR128:$dst, (IntId128 VR128:$src))]>,
6774 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6776 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6778 (IntId128 (bitconvert (ld_frag addr:$src))))]>,
6779 Sched<[Sched.Folded]>;
6782 // PHMIN has the same profile as PSAD, thus we use the same scheduling
6783 // model, although the naming is misleading.
6784 let Predicates = [HasAVX] in
6785 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6786 int_x86_sse41_phminposuw, loadv2i64,
6788 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6789 int_x86_sse41_phminposuw, memopv2i64,
6792 /// SS48I_binop_rm - Simple SSE41 binary operator.
6793 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6794 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6795 X86MemOperand x86memop, bit Is2Addr = 1,
6796 OpndItins itins = SSE_INTALU_ITINS_P> {
6797 let isCommutable = 1 in
6798 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6799 (ins RC:$src1, RC:$src2),
6801 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6802 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6803 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6804 Sched<[itins.Sched]>;
6805 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6806 (ins RC:$src1, x86memop:$src2),
6808 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6809 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6811 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
6812 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6815 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
6817 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
6818 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
6819 PatFrag memop_frag, X86MemOperand x86memop,
6821 bit IsCommutable = 0, bit Is2Addr = 1> {
6822 let isCommutable = IsCommutable in
6823 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6824 (ins RC:$src1, RC:$src2),
6826 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6827 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6828 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
6829 Sched<[itins.Sched]>;
6830 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6831 (ins RC:$src1, x86memop:$src2),
6833 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6834 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6835 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
6836 (bitconvert (memop_frag addr:$src2)))))]>,
6837 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6840 let Predicates = [HasAVX, NoVLX] in {
6841 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", smin, v16i8, VR128,
6842 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6844 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", smin, v4i32, VR128,
6845 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6847 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", umin, v4i32, VR128,
6848 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6850 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", umin, v8i16, VR128,
6851 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6853 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v16i8, VR128,
6854 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6856 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v4i32, VR128,
6857 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6859 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", umax, v4i32, VR128,
6860 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6862 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v8i16, VR128,
6863 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6865 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
6866 VR128, loadv2i64, i128mem,
6867 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
6870 let Predicates = [HasAVX2, NoVLX] in {
6871 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", smin, v32i8, VR256,
6872 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6874 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", smin, v8i32, VR256,
6875 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6877 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", umin, v8i32, VR256,
6878 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6880 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", umin, v16i16, VR256,
6881 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6883 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", smax, v32i8, VR256,
6884 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6886 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", smax, v8i32, VR256,
6887 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6889 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", umax, v8i32, VR256,
6890 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6892 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", umax, v16i16, VR256,
6893 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6895 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
6896 VR256, loadv4i64, i256mem,
6897 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
6900 let Constraints = "$src1 = $dst" in {
6901 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", smin, v16i8, VR128,
6902 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6903 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", smin, v4i32, VR128,
6904 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6905 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", umin, v4i32, VR128,
6906 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6907 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", umin, v8i16, VR128,
6908 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6909 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", smax, v16i8, VR128,
6910 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6911 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", smax, v4i32, VR128,
6912 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6913 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", umax, v4i32, VR128,
6914 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6915 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", umax, v8i16, VR128,
6916 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6917 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
6918 VR128, memopv2i64, i128mem,
6919 SSE_INTMUL_ITINS_P, 1>;
6922 let Predicates = [HasAVX, NoVLX] in {
6923 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6924 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
6926 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6927 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6930 let Predicates = [HasAVX2] in {
6931 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6932 loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
6934 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6935 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6939 let Constraints = "$src1 = $dst" in {
6940 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6941 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6942 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6943 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6946 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6947 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6948 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6949 X86MemOperand x86memop, bit Is2Addr = 1,
6950 OpndItins itins = DEFAULT_ITINS> {
6951 let isCommutable = 1 in
6952 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6953 (ins RC:$src1, RC:$src2, u8imm:$src3),
6955 !strconcat(OpcodeStr,
6956 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6957 !strconcat(OpcodeStr,
6958 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6959 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6960 Sched<[itins.Sched]>;
6961 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6962 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6964 !strconcat(OpcodeStr,
6965 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6966 !strconcat(OpcodeStr,
6967 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6970 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6971 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6974 /// SS41I_binop_rmi - SSE 4.1 binary operator with 8-bit immediate
6975 multiclass SS41I_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
6976 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6977 X86MemOperand x86memop, bit Is2Addr = 1,
6978 OpndItins itins = DEFAULT_ITINS> {
6979 let isCommutable = 1 in
6980 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6981 (ins RC:$src1, RC:$src2, u8imm:$src3),
6983 !strconcat(OpcodeStr,
6984 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6985 !strconcat(OpcodeStr,
6986 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6987 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))],
6988 itins.rr>, Sched<[itins.Sched]>;
6989 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6990 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6992 !strconcat(OpcodeStr,
6993 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6994 !strconcat(OpcodeStr,
6995 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6997 (OpVT (OpNode RC:$src1,
6998 (bitconvert (memop_frag addr:$src2)), imm:$src3)))], itins.rm>,
6999 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7002 let Predicates = [HasAVX] in {
7003 let isCommutable = 0 in {
7004 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7005 VR128, loadv2i64, i128mem, 0,
7006 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7009 let ExeDomain = SSEPackedSingle in {
7010 defm VBLENDPS : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v4f32,
7011 VR128, loadv4f32, f128mem, 0,
7012 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7013 defm VBLENDPSY : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v8f32,
7014 VR256, loadv8f32, f256mem, 0,
7015 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7017 let ExeDomain = SSEPackedDouble in {
7018 defm VBLENDPD : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v2f64,
7019 VR128, loadv2f64, f128mem, 0,
7020 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7021 defm VBLENDPDY : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v4f64,
7022 VR256, loadv4f64, f256mem, 0,
7023 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7025 defm VPBLENDW : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v8i16,
7026 VR128, loadv2i64, i128mem, 0,
7027 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7029 let ExeDomain = SSEPackedSingle in
7030 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7031 VR128, loadv4f32, f128mem, 0,
7032 SSE_DPPS_ITINS>, VEX_4V;
7033 let ExeDomain = SSEPackedDouble in
7034 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7035 VR128, loadv2f64, f128mem, 0,
7036 SSE_DPPS_ITINS>, VEX_4V;
7037 let ExeDomain = SSEPackedSingle in
7038 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7039 VR256, loadv8f32, i256mem, 0,
7040 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7043 let Predicates = [HasAVX2] in {
7044 let isCommutable = 0 in {
7045 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7046 VR256, loadv4i64, i256mem, 0,
7047 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7049 defm VPBLENDWY : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v16i16,
7050 VR256, loadv4i64, i256mem, 0,
7051 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7054 let Constraints = "$src1 = $dst" in {
7055 let isCommutable = 0 in {
7056 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7057 VR128, memopv2i64, i128mem,
7058 1, SSE_MPSADBW_ITINS>;
7060 let ExeDomain = SSEPackedSingle in
7061 defm BLENDPS : SS41I_binop_rmi<0x0C, "blendps", X86Blendi, v4f32,
7062 VR128, memopv4f32, f128mem,
7063 1, SSE_INTALU_ITINS_FBLEND_P>;
7064 let ExeDomain = SSEPackedDouble in
7065 defm BLENDPD : SS41I_binop_rmi<0x0D, "blendpd", X86Blendi, v2f64,
7066 VR128, memopv2f64, f128mem,
7067 1, SSE_INTALU_ITINS_FBLEND_P>;
7068 defm PBLENDW : SS41I_binop_rmi<0x0E, "pblendw", X86Blendi, v8i16,
7069 VR128, memopv2i64, i128mem,
7070 1, SSE_INTALU_ITINS_BLEND_P>;
7071 let ExeDomain = SSEPackedSingle in
7072 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7073 VR128, memopv4f32, f128mem, 1,
7075 let ExeDomain = SSEPackedDouble in
7076 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7077 VR128, memopv2f64, f128mem, 1,
7081 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7082 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7083 RegisterClass RC, X86MemOperand x86memop,
7084 PatFrag mem_frag, Intrinsic IntId,
7085 X86FoldableSchedWrite Sched> {
7086 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7087 (ins RC:$src1, RC:$src2, RC:$src3),
7088 !strconcat(OpcodeStr,
7089 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7090 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7091 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7094 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7095 (ins RC:$src1, x86memop:$src2, RC:$src3),
7096 !strconcat(OpcodeStr,
7097 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7099 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7101 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7102 Sched<[Sched.Folded, ReadAfterLd]>;
7105 let Predicates = [HasAVX] in {
7106 let ExeDomain = SSEPackedDouble in {
7107 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7108 loadv2f64, int_x86_sse41_blendvpd,
7110 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7111 loadv4f64, int_x86_avx_blendv_pd_256,
7112 WriteFVarBlend>, VEX_L;
7113 } // ExeDomain = SSEPackedDouble
7114 let ExeDomain = SSEPackedSingle in {
7115 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7116 loadv4f32, int_x86_sse41_blendvps,
7118 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7119 loadv8f32, int_x86_avx_blendv_ps_256,
7120 WriteFVarBlend>, VEX_L;
7121 } // ExeDomain = SSEPackedSingle
7122 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7123 loadv2i64, int_x86_sse41_pblendvb,
7127 let Predicates = [HasAVX2] in {
7128 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7129 loadv4i64, int_x86_avx2_pblendvb,
7130 WriteVarBlend>, VEX_L;
7133 let Predicates = [HasAVX] in {
7134 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7135 (v16i8 VR128:$src2))),
7136 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7137 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7138 (v4i32 VR128:$src2))),
7139 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7140 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7141 (v4f32 VR128:$src2))),
7142 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7143 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7144 (v2i64 VR128:$src2))),
7145 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7146 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7147 (v2f64 VR128:$src2))),
7148 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7149 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7150 (v8i32 VR256:$src2))),
7151 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7152 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7153 (v8f32 VR256:$src2))),
7154 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7155 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7156 (v4i64 VR256:$src2))),
7157 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7158 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7159 (v4f64 VR256:$src2))),
7160 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7163 let Predicates = [HasAVX2] in {
7164 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7165 (v32i8 VR256:$src2))),
7166 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7170 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7171 // on targets where they have equal performance. These were changed to use
7172 // blends because blends have better throughput on SandyBridge and Haswell, but
7173 // movs[s/d] are 1-2 byte shorter instructions.
7174 let Predicates = [UseAVX] in {
7175 let AddedComplexity = 15 in {
7176 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7177 // MOVS{S,D} to the lower bits.
7178 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7179 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7180 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7181 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7182 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7183 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7184 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7185 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7187 // Move low f32 and clear high bits.
7188 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7189 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7191 // Move low f64 and clear high bits.
7192 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7193 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7196 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7197 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7198 (SUBREG_TO_REG (i32 0),
7199 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7201 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7202 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7203 (SUBREG_TO_REG (i64 0),
7204 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7207 // These will incur an FP/int domain crossing penalty, but it may be the only
7208 // way without AVX2. Do not add any complexity because we may be able to match
7209 // more optimal patterns defined earlier in this file.
7210 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7211 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7212 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7213 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7216 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7217 // on targets where they have equal performance. These were changed to use
7218 // blends because blends have better throughput on SandyBridge and Haswell, but
7219 // movs[s/d] are 1-2 byte shorter instructions.
7220 let Predicates = [UseSSE41] in {
7221 // With SSE41 we can use blends for these patterns.
7222 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7223 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7224 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7225 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7226 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7227 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7231 /// SS41I_ternary_int - SSE 4.1 ternary operator
7232 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7233 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7234 X86MemOperand x86memop, Intrinsic IntId,
7235 OpndItins itins = DEFAULT_ITINS> {
7236 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7237 (ins VR128:$src1, VR128:$src2),
7238 !strconcat(OpcodeStr,
7239 "\t{$src2, $dst|$dst, $src2}"),
7240 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7241 itins.rr>, Sched<[itins.Sched]>;
7243 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7244 (ins VR128:$src1, x86memop:$src2),
7245 !strconcat(OpcodeStr,
7246 "\t{$src2, $dst|$dst, $src2}"),
7249 (bitconvert (mem_frag addr:$src2)), XMM0))],
7250 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7254 let ExeDomain = SSEPackedDouble in
7255 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7256 int_x86_sse41_blendvpd,
7257 DEFAULT_ITINS_FBLENDSCHED>;
7258 let ExeDomain = SSEPackedSingle in
7259 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7260 int_x86_sse41_blendvps,
7261 DEFAULT_ITINS_FBLENDSCHED>;
7262 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7263 int_x86_sse41_pblendvb,
7264 DEFAULT_ITINS_VARBLENDSCHED>;
7266 // Aliases with the implicit xmm0 argument
7267 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7268 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7269 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7270 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7271 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7272 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7273 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7274 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7275 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7276 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7277 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7278 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7280 let Predicates = [UseSSE41] in {
7281 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7282 (v16i8 VR128:$src2))),
7283 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7284 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7285 (v4i32 VR128:$src2))),
7286 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7287 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7288 (v4f32 VR128:$src2))),
7289 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7290 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7291 (v2i64 VR128:$src2))),
7292 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7293 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7294 (v2f64 VR128:$src2))),
7295 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7298 let SchedRW = [WriteLoad] in {
7299 let Predicates = [HasAVX] in
7300 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7301 "vmovntdqa\t{$src, $dst|$dst, $src}",
7302 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7304 let Predicates = [HasAVX2] in
7305 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7306 "vmovntdqa\t{$src, $dst|$dst, $src}",
7307 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7309 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7310 "movntdqa\t{$src, $dst|$dst, $src}",
7311 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7314 //===----------------------------------------------------------------------===//
7315 // SSE4.2 - Compare Instructions
7316 //===----------------------------------------------------------------------===//
7318 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7319 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7320 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7321 X86MemOperand x86memop, bit Is2Addr = 1> {
7322 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7323 (ins RC:$src1, RC:$src2),
7325 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7326 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7327 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7328 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7329 (ins RC:$src1, x86memop:$src2),
7331 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7332 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7334 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7337 let Predicates = [HasAVX] in
7338 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7339 loadv2i64, i128mem, 0>, VEX_4V;
7341 let Predicates = [HasAVX2] in
7342 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7343 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7345 let Constraints = "$src1 = $dst" in
7346 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7347 memopv2i64, i128mem>;
7349 //===----------------------------------------------------------------------===//
7350 // SSE4.2 - String/text Processing Instructions
7351 //===----------------------------------------------------------------------===//
7353 // Packed Compare Implicit Length Strings, Return Mask
7354 multiclass pseudo_pcmpistrm<string asm, PatFrag ld_frag> {
7355 def REG : PseudoI<(outs VR128:$dst),
7356 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7357 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7359 def MEM : PseudoI<(outs VR128:$dst),
7360 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7361 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7362 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7365 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7366 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128", loadv2i64>,
7368 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128", memopv2i64>,
7369 Requires<[UseSSE42]>;
7372 multiclass pcmpistrm_SS42AI<string asm> {
7373 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7374 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7375 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7376 []>, Sched<[WritePCmpIStrM]>;
7378 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7379 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7380 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7381 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7384 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7385 let Predicates = [HasAVX] in
7386 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7387 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7390 // Packed Compare Explicit Length Strings, Return Mask
7391 multiclass pseudo_pcmpestrm<string asm, PatFrag ld_frag> {
7392 def REG : PseudoI<(outs VR128:$dst),
7393 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7394 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7395 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7396 def MEM : PseudoI<(outs VR128:$dst),
7397 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7398 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7399 (bc_v16i8 (ld_frag addr:$src3)), EDX, imm:$src5))]>;
7402 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7403 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128", loadv2i64>,
7405 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128", memopv2i64>,
7406 Requires<[UseSSE42]>;
7409 multiclass SS42AI_pcmpestrm<string asm> {
7410 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7411 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7412 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7413 []>, Sched<[WritePCmpEStrM]>;
7415 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7416 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7417 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7418 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7421 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7422 let Predicates = [HasAVX] in
7423 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7424 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7427 // Packed Compare Implicit Length Strings, Return Index
7428 multiclass pseudo_pcmpistri<string asm, PatFrag ld_frag> {
7429 def REG : PseudoI<(outs GR32:$dst),
7430 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7431 [(set GR32:$dst, EFLAGS,
7432 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7433 def MEM : PseudoI<(outs GR32:$dst),
7434 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7435 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7436 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7439 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7440 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI", loadv2i64>,
7442 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI", memopv2i64>,
7443 Requires<[UseSSE42]>;
7446 multiclass SS42AI_pcmpistri<string asm> {
7447 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7448 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7449 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7450 []>, Sched<[WritePCmpIStrI]>;
7452 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7453 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7454 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7455 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7458 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7459 let Predicates = [HasAVX] in
7460 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7461 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7464 // Packed Compare Explicit Length Strings, Return Index
7465 multiclass pseudo_pcmpestri<string asm, PatFrag ld_frag> {
7466 def REG : PseudoI<(outs GR32:$dst),
7467 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7468 [(set GR32:$dst, EFLAGS,
7469 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7470 def MEM : PseudoI<(outs GR32:$dst),
7471 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7472 [(set GR32:$dst, EFLAGS,
7473 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (ld_frag addr:$src3)), EDX,
7477 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7478 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI", loadv2i64>,
7480 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI", memopv2i64>,
7481 Requires<[UseSSE42]>;
7484 multiclass SS42AI_pcmpestri<string asm> {
7485 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7486 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7487 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7488 []>, Sched<[WritePCmpEStrI]>;
7490 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7491 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7492 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7493 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7496 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7497 let Predicates = [HasAVX] in
7498 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7499 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7502 //===----------------------------------------------------------------------===//
7503 // SSE4.2 - CRC Instructions
7504 //===----------------------------------------------------------------------===//
7506 // No CRC instructions have AVX equivalents
7508 // crc intrinsic instruction
7509 // This set of instructions are only rm, the only difference is the size
7511 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7512 RegisterClass RCIn, SDPatternOperator Int> :
7513 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7514 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7515 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7518 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7519 X86MemOperand x86memop, SDPatternOperator Int> :
7520 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7521 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7522 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7523 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7525 let Constraints = "$src1 = $dst" in {
7526 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7527 int_x86_sse42_crc32_32_8>;
7528 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7529 int_x86_sse42_crc32_32_8>;
7530 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7531 int_x86_sse42_crc32_32_16>, OpSize16;
7532 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7533 int_x86_sse42_crc32_32_16>, OpSize16;
7534 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7535 int_x86_sse42_crc32_32_32>, OpSize32;
7536 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7537 int_x86_sse42_crc32_32_32>, OpSize32;
7538 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7539 int_x86_sse42_crc32_64_64>, REX_W;
7540 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7541 int_x86_sse42_crc32_64_64>, REX_W;
7542 let hasSideEffects = 0 in {
7544 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7546 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7551 //===----------------------------------------------------------------------===//
7552 // SHA-NI Instructions
7553 //===----------------------------------------------------------------------===//
7555 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7557 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7558 (ins VR128:$src1, VR128:$src2),
7559 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7561 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7562 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7564 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7565 (ins VR128:$src1, i128mem:$src2),
7566 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7568 (set VR128:$dst, (IntId VR128:$src1,
7569 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7570 (set VR128:$dst, (IntId VR128:$src1,
7571 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7574 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7575 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7576 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7577 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7579 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7580 (i8 imm:$src3)))]>, TA;
7581 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7582 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7583 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7585 (int_x86_sha1rnds4 VR128:$src1,
7586 (bc_v4i32 (memopv2i64 addr:$src2)),
7587 (i8 imm:$src3)))]>, TA;
7589 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7590 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7591 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7594 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7596 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7597 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7600 // Aliases with explicit %xmm0
7601 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7602 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7603 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7604 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7606 //===----------------------------------------------------------------------===//
7607 // AES-NI Instructions
7608 //===----------------------------------------------------------------------===//
7610 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
7611 PatFrag ld_frag, bit Is2Addr = 1> {
7612 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7613 (ins VR128:$src1, VR128:$src2),
7615 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7616 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7617 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7618 Sched<[WriteAESDecEnc]>;
7619 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7620 (ins VR128:$src1, i128mem:$src2),
7622 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7623 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7625 (IntId128 VR128:$src1, (ld_frag addr:$src2)))]>,
7626 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7629 // Perform One Round of an AES Encryption/Decryption Flow
7630 let Predicates = [HasAVX, HasAES] in {
7631 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7632 int_x86_aesni_aesenc, loadv2i64, 0>, VEX_4V;
7633 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7634 int_x86_aesni_aesenclast, loadv2i64, 0>, VEX_4V;
7635 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7636 int_x86_aesni_aesdec, loadv2i64, 0>, VEX_4V;
7637 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7638 int_x86_aesni_aesdeclast, loadv2i64, 0>, VEX_4V;
7641 let Constraints = "$src1 = $dst" in {
7642 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7643 int_x86_aesni_aesenc, memopv2i64>;
7644 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7645 int_x86_aesni_aesenclast, memopv2i64>;
7646 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7647 int_x86_aesni_aesdec, memopv2i64>;
7648 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7649 int_x86_aesni_aesdeclast, memopv2i64>;
7652 // Perform the AES InvMixColumn Transformation
7653 let Predicates = [HasAVX, HasAES] in {
7654 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7656 "vaesimc\t{$src1, $dst|$dst, $src1}",
7658 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7660 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7661 (ins i128mem:$src1),
7662 "vaesimc\t{$src1, $dst|$dst, $src1}",
7663 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7664 Sched<[WriteAESIMCLd]>, VEX;
7666 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7668 "aesimc\t{$src1, $dst|$dst, $src1}",
7670 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7671 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7672 (ins i128mem:$src1),
7673 "aesimc\t{$src1, $dst|$dst, $src1}",
7674 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7675 Sched<[WriteAESIMCLd]>;
7677 // AES Round Key Generation Assist
7678 let Predicates = [HasAVX, HasAES] in {
7679 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7680 (ins VR128:$src1, u8imm:$src2),
7681 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7683 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7684 Sched<[WriteAESKeyGen]>, VEX;
7685 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7686 (ins i128mem:$src1, u8imm:$src2),
7687 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7689 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7690 Sched<[WriteAESKeyGenLd]>, VEX;
7692 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7693 (ins VR128:$src1, u8imm:$src2),
7694 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7696 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7697 Sched<[WriteAESKeyGen]>;
7698 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7699 (ins i128mem:$src1, u8imm:$src2),
7700 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7702 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7703 Sched<[WriteAESKeyGenLd]>;
7705 //===----------------------------------------------------------------------===//
7706 // PCLMUL Instructions
7707 //===----------------------------------------------------------------------===//
7709 // AVX carry-less Multiplication instructions
7710 let isCommutable = 1 in
7711 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7712 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7713 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7715 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7716 Sched<[WriteCLMul]>;
7718 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7719 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7720 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7721 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7722 (loadv2i64 addr:$src2), imm:$src3))]>,
7723 Sched<[WriteCLMulLd, ReadAfterLd]>;
7725 // Carry-less Multiplication instructions
7726 let Constraints = "$src1 = $dst" in {
7727 let isCommutable = 1 in
7728 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7729 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7730 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7732 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7733 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
7735 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7736 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7737 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7738 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7739 (memopv2i64 addr:$src2), imm:$src3))],
7740 IIC_SSE_PCLMULQDQ_RM>,
7741 Sched<[WriteCLMulLd, ReadAfterLd]>;
7742 } // Constraints = "$src1 = $dst"
7745 multiclass pclmul_alias<string asm, int immop> {
7746 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7747 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
7749 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7750 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
7752 def : InstAlias<!strconcat("vpclmul", asm,
7753 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7754 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
7757 def : InstAlias<!strconcat("vpclmul", asm,
7758 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7759 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
7762 defm : pclmul_alias<"hqhq", 0x11>;
7763 defm : pclmul_alias<"hqlq", 0x01>;
7764 defm : pclmul_alias<"lqhq", 0x10>;
7765 defm : pclmul_alias<"lqlq", 0x00>;
7767 //===----------------------------------------------------------------------===//
7768 // SSE4A Instructions
7769 //===----------------------------------------------------------------------===//
7771 let Predicates = [HasSSE4A] in {
7773 let Constraints = "$src = $dst" in {
7774 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
7775 (ins VR128:$src, u8imm:$len, u8imm:$idx),
7776 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7777 [(set VR128:$dst, (X86extrqi VR128:$src, imm:$len,
7779 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7780 (ins VR128:$src, VR128:$mask),
7781 "extrq\t{$mask, $src|$src, $mask}",
7782 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7783 VR128:$mask))]>, PD;
7785 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7786 (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
7787 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7788 [(set VR128:$dst, (X86insertqi VR128:$src, VR128:$src2,
7789 imm:$len, imm:$idx))]>, XD;
7790 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7791 (ins VR128:$src, VR128:$mask),
7792 "insertq\t{$mask, $src|$src, $mask}",
7793 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7794 VR128:$mask))]>, XD;
7797 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7798 "movntss\t{$src, $dst|$dst, $src}",
7799 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7801 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7802 "movntsd\t{$src, $dst|$dst, $src}",
7803 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7806 //===----------------------------------------------------------------------===//
7808 //===----------------------------------------------------------------------===//
7810 //===----------------------------------------------------------------------===//
7811 // VBROADCAST - Load from memory and broadcast to all elements of the
7812 // destination operand
7814 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7815 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
7816 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7817 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7818 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
7820 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
7821 X86MemOperand x86memop, ValueType VT,
7822 PatFrag ld_frag, SchedWrite Sched> :
7823 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7824 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7825 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
7826 Sched<[Sched]>, VEX {
7830 // AVX2 adds register forms
7831 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7832 Intrinsic Int, SchedWrite Sched> :
7833 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7834 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7835 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
7837 let ExeDomain = SSEPackedSingle in {
7838 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
7839 f32mem, v4f32, loadf32, WriteLoad>;
7840 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
7841 f32mem, v8f32, loadf32,
7842 WriteFShuffleLd>, VEX_L;
7844 let ExeDomain = SSEPackedDouble in
7845 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
7846 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
7847 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7848 int_x86_avx_vbroadcastf128_pd_256,
7849 WriteFShuffleLd>, VEX_L;
7851 let ExeDomain = SSEPackedSingle in {
7852 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7853 int_x86_avx2_vbroadcast_ss_ps,
7855 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7856 int_x86_avx2_vbroadcast_ss_ps_256,
7857 WriteFShuffle256>, VEX_L;
7859 let ExeDomain = SSEPackedDouble in
7860 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7861 int_x86_avx2_vbroadcast_sd_pd_256,
7862 WriteFShuffle256>, VEX_L;
7864 let mayLoad = 1, Predicates = [HasAVX2] in
7865 def VBROADCASTI128 : AVX8I<0x5A, MRMSrcMem, (outs VR256:$dst),
7867 "vbroadcasti128\t{$src, $dst|$dst, $src}", []>,
7868 Sched<[WriteLoad]>, VEX, VEX_L;
7870 let Predicates = [HasAVX] in
7871 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7872 (VBROADCASTF128 addr:$src)>;
7875 //===----------------------------------------------------------------------===//
7876 // VINSERTF128 - Insert packed floating-point values
7878 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7879 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7880 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
7881 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7882 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
7884 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7885 (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
7886 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7887 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
7890 let Predicates = [HasAVX] in {
7891 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7893 (VINSERTF128rr VR256:$src1, VR128:$src2,
7894 (INSERT_get_vinsert128_imm VR256:$ins))>;
7895 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7897 (VINSERTF128rr VR256:$src1, VR128:$src2,
7898 (INSERT_get_vinsert128_imm VR256:$ins))>;
7900 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7902 (VINSERTF128rm VR256:$src1, addr:$src2,
7903 (INSERT_get_vinsert128_imm VR256:$ins))>;
7904 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7906 (VINSERTF128rm VR256:$src1, addr:$src2,
7907 (INSERT_get_vinsert128_imm VR256:$ins))>;
7910 let Predicates = [HasAVX1Only] in {
7911 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7913 (VINSERTF128rr VR256:$src1, VR128:$src2,
7914 (INSERT_get_vinsert128_imm VR256:$ins))>;
7915 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7917 (VINSERTF128rr VR256:$src1, VR128:$src2,
7918 (INSERT_get_vinsert128_imm VR256:$ins))>;
7919 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7921 (VINSERTF128rr VR256:$src1, VR128:$src2,
7922 (INSERT_get_vinsert128_imm VR256:$ins))>;
7923 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7925 (VINSERTF128rr VR256:$src1, VR128:$src2,
7926 (INSERT_get_vinsert128_imm VR256:$ins))>;
7928 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7930 (VINSERTF128rm VR256:$src1, addr:$src2,
7931 (INSERT_get_vinsert128_imm VR256:$ins))>;
7932 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7933 (bc_v4i32 (loadv2i64 addr:$src2)),
7935 (VINSERTF128rm VR256:$src1, addr:$src2,
7936 (INSERT_get_vinsert128_imm VR256:$ins))>;
7937 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7938 (bc_v16i8 (loadv2i64 addr:$src2)),
7940 (VINSERTF128rm VR256:$src1, addr:$src2,
7941 (INSERT_get_vinsert128_imm VR256:$ins))>;
7942 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7943 (bc_v8i16 (loadv2i64 addr:$src2)),
7945 (VINSERTF128rm VR256:$src1, addr:$src2,
7946 (INSERT_get_vinsert128_imm VR256:$ins))>;
7949 //===----------------------------------------------------------------------===//
7950 // VEXTRACTF128 - Extract packed floating-point values
7952 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7953 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7954 (ins VR256:$src1, u8imm:$src2),
7955 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7956 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
7958 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7959 (ins f128mem:$dst, VR256:$src1, u8imm:$src2),
7960 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7961 []>, Sched<[WriteStore]>, VEX, VEX_L;
7965 let Predicates = [HasAVX] in {
7966 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7967 (v4f32 (VEXTRACTF128rr
7968 (v8f32 VR256:$src1),
7969 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7970 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7971 (v2f64 (VEXTRACTF128rr
7972 (v4f64 VR256:$src1),
7973 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7975 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7976 (iPTR imm))), addr:$dst),
7977 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7978 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7979 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7980 (iPTR imm))), addr:$dst),
7981 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7982 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7985 let Predicates = [HasAVX1Only] in {
7986 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7987 (v2i64 (VEXTRACTF128rr
7988 (v4i64 VR256:$src1),
7989 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7990 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7991 (v4i32 (VEXTRACTF128rr
7992 (v8i32 VR256:$src1),
7993 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7994 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7995 (v8i16 (VEXTRACTF128rr
7996 (v16i16 VR256:$src1),
7997 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7998 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7999 (v16i8 (VEXTRACTF128rr
8000 (v32i8 VR256:$src1),
8001 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8003 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8004 (iPTR imm))), addr:$dst),
8005 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8006 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8007 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8008 (iPTR imm))), addr:$dst),
8009 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8010 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8011 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8012 (iPTR imm))), addr:$dst),
8013 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8014 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8015 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8016 (iPTR imm))), addr:$dst),
8017 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8018 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8021 //===----------------------------------------------------------------------===//
8022 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8024 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8025 Intrinsic IntLd, Intrinsic IntLd256,
8026 Intrinsic IntSt, Intrinsic IntSt256> {
8027 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8028 (ins VR128:$src1, f128mem:$src2),
8029 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8030 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8032 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8033 (ins VR256:$src1, f256mem:$src2),
8034 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8035 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8037 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8038 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8039 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8040 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8041 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8042 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8043 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8044 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8047 let ExeDomain = SSEPackedSingle in
8048 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8049 int_x86_avx_maskload_ps,
8050 int_x86_avx_maskload_ps_256,
8051 int_x86_avx_maskstore_ps,
8052 int_x86_avx_maskstore_ps_256>;
8053 let ExeDomain = SSEPackedDouble in
8054 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8055 int_x86_avx_maskload_pd,
8056 int_x86_avx_maskload_pd_256,
8057 int_x86_avx_maskstore_pd,
8058 int_x86_avx_maskstore_pd_256>;
8060 //===----------------------------------------------------------------------===//
8061 // VPERMIL - Permute Single and Double Floating-Point Values
8063 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8064 RegisterClass RC, X86MemOperand x86memop_f,
8065 X86MemOperand x86memop_i, PatFrag i_frag,
8066 Intrinsic IntVar, ValueType vt> {
8067 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8068 (ins RC:$src1, RC:$src2),
8069 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8070 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8071 Sched<[WriteFShuffle]>;
8072 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8073 (ins RC:$src1, x86memop_i:$src2),
8074 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8075 [(set RC:$dst, (IntVar RC:$src1,
8076 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8077 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8079 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8080 (ins RC:$src1, u8imm:$src2),
8081 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8082 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8083 Sched<[WriteFShuffle]>;
8084 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8085 (ins x86memop_f:$src1, u8imm:$src2),
8086 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8088 (vt (X86VPermilpi (load addr:$src1), (i8 imm:$src2))))]>, VEX,
8089 Sched<[WriteFShuffleLd]>;
8092 let ExeDomain = SSEPackedSingle in {
8093 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8094 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8095 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8096 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8098 let ExeDomain = SSEPackedDouble in {
8099 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8100 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8101 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8102 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8105 let Predicates = [HasAVX] in {
8106 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8107 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8108 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8109 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8110 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8111 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8112 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8113 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8115 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8116 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8117 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8118 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8119 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8121 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8122 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8123 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8125 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8126 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8127 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8128 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8129 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8130 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8131 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8132 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8134 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8135 (VPERMILPDri VR128:$src1, imm:$imm)>;
8136 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8137 (VPERMILPDmi addr:$src1, imm:$imm)>;
8140 //===----------------------------------------------------------------------===//
8141 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8143 let ExeDomain = SSEPackedSingle in {
8144 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8145 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8146 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8147 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8148 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8149 Sched<[WriteFShuffle]>;
8150 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8151 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8152 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8153 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8154 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8155 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8158 let Predicates = [HasAVX] in {
8159 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8160 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8161 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8162 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8163 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8166 let Predicates = [HasAVX1Only] in {
8167 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8168 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8169 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8170 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8171 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8172 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8173 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8174 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8176 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8177 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8178 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8179 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8180 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8181 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8182 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8183 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8184 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8185 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8186 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8187 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8190 //===----------------------------------------------------------------------===//
8191 // VZERO - Zero YMM registers
8193 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8194 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8195 // Zero All YMM registers
8196 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8197 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8199 // Zero Upper bits of YMM registers
8200 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8201 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8204 //===----------------------------------------------------------------------===//
8205 // Half precision conversion instructions
8206 //===----------------------------------------------------------------------===//
8207 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8208 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8209 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8210 [(set RC:$dst, (Int VR128:$src))]>,
8211 T8PD, VEX, Sched<[WriteCvtF2F]>;
8212 let hasSideEffects = 0, mayLoad = 1 in
8213 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8214 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8215 Sched<[WriteCvtF2FLd]>;
8218 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8219 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8220 (ins RC:$src1, i32u8imm:$src2),
8221 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8222 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8223 TAPD, VEX, Sched<[WriteCvtF2F]>;
8224 let hasSideEffects = 0, mayStore = 1,
8225 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8226 def mr : Ii8<0x1D, MRMDestMem, (outs),
8227 (ins x86memop:$dst, RC:$src1, i32u8imm:$src2),
8228 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8232 let Predicates = [HasF16C] in {
8233 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8234 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8235 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8236 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8238 // Pattern match vcvtph2ps of a scalar i64 load.
8239 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8240 (VCVTPH2PSrm addr:$src)>;
8241 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8242 (VCVTPH2PSrm addr:$src)>;
8244 def : Pat<(store (f64 (vector_extract (bc_v2f64 (v8i16
8245 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8247 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8248 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v8i16
8249 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8251 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8252 def : Pat<(store (v8i16 (int_x86_vcvtps2ph_256 VR256:$src1, i32:$src2)),
8254 (VCVTPS2PHYmr addr:$dst, VR256:$src1, imm:$src2)>;
8257 // Patterns for matching conversions from float to half-float and vice versa.
8258 let Predicates = [HasF16C] in {
8259 def : Pat<(fp_to_f16 FR32:$src),
8260 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8261 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8263 def : Pat<(f16_to_fp GR16:$src),
8264 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8265 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8267 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8268 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8269 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8272 //===----------------------------------------------------------------------===//
8273 // AVX2 Instructions
8274 //===----------------------------------------------------------------------===//
8276 /// AVX2_binop_rmi - AVX2 binary operator with 8-bit immediate
8277 multiclass AVX2_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
8278 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
8279 X86MemOperand x86memop> {
8280 let isCommutable = 1 in
8281 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8282 (ins RC:$src1, RC:$src2, u8imm:$src3),
8283 !strconcat(OpcodeStr,
8284 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8285 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))]>,
8286 Sched<[WriteBlend]>, VEX_4V;
8287 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8288 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
8289 !strconcat(OpcodeStr,
8290 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8292 (OpVT (OpNode RC:$src1,
8293 (bitconvert (memop_frag addr:$src2)), imm:$src3)))]>,
8294 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8297 defm VPBLENDD : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v4i32,
8298 VR128, loadv2i64, i128mem>;
8299 defm VPBLENDDY : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v8i32,
8300 VR256, loadv4i64, i256mem>, VEX_L;
8302 //===----------------------------------------------------------------------===//
8303 // VPBROADCAST - Load from memory and broadcast to all elements of the
8304 // destination operand
8306 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8307 X86MemOperand x86memop, PatFrag ld_frag,
8308 Intrinsic Int128, Intrinsic Int256> {
8309 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8310 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8311 [(set VR128:$dst, (Int128 VR128:$src))]>,
8312 Sched<[WriteShuffle]>, VEX;
8313 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8314 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8316 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8317 Sched<[WriteLoad]>, VEX;
8318 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8319 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8320 [(set VR256:$dst, (Int256 VR128:$src))]>,
8321 Sched<[WriteShuffle256]>, VEX, VEX_L;
8322 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8323 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8325 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8326 Sched<[WriteLoad]>, VEX, VEX_L;
8329 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8330 int_x86_avx2_pbroadcastb_128,
8331 int_x86_avx2_pbroadcastb_256>;
8332 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8333 int_x86_avx2_pbroadcastw_128,
8334 int_x86_avx2_pbroadcastw_256>;
8335 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8336 int_x86_avx2_pbroadcastd_128,
8337 int_x86_avx2_pbroadcastd_256>;
8338 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8339 int_x86_avx2_pbroadcastq_128,
8340 int_x86_avx2_pbroadcastq_256>;
8342 let Predicates = [HasAVX2] in {
8343 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8344 (VPBROADCASTBrm addr:$src)>;
8345 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8346 (VPBROADCASTBYrm addr:$src)>;
8347 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8348 (VPBROADCASTWrm addr:$src)>;
8349 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8350 (VPBROADCASTWYrm addr:$src)>;
8351 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8352 (VPBROADCASTDrm addr:$src)>;
8353 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8354 (VPBROADCASTDYrm addr:$src)>;
8355 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8356 (VPBROADCASTQrm addr:$src)>;
8357 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8358 (VPBROADCASTQYrm addr:$src)>;
8360 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8361 (VPBROADCASTBrr VR128:$src)>;
8362 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8363 (VPBROADCASTBYrr VR128:$src)>;
8364 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8365 (VPBROADCASTWrr VR128:$src)>;
8366 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8367 (VPBROADCASTWYrr VR128:$src)>;
8368 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8369 (VPBROADCASTDrr VR128:$src)>;
8370 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8371 (VPBROADCASTDYrr VR128:$src)>;
8372 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8373 (VPBROADCASTQrr VR128:$src)>;
8374 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8375 (VPBROADCASTQYrr VR128:$src)>;
8376 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8377 (VBROADCASTSSrr VR128:$src)>;
8378 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8379 (VBROADCASTSSYrr VR128:$src)>;
8380 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8381 (VPBROADCASTQrr VR128:$src)>;
8382 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8383 (VBROADCASTSDYrr VR128:$src)>;
8385 // Provide aliases for broadcast from the same register class that
8386 // automatically does the extract.
8387 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8388 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8390 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8391 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8393 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8394 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8396 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8397 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8399 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8400 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8402 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8403 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8406 // Provide fallback in case the load node that is used in the patterns above
8407 // is used by additional users, which prevents the pattern selection.
8408 let AddedComplexity = 20 in {
8409 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8410 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8411 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8412 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8413 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8414 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8416 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8417 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8418 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8419 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8420 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8421 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8423 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8424 (VPBROADCASTBrr (COPY_TO_REGCLASS
8425 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8427 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8428 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8429 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8432 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8433 (VPBROADCASTWrr (COPY_TO_REGCLASS
8434 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8436 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8437 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8438 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8441 // The patterns for VPBROADCASTD are not needed because they would match
8442 // the exact same thing as VBROADCASTSS patterns.
8444 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8445 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8446 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8450 // AVX1 broadcast patterns
8451 let Predicates = [HasAVX1Only] in {
8452 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8453 (VBROADCASTSSYrm addr:$src)>;
8454 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8455 (VBROADCASTSDYrm addr:$src)>;
8456 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8457 (VBROADCASTSSrm addr:$src)>;
8460 let Predicates = [HasAVX] in {
8461 // Provide fallback in case the load node that is used in the patterns above
8462 // is used by additional users, which prevents the pattern selection.
8463 let AddedComplexity = 20 in {
8464 // 128bit broadcasts:
8465 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8466 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8467 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8468 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8469 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8470 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8471 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8472 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8473 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8474 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8476 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8477 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8478 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8479 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8480 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8481 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8482 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8483 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8484 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8485 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8488 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8489 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8490 def : Pat<(v2i64 (X86VBroadcast i64:$src)),
8491 (VMOVDDUPrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8494 //===----------------------------------------------------------------------===//
8495 // VPERM - Permute instructions
8498 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8499 ValueType OpVT, X86FoldableSchedWrite Sched> {
8500 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8501 (ins VR256:$src1, VR256:$src2),
8502 !strconcat(OpcodeStr,
8503 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8505 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8506 Sched<[Sched]>, VEX_4V, VEX_L;
8507 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8508 (ins VR256:$src1, i256mem:$src2),
8509 !strconcat(OpcodeStr,
8510 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8512 (OpVT (X86VPermv VR256:$src1,
8513 (bitconvert (mem_frag addr:$src2)))))]>,
8514 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8517 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8518 let ExeDomain = SSEPackedSingle in
8519 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8521 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8522 ValueType OpVT, X86FoldableSchedWrite Sched> {
8523 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8524 (ins VR256:$src1, u8imm:$src2),
8525 !strconcat(OpcodeStr,
8526 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8528 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8529 Sched<[Sched]>, VEX, VEX_L;
8530 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8531 (ins i256mem:$src1, u8imm:$src2),
8532 !strconcat(OpcodeStr,
8533 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8535 (OpVT (X86VPermi (mem_frag addr:$src1),
8536 (i8 imm:$src2))))]>,
8537 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8540 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8541 WriteShuffle256>, VEX_W;
8542 let ExeDomain = SSEPackedDouble in
8543 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8544 WriteFShuffle256>, VEX_W;
8546 //===----------------------------------------------------------------------===//
8547 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8549 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8550 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8551 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8552 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8553 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8555 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8556 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8557 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8558 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8560 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8562 let Predicates = [HasAVX2] in {
8563 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8564 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8565 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8566 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8567 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8568 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8570 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8572 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8573 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8574 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8575 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8576 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8578 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8582 //===----------------------------------------------------------------------===//
8583 // VINSERTI128 - Insert packed integer values
8585 let hasSideEffects = 0 in {
8586 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8587 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8588 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8589 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8591 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8592 (ins VR256:$src1, i128mem:$src2, u8imm:$src3),
8593 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8594 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8597 let Predicates = [HasAVX2] in {
8598 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8600 (VINSERTI128rr VR256:$src1, VR128:$src2,
8601 (INSERT_get_vinsert128_imm VR256:$ins))>;
8602 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8604 (VINSERTI128rr VR256:$src1, VR128:$src2,
8605 (INSERT_get_vinsert128_imm VR256:$ins))>;
8606 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8608 (VINSERTI128rr VR256:$src1, VR128:$src2,
8609 (INSERT_get_vinsert128_imm VR256:$ins))>;
8610 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8612 (VINSERTI128rr VR256:$src1, VR128:$src2,
8613 (INSERT_get_vinsert128_imm VR256:$ins))>;
8615 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8617 (VINSERTI128rm VR256:$src1, addr:$src2,
8618 (INSERT_get_vinsert128_imm VR256:$ins))>;
8619 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8620 (bc_v4i32 (loadv2i64 addr:$src2)),
8622 (VINSERTI128rm VR256:$src1, addr:$src2,
8623 (INSERT_get_vinsert128_imm VR256:$ins))>;
8624 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8625 (bc_v16i8 (loadv2i64 addr:$src2)),
8627 (VINSERTI128rm VR256:$src1, addr:$src2,
8628 (INSERT_get_vinsert128_imm VR256:$ins))>;
8629 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8630 (bc_v8i16 (loadv2i64 addr:$src2)),
8632 (VINSERTI128rm VR256:$src1, addr:$src2,
8633 (INSERT_get_vinsert128_imm VR256:$ins))>;
8636 //===----------------------------------------------------------------------===//
8637 // VEXTRACTI128 - Extract packed integer values
8639 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8640 (ins VR256:$src1, u8imm:$src2),
8641 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8642 Sched<[WriteShuffle256]>, VEX, VEX_L;
8643 let hasSideEffects = 0, mayStore = 1 in
8644 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8645 (ins i128mem:$dst, VR256:$src1, u8imm:$src2),
8646 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8647 Sched<[WriteStore]>, VEX, VEX_L;
8649 let Predicates = [HasAVX2] in {
8650 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8651 (v2i64 (VEXTRACTI128rr
8652 (v4i64 VR256:$src1),
8653 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8654 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8655 (v4i32 (VEXTRACTI128rr
8656 (v8i32 VR256:$src1),
8657 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8658 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8659 (v8i16 (VEXTRACTI128rr
8660 (v16i16 VR256:$src1),
8661 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8662 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8663 (v16i8 (VEXTRACTI128rr
8664 (v32i8 VR256:$src1),
8665 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8667 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8668 (iPTR imm))), addr:$dst),
8669 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8670 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8671 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8672 (iPTR imm))), addr:$dst),
8673 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8674 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8675 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8676 (iPTR imm))), addr:$dst),
8677 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8678 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8679 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8680 (iPTR imm))), addr:$dst),
8681 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8682 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8685 //===----------------------------------------------------------------------===//
8686 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8688 multiclass avx2_pmovmask<string OpcodeStr,
8689 Intrinsic IntLd128, Intrinsic IntLd256,
8690 Intrinsic IntSt128, Intrinsic IntSt256> {
8691 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8692 (ins VR128:$src1, i128mem:$src2),
8693 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8694 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8695 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8696 (ins VR256:$src1, i256mem:$src2),
8697 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8698 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8700 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8701 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8702 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8703 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8704 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8705 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8706 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8707 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8710 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8711 int_x86_avx2_maskload_d,
8712 int_x86_avx2_maskload_d_256,
8713 int_x86_avx2_maskstore_d,
8714 int_x86_avx2_maskstore_d_256>;
8715 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8716 int_x86_avx2_maskload_q,
8717 int_x86_avx2_maskload_q_256,
8718 int_x86_avx2_maskstore_q,
8719 int_x86_avx2_maskstore_q_256>, VEX_W;
8721 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8722 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8724 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8725 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8727 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8728 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
8730 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
8731 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8733 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8734 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8736 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
8737 (bc_v8f32 (v8i32 immAllZerosV)))),
8738 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8740 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
8741 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
8744 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8745 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8747 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
8748 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8750 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
8751 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
8754 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8755 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8757 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
8758 (bc_v4f32 (v4i32 immAllZerosV)))),
8759 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8761 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
8762 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
8765 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8766 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8768 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
8769 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8771 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
8772 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
8775 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
8776 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8778 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
8779 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8781 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8782 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8784 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8785 (v4f64 immAllZerosV))),
8786 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8788 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
8789 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
8792 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8793 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8795 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8796 (bc_v4i64 (v8i32 immAllZerosV)))),
8797 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8799 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
8800 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
8803 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
8804 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8806 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
8807 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
8809 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8810 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8812 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8813 (v2f64 immAllZerosV))),
8814 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8816 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
8817 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
8820 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8821 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8823 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8824 (bc_v2i64 (v4i32 immAllZerosV)))),
8825 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8827 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
8828 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
8831 //===----------------------------------------------------------------------===//
8832 // Variable Bit Shifts
8834 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8835 ValueType vt128, ValueType vt256> {
8836 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8837 (ins VR128:$src1, VR128:$src2),
8838 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8840 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8841 VEX_4V, Sched<[WriteVarVecShift]>;
8842 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8843 (ins VR128:$src1, i128mem:$src2),
8844 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8846 (vt128 (OpNode VR128:$src1,
8847 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8848 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8849 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8850 (ins VR256:$src1, VR256:$src2),
8851 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8853 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8854 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
8855 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8856 (ins VR256:$src1, i256mem:$src2),
8857 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8859 (vt256 (OpNode VR256:$src1,
8860 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8861 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8864 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8865 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8866 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8867 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8868 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8870 //===----------------------------------------------------------------------===//
8871 // VGATHER - GATHER Operations
8872 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8873 X86MemOperand memop128, X86MemOperand memop256> {
8874 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8875 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8876 !strconcat(OpcodeStr,
8877 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8879 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8880 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8881 !strconcat(OpcodeStr,
8882 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8883 []>, VEX_4VOp3, VEX_L;
8886 let mayLoad = 1, Constraints
8887 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8889 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8890 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8891 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8892 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
8894 let ExeDomain = SSEPackedDouble in {
8895 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8896 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8899 let ExeDomain = SSEPackedSingle in {
8900 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8901 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;