1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 def SSE_BIT_ITINS_P : OpndItins<
124 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
127 let Sched = WriteVecALU in {
128 def SSE_INTALU_ITINS_P : OpndItins<
129 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
132 def SSE_INTALUQ_ITINS_P : OpndItins<
133 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
137 let Sched = WriteVecIMul in
138 def SSE_INTMUL_ITINS_P : OpndItins<
139 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
142 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
143 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
146 def SSE_MOVA_ITINS : OpndItins<
147 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
150 def SSE_MOVU_ITINS : OpndItins<
151 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
154 def SSE_DPPD_ITINS : OpndItins<
155 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
158 def SSE_DPPS_ITINS : OpndItins<
159 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
162 def DEFAULT_ITINS : OpndItins<
163 IIC_ALU_NONMEM, IIC_ALU_MEM
166 def SSE_EXTRACT_ITINS : OpndItins<
167 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
170 def SSE_INSERT_ITINS : OpndItins<
171 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
174 def SSE_MPSADBW_ITINS : OpndItins<
175 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
178 def SSE_PMULLD_ITINS : OpndItins<
179 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
182 //===----------------------------------------------------------------------===//
183 // SSE 1 & 2 Instructions Classes
184 //===----------------------------------------------------------------------===//
186 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
187 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
188 RegisterClass RC, X86MemOperand x86memop,
191 let isCommutable = 1 in {
192 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
194 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
195 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
196 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
197 Sched<[itins.Sched]>;
199 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
201 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
202 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
203 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
204 Sched<[itins.Sched.Folded, ReadAfterLd]>;
207 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
208 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
209 string asm, string SSEVer, string FPSizeStr,
210 Operand memopr, ComplexPattern mem_cpat,
213 let isCodeGenOnly = 1 in {
214 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
216 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 [(set RC:$dst, (!cast<Intrinsic>(
219 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
220 RC:$src1, RC:$src2))], itins.rr>,
221 Sched<[itins.Sched]>;
222 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
224 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
225 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
226 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
227 SSEVer, "_", OpcodeStr, FPSizeStr))
228 RC:$src1, mem_cpat:$src2))], itins.rm>,
229 Sched<[itins.Sched.Folded, ReadAfterLd]>;
233 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
234 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
235 RegisterClass RC, ValueType vt,
236 X86MemOperand x86memop, PatFrag mem_frag,
237 Domain d, OpndItins itins, bit Is2Addr = 1> {
238 let isCommutable = 1 in
239 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
241 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
242 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
243 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
244 Sched<[itins.Sched]>;
246 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
250 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
252 Sched<[itins.Sched.Folded, ReadAfterLd]>;
255 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
256 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
257 string OpcodeStr, X86MemOperand x86memop,
258 list<dag> pat_rr, list<dag> pat_rm,
260 let isCommutable = 1, hasSideEffects = 0 in
261 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
263 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
264 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
265 pat_rr, NoItinerary, d>,
266 Sched<[WriteVecLogic]>;
267 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
269 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
270 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
271 pat_rm, NoItinerary, d>,
272 Sched<[WriteVecLogicLd, ReadAfterLd]>;
275 //===----------------------------------------------------------------------===//
276 // Non-instruction patterns
277 //===----------------------------------------------------------------------===//
279 // A vector extract of the first f32/f64 position is a subregister copy
280 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
281 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
282 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
283 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
285 // A 128-bit subvector extract from the first 256-bit vector position
286 // is a subregister copy that needs no instruction.
287 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
288 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
289 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
290 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
292 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
293 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
294 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
295 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
297 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
298 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
299 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
300 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
302 // A 128-bit subvector insert to the first 256-bit vector position
303 // is a subregister copy that needs no instruction.
304 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
305 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
306 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
307 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
308 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
309 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
310 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
311 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
312 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
313 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
314 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
315 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
316 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
319 // Implicitly promote a 32-bit scalar to a vector.
320 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
321 (COPY_TO_REGCLASS FR32:$src, VR128)>;
322 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
323 (COPY_TO_REGCLASS FR32:$src, VR128)>;
324 // Implicitly promote a 64-bit scalar to a vector.
325 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
326 (COPY_TO_REGCLASS FR64:$src, VR128)>;
327 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
328 (COPY_TO_REGCLASS FR64:$src, VR128)>;
330 // Bitcasts between 128-bit vector types. Return the original type since
331 // no instruction is needed for the conversion
332 let Predicates = [HasSSE2] in {
333 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
334 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
335 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
336 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
337 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
338 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
339 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
340 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
341 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
342 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
343 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
344 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
345 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
346 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
347 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
348 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
349 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
350 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
351 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
352 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
353 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
354 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
355 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
356 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
357 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
358 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
359 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
360 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
361 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
362 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
365 // Bitcasts between 256-bit vector types. Return the original type since
366 // no instruction is needed for the conversion
367 let Predicates = [HasAVX] in {
368 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
369 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
370 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
371 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
372 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
373 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
374 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
375 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
376 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
377 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
378 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
379 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
380 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
381 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
382 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
383 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
384 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
385 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
386 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
387 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
388 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
389 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
390 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
391 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
392 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
393 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
394 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
395 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
396 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
397 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
400 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
401 // This is expanded by ExpandPostRAPseudos.
402 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
403 isPseudo = 1, SchedRW = [WriteZero] in {
404 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
405 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
406 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
407 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
410 //===----------------------------------------------------------------------===//
411 // AVX & SSE - Zero/One Vectors
412 //===----------------------------------------------------------------------===//
414 // Alias instruction that maps zero vector to pxor / xorp* for sse.
415 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
416 // swizzled by ExecutionDepsFix to pxor.
417 // We set canFoldAsLoad because this can be converted to a constant-pool
418 // load of an all-zeros value if folding it would be beneficial.
419 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
420 isPseudo = 1, SchedRW = [WriteZero] in {
421 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
422 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
425 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
426 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
427 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
428 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
429 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
432 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
433 // and doesn't need it because on sandy bridge the register is set to zero
434 // at the rename stage without using any execution unit, so SET0PSY
435 // and SET0PDY can be used for vector int instructions without penalty
436 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
437 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
438 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
439 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
442 let Predicates = [HasAVX] in
443 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
445 let Predicates = [HasAVX2] in {
446 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
447 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
448 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
449 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
452 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
453 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
454 let Predicates = [HasAVX1Only] in {
455 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
456 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
457 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
459 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
460 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
461 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
463 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
464 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
465 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
467 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
468 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
469 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
472 // We set canFoldAsLoad because this can be converted to a constant-pool
473 // load of an all-ones value if folding it would be beneficial.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
475 isPseudo = 1, SchedRW = [WriteZero] in {
476 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
477 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
478 let Predicates = [HasAVX2] in
479 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
480 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
484 //===----------------------------------------------------------------------===//
485 // SSE 1 & 2 - Move FP Scalar Instructions
487 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
488 // register copies because it's a partial register update; Register-to-register
489 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
490 // that the insert be implementable in terms of a copy, and just mentioned, we
491 // don't use movss/movsd for copies.
492 //===----------------------------------------------------------------------===//
494 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
495 X86MemOperand x86memop, string base_opc,
497 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
498 (ins VR128:$src1, RC:$src2),
499 !strconcat(base_opc, asm_opr),
500 [(set VR128:$dst, (vt (OpNode VR128:$src1,
501 (scalar_to_vector RC:$src2))))],
502 IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
504 // For the disassembler
505 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
506 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
507 (ins VR128:$src1, RC:$src2),
508 !strconcat(base_opc, asm_opr),
509 [], IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
512 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
513 X86MemOperand x86memop, string OpcodeStr> {
515 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
516 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
519 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
520 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
521 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
522 VEX, VEX_LIG, Sched<[WriteStore]>;
524 let Constraints = "$src1 = $dst" in {
525 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
526 "\t{$src2, $dst|$dst, $src2}">;
529 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
530 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
531 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
535 // Loading from memory automatically zeroing upper bits.
536 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
537 PatFrag mem_pat, string OpcodeStr> {
538 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
539 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
540 [(set RC:$dst, (mem_pat addr:$src))],
541 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
542 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
543 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
544 [(set RC:$dst, (mem_pat addr:$src))],
545 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
548 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
549 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
551 let canFoldAsLoad = 1, isReMaterializable = 1 in {
552 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
554 let AddedComplexity = 20 in
555 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
559 let Predicates = [UseAVX] in {
560 let AddedComplexity = 15 in {
561 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
562 // MOVS{S,D} to the lower bits.
563 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
564 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
565 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
566 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
567 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
568 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
569 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
570 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
572 // Move low f32 and clear high bits.
573 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
574 (SUBREG_TO_REG (i32 0),
575 (VMOVSSrr (v4f32 (V_SET0)),
576 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
577 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
578 (SUBREG_TO_REG (i32 0),
579 (VMOVSSrr (v4i32 (V_SET0)),
580 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
583 let AddedComplexity = 20 in {
584 // MOVSSrm zeros the high parts of the register; represent this
585 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
586 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
587 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
588 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
589 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
590 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
591 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
593 // MOVSDrm zeros the high parts of the register; represent this
594 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
595 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
596 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
597 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
598 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
599 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
600 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
601 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
602 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
603 def : Pat<(v2f64 (X86vzload addr:$src)),
604 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
606 // Represent the same patterns above but in the form they appear for
608 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
609 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
610 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
611 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
612 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
613 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
614 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
615 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
616 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
618 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
619 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
620 (SUBREG_TO_REG (i32 0),
621 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
623 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
624 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
625 (SUBREG_TO_REG (i64 0),
626 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
628 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
629 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
630 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
632 // Move low f64 and clear high bits.
633 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
634 (SUBREG_TO_REG (i32 0),
635 (VMOVSDrr (v2f64 (V_SET0)),
636 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
638 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
639 (SUBREG_TO_REG (i32 0),
640 (VMOVSDrr (v2i64 (V_SET0)),
641 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
643 // Extract and store.
644 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
646 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
647 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
649 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
651 // Shuffle with VMOVSS
652 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
653 (VMOVSSrr (v4i32 VR128:$src1),
654 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
655 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
656 (VMOVSSrr (v4f32 VR128:$src1),
657 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
660 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
661 (SUBREG_TO_REG (i32 0),
662 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
663 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
665 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
666 (SUBREG_TO_REG (i32 0),
667 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
668 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
671 // Shuffle with VMOVSD
672 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
673 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
674 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
675 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
676 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
677 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
678 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
679 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
682 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
683 (SUBREG_TO_REG (i32 0),
684 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
685 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
687 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
688 (SUBREG_TO_REG (i32 0),
689 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
690 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
694 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
695 // is during lowering, where it's not possible to recognize the fold cause
696 // it has two uses through a bitcast. One use disappears at isel time and the
697 // fold opportunity reappears.
698 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
699 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
700 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
701 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
702 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
703 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
704 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
705 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
708 let Predicates = [UseSSE1] in {
709 let AddedComplexity = 15 in {
710 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
711 // MOVSS to the lower bits.
712 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
713 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
714 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
715 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
716 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
717 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
720 let AddedComplexity = 20 in {
721 // MOVSSrm already zeros the high parts of the register.
722 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
723 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
724 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
725 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
726 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
727 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
730 // Extract and store.
731 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
733 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
735 // Shuffle with MOVSS
736 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
737 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
738 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
739 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
742 let Predicates = [UseSSE2] in {
743 let AddedComplexity = 15 in {
744 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
745 // MOVSD to the lower bits.
746 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
747 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
750 let AddedComplexity = 20 in {
751 // MOVSDrm already zeros the high parts of the register.
752 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
753 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
754 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
755 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
756 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
757 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
758 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
759 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
760 def : Pat<(v2f64 (X86vzload addr:$src)),
761 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 // Extract and store.
765 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
767 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
769 // Shuffle with MOVSD
770 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
771 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
772 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
773 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
774 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
775 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
776 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
777 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
779 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
780 // is during lowering, where it's not possible to recognize the fold cause
781 // it has two uses through a bitcast. One use disappears at isel time and the
782 // fold opportunity reappears.
783 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
784 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
785 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
786 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
788 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
789 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
790 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
793 //===----------------------------------------------------------------------===//
794 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
795 //===----------------------------------------------------------------------===//
797 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
798 X86MemOperand x86memop, PatFrag ld_frag,
799 string asm, Domain d,
801 bit IsReMaterializable = 1> {
802 let neverHasSideEffects = 1 in
803 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
804 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
806 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
807 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
808 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
809 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
813 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
814 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
816 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
817 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
819 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
820 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
822 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
823 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
826 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
827 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
829 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
830 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
831 TB, OpSize, VEX, VEX_L;
832 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
833 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
835 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
836 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
837 TB, OpSize, VEX, VEX_L;
838 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
839 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
841 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
842 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
844 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
845 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
847 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
848 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
851 let SchedRW = [WriteStore] in {
852 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
853 "movaps\t{$src, $dst|$dst, $src}",
854 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
855 IIC_SSE_MOVA_P_MR>, VEX;
856 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
857 "movapd\t{$src, $dst|$dst, $src}",
858 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
859 IIC_SSE_MOVA_P_MR>, VEX;
860 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
861 "movups\t{$src, $dst|$dst, $src}",
862 [(store (v4f32 VR128:$src), addr:$dst)],
863 IIC_SSE_MOVU_P_MR>, VEX;
864 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
865 "movupd\t{$src, $dst|$dst, $src}",
866 [(store (v2f64 VR128:$src), addr:$dst)],
867 IIC_SSE_MOVU_P_MR>, VEX;
868 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
869 "movaps\t{$src, $dst|$dst, $src}",
870 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
871 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
872 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
873 "movapd\t{$src, $dst|$dst, $src}",
874 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
875 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
876 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
877 "movups\t{$src, $dst|$dst, $src}",
878 [(store (v8f32 VR256:$src), addr:$dst)],
879 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
880 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
881 "movupd\t{$src, $dst|$dst, $src}",
882 [(store (v4f64 VR256:$src), addr:$dst)],
883 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
887 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
888 SchedRW = [WriteMove] in {
889 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
891 "movaps\t{$src, $dst|$dst, $src}", [],
892 IIC_SSE_MOVA_P_RR>, VEX;
893 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
895 "movapd\t{$src, $dst|$dst, $src}", [],
896 IIC_SSE_MOVA_P_RR>, VEX;
897 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
899 "movups\t{$src, $dst|$dst, $src}", [],
900 IIC_SSE_MOVU_P_RR>, VEX;
901 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
903 "movupd\t{$src, $dst|$dst, $src}", [],
904 IIC_SSE_MOVU_P_RR>, VEX;
905 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
907 "movaps\t{$src, $dst|$dst, $src}", [],
908 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
909 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
911 "movapd\t{$src, $dst|$dst, $src}", [],
912 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
913 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
915 "movups\t{$src, $dst|$dst, $src}", [],
916 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
917 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
919 "movupd\t{$src, $dst|$dst, $src}", [],
920 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
923 let Predicates = [HasAVX] in {
924 def : Pat<(v8i32 (X86vzmovl
925 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
926 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
927 def : Pat<(v4i64 (X86vzmovl
928 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
929 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
930 def : Pat<(v8f32 (X86vzmovl
931 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
932 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
933 def : Pat<(v4f64 (X86vzmovl
934 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
935 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
939 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
940 (VMOVUPSYmr addr:$dst, VR256:$src)>;
941 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
942 (VMOVUPDYmr addr:$dst, VR256:$src)>;
944 let SchedRW = [WriteStore] in {
945 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
946 "movaps\t{$src, $dst|$dst, $src}",
947 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
949 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
950 "movapd\t{$src, $dst|$dst, $src}",
951 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
953 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
954 "movups\t{$src, $dst|$dst, $src}",
955 [(store (v4f32 VR128:$src), addr:$dst)],
957 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
958 "movupd\t{$src, $dst|$dst, $src}",
959 [(store (v2f64 VR128:$src), addr:$dst)],
964 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
965 SchedRW = [WriteMove] in {
966 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
967 "movaps\t{$src, $dst|$dst, $src}", [],
969 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
970 "movapd\t{$src, $dst|$dst, $src}", [],
972 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
973 "movups\t{$src, $dst|$dst, $src}", [],
975 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
976 "movupd\t{$src, $dst|$dst, $src}", [],
980 let Predicates = [HasAVX] in {
981 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
982 (VMOVUPSmr addr:$dst, VR128:$src)>;
983 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
984 (VMOVUPDmr addr:$dst, VR128:$src)>;
987 let Predicates = [UseSSE1] in
988 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
989 (MOVUPSmr addr:$dst, VR128:$src)>;
990 let Predicates = [UseSSE2] in
991 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
992 (MOVUPDmr addr:$dst, VR128:$src)>;
994 // Use vmovaps/vmovups for AVX integer load/store.
995 let Predicates = [HasAVX] in {
996 // 128-bit load/store
997 def : Pat<(alignedloadv2i64 addr:$src),
998 (VMOVAPSrm addr:$src)>;
999 def : Pat<(loadv2i64 addr:$src),
1000 (VMOVUPSrm addr:$src)>;
1002 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1003 (VMOVAPSmr addr:$dst, VR128:$src)>;
1004 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1005 (VMOVAPSmr addr:$dst, VR128:$src)>;
1006 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1007 (VMOVAPSmr addr:$dst, VR128:$src)>;
1008 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1009 (VMOVAPSmr addr:$dst, VR128:$src)>;
1010 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1011 (VMOVUPSmr addr:$dst, VR128:$src)>;
1012 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1013 (VMOVUPSmr addr:$dst, VR128:$src)>;
1014 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1015 (VMOVUPSmr addr:$dst, VR128:$src)>;
1016 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1017 (VMOVUPSmr addr:$dst, VR128:$src)>;
1019 // 256-bit load/store
1020 def : Pat<(alignedloadv4i64 addr:$src),
1021 (VMOVAPSYrm addr:$src)>;
1022 def : Pat<(loadv4i64 addr:$src),
1023 (VMOVUPSYrm addr:$src)>;
1024 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1025 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1026 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1027 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1028 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1029 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1030 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1031 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1032 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1033 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1034 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1035 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1036 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1037 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1038 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1039 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1041 // Special patterns for storing subvector extracts of lower 128-bits
1042 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1043 def : Pat<(alignedstore (v2f64 (extract_subvector
1044 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1045 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1046 def : Pat<(alignedstore (v4f32 (extract_subvector
1047 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1048 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1049 def : Pat<(alignedstore (v2i64 (extract_subvector
1050 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1051 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1052 def : Pat<(alignedstore (v4i32 (extract_subvector
1053 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1054 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1055 def : Pat<(alignedstore (v8i16 (extract_subvector
1056 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1057 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1058 def : Pat<(alignedstore (v16i8 (extract_subvector
1059 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1062 def : Pat<(store (v2f64 (extract_subvector
1063 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1064 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1065 def : Pat<(store (v4f32 (extract_subvector
1066 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1067 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1068 def : Pat<(store (v2i64 (extract_subvector
1069 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1070 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1071 def : Pat<(store (v4i32 (extract_subvector
1072 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1073 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1074 def : Pat<(store (v8i16 (extract_subvector
1075 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1076 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1077 def : Pat<(store (v16i8 (extract_subvector
1078 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1079 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1082 // Use movaps / movups for SSE integer load / store (one byte shorter).
1083 // The instructions selected below are then converted to MOVDQA/MOVDQU
1084 // during the SSE domain pass.
1085 let Predicates = [UseSSE1] in {
1086 def : Pat<(alignedloadv2i64 addr:$src),
1087 (MOVAPSrm addr:$src)>;
1088 def : Pat<(loadv2i64 addr:$src),
1089 (MOVUPSrm addr:$src)>;
1091 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1092 (MOVAPSmr addr:$dst, VR128:$src)>;
1093 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1094 (MOVAPSmr addr:$dst, VR128:$src)>;
1095 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1096 (MOVAPSmr addr:$dst, VR128:$src)>;
1097 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1098 (MOVAPSmr addr:$dst, VR128:$src)>;
1099 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1100 (MOVUPSmr addr:$dst, VR128:$src)>;
1101 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1102 (MOVUPSmr addr:$dst, VR128:$src)>;
1103 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1104 (MOVUPSmr addr:$dst, VR128:$src)>;
1105 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1106 (MOVUPSmr addr:$dst, VR128:$src)>;
1109 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1110 // bits are disregarded. FIXME: Set encoding to pseudo!
1111 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1112 let isCodeGenOnly = 1 in {
1113 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1114 "movaps\t{$src, $dst|$dst, $src}",
1115 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1116 IIC_SSE_MOVA_P_RM>, VEX;
1117 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1118 "movapd\t{$src, $dst|$dst, $src}",
1119 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1120 IIC_SSE_MOVA_P_RM>, VEX;
1121 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1122 "movaps\t{$src, $dst|$dst, $src}",
1123 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1125 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1126 "movapd\t{$src, $dst|$dst, $src}",
1127 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1132 //===----------------------------------------------------------------------===//
1133 // SSE 1 & 2 - Move Low packed FP Instructions
1134 //===----------------------------------------------------------------------===//
1136 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1137 string base_opc, string asm_opr,
1138 InstrItinClass itin> {
1139 def PSrm : PI<opc, MRMSrcMem,
1140 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1141 !strconcat(base_opc, "s", asm_opr),
1143 (psnode VR128:$src1,
1144 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1145 itin, SSEPackedSingle>, TB,
1146 Sched<[WriteShuffleLd, ReadAfterLd]>;
1148 def PDrm : PI<opc, MRMSrcMem,
1149 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1150 !strconcat(base_opc, "d", asm_opr),
1151 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1152 (scalar_to_vector (loadf64 addr:$src2)))))],
1153 itin, SSEPackedDouble>, TB, OpSize,
1154 Sched<[WriteShuffleLd, ReadAfterLd]>;
1158 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1159 string base_opc, InstrItinClass itin> {
1160 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1161 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1164 let Constraints = "$src1 = $dst" in
1165 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1166 "\t{$src2, $dst|$dst, $src2}",
1170 let AddedComplexity = 20 in {
1171 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1175 let SchedRW = [WriteStore] in {
1176 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1177 "movlps\t{$src, $dst|$dst, $src}",
1178 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1179 (iPTR 0))), addr:$dst)],
1180 IIC_SSE_MOV_LH>, VEX;
1181 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1182 "movlpd\t{$src, $dst|$dst, $src}",
1183 [(store (f64 (vector_extract (v2f64 VR128:$src),
1184 (iPTR 0))), addr:$dst)],
1185 IIC_SSE_MOV_LH>, VEX;
1186 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1187 "movlps\t{$src, $dst|$dst, $src}",
1188 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1189 (iPTR 0))), addr:$dst)],
1191 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1192 "movlpd\t{$src, $dst|$dst, $src}",
1193 [(store (f64 (vector_extract (v2f64 VR128:$src),
1194 (iPTR 0))), addr:$dst)],
1198 let Predicates = [HasAVX] in {
1199 // Shuffle with VMOVLPS
1200 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1201 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1202 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1203 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1205 // Shuffle with VMOVLPD
1206 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1207 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1208 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1209 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1212 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1214 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1215 def : Pat<(store (v4i32 (X86Movlps
1216 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1217 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1218 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1220 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1221 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1223 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1226 let Predicates = [UseSSE1] in {
1227 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1228 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1229 (iPTR 0))), addr:$src1),
1230 (MOVLPSmr addr:$src1, VR128:$src2)>;
1232 // Shuffle with MOVLPS
1233 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1234 (MOVLPSrm VR128:$src1, addr:$src2)>;
1235 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1236 (MOVLPSrm VR128:$src1, addr:$src2)>;
1237 def : Pat<(X86Movlps VR128:$src1,
1238 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1239 (MOVLPSrm VR128:$src1, addr:$src2)>;
1242 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1244 (MOVLPSmr addr:$src1, VR128:$src2)>;
1245 def : Pat<(store (v4i32 (X86Movlps
1246 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1248 (MOVLPSmr addr:$src1, VR128:$src2)>;
1251 let Predicates = [UseSSE2] in {
1252 // Shuffle with MOVLPD
1253 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1254 (MOVLPDrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1256 (MOVLPDrm VR128:$src1, addr:$src2)>;
1259 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1261 (MOVLPDmr addr:$src1, VR128:$src2)>;
1262 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1264 (MOVLPDmr addr:$src1, VR128:$src2)>;
1267 //===----------------------------------------------------------------------===//
1268 // SSE 1 & 2 - Move Hi packed FP Instructions
1269 //===----------------------------------------------------------------------===//
1271 let AddedComplexity = 20 in {
1272 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1276 let SchedRW = [WriteStore] in {
1277 // v2f64 extract element 1 is always custom lowered to unpack high to low
1278 // and extract element 0 so the non-store version isn't too horrible.
1279 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1280 "movhps\t{$src, $dst|$dst, $src}",
1281 [(store (f64 (vector_extract
1282 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1283 (bc_v2f64 (v4f32 VR128:$src))),
1284 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1285 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1286 "movhpd\t{$src, $dst|$dst, $src}",
1287 [(store (f64 (vector_extract
1288 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1289 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1290 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1291 "movhps\t{$src, $dst|$dst, $src}",
1292 [(store (f64 (vector_extract
1293 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1294 (bc_v2f64 (v4f32 VR128:$src))),
1295 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1296 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1297 "movhpd\t{$src, $dst|$dst, $src}",
1298 [(store (f64 (vector_extract
1299 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1300 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1303 let Predicates = [HasAVX] in {
1305 def : Pat<(X86Movlhps VR128:$src1,
1306 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1307 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1308 def : Pat<(X86Movlhps VR128:$src1,
1309 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1310 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1312 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1313 // is during lowering, where it's not possible to recognize the load fold
1314 // cause it has two uses through a bitcast. One use disappears at isel time
1315 // and the fold opportunity reappears.
1316 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1317 (scalar_to_vector (loadf64 addr:$src2)))),
1318 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1321 let Predicates = [UseSSE1] in {
1323 def : Pat<(X86Movlhps VR128:$src1,
1324 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1325 (MOVHPSrm VR128:$src1, addr:$src2)>;
1326 def : Pat<(X86Movlhps VR128:$src1,
1327 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1328 (MOVHPSrm VR128:$src1, addr:$src2)>;
1331 let Predicates = [UseSSE2] in {
1332 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1333 // is during lowering, where it's not possible to recognize the load fold
1334 // cause it has two uses through a bitcast. One use disappears at isel time
1335 // and the fold opportunity reappears.
1336 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1337 (scalar_to_vector (loadf64 addr:$src2)))),
1338 (MOVHPDrm VR128:$src1, addr:$src2)>;
1341 //===----------------------------------------------------------------------===//
1342 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1343 //===----------------------------------------------------------------------===//
1345 let AddedComplexity = 20, Predicates = [UseAVX] in {
1346 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1347 (ins VR128:$src1, VR128:$src2),
1348 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1350 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1352 VEX_4V, Sched<[WriteShuffle]>;
1353 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1354 (ins VR128:$src1, VR128:$src2),
1355 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1357 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1359 VEX_4V, Sched<[WriteShuffle]>;
1361 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1362 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1363 (ins VR128:$src1, VR128:$src2),
1364 "movlhps\t{$src2, $dst|$dst, $src2}",
1366 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1367 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1368 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1369 (ins VR128:$src1, VR128:$src2),
1370 "movhlps\t{$src2, $dst|$dst, $src2}",
1372 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1373 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1376 let Predicates = [UseAVX] in {
1378 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1379 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1380 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1381 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1384 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1385 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1388 let Predicates = [UseSSE1] in {
1390 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1391 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1392 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1393 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1396 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1397 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1400 //===----------------------------------------------------------------------===//
1401 // SSE 1 & 2 - Conversion Instructions
1402 //===----------------------------------------------------------------------===//
1404 def SSE_CVT_PD : OpndItins<
1405 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1408 let Sched = WriteCvtI2F in
1409 def SSE_CVT_PS : OpndItins<
1410 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1413 let Sched = WriteCvtI2F in
1414 def SSE_CVT_Scalar : OpndItins<
1415 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1418 let Sched = WriteCvtF2I in
1419 def SSE_CVT_SS2SI_32 : OpndItins<
1420 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1423 let Sched = WriteCvtF2I in
1424 def SSE_CVT_SS2SI_64 : OpndItins<
1425 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1428 let Sched = WriteCvtF2I in
1429 def SSE_CVT_SD2SI : OpndItins<
1430 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1433 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1434 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1435 string asm, OpndItins itins> {
1436 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1437 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1438 itins.rr>, Sched<[itins.Sched]>;
1439 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1440 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1441 itins.rm>, Sched<[itins.Sched.Folded]>;
1444 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1445 X86MemOperand x86memop, string asm, Domain d,
1447 let neverHasSideEffects = 1 in {
1448 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1449 [], itins.rr, d>, Sched<[itins.Sched]>;
1451 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1452 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1456 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1457 X86MemOperand x86memop, string asm> {
1458 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1459 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1460 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1461 Sched<[WriteCvtI2F]>;
1463 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1464 (ins DstRC:$src1, x86memop:$src),
1465 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1466 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1467 } // neverHasSideEffects = 1
1470 let Predicates = [UseAVX] in {
1471 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1472 "cvttss2si\t{$src, $dst|$dst, $src}",
1475 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1476 "cvttss2si\t{$src, $dst|$dst, $src}",
1478 XS, VEX, VEX_W, VEX_LIG;
1479 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1480 "cvttsd2si\t{$src, $dst|$dst, $src}",
1483 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1484 "cvttsd2si\t{$src, $dst|$dst, $src}",
1486 XD, VEX, VEX_W, VEX_LIG;
1488 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1489 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1490 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1491 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1492 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1493 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1494 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1495 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1496 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1497 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1498 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1499 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1500 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1501 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1502 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1503 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1505 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1506 // register, but the same isn't true when only using memory operands,
1507 // provide other assembly "l" and "q" forms to address this explicitly
1508 // where appropriate to do so.
1509 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1510 XS, VEX_4V, VEX_LIG;
1511 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1512 XS, VEX_4V, VEX_W, VEX_LIG;
1513 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1514 XD, VEX_4V, VEX_LIG;
1515 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1516 XD, VEX_4V, VEX_W, VEX_LIG;
1518 let Predicates = [UseAVX] in {
1519 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1520 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1521 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1522 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1524 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1525 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1526 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1527 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1528 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1529 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1530 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1531 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1533 def : Pat<(f32 (sint_to_fp GR32:$src)),
1534 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1535 def : Pat<(f32 (sint_to_fp GR64:$src)),
1536 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1537 def : Pat<(f64 (sint_to_fp GR32:$src)),
1538 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1539 def : Pat<(f64 (sint_to_fp GR64:$src)),
1540 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1543 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1544 "cvttss2si\t{$src, $dst|$dst, $src}",
1545 SSE_CVT_SS2SI_32>, XS;
1546 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1547 "cvttss2si\t{$src, $dst|$dst, $src}",
1548 SSE_CVT_SS2SI_64>, XS, REX_W;
1549 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1550 "cvttsd2si\t{$src, $dst|$dst, $src}",
1552 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1553 "cvttsd2si\t{$src, $dst|$dst, $src}",
1554 SSE_CVT_SD2SI>, XD, REX_W;
1555 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1556 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1557 SSE_CVT_Scalar>, XS;
1558 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1559 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1560 SSE_CVT_Scalar>, XS, REX_W;
1561 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1562 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1563 SSE_CVT_Scalar>, XD;
1564 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1565 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1566 SSE_CVT_Scalar>, XD, REX_W;
1568 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1569 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1570 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1571 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1572 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1573 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1574 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1575 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1576 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1577 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1578 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1579 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1580 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1581 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1582 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1583 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1585 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1586 (CVTSI2SSrm FR64:$dst, i32mem:$src)>;
1587 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1588 (CVTSI2SDrm FR64:$dst, i32mem:$src)>;
1590 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1591 // and/or XMM operand(s).
1593 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1594 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1595 string asm, OpndItins itins> {
1596 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1597 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1598 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1599 Sched<[itins.Sched]>;
1600 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1601 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1602 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1603 Sched<[itins.Sched.Folded]>;
1606 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1607 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1608 PatFrag ld_frag, string asm, OpndItins itins,
1610 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1612 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1613 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1614 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1615 itins.rr>, Sched<[itins.Sched]>;
1616 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1617 (ins DstRC:$src1, x86memop:$src2),
1619 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1620 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1621 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1622 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1625 let Predicates = [UseAVX] in {
1626 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1627 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1628 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1629 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1630 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1631 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1633 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1634 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1635 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1636 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1639 let isCodeGenOnly = 1 in {
1640 let Predicates = [UseAVX] in {
1641 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1642 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1643 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1644 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1645 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1646 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1648 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1649 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1650 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1651 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1652 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1653 SSE_CVT_Scalar, 0>, XD,
1656 let Constraints = "$src1 = $dst" in {
1657 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1658 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1659 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1660 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1661 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1662 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1663 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1664 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1665 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1666 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1667 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1668 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1670 } // isCodeGenOnly = 1
1674 // Aliases for intrinsics
1675 let isCodeGenOnly = 1 in {
1676 let Predicates = [UseAVX] in {
1677 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1678 ssmem, sse_load_f32, "cvttss2si",
1679 SSE_CVT_SS2SI_32>, XS, VEX;
1680 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1681 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1682 "cvttss2si", SSE_CVT_SS2SI_64>,
1684 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1685 sdmem, sse_load_f64, "cvttsd2si",
1686 SSE_CVT_SD2SI>, XD, VEX;
1687 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1688 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1689 "cvttsd2si", SSE_CVT_SD2SI>,
1692 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1693 ssmem, sse_load_f32, "cvttss2si",
1694 SSE_CVT_SS2SI_32>, XS;
1695 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1696 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1697 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1698 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1699 sdmem, sse_load_f64, "cvttsd2si",
1701 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1702 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1703 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1704 } // isCodeGenOnly = 1
1706 let Predicates = [UseAVX] in {
1707 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1708 ssmem, sse_load_f32, "cvtss2si",
1709 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1710 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1711 ssmem, sse_load_f32, "cvtss2si",
1712 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1714 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1715 ssmem, sse_load_f32, "cvtss2si",
1716 SSE_CVT_SS2SI_32>, XS;
1717 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1718 ssmem, sse_load_f32, "cvtss2si",
1719 SSE_CVT_SS2SI_64>, XS, REX_W;
1721 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1722 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1723 SSEPackedSingle, SSE_CVT_PS>,
1724 TB, VEX, Requires<[HasAVX]>;
1725 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1726 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1727 SSEPackedSingle, SSE_CVT_PS>,
1728 TB, VEX, VEX_L, Requires<[HasAVX]>;
1730 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1731 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1732 SSEPackedSingle, SSE_CVT_PS>,
1733 TB, Requires<[UseSSE2]>;
1735 let Predicates = [UseAVX] in {
1736 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1737 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1738 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1739 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1740 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1741 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1742 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1743 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1744 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1745 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1746 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1747 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1748 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1749 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1750 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1751 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1754 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1755 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1756 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1757 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1758 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1759 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1760 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1761 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1762 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1763 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1764 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1765 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1766 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1767 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1768 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1769 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1773 // Convert scalar double to scalar single
1774 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1775 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1776 (ins FR64:$src1, FR64:$src2),
1777 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1778 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1779 Sched<[WriteCvtF2F]>;
1781 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1782 (ins FR64:$src1, f64mem:$src2),
1783 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1784 [], IIC_SSE_CVT_Scalar_RM>,
1785 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1786 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1789 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1792 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1793 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1794 [(set FR32:$dst, (fround FR64:$src))],
1795 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1796 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1797 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1798 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1799 IIC_SSE_CVT_Scalar_RM>,
1801 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1803 let isCodeGenOnly = 1 in {
1804 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1805 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1806 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1808 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1809 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1810 Sched<[WriteCvtF2F]>;
1811 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1812 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1813 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1814 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1815 VR128:$src1, sse_load_f64:$src2))],
1816 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1817 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1819 let Constraints = "$src1 = $dst" in {
1820 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1821 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1822 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1824 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1825 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1826 Sched<[WriteCvtF2F]>;
1827 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1828 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1829 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1830 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1831 VR128:$src1, sse_load_f64:$src2))],
1832 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1833 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1835 } // isCodeGenOnly = 1
1837 // Convert scalar single to scalar double
1838 // SSE2 instructions with XS prefix
1839 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1840 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1841 (ins FR32:$src1, FR32:$src2),
1842 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1843 [], IIC_SSE_CVT_Scalar_RR>,
1844 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1845 Sched<[WriteCvtF2F]>;
1847 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1848 (ins FR32:$src1, f32mem:$src2),
1849 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1850 [], IIC_SSE_CVT_Scalar_RM>,
1851 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1852 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1855 def : Pat<(f64 (fextend FR32:$src)),
1856 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1857 def : Pat<(fextend (loadf32 addr:$src)),
1858 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1860 def : Pat<(extloadf32 addr:$src),
1861 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1862 Requires<[UseAVX, OptForSize]>;
1863 def : Pat<(extloadf32 addr:$src),
1864 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1865 Requires<[UseAVX, OptForSpeed]>;
1867 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1868 "cvtss2sd\t{$src, $dst|$dst, $src}",
1869 [(set FR64:$dst, (fextend FR32:$src))],
1870 IIC_SSE_CVT_Scalar_RR>, XS,
1871 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1872 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1873 "cvtss2sd\t{$src, $dst|$dst, $src}",
1874 [(set FR64:$dst, (extloadf32 addr:$src))],
1875 IIC_SSE_CVT_Scalar_RM>, XS,
1876 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1878 // extload f32 -> f64. This matches load+fextend because we have a hack in
1879 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1881 // Since these loads aren't folded into the fextend, we have to match it
1883 def : Pat<(fextend (loadf32 addr:$src)),
1884 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1885 def : Pat<(extloadf32 addr:$src),
1886 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1888 let isCodeGenOnly = 1 in {
1889 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1890 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1891 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1893 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1894 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1895 Sched<[WriteCvtF2F]>;
1896 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1897 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1898 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1900 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1901 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1902 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1903 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1904 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1905 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1906 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1908 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1909 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1910 Sched<[WriteCvtF2F]>;
1911 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1912 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1913 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1915 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1916 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1917 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1919 } // isCodeGenOnly = 1
1921 // Convert packed single/double fp to doubleword
1922 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1923 "cvtps2dq\t{$src, $dst|$dst, $src}",
1924 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1925 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1926 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1927 "cvtps2dq\t{$src, $dst|$dst, $src}",
1929 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1930 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1931 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1932 "cvtps2dq\t{$src, $dst|$dst, $src}",
1934 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1935 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1936 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1937 "cvtps2dq\t{$src, $dst|$dst, $src}",
1939 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1940 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1941 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1942 "cvtps2dq\t{$src, $dst|$dst, $src}",
1943 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1944 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1945 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1946 "cvtps2dq\t{$src, $dst|$dst, $src}",
1948 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1949 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1952 // Convert Packed Double FP to Packed DW Integers
1953 let Predicates = [HasAVX] in {
1954 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1955 // register, but the same isn't true when using memory operands instead.
1956 // Provide other assembly rr and rm forms to address this explicitly.
1957 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1958 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1959 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1960 VEX, Sched<[WriteCvtF2I]>;
1963 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1964 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1965 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1966 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1968 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
1969 Sched<[WriteCvtF2ILd]>;
1972 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1973 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1975 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
1976 Sched<[WriteCvtF2I]>;
1977 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1978 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1980 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
1981 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1982 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1983 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1986 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1987 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1989 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1990 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
1991 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1992 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1993 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1994 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
1996 // Convert with truncation packed single/double fp to doubleword
1997 // SSE2 packed instructions with XS prefix
1998 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1999 "cvttps2dq\t{$src, $dst|$dst, $src}",
2001 (int_x86_sse2_cvttps2dq VR128:$src))],
2002 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2003 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2004 "cvttps2dq\t{$src, $dst|$dst, $src}",
2005 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2006 (loadv4f32 addr:$src)))],
2007 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2008 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2009 "cvttps2dq\t{$src, $dst|$dst, $src}",
2011 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2012 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2013 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2014 "cvttps2dq\t{$src, $dst|$dst, $src}",
2015 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2016 (loadv8f32 addr:$src)))],
2017 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2018 Sched<[WriteCvtF2ILd]>;
2020 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2021 "cvttps2dq\t{$src, $dst|$dst, $src}",
2022 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2023 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2024 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2025 "cvttps2dq\t{$src, $dst|$dst, $src}",
2027 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2028 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2030 let Predicates = [HasAVX] in {
2031 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2032 (VCVTDQ2PSrr VR128:$src)>;
2033 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2034 (VCVTDQ2PSrm addr:$src)>;
2036 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2037 (VCVTDQ2PSrr VR128:$src)>;
2038 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2039 (VCVTDQ2PSrm addr:$src)>;
2041 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2042 (VCVTTPS2DQrr VR128:$src)>;
2043 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2044 (VCVTTPS2DQrm addr:$src)>;
2046 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2047 (VCVTDQ2PSYrr VR256:$src)>;
2048 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2049 (VCVTDQ2PSYrm addr:$src)>;
2051 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2052 (VCVTTPS2DQYrr VR256:$src)>;
2053 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2054 (VCVTTPS2DQYrm addr:$src)>;
2057 let Predicates = [UseSSE2] in {
2058 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2059 (CVTDQ2PSrr VR128:$src)>;
2060 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2061 (CVTDQ2PSrm addr:$src)>;
2063 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2064 (CVTDQ2PSrr VR128:$src)>;
2065 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2066 (CVTDQ2PSrm addr:$src)>;
2068 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2069 (CVTTPS2DQrr VR128:$src)>;
2070 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2071 (CVTTPS2DQrm addr:$src)>;
2074 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2075 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2077 (int_x86_sse2_cvttpd2dq VR128:$src))],
2078 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2080 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2081 // register, but the same isn't true when using memory operands instead.
2082 // Provide other assembly rr and rm forms to address this explicitly.
2085 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2086 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
2087 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2088 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2089 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2090 (loadv2f64 addr:$src)))],
2091 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2094 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2095 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2097 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2098 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2099 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2100 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2102 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2103 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2104 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2105 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
2107 let Predicates = [HasAVX] in {
2108 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2109 (VCVTTPD2DQYrr VR256:$src)>;
2110 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2111 (VCVTTPD2DQYrm addr:$src)>;
2112 } // Predicates = [HasAVX]
2114 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2115 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2116 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2117 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2118 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2119 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2120 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2121 (memopv2f64 addr:$src)))],
2123 Sched<[WriteCvtF2ILd]>;
2125 // Convert packed single to packed double
2126 let Predicates = [HasAVX] in {
2127 // SSE2 instructions without OpSize prefix
2128 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2129 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2130 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2131 IIC_SSE_CVT_PD_RR>, TB, VEX, Sched<[WriteCvtF2F]>;
2132 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2133 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2134 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2135 IIC_SSE_CVT_PD_RM>, TB, VEX, Sched<[WriteCvtF2FLd]>;
2136 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2137 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2139 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2140 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2141 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2142 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2144 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2145 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2148 let Predicates = [UseSSE2] in {
2149 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2150 "cvtps2pd\t{$src, $dst|$dst, $src}",
2151 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2152 IIC_SSE_CVT_PD_RR>, TB, Sched<[WriteCvtF2F]>;
2153 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2154 "cvtps2pd\t{$src, $dst|$dst, $src}",
2155 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2156 IIC_SSE_CVT_PD_RM>, TB, Sched<[WriteCvtF2FLd]>;
2159 // Convert Packed DW Integers to Packed Double FP
2160 let Predicates = [HasAVX] in {
2161 let neverHasSideEffects = 1, mayLoad = 1 in
2162 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2163 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2164 []>, VEX, Sched<[WriteCvtI2FLd]>;
2165 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2166 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2168 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2169 Sched<[WriteCvtI2F]>;
2170 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2171 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2173 (int_x86_avx_cvtdq2_pd_256
2174 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2175 Sched<[WriteCvtI2FLd]>;
2176 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2177 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2179 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2180 Sched<[WriteCvtI2F]>;
2183 let neverHasSideEffects = 1, mayLoad = 1 in
2184 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2185 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2186 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2187 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2188 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2189 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2190 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2192 // AVX 256-bit register conversion intrinsics
2193 let Predicates = [HasAVX] in {
2194 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2195 (VCVTDQ2PDYrr VR128:$src)>;
2196 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2197 (VCVTDQ2PDYrm addr:$src)>;
2198 } // Predicates = [HasAVX]
2200 // Convert packed double to packed single
2201 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2202 // register, but the same isn't true when using memory operands instead.
2203 // Provide other assembly rr and rm forms to address this explicitly.
2204 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2205 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2206 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2207 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2210 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2211 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2212 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2213 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2215 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2216 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2219 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2220 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2222 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2223 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2224 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2225 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2227 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2228 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2229 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2230 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2232 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2233 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2234 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2235 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2236 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2237 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2239 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2240 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2243 // AVX 256-bit register conversion intrinsics
2244 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2245 // whenever possible to avoid declaring two versions of each one.
2246 let Predicates = [HasAVX] in {
2247 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2248 (VCVTDQ2PSYrr VR256:$src)>;
2249 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2250 (VCVTDQ2PSYrm addr:$src)>;
2252 // Match fround and fextend for 128/256-bit conversions
2253 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2254 (VCVTPD2PSrr VR128:$src)>;
2255 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2256 (VCVTPD2PSXrm addr:$src)>;
2257 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2258 (VCVTPD2PSYrr VR256:$src)>;
2259 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2260 (VCVTPD2PSYrm addr:$src)>;
2262 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2263 (VCVTPS2PDrr VR128:$src)>;
2264 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2265 (VCVTPS2PDYrr VR128:$src)>;
2266 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2267 (VCVTPS2PDYrm addr:$src)>;
2270 let Predicates = [UseSSE2] in {
2271 // Match fround and fextend for 128 conversions
2272 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2273 (CVTPD2PSrr VR128:$src)>;
2274 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2275 (CVTPD2PSrm addr:$src)>;
2277 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2278 (CVTPS2PDrr VR128:$src)>;
2281 //===----------------------------------------------------------------------===//
2282 // SSE 1 & 2 - Compare Instructions
2283 //===----------------------------------------------------------------------===//
2285 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2286 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2287 Operand CC, SDNode OpNode, ValueType VT,
2288 PatFrag ld_frag, string asm, string asm_alt,
2290 def rr : SIi8<0xC2, MRMSrcReg,
2291 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2292 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2293 itins.rr>, Sched<[itins.Sched]>;
2294 def rm : SIi8<0xC2, MRMSrcMem,
2295 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2296 [(set RC:$dst, (OpNode (VT RC:$src1),
2297 (ld_frag addr:$src2), imm:$cc))],
2299 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2301 // Accept explicit immediate argument form instead of comparison code.
2302 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2303 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2304 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2305 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2307 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2308 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2309 IIC_SSE_ALU_F32S_RM>,
2310 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2314 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2315 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2316 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2318 XS, VEX_4V, VEX_LIG;
2319 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2320 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2321 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2322 SSE_ALU_F32S>, // same latency as 32 bit compare
2323 XD, VEX_4V, VEX_LIG;
2325 let Constraints = "$src1 = $dst" in {
2326 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2327 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2328 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2330 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2331 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2332 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2337 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2338 Intrinsic Int, string asm, OpndItins itins> {
2339 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2340 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2341 [(set VR128:$dst, (Int VR128:$src1,
2342 VR128:$src, imm:$cc))],
2344 Sched<[itins.Sched]>;
2345 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2346 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2347 [(set VR128:$dst, (Int VR128:$src1,
2348 (load addr:$src), imm:$cc))],
2350 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2353 let isCodeGenOnly = 1 in {
2354 // Aliases to match intrinsics which expect XMM operand(s).
2355 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2356 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2359 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2360 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2361 SSE_ALU_F32S>, // same latency as f32
2363 let Constraints = "$src1 = $dst" in {
2364 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2365 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2367 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2368 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2375 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2376 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2377 ValueType vt, X86MemOperand x86memop,
2378 PatFrag ld_frag, string OpcodeStr> {
2379 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2380 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2381 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2384 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2385 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2386 [(set EFLAGS, (OpNode (vt RC:$src1),
2387 (ld_frag addr:$src2)))],
2389 Sched<[WriteFAddLd, ReadAfterLd]>;
2392 let Defs = [EFLAGS] in {
2393 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2394 "ucomiss">, TB, VEX, VEX_LIG;
2395 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2396 "ucomisd">, TB, OpSize, VEX, VEX_LIG;
2397 let Pattern = []<dag> in {
2398 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2399 "comiss">, TB, VEX, VEX_LIG;
2400 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2401 "comisd">, TB, OpSize, VEX, VEX_LIG;
2404 let isCodeGenOnly = 1 in {
2405 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2406 load, "ucomiss">, TB, VEX;
2407 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2408 load, "ucomisd">, TB, OpSize, VEX;
2410 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2411 load, "comiss">, TB, VEX;
2412 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2413 load, "comisd">, TB, OpSize, VEX;
2415 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2417 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2418 "ucomisd">, TB, OpSize;
2420 let Pattern = []<dag> in {
2421 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2423 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2424 "comisd">, TB, OpSize;
2427 let isCodeGenOnly = 1 in {
2428 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2429 load, "ucomiss">, TB;
2430 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2431 load, "ucomisd">, TB, OpSize;
2433 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2435 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2436 "comisd">, TB, OpSize;
2438 } // Defs = [EFLAGS]
2440 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2441 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2442 Operand CC, Intrinsic Int, string asm,
2443 string asm_alt, Domain d,
2444 OpndItins itins = SSE_ALU_F32P> {
2445 def rri : PIi8<0xC2, MRMSrcReg,
2446 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2447 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2450 def rmi : PIi8<0xC2, MRMSrcMem,
2451 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2452 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2454 Sched<[WriteFAddLd, ReadAfterLd]>;
2456 // Accept explicit immediate argument form instead of comparison code.
2457 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2458 def rri_alt : PIi8<0xC2, MRMSrcReg,
2459 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2460 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2461 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2462 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2463 asm_alt, [], itins.rm, d>,
2464 Sched<[WriteFAddLd, ReadAfterLd]>;
2468 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2469 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2470 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2471 SSEPackedSingle>, TB, VEX_4V;
2472 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2473 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2474 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2475 SSEPackedDouble>, TB, OpSize, VEX_4V;
2476 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2477 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2478 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2479 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2480 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2481 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2482 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2483 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2484 let Constraints = "$src1 = $dst" in {
2485 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2486 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2487 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2488 SSEPackedSingle, SSE_ALU_F32P>, TB;
2489 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2490 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2491 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2492 SSEPackedDouble, SSE_ALU_F64P>, TB, OpSize;
2495 let Predicates = [HasAVX] in {
2496 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2497 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2498 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2499 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2500 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2501 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2502 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2503 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2505 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2506 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2507 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2508 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2509 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2510 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2511 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2512 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2515 let Predicates = [UseSSE1] in {
2516 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2517 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2518 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2519 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2522 let Predicates = [UseSSE2] in {
2523 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2524 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2525 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2526 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2529 //===----------------------------------------------------------------------===//
2530 // SSE 1 & 2 - Shuffle Instructions
2531 //===----------------------------------------------------------------------===//
2533 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2534 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2535 ValueType vt, string asm, PatFrag mem_frag,
2536 Domain d, bit IsConvertibleToThreeAddress = 0> {
2537 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2538 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2539 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2540 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2541 Sched<[WriteShuffleLd, ReadAfterLd]>;
2542 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2543 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2544 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2545 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2546 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2547 Sched<[WriteShuffle]>;
2550 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2551 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2552 loadv4f32, SSEPackedSingle>, TB, VEX_4V;
2553 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2554 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2555 loadv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2556 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2557 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2558 loadv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2559 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2560 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2561 loadv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2563 let Constraints = "$src1 = $dst" in {
2564 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2565 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2566 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2568 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2569 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2570 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2574 let Predicates = [HasAVX] in {
2575 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2576 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2577 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2578 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2579 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2581 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2582 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2583 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2584 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2585 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2588 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2589 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2590 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2591 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2592 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2594 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2595 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2596 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2597 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2598 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2601 let Predicates = [UseSSE1] in {
2602 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2603 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2604 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2605 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2606 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2609 let Predicates = [UseSSE2] in {
2610 // Generic SHUFPD patterns
2611 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2612 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2613 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2614 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2615 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2618 //===----------------------------------------------------------------------===//
2619 // SSE 1 & 2 - Unpack Instructions
2620 //===----------------------------------------------------------------------===//
2622 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2623 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2624 PatFrag mem_frag, RegisterClass RC,
2625 X86MemOperand x86memop, string asm,
2627 def rr : PI<opc, MRMSrcReg,
2628 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2630 (vt (OpNode RC:$src1, RC:$src2)))],
2631 IIC_SSE_UNPCK, d>, Sched<[WriteShuffle]>;
2632 def rm : PI<opc, MRMSrcMem,
2633 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2635 (vt (OpNode RC:$src1,
2636 (mem_frag addr:$src2))))],
2638 Sched<[WriteShuffleLd, ReadAfterLd]>;
2641 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2642 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2643 SSEPackedSingle>, TB, VEX_4V;
2644 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2645 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2646 SSEPackedDouble>, TB, OpSize, VEX_4V;
2647 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2648 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2649 SSEPackedSingle>, TB, VEX_4V;
2650 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2651 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2652 SSEPackedDouble>, TB, OpSize, VEX_4V;
2654 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2655 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2656 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2657 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2658 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2659 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2660 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2661 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2662 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2663 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2664 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2665 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2667 let Constraints = "$src1 = $dst" in {
2668 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2669 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2670 SSEPackedSingle>, TB;
2671 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2672 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2673 SSEPackedDouble>, TB, OpSize;
2674 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2675 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2676 SSEPackedSingle>, TB;
2677 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2678 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2679 SSEPackedDouble>, TB, OpSize;
2680 } // Constraints = "$src1 = $dst"
2682 let Predicates = [HasAVX1Only] in {
2683 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2684 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2685 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2686 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2687 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2688 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2689 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2690 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2692 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2693 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2694 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2695 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2696 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2697 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2698 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2699 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2702 let Predicates = [HasAVX] in {
2703 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2704 // problem is during lowering, where it's not possible to recognize the load
2705 // fold cause it has two uses through a bitcast. One use disappears at isel
2706 // time and the fold opportunity reappears.
2707 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2708 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2711 let Predicates = [UseSSE2] in {
2712 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2713 // problem is during lowering, where it's not possible to recognize the load
2714 // fold cause it has two uses through a bitcast. One use disappears at isel
2715 // time and the fold opportunity reappears.
2716 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2717 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2720 //===----------------------------------------------------------------------===//
2721 // SSE 1 & 2 - Extract Floating-Point Sign mask
2722 //===----------------------------------------------------------------------===//
2724 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2725 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2727 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2728 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2729 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2730 Sched<[WriteVecLogic]>;
2733 let Predicates = [HasAVX] in {
2734 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2735 "movmskps", SSEPackedSingle>, TB, VEX;
2736 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2737 "movmskpd", SSEPackedDouble>, TB,
2739 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2740 "movmskps", SSEPackedSingle>, TB,
2742 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2743 "movmskpd", SSEPackedDouble>, TB,
2746 def : Pat<(i32 (X86fgetsign FR32:$src)),
2747 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2748 def : Pat<(i64 (X86fgetsign FR32:$src)),
2749 (SUBREG_TO_REG (i64 0),
2750 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2751 def : Pat<(i32 (X86fgetsign FR64:$src)),
2752 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2753 def : Pat<(i64 (X86fgetsign FR64:$src)),
2754 (SUBREG_TO_REG (i64 0),
2755 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2758 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2759 SSEPackedSingle>, TB;
2760 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2761 SSEPackedDouble>, TB, OpSize;
2763 def : Pat<(i32 (X86fgetsign FR32:$src)),
2764 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2765 Requires<[UseSSE1]>;
2766 def : Pat<(i64 (X86fgetsign FR32:$src)),
2767 (SUBREG_TO_REG (i64 0),
2768 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2769 Requires<[UseSSE1]>;
2770 def : Pat<(i32 (X86fgetsign FR64:$src)),
2771 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2772 Requires<[UseSSE2]>;
2773 def : Pat<(i64 (X86fgetsign FR64:$src)),
2774 (SUBREG_TO_REG (i64 0),
2775 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2776 Requires<[UseSSE2]>;
2778 //===---------------------------------------------------------------------===//
2779 // SSE2 - Packed Integer Logical Instructions
2780 //===---------------------------------------------------------------------===//
2782 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2784 /// PDI_binop_rm - Simple SSE2 binary operator.
2785 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2786 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2787 X86MemOperand x86memop, OpndItins itins,
2788 bit IsCommutable, bit Is2Addr> {
2789 let isCommutable = IsCommutable in
2790 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2791 (ins RC:$src1, RC:$src2),
2793 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2794 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2795 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2796 Sched<[itins.Sched]>;
2797 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2798 (ins RC:$src1, x86memop:$src2),
2800 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2801 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2802 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2803 (bitconvert (memop_frag addr:$src2)))))],
2805 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2807 } // ExeDomain = SSEPackedInt
2809 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2810 ValueType OpVT128, ValueType OpVT256,
2811 OpndItins itins, bit IsCommutable = 0> {
2812 let Predicates = [HasAVX] in
2813 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2814 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2816 let Constraints = "$src1 = $dst" in
2817 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2818 memopv2i64, i128mem, itins, IsCommutable, 1>;
2820 let Predicates = [HasAVX2] in
2821 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2822 OpVT256, VR256, loadv4i64, i256mem, itins,
2823 IsCommutable, 0>, VEX_4V, VEX_L;
2826 // These are ordered here for pattern ordering requirements with the fp versions
2828 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2829 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2830 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2831 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2832 SSE_BIT_ITINS_P, 0>;
2834 //===----------------------------------------------------------------------===//
2835 // SSE 1 & 2 - Logical Instructions
2836 //===----------------------------------------------------------------------===//
2838 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2840 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2841 SDNode OpNode, OpndItins itins> {
2842 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2843 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2846 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2847 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2850 let Constraints = "$src1 = $dst" in {
2851 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2852 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2855 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2856 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2861 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2862 let isCodeGenOnly = 1 in {
2863 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2865 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2867 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2870 let isCommutable = 0 in
2871 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2875 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2877 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2879 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2880 !strconcat(OpcodeStr, "ps"), f256mem,
2881 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2882 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2883 (loadv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2885 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2886 !strconcat(OpcodeStr, "pd"), f256mem,
2887 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2888 (bc_v4i64 (v4f64 VR256:$src2))))],
2889 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2890 (loadv4i64 addr:$src2)))], 0>,
2891 TB, OpSize, VEX_4V, VEX_L;
2893 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2894 // are all promoted to v2i64, and the patterns are covered by the int
2895 // version. This is needed in SSE only, because v2i64 isn't supported on
2896 // SSE1, but only on SSE2.
2897 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2898 !strconcat(OpcodeStr, "ps"), f128mem, [],
2899 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2900 (loadv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2902 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2903 !strconcat(OpcodeStr, "pd"), f128mem,
2904 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2905 (bc_v2i64 (v2f64 VR128:$src2))))],
2906 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2907 (loadv2i64 addr:$src2)))], 0>,
2910 let Constraints = "$src1 = $dst" in {
2911 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2912 !strconcat(OpcodeStr, "ps"), f128mem,
2913 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2914 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2915 (memopv2i64 addr:$src2)))]>, TB;
2917 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2918 !strconcat(OpcodeStr, "pd"), f128mem,
2919 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2920 (bc_v2i64 (v2f64 VR128:$src2))))],
2921 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2922 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2926 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2927 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2928 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2929 let isCommutable = 0 in
2930 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2932 //===----------------------------------------------------------------------===//
2933 // SSE 1 & 2 - Arithmetic Instructions
2934 //===----------------------------------------------------------------------===//
2936 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2939 /// In addition, we also have a special variant of the scalar form here to
2940 /// represent the associated intrinsic operation. This form is unlike the
2941 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2942 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2944 /// These three forms can each be reg+reg or reg+mem.
2947 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2949 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
2950 SDNode OpNode, SizeItins itins> {
2951 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2952 VR128, v4f32, f128mem, loadv4f32,
2953 SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
2954 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2955 VR128, v2f64, f128mem, loadv2f64,
2956 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V;
2958 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
2959 OpNode, VR256, v8f32, f256mem, loadv8f32,
2960 SSEPackedSingle, itins.s, 0>, TB, VEX_4V, VEX_L;
2961 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
2962 OpNode, VR256, v4f64, f256mem, loadv4f64,
2963 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V, VEX_L;
2965 let Constraints = "$src1 = $dst" in {
2966 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2967 v4f32, f128mem, memopv4f32, SSEPackedSingle,
2969 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2970 v2f64, f128mem, memopv2f64, SSEPackedDouble,
2971 itins.d>, TB, OpSize;
2975 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2977 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2978 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
2979 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2980 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
2982 let Constraints = "$src1 = $dst" in {
2983 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2984 OpNode, FR32, f32mem, itins.s>, XS;
2985 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2986 OpNode, FR64, f64mem, itins.d>, XD;
2990 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2992 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2993 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2994 itins.s, 0>, XS, VEX_4V, VEX_LIG;
2995 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2996 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2997 itins.d, 0>, XD, VEX_4V, VEX_LIG;
2999 let Constraints = "$src1 = $dst" in {
3000 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3001 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3003 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3004 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3009 // Binary Arithmetic instructions
3010 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3011 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3012 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3013 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3014 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3015 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3016 let isCommutable = 0 in {
3017 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3018 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3019 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3020 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3021 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3022 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3023 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3024 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3025 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3026 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3027 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3028 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3031 let isCodeGenOnly = 1 in {
3032 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3033 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3034 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3035 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3038 // Patterns used to select SSE scalar fp arithmetic instructions from
3039 // a scalar fp operation followed by a blend.
3041 // These patterns know, for example, how to select an ADDSS from a
3042 // float add plus vector insert.
3044 // The effect is that the backend no longer emits unnecessary vector
3045 // insert instructions immediately after SSE scalar fp instructions
3046 // like addss or mulss.
3048 // For example, given the following code:
3049 // __m128 foo(__m128 A, __m128 B) {
3054 // previously we generated:
3055 // addss %xmm0, %xmm1
3056 // movss %xmm1, %xmm0
3059 // addss %xmm1, %xmm0
3061 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3062 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3064 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3065 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3066 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3068 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3069 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3070 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3072 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3073 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3074 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3076 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3078 let Predicates = [HasSSE2] in {
3079 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3081 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3082 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3084 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3085 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3086 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3088 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3089 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3090 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3092 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3093 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3094 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3096 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3099 let Predicates = [UseSSE41] in {
3100 // If the subtarget has SSE4.1 but not AVX, the vector insert
3101 // instruction is lowered into a X86insrtps rather than a X86Movss.
3102 // When selecting SSE scalar single-precision fp arithmetic instructions,
3103 // make sure that we correctly match the X86insrtps.
3105 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3106 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3107 FR32:$src))), (iPTR 0))),
3108 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3109 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3110 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3111 FR32:$src))), (iPTR 0))),
3112 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3113 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3114 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3115 FR32:$src))), (iPTR 0))),
3116 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3117 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3118 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3119 FR32:$src))), (iPTR 0))),
3120 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3123 let AddedComplexity = 20, Predicates = [HasAVX] in {
3124 // The following patterns select AVX Scalar single/double precision fp
3125 // arithmetic instructions.
3126 // The 'AddedComplexity' is required to give them higher priority over
3127 // the equivalent SSE/SSE2 patterns.
3129 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3130 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3132 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3133 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3134 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3136 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3137 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3138 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3140 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3141 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3142 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3144 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3145 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3146 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3147 FR32:$src))), (iPTR 0))),
3148 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3149 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3150 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3151 FR32:$src))), (iPTR 0))),
3152 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3153 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3154 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3155 FR32:$src))), (iPTR 0))),
3156 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3157 def : Pat<(v4f32 (X86insrtps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3158 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3159 FR32:$src))), (iPTR 0))),
3160 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3163 // Patterns used to select SSE scalar fp arithmetic instructions from
3164 // a vector packed single/double fp operation followed by a vector insert.
3166 // The effect is that the backend converts the packed fp instruction
3167 // followed by a vector insert into a single SSE scalar fp instruction.
3169 // For example, given the following code:
3170 // __m128 foo(__m128 A, __m128 B) {
3171 // __m128 C = A + B;
3172 // return (__m128) {c[0], a[1], a[2], a[3]};
3175 // previously we generated:
3176 // addps %xmm0, %xmm1
3177 // movss %xmm1, %xmm0
3180 // addss %xmm1, %xmm0
3182 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3183 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3184 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3185 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3186 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3187 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3188 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3189 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3190 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3191 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3192 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3193 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3195 let Predicates = [HasSSE2] in {
3196 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3197 // from a packed double-precision fp instruction plus movsd.
3199 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3200 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3201 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3202 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3203 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3204 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3205 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3206 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3207 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3208 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3209 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3210 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3213 let AddedComplexity = 20, Predicates = [HasAVX] in {
3214 // The following patterns select AVX Scalar single/double precision fp
3215 // arithmetic instructions from a packed single precision fp instruction
3216 // plus movss/movsd.
3217 // The 'AddedComplexity' is required to give them higher priority over
3218 // the equivalent SSE/SSE2 patterns.
3220 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3221 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3222 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3223 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3224 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3225 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3226 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3227 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3228 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3229 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3230 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3231 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3232 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3233 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3234 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3235 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3236 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3237 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3238 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3239 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3240 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3241 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3242 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3243 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3247 /// In addition, we also have a special variant of the scalar form here to
3248 /// represent the associated intrinsic operation. This form is unlike the
3249 /// plain scalar form, in that it takes an entire vector (instead of a
3250 /// scalar) and leaves the top elements undefined.
3252 /// And, we have a special variant form for a full-vector intrinsic form.
3254 let Sched = WriteFSqrt in {
3255 def SSE_SQRTPS : OpndItins<
3256 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3259 def SSE_SQRTSS : OpndItins<
3260 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3263 def SSE_SQRTPD : OpndItins<
3264 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3267 def SSE_SQRTSD : OpndItins<
3268 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3272 let Sched = WriteFRcp in {
3273 def SSE_RCPP : OpndItins<
3274 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3277 def SSE_RCPS : OpndItins<
3278 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3282 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3283 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3284 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3285 let Predicates = [HasAVX], hasSideEffects = 0 in {
3286 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3287 (ins FR32:$src1, FR32:$src2),
3288 !strconcat("v", OpcodeStr,
3289 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3290 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3291 let mayLoad = 1 in {
3292 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3293 (ins FR32:$src1,f32mem:$src2),
3294 !strconcat("v", OpcodeStr,
3295 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3296 []>, VEX_4V, VEX_LIG,
3297 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3298 let isCodeGenOnly = 1 in
3299 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3300 (ins VR128:$src1, ssmem:$src2),
3301 !strconcat("v", OpcodeStr,
3302 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3303 []>, VEX_4V, VEX_LIG,
3304 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3308 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3309 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3310 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3311 // For scalar unary operations, fold a load into the operation
3312 // only in OptForSize mode. It eliminates an instruction, but it also
3313 // eliminates a whole-register clobber (the load), so it introduces a
3314 // partial register update condition.
3315 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3316 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3317 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3318 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3319 let isCodeGenOnly = 1 in {
3320 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3321 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3322 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3323 Sched<[itins.Sched]>;
3324 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3325 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3326 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3327 Sched<[itins.Sched.Folded]>;
3331 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3332 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3334 let Predicates = [HasAVX], hasSideEffects = 0 in {
3335 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3336 (ins FR32:$src1, FR32:$src2),
3337 !strconcat("v", OpcodeStr,
3338 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3339 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3340 let mayLoad = 1 in {
3341 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3342 (ins FR32:$src1,f32mem:$src2),
3343 !strconcat("v", OpcodeStr,
3344 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3345 []>, VEX_4V, VEX_LIG,
3346 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3347 let isCodeGenOnly = 1 in
3348 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3349 (ins VR128:$src1, ssmem:$src2),
3350 !strconcat("v", OpcodeStr,
3351 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3352 []>, VEX_4V, VEX_LIG,
3353 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3357 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3358 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3359 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3360 // For scalar unary operations, fold a load into the operation
3361 // only in OptForSize mode. It eliminates an instruction, but it also
3362 // eliminates a whole-register clobber (the load), so it introduces a
3363 // partial register update condition.
3364 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3365 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3366 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3367 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3368 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3369 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3370 (ins VR128:$src1, VR128:$src2),
3371 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3372 [], itins.rr>, Sched<[itins.Sched]>;
3373 let mayLoad = 1, hasSideEffects = 0 in
3374 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3375 (ins VR128:$src1, ssmem:$src2),
3376 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3377 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3381 /// sse1_fp_unop_p - SSE1 unops in packed form.
3382 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3384 let Predicates = [HasAVX] in {
3385 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3386 !strconcat("v", OpcodeStr,
3387 "ps\t{$src, $dst|$dst, $src}"),
3388 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3389 itins.rr>, VEX, Sched<[itins.Sched]>;
3390 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3391 !strconcat("v", OpcodeStr,
3392 "ps\t{$src, $dst|$dst, $src}"),
3393 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3394 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3395 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3396 !strconcat("v", OpcodeStr,
3397 "ps\t{$src, $dst|$dst, $src}"),
3398 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3399 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3400 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3401 !strconcat("v", OpcodeStr,
3402 "ps\t{$src, $dst|$dst, $src}"),
3403 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3404 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3407 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3408 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3409 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3410 Sched<[itins.Sched]>;
3411 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3412 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3413 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3414 Sched<[itins.Sched.Folded]>;
3417 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3418 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3419 Intrinsic V4F32Int, Intrinsic V8F32Int,
3421 let isCodeGenOnly = 1 in {
3422 let Predicates = [HasAVX] in {
3423 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3424 !strconcat("v", OpcodeStr,
3425 "ps\t{$src, $dst|$dst, $src}"),
3426 [(set VR128:$dst, (V4F32Int VR128:$src))],
3427 itins.rr>, VEX, Sched<[itins.Sched]>;
3428 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3429 !strconcat("v", OpcodeStr,
3430 "ps\t{$src, $dst|$dst, $src}"),
3431 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3432 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3433 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3434 !strconcat("v", OpcodeStr,
3435 "ps\t{$src, $dst|$dst, $src}"),
3436 [(set VR256:$dst, (V8F32Int VR256:$src))],
3437 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3438 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3440 !strconcat("v", OpcodeStr,
3441 "ps\t{$src, $dst|$dst, $src}"),
3442 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3443 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3446 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3447 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3448 [(set VR128:$dst, (V4F32Int VR128:$src))],
3449 itins.rr>, Sched<[itins.Sched]>;
3450 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3451 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3452 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3453 itins.rm>, Sched<[itins.Sched.Folded]>;
3454 } // isCodeGenOnly = 1
3457 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3458 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3459 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3460 let Predicates = [HasAVX], hasSideEffects = 0 in {
3461 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3462 (ins FR64:$src1, FR64:$src2),
3463 !strconcat("v", OpcodeStr,
3464 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3465 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3466 let mayLoad = 1 in {
3467 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3468 (ins FR64:$src1,f64mem:$src2),
3469 !strconcat("v", OpcodeStr,
3470 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3471 []>, VEX_4V, VEX_LIG,
3472 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3473 let isCodeGenOnly = 1 in
3474 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3475 (ins VR128:$src1, sdmem:$src2),
3476 !strconcat("v", OpcodeStr,
3477 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3478 []>, VEX_4V, VEX_LIG,
3479 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3483 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3484 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3485 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3486 Sched<[itins.Sched]>;
3487 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3488 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3489 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3490 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3491 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3492 let isCodeGenOnly = 1 in {
3493 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3494 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3495 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3496 Sched<[itins.Sched]>;
3497 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3498 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3499 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3500 Sched<[itins.Sched.Folded]>;
3504 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3505 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3506 SDNode OpNode, OpndItins itins> {
3507 let Predicates = [HasAVX] in {
3508 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3509 !strconcat("v", OpcodeStr,
3510 "pd\t{$src, $dst|$dst, $src}"),
3511 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3512 itins.rr>, VEX, Sched<[itins.Sched]>;
3513 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3514 !strconcat("v", OpcodeStr,
3515 "pd\t{$src, $dst|$dst, $src}"),
3516 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3517 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3518 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3519 !strconcat("v", OpcodeStr,
3520 "pd\t{$src, $dst|$dst, $src}"),
3521 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3522 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3523 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3524 !strconcat("v", OpcodeStr,
3525 "pd\t{$src, $dst|$dst, $src}"),
3526 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3527 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3530 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3531 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3532 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3533 Sched<[itins.Sched]>;
3534 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3535 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3536 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3537 Sched<[itins.Sched.Folded]>;
3541 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3543 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3544 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3546 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3548 // Reciprocal approximations. Note that these typically require refinement
3549 // in order to obtain suitable precision.
3550 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTSS>,
3551 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTPS>,
3552 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3553 int_x86_avx_rsqrt_ps_256, SSE_SQRTPS>;
3554 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3555 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3556 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3557 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3559 let Predicates = [UseAVX] in {
3560 def : Pat<(f32 (fsqrt FR32:$src)),
3561 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3562 def : Pat<(f32 (fsqrt (load addr:$src))),
3563 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3564 Requires<[HasAVX, OptForSize]>;
3565 def : Pat<(f64 (fsqrt FR64:$src)),
3566 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3567 def : Pat<(f64 (fsqrt (load addr:$src))),
3568 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3569 Requires<[HasAVX, OptForSize]>;
3571 def : Pat<(f32 (X86frsqrt FR32:$src)),
3572 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3573 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3574 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3575 Requires<[HasAVX, OptForSize]>;
3577 def : Pat<(f32 (X86frcp FR32:$src)),
3578 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3579 def : Pat<(f32 (X86frcp (load addr:$src))),
3580 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3581 Requires<[HasAVX, OptForSize]>;
3583 let Predicates = [UseAVX] in {
3584 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3585 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3586 (COPY_TO_REGCLASS VR128:$src, FR32)),
3588 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3589 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3591 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3592 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3593 (COPY_TO_REGCLASS VR128:$src, FR64)),
3595 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3596 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3599 let Predicates = [HasAVX] in {
3600 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3601 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3602 (COPY_TO_REGCLASS VR128:$src, FR32)),
3604 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3605 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3607 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3608 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3609 (COPY_TO_REGCLASS VR128:$src, FR32)),
3611 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3612 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3615 // Reciprocal approximations. Note that these typically require refinement
3616 // in order to obtain suitable precision.
3617 let Predicates = [UseSSE1] in {
3618 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3619 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3620 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3621 (RCPSSr_Int VR128:$src, VR128:$src)>;
3624 // There is no f64 version of the reciprocal approximation instructions.
3626 //===----------------------------------------------------------------------===//
3627 // SSE 1 & 2 - Non-temporal stores
3628 //===----------------------------------------------------------------------===//
3630 let AddedComplexity = 400 in { // Prefer non-temporal versions
3631 let SchedRW = [WriteStore] in {
3632 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3633 (ins f128mem:$dst, VR128:$src),
3634 "movntps\t{$src, $dst|$dst, $src}",
3635 [(alignednontemporalstore (v4f32 VR128:$src),
3637 IIC_SSE_MOVNT>, VEX;
3638 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3639 (ins f128mem:$dst, VR128:$src),
3640 "movntpd\t{$src, $dst|$dst, $src}",
3641 [(alignednontemporalstore (v2f64 VR128:$src),
3643 IIC_SSE_MOVNT>, VEX;
3645 let ExeDomain = SSEPackedInt in
3646 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3647 (ins f128mem:$dst, VR128:$src),
3648 "movntdq\t{$src, $dst|$dst, $src}",
3649 [(alignednontemporalstore (v2i64 VR128:$src),
3651 IIC_SSE_MOVNT>, VEX;
3653 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3654 (ins f256mem:$dst, VR256:$src),
3655 "movntps\t{$src, $dst|$dst, $src}",
3656 [(alignednontemporalstore (v8f32 VR256:$src),
3658 IIC_SSE_MOVNT>, VEX, VEX_L;
3659 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3660 (ins f256mem:$dst, VR256:$src),
3661 "movntpd\t{$src, $dst|$dst, $src}",
3662 [(alignednontemporalstore (v4f64 VR256:$src),
3664 IIC_SSE_MOVNT>, VEX, VEX_L;
3665 let ExeDomain = SSEPackedInt in
3666 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3667 (ins f256mem:$dst, VR256:$src),
3668 "movntdq\t{$src, $dst|$dst, $src}",
3669 [(alignednontemporalstore (v4i64 VR256:$src),
3671 IIC_SSE_MOVNT>, VEX, VEX_L;
3673 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3674 "movntps\t{$src, $dst|$dst, $src}",
3675 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3677 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3678 "movntpd\t{$src, $dst|$dst, $src}",
3679 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3682 let ExeDomain = SSEPackedInt in
3683 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3684 "movntdq\t{$src, $dst|$dst, $src}",
3685 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3688 // There is no AVX form for instructions below this point
3689 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3690 "movnti{l}\t{$src, $dst|$dst, $src}",
3691 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3693 TB, Requires<[HasSSE2]>;
3694 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3695 "movnti{q}\t{$src, $dst|$dst, $src}",
3696 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3698 TB, Requires<[HasSSE2]>;
3699 } // SchedRW = [WriteStore]
3701 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3702 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3704 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3705 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3706 } // AddedComplexity
3708 //===----------------------------------------------------------------------===//
3709 // SSE 1 & 2 - Prefetch and memory fence
3710 //===----------------------------------------------------------------------===//
3712 // Prefetch intrinsic.
3713 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3714 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3715 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3716 IIC_SSE_PREFETCH>, TB;
3717 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3718 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3719 IIC_SSE_PREFETCH>, TB;
3720 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3721 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3722 IIC_SSE_PREFETCH>, TB;
3723 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3724 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3725 IIC_SSE_PREFETCH>, TB;
3728 // FIXME: How should these memory instructions be modeled?
3729 let SchedRW = [WriteLoad] in {
3731 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3732 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3733 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3735 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3736 // was introduced with SSE2, it's backward compatible.
3737 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3738 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3739 REP, Requires<[HasSSE2]>;
3741 // Load, store, and memory fence
3742 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3743 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3744 TB, Requires<[HasSSE1]>;
3745 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3746 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3747 TB, Requires<[HasSSE2]>;
3748 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3749 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3750 TB, Requires<[HasSSE2]>;
3753 def : Pat<(X86SFence), (SFENCE)>;
3754 def : Pat<(X86LFence), (LFENCE)>;
3755 def : Pat<(X86MFence), (MFENCE)>;
3757 //===----------------------------------------------------------------------===//
3758 // SSE 1 & 2 - Load/Store XCSR register
3759 //===----------------------------------------------------------------------===//
3761 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3762 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3763 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3764 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3765 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3766 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3768 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3769 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3770 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
3771 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3772 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3773 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
3775 //===---------------------------------------------------------------------===//
3776 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3777 //===---------------------------------------------------------------------===//
3779 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3781 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
3782 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3783 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3785 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3786 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3788 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3789 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3791 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3792 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3797 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3798 SchedRW = [WriteMove] in {
3799 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3800 "movdqa\t{$src, $dst|$dst, $src}", [],
3803 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3804 "movdqa\t{$src, $dst|$dst, $src}", [],
3805 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3806 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3807 "movdqu\t{$src, $dst|$dst, $src}", [],
3810 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3811 "movdqu\t{$src, $dst|$dst, $src}", [],
3812 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3815 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3816 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3817 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3818 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3820 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3821 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3823 let Predicates = [HasAVX] in {
3824 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3825 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3827 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3828 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3833 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3834 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3835 (ins i128mem:$dst, VR128:$src),
3836 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3838 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3839 (ins i256mem:$dst, VR256:$src),
3840 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3842 let Predicates = [HasAVX] in {
3843 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3844 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3846 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3847 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3852 let SchedRW = [WriteMove] in {
3853 let neverHasSideEffects = 1 in
3854 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3855 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3857 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3858 "movdqu\t{$src, $dst|$dst, $src}",
3859 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3862 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3863 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3864 "movdqa\t{$src, $dst|$dst, $src}", [],
3867 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3868 "movdqu\t{$src, $dst|$dst, $src}",
3869 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3873 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3874 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3875 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3876 "movdqa\t{$src, $dst|$dst, $src}",
3877 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3879 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3880 "movdqu\t{$src, $dst|$dst, $src}",
3881 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3883 XS, Requires<[UseSSE2]>;
3886 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3887 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3888 "movdqa\t{$src, $dst|$dst, $src}",
3889 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3891 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3892 "movdqu\t{$src, $dst|$dst, $src}",
3893 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3895 XS, Requires<[UseSSE2]>;
3898 } // ExeDomain = SSEPackedInt
3900 let Predicates = [HasAVX] in {
3901 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3902 (VMOVDQUmr addr:$dst, VR128:$src)>;
3903 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3904 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3906 let Predicates = [UseSSE2] in
3907 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3908 (MOVDQUmr addr:$dst, VR128:$src)>;
3910 //===---------------------------------------------------------------------===//
3911 // SSE2 - Packed Integer Arithmetic Instructions
3912 //===---------------------------------------------------------------------===//
3914 let Sched = WriteVecIMul in
3915 def SSE_PMADD : OpndItins<
3916 IIC_SSE_PMADD, IIC_SSE_PMADD
3919 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3921 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3922 RegisterClass RC, PatFrag memop_frag,
3923 X86MemOperand x86memop,
3925 bit IsCommutable = 0,
3927 let isCommutable = IsCommutable in
3928 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3929 (ins RC:$src1, RC:$src2),
3931 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3932 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3933 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3934 Sched<[itins.Sched]>;
3935 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3936 (ins RC:$src1, x86memop:$src2),
3938 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3939 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3940 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3941 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3944 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3945 Intrinsic IntId256, OpndItins itins,
3946 bit IsCommutable = 0> {
3947 let Predicates = [HasAVX] in
3948 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3949 VR128, loadv2i64, i128mem, itins,
3950 IsCommutable, 0>, VEX_4V;
3952 let Constraints = "$src1 = $dst" in
3953 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3954 i128mem, itins, IsCommutable, 1>;
3956 let Predicates = [HasAVX2] in
3957 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3958 VR256, loadv4i64, i256mem, itins,
3959 IsCommutable, 0>, VEX_4V, VEX_L;
3962 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3963 string OpcodeStr, SDNode OpNode,
3964 SDNode OpNode2, RegisterClass RC,
3965 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3966 ShiftOpndItins itins,
3968 // src2 is always 128-bit
3969 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3970 (ins RC:$src1, VR128:$src2),
3972 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3973 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3974 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3975 itins.rr>, Sched<[WriteVecShift]>;
3976 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3977 (ins RC:$src1, i128mem:$src2),
3979 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3980 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3981 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3982 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
3983 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3984 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3985 (ins RC:$src1, i8imm:$src2),
3987 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3988 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3989 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3990 Sched<[WriteVecShift]>;
3993 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3994 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3995 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3996 PatFrag memop_frag, X86MemOperand x86memop,
3998 bit IsCommutable = 0, bit Is2Addr = 1> {
3999 let isCommutable = IsCommutable in
4000 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4001 (ins RC:$src1, RC:$src2),
4003 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4004 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4005 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4006 Sched<[itins.Sched]>;
4007 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4008 (ins RC:$src1, x86memop:$src2),
4010 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4011 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4012 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4013 (bitconvert (memop_frag addr:$src2)))))]>,
4014 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4016 } // ExeDomain = SSEPackedInt
4018 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4019 SSE_INTALU_ITINS_P, 1>;
4020 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4021 SSE_INTALU_ITINS_P, 1>;
4022 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4023 SSE_INTALU_ITINS_P, 1>;
4024 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4025 SSE_INTALUQ_ITINS_P, 1>;
4026 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4027 SSE_INTMUL_ITINS_P, 1>;
4028 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4029 SSE_INTALU_ITINS_P, 0>;
4030 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4031 SSE_INTALU_ITINS_P, 0>;
4032 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4033 SSE_INTALU_ITINS_P, 0>;
4034 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4035 SSE_INTALUQ_ITINS_P, 0>;
4036 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4037 SSE_INTALU_ITINS_P, 0>;
4038 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4039 SSE_INTALU_ITINS_P, 0>;
4040 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4041 SSE_INTALU_ITINS_P, 1>;
4042 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4043 SSE_INTALU_ITINS_P, 1>;
4044 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4045 SSE_INTALU_ITINS_P, 1>;
4046 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4047 SSE_INTALU_ITINS_P, 1>;
4050 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4051 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4052 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4053 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4054 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4055 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4056 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4057 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4058 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4059 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4060 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4061 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4062 defm PMULHUW : PDI_binop_all_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
4063 int_x86_avx2_pmulhu_w, SSE_INTMUL_ITINS_P, 1>;
4064 defm PMULHW : PDI_binop_all_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
4065 int_x86_avx2_pmulh_w, SSE_INTMUL_ITINS_P, 1>;
4066 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4067 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4068 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4069 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4070 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4071 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4072 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4073 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4075 let Predicates = [HasAVX] in
4076 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4077 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4079 let Predicates = [HasAVX2] in
4080 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4081 VR256, loadv4i64, i256mem,
4082 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4083 let Constraints = "$src1 = $dst" in
4084 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4085 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4087 //===---------------------------------------------------------------------===//
4088 // SSE2 - Packed Integer Logical Instructions
4089 //===---------------------------------------------------------------------===//
4091 let Predicates = [HasAVX] in {
4092 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4093 VR128, v8i16, v8i16, bc_v8i16,
4094 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4095 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4096 VR128, v4i32, v4i32, bc_v4i32,
4097 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4098 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4099 VR128, v2i64, v2i64, bc_v2i64,
4100 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4102 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4103 VR128, v8i16, v8i16, bc_v8i16,
4104 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4105 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4106 VR128, v4i32, v4i32, bc_v4i32,
4107 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4108 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4109 VR128, v2i64, v2i64, bc_v2i64,
4110 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4112 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4113 VR128, v8i16, v8i16, bc_v8i16,
4114 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4115 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4116 VR128, v4i32, v4i32, bc_v4i32,
4117 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4119 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4120 // 128-bit logical shifts.
4121 def VPSLLDQri : PDIi8<0x73, MRM7r,
4122 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4123 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4125 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
4127 def VPSRLDQri : PDIi8<0x73, MRM3r,
4128 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4129 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4131 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
4133 // PSRADQri doesn't exist in SSE[1-3].
4135 } // Predicates = [HasAVX]
4137 let Predicates = [HasAVX2] in {
4138 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4139 VR256, v16i16, v8i16, bc_v8i16,
4140 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4141 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4142 VR256, v8i32, v4i32, bc_v4i32,
4143 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4144 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4145 VR256, v4i64, v2i64, bc_v2i64,
4146 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4148 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4149 VR256, v16i16, v8i16, bc_v8i16,
4150 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4151 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4152 VR256, v8i32, v4i32, bc_v4i32,
4153 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4154 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4155 VR256, v4i64, v2i64, bc_v2i64,
4156 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4158 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4159 VR256, v16i16, v8i16, bc_v8i16,
4160 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4161 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4162 VR256, v8i32, v4i32, bc_v4i32,
4163 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4165 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4166 // 256-bit logical shifts.
4167 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4168 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4169 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4171 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4173 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4174 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4175 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4177 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4179 // PSRADQYri doesn't exist in SSE[1-3].
4181 } // Predicates = [HasAVX2]
4183 let Constraints = "$src1 = $dst" in {
4184 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4185 VR128, v8i16, v8i16, bc_v8i16,
4186 SSE_INTSHIFT_ITINS_P>;
4187 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4188 VR128, v4i32, v4i32, bc_v4i32,
4189 SSE_INTSHIFT_ITINS_P>;
4190 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4191 VR128, v2i64, v2i64, bc_v2i64,
4192 SSE_INTSHIFT_ITINS_P>;
4194 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4195 VR128, v8i16, v8i16, bc_v8i16,
4196 SSE_INTSHIFT_ITINS_P>;
4197 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4198 VR128, v4i32, v4i32, bc_v4i32,
4199 SSE_INTSHIFT_ITINS_P>;
4200 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4201 VR128, v2i64, v2i64, bc_v2i64,
4202 SSE_INTSHIFT_ITINS_P>;
4204 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4205 VR128, v8i16, v8i16, bc_v8i16,
4206 SSE_INTSHIFT_ITINS_P>;
4207 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4208 VR128, v4i32, v4i32, bc_v4i32,
4209 SSE_INTSHIFT_ITINS_P>;
4211 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4212 // 128-bit logical shifts.
4213 def PSLLDQri : PDIi8<0x73, MRM7r,
4214 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4215 "pslldq\t{$src2, $dst|$dst, $src2}",
4217 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
4218 IIC_SSE_INTSHDQ_P_RI>;
4219 def PSRLDQri : PDIi8<0x73, MRM3r,
4220 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4221 "psrldq\t{$src2, $dst|$dst, $src2}",
4223 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
4224 IIC_SSE_INTSHDQ_P_RI>;
4225 // PSRADQri doesn't exist in SSE[1-3].
4227 } // Constraints = "$src1 = $dst"
4229 let Predicates = [HasAVX] in {
4230 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4231 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4232 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4233 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4234 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4235 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4237 // Shift up / down and insert zero's.
4238 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4239 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4240 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4241 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4244 let Predicates = [HasAVX2] in {
4245 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4246 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4247 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4248 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4251 let Predicates = [UseSSE2] in {
4252 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4253 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4254 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4255 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4256 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4257 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4259 // Shift up / down and insert zero's.
4260 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4261 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4262 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4263 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4266 //===---------------------------------------------------------------------===//
4267 // SSE2 - Packed Integer Comparison Instructions
4268 //===---------------------------------------------------------------------===//
4270 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4271 SSE_INTALU_ITINS_P, 1>;
4272 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4273 SSE_INTALU_ITINS_P, 1>;
4274 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4275 SSE_INTALU_ITINS_P, 1>;
4276 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4277 SSE_INTALU_ITINS_P, 0>;
4278 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4279 SSE_INTALU_ITINS_P, 0>;
4280 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4281 SSE_INTALU_ITINS_P, 0>;
4283 //===---------------------------------------------------------------------===//
4284 // SSE2 - Packed Integer Pack Instructions
4285 //===---------------------------------------------------------------------===//
4287 defm PACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4288 int_x86_avx2_packsswb, SSE_INTALU_ITINS_P, 0>;
4289 defm PACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4290 int_x86_avx2_packssdw, SSE_INTALU_ITINS_P, 0>;
4291 defm PACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4292 int_x86_avx2_packuswb, SSE_INTALU_ITINS_P, 0>;
4294 //===---------------------------------------------------------------------===//
4295 // SSE2 - Packed Integer Shuffle Instructions
4296 //===---------------------------------------------------------------------===//
4298 let ExeDomain = SSEPackedInt in {
4299 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4301 let Predicates = [HasAVX] in {
4302 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4303 (ins VR128:$src1, i8imm:$src2),
4304 !strconcat("v", OpcodeStr,
4305 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4307 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4308 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4309 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4310 (ins i128mem:$src1, i8imm:$src2),
4311 !strconcat("v", OpcodeStr,
4312 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4314 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4315 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4316 Sched<[WriteShuffleLd]>;
4319 let Predicates = [HasAVX2] in {
4320 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4321 (ins VR256:$src1, i8imm:$src2),
4322 !strconcat("v", OpcodeStr,
4323 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4325 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4326 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4327 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4328 (ins i256mem:$src1, i8imm:$src2),
4329 !strconcat("v", OpcodeStr,
4330 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4332 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4333 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4334 Sched<[WriteShuffleLd]>;
4337 let Predicates = [UseSSE2] in {
4338 def ri : Ii8<0x70, MRMSrcReg,
4339 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4340 !strconcat(OpcodeStr,
4341 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4343 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4344 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4345 def mi : Ii8<0x70, MRMSrcMem,
4346 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4347 !strconcat(OpcodeStr,
4348 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4350 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4351 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4352 Sched<[WriteShuffleLd]>;
4355 } // ExeDomain = SSEPackedInt
4357 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, TB, OpSize;
4358 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4359 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4361 let Predicates = [HasAVX] in {
4362 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4363 (VPSHUFDmi addr:$src1, imm:$imm)>;
4364 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4365 (VPSHUFDri VR128:$src1, imm:$imm)>;
4368 let Predicates = [UseSSE2] in {
4369 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4370 (PSHUFDmi addr:$src1, imm:$imm)>;
4371 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4372 (PSHUFDri VR128:$src1, imm:$imm)>;
4375 //===---------------------------------------------------------------------===//
4376 // SSE2 - Packed Integer Unpack Instructions
4377 //===---------------------------------------------------------------------===//
4379 let ExeDomain = SSEPackedInt in {
4380 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4381 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4382 def rr : PDI<opc, MRMSrcReg,
4383 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4385 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4386 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4387 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4388 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4389 def rm : PDI<opc, MRMSrcMem,
4390 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4392 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4393 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4394 [(set VR128:$dst, (OpNode VR128:$src1,
4395 (bc_frag (memopv2i64
4398 Sched<[WriteShuffleLd, ReadAfterLd]>;
4401 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4402 SDNode OpNode, PatFrag bc_frag> {
4403 def Yrr : PDI<opc, MRMSrcReg,
4404 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4405 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4406 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4407 Sched<[WriteShuffle]>;
4408 def Yrm : PDI<opc, MRMSrcMem,
4409 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4410 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4411 [(set VR256:$dst, (OpNode VR256:$src1,
4412 (bc_frag (memopv4i64 addr:$src2))))]>,
4413 Sched<[WriteShuffleLd, ReadAfterLd]>;
4416 let Predicates = [HasAVX] in {
4417 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4418 bc_v16i8, 0>, VEX_4V;
4419 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4420 bc_v8i16, 0>, VEX_4V;
4421 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4422 bc_v4i32, 0>, VEX_4V;
4423 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4424 bc_v2i64, 0>, VEX_4V;
4426 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4427 bc_v16i8, 0>, VEX_4V;
4428 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4429 bc_v8i16, 0>, VEX_4V;
4430 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4431 bc_v4i32, 0>, VEX_4V;
4432 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4433 bc_v2i64, 0>, VEX_4V;
4436 let Predicates = [HasAVX2] in {
4437 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4438 bc_v32i8>, VEX_4V, VEX_L;
4439 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4440 bc_v16i16>, VEX_4V, VEX_L;
4441 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4442 bc_v8i32>, VEX_4V, VEX_L;
4443 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4444 bc_v4i64>, VEX_4V, VEX_L;
4446 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4447 bc_v32i8>, VEX_4V, VEX_L;
4448 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4449 bc_v16i16>, VEX_4V, VEX_L;
4450 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4451 bc_v8i32>, VEX_4V, VEX_L;
4452 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4453 bc_v4i64>, VEX_4V, VEX_L;
4456 let Constraints = "$src1 = $dst" in {
4457 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4459 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4461 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4463 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4466 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4468 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4470 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4472 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4475 } // ExeDomain = SSEPackedInt
4477 //===---------------------------------------------------------------------===//
4478 // SSE2 - Packed Integer Extract and Insert
4479 //===---------------------------------------------------------------------===//
4481 let ExeDomain = SSEPackedInt in {
4482 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4483 def rri : Ii8<0xC4, MRMSrcReg,
4484 (outs VR128:$dst), (ins VR128:$src1,
4485 GR32orGR64:$src2, i32i8imm:$src3),
4487 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4488 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4490 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4491 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4492 def rmi : Ii8<0xC4, MRMSrcMem,
4493 (outs VR128:$dst), (ins VR128:$src1,
4494 i16mem:$src2, i32i8imm:$src3),
4496 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4497 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4499 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4500 imm:$src3))], IIC_SSE_PINSRW>,
4501 Sched<[WriteShuffleLd, ReadAfterLd]>;
4505 let Predicates = [HasAVX] in
4506 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4507 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4508 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4509 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4510 imm:$src2))]>, TB, OpSize, VEX,
4511 Sched<[WriteShuffle]>;
4512 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4513 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4514 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4515 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4516 imm:$src2))], IIC_SSE_PEXTRW>,
4517 Sched<[WriteShuffleLd, ReadAfterLd]>;
4520 let Predicates = [HasAVX] in
4521 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4523 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4524 defm PINSRW : sse2_pinsrw, TB, OpSize;
4526 } // ExeDomain = SSEPackedInt
4528 //===---------------------------------------------------------------------===//
4529 // SSE2 - Packed Mask Creation
4530 //===---------------------------------------------------------------------===//
4532 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4534 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4536 "pmovmskb\t{$src, $dst|$dst, $src}",
4537 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4538 IIC_SSE_MOVMSK>, VEX;
4540 let Predicates = [HasAVX2] in {
4541 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4543 "pmovmskb\t{$src, $dst|$dst, $src}",
4544 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4548 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4549 "pmovmskb\t{$src, $dst|$dst, $src}",
4550 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4553 } // ExeDomain = SSEPackedInt
4555 //===---------------------------------------------------------------------===//
4556 // SSE2 - Conditional Store
4557 //===---------------------------------------------------------------------===//
4559 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4561 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4562 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4563 (ins VR128:$src, VR128:$mask),
4564 "maskmovdqu\t{$mask, $src|$src, $mask}",
4565 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4566 IIC_SSE_MASKMOV>, VEX;
4567 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4568 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4569 (ins VR128:$src, VR128:$mask),
4570 "maskmovdqu\t{$mask, $src|$src, $mask}",
4571 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4572 IIC_SSE_MASKMOV>, VEX;
4574 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4575 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4576 "maskmovdqu\t{$mask, $src|$src, $mask}",
4577 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4579 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4580 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4581 "maskmovdqu\t{$mask, $src|$src, $mask}",
4582 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4585 } // ExeDomain = SSEPackedInt
4587 //===---------------------------------------------------------------------===//
4588 // SSE2 - Move Doubleword
4589 //===---------------------------------------------------------------------===//
4591 //===---------------------------------------------------------------------===//
4592 // Move Int Doubleword to Packed Double Int
4594 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4595 "movd\t{$src, $dst|$dst, $src}",
4597 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4598 VEX, Sched<[WriteMove]>;
4599 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4600 "movd\t{$src, $dst|$dst, $src}",
4602 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4604 VEX, Sched<[WriteLoad]>;
4605 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4606 "movq\t{$src, $dst|$dst, $src}",
4608 (v2i64 (scalar_to_vector GR64:$src)))],
4609 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4610 let isCodeGenOnly = 1 in
4611 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4612 "movq\t{$src, $dst|$dst, $src}",
4613 [(set FR64:$dst, (bitconvert GR64:$src))],
4614 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4616 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4617 "movd\t{$src, $dst|$dst, $src}",
4619 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4621 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4622 "movd\t{$src, $dst|$dst, $src}",
4624 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4625 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4626 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4627 "mov{d|q}\t{$src, $dst|$dst, $src}",
4629 (v2i64 (scalar_to_vector GR64:$src)))],
4630 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4631 let isCodeGenOnly = 1 in
4632 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4633 "mov{d|q}\t{$src, $dst|$dst, $src}",
4634 [(set FR64:$dst, (bitconvert GR64:$src))],
4635 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4637 //===---------------------------------------------------------------------===//
4638 // Move Int Doubleword to Single Scalar
4640 let isCodeGenOnly = 1 in {
4641 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4642 "movd\t{$src, $dst|$dst, $src}",
4643 [(set FR32:$dst, (bitconvert GR32:$src))],
4644 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4646 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4647 "movd\t{$src, $dst|$dst, $src}",
4648 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4650 VEX, Sched<[WriteLoad]>;
4651 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4652 "movd\t{$src, $dst|$dst, $src}",
4653 [(set FR32:$dst, (bitconvert GR32:$src))],
4654 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4656 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4657 "movd\t{$src, $dst|$dst, $src}",
4658 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4659 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4662 //===---------------------------------------------------------------------===//
4663 // Move Packed Doubleword Int to Packed Double Int
4665 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4666 "movd\t{$src, $dst|$dst, $src}",
4667 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4668 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4670 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4671 (ins i32mem:$dst, VR128:$src),
4672 "movd\t{$src, $dst|$dst, $src}",
4673 [(store (i32 (vector_extract (v4i32 VR128:$src),
4674 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4675 VEX, Sched<[WriteLoad]>;
4676 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4677 "movd\t{$src, $dst|$dst, $src}",
4678 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4679 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4681 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4682 "movd\t{$src, $dst|$dst, $src}",
4683 [(store (i32 (vector_extract (v4i32 VR128:$src),
4684 (iPTR 0))), addr:$dst)],
4685 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4687 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4688 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4690 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4691 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4693 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4694 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4696 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4697 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4699 //===---------------------------------------------------------------------===//
4700 // Move Packed Doubleword Int first element to Doubleword Int
4702 let SchedRW = [WriteMove] in {
4703 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4704 "movq\t{$src, $dst|$dst, $src}",
4705 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4710 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4711 "mov{d|q}\t{$src, $dst|$dst, $src}",
4712 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4717 //===---------------------------------------------------------------------===//
4718 // Bitcast FR64 <-> GR64
4720 let isCodeGenOnly = 1 in {
4721 let Predicates = [UseAVX] in
4722 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4723 "movq\t{$src, $dst|$dst, $src}",
4724 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4725 VEX, Sched<[WriteLoad]>;
4726 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4727 "movq\t{$src, $dst|$dst, $src}",
4728 [(set GR64:$dst, (bitconvert FR64:$src))],
4729 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4730 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4731 "movq\t{$src, $dst|$dst, $src}",
4732 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4733 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4735 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4736 "movq\t{$src, $dst|$dst, $src}",
4737 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4738 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4739 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4740 "mov{d|q}\t{$src, $dst|$dst, $src}",
4741 [(set GR64:$dst, (bitconvert FR64:$src))],
4742 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4743 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4744 "movq\t{$src, $dst|$dst, $src}",
4745 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4746 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4749 //===---------------------------------------------------------------------===//
4750 // Move Scalar Single to Double Int
4752 let isCodeGenOnly = 1 in {
4753 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4754 "movd\t{$src, $dst|$dst, $src}",
4755 [(set GR32:$dst, (bitconvert FR32:$src))],
4756 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4757 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4758 "movd\t{$src, $dst|$dst, $src}",
4759 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4760 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4761 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4762 "movd\t{$src, $dst|$dst, $src}",
4763 [(set GR32:$dst, (bitconvert FR32:$src))],
4764 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4765 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4766 "movd\t{$src, $dst|$dst, $src}",
4767 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4768 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4771 //===---------------------------------------------------------------------===//
4772 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4774 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4775 let AddedComplexity = 15 in {
4776 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4777 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4778 [(set VR128:$dst, (v2i64 (X86vzmovl
4779 (v2i64 (scalar_to_vector GR64:$src)))))],
4782 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4783 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4784 [(set VR128:$dst, (v2i64 (X86vzmovl
4785 (v2i64 (scalar_to_vector GR64:$src)))))],
4788 } // isCodeGenOnly, SchedRW
4790 let Predicates = [UseAVX] in {
4791 let AddedComplexity = 15 in
4792 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4793 (VMOVDI2PDIrr GR32:$src)>;
4795 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4796 let AddedComplexity = 20 in {
4797 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4798 (VMOVDI2PDIrm addr:$src)>;
4799 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4800 (VMOVDI2PDIrm addr:$src)>;
4801 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4802 (VMOVDI2PDIrm addr:$src)>;
4804 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4805 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4806 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4807 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4808 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4809 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4810 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4813 let Predicates = [UseSSE2] in {
4814 let AddedComplexity = 15 in
4815 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4816 (MOVDI2PDIrr GR32:$src)>;
4818 let AddedComplexity = 20 in {
4819 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4820 (MOVDI2PDIrm addr:$src)>;
4821 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4822 (MOVDI2PDIrm addr:$src)>;
4823 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4824 (MOVDI2PDIrm addr:$src)>;
4828 // These are the correct encodings of the instructions so that we know how to
4829 // read correct assembly, even though we continue to emit the wrong ones for
4830 // compatibility with Darwin's buggy assembler.
4831 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4832 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4833 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4834 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4835 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4836 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4837 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4838 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4839 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4841 //===---------------------------------------------------------------------===//
4842 // SSE2 - Move Quadword
4843 //===---------------------------------------------------------------------===//
4845 //===---------------------------------------------------------------------===//
4846 // Move Quadword Int to Packed Quadword Int
4849 let SchedRW = [WriteLoad] in {
4850 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4851 "vmovq\t{$src, $dst|$dst, $src}",
4853 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4854 VEX, Requires<[UseAVX]>;
4855 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4856 "movq\t{$src, $dst|$dst, $src}",
4858 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4860 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4863 //===---------------------------------------------------------------------===//
4864 // Move Packed Quadword Int to Quadword Int
4866 let SchedRW = [WriteStore] in {
4867 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4868 "movq\t{$src, $dst|$dst, $src}",
4869 [(store (i64 (vector_extract (v2i64 VR128:$src),
4870 (iPTR 0))), addr:$dst)],
4871 IIC_SSE_MOVDQ>, VEX;
4872 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4873 "movq\t{$src, $dst|$dst, $src}",
4874 [(store (i64 (vector_extract (v2i64 VR128:$src),
4875 (iPTR 0))), addr:$dst)],
4879 // For disassembler only
4880 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4881 SchedRW = [WriteVecLogic] in {
4882 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4883 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
4884 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4885 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
4888 //===---------------------------------------------------------------------===//
4889 // Store / copy lower 64-bits of a XMM register.
4891 let Predicates = [UseAVX] in
4892 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
4893 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
4894 let Predicates = [UseSSE2] in
4895 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
4896 (MOVPQI2QImr addr:$dst, VR128:$src)>;
4898 let isCodeGenOnly = 1, AddedComplexity = 20 in {
4899 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4900 "vmovq\t{$src, $dst|$dst, $src}",
4902 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4903 (loadi64 addr:$src))))))],
4905 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
4907 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4908 "movq\t{$src, $dst|$dst, $src}",
4910 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4911 (loadi64 addr:$src))))))],
4913 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
4916 let Predicates = [UseAVX], AddedComplexity = 20 in {
4917 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4918 (VMOVZQI2PQIrm addr:$src)>;
4919 def : Pat<(v2i64 (X86vzload addr:$src)),
4920 (VMOVZQI2PQIrm addr:$src)>;
4923 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4924 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4925 (MOVZQI2PQIrm addr:$src)>;
4926 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4929 let Predicates = [HasAVX] in {
4930 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4931 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4932 def : Pat<(v4i64 (X86vzload addr:$src)),
4933 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4936 //===---------------------------------------------------------------------===//
4937 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4938 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4940 let SchedRW = [WriteVecLogic] in {
4941 let AddedComplexity = 15 in
4942 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4943 "vmovq\t{$src, $dst|$dst, $src}",
4944 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4946 XS, VEX, Requires<[UseAVX]>;
4947 let AddedComplexity = 15 in
4948 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4949 "movq\t{$src, $dst|$dst, $src}",
4950 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4952 XS, Requires<[UseSSE2]>;
4955 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
4956 let AddedComplexity = 20 in
4957 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4958 "vmovq\t{$src, $dst|$dst, $src}",
4959 [(set VR128:$dst, (v2i64 (X86vzmovl
4960 (loadv2i64 addr:$src))))],
4962 XS, VEX, Requires<[UseAVX]>;
4963 let AddedComplexity = 20 in {
4964 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4965 "movq\t{$src, $dst|$dst, $src}",
4966 [(set VR128:$dst, (v2i64 (X86vzmovl
4967 (loadv2i64 addr:$src))))],
4969 XS, Requires<[UseSSE2]>;
4971 } // isCodeGenOnly, SchedRW
4973 let AddedComplexity = 20 in {
4974 let Predicates = [UseAVX] in {
4975 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4976 (VMOVZPQILo2PQIrr VR128:$src)>;
4978 let Predicates = [UseSSE2] in {
4979 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4980 (MOVZPQILo2PQIrr VR128:$src)>;
4984 //===---------------------------------------------------------------------===//
4985 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4986 //===---------------------------------------------------------------------===//
4987 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4988 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4989 X86MemOperand x86memop> {
4990 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4991 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4992 [(set RC:$dst, (vt (OpNode RC:$src)))],
4993 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4994 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4995 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4996 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4997 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
5000 let Predicates = [HasAVX] in {
5001 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5002 v4f32, VR128, loadv4f32, f128mem>, VEX;
5003 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5004 v4f32, VR128, loadv4f32, f128mem>, VEX;
5005 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5006 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5007 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5008 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5010 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5011 memopv4f32, f128mem>;
5012 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5013 memopv4f32, f128mem>;
5015 let Predicates = [HasAVX] in {
5016 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5017 (VMOVSHDUPrr VR128:$src)>;
5018 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5019 (VMOVSHDUPrm addr:$src)>;
5020 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5021 (VMOVSLDUPrr VR128:$src)>;
5022 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5023 (VMOVSLDUPrm addr:$src)>;
5024 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5025 (VMOVSHDUPYrr VR256:$src)>;
5026 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5027 (VMOVSHDUPYrm addr:$src)>;
5028 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5029 (VMOVSLDUPYrr VR256:$src)>;
5030 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5031 (VMOVSLDUPYrm addr:$src)>;
5034 let Predicates = [UseSSE3] in {
5035 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5036 (MOVSHDUPrr VR128:$src)>;
5037 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5038 (MOVSHDUPrm addr:$src)>;
5039 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5040 (MOVSLDUPrr VR128:$src)>;
5041 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5042 (MOVSLDUPrm addr:$src)>;
5045 //===---------------------------------------------------------------------===//
5046 // SSE3 - Replicate Double FP - MOVDDUP
5047 //===---------------------------------------------------------------------===//
5049 multiclass sse3_replicate_dfp<string OpcodeStr> {
5050 let neverHasSideEffects = 1 in
5051 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5052 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5053 [], IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
5054 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5055 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5058 (scalar_to_vector (loadf64 addr:$src)))))],
5059 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
5062 // FIXME: Merge with above classe when there're patterns for the ymm version
5063 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5064 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5065 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5066 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5067 Sched<[WriteShuffle]>;
5068 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5069 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5072 (scalar_to_vector (loadf64 addr:$src)))))]>,
5073 Sched<[WriteShuffleLd]>;
5076 let Predicates = [HasAVX] in {
5077 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5078 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5081 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5083 let Predicates = [HasAVX] in {
5084 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5085 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5086 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5087 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5088 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5089 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5090 def : Pat<(X86Movddup (bc_v2f64
5091 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5092 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5095 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5096 (VMOVDDUPYrm addr:$src)>;
5097 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5098 (VMOVDDUPYrm addr:$src)>;
5099 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5100 (VMOVDDUPYrm addr:$src)>;
5101 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5102 (VMOVDDUPYrr VR256:$src)>;
5105 let Predicates = [UseSSE3] in {
5106 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5107 (MOVDDUPrm addr:$src)>;
5108 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5109 (MOVDDUPrm addr:$src)>;
5110 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5111 (MOVDDUPrm addr:$src)>;
5112 def : Pat<(X86Movddup (bc_v2f64
5113 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5114 (MOVDDUPrm addr:$src)>;
5117 //===---------------------------------------------------------------------===//
5118 // SSE3 - Move Unaligned Integer
5119 //===---------------------------------------------------------------------===//
5121 let SchedRW = [WriteLoad] in {
5122 let Predicates = [HasAVX] in {
5123 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5124 "vlddqu\t{$src, $dst|$dst, $src}",
5125 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5126 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5127 "vlddqu\t{$src, $dst|$dst, $src}",
5128 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5131 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5132 "lddqu\t{$src, $dst|$dst, $src}",
5133 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5137 //===---------------------------------------------------------------------===//
5138 // SSE3 - Arithmetic
5139 //===---------------------------------------------------------------------===//
5141 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5142 X86MemOperand x86memop, OpndItins itins,
5144 def rr : I<0xD0, MRMSrcReg,
5145 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5147 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5148 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5149 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5150 Sched<[itins.Sched]>;
5151 def rm : I<0xD0, MRMSrcMem,
5152 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5154 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5155 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5156 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
5157 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5160 let Predicates = [HasAVX] in {
5161 let ExeDomain = SSEPackedSingle in {
5162 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5163 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5164 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5165 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
5167 let ExeDomain = SSEPackedDouble in {
5168 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5169 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5170 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5171 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
5174 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5175 let ExeDomain = SSEPackedSingle in
5176 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5177 f128mem, SSE_ALU_F32P>, TB, XD;
5178 let ExeDomain = SSEPackedDouble in
5179 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5180 f128mem, SSE_ALU_F64P>, TB, OpSize;
5183 //===---------------------------------------------------------------------===//
5184 // SSE3 Instructions
5185 //===---------------------------------------------------------------------===//
5188 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5189 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5190 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5192 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5193 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5194 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5197 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5199 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5200 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5201 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5202 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5204 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5205 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5206 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5208 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5209 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5210 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5213 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5215 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5216 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5217 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5218 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5221 let Predicates = [HasAVX] in {
5222 let ExeDomain = SSEPackedSingle in {
5223 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5224 X86fhadd, 0>, VEX_4V;
5225 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5226 X86fhsub, 0>, VEX_4V;
5227 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5228 X86fhadd, 0>, VEX_4V, VEX_L;
5229 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5230 X86fhsub, 0>, VEX_4V, VEX_L;
5232 let ExeDomain = SSEPackedDouble in {
5233 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5234 X86fhadd, 0>, VEX_4V;
5235 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5236 X86fhsub, 0>, VEX_4V;
5237 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5238 X86fhadd, 0>, VEX_4V, VEX_L;
5239 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5240 X86fhsub, 0>, VEX_4V, VEX_L;
5244 let Constraints = "$src1 = $dst" in {
5245 let ExeDomain = SSEPackedSingle in {
5246 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5247 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5249 let ExeDomain = SSEPackedDouble in {
5250 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5251 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5255 //===---------------------------------------------------------------------===//
5256 // SSSE3 - Packed Absolute Instructions
5257 //===---------------------------------------------------------------------===//
5260 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5261 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5262 Intrinsic IntId128> {
5263 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5265 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5266 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5267 OpSize, Sched<[WriteVecALU]>;
5269 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5271 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5274 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5275 OpSize, Sched<[WriteVecALULd]>;
5278 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5279 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5280 Intrinsic IntId256> {
5281 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5283 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5284 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5285 OpSize, Sched<[WriteVecALU]>;
5287 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5289 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5292 (bitconvert (memopv4i64 addr:$src))))]>, OpSize,
5293 Sched<[WriteVecALULd]>;
5296 // Helper fragments to match sext vXi1 to vXiY.
5297 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5299 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5300 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5301 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5303 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5304 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5306 let Predicates = [HasAVX] in {
5307 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5308 int_x86_ssse3_pabs_b_128>, VEX;
5309 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5310 int_x86_ssse3_pabs_w_128>, VEX;
5311 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5312 int_x86_ssse3_pabs_d_128>, VEX;
5315 (bc_v2i64 (v16i1sextv16i8)),
5316 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5317 (VPABSBrr128 VR128:$src)>;
5319 (bc_v2i64 (v8i1sextv8i16)),
5320 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5321 (VPABSWrr128 VR128:$src)>;
5323 (bc_v2i64 (v4i1sextv4i32)),
5324 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5325 (VPABSDrr128 VR128:$src)>;
5328 let Predicates = [HasAVX2] in {
5329 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5330 int_x86_avx2_pabs_b>, VEX, VEX_L;
5331 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5332 int_x86_avx2_pabs_w>, VEX, VEX_L;
5333 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5334 int_x86_avx2_pabs_d>, VEX, VEX_L;
5337 (bc_v4i64 (v32i1sextv32i8)),
5338 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5339 (VPABSBrr256 VR256:$src)>;
5341 (bc_v4i64 (v16i1sextv16i16)),
5342 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5343 (VPABSWrr256 VR256:$src)>;
5345 (bc_v4i64 (v8i1sextv8i32)),
5346 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5347 (VPABSDrr256 VR256:$src)>;
5350 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5351 int_x86_ssse3_pabs_b_128>;
5352 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5353 int_x86_ssse3_pabs_w_128>;
5354 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5355 int_x86_ssse3_pabs_d_128>;
5357 let Predicates = [HasSSSE3] in {
5359 (bc_v2i64 (v16i1sextv16i8)),
5360 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5361 (PABSBrr128 VR128:$src)>;
5363 (bc_v2i64 (v8i1sextv8i16)),
5364 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5365 (PABSWrr128 VR128:$src)>;
5367 (bc_v2i64 (v4i1sextv4i32)),
5368 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5369 (PABSDrr128 VR128:$src)>;
5372 //===---------------------------------------------------------------------===//
5373 // SSSE3 - Packed Binary Operator Instructions
5374 //===---------------------------------------------------------------------===//
5376 let Sched = WriteVecALU in {
5377 def SSE_PHADDSUBD : OpndItins<
5378 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5380 def SSE_PHADDSUBSW : OpndItins<
5381 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5383 def SSE_PHADDSUBW : OpndItins<
5384 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5387 let Sched = WriteShuffle in
5388 def SSE_PSHUFB : OpndItins<
5389 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5391 let Sched = WriteVecALU in
5392 def SSE_PSIGN : OpndItins<
5393 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5395 let Sched = WriteVecIMul in
5396 def SSE_PMULHRSW : OpndItins<
5397 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5400 /// SS3I_binop_rm - Simple SSSE3 bin op
5401 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5402 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5403 X86MemOperand x86memop, OpndItins itins,
5405 let isCommutable = 1 in
5406 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5407 (ins RC:$src1, RC:$src2),
5409 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5410 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5411 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5412 OpSize, Sched<[itins.Sched]>;
5413 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5414 (ins RC:$src1, x86memop:$src2),
5416 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5417 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5419 (OpVT (OpNode RC:$src1,
5420 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize,
5421 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5424 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5425 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5426 Intrinsic IntId128, OpndItins itins,
5428 let isCommutable = 1 in
5429 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5430 (ins VR128:$src1, VR128:$src2),
5432 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5433 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5434 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5435 OpSize, Sched<[itins.Sched]>;
5436 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5437 (ins VR128:$src1, i128mem:$src2),
5439 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5440 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5442 (IntId128 VR128:$src1,
5443 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize,
5444 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5447 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5448 Intrinsic IntId256> {
5449 let isCommutable = 1 in
5450 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5451 (ins VR256:$src1, VR256:$src2),
5452 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5453 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5455 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5456 (ins VR256:$src1, i256mem:$src2),
5457 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5459 (IntId256 VR256:$src1,
5460 (bitconvert (loadv4i64 addr:$src2))))]>, OpSize;
5463 let ImmT = NoImm, Predicates = [HasAVX] in {
5464 let isCommutable = 0 in {
5465 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5467 SSE_PHADDSUBW, 0>, VEX_4V;
5468 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5470 SSE_PHADDSUBD, 0>, VEX_4V;
5471 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5473 SSE_PHADDSUBW, 0>, VEX_4V;
5474 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5476 SSE_PHADDSUBD, 0>, VEX_4V;
5477 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5479 SSE_PSIGN, 0>, VEX_4V;
5480 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5482 SSE_PSIGN, 0>, VEX_4V;
5483 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5485 SSE_PSIGN, 0>, VEX_4V;
5486 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5488 SSE_PSHUFB, 0>, VEX_4V;
5489 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5490 int_x86_ssse3_phadd_sw_128,
5491 SSE_PHADDSUBSW, 0>, VEX_4V;
5492 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5493 int_x86_ssse3_phsub_sw_128,
5494 SSE_PHADDSUBSW, 0>, VEX_4V;
5495 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5496 int_x86_ssse3_pmadd_ub_sw_128,
5497 SSE_PMADD, 0>, VEX_4V;
5499 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5500 int_x86_ssse3_pmul_hr_sw_128,
5501 SSE_PMULHRSW, 0>, VEX_4V;
5504 let ImmT = NoImm, Predicates = [HasAVX2] in {
5505 let isCommutable = 0 in {
5506 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5508 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5509 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5511 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5512 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5514 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5515 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5517 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5518 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5520 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5521 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5523 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5524 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5526 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5527 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5529 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5530 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5531 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5532 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5533 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5534 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5535 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5537 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5538 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5541 // None of these have i8 immediate fields.
5542 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5543 let isCommutable = 0 in {
5544 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5545 memopv2i64, i128mem, SSE_PHADDSUBW>;
5546 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5547 memopv2i64, i128mem, SSE_PHADDSUBD>;
5548 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5549 memopv2i64, i128mem, SSE_PHADDSUBW>;
5550 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5551 memopv2i64, i128mem, SSE_PHADDSUBD>;
5552 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5553 memopv2i64, i128mem, SSE_PSIGN>;
5554 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5555 memopv2i64, i128mem, SSE_PSIGN>;
5556 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5557 memopv2i64, i128mem, SSE_PSIGN>;
5558 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5559 memopv2i64, i128mem, SSE_PSHUFB>;
5560 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5561 int_x86_ssse3_phadd_sw_128,
5563 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5564 int_x86_ssse3_phsub_sw_128,
5566 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5567 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5569 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5570 int_x86_ssse3_pmul_hr_sw_128,
5574 //===---------------------------------------------------------------------===//
5575 // SSSE3 - Packed Align Instruction Patterns
5576 //===---------------------------------------------------------------------===//
5578 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5579 let neverHasSideEffects = 1 in {
5580 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5581 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5583 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5585 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5586 [], IIC_SSE_PALIGNRR>, OpSize, Sched<[WriteShuffle]>;
5588 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5589 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5591 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5593 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5594 [], IIC_SSE_PALIGNRM>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5598 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5599 let neverHasSideEffects = 1 in {
5600 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5601 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5603 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5604 []>, OpSize, Sched<[WriteShuffle]>;
5606 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5607 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5609 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5610 []>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5614 let Predicates = [HasAVX] in
5615 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5616 let Predicates = [HasAVX2] in
5617 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5618 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5619 defm PALIGN : ssse3_palignr<"palignr">;
5621 let Predicates = [HasAVX2] in {
5622 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5623 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5624 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5625 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5626 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5627 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5628 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5629 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5632 let Predicates = [HasAVX] in {
5633 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5634 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5635 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5636 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5637 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5638 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5639 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5640 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5643 let Predicates = [UseSSSE3] in {
5644 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5645 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5646 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5647 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5648 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5649 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5650 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5651 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5654 //===---------------------------------------------------------------------===//
5655 // SSSE3 - Thread synchronization
5656 //===---------------------------------------------------------------------===//
5658 let SchedRW = [WriteSystem] in {
5659 let usesCustomInserter = 1 in {
5660 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5661 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5662 Requires<[HasSSE3]>;
5665 let Uses = [EAX, ECX, EDX] in
5666 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5667 TB, Requires<[HasSSE3]>;
5668 let Uses = [ECX, EAX] in
5669 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5670 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5671 TB, Requires<[HasSSE3]>;
5674 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5675 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5677 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5678 Requires<[Not64BitMode]>;
5679 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5680 Requires<[In64BitMode]>;
5682 //===----------------------------------------------------------------------===//
5683 // SSE4.1 - Packed Move with Sign/Zero Extend
5684 //===----------------------------------------------------------------------===//
5686 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5687 OpndItins itins = DEFAULT_ITINS> {
5688 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5689 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5690 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>, OpSize;
5692 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5693 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5695 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))],
5699 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5701 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5702 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5703 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5705 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5706 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5707 [(set VR256:$dst, (IntId (load addr:$src)))]>,
5711 let Predicates = [HasAVX] in {
5712 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw",
5713 int_x86_sse41_pmovsxbw>, VEX;
5714 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd",
5715 int_x86_sse41_pmovsxwd>, VEX;
5716 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq",
5717 int_x86_sse41_pmovsxdq>, VEX;
5718 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw",
5719 int_x86_sse41_pmovzxbw>, VEX;
5720 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd",
5721 int_x86_sse41_pmovzxwd>, VEX;
5722 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq",
5723 int_x86_sse41_pmovzxdq>, VEX;
5726 let Predicates = [HasAVX2] in {
5727 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5728 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5729 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5730 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5731 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5732 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5733 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5734 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5735 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5736 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5737 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5738 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5741 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw, SSE_INTALU_ITINS_P>;
5742 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd, SSE_INTALU_ITINS_P>;
5743 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq, SSE_INTALU_ITINS_P>;
5744 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw, SSE_INTALU_ITINS_P>;
5745 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd, SSE_INTALU_ITINS_P>;
5746 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq, SSE_INTALU_ITINS_P>;
5748 let Predicates = [HasAVX] in {
5749 // Common patterns involving scalar load.
5750 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5751 (VPMOVSXBWrm addr:$src)>;
5752 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5753 (VPMOVSXBWrm addr:$src)>;
5754 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5755 (VPMOVSXBWrm addr:$src)>;
5757 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5758 (VPMOVSXWDrm addr:$src)>;
5759 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5760 (VPMOVSXWDrm addr:$src)>;
5761 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5762 (VPMOVSXWDrm addr:$src)>;
5764 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5765 (VPMOVSXDQrm addr:$src)>;
5766 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5767 (VPMOVSXDQrm addr:$src)>;
5768 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5769 (VPMOVSXDQrm addr:$src)>;
5771 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5772 (VPMOVZXBWrm addr:$src)>;
5773 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5774 (VPMOVZXBWrm addr:$src)>;
5775 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5776 (VPMOVZXBWrm addr:$src)>;
5778 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5779 (VPMOVZXWDrm addr:$src)>;
5780 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5781 (VPMOVZXWDrm addr:$src)>;
5782 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5783 (VPMOVZXWDrm addr:$src)>;
5785 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5786 (VPMOVZXDQrm addr:$src)>;
5787 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5788 (VPMOVZXDQrm addr:$src)>;
5789 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5790 (VPMOVZXDQrm addr:$src)>;
5793 let Predicates = [UseSSE41] in {
5794 // Common patterns involving scalar load.
5795 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5796 (PMOVSXBWrm addr:$src)>;
5797 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5798 (PMOVSXBWrm addr:$src)>;
5799 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5800 (PMOVSXBWrm addr:$src)>;
5802 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5803 (PMOVSXWDrm addr:$src)>;
5804 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5805 (PMOVSXWDrm addr:$src)>;
5806 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5807 (PMOVSXWDrm addr:$src)>;
5809 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5810 (PMOVSXDQrm addr:$src)>;
5811 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5812 (PMOVSXDQrm addr:$src)>;
5813 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5814 (PMOVSXDQrm addr:$src)>;
5816 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5817 (PMOVZXBWrm addr:$src)>;
5818 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5819 (PMOVZXBWrm addr:$src)>;
5820 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5821 (PMOVZXBWrm addr:$src)>;
5823 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5824 (PMOVZXWDrm addr:$src)>;
5825 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5826 (PMOVZXWDrm addr:$src)>;
5827 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5828 (PMOVZXWDrm addr:$src)>;
5830 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5831 (PMOVZXDQrm addr:$src)>;
5832 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5833 (PMOVZXDQrm addr:$src)>;
5834 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5835 (PMOVZXDQrm addr:$src)>;
5838 let Predicates = [HasAVX2] in {
5839 let AddedComplexity = 15 in {
5840 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5841 (VPMOVZXDQYrr VR128:$src)>;
5842 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5843 (VPMOVZXWDYrr VR128:$src)>;
5844 def : Pat<(v16i16 (X86vzmovly (v16i8 VR128:$src))),
5845 (VPMOVZXBWYrr VR128:$src)>;
5848 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5849 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5850 def : Pat<(v16i16 (X86vsmovl (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
5853 let Predicates = [HasAVX] in {
5854 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5855 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5856 def : Pat<(v8i16 (X86vsmovl (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
5859 let Predicates = [UseSSE41] in {
5860 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5861 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5862 def : Pat<(v8i16 (X86vsmovl (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
5866 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5867 OpndItins itins = DEFAULT_ITINS> {
5868 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5869 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5870 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>, OpSize;
5872 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5873 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5875 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))],
5880 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5882 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5883 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5884 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5886 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5887 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5889 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5893 let Predicates = [HasAVX] in {
5894 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5896 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5898 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5900 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5904 let Predicates = [HasAVX2] in {
5905 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5906 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5907 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5908 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5909 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5910 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5911 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5912 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5915 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd,
5916 SSE_INTALU_ITINS_P>;
5917 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq,
5918 SSE_INTALU_ITINS_P>;
5919 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd,
5920 SSE_INTALU_ITINS_P>;
5921 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq,
5922 SSE_INTALU_ITINS_P>;
5924 let Predicates = [HasAVX] in {
5925 // Common patterns involving scalar load
5926 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5927 (VPMOVSXBDrm addr:$src)>;
5928 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5929 (VPMOVSXWQrm addr:$src)>;
5931 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5932 (VPMOVZXBDrm addr:$src)>;
5933 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5934 (VPMOVZXWQrm addr:$src)>;
5937 let Predicates = [UseSSE41] in {
5938 // Common patterns involving scalar load
5939 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5940 (PMOVSXBDrm addr:$src)>;
5941 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5942 (PMOVSXWQrm addr:$src)>;
5944 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5945 (PMOVZXBDrm addr:$src)>;
5946 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5947 (PMOVZXWQrm addr:$src)>;
5950 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5951 OpndItins itins = DEFAULT_ITINS> {
5952 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5953 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5954 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5956 // Expecting a i16 load any extended to i32 value.
5957 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5958 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5959 [(set VR128:$dst, (IntId (bitconvert
5960 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5964 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5966 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5967 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5968 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5970 // Expecting a i16 load any extended to i32 value.
5971 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5972 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5973 [(set VR256:$dst, (IntId (bitconvert
5974 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5978 let Predicates = [HasAVX] in {
5979 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5981 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5984 let Predicates = [HasAVX2] in {
5985 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5986 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5987 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5988 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5990 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq,
5991 SSE_INTALU_ITINS_P>;
5992 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq,
5993 SSE_INTALU_ITINS_P>;
5995 let Predicates = [HasAVX2] in {
5996 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
5997 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
5998 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
6000 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
6001 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
6003 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
6005 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
6006 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6007 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
6008 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6009 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
6010 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6012 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
6013 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6014 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
6015 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6017 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
6018 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6020 def : Pat<(v8i32 (X86vsmovl (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
6021 (VPMOVSXWDYrm addr:$src)>;
6022 def : Pat<(v4i64 (X86vsmovl (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
6023 (VPMOVSXDQYrm addr:$src)>;
6025 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
6026 (scalar_to_vector (loadi64 addr:$src))))))),
6027 (VPMOVSXBDYrm addr:$src)>;
6028 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
6029 (scalar_to_vector (loadf64 addr:$src))))))),
6030 (VPMOVSXBDYrm addr:$src)>;
6032 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
6033 (scalar_to_vector (loadi64 addr:$src))))))),
6034 (VPMOVSXWQYrm addr:$src)>;
6035 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
6036 (scalar_to_vector (loadf64 addr:$src))))))),
6037 (VPMOVSXWQYrm addr:$src)>;
6039 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
6040 (scalar_to_vector (loadi32 addr:$src))))))),
6041 (VPMOVSXBQYrm addr:$src)>;
6044 let Predicates = [HasAVX] in {
6045 // Common patterns involving scalar load
6046 def : Pat<(int_x86_sse41_pmovsxbq
6047 (bitconvert (v4i32 (X86vzmovl
6048 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6049 (VPMOVSXBQrm addr:$src)>;
6051 def : Pat<(int_x86_sse41_pmovzxbq
6052 (bitconvert (v4i32 (X86vzmovl
6053 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6054 (VPMOVZXBQrm addr:$src)>;
6057 let Predicates = [UseSSE41] in {
6058 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
6059 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
6060 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
6062 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
6063 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
6065 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
6067 // Common patterns involving scalar load
6068 def : Pat<(int_x86_sse41_pmovsxbq
6069 (bitconvert (v4i32 (X86vzmovl
6070 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6071 (PMOVSXBQrm addr:$src)>;
6073 def : Pat<(int_x86_sse41_pmovzxbq
6074 (bitconvert (v4i32 (X86vzmovl
6075 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6076 (PMOVZXBQrm addr:$src)>;
6078 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6079 (scalar_to_vector (loadi64 addr:$src))))))),
6080 (PMOVSXWDrm addr:$src)>;
6081 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6082 (scalar_to_vector (loadf64 addr:$src))))))),
6083 (PMOVSXWDrm addr:$src)>;
6084 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6085 (scalar_to_vector (loadi32 addr:$src))))))),
6086 (PMOVSXBDrm addr:$src)>;
6087 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6088 (scalar_to_vector (loadi32 addr:$src))))))),
6089 (PMOVSXWQrm addr:$src)>;
6090 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6091 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6092 (PMOVSXBQrm addr:$src)>;
6093 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6094 (scalar_to_vector (loadi64 addr:$src))))))),
6095 (PMOVSXDQrm addr:$src)>;
6096 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6097 (scalar_to_vector (loadf64 addr:$src))))))),
6098 (PMOVSXDQrm addr:$src)>;
6099 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6100 (scalar_to_vector (loadi64 addr:$src))))))),
6101 (PMOVSXBWrm addr:$src)>;
6102 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6103 (scalar_to_vector (loadf64 addr:$src))))))),
6104 (PMOVSXBWrm addr:$src)>;
6107 let Predicates = [HasAVX2] in {
6108 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
6109 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
6110 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
6112 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
6113 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
6115 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
6117 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
6118 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6119 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
6120 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6121 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
6122 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6124 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
6125 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6126 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
6127 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6129 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
6130 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6133 let Predicates = [HasAVX] in {
6134 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
6135 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
6136 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
6138 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
6139 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
6141 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
6143 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6144 (VPMOVZXBWrm addr:$src)>;
6145 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6146 (VPMOVZXBWrm addr:$src)>;
6147 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6148 (VPMOVZXBDrm addr:$src)>;
6149 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6150 (VPMOVZXBQrm addr:$src)>;
6152 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6153 (VPMOVZXWDrm addr:$src)>;
6154 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6155 (VPMOVZXWDrm addr:$src)>;
6156 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6157 (VPMOVZXWQrm addr:$src)>;
6159 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6160 (VPMOVZXDQrm addr:$src)>;
6161 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6162 (VPMOVZXDQrm addr:$src)>;
6163 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6164 (VPMOVZXDQrm addr:$src)>;
6166 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
6167 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
6168 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
6170 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
6171 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
6173 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
6175 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6176 (scalar_to_vector (loadi64 addr:$src))))))),
6177 (VPMOVSXWDrm addr:$src)>;
6178 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6179 (scalar_to_vector (loadi64 addr:$src))))))),
6180 (VPMOVSXDQrm addr:$src)>;
6181 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6182 (scalar_to_vector (loadf64 addr:$src))))))),
6183 (VPMOVSXWDrm addr:$src)>;
6184 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6185 (scalar_to_vector (loadf64 addr:$src))))))),
6186 (VPMOVSXDQrm addr:$src)>;
6187 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6188 (scalar_to_vector (loadi64 addr:$src))))))),
6189 (VPMOVSXBWrm addr:$src)>;
6190 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6191 (scalar_to_vector (loadf64 addr:$src))))))),
6192 (VPMOVSXBWrm addr:$src)>;
6194 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6195 (scalar_to_vector (loadi32 addr:$src))))))),
6196 (VPMOVSXBDrm addr:$src)>;
6197 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6198 (scalar_to_vector (loadi32 addr:$src))))))),
6199 (VPMOVSXWQrm addr:$src)>;
6200 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6201 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6202 (VPMOVSXBQrm addr:$src)>;
6205 let Predicates = [UseSSE41] in {
6206 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
6207 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
6208 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
6210 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
6211 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
6213 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
6215 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6216 (PMOVZXBWrm addr:$src)>;
6217 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6218 (PMOVZXBWrm addr:$src)>;
6219 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6220 (PMOVZXBDrm addr:$src)>;
6221 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6222 (PMOVZXBQrm addr:$src)>;
6224 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6225 (PMOVZXWDrm addr:$src)>;
6226 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6227 (PMOVZXWDrm addr:$src)>;
6228 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6229 (PMOVZXWQrm addr:$src)>;
6231 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6232 (PMOVZXDQrm addr:$src)>;
6233 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6234 (PMOVZXDQrm addr:$src)>;
6235 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6236 (PMOVZXDQrm addr:$src)>;
6239 //===----------------------------------------------------------------------===//
6240 // SSE4.1 - Extract Instructions
6241 //===----------------------------------------------------------------------===//
6243 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6244 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6245 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6246 (ins VR128:$src1, i32i8imm:$src2),
6247 !strconcat(OpcodeStr,
6248 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6249 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6252 let neverHasSideEffects = 1, mayStore = 1 in
6253 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6254 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6255 !strconcat(OpcodeStr,
6256 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6259 // There's an AssertZext in the way of writing the store pattern
6260 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6263 let Predicates = [HasAVX] in
6264 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6266 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6269 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6270 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6271 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6272 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6273 (ins VR128:$src1, i32i8imm:$src2),
6274 !strconcat(OpcodeStr,
6275 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6278 let neverHasSideEffects = 1, mayStore = 1 in
6279 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6280 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6281 !strconcat(OpcodeStr,
6282 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6285 // There's an AssertZext in the way of writing the store pattern
6286 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6289 let Predicates = [HasAVX] in
6290 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6292 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6295 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6296 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6297 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6298 (ins VR128:$src1, i32i8imm:$src2),
6299 !strconcat(OpcodeStr,
6300 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6302 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
6303 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6304 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6305 !strconcat(OpcodeStr,
6306 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6307 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6308 addr:$dst)]>, OpSize;
6311 let Predicates = [HasAVX] in
6312 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6314 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6316 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6317 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6318 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6319 (ins VR128:$src1, i32i8imm:$src2),
6320 !strconcat(OpcodeStr,
6321 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6323 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
6324 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6325 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6326 !strconcat(OpcodeStr,
6327 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6328 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6329 addr:$dst)]>, OpSize, REX_W;
6332 let Predicates = [HasAVX] in
6333 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6335 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6337 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6339 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6340 OpndItins itins = DEFAULT_ITINS> {
6341 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6342 (ins VR128:$src1, i32i8imm:$src2),
6343 !strconcat(OpcodeStr,
6344 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6345 [(set GR32orGR64:$dst,
6346 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6349 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6350 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6351 !strconcat(OpcodeStr,
6352 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6353 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6354 addr:$dst)], itins.rm>, OpSize;
6357 let ExeDomain = SSEPackedSingle in {
6358 let Predicates = [UseAVX] in
6359 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6360 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6363 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6364 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6367 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6369 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6372 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6373 Requires<[UseSSE41]>;
6375 //===----------------------------------------------------------------------===//
6376 // SSE4.1 - Insert Instructions
6377 //===----------------------------------------------------------------------===//
6379 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6380 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6381 (ins VR128:$src1, GR32orGR64:$src2, i32i8imm:$src3),
6383 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6385 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6387 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>, OpSize;
6388 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6389 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6391 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6393 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6395 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6396 imm:$src3))]>, OpSize;
6399 let Predicates = [HasAVX] in
6400 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6401 let Constraints = "$src1 = $dst" in
6402 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6404 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6405 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6406 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6408 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6410 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6412 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6414 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6415 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6417 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6419 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6421 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6422 imm:$src3)))]>, OpSize;
6425 let Predicates = [HasAVX] in
6426 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6427 let Constraints = "$src1 = $dst" in
6428 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6430 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6431 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6432 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6434 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6436 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6438 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6440 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6441 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6443 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6445 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6447 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6448 imm:$src3)))]>, OpSize;
6451 let Predicates = [HasAVX] in
6452 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6453 let Constraints = "$src1 = $dst" in
6454 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6456 // insertps has a few different modes, there's the first two here below which
6457 // are optimized inserts that won't zero arbitrary elements in the destination
6458 // vector. The next one matches the intrinsic and could zero arbitrary elements
6459 // in the target vector.
6460 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6461 OpndItins itins = DEFAULT_ITINS> {
6462 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6463 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6465 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6467 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6469 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6471 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6472 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6474 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6476 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6478 (X86insrtps VR128:$src1,
6479 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6480 imm:$src3))], itins.rm>, OpSize;
6483 let ExeDomain = SSEPackedSingle in {
6484 let Predicates = [UseAVX] in
6485 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6486 let Constraints = "$src1 = $dst" in
6487 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6490 //===----------------------------------------------------------------------===//
6491 // SSE4.1 - Round Instructions
6492 //===----------------------------------------------------------------------===//
6494 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6495 X86MemOperand x86memop, RegisterClass RC,
6496 PatFrag mem_frag32, PatFrag mem_frag64,
6497 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6498 let ExeDomain = SSEPackedSingle in {
6499 // Intrinsic operation, reg.
6500 // Vector intrinsic operation, reg
6501 def PSr : SS4AIi8<opcps, MRMSrcReg,
6502 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6503 !strconcat(OpcodeStr,
6504 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6505 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6506 IIC_SSE_ROUNDPS_REG>,
6509 // Vector intrinsic operation, mem
6510 def PSm : SS4AIi8<opcps, MRMSrcMem,
6511 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6512 !strconcat(OpcodeStr,
6513 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6515 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6516 IIC_SSE_ROUNDPS_MEM>,
6518 } // ExeDomain = SSEPackedSingle
6520 let ExeDomain = SSEPackedDouble in {
6521 // Vector intrinsic operation, reg
6522 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6523 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6524 !strconcat(OpcodeStr,
6525 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6526 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6527 IIC_SSE_ROUNDPS_REG>,
6530 // Vector intrinsic operation, mem
6531 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6532 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6533 !strconcat(OpcodeStr,
6534 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6536 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6537 IIC_SSE_ROUNDPS_REG>,
6539 } // ExeDomain = SSEPackedDouble
6542 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6545 Intrinsic F64Int, bit Is2Addr = 1> {
6546 let ExeDomain = GenericDomain in {
6548 let hasSideEffects = 0 in
6549 def SSr : SS4AIi8<opcss, MRMSrcReg,
6550 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6552 !strconcat(OpcodeStr,
6553 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6554 !strconcat(OpcodeStr,
6555 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6558 // Intrinsic operation, reg.
6559 let isCodeGenOnly = 1 in
6560 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6561 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6563 !strconcat(OpcodeStr,
6564 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6565 !strconcat(OpcodeStr,
6566 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6567 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6570 // Intrinsic operation, mem.
6571 def SSm : SS4AIi8<opcss, MRMSrcMem,
6572 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6574 !strconcat(OpcodeStr,
6575 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6576 !strconcat(OpcodeStr,
6577 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6579 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6583 let hasSideEffects = 0 in
6584 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6585 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6587 !strconcat(OpcodeStr,
6588 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6589 !strconcat(OpcodeStr,
6590 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6593 // Intrinsic operation, reg.
6594 let isCodeGenOnly = 1 in
6595 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6596 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6598 !strconcat(OpcodeStr,
6599 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6600 !strconcat(OpcodeStr,
6601 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6602 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6605 // Intrinsic operation, mem.
6606 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6607 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6609 !strconcat(OpcodeStr,
6610 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6611 !strconcat(OpcodeStr,
6612 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6614 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6616 } // ExeDomain = GenericDomain
6619 // FP round - roundss, roundps, roundsd, roundpd
6620 let Predicates = [HasAVX] in {
6622 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6623 loadv4f32, loadv2f64,
6624 int_x86_sse41_round_ps,
6625 int_x86_sse41_round_pd>, VEX;
6626 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6627 loadv8f32, loadv4f64,
6628 int_x86_avx_round_ps_256,
6629 int_x86_avx_round_pd_256>, VEX, VEX_L;
6630 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6631 int_x86_sse41_round_ss,
6632 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6634 def : Pat<(ffloor FR32:$src),
6635 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6636 def : Pat<(f64 (ffloor FR64:$src)),
6637 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6638 def : Pat<(f32 (fnearbyint FR32:$src)),
6639 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6640 def : Pat<(f64 (fnearbyint FR64:$src)),
6641 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6642 def : Pat<(f32 (fceil FR32:$src)),
6643 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6644 def : Pat<(f64 (fceil FR64:$src)),
6645 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6646 def : Pat<(f32 (frint FR32:$src)),
6647 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6648 def : Pat<(f64 (frint FR64:$src)),
6649 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6650 def : Pat<(f32 (ftrunc FR32:$src)),
6651 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6652 def : Pat<(f64 (ftrunc FR64:$src)),
6653 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6655 def : Pat<(v4f32 (ffloor VR128:$src)),
6656 (VROUNDPSr VR128:$src, (i32 0x1))>;
6657 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6658 (VROUNDPSr VR128:$src, (i32 0xC))>;
6659 def : Pat<(v4f32 (fceil VR128:$src)),
6660 (VROUNDPSr VR128:$src, (i32 0x2))>;
6661 def : Pat<(v4f32 (frint VR128:$src)),
6662 (VROUNDPSr VR128:$src, (i32 0x4))>;
6663 def : Pat<(v4f32 (ftrunc VR128:$src)),
6664 (VROUNDPSr VR128:$src, (i32 0x3))>;
6666 def : Pat<(v2f64 (ffloor VR128:$src)),
6667 (VROUNDPDr VR128:$src, (i32 0x1))>;
6668 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6669 (VROUNDPDr VR128:$src, (i32 0xC))>;
6670 def : Pat<(v2f64 (fceil VR128:$src)),
6671 (VROUNDPDr VR128:$src, (i32 0x2))>;
6672 def : Pat<(v2f64 (frint VR128:$src)),
6673 (VROUNDPDr VR128:$src, (i32 0x4))>;
6674 def : Pat<(v2f64 (ftrunc VR128:$src)),
6675 (VROUNDPDr VR128:$src, (i32 0x3))>;
6677 def : Pat<(v8f32 (ffloor VR256:$src)),
6678 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6679 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6680 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6681 def : Pat<(v8f32 (fceil VR256:$src)),
6682 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6683 def : Pat<(v8f32 (frint VR256:$src)),
6684 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6685 def : Pat<(v8f32 (ftrunc VR256:$src)),
6686 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6688 def : Pat<(v4f64 (ffloor VR256:$src)),
6689 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6690 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6691 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6692 def : Pat<(v4f64 (fceil VR256:$src)),
6693 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6694 def : Pat<(v4f64 (frint VR256:$src)),
6695 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6696 def : Pat<(v4f64 (ftrunc VR256:$src)),
6697 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6700 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6701 memopv4f32, memopv2f64,
6702 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6703 let Constraints = "$src1 = $dst" in
6704 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6705 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6707 let Predicates = [UseSSE41] in {
6708 def : Pat<(ffloor FR32:$src),
6709 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6710 def : Pat<(f64 (ffloor FR64:$src)),
6711 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6712 def : Pat<(f32 (fnearbyint FR32:$src)),
6713 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6714 def : Pat<(f64 (fnearbyint FR64:$src)),
6715 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6716 def : Pat<(f32 (fceil FR32:$src)),
6717 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6718 def : Pat<(f64 (fceil FR64:$src)),
6719 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6720 def : Pat<(f32 (frint FR32:$src)),
6721 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6722 def : Pat<(f64 (frint FR64:$src)),
6723 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6724 def : Pat<(f32 (ftrunc FR32:$src)),
6725 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6726 def : Pat<(f64 (ftrunc FR64:$src)),
6727 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6729 def : Pat<(v4f32 (ffloor VR128:$src)),
6730 (ROUNDPSr VR128:$src, (i32 0x1))>;
6731 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6732 (ROUNDPSr VR128:$src, (i32 0xC))>;
6733 def : Pat<(v4f32 (fceil VR128:$src)),
6734 (ROUNDPSr VR128:$src, (i32 0x2))>;
6735 def : Pat<(v4f32 (frint VR128:$src)),
6736 (ROUNDPSr VR128:$src, (i32 0x4))>;
6737 def : Pat<(v4f32 (ftrunc VR128:$src)),
6738 (ROUNDPSr VR128:$src, (i32 0x3))>;
6740 def : Pat<(v2f64 (ffloor VR128:$src)),
6741 (ROUNDPDr VR128:$src, (i32 0x1))>;
6742 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6743 (ROUNDPDr VR128:$src, (i32 0xC))>;
6744 def : Pat<(v2f64 (fceil VR128:$src)),
6745 (ROUNDPDr VR128:$src, (i32 0x2))>;
6746 def : Pat<(v2f64 (frint VR128:$src)),
6747 (ROUNDPDr VR128:$src, (i32 0x4))>;
6748 def : Pat<(v2f64 (ftrunc VR128:$src)),
6749 (ROUNDPDr VR128:$src, (i32 0x3))>;
6752 //===----------------------------------------------------------------------===//
6753 // SSE4.1 - Packed Bit Test
6754 //===----------------------------------------------------------------------===//
6756 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6757 // the intel intrinsic that corresponds to this.
6758 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6759 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6760 "vptest\t{$src2, $src1|$src1, $src2}",
6761 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6763 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6764 "vptest\t{$src2, $src1|$src1, $src2}",
6765 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6768 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6769 "vptest\t{$src2, $src1|$src1, $src2}",
6770 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6772 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6773 "vptest\t{$src2, $src1|$src1, $src2}",
6774 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6778 let Defs = [EFLAGS] in {
6779 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6780 "ptest\t{$src2, $src1|$src1, $src2}",
6781 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6783 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6784 "ptest\t{$src2, $src1|$src1, $src2}",
6785 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6789 // The bit test instructions below are AVX only
6790 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6791 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6792 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6793 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6794 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6795 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6796 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6797 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6801 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6802 let ExeDomain = SSEPackedSingle in {
6803 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6804 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6807 let ExeDomain = SSEPackedDouble in {
6808 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6809 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6814 //===----------------------------------------------------------------------===//
6815 // SSE4.1 - Misc Instructions
6816 //===----------------------------------------------------------------------===//
6818 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6819 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6820 "popcnt{w}\t{$src, $dst|$dst, $src}",
6821 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6824 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6825 "popcnt{w}\t{$src, $dst|$dst, $src}",
6826 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6827 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, OpSize, XS;
6829 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6830 "popcnt{l}\t{$src, $dst|$dst, $src}",
6831 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6834 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6835 "popcnt{l}\t{$src, $dst|$dst, $src}",
6836 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6837 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, XS;
6839 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6840 "popcnt{q}\t{$src, $dst|$dst, $src}",
6841 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6844 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6845 "popcnt{q}\t{$src, $dst|$dst, $src}",
6846 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6847 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>, XS;
6852 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6853 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6854 Intrinsic IntId128> {
6855 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6857 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6858 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6859 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6861 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6864 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6867 let Predicates = [HasAVX] in
6868 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6869 int_x86_sse41_phminposuw>, VEX;
6870 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6871 int_x86_sse41_phminposuw>;
6873 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6874 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6875 Intrinsic IntId128, bit Is2Addr = 1,
6876 OpndItins itins = DEFAULT_ITINS> {
6877 let isCommutable = 1 in
6878 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6879 (ins VR128:$src1, VR128:$src2),
6881 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6882 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6883 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
6885 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6886 (ins VR128:$src1, i128mem:$src2),
6888 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6889 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6891 (IntId128 VR128:$src1,
6892 (bitconvert (memopv2i64 addr:$src2))))],
6896 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6897 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6898 Intrinsic IntId256> {
6899 let isCommutable = 1 in
6900 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6901 (ins VR256:$src1, VR256:$src2),
6902 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6903 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6904 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6905 (ins VR256:$src1, i256mem:$src2),
6906 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6908 (IntId256 VR256:$src1,
6909 (bitconvert (loadv4i64 addr:$src2))))]>, OpSize;
6913 /// SS48I_binop_rm - Simple SSE41 binary operator.
6914 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6915 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6916 X86MemOperand x86memop, bit Is2Addr = 1,
6917 OpndItins itins = DEFAULT_ITINS> {
6918 let isCommutable = 1 in
6919 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6920 (ins RC:$src1, RC:$src2),
6922 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6923 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6924 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6925 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6926 (ins RC:$src1, x86memop:$src2),
6928 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6929 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6931 (OpVT (OpNode RC:$src1,
6932 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6935 let Predicates = [HasAVX] in {
6936 let isCommutable = 0 in
6937 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6939 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6940 loadv2i64, i128mem, 0>, VEX_4V;
6941 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6942 loadv2i64, i128mem, 0>, VEX_4V;
6943 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6944 loadv2i64, i128mem, 0>, VEX_4V;
6945 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6946 loadv2i64, i128mem, 0>, VEX_4V;
6947 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6948 loadv2i64, i128mem, 0>, VEX_4V;
6949 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6950 loadv2i64, i128mem, 0>, VEX_4V;
6951 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6952 loadv2i64, i128mem, 0>, VEX_4V;
6953 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6954 loadv2i64, i128mem, 0>, VEX_4V;
6955 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6959 let Predicates = [HasAVX2] in {
6960 let isCommutable = 0 in
6961 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6962 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6963 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6964 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6965 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6966 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6967 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6968 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6969 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6970 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6971 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6972 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6973 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6974 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6975 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6976 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6977 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6978 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
6979 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6980 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6983 let Constraints = "$src1 = $dst" in {
6984 let isCommutable = 0 in
6985 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6986 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6987 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6988 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6989 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6990 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6991 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6992 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6993 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6994 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6995 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6996 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6997 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6998 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6999 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7000 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
7001 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7002 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq,
7003 1, SSE_INTMUL_ITINS_P>;
7006 let Predicates = [HasAVX] in {
7007 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
7008 memopv2i64, i128mem, 0>, VEX_4V;
7009 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
7010 memopv2i64, i128mem, 0>, VEX_4V;
7012 let Predicates = [HasAVX2] in {
7013 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
7014 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
7015 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
7016 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
7019 let Constraints = "$src1 = $dst" in {
7020 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
7021 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
7022 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
7023 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
7026 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
7027 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
7028 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7029 X86MemOperand x86memop, bit Is2Addr = 1,
7030 OpndItins itins = DEFAULT_ITINS> {
7031 let isCommutable = 1 in
7032 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
7033 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7035 !strconcat(OpcodeStr,
7036 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7037 !strconcat(OpcodeStr,
7038 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7039 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
7041 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
7042 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7044 !strconcat(OpcodeStr,
7045 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7046 !strconcat(OpcodeStr,
7047 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7050 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
7054 let Predicates = [HasAVX] in {
7055 let isCommutable = 0 in {
7056 let ExeDomain = SSEPackedSingle in {
7057 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
7058 VR128, loadv4f32, f128mem, 0>, VEX_4V;
7059 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
7060 int_x86_avx_blend_ps_256, VR256, loadv8f32,
7061 f256mem, 0>, VEX_4V, VEX_L;
7063 let ExeDomain = SSEPackedDouble in {
7064 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
7065 VR128, loadv2f64, f128mem, 0>, VEX_4V;
7066 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
7067 int_x86_avx_blend_pd_256,VR256, loadv4f64,
7068 f256mem, 0>, VEX_4V, VEX_L;
7070 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
7071 VR128, loadv2i64, i128mem, 0>, VEX_4V;
7072 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7073 VR128, loadv2i64, i128mem, 0>, VEX_4V;
7075 let ExeDomain = SSEPackedSingle in
7076 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7077 VR128, loadv4f32, f128mem, 0>, VEX_4V;
7078 let ExeDomain = SSEPackedDouble in
7079 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7080 VR128, loadv2f64, f128mem, 0>, VEX_4V;
7081 let ExeDomain = SSEPackedSingle in
7082 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7083 VR256, loadv8f32, i256mem, 0>, VEX_4V, VEX_L;
7086 let Predicates = [HasAVX2] in {
7087 let isCommutable = 0 in {
7088 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
7089 VR256, loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7090 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7091 VR256, loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7095 let Constraints = "$src1 = $dst" in {
7096 let isCommutable = 0 in {
7097 let ExeDomain = SSEPackedSingle in
7098 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
7099 VR128, memopv4f32, f128mem,
7100 1, SSE_INTALU_ITINS_P>;
7101 let ExeDomain = SSEPackedDouble in
7102 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
7103 VR128, memopv2f64, f128mem,
7104 1, SSE_INTALU_ITINS_P>;
7105 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
7106 VR128, memopv2i64, i128mem,
7107 1, SSE_INTALU_ITINS_P>;
7108 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7109 VR128, memopv2i64, i128mem,
7110 1, SSE_INTMUL_ITINS_P>;
7112 let ExeDomain = SSEPackedSingle in
7113 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7114 VR128, memopv4f32, f128mem, 1,
7116 let ExeDomain = SSEPackedDouble in
7117 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7118 VR128, memopv2f64, f128mem, 1,
7122 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7123 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7124 RegisterClass RC, X86MemOperand x86memop,
7125 PatFrag mem_frag, Intrinsic IntId> {
7126 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7127 (ins RC:$src1, RC:$src2, RC:$src3),
7128 !strconcat(OpcodeStr,
7129 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7130 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7131 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
7133 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7134 (ins RC:$src1, x86memop:$src2, RC:$src3),
7135 !strconcat(OpcodeStr,
7136 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7138 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7140 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
7143 let Predicates = [HasAVX] in {
7144 let ExeDomain = SSEPackedDouble in {
7145 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7146 loadv2f64, int_x86_sse41_blendvpd>;
7147 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7148 loadv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
7149 } // ExeDomain = SSEPackedDouble
7150 let ExeDomain = SSEPackedSingle in {
7151 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7152 loadv4f32, int_x86_sse41_blendvps>;
7153 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7154 loadv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
7155 } // ExeDomain = SSEPackedSingle
7156 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7157 loadv2i64, int_x86_sse41_pblendvb>;
7160 let Predicates = [HasAVX2] in {
7161 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7162 loadv4i64, int_x86_avx2_pblendvb>, VEX_L;
7165 let Predicates = [HasAVX] in {
7166 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7167 (v16i8 VR128:$src2))),
7168 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7169 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7170 (v4i32 VR128:$src2))),
7171 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7172 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7173 (v4f32 VR128:$src2))),
7174 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7175 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7176 (v2i64 VR128:$src2))),
7177 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7178 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7179 (v2f64 VR128:$src2))),
7180 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7181 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7182 (v8i32 VR256:$src2))),
7183 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7184 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7185 (v8f32 VR256:$src2))),
7186 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7187 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7188 (v4i64 VR256:$src2))),
7189 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7190 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7191 (v4f64 VR256:$src2))),
7192 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7194 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
7196 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7197 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
7199 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7201 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7203 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7204 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7206 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7207 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7209 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7212 let Predicates = [HasAVX2] in {
7213 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7214 (v32i8 VR256:$src2))),
7215 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7216 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
7218 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7221 /// SS41I_ternary_int - SSE 4.1 ternary operator
7222 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7223 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7224 X86MemOperand x86memop, Intrinsic IntId,
7225 OpndItins itins = DEFAULT_ITINS> {
7226 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7227 (ins VR128:$src1, VR128:$src2),
7228 !strconcat(OpcodeStr,
7229 "\t{$src2, $dst|$dst, $src2}"),
7230 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7233 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7234 (ins VR128:$src1, x86memop:$src2),
7235 !strconcat(OpcodeStr,
7236 "\t{$src2, $dst|$dst, $src2}"),
7239 (bitconvert (mem_frag addr:$src2)), XMM0))],
7244 let ExeDomain = SSEPackedDouble in
7245 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7246 int_x86_sse41_blendvpd>;
7247 let ExeDomain = SSEPackedSingle in
7248 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7249 int_x86_sse41_blendvps>;
7250 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7251 int_x86_sse41_pblendvb>;
7253 // Aliases with the implicit xmm0 argument
7254 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7255 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7256 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7257 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7258 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7259 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7260 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7261 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7262 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7263 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7264 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7265 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7267 let Predicates = [UseSSE41] in {
7268 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7269 (v16i8 VR128:$src2))),
7270 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7271 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7272 (v4i32 VR128:$src2))),
7273 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7274 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7275 (v4f32 VR128:$src2))),
7276 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7277 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7278 (v2i64 VR128:$src2))),
7279 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7280 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7281 (v2f64 VR128:$src2))),
7282 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7284 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7286 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7287 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7289 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7290 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7292 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7296 let Predicates = [HasAVX] in
7297 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7298 "vmovntdqa\t{$src, $dst|$dst, $src}",
7299 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7301 let Predicates = [HasAVX2] in
7302 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7303 "vmovntdqa\t{$src, $dst|$dst, $src}",
7304 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7306 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7307 "movntdqa\t{$src, $dst|$dst, $src}",
7308 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7311 //===----------------------------------------------------------------------===//
7312 // SSE4.2 - Compare Instructions
7313 //===----------------------------------------------------------------------===//
7315 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7316 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7317 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7318 X86MemOperand x86memop, bit Is2Addr = 1> {
7319 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7320 (ins RC:$src1, RC:$src2),
7322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7324 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7326 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7327 (ins RC:$src1, x86memop:$src2),
7329 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7330 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7332 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
7335 let Predicates = [HasAVX] in
7336 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7337 loadv2i64, i128mem, 0>, VEX_4V;
7339 let Predicates = [HasAVX2] in
7340 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7341 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7343 let Constraints = "$src1 = $dst" in
7344 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7345 memopv2i64, i128mem>;
7347 //===----------------------------------------------------------------------===//
7348 // SSE4.2 - String/text Processing Instructions
7349 //===----------------------------------------------------------------------===//
7351 // Packed Compare Implicit Length Strings, Return Mask
7352 multiclass pseudo_pcmpistrm<string asm> {
7353 def REG : PseudoI<(outs VR128:$dst),
7354 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7355 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7357 def MEM : PseudoI<(outs VR128:$dst),
7358 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7359 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7360 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7363 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7364 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7365 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7368 multiclass pcmpistrm_SS42AI<string asm> {
7369 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7370 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7371 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7374 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7375 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7376 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7380 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7381 let Predicates = [HasAVX] in
7382 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7383 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7386 // Packed Compare Explicit Length Strings, Return Mask
7387 multiclass pseudo_pcmpestrm<string asm> {
7388 def REG : PseudoI<(outs VR128:$dst),
7389 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7390 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7391 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7392 def MEM : PseudoI<(outs VR128:$dst),
7393 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7394 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7395 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7398 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7399 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7400 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7403 multiclass SS42AI_pcmpestrm<string asm> {
7404 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7405 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7406 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7409 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7410 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7411 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7415 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7416 let Predicates = [HasAVX] in
7417 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7418 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7421 // Packed Compare Implicit Length Strings, Return Index
7422 multiclass pseudo_pcmpistri<string asm> {
7423 def REG : PseudoI<(outs GR32:$dst),
7424 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7425 [(set GR32:$dst, EFLAGS,
7426 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7427 def MEM : PseudoI<(outs GR32:$dst),
7428 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7429 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7430 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7433 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7434 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7435 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7438 multiclass SS42AI_pcmpistri<string asm> {
7439 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7440 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7441 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7444 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7445 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7446 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7450 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7451 let Predicates = [HasAVX] in
7452 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7453 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7456 // Packed Compare Explicit Length Strings, Return Index
7457 multiclass pseudo_pcmpestri<string asm> {
7458 def REG : PseudoI<(outs GR32:$dst),
7459 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7460 [(set GR32:$dst, EFLAGS,
7461 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7462 def MEM : PseudoI<(outs GR32:$dst),
7463 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7464 [(set GR32:$dst, EFLAGS,
7465 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7469 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7470 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7471 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7474 multiclass SS42AI_pcmpestri<string asm> {
7475 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7476 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7477 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7480 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7481 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7482 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7486 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7487 let Predicates = [HasAVX] in
7488 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7489 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7492 //===----------------------------------------------------------------------===//
7493 // SSE4.2 - CRC Instructions
7494 //===----------------------------------------------------------------------===//
7496 // No CRC instructions have AVX equivalents
7498 // crc intrinsic instruction
7499 // This set of instructions are only rm, the only difference is the size
7501 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7502 RegisterClass RCIn, SDPatternOperator Int> :
7503 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7504 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7505 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>;
7507 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7508 X86MemOperand x86memop, SDPatternOperator Int> :
7509 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7510 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7511 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7514 let Constraints = "$src1 = $dst" in {
7515 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7516 int_x86_sse42_crc32_32_8>;
7517 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7518 int_x86_sse42_crc32_32_8>;
7519 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7520 int_x86_sse42_crc32_32_16>, OpSize;
7521 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7522 int_x86_sse42_crc32_32_16>, OpSize;
7523 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7524 int_x86_sse42_crc32_32_32>;
7525 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7526 int_x86_sse42_crc32_32_32>;
7527 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7528 int_x86_sse42_crc32_64_64>, REX_W;
7529 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7530 int_x86_sse42_crc32_64_64>, REX_W;
7531 let hasSideEffects = 0 in {
7533 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7535 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7540 //===----------------------------------------------------------------------===//
7541 // SHA-NI Instructions
7542 //===----------------------------------------------------------------------===//
7544 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7546 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7547 (ins VR128:$src1, VR128:$src2),
7548 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7550 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7551 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7553 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7554 (ins VR128:$src1, i128mem:$src2),
7555 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7557 (set VR128:$dst, (IntId VR128:$src1,
7558 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7559 (set VR128:$dst, (IntId VR128:$src1,
7560 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7563 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7564 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7565 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7566 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7568 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7569 (i8 imm:$src3)))]>, TA;
7570 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7571 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7572 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7574 (int_x86_sha1rnds4 VR128:$src1,
7575 (bc_v4i32 (memopv2i64 addr:$src2)),
7576 (i8 imm:$src3)))]>, TA;
7578 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7579 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7580 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7583 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7585 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7586 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7589 // Aliases with explicit %xmm0
7590 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7591 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7592 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7593 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7595 //===----------------------------------------------------------------------===//
7596 // AES-NI Instructions
7597 //===----------------------------------------------------------------------===//
7599 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7600 Intrinsic IntId128, bit Is2Addr = 1> {
7601 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7602 (ins VR128:$src1, VR128:$src2),
7604 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7605 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7606 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7608 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7609 (ins VR128:$src1, i128mem:$src2),
7611 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7612 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7614 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7617 // Perform One Round of an AES Encryption/Decryption Flow
7618 let Predicates = [HasAVX, HasAES] in {
7619 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7620 int_x86_aesni_aesenc, 0>, VEX_4V;
7621 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7622 int_x86_aesni_aesenclast, 0>, VEX_4V;
7623 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7624 int_x86_aesni_aesdec, 0>, VEX_4V;
7625 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7626 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7629 let Constraints = "$src1 = $dst" in {
7630 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7631 int_x86_aesni_aesenc>;
7632 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7633 int_x86_aesni_aesenclast>;
7634 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7635 int_x86_aesni_aesdec>;
7636 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7637 int_x86_aesni_aesdeclast>;
7640 // Perform the AES InvMixColumn Transformation
7641 let Predicates = [HasAVX, HasAES] in {
7642 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7644 "vaesimc\t{$src1, $dst|$dst, $src1}",
7646 (int_x86_aesni_aesimc VR128:$src1))]>,
7648 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7649 (ins i128mem:$src1),
7650 "vaesimc\t{$src1, $dst|$dst, $src1}",
7651 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7654 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7656 "aesimc\t{$src1, $dst|$dst, $src1}",
7658 (int_x86_aesni_aesimc VR128:$src1))]>,
7660 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7661 (ins i128mem:$src1),
7662 "aesimc\t{$src1, $dst|$dst, $src1}",
7663 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7666 // AES Round Key Generation Assist
7667 let Predicates = [HasAVX, HasAES] in {
7668 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7669 (ins VR128:$src1, i8imm:$src2),
7670 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7672 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7674 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7675 (ins i128mem:$src1, i8imm:$src2),
7676 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7678 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7681 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7682 (ins VR128:$src1, i8imm:$src2),
7683 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7685 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7687 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7688 (ins i128mem:$src1, i8imm:$src2),
7689 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7691 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7694 //===----------------------------------------------------------------------===//
7695 // PCLMUL Instructions
7696 //===----------------------------------------------------------------------===//
7698 // AVX carry-less Multiplication instructions
7699 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7700 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7701 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7703 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7705 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7706 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7707 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7708 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7709 (loadv2i64 addr:$src2), imm:$src3))]>;
7711 // Carry-less Multiplication instructions
7712 let Constraints = "$src1 = $dst" in {
7713 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7714 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7715 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7717 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7718 IIC_SSE_PCLMULQDQ_RR>;
7720 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7721 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7722 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7723 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7724 (memopv2i64 addr:$src2), imm:$src3))],
7725 IIC_SSE_PCLMULQDQ_RM>;
7726 } // Constraints = "$src1 = $dst"
7729 multiclass pclmul_alias<string asm, int immop> {
7730 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7731 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7733 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7734 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7736 def : InstAlias<!strconcat("vpclmul", asm,
7737 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7738 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7740 def : InstAlias<!strconcat("vpclmul", asm,
7741 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7742 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7744 defm : pclmul_alias<"hqhq", 0x11>;
7745 defm : pclmul_alias<"hqlq", 0x01>;
7746 defm : pclmul_alias<"lqhq", 0x10>;
7747 defm : pclmul_alias<"lqlq", 0x00>;
7749 //===----------------------------------------------------------------------===//
7750 // SSE4A Instructions
7751 //===----------------------------------------------------------------------===//
7753 let Predicates = [HasSSE4A] in {
7755 let Constraints = "$src = $dst" in {
7756 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7757 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7758 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7759 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7760 imm:$idx))]>, TB, OpSize;
7761 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7762 (ins VR128:$src, VR128:$mask),
7763 "extrq\t{$mask, $src|$src, $mask}",
7764 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7765 VR128:$mask))]>, TB, OpSize;
7767 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7768 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7769 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7770 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7771 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7772 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7773 (ins VR128:$src, VR128:$mask),
7774 "insertq\t{$mask, $src|$src, $mask}",
7775 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7776 VR128:$mask))]>, XD;
7779 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7780 "movntss\t{$src, $dst|$dst, $src}",
7781 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7783 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7784 "movntsd\t{$src, $dst|$dst, $src}",
7785 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7788 //===----------------------------------------------------------------------===//
7790 //===----------------------------------------------------------------------===//
7792 //===----------------------------------------------------------------------===//
7793 // VBROADCAST - Load from memory and broadcast to all elements of the
7794 // destination operand
7796 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7797 X86MemOperand x86memop, Intrinsic Int> :
7798 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7799 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7800 [(set RC:$dst, (Int addr:$src))]>, VEX;
7802 // AVX2 adds register forms
7803 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7805 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7806 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7807 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7809 let ExeDomain = SSEPackedSingle in {
7810 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7811 int_x86_avx_vbroadcast_ss>;
7812 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7813 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7815 let ExeDomain = SSEPackedDouble in
7816 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7817 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7818 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7819 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7821 let ExeDomain = SSEPackedSingle in {
7822 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7823 int_x86_avx2_vbroadcast_ss_ps>;
7824 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7825 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7827 let ExeDomain = SSEPackedDouble in
7828 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7829 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7831 let Predicates = [HasAVX2] in
7832 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7833 int_x86_avx2_vbroadcasti128>, VEX_L;
7835 let Predicates = [HasAVX] in
7836 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7837 (VBROADCASTF128 addr:$src)>;
7840 //===----------------------------------------------------------------------===//
7841 // VINSERTF128 - Insert packed floating-point values
7843 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7844 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7845 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7846 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7849 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7850 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7851 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7855 let Predicates = [HasAVX] in {
7856 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7858 (VINSERTF128rr VR256:$src1, VR128:$src2,
7859 (INSERT_get_vinsert128_imm VR256:$ins))>;
7860 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7862 (VINSERTF128rr VR256:$src1, VR128:$src2,
7863 (INSERT_get_vinsert128_imm VR256:$ins))>;
7865 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7867 (VINSERTF128rm VR256:$src1, addr:$src2,
7868 (INSERT_get_vinsert128_imm VR256:$ins))>;
7869 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7871 (VINSERTF128rm VR256:$src1, addr:$src2,
7872 (INSERT_get_vinsert128_imm VR256:$ins))>;
7875 let Predicates = [HasAVX1Only] in {
7876 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7878 (VINSERTF128rr VR256:$src1, VR128:$src2,
7879 (INSERT_get_vinsert128_imm VR256:$ins))>;
7880 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7882 (VINSERTF128rr VR256:$src1, VR128:$src2,
7883 (INSERT_get_vinsert128_imm VR256:$ins))>;
7884 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7886 (VINSERTF128rr VR256:$src1, VR128:$src2,
7887 (INSERT_get_vinsert128_imm VR256:$ins))>;
7888 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7890 (VINSERTF128rr VR256:$src1, VR128:$src2,
7891 (INSERT_get_vinsert128_imm VR256:$ins))>;
7893 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7895 (VINSERTF128rm VR256:$src1, addr:$src2,
7896 (INSERT_get_vinsert128_imm VR256:$ins))>;
7897 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7898 (bc_v4i32 (loadv2i64 addr:$src2)),
7900 (VINSERTF128rm VR256:$src1, addr:$src2,
7901 (INSERT_get_vinsert128_imm VR256:$ins))>;
7902 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7903 (bc_v16i8 (loadv2i64 addr:$src2)),
7905 (VINSERTF128rm VR256:$src1, addr:$src2,
7906 (INSERT_get_vinsert128_imm VR256:$ins))>;
7907 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7908 (bc_v8i16 (loadv2i64 addr:$src2)),
7910 (VINSERTF128rm VR256:$src1, addr:$src2,
7911 (INSERT_get_vinsert128_imm VR256:$ins))>;
7914 //===----------------------------------------------------------------------===//
7915 // VEXTRACTF128 - Extract packed floating-point values
7917 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7918 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7919 (ins VR256:$src1, i8imm:$src2),
7920 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7923 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7924 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7925 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7930 let Predicates = [HasAVX] in {
7931 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7932 (v4f32 (VEXTRACTF128rr
7933 (v8f32 VR256:$src1),
7934 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7935 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7936 (v2f64 (VEXTRACTF128rr
7937 (v4f64 VR256:$src1),
7938 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7940 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7941 (iPTR imm))), addr:$dst),
7942 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7943 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7944 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7945 (iPTR imm))), addr:$dst),
7946 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7947 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7950 let Predicates = [HasAVX1Only] in {
7951 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7952 (v2i64 (VEXTRACTF128rr
7953 (v4i64 VR256:$src1),
7954 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7955 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7956 (v4i32 (VEXTRACTF128rr
7957 (v8i32 VR256:$src1),
7958 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7959 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7960 (v8i16 (VEXTRACTF128rr
7961 (v16i16 VR256:$src1),
7962 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7963 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7964 (v16i8 (VEXTRACTF128rr
7965 (v32i8 VR256:$src1),
7966 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7968 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
7969 (iPTR imm))), addr:$dst),
7970 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7971 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7972 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
7973 (iPTR imm))), addr:$dst),
7974 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7975 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7976 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
7977 (iPTR imm))), addr:$dst),
7978 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7979 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7980 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
7981 (iPTR imm))), addr:$dst),
7982 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7983 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7986 //===----------------------------------------------------------------------===//
7987 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7989 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7990 Intrinsic IntLd, Intrinsic IntLd256,
7991 Intrinsic IntSt, Intrinsic IntSt256> {
7992 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7993 (ins VR128:$src1, f128mem:$src2),
7994 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7995 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7997 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7998 (ins VR256:$src1, f256mem:$src2),
7999 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8000 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8002 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8003 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8004 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8005 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8006 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8007 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8008 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8009 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8012 let ExeDomain = SSEPackedSingle in
8013 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8014 int_x86_avx_maskload_ps,
8015 int_x86_avx_maskload_ps_256,
8016 int_x86_avx_maskstore_ps,
8017 int_x86_avx_maskstore_ps_256>;
8018 let ExeDomain = SSEPackedDouble in
8019 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8020 int_x86_avx_maskload_pd,
8021 int_x86_avx_maskload_pd_256,
8022 int_x86_avx_maskstore_pd,
8023 int_x86_avx_maskstore_pd_256>;
8025 //===----------------------------------------------------------------------===//
8026 // VPERMIL - Permute Single and Double Floating-Point Values
8028 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8029 RegisterClass RC, X86MemOperand x86memop_f,
8030 X86MemOperand x86memop_i, PatFrag i_frag,
8031 Intrinsic IntVar, ValueType vt> {
8032 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8033 (ins RC:$src1, RC:$src2),
8034 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8035 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
8036 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8037 (ins RC:$src1, x86memop_i:$src2),
8038 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8039 [(set RC:$dst, (IntVar RC:$src1,
8040 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
8042 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8043 (ins RC:$src1, i8imm:$src2),
8044 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8045 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
8046 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8047 (ins x86memop_f:$src1, i8imm:$src2),
8048 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8050 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
8053 let ExeDomain = SSEPackedSingle in {
8054 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8055 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8056 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8057 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8059 let ExeDomain = SSEPackedDouble in {
8060 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8061 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8062 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8063 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8066 let Predicates = [HasAVX] in {
8067 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
8068 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8069 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
8070 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8071 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (loadv4i64 addr:$src1)),
8073 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8074 def : Pat<(v4i64 (X86VPermilp (loadv4i64 addr:$src1), (i8 imm:$imm))),
8075 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8077 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
8078 (VPERMILPDri VR128:$src1, imm:$imm)>;
8079 def : Pat<(v2i64 (X86VPermilp (loadv2i64 addr:$src1), (i8 imm:$imm))),
8080 (VPERMILPDmi addr:$src1, imm:$imm)>;
8083 //===----------------------------------------------------------------------===//
8084 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8086 let ExeDomain = SSEPackedSingle in {
8087 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8088 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8089 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8090 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8091 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
8092 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8093 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8094 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8095 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8096 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
8099 let Predicates = [HasAVX] in {
8100 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8101 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8102 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8103 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8104 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8107 let Predicates = [HasAVX1Only] in {
8108 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8109 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8110 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8111 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8112 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8113 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8114 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8115 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8117 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8118 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8119 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8120 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8121 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8122 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8123 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8124 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8125 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8126 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8127 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8128 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8131 //===----------------------------------------------------------------------===//
8132 // VZERO - Zero YMM registers
8134 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8135 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8136 // Zero All YMM registers
8137 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8138 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
8140 // Zero Upper bits of YMM registers
8141 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8142 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
8145 //===----------------------------------------------------------------------===//
8146 // Half precision conversion instructions
8147 //===----------------------------------------------------------------------===//
8148 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8149 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8150 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8151 [(set RC:$dst, (Int VR128:$src))]>,
8153 let neverHasSideEffects = 1, mayLoad = 1 in
8154 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8155 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
8158 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8159 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8160 (ins RC:$src1, i32i8imm:$src2),
8161 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8162 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8164 let neverHasSideEffects = 1, mayStore = 1 in
8165 def mr : Ii8<0x1D, MRMDestMem, (outs),
8166 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
8167 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8171 let Predicates = [HasF16C] in {
8172 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8173 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8174 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8175 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8178 //===----------------------------------------------------------------------===//
8179 // AVX2 Instructions
8180 //===----------------------------------------------------------------------===//
8182 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
8183 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
8184 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
8185 X86MemOperand x86memop> {
8186 let isCommutable = 1 in
8187 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8188 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
8189 !strconcat(OpcodeStr,
8190 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8191 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8193 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8194 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
8195 !strconcat(OpcodeStr,
8196 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8199 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8203 let isCommutable = 0 in {
8204 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8205 VR128, loadv2i64, i128mem>;
8206 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8207 VR256, loadv4i64, i256mem>, VEX_L;
8210 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8212 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8213 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8215 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8217 //===----------------------------------------------------------------------===//
8218 // VPBROADCAST - Load from memory and broadcast to all elements of the
8219 // destination operand
8221 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8222 X86MemOperand x86memop, PatFrag ld_frag,
8223 Intrinsic Int128, Intrinsic Int256> {
8224 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8225 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8226 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
8227 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8228 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8230 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
8231 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8232 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8233 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
8234 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8235 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8237 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8241 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8242 int_x86_avx2_pbroadcastb_128,
8243 int_x86_avx2_pbroadcastb_256>;
8244 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8245 int_x86_avx2_pbroadcastw_128,
8246 int_x86_avx2_pbroadcastw_256>;
8247 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8248 int_x86_avx2_pbroadcastd_128,
8249 int_x86_avx2_pbroadcastd_256>;
8250 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8251 int_x86_avx2_pbroadcastq_128,
8252 int_x86_avx2_pbroadcastq_256>;
8254 let Predicates = [HasAVX2] in {
8255 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8256 (VPBROADCASTBrm addr:$src)>;
8257 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8258 (VPBROADCASTBYrm addr:$src)>;
8259 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8260 (VPBROADCASTWrm addr:$src)>;
8261 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8262 (VPBROADCASTWYrm addr:$src)>;
8263 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8264 (VPBROADCASTDrm addr:$src)>;
8265 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8266 (VPBROADCASTDYrm addr:$src)>;
8267 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8268 (VPBROADCASTQrm addr:$src)>;
8269 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8270 (VPBROADCASTQYrm addr:$src)>;
8272 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8273 (VPBROADCASTBrr VR128:$src)>;
8274 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8275 (VPBROADCASTBYrr VR128:$src)>;
8276 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8277 (VPBROADCASTWrr VR128:$src)>;
8278 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8279 (VPBROADCASTWYrr VR128:$src)>;
8280 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8281 (VPBROADCASTDrr VR128:$src)>;
8282 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8283 (VPBROADCASTDYrr VR128:$src)>;
8284 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8285 (VPBROADCASTQrr VR128:$src)>;
8286 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8287 (VPBROADCASTQYrr VR128:$src)>;
8288 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8289 (VBROADCASTSSrr VR128:$src)>;
8290 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8291 (VBROADCASTSSYrr VR128:$src)>;
8292 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8293 (VPBROADCASTQrr VR128:$src)>;
8294 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8295 (VBROADCASTSDYrr VR128:$src)>;
8297 // Provide fallback in case the load node that is used in the patterns above
8298 // is used by additional users, which prevents the pattern selection.
8299 let AddedComplexity = 20 in {
8300 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8301 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8302 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8303 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8304 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8305 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8307 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8308 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8309 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8310 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8311 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8312 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8316 // AVX1 broadcast patterns
8317 let Predicates = [HasAVX1Only] in {
8318 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8319 (VBROADCASTSSYrm addr:$src)>;
8320 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8321 (VBROADCASTSDYrm addr:$src)>;
8322 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8323 (VBROADCASTSSrm addr:$src)>;
8326 let Predicates = [HasAVX] in {
8327 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
8328 (VBROADCASTSSYrm addr:$src)>;
8329 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
8330 (VBROADCASTSDYrm addr:$src)>;
8331 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
8332 (VBROADCASTSSrm addr:$src)>;
8334 // Provide fallback in case the load node that is used in the patterns above
8335 // is used by additional users, which prevents the pattern selection.
8336 let AddedComplexity = 20 in {
8337 // 128bit broadcasts:
8338 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8339 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8340 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8341 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8342 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8343 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8344 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8345 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8346 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8347 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8349 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8350 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8351 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8352 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8353 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8354 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8355 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8356 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8357 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8358 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8362 //===----------------------------------------------------------------------===//
8363 // VPERM - Permute instructions
8366 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8368 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8369 (ins VR256:$src1, VR256:$src2),
8370 !strconcat(OpcodeStr,
8371 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8373 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8375 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8376 (ins VR256:$src1, i256mem:$src2),
8377 !strconcat(OpcodeStr,
8378 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8380 (OpVT (X86VPermv VR256:$src1,
8381 (bitconvert (mem_frag addr:$src2)))))]>,
8385 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32>;
8386 let ExeDomain = SSEPackedSingle in
8387 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32>;
8389 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8391 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8392 (ins VR256:$src1, i8imm:$src2),
8393 !strconcat(OpcodeStr,
8394 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8396 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8398 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8399 (ins i256mem:$src1, i8imm:$src2),
8400 !strconcat(OpcodeStr,
8401 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8403 (OpVT (X86VPermi (mem_frag addr:$src1),
8404 (i8 imm:$src2))))]>, VEX, VEX_L;
8407 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64>, VEX_W;
8408 let ExeDomain = SSEPackedDouble in
8409 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64>, VEX_W;
8411 //===----------------------------------------------------------------------===//
8412 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8414 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8415 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8416 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8417 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8418 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
8419 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8420 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8421 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8422 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8423 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
8425 let Predicates = [HasAVX2] in {
8426 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8427 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8428 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8429 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8430 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8431 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8433 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8435 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8436 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8437 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8438 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8439 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8441 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8445 //===----------------------------------------------------------------------===//
8446 // VINSERTI128 - Insert packed integer values
8448 let neverHasSideEffects = 1 in {
8449 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8450 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8451 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8454 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8455 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8456 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8460 let Predicates = [HasAVX2] in {
8461 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8463 (VINSERTI128rr VR256:$src1, VR128:$src2,
8464 (INSERT_get_vinsert128_imm VR256:$ins))>;
8465 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8467 (VINSERTI128rr VR256:$src1, VR128:$src2,
8468 (INSERT_get_vinsert128_imm VR256:$ins))>;
8469 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8471 (VINSERTI128rr VR256:$src1, VR128:$src2,
8472 (INSERT_get_vinsert128_imm VR256:$ins))>;
8473 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8475 (VINSERTI128rr VR256:$src1, VR128:$src2,
8476 (INSERT_get_vinsert128_imm VR256:$ins))>;
8478 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8480 (VINSERTI128rm VR256:$src1, addr:$src2,
8481 (INSERT_get_vinsert128_imm VR256:$ins))>;
8482 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8483 (bc_v4i32 (loadv2i64 addr:$src2)),
8485 (VINSERTI128rm VR256:$src1, addr:$src2,
8486 (INSERT_get_vinsert128_imm VR256:$ins))>;
8487 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8488 (bc_v16i8 (loadv2i64 addr:$src2)),
8490 (VINSERTI128rm VR256:$src1, addr:$src2,
8491 (INSERT_get_vinsert128_imm VR256:$ins))>;
8492 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8493 (bc_v8i16 (loadv2i64 addr:$src2)),
8495 (VINSERTI128rm VR256:$src1, addr:$src2,
8496 (INSERT_get_vinsert128_imm VR256:$ins))>;
8499 //===----------------------------------------------------------------------===//
8500 // VEXTRACTI128 - Extract packed integer values
8502 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8503 (ins VR256:$src1, i8imm:$src2),
8504 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8506 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8508 let neverHasSideEffects = 1, mayStore = 1 in
8509 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8510 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8511 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8514 let Predicates = [HasAVX2] in {
8515 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8516 (v2i64 (VEXTRACTI128rr
8517 (v4i64 VR256:$src1),
8518 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8519 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8520 (v4i32 (VEXTRACTI128rr
8521 (v8i32 VR256:$src1),
8522 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8523 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8524 (v8i16 (VEXTRACTI128rr
8525 (v16i16 VR256:$src1),
8526 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8527 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8528 (v16i8 (VEXTRACTI128rr
8529 (v32i8 VR256:$src1),
8530 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8532 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8533 (iPTR imm))), addr:$dst),
8534 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8535 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8536 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8537 (iPTR imm))), addr:$dst),
8538 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8539 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8540 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8541 (iPTR imm))), addr:$dst),
8542 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8543 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8544 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8545 (iPTR imm))), addr:$dst),
8546 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8547 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8550 //===----------------------------------------------------------------------===//
8551 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8553 multiclass avx2_pmovmask<string OpcodeStr,
8554 Intrinsic IntLd128, Intrinsic IntLd256,
8555 Intrinsic IntSt128, Intrinsic IntSt256> {
8556 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8557 (ins VR128:$src1, i128mem:$src2),
8558 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8559 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8560 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8561 (ins VR256:$src1, i256mem:$src2),
8562 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8563 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8565 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8566 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8567 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8568 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8569 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8570 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8571 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8572 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8575 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8576 int_x86_avx2_maskload_d,
8577 int_x86_avx2_maskload_d_256,
8578 int_x86_avx2_maskstore_d,
8579 int_x86_avx2_maskstore_d_256>;
8580 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8581 int_x86_avx2_maskload_q,
8582 int_x86_avx2_maskload_q_256,
8583 int_x86_avx2_maskstore_q,
8584 int_x86_avx2_maskstore_q_256>, VEX_W;
8587 //===----------------------------------------------------------------------===//
8588 // Variable Bit Shifts
8590 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8591 ValueType vt128, ValueType vt256> {
8592 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8593 (ins VR128:$src1, VR128:$src2),
8594 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8596 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8598 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8599 (ins VR128:$src1, i128mem:$src2),
8600 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8602 (vt128 (OpNode VR128:$src1,
8603 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8605 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8606 (ins VR256:$src1, VR256:$src2),
8607 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8609 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8611 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8612 (ins VR256:$src1, i256mem:$src2),
8613 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8615 (vt256 (OpNode VR256:$src1,
8616 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8620 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8621 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8622 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8623 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8624 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8626 //===----------------------------------------------------------------------===//
8627 // VGATHER - GATHER Operations
8628 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8629 X86MemOperand memop128, X86MemOperand memop256> {
8630 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8631 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8632 !strconcat(OpcodeStr,
8633 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8635 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8636 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8637 !strconcat(OpcodeStr,
8638 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8639 []>, VEX_4VOp3, VEX_L;
8642 let mayLoad = 1, Constraints
8643 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8645 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8646 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8647 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8648 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8649 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8650 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8651 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8652 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;