1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_DEFAULT, d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
80 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
81 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
82 string OpcodeStr, X86MemOperand x86memop,
83 list<dag> pat_rr, list<dag> pat_rm,
85 bit rr_hasSideEffects = 0> {
86 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
87 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
89 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
90 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
91 pat_rr, IIC_DEFAULT, d>;
92 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
94 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
95 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
96 pat_rm, IIC_DEFAULT, d>;
99 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
100 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
101 string asm, string SSEVer, string FPSizeStr,
102 X86MemOperand x86memop, PatFrag mem_frag,
103 Domain d, bit Is2Addr = 1> {
104 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
106 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
107 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
108 [(set RC:$dst, (!cast<Intrinsic>(
109 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
110 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
111 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
113 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
114 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
115 [(set RC:$dst, (!cast<Intrinsic>(
116 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
117 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
120 //===----------------------------------------------------------------------===//
121 // Non-instruction patterns
122 //===----------------------------------------------------------------------===//
124 // A vector extract of the first f32/f64 position is a subregister copy
125 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
126 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
127 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
128 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
130 // A 128-bit subvector extract from the first 256-bit vector position
131 // is a subregister copy that needs no instruction.
132 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
133 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
134 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
135 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
137 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
138 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
139 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
140 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
142 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
143 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
144 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
145 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
147 // A 128-bit subvector insert to the first 256-bit vector position
148 // is a subregister copy that needs no instruction.
149 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
150 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
151 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
152 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
153 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
154 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
155 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
156 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
157 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
158 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
159 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
160 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
162 // Implicitly promote a 32-bit scalar to a vector.
163 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
164 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
165 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
166 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
167 // Implicitly promote a 64-bit scalar to a vector.
168 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
169 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
170 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
171 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
173 // Bitcasts between 128-bit vector types. Return the original type since
174 // no instruction is needed for the conversion
175 let Predicates = [HasSSE2] in {
176 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
178 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
179 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
180 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
183 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
184 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
185 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
188 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
189 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
190 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
193 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
194 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
195 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
198 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
199 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
200 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
202 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
203 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
204 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
205 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
208 // Bitcasts between 256-bit vector types. Return the original type since
209 // no instruction is needed for the conversion
210 let Predicates = [HasAVX] in {
211 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
213 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
214 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
215 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
218 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
219 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
220 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
223 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
224 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
225 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
228 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
229 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
230 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
233 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
234 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
235 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
237 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
238 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
239 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
240 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
243 // Alias instructions that map fld0 to pxor for sse.
244 // This is expanded by ExpandPostRAPseudos.
245 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
247 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
248 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
249 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
250 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
253 //===----------------------------------------------------------------------===//
254 // AVX & SSE - Zero/One Vectors
255 //===----------------------------------------------------------------------===//
257 // Alias instruction that maps zero vector to pxor / xorp* for sse.
258 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
259 // swizzled by ExecutionDepsFix to pxor.
260 // We set canFoldAsLoad because this can be converted to a constant-pool
261 // load of an all-zeros value if folding it would be beneficial.
262 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
263 isPseudo = 1, neverHasSideEffects = 1 in {
264 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
267 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
268 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
269 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
270 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
271 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
272 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
275 // The same as done above but for AVX. The 256-bit ISA does not support PI,
276 // and doesn't need it because on sandy bridge the register is set to zero
277 // at the rename stage without using any execution unit, so SET0PSY
278 // and SET0PDY can be used for vector int instructions without penalty
279 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
280 // JIT implementatioan, it does not expand the instructions below like
281 // X86MCInstLower does.
282 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
283 isCodeGenOnly = 1 in {
284 let Predicates = [HasAVX] in {
285 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
286 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
287 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
288 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
290 let Predicates = [HasAVX2], neverHasSideEffects = 1 in
291 def AVX2_SET0 : PDI<0xef, MRMInitReg, (outs VR256:$dst), (ins), "",
295 let Predicates = [HasAVX2], AddedComplexity = 5 in {
296 def : Pat<(v4i64 immAllZerosV), (AVX2_SET0)>;
297 def : Pat<(v8i32 immAllZerosV), (AVX2_SET0)>;
298 def : Pat<(v16i16 immAllZerosV), (AVX2_SET0)>;
299 def : Pat<(v32i8 immAllZerosV), (AVX2_SET0)>;
302 // AVX has no support for 256-bit integer instructions, but since the 128-bit
303 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
304 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
305 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
306 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
308 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
309 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
310 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
312 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
313 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
314 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
316 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
317 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
318 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
320 // We set canFoldAsLoad because this can be converted to a constant-pool
321 // load of an all-ones value if folding it would be beneficial.
322 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
323 // JIT implementation, it does not expand the instructions below like
324 // X86MCInstLower does.
325 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
326 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
327 let Predicates = [HasAVX] in
328 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
329 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
330 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
331 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
332 let Predicates = [HasAVX2] in
333 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
334 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
338 //===----------------------------------------------------------------------===//
339 // SSE 1 & 2 - Move FP Scalar Instructions
341 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
342 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
343 // is used instead. Register-to-register movss/movsd is not modeled as an
344 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
345 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
346 //===----------------------------------------------------------------------===//
348 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
349 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
350 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
352 // Loading from memory automatically zeroing upper bits.
353 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
354 PatFrag mem_pat, string OpcodeStr> :
355 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
356 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
357 [(set RC:$dst, (mem_pat addr:$src))]>;
360 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
361 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
363 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
364 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
367 // For the disassembler
368 let isCodeGenOnly = 1 in {
369 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
370 (ins VR128:$src1, FR32:$src2),
371 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
373 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
374 (ins VR128:$src1, FR64:$src2),
375 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
379 let canFoldAsLoad = 1, isReMaterializable = 1 in {
380 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
382 let AddedComplexity = 20 in
383 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
387 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
388 "movss\t{$src, $dst|$dst, $src}",
389 [(store FR32:$src, addr:$dst)]>, XS, VEX, VEX_LIG;
390 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
391 "movsd\t{$src, $dst|$dst, $src}",
392 [(store FR64:$src, addr:$dst)]>, XD, VEX, VEX_LIG;
395 let Constraints = "$src1 = $dst" in {
396 def MOVSSrr : sse12_move_rr<FR32, v4f32,
397 "movss\t{$src2, $dst|$dst, $src2}">, XS;
398 def MOVSDrr : sse12_move_rr<FR64, v2f64,
399 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
401 // For the disassembler
402 let isCodeGenOnly = 1 in {
403 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
404 (ins VR128:$src1, FR32:$src2),
405 "movss\t{$src2, $dst|$dst, $src2}", []>, XS;
406 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
407 (ins VR128:$src1, FR64:$src2),
408 "movsd\t{$src2, $dst|$dst, $src2}", []>, XD;
412 let canFoldAsLoad = 1, isReMaterializable = 1 in {
413 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
415 let AddedComplexity = 20 in
416 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
419 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
420 "movss\t{$src, $dst|$dst, $src}",
421 [(store FR32:$src, addr:$dst)]>;
422 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
423 "movsd\t{$src, $dst|$dst, $src}",
424 [(store FR64:$src, addr:$dst)]>;
427 let Predicates = [HasAVX] in {
428 let AddedComplexity = 15 in {
429 // Extract the low 32-bit value from one vector and insert it into another.
430 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
431 (VMOVSSrr (v4f32 VR128:$src1),
432 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
433 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
434 (VMOVSSrr (v4i32 VR128:$src1),
435 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
437 // Extract the low 64-bit value from one vector and insert it into another.
438 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
439 (VMOVSDrr (v2f64 VR128:$src1),
440 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
441 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
442 (VMOVSDrr (v2i64 VR128:$src1),
443 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
445 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
446 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
447 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
448 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
449 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
451 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
452 // MOVS{S,D} to the lower bits.
453 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
454 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
455 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
456 (VMOVSSrr (v4f32 (V_SET0)),
457 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
458 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
459 (VMOVSSrr (v4i32 (V_SET0)),
460 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
461 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
462 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
464 // Move low f32 and clear high bits.
465 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
466 (SUBREG_TO_REG (i32 0),
467 (VMOVSSrr (v4f32 (V_SET0)),
468 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_ss)), sub_xmm)>;
469 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
470 (SUBREG_TO_REG (i32 0),
471 (VMOVSSrr (v4i32 (V_SET0)),
472 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_ss)), sub_xmm)>;
475 let AddedComplexity = 20 in {
476 // MOVSSrm zeros the high parts of the register; represent this
477 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
478 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
479 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
480 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
481 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
482 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
483 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
485 // MOVSDrm zeros the high parts of the register; represent this
486 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
487 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
488 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
489 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
490 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
491 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
492 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
493 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
494 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
495 def : Pat<(v2f64 (X86vzload addr:$src)),
496 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
498 // Represent the same patterns above but in the form they appear for
500 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
501 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
502 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
503 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
504 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
505 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
506 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
507 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
508 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
510 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
511 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
512 (SUBREG_TO_REG (i32 0),
513 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
515 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
516 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
517 (SUBREG_TO_REG (i64 0),
518 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
520 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
521 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
522 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
524 // Move low f64 and clear high bits.
525 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
526 (SUBREG_TO_REG (i32 0),
527 (VMOVSDrr (v2f64 (V_SET0)),
528 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_sd)), sub_xmm)>;
530 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
531 (SUBREG_TO_REG (i32 0),
532 (VMOVSDrr (v2i64 (V_SET0)),
533 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_sd)), sub_xmm)>;
535 // Extract and store.
536 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
539 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
540 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
543 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
545 // Shuffle with VMOVSS
546 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
547 (VMOVSSrr VR128:$src1, FR32:$src2)>;
548 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
549 (VMOVSSrr (v4i32 VR128:$src1),
550 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
551 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
552 (VMOVSSrr (v4f32 VR128:$src1),
553 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
556 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
557 (SUBREG_TO_REG (i32 0),
558 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_ss),
559 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_ss)), sub_xmm)>;
560 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
561 (SUBREG_TO_REG (i32 0),
562 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_ss),
563 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_ss)), sub_xmm)>;
565 // Shuffle with VMOVSD
566 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
567 (VMOVSDrr VR128:$src1, FR64:$src2)>;
568 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
569 (VMOVSDrr (v2i64 VR128:$src1),
570 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
571 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
572 (VMOVSDrr (v2f64 VR128:$src1),
573 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
574 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
575 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
577 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
578 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
582 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
583 (SUBREG_TO_REG (i32 0),
584 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_sd),
585 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_sd)), sub_xmm)>;
586 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
587 (SUBREG_TO_REG (i32 0),
588 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_sd),
589 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_sd)), sub_xmm)>;
592 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
593 // is during lowering, where it's not possible to recognize the fold cause
594 // it has two uses through a bitcast. One use disappears at isel time and the
595 // fold opportunity reappears.
596 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
597 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
599 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
600 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),
602 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
603 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
605 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
606 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
610 let Predicates = [HasSSE1] in {
611 let AddedComplexity = 15 in {
612 // Extract the low 32-bit value from one vector and insert it into another.
613 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
614 (MOVSSrr (v4f32 VR128:$src1),
615 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
616 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
617 (MOVSSrr (v4i32 VR128:$src1),
618 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
620 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
621 // MOVSS to the lower bits.
622 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
623 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
624 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
625 (MOVSSrr (v4f32 (V_SET0)),
626 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
627 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
628 (MOVSSrr (v4i32 (V_SET0)),
629 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
632 let AddedComplexity = 20 in {
633 // MOVSSrm zeros the high parts of the register; represent this
634 // with SUBREG_TO_REG.
635 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
636 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
637 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
638 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
639 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
640 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
643 // Extract and store.
644 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
647 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
649 // Shuffle with MOVSS
650 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
651 (MOVSSrr VR128:$src1, FR32:$src2)>;
652 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
653 (MOVSSrr (v4i32 VR128:$src1),
654 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
655 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
656 (MOVSSrr (v4f32 VR128:$src1),
657 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
660 let Predicates = [HasSSE2] in {
661 let AddedComplexity = 15 in {
662 // Extract the low 64-bit value from one vector and insert it into another.
663 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
664 (MOVSDrr (v2f64 VR128:$src1),
665 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
666 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
667 (MOVSDrr (v2i64 VR128:$src1),
668 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
670 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
671 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
672 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
673 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
674 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
676 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
677 // MOVSD to the lower bits.
678 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
679 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
682 let AddedComplexity = 20 in {
683 // MOVSDrm zeros the high parts of the register; represent this
684 // with SUBREG_TO_REG.
685 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
686 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
687 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
688 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
689 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
690 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
691 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
692 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
693 def : Pat<(v2f64 (X86vzload addr:$src)),
694 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
697 // Extract and store.
698 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
701 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
703 // Shuffle with MOVSD
704 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
705 (MOVSDrr VR128:$src1, FR64:$src2)>;
706 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
707 (MOVSDrr (v2i64 VR128:$src1),
708 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
709 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
710 (MOVSDrr (v2f64 VR128:$src1),
711 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
712 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
713 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
714 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
715 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
717 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
718 // is during lowering, where it's not possible to recognize the fold cause
719 // it has two uses through a bitcast. One use disappears at isel time and the
720 // fold opportunity reappears.
721 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
722 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
723 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
724 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
725 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
726 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
727 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
728 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
731 //===----------------------------------------------------------------------===//
732 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
733 //===----------------------------------------------------------------------===//
735 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
736 X86MemOperand x86memop, PatFrag ld_frag,
737 string asm, Domain d,
738 bit IsReMaterializable = 1> {
739 let neverHasSideEffects = 1 in
740 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
741 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], IIC_DEFAULT, d>;
742 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
743 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
744 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
745 [(set RC:$dst, (ld_frag addr:$src))], IIC_DEFAULT, d>;
748 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
749 "movaps", SSEPackedSingle>, TB, VEX;
750 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
751 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
752 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
753 "movups", SSEPackedSingle>, TB, VEX;
754 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
755 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
757 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
758 "movaps", SSEPackedSingle>, TB, VEX;
759 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
760 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
761 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
762 "movups", SSEPackedSingle>, TB, VEX;
763 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
764 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
765 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
766 "movaps", SSEPackedSingle>, TB;
767 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
768 "movapd", SSEPackedDouble>, TB, OpSize;
769 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
770 "movups", SSEPackedSingle>, TB;
771 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
772 "movupd", SSEPackedDouble, 0>, TB, OpSize;
774 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
775 "movaps\t{$src, $dst|$dst, $src}",
776 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
777 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
778 "movapd\t{$src, $dst|$dst, $src}",
779 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
780 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
781 "movups\t{$src, $dst|$dst, $src}",
782 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
783 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
784 "movupd\t{$src, $dst|$dst, $src}",
785 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
786 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
787 "movaps\t{$src, $dst|$dst, $src}",
788 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)]>, VEX;
789 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
790 "movapd\t{$src, $dst|$dst, $src}",
791 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)]>, VEX;
792 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
793 "movups\t{$src, $dst|$dst, $src}",
794 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
795 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
796 "movupd\t{$src, $dst|$dst, $src}",
797 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
800 let isCodeGenOnly = 1 in {
801 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
803 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
804 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
806 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
807 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
809 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
810 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
812 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
813 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
815 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
816 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
818 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
819 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
821 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
822 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
824 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
827 let Predicates = [HasAVX] in {
828 def : Pat<(v8i32 (X86vzmovl
829 (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
830 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
831 def : Pat<(v4i64 (X86vzmovl
832 (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
833 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
834 def : Pat<(v8f32 (X86vzmovl
835 (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
836 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
837 def : Pat<(v4f64 (X86vzmovl
838 (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
839 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
843 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
844 (VMOVUPSYmr addr:$dst, VR256:$src)>;
845 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
846 (VMOVUPDYmr addr:$dst, VR256:$src)>;
848 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
849 "movaps\t{$src, $dst|$dst, $src}",
850 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
851 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
852 "movapd\t{$src, $dst|$dst, $src}",
853 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
854 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
855 "movups\t{$src, $dst|$dst, $src}",
856 [(store (v4f32 VR128:$src), addr:$dst)]>;
857 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
858 "movupd\t{$src, $dst|$dst, $src}",
859 [(store (v2f64 VR128:$src), addr:$dst)]>;
862 let isCodeGenOnly = 1 in {
863 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
864 "movaps\t{$src, $dst|$dst, $src}", []>;
865 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
866 "movapd\t{$src, $dst|$dst, $src}", []>;
867 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
868 "movups\t{$src, $dst|$dst, $src}", []>;
869 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
870 "movupd\t{$src, $dst|$dst, $src}", []>;
873 let Predicates = [HasAVX] in {
874 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
875 (VMOVUPSmr addr:$dst, VR128:$src)>;
876 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
877 (VMOVUPDmr addr:$dst, VR128:$src)>;
880 let Predicates = [HasSSE1] in
881 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
882 (MOVUPSmr addr:$dst, VR128:$src)>;
883 let Predicates = [HasSSE2] in
884 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
885 (MOVUPDmr addr:$dst, VR128:$src)>;
887 // Use vmovaps/vmovups for AVX integer load/store.
888 let Predicates = [HasAVX] in {
889 // 128-bit load/store
890 def : Pat<(alignedloadv2i64 addr:$src),
891 (VMOVAPSrm addr:$src)>;
892 def : Pat<(loadv2i64 addr:$src),
893 (VMOVUPSrm addr:$src)>;
895 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
896 (VMOVAPSmr addr:$dst, VR128:$src)>;
897 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
898 (VMOVAPSmr addr:$dst, VR128:$src)>;
899 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
900 (VMOVAPSmr addr:$dst, VR128:$src)>;
901 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
902 (VMOVAPSmr addr:$dst, VR128:$src)>;
903 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
904 (VMOVUPSmr addr:$dst, VR128:$src)>;
905 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
906 (VMOVUPSmr addr:$dst, VR128:$src)>;
907 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
908 (VMOVUPSmr addr:$dst, VR128:$src)>;
909 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
910 (VMOVUPSmr addr:$dst, VR128:$src)>;
912 // 256-bit load/store
913 def : Pat<(alignedloadv4i64 addr:$src),
914 (VMOVAPSYrm addr:$src)>;
915 def : Pat<(loadv4i64 addr:$src),
916 (VMOVUPSYrm addr:$src)>;
917 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
918 (VMOVAPSYmr addr:$dst, VR256:$src)>;
919 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
920 (VMOVAPSYmr addr:$dst, VR256:$src)>;
921 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
922 (VMOVAPSYmr addr:$dst, VR256:$src)>;
923 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
924 (VMOVAPSYmr addr:$dst, VR256:$src)>;
925 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
926 (VMOVUPSYmr addr:$dst, VR256:$src)>;
927 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
928 (VMOVUPSYmr addr:$dst, VR256:$src)>;
929 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
930 (VMOVUPSYmr addr:$dst, VR256:$src)>;
931 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
932 (VMOVUPSYmr addr:$dst, VR256:$src)>;
935 // Use movaps / movups for SSE integer load / store (one byte shorter).
936 // The instructions selected below are then converted to MOVDQA/MOVDQU
937 // during the SSE domain pass.
938 let Predicates = [HasSSE1] in {
939 def : Pat<(alignedloadv2i64 addr:$src),
940 (MOVAPSrm addr:$src)>;
941 def : Pat<(loadv2i64 addr:$src),
942 (MOVUPSrm addr:$src)>;
944 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
945 (MOVAPSmr addr:$dst, VR128:$src)>;
946 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
947 (MOVAPSmr addr:$dst, VR128:$src)>;
948 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
949 (MOVAPSmr addr:$dst, VR128:$src)>;
950 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
951 (MOVAPSmr addr:$dst, VR128:$src)>;
952 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
953 (MOVUPSmr addr:$dst, VR128:$src)>;
954 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
955 (MOVUPSmr addr:$dst, VR128:$src)>;
956 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
957 (MOVUPSmr addr:$dst, VR128:$src)>;
958 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
959 (MOVUPSmr addr:$dst, VR128:$src)>;
962 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
963 // bits are disregarded. FIXME: Set encoding to pseudo!
964 let neverHasSideEffects = 1 in {
965 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
966 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
967 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
968 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
969 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
970 "movaps\t{$src, $dst|$dst, $src}", []>;
971 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
972 "movapd\t{$src, $dst|$dst, $src}", []>;
975 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
976 // bits are disregarded. FIXME: Set encoding to pseudo!
977 let canFoldAsLoad = 1, isReMaterializable = 1 in {
978 let isCodeGenOnly = 1 in {
979 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
980 "movaps\t{$src, $dst|$dst, $src}",
981 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
982 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
983 "movapd\t{$src, $dst|$dst, $src}",
984 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
986 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
987 "movaps\t{$src, $dst|$dst, $src}",
988 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
989 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
990 "movapd\t{$src, $dst|$dst, $src}",
991 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
994 //===----------------------------------------------------------------------===//
995 // SSE 1 & 2 - Move Low packed FP Instructions
996 //===----------------------------------------------------------------------===//
998 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
999 PatFrag mov_frag, string base_opc,
1001 def PSrm : PI<opc, MRMSrcMem,
1002 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1003 !strconcat(base_opc, "s", asm_opr),
1006 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1007 IIC_DEFAULT, SSEPackedSingle>, TB;
1009 def PDrm : PI<opc, MRMSrcMem,
1010 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1011 !strconcat(base_opc, "d", asm_opr),
1012 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
1013 (scalar_to_vector (loadf64 addr:$src2)))))],
1014 IIC_DEFAULT, SSEPackedDouble>, TB, OpSize;
1017 let AddedComplexity = 20 in {
1018 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
1019 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1021 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1022 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
1023 "\t{$src2, $dst|$dst, $src2}">;
1026 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1027 "movlps\t{$src, $dst|$dst, $src}",
1028 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1029 (iPTR 0))), addr:$dst)]>, VEX;
1030 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1031 "movlpd\t{$src, $dst|$dst, $src}",
1032 [(store (f64 (vector_extract (v2f64 VR128:$src),
1033 (iPTR 0))), addr:$dst)]>, VEX;
1034 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1035 "movlps\t{$src, $dst|$dst, $src}",
1036 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1037 (iPTR 0))), addr:$dst)]>;
1038 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1039 "movlpd\t{$src, $dst|$dst, $src}",
1040 [(store (f64 (vector_extract (v2f64 VR128:$src),
1041 (iPTR 0))), addr:$dst)]>;
1043 let Predicates = [HasAVX] in {
1044 let AddedComplexity = 20 in {
1045 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1046 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1047 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1048 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1049 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1050 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1051 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1052 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1053 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1054 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1057 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1058 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1059 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1060 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1061 VR128:$src2)), addr:$src1),
1062 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1064 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1065 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1066 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1067 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1068 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1070 // Shuffle with VMOVLPS
1071 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1072 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1073 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1074 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1075 def : Pat<(X86Movlps VR128:$src1,
1076 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1077 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1079 // Shuffle with VMOVLPD
1080 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1081 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1082 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1083 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1084 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1085 (scalar_to_vector (loadf64 addr:$src2)))),
1086 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1089 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1091 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1092 def : Pat<(store (v4i32 (X86Movlps
1093 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1094 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1095 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1097 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1098 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1100 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1103 let Predicates = [HasSSE1] in {
1104 let AddedComplexity = 20 in {
1105 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1106 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1107 (MOVLPSrm VR128:$src1, addr:$src2)>;
1108 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1109 (MOVLPSrm VR128:$src1, addr:$src2)>;
1112 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1113 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1114 (iPTR 0))), addr:$src1),
1115 (MOVLPSmr addr:$src1, VR128:$src2)>;
1116 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1117 (MOVLPSmr addr:$src1, VR128:$src2)>;
1118 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1119 VR128:$src2)), addr:$src1),
1120 (MOVLPSmr addr:$src1, VR128:$src2)>;
1122 // Shuffle with MOVLPS
1123 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1124 (MOVLPSrm VR128:$src1, addr:$src2)>;
1125 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1126 (MOVLPSrm VR128:$src1, addr:$src2)>;
1127 def : Pat<(X86Movlps VR128:$src1,
1128 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1129 (MOVLPSrm VR128:$src1, addr:$src2)>;
1130 def : Pat<(X86Movlps VR128:$src1,
1131 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1132 (MOVLPSrm VR128:$src1, addr:$src2)>;
1135 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1137 (MOVLPSmr addr:$src1, VR128:$src2)>;
1138 def : Pat<(store (v4i32 (X86Movlps
1139 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1141 (MOVLPSmr addr:$src1, VR128:$src2)>;
1144 let Predicates = [HasSSE2] in {
1145 let AddedComplexity = 20 in {
1146 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1147 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1148 (MOVLPDrm VR128:$src1, addr:$src2)>;
1149 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1150 (MOVLPDrm VR128:$src1, addr:$src2)>;
1153 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1154 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1155 (MOVLPDmr addr:$src1, VR128:$src2)>;
1156 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1157 (MOVLPDmr addr:$src1, VR128:$src2)>;
1159 // Shuffle with MOVLPD
1160 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1161 (MOVLPDrm VR128:$src1, addr:$src2)>;
1162 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1163 (MOVLPDrm VR128:$src1, addr:$src2)>;
1164 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1165 (scalar_to_vector (loadf64 addr:$src2)))),
1166 (MOVLPDrm VR128:$src1, addr:$src2)>;
1169 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1171 (MOVLPDmr addr:$src1, VR128:$src2)>;
1172 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1174 (MOVLPDmr addr:$src1, VR128:$src2)>;
1177 //===----------------------------------------------------------------------===//
1178 // SSE 1 & 2 - Move Hi packed FP Instructions
1179 //===----------------------------------------------------------------------===//
1181 let AddedComplexity = 20 in {
1182 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1183 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1185 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1186 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1187 "\t{$src2, $dst|$dst, $src2}">;
1190 // v2f64 extract element 1 is always custom lowered to unpack high to low
1191 // and extract element 0 so the non-store version isn't too horrible.
1192 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1193 "movhps\t{$src, $dst|$dst, $src}",
1194 [(store (f64 (vector_extract
1195 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1196 (undef)), (iPTR 0))), addr:$dst)]>,
1198 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1199 "movhpd\t{$src, $dst|$dst, $src}",
1200 [(store (f64 (vector_extract
1201 (v2f64 (unpckh VR128:$src, (undef))),
1202 (iPTR 0))), addr:$dst)]>,
1204 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1205 "movhps\t{$src, $dst|$dst, $src}",
1206 [(store (f64 (vector_extract
1207 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1208 (undef)), (iPTR 0))), addr:$dst)]>;
1209 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1210 "movhpd\t{$src, $dst|$dst, $src}",
1211 [(store (f64 (vector_extract
1212 (v2f64 (unpckh VR128:$src, (undef))),
1213 (iPTR 0))), addr:$dst)]>;
1215 let Predicates = [HasAVX] in {
1217 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1218 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1219 def : Pat<(X86Movlhps VR128:$src1,
1220 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1221 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1222 def : Pat<(X86Movlhps VR128:$src1,
1223 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1224 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(X86Movlhps VR128:$src1,
1226 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1227 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1229 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1230 // is during lowering, where it's not possible to recognize the load fold
1231 // cause it has two uses through a bitcast. One use disappears at isel time
1232 // and the fold opportunity reappears.
1233 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1234 (scalar_to_vector (loadf64 addr:$src2)))),
1235 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1237 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1238 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1239 (scalar_to_vector (loadf64 addr:$src2)))),
1240 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1243 def : Pat<(store (f64 (vector_extract
1244 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1245 (bc_v2f64 (v4f32 VR128:$src))), (iPTR 0))), addr:$dst),
1246 (VMOVHPSmr addr:$dst, VR128:$src)>;
1247 def : Pat<(store (f64 (vector_extract
1248 (v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))), addr:$dst),
1249 (VMOVHPDmr addr:$dst, VR128:$src)>;
1252 let Predicates = [HasSSE1] in {
1254 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1255 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1256 def : Pat<(X86Movlhps VR128:$src1,
1257 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1258 (MOVHPSrm VR128:$src1, addr:$src2)>;
1259 def : Pat<(X86Movlhps VR128:$src1,
1260 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1261 (MOVHPSrm VR128:$src1, addr:$src2)>;
1262 def : Pat<(X86Movlhps VR128:$src1,
1263 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1264 (MOVHPSrm VR128:$src1, addr:$src2)>;
1267 def : Pat<(store (f64 (vector_extract
1268 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1269 (bc_v2f64 (v4f32 VR128:$src))), (iPTR 0))), addr:$dst),
1270 (MOVHPSmr addr:$dst, VR128:$src)>;
1273 let Predicates = [HasSSE2] in {
1274 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1275 // is during lowering, where it's not possible to recognize the load fold
1276 // cause it has two uses through a bitcast. One use disappears at isel time
1277 // and the fold opportunity reappears.
1278 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1279 (scalar_to_vector (loadf64 addr:$src2)))),
1280 (MOVHPDrm VR128:$src1, addr:$src2)>;
1282 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1283 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1284 (scalar_to_vector (loadf64 addr:$src2)))),
1285 (MOVHPDrm VR128:$src1, addr:$src2)>;
1288 def : Pat<(store (f64 (vector_extract
1289 (v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))),addr:$dst),
1290 (MOVHPDmr addr:$dst, VR128:$src)>;
1293 //===----------------------------------------------------------------------===//
1294 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1295 //===----------------------------------------------------------------------===//
1297 let AddedComplexity = 20 in {
1298 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1299 (ins VR128:$src1, VR128:$src2),
1300 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1302 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))]>,
1304 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1305 (ins VR128:$src1, VR128:$src2),
1306 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1308 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))]>,
1311 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1312 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1313 (ins VR128:$src1, VR128:$src2),
1314 "movlhps\t{$src2, $dst|$dst, $src2}",
1316 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))]>;
1317 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1318 (ins VR128:$src1, VR128:$src2),
1319 "movhlps\t{$src2, $dst|$dst, $src2}",
1321 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))]>;
1324 let Predicates = [HasAVX] in {
1326 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1327 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1328 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1329 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1332 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1333 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1336 let Predicates = [HasSSE1] in {
1338 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1339 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1340 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1341 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1344 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1345 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1348 //===----------------------------------------------------------------------===//
1349 // SSE 1 & 2 - Conversion Instructions
1350 //===----------------------------------------------------------------------===//
1352 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1353 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1355 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1356 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
1357 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1358 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
1361 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1362 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1363 string asm, Domain d> {
1364 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1365 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1367 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1368 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1372 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1373 X86MemOperand x86memop, string asm> {
1374 let neverHasSideEffects = 1 in {
1375 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1376 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1378 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1379 (ins DstRC:$src1, x86memop:$src),
1380 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1381 } // neverHasSideEffects = 1
1384 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1385 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1387 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1388 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1390 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1391 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX,
1393 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1394 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
1395 VEX, VEX_W, VEX_LIG;
1397 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1398 // register, but the same isn't true when only using memory operands,
1399 // provide other assembly "l" and "q" forms to address this explicitly
1400 // where appropriate to do so.
1401 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
1403 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
1404 VEX_4V, VEX_W, VEX_LIG;
1405 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
1407 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
1409 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
1410 VEX_4V, VEX_W, VEX_LIG;
1412 let Predicates = [HasAVX], AddedComplexity = 1 in {
1413 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1414 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1415 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1416 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1417 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1418 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1419 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1420 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1422 def : Pat<(f32 (sint_to_fp GR32:$src)),
1423 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1424 def : Pat<(f32 (sint_to_fp GR64:$src)),
1425 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1426 def : Pat<(f64 (sint_to_fp GR32:$src)),
1427 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1428 def : Pat<(f64 (sint_to_fp GR64:$src)),
1429 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1432 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1433 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
1434 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1435 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1436 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1437 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
1438 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1439 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1440 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1441 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
1442 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1443 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1444 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1445 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
1446 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1447 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1449 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1450 // and/or XMM operand(s).
1452 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1453 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1455 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1456 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1457 [(set DstRC:$dst, (Int SrcRC:$src))]>;
1458 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1459 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1460 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
1463 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1464 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1465 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
1466 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1468 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1469 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1470 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
1471 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1472 (ins DstRC:$src1, x86memop:$src2),
1474 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1475 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1476 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
1479 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1480 f128mem, load, "cvtsd2si">, XD, VEX, VEX_LIG;
1481 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1482 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
1483 XD, VEX, VEX_W, VEX_LIG;
1485 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1486 f128mem, load, "cvtsd2si{l}">, XD;
1487 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1488 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
1491 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1492 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
1493 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1494 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
1496 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1497 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
1498 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1499 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
1502 let Constraints = "$src1 = $dst" in {
1503 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1504 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1506 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1507 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1508 "cvtsi2ss{q}">, XS, REX_W;
1509 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1510 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1512 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1513 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1514 "cvtsi2sd">, XD, REX_W;
1519 // Aliases for intrinsics
1520 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1521 f32mem, load, "cvttss2si">, XS, VEX;
1522 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1523 int_x86_sse_cvttss2si64, f32mem, load,
1524 "cvttss2si">, XS, VEX, VEX_W;
1525 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1526 f128mem, load, "cvttsd2si">, XD, VEX;
1527 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1528 int_x86_sse2_cvttsd2si64, f128mem, load,
1529 "cvttsd2si">, XD, VEX, VEX_W;
1530 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1531 f32mem, load, "cvttss2si">, XS;
1532 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1533 int_x86_sse_cvttss2si64, f32mem, load,
1534 "cvttss2si{q}">, XS, REX_W;
1535 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1536 f128mem, load, "cvttsd2si">, XD;
1537 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1538 int_x86_sse2_cvttsd2si64, f128mem, load,
1539 "cvttsd2si{q}">, XD, REX_W;
1541 let Pattern = []<dag> in {
1542 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1543 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS,
1545 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1546 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1548 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1549 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1550 SSEPackedSingle>, TB, VEX;
1551 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1552 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1553 SSEPackedSingle>, TB, VEX;
1556 let Pattern = []<dag> in {
1557 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1558 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
1559 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1560 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1561 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1562 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1563 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
1566 let Predicates = [HasAVX] in {
1567 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1568 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1569 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1570 (VCVTSS2SIrm addr:$src)>;
1571 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1572 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1573 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1574 (VCVTSS2SI64rm addr:$src)>;
1577 let Predicates = [HasSSE1] in {
1578 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1579 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1580 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1581 (CVTSS2SIrm addr:$src)>;
1582 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1583 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1584 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1585 (CVTSS2SI64rm addr:$src)>;
1590 // Convert scalar double to scalar single
1591 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1592 (ins FR64:$src1, FR64:$src2),
1593 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1596 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1597 (ins FR64:$src1, f64mem:$src2),
1598 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1599 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1601 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1604 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1605 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1606 [(set FR32:$dst, (fround FR64:$src))]>;
1607 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1608 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1609 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1610 Requires<[HasSSE2, OptForSize]>;
1612 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1613 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1615 let Constraints = "$src1 = $dst" in
1616 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1617 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1619 // Convert scalar single to scalar double
1620 // SSE2 instructions with XS prefix
1621 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1622 (ins FR32:$src1, FR32:$src2),
1623 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1624 []>, XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1626 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1627 (ins FR32:$src1, f32mem:$src2),
1628 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1629 []>, XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1631 let Predicates = [HasAVX] in {
1632 def : Pat<(f64 (fextend FR32:$src)),
1633 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1634 def : Pat<(fextend (loadf32 addr:$src)),
1635 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1636 def : Pat<(extloadf32 addr:$src),
1637 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1640 def : Pat<(extloadf32 addr:$src),
1641 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1642 Requires<[HasAVX, OptForSpeed]>;
1644 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1645 "cvtss2sd\t{$src, $dst|$dst, $src}",
1646 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1647 Requires<[HasSSE2]>;
1648 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1649 "cvtss2sd\t{$src, $dst|$dst, $src}",
1650 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1651 Requires<[HasSSE2, OptForSize]>;
1653 // extload f32 -> f64. This matches load+fextend because we have a hack in
1654 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1656 // Since these loads aren't folded into the fextend, we have to match it
1658 def : Pat<(fextend (loadf32 addr:$src)),
1659 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1660 def : Pat<(extloadf32 addr:$src),
1661 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1663 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1664 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1665 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1666 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1667 VR128:$src2))]>, XS, VEX_4V,
1669 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1670 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1671 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1672 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1673 (load addr:$src2)))]>, XS, VEX_4V,
1675 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1676 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1677 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1678 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1679 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1680 VR128:$src2))]>, XS,
1681 Requires<[HasSSE2]>;
1682 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1683 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1684 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1685 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1686 (load addr:$src2)))]>, XS,
1687 Requires<[HasSSE2]>;
1690 // Convert doubleword to packed single/double fp
1691 // SSE2 instructions without OpSize prefix
1692 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1693 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1694 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1695 TB, VEX, Requires<[HasAVX]>;
1696 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1697 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1698 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1699 (bitconvert (memopv2i64 addr:$src))))]>,
1700 TB, VEX, Requires<[HasAVX]>;
1701 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1702 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1703 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1704 TB, Requires<[HasSSE2]>;
1705 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1706 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1707 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1708 (bitconvert (memopv2i64 addr:$src))))]>,
1709 TB, Requires<[HasSSE2]>;
1711 // FIXME: why the non-intrinsic version is described as SSE3?
1712 // SSE2 instructions with XS prefix
1713 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1714 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1715 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1716 XS, VEX, Requires<[HasAVX]>;
1717 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1718 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1719 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1720 (bitconvert (memopv2i64 addr:$src))))]>,
1721 XS, VEX, Requires<[HasAVX]>;
1722 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1723 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1724 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1725 XS, Requires<[HasSSE2]>;
1726 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1727 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1728 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1729 (bitconvert (memopv2i64 addr:$src))))]>,
1730 XS, Requires<[HasSSE2]>;
1733 // Convert packed single/double fp to doubleword
1734 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1735 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1736 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1737 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1738 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1739 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1740 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1741 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1742 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1743 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1744 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1745 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1747 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1748 "cvtps2dq\t{$src, $dst|$dst, $src}",
1749 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1751 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1753 "cvtps2dq\t{$src, $dst|$dst, $src}",
1754 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1755 (memop addr:$src)))]>, VEX;
1756 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1757 "cvtps2dq\t{$src, $dst|$dst, $src}",
1758 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1759 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1760 "cvtps2dq\t{$src, $dst|$dst, $src}",
1761 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1762 (memop addr:$src)))]>;
1764 // SSE2 packed instructions with XD prefix
1765 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1766 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1767 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1768 XD, VEX, Requires<[HasAVX]>;
1769 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1770 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1771 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1772 (memop addr:$src)))]>,
1773 XD, VEX, Requires<[HasAVX]>;
1774 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1775 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1776 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1777 XD, Requires<[HasSSE2]>;
1778 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1779 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1780 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1781 (memop addr:$src)))]>,
1782 XD, Requires<[HasSSE2]>;
1785 // Convert with truncation packed single/double fp to doubleword
1786 // SSE2 packed instructions with XS prefix
1787 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1788 "cvttps2dq\t{$src, $dst|$dst, $src}",
1790 (int_x86_sse2_cvttps2dq VR128:$src))]>, VEX;
1791 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1792 "cvttps2dq\t{$src, $dst|$dst, $src}",
1793 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1794 (memop addr:$src)))]>, VEX;
1795 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1796 "cvttps2dq\t{$src, $dst|$dst, $src}",
1798 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))]>, VEX;
1799 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1800 "cvttps2dq\t{$src, $dst|$dst, $src}",
1801 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1802 (memopv8f32 addr:$src)))]>, VEX;
1804 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1805 "cvttps2dq\t{$src, $dst|$dst, $src}",
1807 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1808 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1809 "cvttps2dq\t{$src, $dst|$dst, $src}",
1811 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1813 let Predicates = [HasAVX] in {
1814 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1815 (Int_VCVTDQ2PSrr VR128:$src)>;
1816 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1817 (Int_VCVTDQ2PSrm addr:$src)>;
1819 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1820 (VCVTTPS2DQrr VR128:$src)>;
1821 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1822 (VCVTTPS2DQrm addr:$src)>;
1824 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1825 (VCVTDQ2PSYrr VR256:$src)>;
1826 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1827 (VCVTDQ2PSYrm addr:$src)>;
1829 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1830 (VCVTTPS2DQYrr VR256:$src)>;
1831 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1832 (VCVTTPS2DQYrm addr:$src)>;
1835 let Predicates = [HasSSE2] in {
1836 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1837 (Int_CVTDQ2PSrr VR128:$src)>;
1838 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1839 (Int_CVTDQ2PSrm addr:$src)>;
1841 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1842 (CVTTPS2DQrr VR128:$src)>;
1843 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1844 (CVTTPS2DQrm addr:$src)>;
1847 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1848 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1850 (int_x86_sse2_cvttpd2dq VR128:$src))]>, VEX;
1851 let isCodeGenOnly = 1 in
1852 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1853 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1854 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1855 (memop addr:$src)))]>, VEX;
1856 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1857 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1858 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1859 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1860 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1861 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1862 (memop addr:$src)))]>;
1864 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1865 // register, but the same isn't true when using memory operands instead.
1866 // Provide other assembly rr and rm forms to address this explicitly.
1867 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1868 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1871 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1872 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1873 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1874 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1877 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1878 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1879 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1880 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1882 // Convert packed single to packed double
1883 let Predicates = [HasAVX] in {
1884 // SSE2 instructions without OpSize prefix
1885 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1886 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1887 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1888 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1889 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1890 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1891 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1892 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1894 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1895 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1896 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1897 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1899 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1900 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1901 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1902 TB, VEX, Requires<[HasAVX]>;
1903 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1904 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1905 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1906 (load addr:$src)))]>,
1907 TB, VEX, Requires<[HasAVX]>;
1908 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1909 "cvtps2pd\t{$src, $dst|$dst, $src}",
1910 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1911 TB, Requires<[HasSSE2]>;
1912 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1913 "cvtps2pd\t{$src, $dst|$dst, $src}",
1914 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1915 (load addr:$src)))]>,
1916 TB, Requires<[HasSSE2]>;
1918 // Convert packed double to packed single
1919 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1920 // register, but the same isn't true when using memory operands instead.
1921 // Provide other assembly rr and rm forms to address this explicitly.
1922 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1923 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1924 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1925 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1928 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1929 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1930 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1931 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1934 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1935 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1936 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1937 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1938 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1939 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1940 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1941 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1944 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1945 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1946 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1947 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1949 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1950 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1951 (memop addr:$src)))]>;
1952 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1953 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1954 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1955 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1956 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1957 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1958 (memop addr:$src)))]>;
1960 // AVX 256-bit register conversion intrinsics
1961 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1962 // whenever possible to avoid declaring two versions of each one.
1963 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1964 (VCVTDQ2PSYrr VR256:$src)>;
1965 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
1966 (VCVTDQ2PSYrm addr:$src)>;
1968 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1969 (VCVTPD2PSYrr VR256:$src)>;
1970 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1971 (VCVTPD2PSYrm addr:$src)>;
1973 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1974 (VCVTPS2DQYrr VR256:$src)>;
1975 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1976 (VCVTPS2DQYrm addr:$src)>;
1978 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1979 (VCVTPS2PDYrr VR128:$src)>;
1980 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1981 (VCVTPS2PDYrm addr:$src)>;
1983 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1984 (VCVTTPD2DQYrr VR256:$src)>;
1985 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1986 (VCVTTPD2DQYrm addr:$src)>;
1988 // Match fround and fextend for 128/256-bit conversions
1989 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1990 (VCVTPD2PSYrr VR256:$src)>;
1991 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1992 (VCVTPD2PSYrm addr:$src)>;
1994 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1995 (VCVTPS2PDYrr VR128:$src)>;
1996 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1997 (VCVTPS2PDYrm addr:$src)>;
1999 //===----------------------------------------------------------------------===//
2000 // SSE 1 & 2 - Compare Instructions
2001 //===----------------------------------------------------------------------===//
2003 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2004 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2005 SDNode OpNode, ValueType VT, PatFrag ld_frag,
2006 string asm, string asm_alt> {
2007 def rr : SIi8<0xC2, MRMSrcReg,
2008 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2009 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))]>;
2010 def rm : SIi8<0xC2, MRMSrcMem,
2011 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
2012 [(set RC:$dst, (OpNode (VT RC:$src1),
2013 (ld_frag addr:$src2), imm:$cc))]>;
2015 // Accept explicit immediate argument form instead of comparison code.
2016 let neverHasSideEffects = 1 in {
2017 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2018 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, []>;
2020 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2021 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, []>;
2025 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2026 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2027 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2028 XS, VEX_4V, VEX_LIG;
2029 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2030 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2031 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
2032 XD, VEX_4V, VEX_LIG;
2034 let Constraints = "$src1 = $dst" in {
2035 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
2036 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2037 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2039 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2040 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2041 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2045 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
2046 Intrinsic Int, string asm> {
2047 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2048 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
2049 [(set VR128:$dst, (Int VR128:$src1,
2050 VR128:$src, imm:$cc))]>;
2051 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2052 (ins VR128:$src1, x86memop:$src, SSECC:$cc), asm,
2053 [(set VR128:$dst, (Int VR128:$src1,
2054 (load addr:$src), imm:$cc))]>;
2057 // Aliases to match intrinsics which expect XMM operand(s).
2058 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2059 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
2061 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2062 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
2064 let Constraints = "$src1 = $dst" in {
2065 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2066 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
2067 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2068 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
2072 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2073 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2074 ValueType vt, X86MemOperand x86memop,
2075 PatFrag ld_frag, string OpcodeStr, Domain d> {
2076 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2077 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2078 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2080 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2081 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2082 [(set EFLAGS, (OpNode (vt RC:$src1),
2083 (ld_frag addr:$src2)))],
2087 let Defs = [EFLAGS] in {
2088 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2089 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2090 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2091 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2093 let Pattern = []<dag> in {
2094 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2095 "comiss", SSEPackedSingle>, TB, VEX,
2097 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2098 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2102 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2103 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2104 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2105 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2107 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2108 load, "comiss", SSEPackedSingle>, TB, VEX;
2109 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2110 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2111 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2112 "ucomiss", SSEPackedSingle>, TB;
2113 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2114 "ucomisd", SSEPackedDouble>, TB, OpSize;
2116 let Pattern = []<dag> in {
2117 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2118 "comiss", SSEPackedSingle>, TB;
2119 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2120 "comisd", SSEPackedDouble>, TB, OpSize;
2123 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2124 load, "ucomiss", SSEPackedSingle>, TB;
2125 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2126 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2128 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2129 "comiss", SSEPackedSingle>, TB;
2130 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2131 "comisd", SSEPackedDouble>, TB, OpSize;
2132 } // Defs = [EFLAGS]
2134 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
2135 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2136 Intrinsic Int, string asm, string asm_alt,
2138 let isAsmParserOnly = 1 in {
2139 def rri : PIi8<0xC2, MRMSrcReg,
2140 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2141 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2143 def rmi : PIi8<0xC2, MRMSrcMem,
2144 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
2145 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2149 // Accept explicit immediate argument form instead of comparison code.
2150 def rri_alt : PIi8<0xC2, MRMSrcReg,
2151 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2152 asm_alt, [], IIC_DEFAULT, d>;
2153 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2154 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2155 asm_alt, [], IIC_DEFAULT, d>;
2158 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2159 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2160 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2161 SSEPackedSingle>, TB, VEX_4V;
2162 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2163 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2164 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2165 SSEPackedDouble>, TB, OpSize, VEX_4V;
2166 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
2167 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2168 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2169 SSEPackedSingle>, TB, VEX_4V;
2170 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
2171 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2172 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2173 SSEPackedDouble>, TB, OpSize, VEX_4V;
2174 let Constraints = "$src1 = $dst" in {
2175 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2176 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2177 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2178 SSEPackedSingle>, TB;
2179 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2180 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2181 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2182 SSEPackedDouble>, TB, OpSize;
2185 let Predicates = [HasAVX] in {
2186 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2187 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2188 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2189 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2190 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2191 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2192 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2193 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2195 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2196 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2197 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2198 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2199 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2200 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2201 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2202 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2205 let Predicates = [HasSSE1] in {
2206 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2207 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2208 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2209 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2212 let Predicates = [HasSSE2] in {
2213 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2214 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2215 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2216 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2219 //===----------------------------------------------------------------------===//
2220 // SSE 1 & 2 - Shuffle Instructions
2221 //===----------------------------------------------------------------------===//
2223 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2224 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2225 ValueType vt, string asm, PatFrag mem_frag,
2226 Domain d, bit IsConvertibleToThreeAddress = 0> {
2227 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2228 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2229 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2230 (i8 imm:$src3))))], IIC_DEFAULT, d>;
2231 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2232 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2233 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2234 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2235 (i8 imm:$src3))))], IIC_DEFAULT, d>;
2238 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2239 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2240 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2241 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2242 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2243 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2244 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2245 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2246 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2247 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2248 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2249 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2251 let Constraints = "$src1 = $dst" in {
2252 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2253 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2254 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2256 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2257 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2258 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2262 let Predicates = [HasAVX] in {
2263 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2264 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2265 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2266 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2267 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2268 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2269 // fall back to this for SSE1)
2270 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2271 (VSHUFPSrri VR128:$src2, VR128:$src1,
2272 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2274 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2275 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2276 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2277 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2278 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2281 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2282 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2283 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2284 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2285 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2287 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2288 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2289 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2290 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2291 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2294 let Predicates = [HasSSE1] in {
2295 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2296 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2297 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2298 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2299 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2300 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2301 // fall back to this for SSE1)
2302 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2303 (SHUFPSrri VR128:$src2, VR128:$src1,
2304 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2307 let Predicates = [HasSSE2] in {
2308 // Generic SHUFPD patterns
2309 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2310 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2311 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2312 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2313 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2316 //===----------------------------------------------------------------------===//
2317 // SSE 1 & 2 - Unpack Instructions
2318 //===----------------------------------------------------------------------===//
2320 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2321 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
2322 PatFrag mem_frag, RegisterClass RC,
2323 X86MemOperand x86memop, string asm,
2325 def rr : PI<opc, MRMSrcReg,
2326 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2328 (vt (OpNode RC:$src1, RC:$src2)))],
2330 def rm : PI<opc, MRMSrcMem,
2331 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2333 (vt (OpNode RC:$src1,
2334 (mem_frag addr:$src2))))],
2338 let AddedComplexity = 10 in {
2339 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2340 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2341 SSEPackedSingle>, TB, VEX_4V;
2342 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2343 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2344 SSEPackedDouble>, TB, OpSize, VEX_4V;
2345 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2346 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2347 SSEPackedSingle>, TB, VEX_4V;
2348 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2349 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2350 SSEPackedDouble>, TB, OpSize, VEX_4V;
2352 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
2353 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2354 SSEPackedSingle>, TB, VEX_4V;
2355 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
2356 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2357 SSEPackedDouble>, TB, OpSize, VEX_4V;
2358 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
2359 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2360 SSEPackedSingle>, TB, VEX_4V;
2361 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
2362 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2363 SSEPackedDouble>, TB, OpSize, VEX_4V;
2365 let Constraints = "$src1 = $dst" in {
2366 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2367 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2368 SSEPackedSingle>, TB;
2369 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2370 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2371 SSEPackedDouble>, TB, OpSize;
2372 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2373 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2374 SSEPackedSingle>, TB;
2375 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2376 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2377 SSEPackedDouble>, TB, OpSize;
2378 } // Constraints = "$src1 = $dst"
2379 } // AddedComplexity
2381 let Predicates = [HasAVX], AddedComplexity = 1 in {
2382 def : Pat<(v4f32 (X86Unpckl VR128:$src1, (memopv4f32 addr:$src2))),
2383 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
2384 def : Pat<(v4f32 (X86Unpckl VR128:$src1, VR128:$src2)),
2385 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
2386 def : Pat<(v4f32 (X86Unpckh VR128:$src1, (memopv4f32 addr:$src2))),
2387 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
2388 def : Pat<(v4f32 (X86Unpckh VR128:$src1, VR128:$src2)),
2389 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
2391 def : Pat<(v8f32 (X86Unpckl VR256:$src1, (memopv8f32 addr:$src2))),
2392 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2393 def : Pat<(v8f32 (X86Unpckl VR256:$src1, VR256:$src2)),
2394 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2395 def : Pat<(v8f32 (X86Unpckh VR256:$src1, (memopv8f32 addr:$src2))),
2396 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2397 def : Pat<(v8f32 (X86Unpckh VR256:$src1, VR256:$src2)),
2398 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2400 def : Pat<(v2f64 (X86Unpckl VR128:$src1, (memopv2f64 addr:$src2))),
2401 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
2402 def : Pat<(v2f64 (X86Unpckl VR128:$src1, VR128:$src2)),
2403 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
2404 def : Pat<(v2f64 (X86Unpckh VR128:$src1, (memopv2f64 addr:$src2))),
2405 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
2406 def : Pat<(v2f64 (X86Unpckh VR128:$src1, VR128:$src2)),
2407 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
2409 def : Pat<(v4f64 (X86Unpckl VR256:$src1, (memopv4f64 addr:$src2))),
2410 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2411 def : Pat<(v4f64 (X86Unpckl VR256:$src1, VR256:$src2)),
2412 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2413 def : Pat<(v4f64 (X86Unpckh VR256:$src1, (memopv4f64 addr:$src2))),
2414 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2415 def : Pat<(v4f64 (X86Unpckh VR256:$src1, VR256:$src2)),
2416 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2418 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2419 // problem is during lowering, where it's not possible to recognize the load
2420 // fold cause it has two uses through a bitcast. One use disappears at isel
2421 // time and the fold opportunity reappears.
2422 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2423 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2426 let Predicates = [HasSSE1] in {
2427 def : Pat<(v4f32 (X86Unpckl VR128:$src1, (memopv4f32 addr:$src2))),
2428 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
2429 def : Pat<(v4f32 (X86Unpckl VR128:$src1, VR128:$src2)),
2430 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
2431 def : Pat<(v4f32 (X86Unpckh VR128:$src1, (memopv4f32 addr:$src2))),
2432 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
2433 def : Pat<(v4f32 (X86Unpckh VR128:$src1, VR128:$src2)),
2434 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
2437 let Predicates = [HasSSE2] in {
2438 def : Pat<(v2f64 (X86Unpckl VR128:$src1, (memopv2f64 addr:$src2))),
2439 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
2440 def : Pat<(v2f64 (X86Unpckl VR128:$src1, VR128:$src2)),
2441 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
2442 def : Pat<(v2f64 (X86Unpckh VR128:$src1, (memopv2f64 addr:$src2))),
2443 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
2444 def : Pat<(v2f64 (X86Unpckh VR128:$src1, VR128:$src2)),
2445 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
2447 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2448 // problem is during lowering, where it's not possible to recognize the load
2449 // fold cause it has two uses through a bitcast. One use disappears at isel
2450 // time and the fold opportunity reappears.
2451 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2452 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2455 //===----------------------------------------------------------------------===//
2456 // SSE 1 & 2 - Extract Floating-Point Sign mask
2457 //===----------------------------------------------------------------------===//
2459 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2460 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2462 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2463 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2464 [(set GR32:$dst, (Int RC:$src))], IIC_DEFAULT, d>;
2465 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2466 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2467 IIC_DEFAULT, d>, REX_W;
2470 let Predicates = [HasAVX] in {
2471 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2472 "movmskps", SSEPackedSingle>, TB, VEX;
2473 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2474 "movmskpd", SSEPackedDouble>, TB,
2476 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2477 "movmskps", SSEPackedSingle>, TB, VEX;
2478 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2479 "movmskpd", SSEPackedDouble>, TB,
2482 def : Pat<(i32 (X86fgetsign FR32:$src)),
2483 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2485 def : Pat<(i64 (X86fgetsign FR32:$src)),
2486 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2488 def : Pat<(i32 (X86fgetsign FR64:$src)),
2489 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2491 def : Pat<(i64 (X86fgetsign FR64:$src)),
2492 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2496 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2497 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2498 SSEPackedSingle>, TB, VEX;
2499 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2500 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2501 SSEPackedDouble>, TB,
2503 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2504 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2505 SSEPackedSingle>, TB, VEX;
2506 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2507 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_DEFAULT,
2508 SSEPackedDouble>, TB,
2512 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2513 SSEPackedSingle>, TB;
2514 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2515 SSEPackedDouble>, TB, OpSize;
2517 def : Pat<(i32 (X86fgetsign FR32:$src)),
2518 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2519 sub_ss))>, Requires<[HasSSE1]>;
2520 def : Pat<(i64 (X86fgetsign FR32:$src)),
2521 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2522 sub_ss))>, Requires<[HasSSE1]>;
2523 def : Pat<(i32 (X86fgetsign FR64:$src)),
2524 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2525 sub_sd))>, Requires<[HasSSE2]>;
2526 def : Pat<(i64 (X86fgetsign FR64:$src)),
2527 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2528 sub_sd))>, Requires<[HasSSE2]>;
2530 //===---------------------------------------------------------------------===//
2531 // SSE2 - Packed Integer Logical Instructions
2532 //===---------------------------------------------------------------------===//
2534 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2536 /// PDI_binop_rm - Simple SSE2 binary operator.
2537 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2538 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2539 X86MemOperand x86memop, bit IsCommutable = 0,
2541 let isCommutable = IsCommutable in
2542 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2543 (ins RC:$src1, RC:$src2),
2545 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2546 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2547 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
2548 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2549 (ins RC:$src1, x86memop:$src2),
2551 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2552 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2553 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2554 (bitconvert (memop_frag addr:$src2)))))]>;
2556 } // ExeDomain = SSEPackedInt
2558 // These are ordered here for pattern ordering requirements with the fp versions
2560 let Predicates = [HasAVX] in {
2561 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2562 i128mem, 1, 0>, VEX_4V;
2563 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2564 i128mem, 1, 0>, VEX_4V;
2565 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2566 i128mem, 1, 0>, VEX_4V;
2567 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2568 i128mem, 0, 0>, VEX_4V;
2571 let Constraints = "$src1 = $dst" in {
2572 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2574 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2576 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2578 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2580 } // Constraints = "$src1 = $dst"
2582 let Predicates = [HasAVX2] in {
2583 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2584 i256mem, 1, 0>, VEX_4V;
2585 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2586 i256mem, 1, 0>, VEX_4V;
2587 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2588 i256mem, 1, 0>, VEX_4V;
2589 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2590 i256mem, 0, 0>, VEX_4V;
2593 //===----------------------------------------------------------------------===//
2594 // SSE 1 & 2 - Logical Instructions
2595 //===----------------------------------------------------------------------===//
2597 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2599 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2601 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2602 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2604 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2605 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2607 let Constraints = "$src1 = $dst" in {
2608 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2609 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2611 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2612 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2616 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2617 let mayLoad = 0 in {
2618 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2619 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2620 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2623 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2624 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2626 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2628 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2630 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2631 // are all promoted to v2i64, and the patterns are covered by the int
2632 // version. This is needed in SSE only, because v2i64 isn't supported on
2633 // SSE1, but only on SSE2.
2634 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2635 !strconcat(OpcodeStr, "ps"), f128mem, [],
2636 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2637 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2639 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2640 !strconcat(OpcodeStr, "pd"), f128mem,
2641 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2642 (bc_v2i64 (v2f64 VR128:$src2))))],
2643 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2644 (memopv2i64 addr:$src2)))], 0>,
2646 let Constraints = "$src1 = $dst" in {
2647 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2648 !strconcat(OpcodeStr, "ps"), f128mem,
2649 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2650 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2651 (memopv2i64 addr:$src2)))]>, TB;
2653 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2654 !strconcat(OpcodeStr, "pd"), f128mem,
2655 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2656 (bc_v2i64 (v2f64 VR128:$src2))))],
2657 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2658 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2662 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2664 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2666 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2667 !strconcat(OpcodeStr, "ps"), f256mem,
2668 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2669 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2670 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2672 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2673 !strconcat(OpcodeStr, "pd"), f256mem,
2674 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2675 (bc_v4i64 (v4f64 VR256:$src2))))],
2676 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2677 (memopv4i64 addr:$src2)))], 0>,
2681 // AVX 256-bit packed logical ops forms
2682 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2683 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2684 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2685 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2687 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2688 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2689 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2690 let isCommutable = 0 in
2691 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2693 //===----------------------------------------------------------------------===//
2694 // SSE 1 & 2 - Arithmetic Instructions
2695 //===----------------------------------------------------------------------===//
2697 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2700 /// In addition, we also have a special variant of the scalar form here to
2701 /// represent the associated intrinsic operation. This form is unlike the
2702 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2703 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2705 /// These three forms can each be reg+reg or reg+mem.
2708 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2710 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2712 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2713 OpNode, FR32, f32mem, Is2Addr>, XS;
2714 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2715 OpNode, FR64, f64mem, Is2Addr>, XD;
2718 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2720 let mayLoad = 0 in {
2721 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2722 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2723 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2724 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2728 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2730 let mayLoad = 0 in {
2731 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2732 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2733 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2734 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2738 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2740 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2741 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2742 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2743 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2746 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2748 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2749 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2750 SSEPackedSingle, Is2Addr>, TB;
2752 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2753 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2754 SSEPackedDouble, Is2Addr>, TB, OpSize;
2757 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2758 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2759 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2760 SSEPackedSingle, 0>, TB;
2762 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2763 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2764 SSEPackedDouble, 0>, TB, OpSize;
2767 // Binary Arithmetic instructions
2768 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2769 basic_sse12_fp_binop_s_int<0x58, "add", 0>, VEX_4V, VEX_LIG;
2770 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2771 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2772 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2773 basic_sse12_fp_binop_s_int<0x59, "mul", 0>, VEX_4V, VEX_LIG;
2774 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2775 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2777 let isCommutable = 0 in {
2778 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2779 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>, VEX_4V, VEX_LIG;
2780 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2781 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2782 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2783 basic_sse12_fp_binop_s_int<0x5E, "div", 0>, VEX_4V, VEX_LIG;
2784 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2785 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2786 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2787 basic_sse12_fp_binop_s_int<0x5F, "max", 0>, VEX_4V, VEX_LIG;
2788 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2789 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2790 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2791 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2792 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2793 basic_sse12_fp_binop_s_int<0x5D, "min", 0>, VEX_4V, VEX_LIG;
2794 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2795 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2796 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2797 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2800 let Constraints = "$src1 = $dst" in {
2801 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2802 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2803 basic_sse12_fp_binop_s_int<0x58, "add">;
2804 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2805 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2806 basic_sse12_fp_binop_s_int<0x59, "mul">;
2808 let isCommutable = 0 in {
2809 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2810 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2811 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2812 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2813 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2814 basic_sse12_fp_binop_s_int<0x5E, "div">;
2815 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2816 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2817 basic_sse12_fp_binop_s_int<0x5F, "max">,
2818 basic_sse12_fp_binop_p_int<0x5F, "max">;
2819 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2820 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2821 basic_sse12_fp_binop_s_int<0x5D, "min">,
2822 basic_sse12_fp_binop_p_int<0x5D, "min">;
2827 /// In addition, we also have a special variant of the scalar form here to
2828 /// represent the associated intrinsic operation. This form is unlike the
2829 /// plain scalar form, in that it takes an entire vector (instead of a
2830 /// scalar) and leaves the top elements undefined.
2832 /// And, we have a special variant form for a full-vector intrinsic form.
2834 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2835 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2836 SDNode OpNode, Intrinsic F32Int> {
2837 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2838 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2839 [(set FR32:$dst, (OpNode FR32:$src))]>;
2840 // For scalar unary operations, fold a load into the operation
2841 // only in OptForSize mode. It eliminates an instruction, but it also
2842 // eliminates a whole-register clobber (the load), so it introduces a
2843 // partial register update condition.
2844 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2845 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2846 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2847 Requires<[HasSSE1, OptForSize]>;
2848 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2849 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2850 [(set VR128:$dst, (F32Int VR128:$src))]>;
2851 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2852 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2853 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2856 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2857 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2858 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2859 !strconcat(OpcodeStr,
2860 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2862 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2863 !strconcat(OpcodeStr,
2864 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2865 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2866 (ins VR128:$src1, ssmem:$src2),
2867 !strconcat(OpcodeStr,
2868 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2871 /// sse1_fp_unop_p - SSE1 unops in packed form.
2872 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2873 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2874 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2875 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2876 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2877 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2878 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2881 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2882 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2883 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2884 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2885 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2886 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2887 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2888 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2891 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2892 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2893 Intrinsic V4F32Int> {
2894 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2895 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2896 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2897 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2898 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2899 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2902 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2903 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2904 Intrinsic V4F32Int> {
2905 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2906 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2907 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2908 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2909 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2910 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2913 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2914 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2915 SDNode OpNode, Intrinsic F64Int> {
2916 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2917 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2918 [(set FR64:$dst, (OpNode FR64:$src))]>;
2919 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2920 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2921 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2922 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2923 Requires<[HasSSE2, OptForSize]>;
2924 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2925 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2926 [(set VR128:$dst, (F64Int VR128:$src))]>;
2927 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2928 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2929 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2932 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2933 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2934 let neverHasSideEffects = 1 in {
2935 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2936 !strconcat(OpcodeStr,
2937 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2939 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2940 !strconcat(OpcodeStr,
2941 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2943 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2944 (ins VR128:$src1, sdmem:$src2),
2945 !strconcat(OpcodeStr,
2946 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2949 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2950 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2952 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2953 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2954 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2955 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2956 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2957 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2960 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2961 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2962 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2963 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2964 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2965 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2966 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2967 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2970 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2971 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2972 Intrinsic V2F64Int> {
2973 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2974 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2975 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2976 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2977 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2978 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2981 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2982 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2983 Intrinsic V2F64Int> {
2984 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2985 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2986 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2987 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2988 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2989 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2992 let Predicates = [HasAVX] in {
2994 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
2995 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
2997 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
2998 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
2999 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
3000 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
3001 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
3002 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
3003 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
3004 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
3007 // Reciprocal approximations. Note that these typically require refinement
3008 // in order to obtain suitable precision.
3009 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3010 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
3011 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
3012 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
3013 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
3015 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3016 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
3017 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
3018 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
3019 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
3022 let AddedComplexity = 1 in {
3023 def : Pat<(f32 (fsqrt FR32:$src)),
3024 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3025 def : Pat<(f32 (fsqrt (load addr:$src))),
3026 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3027 Requires<[HasAVX, OptForSize]>;
3028 def : Pat<(f64 (fsqrt FR64:$src)),
3029 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3030 def : Pat<(f64 (fsqrt (load addr:$src))),
3031 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3032 Requires<[HasAVX, OptForSize]>;
3034 def : Pat<(f32 (X86frsqrt FR32:$src)),
3035 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3036 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3037 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3038 Requires<[HasAVX, OptForSize]>;
3040 def : Pat<(f32 (X86frcp FR32:$src)),
3041 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3042 def : Pat<(f32 (X86frcp (load addr:$src))),
3043 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3044 Requires<[HasAVX, OptForSize]>;
3047 let Predicates = [HasAVX], AddedComplexity = 1 in {
3048 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3049 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3050 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3051 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3053 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3054 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3056 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3057 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3058 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3059 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3061 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3062 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3064 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3065 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3066 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3067 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3069 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3070 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3072 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3073 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3074 (VRCPSSr (f32 (IMPLICIT_DEF)),
3075 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3077 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3078 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3082 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
3083 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
3084 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
3085 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
3086 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
3087 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
3089 // Reciprocal approximations. Note that these typically require refinement
3090 // in order to obtain suitable precision.
3091 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
3092 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
3093 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
3094 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
3095 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
3096 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
3098 // There is no f64 version of the reciprocal approximation instructions.
3100 //===----------------------------------------------------------------------===//
3101 // SSE 1 & 2 - Non-temporal stores
3102 //===----------------------------------------------------------------------===//
3104 let AddedComplexity = 400 in { // Prefer non-temporal versions
3105 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3106 (ins f128mem:$dst, VR128:$src),
3107 "movntps\t{$src, $dst|$dst, $src}",
3108 [(alignednontemporalstore (v4f32 VR128:$src),
3110 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3111 (ins f128mem:$dst, VR128:$src),
3112 "movntpd\t{$src, $dst|$dst, $src}",
3113 [(alignednontemporalstore (v2f64 VR128:$src),
3116 let ExeDomain = SSEPackedInt in
3117 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3118 (ins f128mem:$dst, VR128:$src),
3119 "movntdq\t{$src, $dst|$dst, $src}",
3120 [(alignednontemporalstore (v2i64 VR128:$src),
3123 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3124 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3126 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3127 (ins f256mem:$dst, VR256:$src),
3128 "movntps\t{$src, $dst|$dst, $src}",
3129 [(alignednontemporalstore (v8f32 VR256:$src),
3131 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3132 (ins f256mem:$dst, VR256:$src),
3133 "movntpd\t{$src, $dst|$dst, $src}",
3134 [(alignednontemporalstore (v4f64 VR256:$src),
3136 let ExeDomain = SSEPackedInt in
3137 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3138 (ins f256mem:$dst, VR256:$src),
3139 "movntdq\t{$src, $dst|$dst, $src}",
3140 [(alignednontemporalstore (v4i64 VR256:$src),
3144 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
3145 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3146 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
3147 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
3148 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
3149 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
3151 let AddedComplexity = 400 in { // Prefer non-temporal versions
3152 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3153 "movntps\t{$src, $dst|$dst, $src}",
3154 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3155 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3156 "movntpd\t{$src, $dst|$dst, $src}",
3157 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
3159 let ExeDomain = SSEPackedInt in
3160 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3161 "movntdq\t{$src, $dst|$dst, $src}",
3162 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)]>;
3164 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3165 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3167 // There is no AVX form for instructions below this point
3168 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3169 "movnti{l}\t{$src, $dst|$dst, $src}",
3170 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
3171 TB, Requires<[HasSSE2]>;
3172 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3173 "movnti{q}\t{$src, $dst|$dst, $src}",
3174 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
3175 TB, Requires<[HasSSE2]>;
3178 //===----------------------------------------------------------------------===//
3179 // SSE 1 & 2 - Prefetch and memory fence
3180 //===----------------------------------------------------------------------===//
3182 // Prefetch intrinsic.
3183 let Predicates = [HasSSE1] in {
3184 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3185 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>, TB;
3186 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3187 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>, TB;
3188 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3189 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>, TB;
3190 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3191 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>, TB;
3195 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3196 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3197 TB, Requires<[HasSSE2]>;
3199 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3200 // was introduced with SSE2, it's backward compatible.
3201 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3203 // Load, store, and memory fence
3204 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3205 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
3206 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3207 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3208 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3209 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3211 def : Pat<(X86SFence), (SFENCE)>;
3212 def : Pat<(X86LFence), (LFENCE)>;
3213 def : Pat<(X86MFence), (MFENCE)>;
3215 //===----------------------------------------------------------------------===//
3216 // SSE 1 & 2 - Load/Store XCSR register
3217 //===----------------------------------------------------------------------===//
3219 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3220 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
3221 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3222 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
3224 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3225 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
3226 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3227 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
3229 //===---------------------------------------------------------------------===//
3230 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3231 //===---------------------------------------------------------------------===//
3233 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3235 let neverHasSideEffects = 1 in {
3236 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3237 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3238 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3239 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3241 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3242 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3243 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3244 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3247 let isCodeGenOnly = 1 in {
3248 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3249 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3250 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3251 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3252 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3253 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3254 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3255 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3258 let canFoldAsLoad = 1, mayLoad = 1 in {
3259 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3260 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3261 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3262 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3263 let Predicates = [HasAVX] in {
3264 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3265 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3266 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3267 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3271 let mayStore = 1 in {
3272 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3273 (ins i128mem:$dst, VR128:$src),
3274 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3275 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3276 (ins i256mem:$dst, VR256:$src),
3277 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3278 let Predicates = [HasAVX] in {
3279 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3280 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3281 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3282 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3286 let neverHasSideEffects = 1 in
3287 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3288 "movdqa\t{$src, $dst|$dst, $src}", []>;
3290 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3291 "movdqu\t{$src, $dst|$dst, $src}",
3292 []>, XS, Requires<[HasSSE2]>;
3295 let isCodeGenOnly = 1 in {
3296 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3297 "movdqa\t{$src, $dst|$dst, $src}", []>;
3299 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3300 "movdqu\t{$src, $dst|$dst, $src}",
3301 []>, XS, Requires<[HasSSE2]>;
3304 let canFoldAsLoad = 1, mayLoad = 1 in {
3305 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3306 "movdqa\t{$src, $dst|$dst, $src}",
3307 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
3308 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3309 "movdqu\t{$src, $dst|$dst, $src}",
3310 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
3311 XS, Requires<[HasSSE2]>;
3314 let mayStore = 1 in {
3315 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3316 "movdqa\t{$src, $dst|$dst, $src}",
3317 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
3318 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3319 "movdqu\t{$src, $dst|$dst, $src}",
3320 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
3321 XS, Requires<[HasSSE2]>;
3324 // Intrinsic forms of MOVDQU load and store
3325 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3326 "vmovdqu\t{$src, $dst|$dst, $src}",
3327 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3328 XS, VEX, Requires<[HasAVX]>;
3330 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3331 "movdqu\t{$src, $dst|$dst, $src}",
3332 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3333 XS, Requires<[HasSSE2]>;
3335 } // ExeDomain = SSEPackedInt
3337 let Predicates = [HasAVX] in {
3338 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3339 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3342 //===---------------------------------------------------------------------===//
3343 // SSE2 - Packed Integer Arithmetic Instructions
3344 //===---------------------------------------------------------------------===//
3346 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3348 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3349 RegisterClass RC, PatFrag memop_frag,
3350 X86MemOperand x86memop, bit IsCommutable = 0,
3352 let isCommutable = IsCommutable in
3353 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3354 (ins RC:$src1, RC:$src2),
3356 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3357 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3358 [(set RC:$dst, (IntId RC:$src1, RC:$src2))]>;
3359 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3360 (ins RC:$src1, x86memop:$src2),
3362 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3363 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3364 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))]>;
3367 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3368 string OpcodeStr, SDNode OpNode,
3369 SDNode OpNode2, RegisterClass RC,
3370 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3372 // src2 is always 128-bit
3373 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3374 (ins RC:$src1, VR128:$src2),
3376 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3377 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3378 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))]>;
3379 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3380 (ins RC:$src1, i128mem:$src2),
3382 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3383 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3384 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3385 (bc_frag (memopv2i64 addr:$src2)))))]>;
3386 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3387 (ins RC:$src1, i32i8imm:$src2),
3389 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3390 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3391 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))]>;
3394 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3395 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3396 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3397 PatFrag memop_frag, X86MemOperand x86memop,
3398 bit IsCommutable = 0, bit Is2Addr = 1> {
3399 let isCommutable = IsCommutable in
3400 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3401 (ins RC:$src1, RC:$src2),
3403 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3404 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3405 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3406 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3407 (ins RC:$src1, x86memop:$src2),
3409 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3410 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3411 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3412 (bitconvert (memop_frag addr:$src2)))))]>;
3414 } // ExeDomain = SSEPackedInt
3416 // 128-bit Integer Arithmetic
3418 let Predicates = [HasAVX] in {
3419 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3420 i128mem, 1, 0 /*3addr*/>, VEX_4V;
3421 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3422 i128mem, 1, 0>, VEX_4V;
3423 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3424 i128mem, 1, 0>, VEX_4V;
3425 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3426 i128mem, 1, 0>, VEX_4V;
3427 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3428 i128mem, 1, 0>, VEX_4V;
3429 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3430 i128mem, 0, 0>, VEX_4V;
3431 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3432 i128mem, 0, 0>, VEX_4V;
3433 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3434 i128mem, 0, 0>, VEX_4V;
3435 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3436 i128mem, 0, 0>, VEX_4V;
3437 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3438 memopv2i64, i128mem, 1, 0>, VEX_4V;
3441 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3442 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3443 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3444 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3445 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3446 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3447 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3448 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3449 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3450 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3451 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3452 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3453 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3454 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3455 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3456 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3457 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3458 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3459 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3460 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3461 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3462 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3463 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3464 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3465 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3466 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3467 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3468 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3469 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3470 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3471 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3472 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3473 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3474 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3475 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3476 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3479 let Predicates = [HasAVX2] in {
3480 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3481 i256mem, 1, 0>, VEX_4V;
3482 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3483 i256mem, 1, 0>, VEX_4V;
3484 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3485 i256mem, 1, 0>, VEX_4V;
3486 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3487 i256mem, 1, 0>, VEX_4V;
3488 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3489 i256mem, 1, 0>, VEX_4V;
3490 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3491 i256mem, 0, 0>, VEX_4V;
3492 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3493 i256mem, 0, 0>, VEX_4V;
3494 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3495 i256mem, 0, 0>, VEX_4V;
3496 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3497 i256mem, 0, 0>, VEX_4V;
3498 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3499 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3502 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3503 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3504 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3505 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3506 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3507 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3508 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3509 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3510 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3511 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3512 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3513 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3514 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3515 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3516 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3517 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3518 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3519 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3520 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3521 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3522 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3523 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3524 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3525 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3526 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3527 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3528 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3529 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3530 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3531 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3532 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3533 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3534 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3535 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3536 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3537 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3540 let Constraints = "$src1 = $dst" in {
3541 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3543 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3545 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3547 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3549 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3551 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3553 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3555 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3557 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3559 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3560 memopv2i64, i128mem, 1>;
3563 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3564 VR128, memopv2i64, i128mem>;
3565 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3566 VR128, memopv2i64, i128mem>;
3567 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3568 VR128, memopv2i64, i128mem>;
3569 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3570 VR128, memopv2i64, i128mem>;
3571 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3572 VR128, memopv2i64, i128mem, 1>;
3573 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3574 VR128, memopv2i64, i128mem, 1>;
3575 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3576 VR128, memopv2i64, i128mem, 1>;
3577 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3578 VR128, memopv2i64, i128mem, 1>;
3579 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3580 VR128, memopv2i64, i128mem, 1>;
3581 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3582 VR128, memopv2i64, i128mem, 1>;
3583 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3584 VR128, memopv2i64, i128mem, 1>;
3585 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3586 VR128, memopv2i64, i128mem, 1>;
3587 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3588 VR128, memopv2i64, i128mem, 1>;
3589 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3590 VR128, memopv2i64, i128mem, 1>;
3591 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3592 VR128, memopv2i64, i128mem, 1>;
3593 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3594 VR128, memopv2i64, i128mem, 1>;
3595 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3596 VR128, memopv2i64, i128mem, 1>;
3597 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3598 VR128, memopv2i64, i128mem, 1>;
3600 } // Constraints = "$src1 = $dst"
3602 //===---------------------------------------------------------------------===//
3603 // SSE2 - Packed Integer Logical Instructions
3604 //===---------------------------------------------------------------------===//
3606 let Predicates = [HasAVX] in {
3607 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3608 VR128, v8i16, v8i16, bc_v8i16, 0>, VEX_4V;
3609 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3610 VR128, v4i32, v4i32, bc_v4i32, 0>, VEX_4V;
3611 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3612 VR128, v2i64, v2i64, bc_v2i64, 0>, VEX_4V;
3614 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3615 VR128, v8i16, v8i16, bc_v8i16, 0>, VEX_4V;
3616 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3617 VR128, v4i32, v4i32, bc_v4i32, 0>, VEX_4V;
3618 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3619 VR128, v2i64, v2i64, bc_v2i64, 0>, VEX_4V;
3621 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3622 VR128, v8i16, v8i16, bc_v8i16, 0>, VEX_4V;
3623 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3624 VR128, v4i32, v4i32, bc_v4i32, 0>, VEX_4V;
3626 let ExeDomain = SSEPackedInt in {
3627 // 128-bit logical shifts.
3628 def VPSLLDQri : PDIi8<0x73, MRM7r,
3629 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3630 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3632 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3634 def VPSRLDQri : PDIi8<0x73, MRM3r,
3635 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3636 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3638 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3640 // PSRADQri doesn't exist in SSE[1-3].
3642 } // Predicates = [HasAVX]
3644 let Predicates = [HasAVX2] in {
3645 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3646 VR256, v16i16, v8i16, bc_v8i16, 0>, VEX_4V;
3647 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3648 VR256, v8i32, v4i32, bc_v4i32, 0>, VEX_4V;
3649 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3650 VR256, v4i64, v2i64, bc_v2i64, 0>, VEX_4V;
3652 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3653 VR256, v16i16, v8i16, bc_v8i16, 0>, VEX_4V;
3654 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3655 VR256, v8i32, v4i32, bc_v4i32, 0>, VEX_4V;
3656 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3657 VR256, v4i64, v2i64, bc_v2i64, 0>, VEX_4V;
3659 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3660 VR256, v16i16, v8i16, bc_v8i16, 0>, VEX_4V;
3661 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3662 VR256, v8i32, v4i32, bc_v4i32, 0>, VEX_4V;
3664 let ExeDomain = SSEPackedInt in {
3665 // 256-bit logical shifts.
3666 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3667 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3668 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3670 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3672 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3673 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3674 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3676 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3678 // PSRADQYri doesn't exist in SSE[1-3].
3680 } // Predicates = [HasAVX2]
3682 let Constraints = "$src1 = $dst" in {
3683 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3684 VR128, v8i16, v8i16, bc_v8i16>;
3685 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3686 VR128, v4i32, v4i32, bc_v4i32>;
3687 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3688 VR128, v2i64, v2i64, bc_v2i64>;
3690 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3691 VR128, v8i16, v8i16, bc_v8i16>;
3692 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3693 VR128, v4i32, v4i32, bc_v4i32>;
3694 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3695 VR128, v2i64, v2i64, bc_v2i64>;
3697 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3698 VR128, v8i16, v8i16, bc_v8i16>;
3699 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3700 VR128, v4i32, v4i32, bc_v4i32>;
3702 let ExeDomain = SSEPackedInt in {
3703 // 128-bit logical shifts.
3704 def PSLLDQri : PDIi8<0x73, MRM7r,
3705 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3706 "pslldq\t{$src2, $dst|$dst, $src2}",
3708 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
3709 def PSRLDQri : PDIi8<0x73, MRM3r,
3710 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3711 "psrldq\t{$src2, $dst|$dst, $src2}",
3713 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
3714 // PSRADQri doesn't exist in SSE[1-3].
3716 } // Constraints = "$src1 = $dst"
3718 let Predicates = [HasAVX] in {
3719 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3720 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3721 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3722 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3723 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3724 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3726 // Shift up / down and insert zero's.
3727 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
3728 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3729 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
3730 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3733 let Predicates = [HasAVX2] in {
3734 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
3735 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3736 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
3737 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
3740 let Predicates = [HasSSE2] in {
3741 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3742 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3743 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3744 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3745 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3746 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
3748 // Shift up / down and insert zero's.
3749 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
3750 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3751 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
3752 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
3755 //===---------------------------------------------------------------------===//
3756 // SSE2 - Packed Integer Comparison Instructions
3757 //===---------------------------------------------------------------------===//
3759 let Predicates = [HasAVX] in {
3760 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
3761 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3762 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
3763 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3764 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
3765 VR128, memopv2i64, i128mem, 1, 0>, VEX_4V;
3766 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
3767 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3768 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
3769 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3770 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
3771 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3774 let Predicates = [HasAVX2] in {
3775 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
3776 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3777 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
3778 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3779 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
3780 VR256, memopv4i64, i256mem, 1, 0>, VEX_4V;
3781 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
3782 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3783 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
3784 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3785 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
3786 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3789 let Constraints = "$src1 = $dst" in {
3790 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
3791 VR128, memopv2i64, i128mem, 1>;
3792 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
3793 VR128, memopv2i64, i128mem, 1>;
3794 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
3795 VR128, memopv2i64, i128mem, 1>;
3796 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
3797 VR128, memopv2i64, i128mem>;
3798 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
3799 VR128, memopv2i64, i128mem>;
3800 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
3801 VR128, memopv2i64, i128mem>;
3802 } // Constraints = "$src1 = $dst"
3804 //===---------------------------------------------------------------------===//
3805 // SSE2 - Packed Integer Pack Instructions
3806 //===---------------------------------------------------------------------===//
3808 let Predicates = [HasAVX] in {
3809 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
3810 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3811 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
3812 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3813 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
3814 VR128, memopv2i64, i128mem, 0, 0>, VEX_4V;
3817 let Predicates = [HasAVX2] in {
3818 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
3819 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3820 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
3821 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3822 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
3823 VR256, memopv4i64, i256mem, 0, 0>, VEX_4V;
3826 let Constraints = "$src1 = $dst" in {
3827 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
3828 VR128, memopv2i64, i128mem>;
3829 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
3830 VR128, memopv2i64, i128mem>;
3831 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
3832 VR128, memopv2i64, i128mem>;
3833 } // Constraints = "$src1 = $dst"
3835 //===---------------------------------------------------------------------===//
3836 // SSE2 - Packed Integer Shuffle Instructions
3837 //===---------------------------------------------------------------------===//
3839 let ExeDomain = SSEPackedInt in {
3840 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
3841 def ri : Ii8<0x70, MRMSrcReg,
3842 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3843 !strconcat(OpcodeStr,
3844 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3845 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))]>;
3846 def mi : Ii8<0x70, MRMSrcMem,
3847 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
3848 !strconcat(OpcodeStr,
3849 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3851 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
3852 (i8 imm:$src2))))]>;
3855 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
3856 def Yri : Ii8<0x70, MRMSrcReg,
3857 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
3858 !strconcat(OpcodeStr,
3859 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3860 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
3861 def Ymi : Ii8<0x70, MRMSrcMem,
3862 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
3863 !strconcat(OpcodeStr,
3864 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3866 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
3867 (i8 imm:$src2))))]>;
3869 } // ExeDomain = SSEPackedInt
3871 let Predicates = [HasAVX] in {
3872 let AddedComplexity = 5 in
3873 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
3875 // SSE2 with ImmT == Imm8 and XS prefix.
3876 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
3878 // SSE2 with ImmT == Imm8 and XD prefix.
3879 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
3881 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
3882 (VPSHUFDmi addr:$src1, imm:$imm)>;
3883 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3884 (VPSHUFDri VR128:$src1, imm:$imm)>;
3887 let Predicates = [HasAVX2] in {
3888 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
3889 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>, XS, VEX;
3890 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>, XD, VEX;
3893 let Predicates = [HasSSE2] in {
3894 let AddedComplexity = 5 in
3895 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
3897 // SSE2 with ImmT == Imm8 and XS prefix.
3898 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
3900 // SSE2 with ImmT == Imm8 and XD prefix.
3901 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
3903 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
3904 (PSHUFDmi addr:$src1, imm:$imm)>;
3905 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3906 (PSHUFDri VR128:$src1, imm:$imm)>;
3909 //===---------------------------------------------------------------------===//
3910 // SSE2 - Packed Integer Unpack Instructions
3911 //===---------------------------------------------------------------------===//
3913 let ExeDomain = SSEPackedInt in {
3914 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
3915 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
3916 def rr : PDI<opc, MRMSrcReg,
3917 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3919 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3920 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3921 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
3922 def rm : PDI<opc, MRMSrcMem,
3923 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3925 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3926 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3927 [(set VR128:$dst, (OpNode VR128:$src1,
3928 (bc_frag (memopv2i64
3932 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
3933 SDNode OpNode, PatFrag bc_frag> {
3934 def Yrr : PDI<opc, MRMSrcReg,
3935 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
3936 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3937 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
3938 def Yrm : PDI<opc, MRMSrcMem,
3939 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
3940 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3941 [(set VR256:$dst, (OpNode VR256:$src1,
3942 (bc_frag (memopv4i64 addr:$src2))))]>;
3945 let Predicates = [HasAVX] in {
3946 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
3947 bc_v16i8, 0>, VEX_4V;
3948 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
3949 bc_v8i16, 0>, VEX_4V;
3950 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
3951 bc_v4i32, 0>, VEX_4V;
3952 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
3953 bc_v2i64, 0>, VEX_4V;
3955 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
3956 bc_v16i8, 0>, VEX_4V;
3957 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
3958 bc_v8i16, 0>, VEX_4V;
3959 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
3960 bc_v4i32, 0>, VEX_4V;
3961 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
3962 bc_v2i64, 0>, VEX_4V;
3965 let Predicates = [HasAVX2] in {
3966 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
3968 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
3970 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
3972 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
3975 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
3977 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
3979 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
3981 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
3985 let Constraints = "$src1 = $dst" in {
3986 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
3988 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
3990 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
3992 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
3995 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
3997 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
3999 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4001 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4004 } // ExeDomain = SSEPackedInt
4006 // Patterns for using AVX1 instructions with integer vectors
4007 // Here to give AVX2 priority
4008 let Predicates = [HasAVX] in {
4009 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4010 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
4011 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
4012 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
4013 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4014 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
4015 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
4016 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
4018 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
4019 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
4020 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
4021 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
4022 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
4023 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
4024 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
4025 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
4028 //===---------------------------------------------------------------------===//
4029 // SSE2 - Packed Integer Extract and Insert
4030 //===---------------------------------------------------------------------===//
4032 let ExeDomain = SSEPackedInt in {
4033 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4034 def rri : Ii8<0xC4, MRMSrcReg,
4035 (outs VR128:$dst), (ins VR128:$src1,
4036 GR32:$src2, i32i8imm:$src3),
4038 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4039 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4041 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
4042 def rmi : Ii8<0xC4, MRMSrcMem,
4043 (outs VR128:$dst), (ins VR128:$src1,
4044 i16mem:$src2, i32i8imm:$src3),
4046 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4047 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4049 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4054 let Predicates = [HasAVX] in
4055 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4056 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4057 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4058 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4059 imm:$src2))]>, TB, OpSize, VEX;
4060 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4061 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4062 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4063 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4067 let Predicates = [HasAVX] in {
4068 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4069 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4070 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4071 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4072 []>, TB, OpSize, VEX_4V;
4075 let Constraints = "$src1 = $dst" in
4076 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4078 } // ExeDomain = SSEPackedInt
4080 //===---------------------------------------------------------------------===//
4081 // SSE2 - Packed Mask Creation
4082 //===---------------------------------------------------------------------===//
4084 let ExeDomain = SSEPackedInt in {
4086 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4087 "pmovmskb\t{$src, $dst|$dst, $src}",
4088 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
4089 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4090 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4092 let Predicates = [HasAVX2] in {
4093 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4094 "pmovmskb\t{$src, $dst|$dst, $src}",
4095 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4096 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4097 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4100 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4101 "pmovmskb\t{$src, $dst|$dst, $src}",
4102 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
4104 } // ExeDomain = SSEPackedInt
4106 //===---------------------------------------------------------------------===//
4107 // SSE2 - Conditional Store
4108 //===---------------------------------------------------------------------===//
4110 let ExeDomain = SSEPackedInt in {
4113 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4114 (ins VR128:$src, VR128:$mask),
4115 "maskmovdqu\t{$mask, $src|$src, $mask}",
4116 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
4118 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4119 (ins VR128:$src, VR128:$mask),
4120 "maskmovdqu\t{$mask, $src|$src, $mask}",
4121 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
4124 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4125 "maskmovdqu\t{$mask, $src|$src, $mask}",
4126 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
4128 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4129 "maskmovdqu\t{$mask, $src|$src, $mask}",
4130 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
4132 } // ExeDomain = SSEPackedInt
4134 //===---------------------------------------------------------------------===//
4135 // SSE2 - Move Doubleword
4136 //===---------------------------------------------------------------------===//
4138 //===---------------------------------------------------------------------===//
4139 // Move Int Doubleword to Packed Double Int
4141 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4142 "movd\t{$src, $dst|$dst, $src}",
4144 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
4145 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4146 "movd\t{$src, $dst|$dst, $src}",
4148 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
4150 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4151 "mov{d|q}\t{$src, $dst|$dst, $src}",
4153 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
4154 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4155 "mov{d|q}\t{$src, $dst|$dst, $src}",
4156 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
4158 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4159 "movd\t{$src, $dst|$dst, $src}",
4161 (v4i32 (scalar_to_vector GR32:$src)))]>;
4162 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4163 "movd\t{$src, $dst|$dst, $src}",
4165 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
4166 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4167 "mov{d|q}\t{$src, $dst|$dst, $src}",
4169 (v2i64 (scalar_to_vector GR64:$src)))]>;
4170 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4171 "mov{d|q}\t{$src, $dst|$dst, $src}",
4172 [(set FR64:$dst, (bitconvert GR64:$src))]>;
4174 //===---------------------------------------------------------------------===//
4175 // Move Int Doubleword to Single Scalar
4177 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4178 "movd\t{$src, $dst|$dst, $src}",
4179 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
4181 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4182 "movd\t{$src, $dst|$dst, $src}",
4183 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4185 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4186 "movd\t{$src, $dst|$dst, $src}",
4187 [(set FR32:$dst, (bitconvert GR32:$src))]>;
4189 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4190 "movd\t{$src, $dst|$dst, $src}",
4191 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
4193 //===---------------------------------------------------------------------===//
4194 // Move Packed Doubleword Int to Packed Double Int
4196 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4197 "movd\t{$src, $dst|$dst, $src}",
4198 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4200 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4201 (ins i32mem:$dst, VR128:$src),
4202 "movd\t{$src, $dst|$dst, $src}",
4203 [(store (i32 (vector_extract (v4i32 VR128:$src),
4204 (iPTR 0))), addr:$dst)]>, VEX;
4205 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4206 "movd\t{$src, $dst|$dst, $src}",
4207 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4209 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4210 "movd\t{$src, $dst|$dst, $src}",
4211 [(store (i32 (vector_extract (v4i32 VR128:$src),
4212 (iPTR 0))), addr:$dst)]>;
4214 //===---------------------------------------------------------------------===//
4215 // Move Packed Doubleword Int first element to Doubleword Int
4217 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4218 "mov{d|q}\t{$src, $dst|$dst, $src}",
4219 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4221 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4223 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4224 "mov{d|q}\t{$src, $dst|$dst, $src}",
4225 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4228 //===---------------------------------------------------------------------===//
4229 // Bitcast FR64 <-> GR64
4231 let Predicates = [HasAVX] in
4232 def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4233 "vmovq\t{$src, $dst|$dst, $src}",
4234 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4236 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4237 "mov{d|q}\t{$src, $dst|$dst, $src}",
4238 [(set GR64:$dst, (bitconvert FR64:$src))]>, VEX;
4239 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4240 "movq\t{$src, $dst|$dst, $src}",
4241 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>,
4244 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4245 "movq\t{$src, $dst|$dst, $src}",
4246 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
4247 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4248 "mov{d|q}\t{$src, $dst|$dst, $src}",
4249 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4250 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4251 "movq\t{$src, $dst|$dst, $src}",
4252 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4254 //===---------------------------------------------------------------------===//
4255 // Move Scalar Single to Double Int
4257 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4258 "movd\t{$src, $dst|$dst, $src}",
4259 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
4260 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4261 "movd\t{$src, $dst|$dst, $src}",
4262 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
4263 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4264 "movd\t{$src, $dst|$dst, $src}",
4265 [(set GR32:$dst, (bitconvert FR32:$src))]>;
4266 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4267 "movd\t{$src, $dst|$dst, $src}",
4268 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
4270 //===---------------------------------------------------------------------===//
4271 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4273 let AddedComplexity = 15 in {
4274 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4275 "movd\t{$src, $dst|$dst, $src}",
4276 [(set VR128:$dst, (v4i32 (X86vzmovl
4277 (v4i32 (scalar_to_vector GR32:$src)))))]>,
4279 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4280 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4281 [(set VR128:$dst, (v2i64 (X86vzmovl
4282 (v2i64 (scalar_to_vector GR64:$src)))))]>,
4285 let AddedComplexity = 15 in {
4286 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4287 "movd\t{$src, $dst|$dst, $src}",
4288 [(set VR128:$dst, (v4i32 (X86vzmovl
4289 (v4i32 (scalar_to_vector GR32:$src)))))]>;
4290 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4291 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4292 [(set VR128:$dst, (v2i64 (X86vzmovl
4293 (v2i64 (scalar_to_vector GR64:$src)))))]>;
4296 let AddedComplexity = 20 in {
4297 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4298 "movd\t{$src, $dst|$dst, $src}",
4300 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4301 (loadi32 addr:$src))))))]>,
4303 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4304 "movd\t{$src, $dst|$dst, $src}",
4306 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4307 (loadi32 addr:$src))))))]>;
4310 let Predicates = [HasAVX] in {
4311 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4312 let AddedComplexity = 20 in {
4313 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4314 (VMOVZDI2PDIrm addr:$src)>;
4315 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4316 (VMOVZDI2PDIrm addr:$src)>;
4318 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4319 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4320 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4321 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4322 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4323 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4324 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4327 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4328 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4329 (MOVZDI2PDIrm addr:$src)>;
4330 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4331 (MOVZDI2PDIrm addr:$src)>;
4334 // These are the correct encodings of the instructions so that we know how to
4335 // read correct assembly, even though we continue to emit the wrong ones for
4336 // compatibility with Darwin's buggy assembler.
4337 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4338 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4339 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4340 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4341 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4342 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4343 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4344 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4345 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4346 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4347 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4348 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4350 //===---------------------------------------------------------------------===//
4351 // SSE2 - Move Quadword
4352 //===---------------------------------------------------------------------===//
4354 //===---------------------------------------------------------------------===//
4355 // Move Quadword Int to Packed Quadword Int
4357 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4358 "vmovq\t{$src, $dst|$dst, $src}",
4360 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4361 VEX, Requires<[HasAVX]>;
4362 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4363 "movq\t{$src, $dst|$dst, $src}",
4365 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4366 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4368 //===---------------------------------------------------------------------===//
4369 // Move Packed Quadword Int to Quadword Int
4371 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4372 "movq\t{$src, $dst|$dst, $src}",
4373 [(store (i64 (vector_extract (v2i64 VR128:$src),
4374 (iPTR 0))), addr:$dst)]>, VEX;
4375 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4376 "movq\t{$src, $dst|$dst, $src}",
4377 [(store (i64 (vector_extract (v2i64 VR128:$src),
4378 (iPTR 0))), addr:$dst)]>;
4380 //===---------------------------------------------------------------------===//
4381 // Store / copy lower 64-bits of a XMM register.
4383 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4384 "movq\t{$src, $dst|$dst, $src}",
4385 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4386 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4387 "movq\t{$src, $dst|$dst, $src}",
4388 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
4390 let AddedComplexity = 20 in
4391 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4392 "vmovq\t{$src, $dst|$dst, $src}",
4394 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4395 (loadi64 addr:$src))))))]>,
4396 XS, VEX, Requires<[HasAVX]>;
4398 let AddedComplexity = 20 in
4399 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4400 "movq\t{$src, $dst|$dst, $src}",
4402 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4403 (loadi64 addr:$src))))))]>,
4404 XS, Requires<[HasSSE2]>;
4406 let Predicates = [HasAVX], AddedComplexity = 20 in {
4407 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4408 (VMOVZQI2PQIrm addr:$src)>;
4409 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4410 (VMOVZQI2PQIrm addr:$src)>;
4411 def : Pat<(v2i64 (X86vzload addr:$src)),
4412 (VMOVZQI2PQIrm addr:$src)>;
4415 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4416 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4417 (MOVZQI2PQIrm addr:$src)>;
4418 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4419 (MOVZQI2PQIrm addr:$src)>;
4420 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4423 let Predicates = [HasAVX] in {
4424 def : Pat<(v4i64 (X86vzload addr:$src)),
4425 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4428 //===---------------------------------------------------------------------===//
4429 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4430 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4432 let AddedComplexity = 15 in
4433 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4434 "vmovq\t{$src, $dst|$dst, $src}",
4435 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4436 XS, VEX, Requires<[HasAVX]>;
4437 let AddedComplexity = 15 in
4438 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4439 "movq\t{$src, $dst|$dst, $src}",
4440 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4441 XS, Requires<[HasSSE2]>;
4443 let AddedComplexity = 20 in
4444 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4445 "vmovq\t{$src, $dst|$dst, $src}",
4446 [(set VR128:$dst, (v2i64 (X86vzmovl
4447 (loadv2i64 addr:$src))))]>,
4448 XS, VEX, Requires<[HasAVX]>;
4449 let AddedComplexity = 20 in {
4450 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4451 "movq\t{$src, $dst|$dst, $src}",
4452 [(set VR128:$dst, (v2i64 (X86vzmovl
4453 (loadv2i64 addr:$src))))]>,
4454 XS, Requires<[HasSSE2]>;
4457 let AddedComplexity = 20 in {
4458 let Predicates = [HasAVX] in {
4459 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4460 (VMOVZPQILo2PQIrm addr:$src)>;
4461 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4462 (VMOVZPQILo2PQIrr VR128:$src)>;
4464 let Predicates = [HasSSE2] in {
4465 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4466 (MOVZPQILo2PQIrm addr:$src)>;
4467 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4468 (MOVZPQILo2PQIrr VR128:$src)>;
4472 // Instructions to match in the assembler
4473 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4474 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4475 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4476 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4477 // Recognize "movd" with GR64 destination, but encode as a "movq"
4478 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4479 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4481 // Instructions for the disassembler
4482 // xr = XMM register
4485 let Predicates = [HasAVX] in
4486 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4487 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4488 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4489 "movq\t{$src, $dst|$dst, $src}", []>, XS;
4491 //===---------------------------------------------------------------------===//
4492 // SSE3 - Conversion Instructions
4493 //===---------------------------------------------------------------------===//
4495 // Convert Packed Double FP to Packed DW Integers
4496 let Predicates = [HasAVX] in {
4497 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4498 // register, but the same isn't true when using memory operands instead.
4499 // Provide other assembly rr and rm forms to address this explicitly.
4500 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4501 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4502 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4503 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4506 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4507 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4508 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4509 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4512 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4513 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4514 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4515 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4518 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4519 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4520 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4521 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4523 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4524 (VCVTTPD2DQYrr VR256:$src)>;
4525 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4526 (VCVTTPD2DQYrm addr:$src)>;
4528 // Convert Packed DW Integers to Packed Double FP
4529 let Predicates = [HasAVX] in {
4530 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4531 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4532 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4533 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4534 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4535 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4536 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4537 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4540 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4541 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4542 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4543 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4545 // AVX 256-bit register conversion intrinsics
4546 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4547 (VCVTDQ2PDYrr VR128:$src)>;
4548 def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
4549 (VCVTDQ2PDYrm addr:$src)>;
4551 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4552 (VCVTPD2DQYrr VR256:$src)>;
4553 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4554 (VCVTPD2DQYrm addr:$src)>;
4556 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4557 (VCVTDQ2PDYrr VR128:$src)>;
4558 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
4559 (VCVTDQ2PDYrm addr:$src)>;
4561 //===---------------------------------------------------------------------===//
4562 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4563 //===---------------------------------------------------------------------===//
4564 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4565 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4566 X86MemOperand x86memop> {
4567 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4568 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4569 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
4570 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4571 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4572 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
4575 let Predicates = [HasAVX] in {
4576 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4577 v4f32, VR128, memopv4f32, f128mem>, VEX;
4578 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4579 v4f32, VR128, memopv4f32, f128mem>, VEX;
4580 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4581 v8f32, VR256, memopv8f32, f256mem>, VEX;
4582 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4583 v8f32, VR256, memopv8f32, f256mem>, VEX;
4585 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4586 memopv4f32, f128mem>;
4587 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4588 memopv4f32, f128mem>;
4590 let Predicates = [HasAVX] in {
4591 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4592 (VMOVSHDUPrr VR128:$src)>;
4593 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4594 (VMOVSHDUPrm addr:$src)>;
4595 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4596 (VMOVSLDUPrr VR128:$src)>;
4597 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4598 (VMOVSLDUPrm addr:$src)>;
4599 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4600 (VMOVSHDUPYrr VR256:$src)>;
4601 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4602 (VMOVSHDUPYrm addr:$src)>;
4603 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4604 (VMOVSLDUPYrr VR256:$src)>;
4605 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4606 (VMOVSLDUPYrm addr:$src)>;
4609 let Predicates = [HasSSE3] in {
4610 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4611 (MOVSHDUPrr VR128:$src)>;
4612 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4613 (MOVSHDUPrm addr:$src)>;
4614 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4615 (MOVSLDUPrr VR128:$src)>;
4616 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4617 (MOVSLDUPrm addr:$src)>;
4620 //===---------------------------------------------------------------------===//
4621 // SSE3 - Replicate Double FP - MOVDDUP
4622 //===---------------------------------------------------------------------===//
4624 multiclass sse3_replicate_dfp<string OpcodeStr> {
4625 let neverHasSideEffects = 1 in
4626 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4627 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4629 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4630 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4633 (scalar_to_vector (loadf64 addr:$src)))))]>;
4636 // FIXME: Merge with above classe when there're patterns for the ymm version
4637 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4638 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4639 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4640 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
4641 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4642 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4645 (scalar_to_vector (loadf64 addr:$src)))))]>;
4648 let Predicates = [HasAVX] in {
4649 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4650 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4653 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4655 let Predicates = [HasAVX] in {
4656 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4657 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4658 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4659 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4660 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4661 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4662 def : Pat<(X86Movddup (bc_v2f64
4663 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4664 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4667 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4668 (VMOVDDUPYrm addr:$src)>;
4669 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4670 (VMOVDDUPYrm addr:$src)>;
4671 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4672 (VMOVDDUPYrm addr:$src)>;
4673 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4674 (VMOVDDUPYrr VR256:$src)>;
4677 let Predicates = [HasSSE3] in {
4678 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4679 (MOVDDUPrm addr:$src)>;
4680 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4681 (MOVDDUPrm addr:$src)>;
4682 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4683 (MOVDDUPrm addr:$src)>;
4684 def : Pat<(X86Movddup (bc_v2f64
4685 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4686 (MOVDDUPrm addr:$src)>;
4689 //===---------------------------------------------------------------------===//
4690 // SSE3 - Move Unaligned Integer
4691 //===---------------------------------------------------------------------===//
4693 let Predicates = [HasAVX] in {
4694 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4695 "vlddqu\t{$src, $dst|$dst, $src}",
4696 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4697 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4698 "vlddqu\t{$src, $dst|$dst, $src}",
4699 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4701 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4702 "lddqu\t{$src, $dst|$dst, $src}",
4703 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
4705 //===---------------------------------------------------------------------===//
4706 // SSE3 - Arithmetic
4707 //===---------------------------------------------------------------------===//
4709 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4710 X86MemOperand x86memop, bit Is2Addr = 1> {
4711 def rr : I<0xD0, MRMSrcReg,
4712 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4714 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4715 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4716 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
4717 def rm : I<0xD0, MRMSrcMem,
4718 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4720 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4721 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4722 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
4725 let Predicates = [HasAVX] in {
4726 let ExeDomain = SSEPackedSingle in {
4727 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4728 f128mem, 0>, TB, XD, VEX_4V;
4729 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4730 f256mem, 0>, TB, XD, VEX_4V;
4732 let ExeDomain = SSEPackedDouble in {
4733 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4734 f128mem, 0>, TB, OpSize, VEX_4V;
4735 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4736 f256mem, 0>, TB, OpSize, VEX_4V;
4739 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
4740 let ExeDomain = SSEPackedSingle in
4741 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4743 let ExeDomain = SSEPackedDouble in
4744 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4745 f128mem>, TB, OpSize;
4748 //===---------------------------------------------------------------------===//
4749 // SSE3 Instructions
4750 //===---------------------------------------------------------------------===//
4753 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4754 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4755 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4757 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4758 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4759 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
4761 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4763 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4764 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4765 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
4767 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4768 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4769 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4771 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4772 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4773 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
4775 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4777 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4778 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4779 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
4782 let Predicates = [HasAVX] in {
4783 let ExeDomain = SSEPackedSingle in {
4784 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4785 X86fhadd, 0>, VEX_4V;
4786 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4787 X86fhsub, 0>, VEX_4V;
4788 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4789 X86fhadd, 0>, VEX_4V;
4790 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4791 X86fhsub, 0>, VEX_4V;
4793 let ExeDomain = SSEPackedDouble in {
4794 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4795 X86fhadd, 0>, VEX_4V;
4796 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4797 X86fhsub, 0>, VEX_4V;
4798 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4799 X86fhadd, 0>, VEX_4V;
4800 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4801 X86fhsub, 0>, VEX_4V;
4805 let Constraints = "$src1 = $dst" in {
4806 let ExeDomain = SSEPackedSingle in {
4807 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
4808 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
4810 let ExeDomain = SSEPackedDouble in {
4811 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
4812 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
4816 //===---------------------------------------------------------------------===//
4817 // SSSE3 - Packed Absolute Instructions
4818 //===---------------------------------------------------------------------===//
4821 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4822 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4823 Intrinsic IntId128> {
4824 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4826 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4827 [(set VR128:$dst, (IntId128 VR128:$src))]>,
4830 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4832 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4835 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
4838 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4839 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
4840 Intrinsic IntId256> {
4841 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
4843 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4844 [(set VR256:$dst, (IntId256 VR256:$src))]>,
4847 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
4849 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4852 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
4855 let Predicates = [HasAVX] in {
4856 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
4857 int_x86_ssse3_pabs_b_128>, VEX;
4858 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
4859 int_x86_ssse3_pabs_w_128>, VEX;
4860 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
4861 int_x86_ssse3_pabs_d_128>, VEX;
4864 let Predicates = [HasAVX2] in {
4865 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
4866 int_x86_avx2_pabs_b>, VEX;
4867 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
4868 int_x86_avx2_pabs_w>, VEX;
4869 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
4870 int_x86_avx2_pabs_d>, VEX;
4873 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
4874 int_x86_ssse3_pabs_b_128>;
4875 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
4876 int_x86_ssse3_pabs_w_128>;
4877 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
4878 int_x86_ssse3_pabs_d_128>;
4880 //===---------------------------------------------------------------------===//
4881 // SSSE3 - Packed Binary Operator Instructions
4882 //===---------------------------------------------------------------------===//
4884 /// SS3I_binop_rm - Simple SSSE3 bin op
4885 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4886 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
4887 X86MemOperand x86memop, bit Is2Addr = 1> {
4888 let isCommutable = 1 in
4889 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
4890 (ins RC:$src1, RC:$src2),
4892 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4893 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4894 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
4896 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
4897 (ins RC:$src1, x86memop:$src2),
4899 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4900 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4902 (OpVT (OpNode RC:$src1,
4903 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
4906 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
4907 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
4908 Intrinsic IntId128, bit Is2Addr = 1> {
4909 let isCommutable = 1 in
4910 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4911 (ins VR128:$src1, VR128:$src2),
4913 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4914 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4915 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4917 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4918 (ins VR128:$src1, i128mem:$src2),
4920 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4921 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4923 (IntId128 VR128:$src1,
4924 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
4927 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
4928 Intrinsic IntId256> {
4929 let isCommutable = 1 in
4930 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
4931 (ins VR256:$src1, VR256:$src2),
4932 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4933 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
4935 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
4936 (ins VR256:$src1, i256mem:$src2),
4937 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4939 (IntId256 VR256:$src1,
4940 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
4943 let ImmT = NoImm, Predicates = [HasAVX] in {
4944 let isCommutable = 0 in {
4945 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
4946 memopv2i64, i128mem, 0>, VEX_4V;
4947 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
4948 memopv2i64, i128mem, 0>, VEX_4V;
4949 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
4950 memopv2i64, i128mem, 0>, VEX_4V;
4951 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
4952 memopv2i64, i128mem, 0>, VEX_4V;
4953 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
4954 memopv2i64, i128mem, 0>, VEX_4V;
4955 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
4956 memopv2i64, i128mem, 0>, VEX_4V;
4957 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
4958 memopv2i64, i128mem, 0>, VEX_4V;
4959 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
4960 memopv2i64, i128mem, 0>, VEX_4V;
4961 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
4962 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
4963 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
4964 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
4965 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
4966 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
4968 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
4969 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
4972 let ImmT = NoImm, Predicates = [HasAVX2] in {
4973 let isCommutable = 0 in {
4974 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
4975 memopv4i64, i256mem, 0>, VEX_4V;
4976 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
4977 memopv4i64, i256mem, 0>, VEX_4V;
4978 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
4979 memopv4i64, i256mem, 0>, VEX_4V;
4980 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
4981 memopv4i64, i256mem, 0>, VEX_4V;
4982 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
4983 memopv4i64, i256mem, 0>, VEX_4V;
4984 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
4985 memopv4i64, i256mem, 0>, VEX_4V;
4986 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
4987 memopv4i64, i256mem, 0>, VEX_4V;
4988 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
4989 memopv4i64, i256mem, 0>, VEX_4V;
4990 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
4991 int_x86_avx2_phadd_sw>, VEX_4V;
4992 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
4993 int_x86_avx2_phsub_sw>, VEX_4V;
4994 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
4995 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
4997 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
4998 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5001 // None of these have i8 immediate fields.
5002 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5003 let isCommutable = 0 in {
5004 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5005 memopv2i64, i128mem>;
5006 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5007 memopv2i64, i128mem>;
5008 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5009 memopv2i64, i128mem>;
5010 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5011 memopv2i64, i128mem>;
5012 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5013 memopv2i64, i128mem>;
5014 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5015 memopv2i64, i128mem>;
5016 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5017 memopv2i64, i128mem>;
5018 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5019 memopv2i64, i128mem>;
5020 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5021 int_x86_ssse3_phadd_sw_128>;
5022 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5023 int_x86_ssse3_phsub_sw_128>;
5024 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5025 int_x86_ssse3_pmadd_ub_sw_128>;
5027 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5028 int_x86_ssse3_pmul_hr_sw_128>;
5031 //===---------------------------------------------------------------------===//
5032 // SSSE3 - Packed Align Instruction Patterns
5033 //===---------------------------------------------------------------------===//
5035 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5036 let neverHasSideEffects = 1 in {
5037 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5038 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5040 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5042 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5045 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5046 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5048 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5050 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5055 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5056 let neverHasSideEffects = 1 in {
5057 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5058 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5060 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5063 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5064 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5066 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5071 let Predicates = [HasAVX] in
5072 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5073 let Predicates = [HasAVX2] in
5074 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5075 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5076 defm PALIGN : ssse3_palign<"palignr">;
5078 let Predicates = [HasAVX2] in {
5079 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5080 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5081 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5082 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5083 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5084 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5085 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5086 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5089 let Predicates = [HasAVX] in {
5090 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5091 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5092 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5093 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5094 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5095 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5096 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5097 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5100 let Predicates = [HasSSSE3] in {
5101 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5102 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5103 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5104 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5105 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5106 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5107 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5108 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5111 //===---------------------------------------------------------------------===//
5112 // SSSE3 - Thread synchronization
5113 //===---------------------------------------------------------------------===//
5115 let usesCustomInserter = 1 in {
5116 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5117 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5118 Requires<[HasSSE3]>;
5119 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5120 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>,
5121 Requires<[HasSSE3]>;
5124 let Uses = [EAX, ECX, EDX] in
5125 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
5126 Requires<[HasSSE3]>;
5127 let Uses = [ECX, EAX] in
5128 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
5129 Requires<[HasSSE3]>;
5131 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5132 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5134 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5135 Requires<[In32BitMode]>;
5136 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5137 Requires<[In64BitMode]>;
5139 //===----------------------------------------------------------------------===//
5140 // SSE4.1 - Packed Move with Sign/Zero Extend
5141 //===----------------------------------------------------------------------===//
5143 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5144 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5145 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5146 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5148 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5149 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5151 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5155 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5157 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5158 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5159 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5161 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5162 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5163 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5166 let Predicates = [HasAVX] in {
5167 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5169 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5171 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5173 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5175 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5177 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5181 let Predicates = [HasAVX2] in {
5182 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5183 int_x86_avx2_pmovsxbw>, VEX;
5184 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5185 int_x86_avx2_pmovsxwd>, VEX;
5186 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5187 int_x86_avx2_pmovsxdq>, VEX;
5188 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5189 int_x86_avx2_pmovzxbw>, VEX;
5190 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5191 int_x86_avx2_pmovzxwd>, VEX;
5192 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5193 int_x86_avx2_pmovzxdq>, VEX;
5196 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5197 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5198 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5199 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5200 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5201 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5203 let Predicates = [HasAVX] in {
5204 // Common patterns involving scalar load.
5205 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5206 (VPMOVSXBWrm addr:$src)>;
5207 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5208 (VPMOVSXBWrm addr:$src)>;
5210 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5211 (VPMOVSXWDrm addr:$src)>;
5212 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5213 (VPMOVSXWDrm addr:$src)>;
5215 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5216 (VPMOVSXDQrm addr:$src)>;
5217 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5218 (VPMOVSXDQrm addr:$src)>;
5220 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5221 (VPMOVZXBWrm addr:$src)>;
5222 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5223 (VPMOVZXBWrm addr:$src)>;
5225 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5226 (VPMOVZXWDrm addr:$src)>;
5227 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5228 (VPMOVZXWDrm addr:$src)>;
5230 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5231 (VPMOVZXDQrm addr:$src)>;
5232 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5233 (VPMOVZXDQrm addr:$src)>;
5236 let Predicates = [HasSSE41] in {
5237 // Common patterns involving scalar load.
5238 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5239 (PMOVSXBWrm addr:$src)>;
5240 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5241 (PMOVSXBWrm addr:$src)>;
5243 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5244 (PMOVSXWDrm addr:$src)>;
5245 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5246 (PMOVSXWDrm addr:$src)>;
5248 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5249 (PMOVSXDQrm addr:$src)>;
5250 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5251 (PMOVSXDQrm addr:$src)>;
5253 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5254 (PMOVZXBWrm addr:$src)>;
5255 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5256 (PMOVZXBWrm addr:$src)>;
5258 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5259 (PMOVZXWDrm addr:$src)>;
5260 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5261 (PMOVZXWDrm addr:$src)>;
5263 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5264 (PMOVZXDQrm addr:$src)>;
5265 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5266 (PMOVZXDQrm addr:$src)>;
5269 let Predicates = [HasAVX] in {
5270 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5271 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5274 let Predicates = [HasSSE41] in {
5275 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5276 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5280 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5281 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5282 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5283 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5285 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5286 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5288 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5292 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5294 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5295 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5296 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5298 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5299 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5301 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5305 let Predicates = [HasAVX] in {
5306 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5308 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5310 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5312 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5316 let Predicates = [HasAVX2] in {
5317 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5318 int_x86_avx2_pmovsxbd>, VEX;
5319 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5320 int_x86_avx2_pmovsxwq>, VEX;
5321 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5322 int_x86_avx2_pmovzxbd>, VEX;
5323 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5324 int_x86_avx2_pmovzxwq>, VEX;
5327 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5328 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5329 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5330 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5332 let Predicates = [HasAVX] in {
5333 // Common patterns involving scalar load
5334 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5335 (VPMOVSXBDrm addr:$src)>;
5336 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5337 (VPMOVSXWQrm addr:$src)>;
5339 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5340 (VPMOVZXBDrm addr:$src)>;
5341 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5342 (VPMOVZXWQrm addr:$src)>;
5345 let Predicates = [HasSSE41] in {
5346 // Common patterns involving scalar load
5347 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5348 (PMOVSXBDrm addr:$src)>;
5349 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5350 (PMOVSXWQrm addr:$src)>;
5352 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5353 (PMOVZXBDrm addr:$src)>;
5354 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5355 (PMOVZXWQrm addr:$src)>;
5358 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5359 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5360 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5361 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5363 // Expecting a i16 load any extended to i32 value.
5364 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5365 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5366 [(set VR128:$dst, (IntId (bitconvert
5367 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5371 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5373 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5374 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5375 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5377 // Expecting a i16 load any extended to i32 value.
5378 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5379 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5380 [(set VR256:$dst, (IntId (bitconvert
5381 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5385 let Predicates = [HasAVX] in {
5386 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5388 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5391 let Predicates = [HasAVX2] in {
5392 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5393 int_x86_avx2_pmovsxbq>, VEX;
5394 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5395 int_x86_avx2_pmovzxbq>, VEX;
5397 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5398 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5400 let Predicates = [HasAVX] in {
5401 // Common patterns involving scalar load
5402 def : Pat<(int_x86_sse41_pmovsxbq
5403 (bitconvert (v4i32 (X86vzmovl
5404 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5405 (VPMOVSXBQrm addr:$src)>;
5407 def : Pat<(int_x86_sse41_pmovzxbq
5408 (bitconvert (v4i32 (X86vzmovl
5409 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5410 (VPMOVZXBQrm addr:$src)>;
5413 let Predicates = [HasSSE41] in {
5414 // Common patterns involving scalar load
5415 def : Pat<(int_x86_sse41_pmovsxbq
5416 (bitconvert (v4i32 (X86vzmovl
5417 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5418 (PMOVSXBQrm addr:$src)>;
5420 def : Pat<(int_x86_sse41_pmovzxbq
5421 (bitconvert (v4i32 (X86vzmovl
5422 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5423 (PMOVZXBQrm addr:$src)>;
5426 //===----------------------------------------------------------------------===//
5427 // SSE4.1 - Extract Instructions
5428 //===----------------------------------------------------------------------===//
5430 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5431 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5432 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5433 (ins VR128:$src1, i32i8imm:$src2),
5434 !strconcat(OpcodeStr,
5435 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5436 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5438 let neverHasSideEffects = 1, mayStore = 1 in
5439 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5440 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5441 !strconcat(OpcodeStr,
5442 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5445 // There's an AssertZext in the way of writing the store pattern
5446 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5449 let Predicates = [HasAVX] in {
5450 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5451 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5452 (ins VR128:$src1, i32i8imm:$src2),
5453 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5456 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5459 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5460 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5461 let neverHasSideEffects = 1, mayStore = 1 in
5462 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5463 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5464 !strconcat(OpcodeStr,
5465 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5468 // There's an AssertZext in the way of writing the store pattern
5469 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5472 let Predicates = [HasAVX] in
5473 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5475 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5478 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5479 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5480 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5481 (ins VR128:$src1, i32i8imm:$src2),
5482 !strconcat(OpcodeStr,
5483 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5485 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5486 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5487 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5488 !strconcat(OpcodeStr,
5489 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5490 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5491 addr:$dst)]>, OpSize;
5494 let Predicates = [HasAVX] in
5495 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5497 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5499 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5500 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5501 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5502 (ins VR128:$src1, i32i8imm:$src2),
5503 !strconcat(OpcodeStr,
5504 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5506 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5507 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5508 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5509 !strconcat(OpcodeStr,
5510 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5511 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5512 addr:$dst)]>, OpSize, REX_W;
5515 let Predicates = [HasAVX] in
5516 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5518 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5520 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5522 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5523 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5524 (ins VR128:$src1, i32i8imm:$src2),
5525 !strconcat(OpcodeStr,
5526 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5528 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5530 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5531 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5532 !strconcat(OpcodeStr,
5533 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5534 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5535 addr:$dst)]>, OpSize;
5538 let ExeDomain = SSEPackedSingle in {
5539 let Predicates = [HasAVX] in {
5540 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5541 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5542 (ins VR128:$src1, i32i8imm:$src2),
5543 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5546 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5549 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5550 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5553 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5555 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5558 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5559 Requires<[HasSSE41]>;
5561 //===----------------------------------------------------------------------===//
5562 // SSE4.1 - Insert Instructions
5563 //===----------------------------------------------------------------------===//
5565 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5566 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5567 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5569 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5571 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5573 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5574 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5575 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5577 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5579 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5581 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5582 imm:$src3))]>, OpSize;
5585 let Predicates = [HasAVX] in
5586 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5587 let Constraints = "$src1 = $dst" in
5588 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5590 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5591 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5592 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5594 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5596 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5598 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5600 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5601 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5603 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5605 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5607 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5608 imm:$src3)))]>, OpSize;
5611 let Predicates = [HasAVX] in
5612 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5613 let Constraints = "$src1 = $dst" in
5614 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5616 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5617 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5618 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5620 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5622 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5624 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5626 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5627 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5629 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5631 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5633 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5634 imm:$src3)))]>, OpSize;
5637 let Predicates = [HasAVX] in
5638 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5639 let Constraints = "$src1 = $dst" in
5640 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5642 // insertps has a few different modes, there's the first two here below which
5643 // are optimized inserts that won't zero arbitrary elements in the destination
5644 // vector. The next one matches the intrinsic and could zero arbitrary elements
5645 // in the target vector.
5646 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5647 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5648 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5650 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5652 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5654 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5656 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5657 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5659 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5661 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5663 (X86insrtps VR128:$src1,
5664 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
5665 imm:$src3))]>, OpSize;
5668 let ExeDomain = SSEPackedSingle in {
5669 let Predicates = [HasAVX] in
5670 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
5671 let Constraints = "$src1 = $dst" in
5672 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
5675 //===----------------------------------------------------------------------===//
5676 // SSE4.1 - Round Instructions
5677 //===----------------------------------------------------------------------===//
5679 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
5680 X86MemOperand x86memop, RegisterClass RC,
5681 PatFrag mem_frag32, PatFrag mem_frag64,
5682 Intrinsic V4F32Int, Intrinsic V2F64Int> {
5683 let ExeDomain = SSEPackedSingle in {
5684 // Intrinsic operation, reg.
5685 // Vector intrinsic operation, reg
5686 def PSr : SS4AIi8<opcps, MRMSrcReg,
5687 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5688 !strconcat(OpcodeStr,
5689 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5690 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
5693 // Vector intrinsic operation, mem
5694 def PSm : SS4AIi8<opcps, MRMSrcMem,
5695 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5696 !strconcat(OpcodeStr,
5697 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5699 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
5701 } // ExeDomain = SSEPackedSingle
5703 let ExeDomain = SSEPackedDouble in {
5704 // Vector intrinsic operation, reg
5705 def PDr : SS4AIi8<opcpd, MRMSrcReg,
5706 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5707 !strconcat(OpcodeStr,
5708 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5709 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
5712 // Vector intrinsic operation, mem
5713 def PDm : SS4AIi8<opcpd, MRMSrcMem,
5714 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5715 !strconcat(OpcodeStr,
5716 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5718 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
5720 } // ExeDomain = SSEPackedDouble
5723 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
5726 Intrinsic F64Int, bit Is2Addr = 1> {
5727 let ExeDomain = GenericDomain in {
5729 def SSr : SS4AIi8<opcss, MRMSrcReg,
5730 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
5732 !strconcat(OpcodeStr,
5733 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5734 !strconcat(OpcodeStr,
5735 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5738 // Intrinsic operation, reg.
5739 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
5740 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5742 !strconcat(OpcodeStr,
5743 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5744 !strconcat(OpcodeStr,
5745 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5746 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5749 // Intrinsic operation, mem.
5750 def SSm : SS4AIi8<opcss, MRMSrcMem,
5751 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5753 !strconcat(OpcodeStr,
5754 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5755 !strconcat(OpcodeStr,
5756 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5758 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
5762 def SDr : SS4AIi8<opcsd, MRMSrcReg,
5763 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
5765 !strconcat(OpcodeStr,
5766 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5767 !strconcat(OpcodeStr,
5768 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5771 // Intrinsic operation, reg.
5772 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
5773 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5775 !strconcat(OpcodeStr,
5776 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5777 !strconcat(OpcodeStr,
5778 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5779 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5782 // Intrinsic operation, mem.
5783 def SDm : SS4AIi8<opcsd, MRMSrcMem,
5784 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5786 !strconcat(OpcodeStr,
5787 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5788 !strconcat(OpcodeStr,
5789 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5791 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
5793 } // ExeDomain = GenericDomain
5796 // FP round - roundss, roundps, roundsd, roundpd
5797 let Predicates = [HasAVX] in {
5799 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
5800 memopv4f32, memopv2f64,
5801 int_x86_sse41_round_ps,
5802 int_x86_sse41_round_pd>, VEX;
5803 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
5804 memopv8f32, memopv4f64,
5805 int_x86_avx_round_ps_256,
5806 int_x86_avx_round_pd_256>, VEX;
5807 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
5808 int_x86_sse41_round_ss,
5809 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
5811 def : Pat<(ffloor FR32:$src),
5812 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
5813 def : Pat<(f64 (ffloor FR64:$src)),
5814 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
5815 def : Pat<(f32 (fnearbyint FR32:$src)),
5816 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
5817 def : Pat<(f64 (fnearbyint FR64:$src)),
5818 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
5819 def : Pat<(f32 (fceil FR32:$src)),
5820 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
5821 def : Pat<(f64 (fceil FR64:$src)),
5822 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
5823 def : Pat<(f32 (frint FR32:$src)),
5824 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
5825 def : Pat<(f64 (frint FR64:$src)),
5826 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
5827 def : Pat<(f32 (ftrunc FR32:$src)),
5828 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
5829 def : Pat<(f64 (ftrunc FR64:$src)),
5830 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
5833 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
5834 memopv4f32, memopv2f64,
5835 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
5836 let Constraints = "$src1 = $dst" in
5837 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
5838 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
5840 def : Pat<(ffloor FR32:$src),
5841 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
5842 def : Pat<(f64 (ffloor FR64:$src)),
5843 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
5844 def : Pat<(f32 (fnearbyint FR32:$src)),
5845 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
5846 def : Pat<(f64 (fnearbyint FR64:$src)),
5847 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
5848 def : Pat<(f32 (fceil FR32:$src)),
5849 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
5850 def : Pat<(f64 (fceil FR64:$src)),
5851 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
5852 def : Pat<(f32 (frint FR32:$src)),
5853 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
5854 def : Pat<(f64 (frint FR64:$src)),
5855 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
5856 def : Pat<(f32 (ftrunc FR32:$src)),
5857 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
5858 def : Pat<(f64 (ftrunc FR64:$src)),
5859 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
5861 //===----------------------------------------------------------------------===//
5862 // SSE4.1 - Packed Bit Test
5863 //===----------------------------------------------------------------------===//
5865 // ptest instruction we'll lower to this in X86ISelLowering primarily from
5866 // the intel intrinsic that corresponds to this.
5867 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5868 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5869 "vptest\t{$src2, $src1|$src1, $src2}",
5870 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5872 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5873 "vptest\t{$src2, $src1|$src1, $src2}",
5874 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5877 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
5878 "vptest\t{$src2, $src1|$src1, $src2}",
5879 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
5881 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
5882 "vptest\t{$src2, $src1|$src1, $src2}",
5883 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
5887 let Defs = [EFLAGS] in {
5888 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5889 "ptest\t{$src2, $src1|$src1, $src2}",
5890 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5892 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5893 "ptest\t{$src2, $src1|$src1, $src2}",
5894 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5898 // The bit test instructions below are AVX only
5899 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
5900 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
5901 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
5902 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5903 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
5904 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
5905 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5906 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
5910 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5911 let ExeDomain = SSEPackedSingle in {
5912 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
5913 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
5915 let ExeDomain = SSEPackedDouble in {
5916 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
5917 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
5921 //===----------------------------------------------------------------------===//
5922 // SSE4.1 - Misc Instructions
5923 //===----------------------------------------------------------------------===//
5925 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
5926 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
5927 "popcnt{w}\t{$src, $dst|$dst, $src}",
5928 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
5930 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
5931 "popcnt{w}\t{$src, $dst|$dst, $src}",
5932 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
5933 (implicit EFLAGS)]>, OpSize, XS;
5935 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
5936 "popcnt{l}\t{$src, $dst|$dst, $src}",
5937 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
5939 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
5940 "popcnt{l}\t{$src, $dst|$dst, $src}",
5941 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
5942 (implicit EFLAGS)]>, XS;
5944 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
5945 "popcnt{q}\t{$src, $dst|$dst, $src}",
5946 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
5948 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
5949 "popcnt{q}\t{$src, $dst|$dst, $src}",
5950 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
5951 (implicit EFLAGS)]>, XS;
5956 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
5957 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
5958 Intrinsic IntId128> {
5959 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5961 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5962 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
5963 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5965 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5968 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
5971 let Predicates = [HasAVX] in
5972 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
5973 int_x86_sse41_phminposuw>, VEX;
5974 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
5975 int_x86_sse41_phminposuw>;
5977 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
5978 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
5979 Intrinsic IntId128, bit Is2Addr = 1> {
5980 let isCommutable = 1 in
5981 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5982 (ins VR128:$src1, VR128:$src2),
5984 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5985 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5986 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
5987 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5988 (ins VR128:$src1, i128mem:$src2),
5990 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5991 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5993 (IntId128 VR128:$src1,
5994 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5997 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
5998 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5999 Intrinsic IntId256> {
6000 let isCommutable = 1 in
6001 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6002 (ins VR256:$src1, VR256:$src2),
6003 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6004 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6005 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6006 (ins VR256:$src1, i256mem:$src2),
6007 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6009 (IntId256 VR256:$src1,
6010 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6013 let Predicates = [HasAVX] in {
6014 let isCommutable = 0 in
6015 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6017 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6019 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6021 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6023 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6025 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6027 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6029 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6031 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6033 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6037 let Predicates = [HasAVX2] in {
6038 let isCommutable = 0 in
6039 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6040 int_x86_avx2_packusdw>, VEX_4V;
6041 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6042 int_x86_avx2_pmins_b>, VEX_4V;
6043 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6044 int_x86_avx2_pmins_d>, VEX_4V;
6045 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6046 int_x86_avx2_pminu_d>, VEX_4V;
6047 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6048 int_x86_avx2_pminu_w>, VEX_4V;
6049 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6050 int_x86_avx2_pmaxs_b>, VEX_4V;
6051 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6052 int_x86_avx2_pmaxs_d>, VEX_4V;
6053 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6054 int_x86_avx2_pmaxu_d>, VEX_4V;
6055 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6056 int_x86_avx2_pmaxu_w>, VEX_4V;
6057 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6058 int_x86_avx2_pmul_dq>, VEX_4V;
6061 let Constraints = "$src1 = $dst" in {
6062 let isCommutable = 0 in
6063 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6064 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6065 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6066 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6067 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6068 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6069 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6070 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6071 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6072 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6075 /// SS48I_binop_rm - Simple SSE41 binary operator.
6076 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6077 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6078 X86MemOperand x86memop, bit Is2Addr = 1> {
6079 let isCommutable = 1 in
6080 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6081 (ins RC:$src1, RC:$src2),
6083 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6084 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6085 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6086 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6087 (ins RC:$src1, x86memop:$src2),
6089 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6090 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6092 (OpVT (OpNode RC:$src1,
6093 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6096 let Predicates = [HasAVX] in {
6097 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6098 memopv2i64, i128mem, 0>, VEX_4V;
6099 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6100 memopv2i64, i128mem, 0>, VEX_4V;
6102 let Predicates = [HasAVX2] in {
6103 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6104 memopv4i64, i256mem, 0>, VEX_4V;
6105 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6106 memopv4i64, i256mem, 0>, VEX_4V;
6109 let Constraints = "$src1 = $dst" in {
6110 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6111 memopv2i64, i128mem>;
6112 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6113 memopv2i64, i128mem>;
6116 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6117 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6118 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6119 X86MemOperand x86memop, bit Is2Addr = 1> {
6120 let isCommutable = 1 in
6121 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6122 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6124 !strconcat(OpcodeStr,
6125 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6126 !strconcat(OpcodeStr,
6127 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6128 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6130 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6131 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6133 !strconcat(OpcodeStr,
6134 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6135 !strconcat(OpcodeStr,
6136 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6139 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6143 let Predicates = [HasAVX] in {
6144 let isCommutable = 0 in {
6145 let ExeDomain = SSEPackedSingle in {
6146 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6147 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6148 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6149 int_x86_avx_blend_ps_256, VR256, memopv8f32, i256mem, 0>, VEX_4V;
6151 let ExeDomain = SSEPackedDouble in {
6152 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6153 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6154 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6155 int_x86_avx_blend_pd_256, VR256, memopv4f64, i256mem, 0>, VEX_4V;
6157 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6158 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6159 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6160 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6162 let ExeDomain = SSEPackedSingle in
6163 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6164 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6165 let ExeDomain = SSEPackedDouble in
6166 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6167 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6168 let ExeDomain = SSEPackedSingle in
6169 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6170 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6173 let Predicates = [HasAVX2] in {
6174 let isCommutable = 0 in {
6175 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6176 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6177 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6178 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6182 let Constraints = "$src1 = $dst" in {
6183 let isCommutable = 0 in {
6184 let ExeDomain = SSEPackedSingle in
6185 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6186 VR128, memopv4f32, i128mem>;
6187 let ExeDomain = SSEPackedDouble in
6188 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6189 VR128, memopv2f64, i128mem>;
6190 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6191 VR128, memopv2i64, i128mem>;
6192 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6193 VR128, memopv2i64, i128mem>;
6195 let ExeDomain = SSEPackedSingle in
6196 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6197 VR128, memopv4f32, i128mem>;
6198 let ExeDomain = SSEPackedDouble in
6199 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6200 VR128, memopv2f64, i128mem>;
6203 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6204 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6205 RegisterClass RC, X86MemOperand x86memop,
6206 PatFrag mem_frag, Intrinsic IntId> {
6207 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6208 (ins RC:$src1, RC:$src2, RC:$src3),
6209 !strconcat(OpcodeStr,
6210 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6211 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6212 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6214 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6215 (ins RC:$src1, x86memop:$src2, RC:$src3),
6216 !strconcat(OpcodeStr,
6217 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6219 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6221 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6224 let Predicates = [HasAVX] in {
6225 let ExeDomain = SSEPackedDouble in {
6226 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
6227 memopv2f64, int_x86_sse41_blendvpd>;
6228 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
6229 memopv4f64, int_x86_avx_blendv_pd_256>;
6230 } // ExeDomain = SSEPackedDouble
6231 let ExeDomain = SSEPackedSingle in {
6232 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
6233 memopv4f32, int_x86_sse41_blendvps>;
6234 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
6235 memopv8f32, int_x86_avx_blendv_ps_256>;
6236 } // ExeDomain = SSEPackedSingle
6237 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6238 memopv2i64, int_x86_sse41_pblendvb>;
6241 let Predicates = [HasAVX2] in {
6242 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6243 memopv4i64, int_x86_avx2_pblendvb>;
6246 let Predicates = [HasAVX] in {
6247 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6248 (v16i8 VR128:$src2))),
6249 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6250 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6251 (v4i32 VR128:$src2))),
6252 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6253 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6254 (v4f32 VR128:$src2))),
6255 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6256 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6257 (v2i64 VR128:$src2))),
6258 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6259 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6260 (v2f64 VR128:$src2))),
6261 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6262 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6263 (v8i32 VR256:$src2))),
6264 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6265 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6266 (v8f32 VR256:$src2))),
6267 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6268 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6269 (v4i64 VR256:$src2))),
6270 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6271 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6272 (v4f64 VR256:$src2))),
6273 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6276 let Predicates = [HasAVX2] in {
6277 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6278 (v32i8 VR256:$src2))),
6279 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6282 /// SS41I_ternary_int - SSE 4.1 ternary operator
6283 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6284 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6286 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6287 (ins VR128:$src1, VR128:$src2),
6288 !strconcat(OpcodeStr,
6289 "\t{$src2, $dst|$dst, $src2}"),
6290 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6293 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6294 (ins VR128:$src1, i128mem:$src2),
6295 !strconcat(OpcodeStr,
6296 "\t{$src2, $dst|$dst, $src2}"),
6299 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6303 let ExeDomain = SSEPackedDouble in
6304 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64,
6305 int_x86_sse41_blendvpd>;
6306 let ExeDomain = SSEPackedSingle in
6307 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32,
6308 int_x86_sse41_blendvps>;
6309 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64,
6310 int_x86_sse41_pblendvb>;
6312 let Predicates = [HasSSE41] in {
6313 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6314 (v16i8 VR128:$src2))),
6315 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6316 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6317 (v4i32 VR128:$src2))),
6318 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6319 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6320 (v4f32 VR128:$src2))),
6321 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6322 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6323 (v2i64 VR128:$src2))),
6324 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6325 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6326 (v2f64 VR128:$src2))),
6327 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6330 let Predicates = [HasAVX] in
6331 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6332 "vmovntdqa\t{$src, $dst|$dst, $src}",
6333 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6335 let Predicates = [HasAVX2] in
6336 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6337 "vmovntdqa\t{$src, $dst|$dst, $src}",
6338 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6340 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6341 "movntdqa\t{$src, $dst|$dst, $src}",
6342 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6345 //===----------------------------------------------------------------------===//
6346 // SSE4.2 - Compare Instructions
6347 //===----------------------------------------------------------------------===//
6349 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6350 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6351 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6352 X86MemOperand x86memop, bit Is2Addr = 1> {
6353 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6354 (ins RC:$src1, RC:$src2),
6356 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6357 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6358 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6360 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6361 (ins RC:$src1, x86memop:$src2),
6363 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6364 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6366 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6369 let Predicates = [HasAVX] in
6370 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6371 memopv2i64, i128mem, 0>, VEX_4V;
6373 let Predicates = [HasAVX2] in
6374 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6375 memopv4i64, i256mem, 0>, VEX_4V;
6377 let Constraints = "$src1 = $dst" in
6378 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6379 memopv2i64, i128mem>;
6381 //===----------------------------------------------------------------------===//
6382 // SSE4.2 - String/text Processing Instructions
6383 //===----------------------------------------------------------------------===//
6385 // Packed Compare Implicit Length Strings, Return Mask
6386 multiclass pseudo_pcmpistrm<string asm> {
6387 def REG : PseudoI<(outs VR128:$dst),
6388 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6389 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6391 def MEM : PseudoI<(outs VR128:$dst),
6392 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6393 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6394 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6397 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6398 let AddedComplexity = 1 in
6399 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6400 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6403 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6404 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6405 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6406 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6408 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6409 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6410 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6413 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6414 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6415 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6416 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6418 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6419 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6420 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6423 // Packed Compare Explicit Length Strings, Return Mask
6424 multiclass pseudo_pcmpestrm<string asm> {
6425 def REG : PseudoI<(outs VR128:$dst),
6426 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6427 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6428 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6429 def MEM : PseudoI<(outs VR128:$dst),
6430 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6431 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6432 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6435 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6436 let AddedComplexity = 1 in
6437 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6438 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6441 let Predicates = [HasAVX],
6442 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6443 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6444 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6445 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6447 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6448 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6449 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6452 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6453 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6454 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6455 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6457 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6458 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6459 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6462 // Packed Compare Implicit Length Strings, Return Index
6463 let Defs = [ECX, EFLAGS] in {
6464 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6465 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6466 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6467 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6468 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6469 (implicit EFLAGS)]>, OpSize;
6470 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6471 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6472 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6473 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6474 (implicit EFLAGS)]>, OpSize;
6478 let Predicates = [HasAVX] in {
6479 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6481 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6483 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6485 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6487 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6489 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6493 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6494 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6495 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6496 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6497 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6498 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6500 // Packed Compare Explicit Length Strings, Return Index
6501 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6502 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6503 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6504 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6505 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6506 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6507 (implicit EFLAGS)]>, OpSize;
6508 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6509 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6510 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6512 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6513 (implicit EFLAGS)]>, OpSize;
6517 let Predicates = [HasAVX] in {
6518 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6520 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6522 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6524 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6526 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6528 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6532 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6533 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6534 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6535 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6536 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6537 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6539 //===----------------------------------------------------------------------===//
6540 // SSE4.2 - CRC Instructions
6541 //===----------------------------------------------------------------------===//
6543 // No CRC instructions have AVX equivalents
6545 // crc intrinsic instruction
6546 // This set of instructions are only rm, the only difference is the size
6548 let Constraints = "$src1 = $dst" in {
6549 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6550 (ins GR32:$src1, i8mem:$src2),
6551 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6553 (int_x86_sse42_crc32_32_8 GR32:$src1,
6554 (load addr:$src2)))]>;
6555 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6556 (ins GR32:$src1, GR8:$src2),
6557 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6559 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6560 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6561 (ins GR32:$src1, i16mem:$src2),
6562 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6564 (int_x86_sse42_crc32_32_16 GR32:$src1,
6565 (load addr:$src2)))]>,
6567 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6568 (ins GR32:$src1, GR16:$src2),
6569 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6571 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6573 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6574 (ins GR32:$src1, i32mem:$src2),
6575 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6577 (int_x86_sse42_crc32_32_32 GR32:$src1,
6578 (load addr:$src2)))]>;
6579 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6580 (ins GR32:$src1, GR32:$src2),
6581 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6583 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6584 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6585 (ins GR64:$src1, i8mem:$src2),
6586 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6588 (int_x86_sse42_crc32_64_8 GR64:$src1,
6589 (load addr:$src2)))]>,
6591 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6592 (ins GR64:$src1, GR8:$src2),
6593 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6595 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6597 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6598 (ins GR64:$src1, i64mem:$src2),
6599 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6601 (int_x86_sse42_crc32_64_64 GR64:$src1,
6602 (load addr:$src2)))]>,
6604 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6605 (ins GR64:$src1, GR64:$src2),
6606 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6608 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6612 //===----------------------------------------------------------------------===//
6613 // AES-NI Instructions
6614 //===----------------------------------------------------------------------===//
6616 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
6617 Intrinsic IntId128, bit Is2Addr = 1> {
6618 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
6619 (ins VR128:$src1, VR128:$src2),
6621 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6622 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6623 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6625 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
6626 (ins VR128:$src1, i128mem:$src2),
6628 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6629 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6631 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
6634 // Perform One Round of an AES Encryption/Decryption Flow
6635 let Predicates = [HasAVX, HasAES] in {
6636 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
6637 int_x86_aesni_aesenc, 0>, VEX_4V;
6638 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
6639 int_x86_aesni_aesenclast, 0>, VEX_4V;
6640 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
6641 int_x86_aesni_aesdec, 0>, VEX_4V;
6642 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
6643 int_x86_aesni_aesdeclast, 0>, VEX_4V;
6646 let Constraints = "$src1 = $dst" in {
6647 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
6648 int_x86_aesni_aesenc>;
6649 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
6650 int_x86_aesni_aesenclast>;
6651 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
6652 int_x86_aesni_aesdec>;
6653 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
6654 int_x86_aesni_aesdeclast>;
6657 // Perform the AES InvMixColumn Transformation
6658 let Predicates = [HasAVX, HasAES] in {
6659 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6661 "vaesimc\t{$src1, $dst|$dst, $src1}",
6663 (int_x86_aesni_aesimc VR128:$src1))]>,
6665 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6666 (ins i128mem:$src1),
6667 "vaesimc\t{$src1, $dst|$dst, $src1}",
6668 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
6671 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6673 "aesimc\t{$src1, $dst|$dst, $src1}",
6675 (int_x86_aesni_aesimc VR128:$src1))]>,
6677 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6678 (ins i128mem:$src1),
6679 "aesimc\t{$src1, $dst|$dst, $src1}",
6680 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
6683 // AES Round Key Generation Assist
6684 let Predicates = [HasAVX, HasAES] in {
6685 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6686 (ins VR128:$src1, i8imm:$src2),
6687 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6689 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6691 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6692 (ins i128mem:$src1, i8imm:$src2),
6693 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6695 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
6698 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6699 (ins VR128:$src1, i8imm:$src2),
6700 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6702 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6704 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6705 (ins i128mem:$src1, i8imm:$src2),
6706 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6708 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
6711 //===----------------------------------------------------------------------===//
6712 // CLMUL Instructions
6713 //===----------------------------------------------------------------------===//
6715 // Carry-less Multiplication instructions
6716 let neverHasSideEffects = 1 in {
6717 // AVX carry-less Multiplication instructions
6718 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6719 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6720 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6724 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6725 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6726 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6729 let Constraints = "$src1 = $dst" in {
6730 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6731 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6732 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6736 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6737 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6738 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6740 } // Constraints = "$src1 = $dst"
6741 } // neverHasSideEffects = 1
6744 multiclass pclmul_alias<string asm, int immop> {
6745 def : InstAlias<!strconcat("pclmul", asm,
6746 "dq {$src, $dst|$dst, $src}"),
6747 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
6749 def : InstAlias<!strconcat("pclmul", asm,
6750 "dq {$src, $dst|$dst, $src}"),
6751 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
6753 def : InstAlias<!strconcat("vpclmul", asm,
6754 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6755 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
6757 def : InstAlias<!strconcat("vpclmul", asm,
6758 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6759 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
6761 defm : pclmul_alias<"hqhq", 0x11>;
6762 defm : pclmul_alias<"hqlq", 0x01>;
6763 defm : pclmul_alias<"lqhq", 0x10>;
6764 defm : pclmul_alias<"lqlq", 0x00>;
6766 //===----------------------------------------------------------------------===//
6768 //===----------------------------------------------------------------------===//
6770 //===----------------------------------------------------------------------===//
6771 // VBROADCAST - Load from memory and broadcast to all elements of the
6772 // destination operand
6774 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
6775 X86MemOperand x86memop, Intrinsic Int> :
6776 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
6777 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6778 [(set RC:$dst, (Int addr:$src))]>, VEX;
6780 // AVX2 adds register forms
6781 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
6783 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
6784 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6785 [(set RC:$dst, (Int VR128:$src))]>, VEX;
6787 let ExeDomain = SSEPackedSingle in {
6788 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
6789 int_x86_avx_vbroadcast_ss>;
6790 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
6791 int_x86_avx_vbroadcast_ss_256>;
6793 let ExeDomain = SSEPackedDouble in
6794 def VBROADCASTSDrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
6795 int_x86_avx_vbroadcast_sd_256>;
6796 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
6797 int_x86_avx_vbroadcastf128_pd_256>;
6799 let ExeDomain = SSEPackedSingle in {
6800 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
6801 int_x86_avx2_vbroadcast_ss_ps>;
6802 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
6803 int_x86_avx2_vbroadcast_ss_ps_256>;
6805 let ExeDomain = SSEPackedDouble in
6806 def VBROADCASTSDrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
6807 int_x86_avx2_vbroadcast_sd_pd_256>;
6809 let Predicates = [HasAVX2] in
6810 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
6811 int_x86_avx2_vbroadcasti128>;
6813 let Predicates = [HasAVX] in
6814 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
6815 (VBROADCASTF128 addr:$src)>;
6818 //===----------------------------------------------------------------------===//
6819 // VINSERTF128 - Insert packed floating-point values
6821 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
6822 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
6823 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
6824 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6827 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
6828 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
6829 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6833 let Predicates = [HasAVX] in {
6834 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
6835 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6836 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
6837 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6838 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
6839 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6842 //===----------------------------------------------------------------------===//
6843 // VEXTRACTF128 - Extract packed floating-point values
6845 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
6846 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
6847 (ins VR256:$src1, i8imm:$src2),
6848 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6851 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
6852 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
6853 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6857 let Predicates = [HasAVX] in {
6858 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
6859 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6860 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
6861 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6862 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
6863 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6866 //===----------------------------------------------------------------------===//
6867 // VMASKMOV - Conditional SIMD Packed Loads and Stores
6869 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
6870 Intrinsic IntLd, Intrinsic IntLd256,
6871 Intrinsic IntSt, Intrinsic IntSt256> {
6872 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
6873 (ins VR128:$src1, f128mem:$src2),
6874 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6875 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
6877 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
6878 (ins VR256:$src1, f256mem:$src2),
6879 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6880 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
6882 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
6883 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
6884 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6885 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
6886 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
6887 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
6888 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6889 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
6892 let ExeDomain = SSEPackedSingle in
6893 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
6894 int_x86_avx_maskload_ps,
6895 int_x86_avx_maskload_ps_256,
6896 int_x86_avx_maskstore_ps,
6897 int_x86_avx_maskstore_ps_256>;
6898 let ExeDomain = SSEPackedDouble in
6899 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
6900 int_x86_avx_maskload_pd,
6901 int_x86_avx_maskload_pd_256,
6902 int_x86_avx_maskstore_pd,
6903 int_x86_avx_maskstore_pd_256>;
6905 //===----------------------------------------------------------------------===//
6906 // VPERMIL - Permute Single and Double Floating-Point Values
6908 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
6909 RegisterClass RC, X86MemOperand x86memop_f,
6910 X86MemOperand x86memop_i, PatFrag i_frag,
6911 Intrinsic IntVar, ValueType vt> {
6912 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
6913 (ins RC:$src1, RC:$src2),
6914 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6915 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
6916 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
6917 (ins RC:$src1, x86memop_i:$src2),
6918 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6919 [(set RC:$dst, (IntVar RC:$src1,
6920 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
6922 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
6923 (ins RC:$src1, i8imm:$src2),
6924 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6925 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
6926 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
6927 (ins x86memop_f:$src1, i8imm:$src2),
6928 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6930 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
6933 let ExeDomain = SSEPackedSingle in {
6934 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
6935 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
6936 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
6937 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>;
6939 let ExeDomain = SSEPackedDouble in {
6940 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
6941 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
6942 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
6943 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>;
6946 let Predicates = [HasAVX] in {
6947 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
6948 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6949 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
6950 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6951 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
6953 (VPERMILPSYmi addr:$src1, imm:$imm)>;
6954 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
6955 (VPERMILPDYmi addr:$src1, imm:$imm)>;
6957 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
6958 (VPERMILPDri VR128:$src1, imm:$imm)>;
6959 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
6960 (VPERMILPDmi addr:$src1, imm:$imm)>;
6963 //===----------------------------------------------------------------------===//
6964 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
6966 let ExeDomain = SSEPackedSingle in {
6967 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
6968 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
6969 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6970 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
6971 (i8 imm:$src3))))]>, VEX_4V;
6972 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
6973 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
6974 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6975 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
6976 (i8 imm:$src3)))]>, VEX_4V;
6979 let Predicates = [HasAVX] in {
6980 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6981 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6982 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6983 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6984 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6985 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6986 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6987 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6988 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6989 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6991 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1,
6992 (memopv8f32 addr:$src2), (i8 imm:$imm))),
6993 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
6994 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
6995 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
6996 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
6997 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
6998 (memopv4i64 addr:$src2), (i8 imm:$imm))),
6999 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7000 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7001 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7002 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7003 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7004 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7005 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7006 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7007 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7008 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7011 //===----------------------------------------------------------------------===//
7012 // VZERO - Zero YMM registers
7014 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7015 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7016 // Zero All YMM registers
7017 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7018 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7020 // Zero Upper bits of YMM registers
7021 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7022 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7025 //===----------------------------------------------------------------------===//
7026 // Half precision conversion instructions
7027 //===----------------------------------------------------------------------===//
7028 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7029 let Predicates = [HasAVX, HasF16C] in {
7030 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7031 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7032 [(set RC:$dst, (Int VR128:$src))]>,
7034 let neverHasSideEffects = 1, mayLoad = 1 in
7035 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7036 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7040 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7041 let Predicates = [HasAVX, HasF16C] in {
7042 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7043 (ins RC:$src1, i32i8imm:$src2),
7044 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7045 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7047 let neverHasSideEffects = 1, mayLoad = 1 in
7048 def mr : Ii8<0x1D, MRMDestMem, (outs x86memop:$dst),
7049 (ins RC:$src1, i32i8imm:$src2),
7050 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7055 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7056 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7057 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7058 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7060 //===----------------------------------------------------------------------===//
7061 // AVX2 Instructions
7062 //===----------------------------------------------------------------------===//
7064 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7065 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7066 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7067 X86MemOperand x86memop> {
7068 let isCommutable = 1 in
7069 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7070 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7071 !strconcat(OpcodeStr,
7072 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7073 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7075 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7076 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7077 !strconcat(OpcodeStr,
7078 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7081 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7085 let isCommutable = 0 in {
7086 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7087 VR128, memopv2i64, i128mem>;
7088 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7089 VR256, memopv4i64, i256mem>;
7092 //===----------------------------------------------------------------------===//
7093 // VPBROADCAST - Load from memory and broadcast to all elements of the
7094 // destination operand
7096 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7097 X86MemOperand x86memop, PatFrag ld_frag,
7098 Intrinsic Int128, Intrinsic Int256> {
7099 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7100 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7101 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7102 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7103 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7105 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7106 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7107 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7108 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7109 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7110 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7112 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7115 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7116 int_x86_avx2_pbroadcastb_128,
7117 int_x86_avx2_pbroadcastb_256>;
7118 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7119 int_x86_avx2_pbroadcastw_128,
7120 int_x86_avx2_pbroadcastw_256>;
7121 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7122 int_x86_avx2_pbroadcastd_128,
7123 int_x86_avx2_pbroadcastd_256>;
7124 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7125 int_x86_avx2_pbroadcastq_128,
7126 int_x86_avx2_pbroadcastq_256>;
7128 let Predicates = [HasAVX2] in {
7129 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7130 (VPBROADCASTBrm addr:$src)>;
7131 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7132 (VPBROADCASTBYrm addr:$src)>;
7133 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7134 (VPBROADCASTWrm addr:$src)>;
7135 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7136 (VPBROADCASTWYrm addr:$src)>;
7137 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7138 (VPBROADCASTDrm addr:$src)>;
7139 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7140 (VPBROADCASTDYrm addr:$src)>;
7141 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7142 (VPBROADCASTQrm addr:$src)>;
7143 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7144 (VPBROADCASTQYrm addr:$src)>;
7147 // AVX1 broadcast patterns
7148 let Predicates = [HasAVX] in {
7149 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7150 (VBROADCASTSSYrm addr:$src)>;
7151 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7152 (VBROADCASTSDrm addr:$src)>;
7153 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7154 (VBROADCASTSSYrm addr:$src)>;
7155 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7156 (VBROADCASTSDrm addr:$src)>;
7158 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7159 (VBROADCASTSSrm addr:$src)>;
7160 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7161 (VBROADCASTSSrm addr:$src)>;
7164 //===----------------------------------------------------------------------===//
7165 // VPERM - Permute instructions
7168 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7170 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7171 (ins VR256:$src1, VR256:$src2),
7172 !strconcat(OpcodeStr,
7173 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7174 [(set VR256:$dst, (Int VR256:$src1, VR256:$src2))]>, VEX_4V;
7175 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7176 (ins VR256:$src1, i256mem:$src2),
7177 !strconcat(OpcodeStr,
7178 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7179 [(set VR256:$dst, (Int VR256:$src1,
7180 (bitconvert (mem_frag addr:$src2))))]>,
7184 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, int_x86_avx2_permd>;
7185 let ExeDomain = SSEPackedSingle in
7186 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, int_x86_avx2_permps>;
7188 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7190 def Yrr : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7191 (ins VR256:$src1, i8imm:$src2),
7192 !strconcat(OpcodeStr,
7193 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7194 [(set VR256:$dst, (Int VR256:$src1, imm:$src2))]>, VEX;
7195 def Yrm : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7196 (ins i256mem:$src1, i8imm:$src2),
7197 !strconcat(OpcodeStr,
7198 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7199 [(set VR256:$dst, (Int (mem_frag addr:$src1), imm:$src2))]>,
7203 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, int_x86_avx2_permq>,
7205 let ExeDomain = SSEPackedDouble in
7206 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, int_x86_avx2_permpd>,
7209 //===----------------------------------------------------------------------===//
7210 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7212 let AddedComplexity = 1 in {
7213 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7214 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7215 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7216 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7217 (i8 imm:$src3))))]>, VEX_4V;
7218 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7219 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7220 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7221 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7222 (i8 imm:$src3)))]>, VEX_4V;
7225 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7226 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7227 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7228 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7229 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7230 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7231 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7233 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7235 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7236 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7237 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7238 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7239 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7241 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7245 //===----------------------------------------------------------------------===//
7246 // VINSERTI128 - Insert packed integer values
7248 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7249 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7250 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7252 (int_x86_avx2_vinserti128 VR256:$src1, VR128:$src2, imm:$src3))]>,
7254 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7255 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7256 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7258 (int_x86_avx2_vinserti128 VR256:$src1, (memopv2i64 addr:$src2),
7259 imm:$src3))]>, VEX_4V;
7261 let Predicates = [HasAVX2] in {
7262 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7264 (VINSERTI128rr VR256:$src1, VR128:$src2,
7265 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7266 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7268 (VINSERTI128rr VR256:$src1, VR128:$src2,
7269 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7270 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7272 (VINSERTI128rr VR256:$src1, VR128:$src2,
7273 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7274 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7276 (VINSERTI128rr VR256:$src1, VR128:$src2,
7277 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7281 let Predicates = [HasAVX] in {
7282 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7284 (VINSERTF128rr VR256:$src1, VR128:$src2,
7285 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7286 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7288 (VINSERTF128rr VR256:$src1, VR128:$src2,
7289 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7290 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7292 (VINSERTF128rr VR256:$src1, VR128:$src2,
7293 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7294 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7296 (VINSERTF128rr VR256:$src1, VR128:$src2,
7297 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7298 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7300 (VINSERTF128rr VR256:$src1, VR128:$src2,
7301 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7302 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7304 (VINSERTF128rr VR256:$src1, VR128:$src2,
7305 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7308 //===----------------------------------------------------------------------===//
7309 // VEXTRACTI128 - Extract packed integer values
7311 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7312 (ins VR256:$src1, i8imm:$src2),
7313 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7315 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7317 let neverHasSideEffects = 1, mayStore = 1 in
7318 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7319 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7320 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7322 let Predicates = [HasAVX2] in {
7323 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7324 (v2i64 (VEXTRACTI128rr
7325 (v4i64 VR256:$src1),
7326 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7327 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7328 (v4i32 (VEXTRACTI128rr
7329 (v8i32 VR256:$src1),
7330 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7331 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7332 (v8i16 (VEXTRACTI128rr
7333 (v16i16 VR256:$src1),
7334 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7335 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7336 (v16i8 (VEXTRACTI128rr
7337 (v32i8 VR256:$src1),
7338 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7342 let Predicates = [HasAVX] in {
7343 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7344 (v4f32 (VEXTRACTF128rr
7345 (v8f32 VR256:$src1),
7346 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7347 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7348 (v2f64 (VEXTRACTF128rr
7349 (v4f64 VR256:$src1),
7350 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7351 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7352 (v2i64 (VEXTRACTF128rr
7353 (v4i64 VR256:$src1),
7354 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7355 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7356 (v4i32 (VEXTRACTF128rr
7357 (v8i32 VR256:$src1),
7358 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7359 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7360 (v8i16 (VEXTRACTF128rr
7361 (v16i16 VR256:$src1),
7362 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7363 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7364 (v16i8 (VEXTRACTF128rr
7365 (v32i8 VR256:$src1),
7366 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7369 //===----------------------------------------------------------------------===//
7370 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7372 multiclass avx2_pmovmask<string OpcodeStr,
7373 Intrinsic IntLd128, Intrinsic IntLd256,
7374 Intrinsic IntSt128, Intrinsic IntSt256> {
7375 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7376 (ins VR128:$src1, i128mem:$src2),
7377 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7378 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7379 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7380 (ins VR256:$src1, i256mem:$src2),
7381 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7382 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7383 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7384 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7385 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7386 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7387 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7388 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7389 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7390 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7393 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
7394 int_x86_avx2_maskload_d,
7395 int_x86_avx2_maskload_d_256,
7396 int_x86_avx2_maskstore_d,
7397 int_x86_avx2_maskstore_d_256>;
7398 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
7399 int_x86_avx2_maskload_q,
7400 int_x86_avx2_maskload_q_256,
7401 int_x86_avx2_maskstore_q,
7402 int_x86_avx2_maskstore_q_256>, VEX_W;
7405 //===----------------------------------------------------------------------===//
7406 // Variable Bit Shifts
7408 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
7409 ValueType vt128, ValueType vt256> {
7410 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7411 (ins VR128:$src1, VR128:$src2),
7412 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7414 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
7416 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
7417 (ins VR128:$src1, i128mem:$src2),
7418 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7420 (vt128 (OpNode VR128:$src1,
7421 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
7423 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7424 (ins VR256:$src1, VR256:$src2),
7425 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7427 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
7429 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7430 (ins VR256:$src1, i256mem:$src2),
7431 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7433 (vt256 (OpNode VR256:$src1,
7434 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
7438 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
7439 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
7440 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
7441 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
7442 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;