1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
75 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
77 //===----------------------------------------------------------------------===//
78 // SSE Complex Patterns
79 //===----------------------------------------------------------------------===//
81 // These are 'extloads' from a scalar to the low element of a vector, zeroing
82 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
84 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
85 [SDNPHasChain, SDNPMayLoad]>;
86 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
87 [SDNPHasChain, SDNPMayLoad]>;
89 def ssmem : Operand<v4f32> {
90 let PrintMethod = "printf32mem";
91 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
92 let ParserMatchClass = X86MemAsmOperand;
94 def sdmem : Operand<v2f64> {
95 let PrintMethod = "printf64mem";
96 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
97 let ParserMatchClass = X86MemAsmOperand;
100 //===----------------------------------------------------------------------===//
101 // SSE pattern fragments
102 //===----------------------------------------------------------------------===//
104 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
105 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
106 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
107 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
109 // Like 'store', but always requires vector alignment.
110 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
111 (store node:$val, node:$ptr), [{
112 return cast<StoreSDNode>(N)->getAlignment() >= 16;
115 // Like 'load', but always requires vector alignment.
116 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
117 return cast<LoadSDNode>(N)->getAlignment() >= 16;
120 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
121 (f32 (alignedload node:$ptr))>;
122 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
123 (f64 (alignedload node:$ptr))>;
124 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
125 (v4f32 (alignedload node:$ptr))>;
126 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
127 (v2f64 (alignedload node:$ptr))>;
128 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
129 (v4i32 (alignedload node:$ptr))>;
130 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
131 (v2i64 (alignedload node:$ptr))>;
133 // Like 'load', but uses special alignment checks suitable for use in
134 // memory operands in most SSE instructions, which are required to
135 // be naturally aligned on some targets but not on others. If the subtarget
136 // allows unaligned accesses, match any load, though this may require
137 // setting a feature bit in the processor (on startup, for example).
138 // Opteron 10h and later implement such a feature.
139 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
140 return Subtarget->hasVectorUAMem()
141 || cast<LoadSDNode>(N)->getAlignment() >= 16;
144 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
145 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
146 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
147 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
148 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
149 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
150 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
152 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
154 // FIXME: 8 byte alignment for mmx reads is not required
155 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
156 return cast<LoadSDNode>(N)->getAlignment() >= 8;
159 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
160 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
161 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
162 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
165 // Like 'store', but requires the non-temporal bit to be set
166 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
167 (st node:$val, node:$ptr), [{
168 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
169 return ST->isNonTemporal();
173 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
174 (st node:$val, node:$ptr), [{
175 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
176 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
177 ST->getAddressingMode() == ISD::UNINDEXED &&
178 ST->getAlignment() >= 16;
182 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
183 (st node:$val, node:$ptr), [{
184 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
185 return ST->isNonTemporal() &&
186 ST->getAlignment() < 16;
190 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
191 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
192 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
193 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
194 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
195 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
197 def vzmovl_v2i64 : PatFrag<(ops node:$src),
198 (bitconvert (v2i64 (X86vzmovl
199 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
200 def vzmovl_v4i32 : PatFrag<(ops node:$src),
201 (bitconvert (v4i32 (X86vzmovl
202 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
204 def vzload_v2i64 : PatFrag<(ops node:$src),
205 (bitconvert (v2i64 (X86vzload node:$src)))>;
208 def fp32imm0 : PatLeaf<(f32 fpimm), [{
209 return N->isExactlyValue(+0.0);
212 // BYTE_imm - Transform bit immediates into byte immediates.
213 def BYTE_imm : SDNodeXForm<imm, [{
214 // Transformation function: imm >> 3
215 return getI32Imm(N->getZExtValue() >> 3);
218 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
220 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
221 return getI8Imm(X86::getShuffleSHUFImmediate(N));
224 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
226 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
227 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
230 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
232 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
233 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
236 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
238 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
239 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
242 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
243 (vector_shuffle node:$lhs, node:$rhs), [{
244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
245 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
248 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
249 (vector_shuffle node:$lhs, node:$rhs), [{
250 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
253 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
254 (vector_shuffle node:$lhs, node:$rhs), [{
255 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
258 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
259 (vector_shuffle node:$lhs, node:$rhs), [{
260 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
263 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
264 (vector_shuffle node:$lhs, node:$rhs), [{
265 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
268 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
269 (vector_shuffle node:$lhs, node:$rhs), [{
270 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
273 def movl : PatFrag<(ops node:$lhs, node:$rhs),
274 (vector_shuffle node:$lhs, node:$rhs), [{
275 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
278 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
279 (vector_shuffle node:$lhs, node:$rhs), [{
280 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
283 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
284 (vector_shuffle node:$lhs, node:$rhs), [{
285 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
288 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
289 (vector_shuffle node:$lhs, node:$rhs), [{
290 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
293 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
294 (vector_shuffle node:$lhs, node:$rhs), [{
295 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
298 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
299 (vector_shuffle node:$lhs, node:$rhs), [{
300 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
303 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
304 (vector_shuffle node:$lhs, node:$rhs), [{
305 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
308 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
309 (vector_shuffle node:$lhs, node:$rhs), [{
310 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
311 }], SHUFFLE_get_shuf_imm>;
313 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
314 (vector_shuffle node:$lhs, node:$rhs), [{
315 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
316 }], SHUFFLE_get_shuf_imm>;
318 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
319 (vector_shuffle node:$lhs, node:$rhs), [{
320 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
321 }], SHUFFLE_get_pshufhw_imm>;
323 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
324 (vector_shuffle node:$lhs, node:$rhs), [{
325 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
326 }], SHUFFLE_get_pshuflw_imm>;
328 def palign : PatFrag<(ops node:$lhs, node:$rhs),
329 (vector_shuffle node:$lhs, node:$rhs), [{
330 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
331 }], SHUFFLE_get_palign_imm>;
333 //===----------------------------------------------------------------------===//
334 // SSE scalar FP Instructions
335 //===----------------------------------------------------------------------===//
337 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
338 // instruction selection into a branch sequence.
339 let Uses = [EFLAGS], usesCustomInserter = 1 in {
340 def CMOV_FR32 : I<0, Pseudo,
341 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
342 "#CMOV_FR32 PSEUDO!",
343 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
345 def CMOV_FR64 : I<0, Pseudo,
346 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
347 "#CMOV_FR64 PSEUDO!",
348 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
350 def CMOV_V4F32 : I<0, Pseudo,
351 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
352 "#CMOV_V4F32 PSEUDO!",
354 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
356 def CMOV_V2F64 : I<0, Pseudo,
357 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
358 "#CMOV_V2F64 PSEUDO!",
360 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
362 def CMOV_V2I64 : I<0, Pseudo,
363 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
364 "#CMOV_V2I64 PSEUDO!",
366 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
370 //===----------------------------------------------------------------------===//
371 // SSE 1 & 2 Instructions Classes
372 //===----------------------------------------------------------------------===//
374 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
375 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
376 RegisterClass RC, X86MemOperand memop> {
377 let isCommutable = 1 in {
378 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
379 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
381 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memop:$src2),
382 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
385 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
386 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
387 string asm, string SSEVer, string FPSizeStr,
388 Operand memop, ComplexPattern mem_cpat> {
389 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
390 asm, [(set RC:$dst, (
391 !nameconcat<Intrinsic>("int_x86_sse",
392 !strconcat(SSEVer, !strconcat("_",
393 !strconcat(OpcodeStr, FPSizeStr))))
394 RC:$src1, RC:$src2))]>;
395 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memop:$src2),
396 asm, [(set RC:$dst, (
397 !nameconcat<Intrinsic>("int_x86_sse",
398 !strconcat(SSEVer, !strconcat("_",
399 !strconcat(OpcodeStr, FPSizeStr))))
400 RC:$src1, mem_cpat:$src2))]>;
403 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
404 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
405 RegisterClass RC, ValueType vt,
406 X86MemOperand x86memop, PatFrag mem_frag,
407 Domain d, bit MayLoad = 0> {
408 let isCommutable = 1 in
409 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
410 OpcodeStr, [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))],d>;
411 let mayLoad = MayLoad in
412 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
413 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
414 (mem_frag addr:$src2)))],d>;
417 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
418 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
419 string OpcodeStr, X86MemOperand x86memop,
420 list<dag> pat_rr, list<dag> pat_rm> {
421 let isCommutable = 1 in
422 def rr : PI<opc, MRMSrcReg, (outs RC:$dst),
423 (ins RC:$src1, RC:$src2), OpcodeStr, pat_rr, d>;
424 def rm : PI<opc, MRMSrcMem, (outs RC:$dst),
425 (ins RC:$src1, x86memop:$src2), OpcodeStr, pat_rm, d>;
428 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
429 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
430 string asm, string SSEVer, string FPSizeStr,
431 X86MemOperand memop, PatFrag mem_frag,
433 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
434 asm, [(set RC:$dst, (
435 !nameconcat<Intrinsic>("int_x86_sse",
436 !strconcat(SSEVer, !strconcat("_",
437 !strconcat(OpcodeStr, FPSizeStr))))
438 RC:$src1, RC:$src2))], d>;
439 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memop:$src2),
440 asm, [(set RC:$dst, (
441 !nameconcat<Intrinsic>("int_x86_sse",
442 !strconcat(SSEVer, !strconcat("_",
443 !strconcat(OpcodeStr, FPSizeStr))))
444 RC:$src1, (mem_frag addr:$src2)))], d>;
447 //===----------------------------------------------------------------------===//
449 //===----------------------------------------------------------------------===//
451 // Move Instructions. Register-to-register movss is not used for FR32
452 // register copies because it's a partial register update; FsMOVAPSrr is
453 // used instead. Register-to-register movss is not modeled as an INSERT_SUBREG
454 // because INSERT_SUBREG requires that the insert be implementable in terms of
455 // a copy, and just mentioned, we don't use movss for copies.
456 let Constraints = "$src1 = $dst" in
457 def MOVSSrr : SSI<0x10, MRMSrcReg,
458 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
459 "movss\t{$src2, $dst|$dst, $src2}",
460 [(set (v4f32 VR128:$dst),
461 (movl VR128:$src1, (scalar_to_vector FR32:$src2)))]>;
463 // Extract the low 32-bit value from one vector and insert it into another.
464 let AddedComplexity = 15 in
465 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
466 (MOVSSrr (v4f32 VR128:$src1),
467 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
469 // Implicitly promote a 32-bit scalar to a vector.
470 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
471 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
473 // Loading from memory automatically zeroing upper bits.
474 let canFoldAsLoad = 1, isReMaterializable = 1 in
475 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
476 "movss\t{$src, $dst|$dst, $src}",
477 [(set FR32:$dst, (loadf32 addr:$src))]>;
479 // MOVSSrm zeros the high parts of the register; represent this
480 // with SUBREG_TO_REG.
481 let AddedComplexity = 20 in {
482 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
483 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
484 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
485 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
486 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
487 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
490 // Store scalar value to memory.
491 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
492 "movss\t{$src, $dst|$dst, $src}",
493 [(store FR32:$src, addr:$dst)]>;
495 // Extract and store.
496 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
499 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
501 // Conversion instructions
502 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
503 "cvttss2si\t{$src, $dst|$dst, $src}",
504 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
505 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
506 "cvttss2si\t{$src, $dst|$dst, $src}",
507 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
508 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
509 "cvtsi2ss\t{$src, $dst|$dst, $src}",
510 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
511 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
512 "cvtsi2ss\t{$src, $dst|$dst, $src}",
513 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
515 // Match intrinsics which expect XMM operand(s).
516 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
517 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
518 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
519 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
521 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
522 "cvtss2si\t{$src, $dst|$dst, $src}",
523 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
524 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
525 "cvtss2si\t{$src, $dst|$dst, $src}",
526 [(set GR32:$dst, (int_x86_sse_cvtss2si
527 (load addr:$src)))]>;
529 // Match intrinsics which expect MM and XMM operand(s).
530 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
531 "cvtps2pi\t{$src, $dst|$dst, $src}",
532 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
533 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
534 "cvtps2pi\t{$src, $dst|$dst, $src}",
535 [(set VR64:$dst, (int_x86_sse_cvtps2pi
536 (load addr:$src)))]>;
537 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
538 "cvttps2pi\t{$src, $dst|$dst, $src}",
539 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
540 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
541 "cvttps2pi\t{$src, $dst|$dst, $src}",
542 [(set VR64:$dst, (int_x86_sse_cvttps2pi
543 (load addr:$src)))]>;
544 let Constraints = "$src1 = $dst" in {
545 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
546 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
547 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
548 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
550 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
551 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
552 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
553 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
554 (load addr:$src2)))]>;
557 // Aliases for intrinsics
558 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
559 "cvttss2si\t{$src, $dst|$dst, $src}",
561 (int_x86_sse_cvttss2si VR128:$src))]>;
562 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
563 "cvttss2si\t{$src, $dst|$dst, $src}",
565 (int_x86_sse_cvttss2si(load addr:$src)))]>;
567 let Constraints = "$src1 = $dst" in {
568 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
569 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
570 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
571 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
573 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
574 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
575 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
576 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
577 (loadi32 addr:$src2)))]>;
580 // Comparison instructions
581 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
582 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
583 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
584 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
586 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
587 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
588 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
590 // Accept explicit immediate argument form instead of comparison code.
591 let isAsmParserOnly = 1 in {
592 def CMPSSrr_alt : SSIi8<0xC2, MRMSrcReg,
593 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
594 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
596 def CMPSSrm_alt : SSIi8<0xC2, MRMSrcMem,
597 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
598 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
602 let Defs = [EFLAGS] in {
603 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
604 "ucomiss\t{$src2, $src1|$src1, $src2}",
605 [(set EFLAGS, (X86cmp FR32:$src1, FR32:$src2))]>;
606 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
607 "ucomiss\t{$src2, $src1|$src1, $src2}",
608 [(set EFLAGS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>;
610 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
611 "comiss\t{$src2, $src1|$src1, $src2}", []>;
612 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
613 "comiss\t{$src2, $src1|$src1, $src2}", []>;
617 // Aliases to match intrinsics which expect XMM operand(s).
618 let Constraints = "$src1 = $dst" in {
619 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
621 (ins VR128:$src1, VR128:$src, SSECC:$cc),
622 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
623 [(set VR128:$dst, (int_x86_sse_cmp_ss
625 VR128:$src, imm:$cc))]>;
626 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
628 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
629 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
630 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
631 (load addr:$src), imm:$cc))]>;
634 let Defs = [EFLAGS] in {
635 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
636 "ucomiss\t{$src2, $src1|$src1, $src2}",
637 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
639 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
640 "ucomiss\t{$src2, $src1|$src1, $src2}",
641 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
642 (load addr:$src2)))]>;
644 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
645 "comiss\t{$src2, $src1|$src1, $src2}",
646 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
648 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
649 "comiss\t{$src2, $src1|$src1, $src2}",
650 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
651 (load addr:$src2)))]>;
654 // Aliases of packed SSE1 instructions for scalar use. These all have names
655 // that start with 'Fs'.
657 // Alias instructions that map fld0 to pxor for sse.
658 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
660 // FIXME: Set encoding to pseudo!
661 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
662 [(set FR32:$dst, fp32imm0)]>,
663 Requires<[HasSSE1]>, TB, OpSize;
665 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
667 let neverHasSideEffects = 1 in
668 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
669 "movaps\t{$src, $dst|$dst, $src}", []>;
671 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
673 let canFoldAsLoad = 1, isReMaterializable = 1 in
674 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
675 "movaps\t{$src, $dst|$dst, $src}",
676 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
678 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
680 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
681 SDNode OpNode, bit MayLoad = 0> {
682 let isAsmParserOnly = 1 in {
683 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
684 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR32,
685 f32, f128mem, memopfsf32, SSEPackedSingle, MayLoad>, VEX_4V;
687 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
688 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR64,
689 f64, f128mem, memopfsf64, SSEPackedDouble, MayLoad>, OpSize,
693 let Constraints = "$src1 = $dst" in {
694 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
695 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, FR32, f32,
696 f128mem, memopfsf32, SSEPackedSingle, MayLoad>, TB;
698 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
699 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, FR64, f64,
700 f128mem, memopfsf64, SSEPackedDouble, MayLoad>, TB, OpSize;
704 // Alias bitwise logical operations using SSE logical ops on packed FP values.
705 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
706 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
707 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
709 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
710 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1>;
712 /// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
715 /// In addition, we also have a special variant of the scalar form here to
716 /// represent the associated intrinsic operation. This form is unlike the
717 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
718 /// and leaves the top elements unmodified (therefore these cannot be commuted).
720 /// These three forms can each be reg+reg or reg+mem, so there are a total of
721 /// six "instructions".
723 multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
726 let isAsmParserOnly = 1 in {
727 defm V#NAME#SS : sse12_fp_scalar<opc,
728 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
729 OpNode, FR32, f32mem>, XS, VEX_4V;
731 defm V#NAME#SD : sse12_fp_scalar<opc,
732 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
733 OpNode, FR64, f64mem>, XD, VEX_4V;
735 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
736 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
737 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
740 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
741 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
742 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
745 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
746 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
747 "", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
749 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
750 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
751 "2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
754 let Constraints = "$src1 = $dst" in {
755 defm SS : sse12_fp_scalar<opc,
756 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
757 OpNode, FR32, f32mem>, XS;
759 defm SD : sse12_fp_scalar<opc,
760 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
761 OpNode, FR64, f64mem>, XD;
763 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
764 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
765 f128mem, memopv4f32, SSEPackedSingle>, TB;
767 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
768 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
769 f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
771 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
772 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
773 "", "_ss", ssmem, sse_load_f32>, XS;
775 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
776 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
777 "2", "_sd", sdmem, sse_load_f64>, XD;
781 // Arithmetic instructions
782 defm ADD : basic_sse12_fp_binop_rm<0x58, "add", fadd>;
783 defm MUL : basic_sse12_fp_binop_rm<0x59, "mul", fmul>;
785 let isCommutable = 0 in {
786 defm SUB : basic_sse12_fp_binop_rm<0x5C, "sub", fsub>;
787 defm DIV : basic_sse12_fp_binop_rm<0x5E, "div", fdiv>;
790 /// sse12_fp_binop_rm - Other SSE 1 & 2 binops
792 /// This multiclass is like basic_sse12_fp_binop_rm, with the addition of
793 /// instructions for a full-vector intrinsic form. Operations that map
794 /// onto C operators don't use this form since they just use the plain
795 /// vector form instead of having a separate vector intrinsic form.
797 /// This provides a total of eight "instructions".
799 multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
802 let isAsmParserOnly = 1 in {
803 // Scalar operation, reg+reg.
804 defm V#NAME#SS : sse12_fp_scalar<opc,
805 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
806 OpNode, FR32, f32mem>, XS, VEX_4V;
808 defm V#NAME#SD : sse12_fp_scalar<opc,
809 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
810 OpNode, FR64, f64mem>, XD, VEX_4V;
812 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
813 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
814 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
817 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
818 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
819 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
822 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
823 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
824 "", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
826 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
827 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
828 "2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
830 defm V#NAME#PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
831 !strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
832 "", "_ps", f128mem, memopv4f32, SSEPackedSingle>, VEX_4V;
834 defm V#NAME#PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
835 !strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
836 "2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, OpSize,
840 let Constraints = "$src1 = $dst" in {
841 // Scalar operation, reg+reg.
842 defm SS : sse12_fp_scalar<opc,
843 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
844 OpNode, FR32, f32mem>, XS;
845 defm SD : sse12_fp_scalar<opc,
846 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
847 OpNode, FR64, f64mem>, XD;
848 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
849 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
850 f128mem, memopv4f32, SSEPackedSingle>, TB;
852 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
853 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
854 f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
856 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
857 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
858 "", "_ss", ssmem, sse_load_f32>, XS;
860 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
861 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
862 "2", "_sd", sdmem, sse_load_f64>, XD;
864 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
865 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
866 "", "_ps", f128mem, memopv4f32, SSEPackedSingle>, TB;
868 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
869 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
870 "2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
874 let isCommutable = 0 in {
875 defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>;
876 defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
879 //===----------------------------------------------------------------------===//
880 // SSE packed FP Instructions
883 let neverHasSideEffects = 1 in
884 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
885 "movaps\t{$src, $dst|$dst, $src}", []>;
886 let canFoldAsLoad = 1, isReMaterializable = 1 in
887 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
888 "movaps\t{$src, $dst|$dst, $src}",
889 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
891 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
892 "movaps\t{$src, $dst|$dst, $src}",
893 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
895 let neverHasSideEffects = 1 in
896 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
897 "movups\t{$src, $dst|$dst, $src}", []>;
898 let canFoldAsLoad = 1, isReMaterializable = 1 in
899 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
900 "movups\t{$src, $dst|$dst, $src}",
901 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
902 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
903 "movups\t{$src, $dst|$dst, $src}",
904 [(store (v4f32 VR128:$src), addr:$dst)]>;
906 // Intrinsic forms of MOVUPS load and store
907 let canFoldAsLoad = 1, isReMaterializable = 1 in
908 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
909 "movups\t{$src, $dst|$dst, $src}",
910 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
911 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
912 "movups\t{$src, $dst|$dst, $src}",
913 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
915 let Constraints = "$src1 = $dst" in {
916 let AddedComplexity = 20 in {
917 def MOVLPSrm : PSI<0x12, MRMSrcMem,
918 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
919 "movlps\t{$src2, $dst|$dst, $src2}",
922 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
923 def MOVHPSrm : PSI<0x16, MRMSrcMem,
924 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
925 "movhps\t{$src2, $dst|$dst, $src2}",
927 (movlhps VR128:$src1,
928 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
930 } // Constraints = "$src1 = $dst"
933 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
934 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
936 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
937 "movlps\t{$src, $dst|$dst, $src}",
938 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
939 (iPTR 0))), addr:$dst)]>;
941 // v2f64 extract element 1 is always custom lowered to unpack high to low
942 // and extract element 0 so the non-store version isn't too horrible.
943 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
944 "movhps\t{$src, $dst|$dst, $src}",
945 [(store (f64 (vector_extract
946 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
947 (undef)), (iPTR 0))), addr:$dst)]>;
949 let Constraints = "$src1 = $dst" in {
950 let AddedComplexity = 20 in {
951 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
952 (ins VR128:$src1, VR128:$src2),
953 "movlhps\t{$src2, $dst|$dst, $src2}",
955 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
957 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
958 (ins VR128:$src1, VR128:$src2),
959 "movhlps\t{$src2, $dst|$dst, $src2}",
961 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
963 } // Constraints = "$src1 = $dst"
965 let AddedComplexity = 20 in {
966 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
967 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
968 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
969 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
976 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
978 /// In addition, we also have a special variant of the scalar form here to
979 /// represent the associated intrinsic operation. This form is unlike the
980 /// plain scalar form, in that it takes an entire vector (instead of a
981 /// scalar) and leaves the top elements undefined.
983 /// And, we have a special variant form for a full-vector intrinsic form.
985 /// These four forms can each have a reg or a mem operand, so there are a
986 /// total of eight "instructions".
988 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
992 bit Commutable = 0> {
993 // Scalar operation, reg.
994 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
995 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
996 [(set FR32:$dst, (OpNode FR32:$src))]> {
997 let isCommutable = Commutable;
1000 // Scalar operation, mem.
1001 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1002 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1003 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1004 Requires<[HasSSE1, OptForSize]>;
1006 // Vector operation, reg.
1007 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1008 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1009 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
1010 let isCommutable = Commutable;
1013 // Vector operation, mem.
1014 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1015 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1016 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1018 // Intrinsic operation, reg.
1019 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1020 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1021 [(set VR128:$dst, (F32Int VR128:$src))]> {
1022 let isCommutable = Commutable;
1025 // Intrinsic operation, mem.
1026 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1027 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1028 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1030 // Vector intrinsic operation, reg
1031 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1032 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1033 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
1034 let isCommutable = Commutable;
1037 // Vector intrinsic operation, mem
1038 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1039 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1040 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1044 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
1045 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
1047 // Reciprocal approximations. Note that these typically require refinement
1048 // in order to obtain suitable precision.
1049 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
1050 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
1051 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
1052 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
1054 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1056 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1057 SDNode OpNode, int HasPat = 0,
1058 list<list<dag>> Pattern = []> {
1059 let isAsmParserOnly = 1 in {
1060 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1061 !strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1063 !if(HasPat, Pattern[0], // rr
1064 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1066 !if(HasPat, Pattern[2], // rm
1067 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1068 (memopv2i64 addr:$src2)))])>,
1071 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1072 !strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1074 !if(HasPat, Pattern[1], // rr
1075 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1078 !if(HasPat, Pattern[3], // rm
1079 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1080 (memopv2i64 addr:$src2)))])>,
1083 let Constraints = "$src1 = $dst" in {
1084 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1085 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), f128mem,
1086 !if(HasPat, Pattern[0], // rr
1087 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1089 !if(HasPat, Pattern[2], // rm
1090 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1091 (memopv2i64 addr:$src2)))])>, TB;
1093 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1094 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), f128mem,
1095 !if(HasPat, Pattern[1], // rr
1096 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1099 !if(HasPat, Pattern[3], // rm
1100 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1101 (memopv2i64 addr:$src2)))])>,
1107 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1108 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1109 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1110 let isCommutable = 0 in
1111 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1113 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1114 (bc_v2i64 (v4i32 immAllOnesV))),
1117 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1118 (bc_v2i64 (v2f64 VR128:$src2))))],
1120 [(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1121 (bc_v2i64 (v4i32 immAllOnesV))),
1122 (memopv2i64 addr:$src2))))],
1124 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1125 (memopv2i64 addr:$src2)))]]>;
1127 let Constraints = "$src1 = $dst" in {
1128 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1129 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1130 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1131 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1132 VR128:$src, imm:$cc))]>;
1133 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1134 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1135 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1136 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1137 (memop addr:$src), imm:$cc))]>;
1139 // Accept explicit immediate argument form instead of comparison code.
1140 let isAsmParserOnly = 1 in {
1141 def CMPPSrri_alt : PSIi8<0xC2, MRMSrcReg,
1142 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, i8imm:$src2),
1143 "cmpps\t{$src2, $src, $dst|$dst, $src, $src}", []>;
1144 def CMPPSrmi_alt : PSIi8<0xC2, MRMSrcMem,
1145 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, i8imm:$src2),
1146 "cmpps\t{$src2, $src, $dst|$dst, $src, $src}", []>;
1149 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1150 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1151 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1152 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1154 // Shuffle and unpack instructions
1155 let Constraints = "$src1 = $dst" in {
1156 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1157 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1158 (outs VR128:$dst), (ins VR128:$src1,
1159 VR128:$src2, i8imm:$src3),
1160 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1162 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1163 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1164 (outs VR128:$dst), (ins VR128:$src1,
1165 f128mem:$src2, i8imm:$src3),
1166 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1169 VR128:$src1, (memopv4f32 addr:$src2))))]>;
1171 let AddedComplexity = 10 in {
1172 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1173 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1174 "unpckhps\t{$src2, $dst|$dst, $src2}",
1176 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
1177 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1178 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1179 "unpckhps\t{$src2, $dst|$dst, $src2}",
1181 (v4f32 (unpckh VR128:$src1,
1182 (memopv4f32 addr:$src2))))]>;
1184 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1185 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1186 "unpcklps\t{$src2, $dst|$dst, $src2}",
1188 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
1189 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1190 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1191 "unpcklps\t{$src2, $dst|$dst, $src2}",
1193 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
1194 } // AddedComplexity
1195 } // Constraints = "$src1 = $dst"
1198 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1199 "movmskps\t{$src, $dst|$dst, $src}",
1200 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1201 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1202 "movmskpd\t{$src, $dst|$dst, $src}",
1203 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1205 // Prefetch intrinsic.
1206 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1207 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1208 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1209 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1210 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1211 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1212 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1213 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1215 // Non-temporal stores
1216 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1217 "movntps\t{$src, $dst|$dst, $src}",
1218 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1220 let AddedComplexity = 400 in { // Prefer non-temporal versions
1221 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1222 "movntps\t{$src, $dst|$dst, $src}",
1223 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1225 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1226 "movntdq\t{$src, $dst|$dst, $src}",
1227 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1229 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1230 "movnti\t{$src, $dst|$dst, $src}",
1231 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1232 TB, Requires<[HasSSE2]>;
1234 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1235 "movnti\t{$src, $dst|$dst, $src}",
1236 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1237 TB, Requires<[HasSSE2]>;
1240 // Load, store, and memory fence
1241 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
1242 TB, Requires<[HasSSE1]>;
1245 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1246 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1247 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1248 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1250 // Alias instructions that map zero vector to pxor / xorp* for sse.
1251 // We set canFoldAsLoad because this can be converted to a constant-pool
1252 // load of an all-zeros value if folding it would be beneficial.
1253 // FIXME: Change encoding to pseudo!
1254 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1255 isCodeGenOnly = 1 in {
1256 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1257 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1258 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1259 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
1260 let ExeDomain = SSEPackedInt in
1261 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
1262 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1265 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
1266 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
1267 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
1269 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1270 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1272 //===---------------------------------------------------------------------===//
1273 // SSE2 Instructions
1274 //===---------------------------------------------------------------------===//
1276 // Move Instructions. Register-to-register movsd is not used for FR64
1277 // register copies because it's a partial register update; FsMOVAPDrr is
1278 // used instead. Register-to-register movsd is not modeled as an INSERT_SUBREG
1279 // because INSERT_SUBREG requires that the insert be implementable in terms of
1280 // a copy, and just mentioned, we don't use movsd for copies.
1281 let Constraints = "$src1 = $dst" in
1282 def MOVSDrr : SDI<0x10, MRMSrcReg,
1283 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
1284 "movsd\t{$src2, $dst|$dst, $src2}",
1285 [(set (v2f64 VR128:$dst),
1286 (movl VR128:$src1, (scalar_to_vector FR64:$src2)))]>;
1288 // Extract the low 64-bit value from one vector and insert it into another.
1289 let AddedComplexity = 15 in
1290 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
1291 (MOVSDrr (v2f64 VR128:$src1),
1292 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
1294 // Implicitly promote a 64-bit scalar to a vector.
1295 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
1296 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
1298 // Loading from memory automatically zeroing upper bits.
1299 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 20 in
1300 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1301 "movsd\t{$src, $dst|$dst, $src}",
1302 [(set FR64:$dst, (loadf64 addr:$src))]>;
1304 // MOVSDrm zeros the high parts of the register; represent this
1305 // with SUBREG_TO_REG.
1306 let AddedComplexity = 20 in {
1307 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1308 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1309 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1310 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1311 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1312 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1313 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1314 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1315 def : Pat<(v2f64 (X86vzload addr:$src)),
1316 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1319 // Store scalar value to memory.
1320 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1321 "movsd\t{$src, $dst|$dst, $src}",
1322 [(store FR64:$src, addr:$dst)]>;
1324 // Extract and store.
1325 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
1328 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
1330 // Conversion instructions
1331 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1332 "cvttsd2si\t{$src, $dst|$dst, $src}",
1333 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1334 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1335 "cvttsd2si\t{$src, $dst|$dst, $src}",
1336 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1337 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1338 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1339 [(set FR32:$dst, (fround FR64:$src))]>;
1340 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1341 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1342 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1343 Requires<[HasSSE2, OptForSize]>;
1344 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1345 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1346 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1347 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1348 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1349 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1351 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1352 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1353 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1354 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1355 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1356 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1357 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1358 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1359 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1360 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1361 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1362 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1363 def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1364 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1365 def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1366 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1367 def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1368 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1369 def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1370 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1372 // SSE2 instructions with XS prefix
1373 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1374 "cvtss2sd\t{$src, $dst|$dst, $src}",
1375 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1376 Requires<[HasSSE2]>;
1377 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1378 "cvtss2sd\t{$src, $dst|$dst, $src}",
1379 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1380 Requires<[HasSSE2, OptForSize]>;
1382 def : Pat<(extloadf32 addr:$src),
1383 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1384 Requires<[HasSSE2, OptForSpeed]>;
1386 // Match intrinsics which expect XMM operand(s).
1387 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1388 "cvtsd2si\t{$src, $dst|$dst, $src}",
1389 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1390 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1391 "cvtsd2si\t{$src, $dst|$dst, $src}",
1392 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1393 (load addr:$src)))]>;
1395 // Match intrinsics which expect MM and XMM operand(s).
1396 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1397 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1398 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1399 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1400 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1401 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1402 (memop addr:$src)))]>;
1403 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1404 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1405 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1406 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1407 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1408 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1409 (memop addr:$src)))]>;
1410 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1411 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1412 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1413 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1414 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1415 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1416 (load addr:$src)))]>;
1418 // Aliases for intrinsics
1419 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1420 "cvttsd2si\t{$src, $dst|$dst, $src}",
1422 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1423 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1424 "cvttsd2si\t{$src, $dst|$dst, $src}",
1425 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1426 (load addr:$src)))]>;
1428 // Comparison instructions
1429 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1430 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1431 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1432 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1434 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1435 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1436 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1438 // Accept explicit immediate argument form instead of comparison code.
1439 let isAsmParserOnly = 1 in {
1440 def CMPSDrr_alt : SDIi8<0xC2, MRMSrcReg,
1441 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1442 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1444 def CMPSDrm_alt : SDIi8<0xC2, MRMSrcMem,
1445 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1446 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1450 let Defs = [EFLAGS] in {
1451 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1452 "ucomisd\t{$src2, $src1|$src1, $src2}",
1453 [(set EFLAGS, (X86cmp FR64:$src1, FR64:$src2))]>;
1454 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1455 "ucomisd\t{$src2, $src1|$src1, $src2}",
1456 [(set EFLAGS, (X86cmp FR64:$src1, (loadf64 addr:$src2)))]>;
1457 } // Defs = [EFLAGS]
1459 // Aliases to match intrinsics which expect XMM operand(s).
1460 let Constraints = "$src1 = $dst" in {
1461 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1463 (ins VR128:$src1, VR128:$src, SSECC:$cc),
1464 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1465 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1466 VR128:$src, imm:$cc))]>;
1467 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1469 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1470 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1471 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1472 (load addr:$src), imm:$cc))]>;
1475 let Defs = [EFLAGS] in {
1476 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1477 "ucomisd\t{$src2, $src1|$src1, $src2}",
1478 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1480 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1481 "ucomisd\t{$src2, $src1|$src1, $src2}",
1482 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1483 (load addr:$src2)))]>;
1485 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1486 "comisd\t{$src2, $src1|$src1, $src2}",
1487 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1489 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1490 "comisd\t{$src2, $src1|$src1, $src2}",
1491 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1492 (load addr:$src2)))]>;
1493 } // Defs = [EFLAGS]
1495 // Aliases of packed SSE2 instructions for scalar use. These all have names
1496 // that start with 'Fs'.
1498 // Alias instructions that map fld0 to pxor for sse.
1499 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1500 canFoldAsLoad = 1 in
1501 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1502 [(set FR64:$dst, fpimm0)]>,
1503 Requires<[HasSSE2]>, TB, OpSize;
1505 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1507 let neverHasSideEffects = 1 in
1508 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1509 "movapd\t{$src, $dst|$dst, $src}", []>;
1511 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1513 let canFoldAsLoad = 1, isReMaterializable = 1 in
1514 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1515 "movapd\t{$src, $dst|$dst, $src}",
1516 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1518 //===---------------------------------------------------------------------===//
1519 // SSE packed FP Instructions
1521 // Move Instructions
1522 let neverHasSideEffects = 1 in
1523 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1524 "movapd\t{$src, $dst|$dst, $src}", []>;
1525 let canFoldAsLoad = 1, isReMaterializable = 1 in
1526 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1527 "movapd\t{$src, $dst|$dst, $src}",
1528 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1530 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1531 "movapd\t{$src, $dst|$dst, $src}",
1532 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1534 let neverHasSideEffects = 1 in
1535 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1536 "movupd\t{$src, $dst|$dst, $src}", []>;
1537 let canFoldAsLoad = 1 in
1538 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1539 "movupd\t{$src, $dst|$dst, $src}",
1540 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1541 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1542 "movupd\t{$src, $dst|$dst, $src}",
1543 [(store (v2f64 VR128:$src), addr:$dst)]>;
1545 // Intrinsic forms of MOVUPD load and store
1546 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1547 "movupd\t{$src, $dst|$dst, $src}",
1548 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1549 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1550 "movupd\t{$src, $dst|$dst, $src}",
1551 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1553 let Constraints = "$src1 = $dst" in {
1554 let AddedComplexity = 20 in {
1555 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1556 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1557 "movlpd\t{$src2, $dst|$dst, $src2}",
1559 (v2f64 (movlp VR128:$src1,
1560 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1561 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1562 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1563 "movhpd\t{$src2, $dst|$dst, $src2}",
1565 (v2f64 (movlhps VR128:$src1,
1566 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1567 } // AddedComplexity
1568 } // Constraints = "$src1 = $dst"
1570 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1571 "movlpd\t{$src, $dst|$dst, $src}",
1572 [(store (f64 (vector_extract (v2f64 VR128:$src),
1573 (iPTR 0))), addr:$dst)]>;
1575 // v2f64 extract element 1 is always custom lowered to unpack high to low
1576 // and extract element 0 so the non-store version isn't too horrible.
1577 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1578 "movhpd\t{$src, $dst|$dst, $src}",
1579 [(store (f64 (vector_extract
1580 (v2f64 (unpckh VR128:$src, (undef))),
1581 (iPTR 0))), addr:$dst)]>;
1583 // SSE2 instructions without OpSize prefix
1584 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1585 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1586 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1587 TB, Requires<[HasSSE2]>;
1588 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1589 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1590 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1591 (bitconvert (memopv2i64 addr:$src))))]>,
1592 TB, Requires<[HasSSE2]>;
1594 // SSE2 instructions with XS prefix
1595 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1596 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1597 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1598 XS, Requires<[HasSSE2]>;
1599 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1600 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1601 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1602 (bitconvert (memopv2i64 addr:$src))))]>,
1603 XS, Requires<[HasSSE2]>;
1605 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1606 "cvtps2dq\t{$src, $dst|$dst, $src}",
1607 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1608 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1609 "cvtps2dq\t{$src, $dst|$dst, $src}",
1610 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1611 (memop addr:$src)))]>;
1612 // SSE2 packed instructions with XS prefix
1613 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1614 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1615 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1616 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1618 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1619 "cvttps2dq\t{$src, $dst|$dst, $src}",
1621 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1622 XS, Requires<[HasSSE2]>;
1623 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1624 "cvttps2dq\t{$src, $dst|$dst, $src}",
1625 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1626 (memop addr:$src)))]>,
1627 XS, Requires<[HasSSE2]>;
1629 // SSE2 packed instructions with XD prefix
1630 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1631 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1632 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1633 XD, Requires<[HasSSE2]>;
1634 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1635 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1636 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1637 (memop addr:$src)))]>,
1638 XD, Requires<[HasSSE2]>;
1640 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1641 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1642 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1643 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1644 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1645 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1646 (memop addr:$src)))]>;
1648 // SSE2 instructions without OpSize prefix
1649 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1650 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1651 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1652 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1654 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1655 "cvtps2pd\t{$src, $dst|$dst, $src}",
1656 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1657 TB, Requires<[HasSSE2]>;
1658 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1659 "cvtps2pd\t{$src, $dst|$dst, $src}",
1660 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1661 (load addr:$src)))]>,
1662 TB, Requires<[HasSSE2]>;
1664 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1665 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1666 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1667 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1670 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1671 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1672 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1673 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1674 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1675 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1676 (memop addr:$src)))]>;
1678 // Match intrinsics which expect XMM operand(s).
1679 // Aliases for intrinsics
1680 let Constraints = "$src1 = $dst" in {
1681 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1682 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1683 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1684 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1686 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1687 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1688 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1689 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1690 (loadi32 addr:$src2)))]>;
1691 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1692 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1693 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1694 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1696 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1697 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1698 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1699 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1700 (load addr:$src2)))]>;
1701 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1702 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1703 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1704 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1705 VR128:$src2))]>, XS,
1706 Requires<[HasSSE2]>;
1707 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1708 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1709 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1710 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1711 (load addr:$src2)))]>, XS,
1712 Requires<[HasSSE2]>;
1717 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1719 /// In addition, we also have a special variant of the scalar form here to
1720 /// represent the associated intrinsic operation. This form is unlike the
1721 /// plain scalar form, in that it takes an entire vector (instead of a
1722 /// scalar) and leaves the top elements undefined.
1724 /// And, we have a special variant form for a full-vector intrinsic form.
1726 /// These four forms can each have a reg or a mem operand, so there are a
1727 /// total of eight "instructions".
1729 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1733 bit Commutable = 0> {
1734 // Scalar operation, reg.
1735 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1736 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1737 [(set FR64:$dst, (OpNode FR64:$src))]> {
1738 let isCommutable = Commutable;
1741 // Scalar operation, mem.
1742 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1743 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1744 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1746 // Vector operation, reg.
1747 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1748 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1749 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1750 let isCommutable = Commutable;
1753 // Vector operation, mem.
1754 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1755 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1756 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1758 // Intrinsic operation, reg.
1759 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1760 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1761 [(set VR128:$dst, (F64Int VR128:$src))]> {
1762 let isCommutable = Commutable;
1765 // Intrinsic operation, mem.
1766 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1767 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1768 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1770 // Vector intrinsic operation, reg
1771 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1772 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1773 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1774 let isCommutable = Commutable;
1777 // Vector intrinsic operation, mem
1778 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1779 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1780 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1784 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1785 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1787 // There is no f64 version of the reciprocal approximation instructions.
1789 let Constraints = "$src1 = $dst" in {
1790 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1791 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1792 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1793 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1794 VR128:$src, imm:$cc))]>;
1795 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1796 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1797 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1798 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1799 (memop addr:$src), imm:$cc))]>;
1801 // Accept explicit immediate argument form instead of comparison code.
1802 let isAsmParserOnly = 1 in {
1803 def CMPPDrri_alt : PDIi8<0xC2, MRMSrcReg,
1804 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, i8imm:$src2),
1805 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1806 def CMPPDrmi_alt : PDIi8<0xC2, MRMSrcMem,
1807 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, i8imm:$src2),
1808 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1811 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1812 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1813 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1814 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1816 // Shuffle and unpack instructions
1817 let Constraints = "$src1 = $dst" in {
1818 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1819 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1820 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1822 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1823 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1824 (outs VR128:$dst), (ins VR128:$src1,
1825 f128mem:$src2, i8imm:$src3),
1826 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1829 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1831 let AddedComplexity = 10 in {
1832 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1833 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1834 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1836 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1837 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1838 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1839 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1841 (v2f64 (unpckh VR128:$src1,
1842 (memopv2f64 addr:$src2))))]>;
1844 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1845 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1846 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1848 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1849 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1850 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1851 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1853 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1854 } // AddedComplexity
1855 } // Constraints = "$src1 = $dst"
1858 //===---------------------------------------------------------------------===//
1859 // SSE integer instructions
1860 let ExeDomain = SSEPackedInt in {
1862 // Move Instructions
1863 let neverHasSideEffects = 1 in
1864 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1865 "movdqa\t{$src, $dst|$dst, $src}", []>;
1866 let canFoldAsLoad = 1, mayLoad = 1 in
1867 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1868 "movdqa\t{$src, $dst|$dst, $src}",
1869 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1871 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1872 "movdqa\t{$src, $dst|$dst, $src}",
1873 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1874 let canFoldAsLoad = 1, mayLoad = 1 in
1875 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1876 "movdqu\t{$src, $dst|$dst, $src}",
1877 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1878 XS, Requires<[HasSSE2]>;
1880 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1881 "movdqu\t{$src, $dst|$dst, $src}",
1882 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1883 XS, Requires<[HasSSE2]>;
1885 // Intrinsic forms of MOVDQU load and store
1886 let canFoldAsLoad = 1 in
1887 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1888 "movdqu\t{$src, $dst|$dst, $src}",
1889 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1890 XS, Requires<[HasSSE2]>;
1891 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1892 "movdqu\t{$src, $dst|$dst, $src}",
1893 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1894 XS, Requires<[HasSSE2]>;
1896 let Constraints = "$src1 = $dst" in {
1898 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1899 bit Commutable = 0> {
1900 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1901 (ins VR128:$src1, VR128:$src2),
1902 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1903 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1904 let isCommutable = Commutable;
1906 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1907 (ins VR128:$src1, i128mem:$src2),
1908 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1909 [(set VR128:$dst, (IntId VR128:$src1,
1910 (bitconvert (memopv2i64
1914 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1916 Intrinsic IntId, Intrinsic IntId2> {
1917 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1918 (ins VR128:$src1, VR128:$src2),
1919 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1920 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1921 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1922 (ins VR128:$src1, i128mem:$src2),
1923 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1924 [(set VR128:$dst, (IntId VR128:$src1,
1925 (bitconvert (memopv2i64 addr:$src2))))]>;
1926 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
1927 (ins VR128:$src1, i32i8imm:$src2),
1928 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1929 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1932 /// PDI_binop_rm - Simple SSE2 binary operator.
1933 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1934 ValueType OpVT, bit Commutable = 0> {
1935 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1936 (ins VR128:$src1, VR128:$src2),
1937 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1938 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1939 let isCommutable = Commutable;
1941 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1942 (ins VR128:$src1, i128mem:$src2),
1943 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1944 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1945 (bitconvert (memopv2i64 addr:$src2)))))]>;
1948 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1950 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1951 /// to collapse (bitconvert VT to VT) into its operand.
1953 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1954 bit Commutable = 0> {
1955 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1956 (ins VR128:$src1, VR128:$src2),
1957 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1958 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1959 let isCommutable = Commutable;
1961 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1962 (ins VR128:$src1, i128mem:$src2),
1963 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1964 [(set VR128:$dst, (OpNode VR128:$src1,
1965 (memopv2i64 addr:$src2)))]>;
1968 } // Constraints = "$src1 = $dst"
1969 } // ExeDomain = SSEPackedInt
1971 // 128-bit Integer Arithmetic
1973 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1974 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1975 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1976 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1978 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1979 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1980 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1981 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1983 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1984 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1985 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1986 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1988 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1989 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1990 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1991 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1993 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1995 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1996 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1997 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1999 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2001 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2002 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2005 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2006 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2007 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2008 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2009 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2012 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2013 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2014 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2015 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2016 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2017 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2019 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2020 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2021 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2022 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2023 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2024 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2026 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2027 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2028 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2029 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2031 // 128-bit logical shifts.
2032 let Constraints = "$src1 = $dst", neverHasSideEffects = 1,
2033 ExeDomain = SSEPackedInt in {
2034 def PSLLDQri : PDIi8<0x73, MRM7r,
2035 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2036 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2037 def PSRLDQri : PDIi8<0x73, MRM3r,
2038 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2039 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2040 // PSRADQri doesn't exist in SSE[1-3].
2043 let Predicates = [HasSSE2] in {
2044 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2045 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2046 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2047 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2048 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2049 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2050 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2051 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2052 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2053 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2055 // Shift up / down and insert zero's.
2056 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2057 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2058 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2059 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2063 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2064 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
2065 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2067 let Constraints = "$src1 = $dst", ExeDomain = SSEPackedInt in {
2068 def PANDNrr : PDI<0xDF, MRMSrcReg,
2069 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2070 "pandn\t{$src2, $dst|$dst, $src2}",
2071 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2074 def PANDNrm : PDI<0xDF, MRMSrcMem,
2075 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2076 "pandn\t{$src2, $dst|$dst, $src2}",
2077 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2078 (memopv2i64 addr:$src2))))]>;
2081 // SSE2 Integer comparison
2082 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2083 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2084 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2085 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2086 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2087 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2089 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2090 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2091 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2092 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2093 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2094 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2095 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2096 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2097 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2098 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2099 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2100 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2102 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2103 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2104 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2105 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2106 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2107 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2108 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2109 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2110 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2111 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2112 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2113 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2116 // Pack instructions
2117 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2118 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2119 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2121 let ExeDomain = SSEPackedInt in {
2123 // Shuffle and unpack instructions
2124 let AddedComplexity = 5 in {
2125 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2126 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2127 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2128 [(set VR128:$dst, (v4i32 (pshufd:$src2
2129 VR128:$src1, (undef))))]>;
2130 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2131 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2132 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2133 [(set VR128:$dst, (v4i32 (pshufd:$src2
2134 (bc_v4i32 (memopv2i64 addr:$src1)),
2138 // SSE2 with ImmT == Imm8 and XS prefix.
2139 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2140 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2141 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2142 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2144 XS, Requires<[HasSSE2]>;
2145 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2146 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2147 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2148 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2149 (bc_v8i16 (memopv2i64 addr:$src1)),
2151 XS, Requires<[HasSSE2]>;
2153 // SSE2 with ImmT == Imm8 and XD prefix.
2154 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2155 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2156 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2157 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2159 XD, Requires<[HasSSE2]>;
2160 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2161 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2162 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2163 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2164 (bc_v8i16 (memopv2i64 addr:$src1)),
2166 XD, Requires<[HasSSE2]>;
2168 // Unpack instructions
2169 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2170 PatFrag unp_frag, PatFrag bc_frag> {
2171 def rr : PDI<opc, MRMSrcReg,
2172 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2173 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2174 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2175 def rm : PDI<opc, MRMSrcMem,
2176 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2177 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2178 [(set VR128:$dst, (unp_frag VR128:$src1,
2179 (bc_frag (memopv2i64
2183 let Constraints = "$src1 = $dst" in {
2184 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2185 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2186 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2188 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2189 /// knew to collapse (bitconvert VT to VT) into its operand.
2190 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2191 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2192 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2194 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2195 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2196 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2197 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2199 (v2i64 (unpckl VR128:$src1,
2200 (memopv2i64 addr:$src2))))]>;
2202 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2203 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2204 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2206 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2207 /// knew to collapse (bitconvert VT to VT) into its operand.
2208 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2209 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2210 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2212 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2213 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2214 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2215 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2217 (v2i64 (unpckh VR128:$src1,
2218 (memopv2i64 addr:$src2))))]>;
2222 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2223 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2224 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2225 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2227 let Constraints = "$src1 = $dst" in {
2228 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2229 (outs VR128:$dst), (ins VR128:$src1,
2230 GR32:$src2, i32i8imm:$src3),
2231 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2233 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2234 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2235 (outs VR128:$dst), (ins VR128:$src1,
2236 i16mem:$src2, i32i8imm:$src3),
2237 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2239 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2244 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2245 "pmovmskb\t{$src, $dst|$dst, $src}",
2246 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2248 // Conditional store
2250 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2251 "maskmovdqu\t{$mask, $src|$src, $mask}",
2252 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2255 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2256 "maskmovdqu\t{$mask, $src|$src, $mask}",
2257 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2259 } // ExeDomain = SSEPackedInt
2261 // Non-temporal stores
2262 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2263 "movntpd\t{$src, $dst|$dst, $src}",
2264 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2265 let ExeDomain = SSEPackedInt in
2266 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2267 "movntdq\t{$src, $dst|$dst, $src}",
2268 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2269 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2270 "movnti\t{$src, $dst|$dst, $src}",
2271 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2272 TB, Requires<[HasSSE2]>;
2274 let AddedComplexity = 400 in { // Prefer non-temporal versions
2275 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2276 "movntpd\t{$src, $dst|$dst, $src}",
2277 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2279 let ExeDomain = SSEPackedInt in
2280 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2281 "movntdq\t{$src, $dst|$dst, $src}",
2282 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2286 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2287 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2288 TB, Requires<[HasSSE2]>;
2290 // Load, store, and memory fence
2291 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2292 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2293 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2294 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2296 // Pause. This "instruction" is encoded as "rep; nop", so even though it
2297 // was introduced with SSE2, it's backward compatible.
2298 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
2300 //TODO: custom lower this so as to never even generate the noop
2301 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2303 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2304 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2305 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2308 // Alias instructions that map zero vector to pxor / xorp* for sse.
2309 // We set canFoldAsLoad because this can be converted to a constant-pool
2310 // load of an all-ones value if folding it would be beneficial.
2311 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2312 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
2313 // FIXME: Change encoding to pseudo.
2314 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2315 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2317 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2318 "movd\t{$src, $dst|$dst, $src}",
2320 (v4i32 (scalar_to_vector GR32:$src)))]>;
2321 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2322 "movd\t{$src, $dst|$dst, $src}",
2324 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2326 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2327 "movd\t{$src, $dst|$dst, $src}",
2328 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2330 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2331 "movd\t{$src, $dst|$dst, $src}",
2332 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2334 // SSE2 instructions with XS prefix
2335 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2336 "movq\t{$src, $dst|$dst, $src}",
2338 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2339 Requires<[HasSSE2]>;
2340 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2341 "movq\t{$src, $dst|$dst, $src}",
2342 [(store (i64 (vector_extract (v2i64 VR128:$src),
2343 (iPTR 0))), addr:$dst)]>;
2345 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2346 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
2348 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2349 "movd\t{$src, $dst|$dst, $src}",
2350 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2352 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2353 "movd\t{$src, $dst|$dst, $src}",
2354 [(store (i32 (vector_extract (v4i32 VR128:$src),
2355 (iPTR 0))), addr:$dst)]>;
2357 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2358 "movd\t{$src, $dst|$dst, $src}",
2359 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2360 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2361 "movd\t{$src, $dst|$dst, $src}",
2362 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2364 // Store / copy lower 64-bits of a XMM register.
2365 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2366 "movq\t{$src, $dst|$dst, $src}",
2367 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2369 // movd / movq to XMM register zero-extends
2370 let AddedComplexity = 15 in {
2371 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2372 "movd\t{$src, $dst|$dst, $src}",
2373 [(set VR128:$dst, (v4i32 (X86vzmovl
2374 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2375 // This is X86-64 only.
2376 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2377 "mov{d|q}\t{$src, $dst|$dst, $src}",
2378 [(set VR128:$dst, (v2i64 (X86vzmovl
2379 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2382 let AddedComplexity = 20 in {
2383 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2384 "movd\t{$src, $dst|$dst, $src}",
2386 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2387 (loadi32 addr:$src))))))]>;
2389 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2390 (MOVZDI2PDIrm addr:$src)>;
2391 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2392 (MOVZDI2PDIrm addr:$src)>;
2393 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2394 (MOVZDI2PDIrm addr:$src)>;
2396 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2397 "movq\t{$src, $dst|$dst, $src}",
2399 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2400 (loadi64 addr:$src))))))]>, XS,
2401 Requires<[HasSSE2]>;
2403 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2404 (MOVZQI2PQIrm addr:$src)>;
2405 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2406 (MOVZQI2PQIrm addr:$src)>;
2407 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2410 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2411 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2412 let AddedComplexity = 15 in
2413 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2414 "movq\t{$src, $dst|$dst, $src}",
2415 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2416 XS, Requires<[HasSSE2]>;
2418 let AddedComplexity = 20 in {
2419 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2420 "movq\t{$src, $dst|$dst, $src}",
2421 [(set VR128:$dst, (v2i64 (X86vzmovl
2422 (loadv2i64 addr:$src))))]>,
2423 XS, Requires<[HasSSE2]>;
2425 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2426 (MOVZPQILo2PQIrm addr:$src)>;
2429 // Instructions for the disassembler
2430 // xr = XMM register
2433 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2434 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2436 //===---------------------------------------------------------------------===//
2437 // SSE3 Instructions
2438 //===---------------------------------------------------------------------===//
2440 // Move Instructions
2441 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2442 "movshdup\t{$src, $dst|$dst, $src}",
2443 [(set VR128:$dst, (v4f32 (movshdup
2444 VR128:$src, (undef))))]>;
2445 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2446 "movshdup\t{$src, $dst|$dst, $src}",
2447 [(set VR128:$dst, (movshdup
2448 (memopv4f32 addr:$src), (undef)))]>;
2450 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2451 "movsldup\t{$src, $dst|$dst, $src}",
2452 [(set VR128:$dst, (v4f32 (movsldup
2453 VR128:$src, (undef))))]>;
2454 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2455 "movsldup\t{$src, $dst|$dst, $src}",
2456 [(set VR128:$dst, (movsldup
2457 (memopv4f32 addr:$src), (undef)))]>;
2459 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2460 "movddup\t{$src, $dst|$dst, $src}",
2461 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2462 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2463 "movddup\t{$src, $dst|$dst, $src}",
2465 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2468 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2470 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2472 let AddedComplexity = 5 in {
2473 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2474 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2475 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2476 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2477 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2478 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2479 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2480 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2484 let Constraints = "$src1 = $dst" in {
2485 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2486 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2487 "addsubps\t{$src2, $dst|$dst, $src2}",
2488 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2490 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2491 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2492 "addsubps\t{$src2, $dst|$dst, $src2}",
2493 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2494 (memop addr:$src2)))]>;
2495 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2496 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2497 "addsubpd\t{$src2, $dst|$dst, $src2}",
2498 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2500 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2501 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2502 "addsubpd\t{$src2, $dst|$dst, $src2}",
2503 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2504 (memop addr:$src2)))]>;
2507 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2508 "lddqu\t{$src, $dst|$dst, $src}",
2509 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2512 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2513 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2514 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2515 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2516 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2517 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2518 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2519 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2520 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2521 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2522 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2523 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2524 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2525 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2526 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2527 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2529 let Constraints = "$src1 = $dst" in {
2530 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2531 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2532 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2533 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2534 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2535 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2536 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2537 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2540 // Thread synchronization
2541 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
2542 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2543 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
2544 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2546 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2547 let AddedComplexity = 15 in
2548 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2549 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2550 let AddedComplexity = 20 in
2551 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2552 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2554 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2555 let AddedComplexity = 15 in
2556 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2557 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2558 let AddedComplexity = 20 in
2559 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2560 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2562 //===---------------------------------------------------------------------===//
2563 // SSSE3 Instructions
2564 //===---------------------------------------------------------------------===//
2566 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2567 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2568 Intrinsic IntId64, Intrinsic IntId128> {
2569 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2570 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2571 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2573 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2576 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2578 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2580 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2581 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2584 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2586 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2589 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2592 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2593 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2594 Intrinsic IntId64, Intrinsic IntId128> {
2595 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2597 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2598 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2600 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2602 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2605 (bitconvert (memopv4i16 addr:$src))))]>;
2607 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2609 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2610 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2613 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2615 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2618 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2621 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2622 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2623 Intrinsic IntId64, Intrinsic IntId128> {
2624 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2626 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2627 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2629 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2631 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2634 (bitconvert (memopv2i32 addr:$src))))]>;
2636 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2638 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2639 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2642 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2644 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2647 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2650 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2651 int_x86_ssse3_pabs_b,
2652 int_x86_ssse3_pabs_b_128>;
2653 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2654 int_x86_ssse3_pabs_w,
2655 int_x86_ssse3_pabs_w_128>;
2656 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2657 int_x86_ssse3_pabs_d,
2658 int_x86_ssse3_pabs_d_128>;
2660 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2661 let Constraints = "$src1 = $dst" in {
2662 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2663 Intrinsic IntId64, Intrinsic IntId128,
2664 bit Commutable = 0> {
2665 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2666 (ins VR64:$src1, VR64:$src2),
2667 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2668 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2669 let isCommutable = Commutable;
2671 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2672 (ins VR64:$src1, i64mem:$src2),
2673 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2675 (IntId64 VR64:$src1,
2676 (bitconvert (memopv8i8 addr:$src2))))]>;
2678 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2679 (ins VR128:$src1, VR128:$src2),
2680 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2681 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2683 let isCommutable = Commutable;
2685 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2686 (ins VR128:$src1, i128mem:$src2),
2687 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2689 (IntId128 VR128:$src1,
2690 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2694 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2695 let Constraints = "$src1 = $dst" in {
2696 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2697 Intrinsic IntId64, Intrinsic IntId128,
2698 bit Commutable = 0> {
2699 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2700 (ins VR64:$src1, VR64:$src2),
2701 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2702 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2703 let isCommutable = Commutable;
2705 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2706 (ins VR64:$src1, i64mem:$src2),
2707 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2709 (IntId64 VR64:$src1,
2710 (bitconvert (memopv4i16 addr:$src2))))]>;
2712 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2713 (ins VR128:$src1, VR128:$src2),
2714 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2715 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2717 let isCommutable = Commutable;
2719 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2720 (ins VR128:$src1, i128mem:$src2),
2721 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2723 (IntId128 VR128:$src1,
2724 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2728 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2729 let Constraints = "$src1 = $dst" in {
2730 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2731 Intrinsic IntId64, Intrinsic IntId128,
2732 bit Commutable = 0> {
2733 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2734 (ins VR64:$src1, VR64:$src2),
2735 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2736 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2737 let isCommutable = Commutable;
2739 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2740 (ins VR64:$src1, i64mem:$src2),
2741 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2743 (IntId64 VR64:$src1,
2744 (bitconvert (memopv2i32 addr:$src2))))]>;
2746 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2747 (ins VR128:$src1, VR128:$src2),
2748 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2749 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2751 let isCommutable = Commutable;
2753 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2754 (ins VR128:$src1, i128mem:$src2),
2755 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2757 (IntId128 VR128:$src1,
2758 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2762 let ImmT = NoImm in { // None of these have i8 immediate fields.
2763 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2764 int_x86_ssse3_phadd_w,
2765 int_x86_ssse3_phadd_w_128>;
2766 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2767 int_x86_ssse3_phadd_d,
2768 int_x86_ssse3_phadd_d_128>;
2769 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2770 int_x86_ssse3_phadd_sw,
2771 int_x86_ssse3_phadd_sw_128>;
2772 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2773 int_x86_ssse3_phsub_w,
2774 int_x86_ssse3_phsub_w_128>;
2775 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2776 int_x86_ssse3_phsub_d,
2777 int_x86_ssse3_phsub_d_128>;
2778 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2779 int_x86_ssse3_phsub_sw,
2780 int_x86_ssse3_phsub_sw_128>;
2781 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2782 int_x86_ssse3_pmadd_ub_sw,
2783 int_x86_ssse3_pmadd_ub_sw_128>;
2784 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2785 int_x86_ssse3_pmul_hr_sw,
2786 int_x86_ssse3_pmul_hr_sw_128, 1>;
2788 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2789 int_x86_ssse3_pshuf_b,
2790 int_x86_ssse3_pshuf_b_128>;
2791 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2792 int_x86_ssse3_psign_b,
2793 int_x86_ssse3_psign_b_128>;
2794 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2795 int_x86_ssse3_psign_w,
2796 int_x86_ssse3_psign_w_128>;
2797 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2798 int_x86_ssse3_psign_d,
2799 int_x86_ssse3_psign_d_128>;
2802 // palignr patterns.
2803 let Constraints = "$src1 = $dst" in {
2804 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2805 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
2806 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2808 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2809 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
2810 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2813 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2814 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
2815 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2817 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2818 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
2819 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2823 let AddedComplexity = 5 in {
2825 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
2826 (PALIGNR64rr VR64:$src2, VR64:$src1,
2827 (SHUFFLE_get_palign_imm VR64:$src3))>,
2828 Requires<[HasSSSE3]>;
2829 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
2830 (PALIGNR64rr VR64:$src2, VR64:$src1,
2831 (SHUFFLE_get_palign_imm VR64:$src3))>,
2832 Requires<[HasSSSE3]>;
2833 def : Pat<(v2f32 (palign:$src3 VR64:$src1, VR64:$src2)),
2834 (PALIGNR64rr VR64:$src2, VR64:$src1,
2835 (SHUFFLE_get_palign_imm VR64:$src3))>,
2836 Requires<[HasSSSE3]>;
2837 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
2838 (PALIGNR64rr VR64:$src2, VR64:$src1,
2839 (SHUFFLE_get_palign_imm VR64:$src3))>,
2840 Requires<[HasSSSE3]>;
2841 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
2842 (PALIGNR64rr VR64:$src2, VR64:$src1,
2843 (SHUFFLE_get_palign_imm VR64:$src3))>,
2844 Requires<[HasSSSE3]>;
2846 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
2847 (PALIGNR128rr VR128:$src2, VR128:$src1,
2848 (SHUFFLE_get_palign_imm VR128:$src3))>,
2849 Requires<[HasSSSE3]>;
2850 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
2851 (PALIGNR128rr VR128:$src2, VR128:$src1,
2852 (SHUFFLE_get_palign_imm VR128:$src3))>,
2853 Requires<[HasSSSE3]>;
2854 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
2855 (PALIGNR128rr VR128:$src2, VR128:$src1,
2856 (SHUFFLE_get_palign_imm VR128:$src3))>,
2857 Requires<[HasSSSE3]>;
2858 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
2859 (PALIGNR128rr VR128:$src2, VR128:$src1,
2860 (SHUFFLE_get_palign_imm VR128:$src3))>,
2861 Requires<[HasSSSE3]>;
2864 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2865 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2866 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2867 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2869 //===---------------------------------------------------------------------===//
2870 // Non-Instruction Patterns
2871 //===---------------------------------------------------------------------===//
2873 // extload f32 -> f64. This matches load+fextend because we have a hack in
2874 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2876 // Since these loads aren't folded into the fextend, we have to match it
2878 let Predicates = [HasSSE2] in
2879 def : Pat<(fextend (loadf32 addr:$src)),
2880 (CVTSS2SDrm addr:$src)>;
2883 let Predicates = [HasSSE2] in {
2884 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2885 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2886 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2887 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2888 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2889 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2890 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2891 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2892 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2893 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2894 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2895 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2896 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2897 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2898 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2899 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2900 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2901 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2902 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2903 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2904 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2905 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2906 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2907 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2908 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2909 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2910 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2911 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2912 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2913 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2916 // Move scalar to XMM zero-extended
2917 // movd to XMM register zero-extends
2918 let AddedComplexity = 15 in {
2919 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2920 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2921 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
2922 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2923 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
2924 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2925 (MOVSSrr (v4f32 (V_SET0PS)),
2926 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
2927 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2928 (MOVSSrr (v4i32 (V_SET0PI)),
2929 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
2932 // Splat v2f64 / v2i64
2933 let AddedComplexity = 10 in {
2934 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2935 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2936 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
2937 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2938 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
2939 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2940 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
2941 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2944 // Special unary SHUFPSrri case.
2945 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2946 (SHUFPSrri VR128:$src1, VR128:$src1,
2947 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2948 let AddedComplexity = 5 in
2949 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
2950 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2951 Requires<[HasSSE2]>;
2952 // Special unary SHUFPDrri case.
2953 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2954 (SHUFPDrri VR128:$src1, VR128:$src1,
2955 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2956 Requires<[HasSSE2]>;
2957 // Special unary SHUFPDrri case.
2958 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2959 (SHUFPDrri VR128:$src1, VR128:$src1,
2960 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2961 Requires<[HasSSE2]>;
2962 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2963 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
2964 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2965 Requires<[HasSSE2]>;
2967 // Special binary v4i32 shuffle cases with SHUFPS.
2968 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2969 (SHUFPSrri VR128:$src1, VR128:$src2,
2970 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2971 Requires<[HasSSE2]>;
2972 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
2973 (SHUFPSrmi VR128:$src1, addr:$src2,
2974 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2975 Requires<[HasSSE2]>;
2976 // Special binary v2i64 shuffle cases using SHUFPDrri.
2977 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2978 (SHUFPDrri VR128:$src1, VR128:$src2,
2979 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2980 Requires<[HasSSE2]>;
2982 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2983 let AddedComplexity = 15 in {
2984 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
2985 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2986 Requires<[OptForSpeed, HasSSE2]>;
2987 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
2988 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2989 Requires<[OptForSpeed, HasSSE2]>;
2991 let AddedComplexity = 10 in {
2992 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
2993 (UNPCKLPSrr VR128:$src, VR128:$src)>;
2994 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
2995 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
2996 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
2997 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
2998 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
2999 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3002 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3003 let AddedComplexity = 15 in {
3004 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3005 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3006 Requires<[OptForSpeed, HasSSE2]>;
3007 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3008 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3009 Requires<[OptForSpeed, HasSSE2]>;
3011 let AddedComplexity = 10 in {
3012 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3013 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3014 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3015 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3016 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3017 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3018 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3019 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3022 let AddedComplexity = 20 in {
3023 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3024 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3025 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3027 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3028 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3029 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3031 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3032 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3033 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3034 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3035 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3038 let AddedComplexity = 20 in {
3039 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3040 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3041 (MOVLPSrm VR128:$src1, addr:$src2)>;
3042 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3043 (MOVLPDrm VR128:$src1, addr:$src2)>;
3044 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3045 (MOVLPSrm VR128:$src1, addr:$src2)>;
3046 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3047 (MOVLPDrm VR128:$src1, addr:$src2)>;
3050 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3051 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3052 (MOVLPSmr addr:$src1, VR128:$src2)>;
3053 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3054 (MOVLPDmr addr:$src1, VR128:$src2)>;
3055 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3057 (MOVLPSmr addr:$src1, VR128:$src2)>;
3058 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3059 (MOVLPDmr addr:$src1, VR128:$src2)>;
3061 let AddedComplexity = 15 in {
3062 // Setting the lowest element in the vector.
3063 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3064 (MOVSSrr (v4i32 VR128:$src1),
3065 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3066 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3067 (MOVSDrr (v2i64 VR128:$src1),
3068 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3070 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3071 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3072 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3073 Requires<[HasSSE2]>;
3074 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3075 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3076 Requires<[HasSSE2]>;
3079 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3080 // fall back to this for SSE1)
3081 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3082 (SHUFPSrri VR128:$src2, VR128:$src1,
3083 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3085 // Set lowest element and zero upper elements.
3086 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3087 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3089 // Some special case pandn patterns.
3090 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3092 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3093 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3095 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3096 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3098 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3100 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3101 (memop addr:$src2))),
3102 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3103 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3104 (memop addr:$src2))),
3105 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3106 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3107 (memop addr:$src2))),
3108 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3110 // vector -> vector casts
3111 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3112 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3113 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3114 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3115 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3116 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3117 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3118 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3120 // Use movaps / movups for SSE integer load / store (one byte shorter).
3121 def : Pat<(alignedloadv4i32 addr:$src),
3122 (MOVAPSrm addr:$src)>;
3123 def : Pat<(loadv4i32 addr:$src),
3124 (MOVUPSrm addr:$src)>;
3125 def : Pat<(alignedloadv2i64 addr:$src),
3126 (MOVAPSrm addr:$src)>;
3127 def : Pat<(loadv2i64 addr:$src),
3128 (MOVUPSrm addr:$src)>;
3130 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3131 (MOVAPSmr addr:$dst, VR128:$src)>;
3132 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3133 (MOVAPSmr addr:$dst, VR128:$src)>;
3134 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3135 (MOVAPSmr addr:$dst, VR128:$src)>;
3136 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3137 (MOVAPSmr addr:$dst, VR128:$src)>;
3138 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3139 (MOVUPSmr addr:$dst, VR128:$src)>;
3140 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3141 (MOVUPSmr addr:$dst, VR128:$src)>;
3142 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3143 (MOVUPSmr addr:$dst, VR128:$src)>;
3144 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3145 (MOVUPSmr addr:$dst, VR128:$src)>;
3147 //===----------------------------------------------------------------------===//
3148 // SSE4.1 Instructions
3149 //===----------------------------------------------------------------------===//
3151 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3154 Intrinsic V2F64Int> {
3155 // Intrinsic operation, reg.
3156 // Vector intrinsic operation, reg
3157 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3158 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3159 !strconcat(OpcodeStr,
3160 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3161 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3164 // Vector intrinsic operation, mem
3165 def PSm_Int : Ii8<opcps, MRMSrcMem,
3166 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3167 !strconcat(OpcodeStr,
3168 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3170 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3172 Requires<[HasSSE41]>;
3174 // Vector intrinsic operation, reg
3175 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3176 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3177 !strconcat(OpcodeStr,
3178 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3179 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3182 // Vector intrinsic operation, mem
3183 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3184 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3185 !strconcat(OpcodeStr,
3186 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3188 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3192 let Constraints = "$src1 = $dst" in {
3193 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3197 // Intrinsic operation, reg.
3198 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3200 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3201 !strconcat(OpcodeStr,
3202 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3204 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3207 // Intrinsic operation, mem.
3208 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3210 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3211 !strconcat(OpcodeStr,
3212 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3214 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3217 // Intrinsic operation, reg.
3218 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3220 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3221 !strconcat(OpcodeStr,
3222 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3224 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3227 // Intrinsic operation, mem.
3228 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3230 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3231 !strconcat(OpcodeStr,
3232 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3234 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3239 // FP round - roundss, roundps, roundsd, roundpd
3240 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3241 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3242 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3243 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3245 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3246 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3247 Intrinsic IntId128> {
3248 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3250 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3251 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3252 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3254 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3257 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3260 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3261 int_x86_sse41_phminposuw>;
3263 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3264 let Constraints = "$src1 = $dst" in {
3265 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3266 Intrinsic IntId128, bit Commutable = 0> {
3267 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3268 (ins VR128:$src1, VR128:$src2),
3269 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3270 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3272 let isCommutable = Commutable;
3274 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3275 (ins VR128:$src1, i128mem:$src2),
3276 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3278 (IntId128 VR128:$src1,
3279 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3283 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3284 int_x86_sse41_pcmpeqq, 1>;
3285 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3286 int_x86_sse41_packusdw, 0>;
3287 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3288 int_x86_sse41_pminsb, 1>;
3289 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3290 int_x86_sse41_pminsd, 1>;
3291 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3292 int_x86_sse41_pminud, 1>;
3293 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3294 int_x86_sse41_pminuw, 1>;
3295 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3296 int_x86_sse41_pmaxsb, 1>;
3297 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3298 int_x86_sse41_pmaxsd, 1>;
3299 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3300 int_x86_sse41_pmaxud, 1>;
3301 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3302 int_x86_sse41_pmaxuw, 1>;
3304 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3306 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3307 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3308 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3309 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3311 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3312 let Constraints = "$src1 = $dst" in {
3313 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3314 SDNode OpNode, Intrinsic IntId128,
3315 bit Commutable = 0> {
3316 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3317 (ins VR128:$src1, VR128:$src2),
3318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3319 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3320 VR128:$src2))]>, OpSize {
3321 let isCommutable = Commutable;
3323 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3324 (ins VR128:$src1, VR128:$src2),
3325 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3326 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3328 let isCommutable = Commutable;
3330 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3331 (ins VR128:$src1, i128mem:$src2),
3332 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3334 (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
3335 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3336 (ins VR128:$src1, i128mem:$src2),
3337 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3339 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3344 /// SS48I_binop_rm - Simple SSE41 binary operator.
3345 let Constraints = "$src1 = $dst" in {
3346 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3347 ValueType OpVT, bit Commutable = 0> {
3348 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3349 (ins VR128:$src1, VR128:$src2),
3350 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3351 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
3353 let isCommutable = Commutable;
3355 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3356 (ins VR128:$src1, i128mem:$src2),
3357 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3358 [(set VR128:$dst, (OpNode VR128:$src1,
3359 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
3364 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
3366 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3367 let Constraints = "$src1 = $dst" in {
3368 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3369 Intrinsic IntId128, bit Commutable = 0> {
3370 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3371 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3372 !strconcat(OpcodeStr,
3373 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3375 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3377 let isCommutable = Commutable;
3379 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3380 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3381 !strconcat(OpcodeStr,
3382 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3384 (IntId128 VR128:$src1,
3385 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3390 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3391 int_x86_sse41_blendps, 0>;
3392 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3393 int_x86_sse41_blendpd, 0>;
3394 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3395 int_x86_sse41_pblendw, 0>;
3396 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3397 int_x86_sse41_dpps, 1>;
3398 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3399 int_x86_sse41_dppd, 1>;
3400 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3401 int_x86_sse41_mpsadbw, 0>;
3404 /// SS41I_ternary_int - SSE 4.1 ternary operator
3405 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3406 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3407 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3408 (ins VR128:$src1, VR128:$src2),
3409 !strconcat(OpcodeStr,
3410 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3411 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3414 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3415 (ins VR128:$src1, i128mem:$src2),
3416 !strconcat(OpcodeStr,
3417 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3420 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3424 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3425 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3426 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3429 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3430 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3431 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3432 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3434 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3435 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3437 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3441 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3442 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3443 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3444 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3445 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3446 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3448 // Common patterns involving scalar load.
3449 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3450 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3451 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3452 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3454 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3455 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3456 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3457 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3459 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3460 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3461 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3462 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3464 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3465 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3466 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3467 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3469 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3470 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3471 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3472 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3474 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3475 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3476 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3477 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3480 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3481 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3482 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3483 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3485 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3486 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3488 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3492 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3493 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3494 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3495 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3497 // Common patterns involving scalar load
3498 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3499 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3500 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3501 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3503 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3504 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3505 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3506 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3509 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3510 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3511 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3512 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3514 // Expecting a i16 load any extended to i32 value.
3515 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3516 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3517 [(set VR128:$dst, (IntId (bitconvert
3518 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3522 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3523 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3525 // Common patterns involving scalar load
3526 def : Pat<(int_x86_sse41_pmovsxbq
3527 (bitconvert (v4i32 (X86vzmovl
3528 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3529 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3531 def : Pat<(int_x86_sse41_pmovzxbq
3532 (bitconvert (v4i32 (X86vzmovl
3533 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3534 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3537 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3538 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3539 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3540 (ins VR128:$src1, i32i8imm:$src2),
3541 !strconcat(OpcodeStr,
3542 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3543 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3545 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3546 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3547 !strconcat(OpcodeStr,
3548 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3551 // There's an AssertZext in the way of writing the store pattern
3552 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3555 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3558 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3559 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3560 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3561 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3562 !strconcat(OpcodeStr,
3563 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3566 // There's an AssertZext in the way of writing the store pattern
3567 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3570 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3573 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3574 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3575 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3576 (ins VR128:$src1, i32i8imm:$src2),
3577 !strconcat(OpcodeStr,
3578 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3580 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3581 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3582 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3583 !strconcat(OpcodeStr,
3584 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3585 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3586 addr:$dst)]>, OpSize;
3589 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3592 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3594 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3595 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3596 (ins VR128:$src1, i32i8imm:$src2),
3597 !strconcat(OpcodeStr,
3598 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3600 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3602 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3603 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3604 !strconcat(OpcodeStr,
3605 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3606 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3607 addr:$dst)]>, OpSize;
3610 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3612 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3613 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3616 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3617 Requires<[HasSSE41]>;
3619 let Constraints = "$src1 = $dst" in {
3620 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3621 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3622 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3623 !strconcat(OpcodeStr,
3624 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3626 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3627 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3628 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3629 !strconcat(OpcodeStr,
3630 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3632 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3633 imm:$src3))]>, OpSize;
3637 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3639 let Constraints = "$src1 = $dst" in {
3640 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3641 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3642 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3643 !strconcat(OpcodeStr,
3644 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3646 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3648 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3649 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3650 !strconcat(OpcodeStr,
3651 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3653 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3654 imm:$src3)))]>, OpSize;
3658 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3660 // insertps has a few different modes, there's the first two here below which
3661 // are optimized inserts that won't zero arbitrary elements in the destination
3662 // vector. The next one matches the intrinsic and could zero arbitrary elements
3663 // in the target vector.
3664 let Constraints = "$src1 = $dst" in {
3665 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3666 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3667 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3668 !strconcat(OpcodeStr,
3669 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3671 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3673 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3674 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3675 !strconcat(OpcodeStr,
3676 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3678 (X86insrtps VR128:$src1,
3679 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3680 imm:$src3))]>, OpSize;
3684 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3686 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3687 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3689 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3690 // the intel intrinsic that corresponds to this.
3691 let Defs = [EFLAGS] in {
3692 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3693 "ptest \t{$src2, $src1|$src1, $src2}",
3694 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
3696 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3697 "ptest \t{$src2, $src1|$src1, $src2}",
3698 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
3702 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3703 "movntdqa\t{$src, $dst|$dst, $src}",
3704 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
3708 //===----------------------------------------------------------------------===//
3709 // SSE4.2 Instructions
3710 //===----------------------------------------------------------------------===//
3712 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3713 let Constraints = "$src1 = $dst" in {
3714 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3715 Intrinsic IntId128, bit Commutable = 0> {
3716 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3717 (ins VR128:$src1, VR128:$src2),
3718 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3719 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3721 let isCommutable = Commutable;
3723 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3724 (ins VR128:$src1, i128mem:$src2),
3725 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3727 (IntId128 VR128:$src1,
3728 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3732 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3734 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3735 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3736 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3737 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3739 // crc intrinsic instruction
3740 // This set of instructions are only rm, the only difference is the size
3742 let Constraints = "$src1 = $dst" in {
3743 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3744 (ins GR32:$src1, i8mem:$src2),
3745 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3747 (int_x86_sse42_crc32_8 GR32:$src1,
3748 (load addr:$src2)))]>;
3749 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3750 (ins GR32:$src1, GR8:$src2),
3751 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3753 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
3754 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3755 (ins GR32:$src1, i16mem:$src2),
3756 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3758 (int_x86_sse42_crc32_16 GR32:$src1,
3759 (load addr:$src2)))]>,
3761 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3762 (ins GR32:$src1, GR16:$src2),
3763 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3765 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3767 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3768 (ins GR32:$src1, i32mem:$src2),
3769 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3771 (int_x86_sse42_crc32_32 GR32:$src1,
3772 (load addr:$src2)))]>;
3773 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3774 (ins GR32:$src1, GR32:$src2),
3775 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3777 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
3778 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3779 (ins GR64:$src1, i8mem:$src2),
3780 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3782 (int_x86_sse42_crc64_8 GR64:$src1,
3783 (load addr:$src2)))]>,
3785 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3786 (ins GR64:$src1, GR8:$src2),
3787 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3789 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
3791 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
3792 (ins GR64:$src1, i64mem:$src2),
3793 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3795 (int_x86_sse42_crc64_64 GR64:$src1,
3796 (load addr:$src2)))]>,
3798 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
3799 (ins GR64:$src1, GR64:$src2),
3800 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3802 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
3806 // String/text processing instructions.
3807 let Defs = [EFLAGS], usesCustomInserter = 1 in {
3808 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3809 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3810 "#PCMPISTRM128rr PSEUDO!",
3811 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
3812 imm:$src3))]>, OpSize;
3813 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3814 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3815 "#PCMPISTRM128rm PSEUDO!",
3816 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
3817 imm:$src3))]>, OpSize;
3820 let Defs = [XMM0, EFLAGS] in {
3821 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
3822 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3823 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3824 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
3825 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3826 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3829 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
3830 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3831 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3832 "#PCMPESTRM128rr PSEUDO!",
3834 (int_x86_sse42_pcmpestrm128
3835 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
3837 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3838 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3839 "#PCMPESTRM128rm PSEUDO!",
3840 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
3841 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
3845 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
3846 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
3847 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3848 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3849 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
3850 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3851 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3854 let Defs = [ECX, EFLAGS] in {
3855 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
3856 def rr : SS42AI<0x63, MRMSrcReg, (outs),
3857 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3858 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3859 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
3860 (implicit EFLAGS)]>, OpSize;
3861 def rm : SS42AI<0x63, MRMSrcMem, (outs),
3862 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3863 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3864 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
3865 (implicit EFLAGS)]>, OpSize;
3869 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
3870 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
3871 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
3872 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
3873 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
3874 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
3876 let Defs = [ECX, EFLAGS] in {
3877 let Uses = [EAX, EDX] in {
3878 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
3879 def rr : SS42AI<0x61, MRMSrcReg, (outs),
3880 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3881 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3882 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
3883 (implicit EFLAGS)]>, OpSize;
3884 def rm : SS42AI<0x61, MRMSrcMem, (outs),
3885 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3886 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3888 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
3889 (implicit EFLAGS)]>, OpSize;
3894 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
3895 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
3896 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
3897 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
3898 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
3899 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
3901 //===----------------------------------------------------------------------===//
3902 // AES-NI Instructions
3903 //===----------------------------------------------------------------------===//
3905 let Constraints = "$src1 = $dst" in {
3906 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
3907 Intrinsic IntId128, bit Commutable = 0> {
3908 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
3909 (ins VR128:$src1, VR128:$src2),
3910 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3911 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3913 let isCommutable = Commutable;
3915 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
3916 (ins VR128:$src1, i128mem:$src2),
3917 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3919 (IntId128 VR128:$src1,
3920 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3924 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
3925 int_x86_aesni_aesenc>;
3926 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
3927 int_x86_aesni_aesenclast>;
3928 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
3929 int_x86_aesni_aesdec>;
3930 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
3931 int_x86_aesni_aesdeclast>;
3933 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
3934 (AESENCrr VR128:$src1, VR128:$src2)>;
3935 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
3936 (AESENCrm VR128:$src1, addr:$src2)>;
3937 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
3938 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
3939 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
3940 (AESENCLASTrm VR128:$src1, addr:$src2)>;
3941 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
3942 (AESDECrr VR128:$src1, VR128:$src2)>;
3943 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
3944 (AESDECrm VR128:$src1, addr:$src2)>;
3945 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
3946 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
3947 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
3948 (AESDECLASTrm VR128:$src1, addr:$src2)>;
3950 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
3952 "aesimc\t{$src1, $dst|$dst, $src1}",
3954 (int_x86_aesni_aesimc VR128:$src1))]>,
3957 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
3958 (ins i128mem:$src1),
3959 "aesimc\t{$src1, $dst|$dst, $src1}",
3961 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
3964 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
3965 (ins VR128:$src1, i8imm:$src2),
3966 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3968 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
3970 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
3971 (ins i128mem:$src1, i8imm:$src2),
3972 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3974 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),