1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // Non-instruction patterns
120 //===----------------------------------------------------------------------===//
122 // A vector extract of the first f32/f64 position is a subregister copy
123 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
124 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
125 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
126 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
128 // A 128-bit subvector extract from the first 256-bit vector position
129 // is a subregister copy that needs no instruction.
130 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
131 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
132 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
133 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
135 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
136 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
137 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
138 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
140 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
141 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
142 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
143 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
145 // A 128-bit subvector insert to the first 256-bit vector position
146 // is a subregister copy that needs no instruction.
147 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
148 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
149 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
150 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
151 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
152 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
153 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
154 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
155 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
156 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
157 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
158 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
160 // Implicitly promote a 32-bit scalar to a vector.
161 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
162 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
163 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
164 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
165 // Implicitly promote a 64-bit scalar to a vector.
166 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
167 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
168 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
169 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
171 // Bitcasts between 128-bit vector types. Return the original type since
172 // no instruction is needed for the conversion
173 let Predicates = [HasXMMInt] in {
174 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
175 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
176 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
178 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
179 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
180 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
183 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
184 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
185 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
188 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
189 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
190 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
193 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
194 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
195 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
198 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
199 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
200 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
202 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
203 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
206 // Bitcasts between 256-bit vector types. Return the original type since
207 // no instruction is needed for the conversion
208 let Predicates = [HasAVX] in {
209 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
210 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
211 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
213 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
214 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
215 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
218 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
219 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
220 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
223 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
224 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
225 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
228 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
229 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
230 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
233 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
234 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
235 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
237 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
238 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
241 // Alias instructions that map fld0 to pxor for sse.
242 // FIXME: Set encoding to pseudo!
243 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
244 canFoldAsLoad = 1 in {
245 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
246 [(set FR32:$dst, fp32imm0)]>,
247 Requires<[HasSSE1]>, TB, OpSize;
248 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
249 [(set FR64:$dst, fpimm0)]>,
250 Requires<[HasSSE2]>, TB, OpSize;
251 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
252 [(set FR32:$dst, fp32imm0)]>,
253 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
254 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
255 [(set FR64:$dst, fpimm0)]>,
256 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
259 //===----------------------------------------------------------------------===//
260 // AVX & SSE - Zero/One Vectors
261 //===----------------------------------------------------------------------===//
263 // Alias instructions that map zero vector to pxor / xorp* for sse.
264 // We set canFoldAsLoad because this can be converted to a constant-pool
265 // load of an all-zeros value if folding it would be beneficial.
266 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
267 // JIT implementation, it does not expand the instructions below like
268 // X86MCInstLower does.
269 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
270 isCodeGenOnly = 1 in {
271 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
272 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
273 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
274 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
275 let ExeDomain = SSEPackedInt in
276 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
277 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
280 // The same as done above but for AVX. The 128-bit versions are the
281 // same, but re-encoded. The 256-bit does not support PI version, and
282 // doesn't need it because on sandy bridge the register is set to zero
283 // at the rename stage without using any execution unit, so SET0PSY
284 // and SET0PDY can be used for vector int instructions without penalty
285 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
286 // JIT implementatioan, it does not expand the instructions below like
287 // X86MCInstLower does.
288 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
289 isCodeGenOnly = 1, Predicates = [HasAVX] in {
290 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
291 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
292 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
293 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
294 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
295 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
296 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
297 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
298 let ExeDomain = SSEPackedInt in
299 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
300 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
303 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
304 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
305 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
307 // AVX has no support for 256-bit integer instructions, but since the 128-bit
308 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
309 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
310 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
311 (SUBREG_TO_REG (i32 0), (AVX_SET0PI), sub_xmm)>;
313 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
314 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
315 (SUBREG_TO_REG (i64 0), (AVX_SET0PI), sub_xmm)>;
317 // We set canFoldAsLoad because this can be converted to a constant-pool
318 // load of an all-ones value if folding it would be beneficial.
319 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
320 // JIT implementation, it does not expand the instructions below like
321 // X86MCInstLower does.
322 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
323 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
324 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
325 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
326 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
327 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
328 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
329 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
332 //===----------------------------------------------------------------------===//
333 // SSE 1 & 2 - Move FP Scalar Instructions
335 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
336 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
337 // is used instead. Register-to-register movss/movsd is not modeled as an
338 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
339 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
340 //===----------------------------------------------------------------------===//
342 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
343 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
344 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
346 // Loading from memory automatically zeroing upper bits.
347 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
348 PatFrag mem_pat, string OpcodeStr> :
349 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
350 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
351 [(set RC:$dst, (mem_pat addr:$src))]>;
354 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
355 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
356 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
357 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
359 let canFoldAsLoad = 1, isReMaterializable = 1 in {
360 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
361 let AddedComplexity = 20 in
362 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
365 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
366 "movss\t{$src, $dst|$dst, $src}",
367 [(store FR32:$src, addr:$dst)]>, XS, VEX;
368 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
369 "movsd\t{$src, $dst|$dst, $src}",
370 [(store FR64:$src, addr:$dst)]>, XD, VEX;
373 let Constraints = "$src1 = $dst" in {
374 def MOVSSrr : sse12_move_rr<FR32, v4f32,
375 "movss\t{$src2, $dst|$dst, $src2}">, XS;
376 def MOVSDrr : sse12_move_rr<FR64, v2f64,
377 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
380 let canFoldAsLoad = 1, isReMaterializable = 1 in {
381 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
383 let AddedComplexity = 20 in
384 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
387 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
388 "movss\t{$src, $dst|$dst, $src}",
389 [(store FR32:$src, addr:$dst)]>;
390 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
391 "movsd\t{$src, $dst|$dst, $src}",
392 [(store FR64:$src, addr:$dst)]>;
395 let Predicates = [HasSSE1] in {
396 let AddedComplexity = 15 in {
397 // Extract the low 32-bit value from one vector and insert it into another.
398 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
399 (MOVSSrr (v4f32 VR128:$src1),
400 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
401 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
402 (MOVSSrr (v4i32 VR128:$src1),
403 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
405 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
406 // MOVSS to the lower bits.
407 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
408 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
409 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
410 (MOVSSrr (v4f32 (V_SET0PS)),
411 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
412 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
413 (MOVSSrr (v4i32 (V_SET0PI)),
414 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
417 let AddedComplexity = 20 in {
418 // MOVSSrm zeros the high parts of the register; represent this
419 // with SUBREG_TO_REG.
420 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
421 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
422 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
423 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
424 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
425 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
428 // Extract and store.
429 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
432 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
434 // Shuffle with MOVSS
435 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
436 (MOVSSrr VR128:$src1, FR32:$src2)>;
437 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
438 (MOVSSrr (v4i32 VR128:$src1),
439 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
440 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
441 (MOVSSrr (v4f32 VR128:$src1),
442 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
445 let Predicates = [HasSSE2] in {
446 let AddedComplexity = 15 in {
447 // Extract the low 64-bit value from one vector and insert it into another.
448 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
449 (MOVSDrr (v2f64 VR128:$src1),
450 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
451 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
452 (MOVSDrr (v2i64 VR128:$src1),
453 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
455 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
456 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
457 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
458 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
459 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
461 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
462 // MOVSD to the lower bits.
463 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
464 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
467 let AddedComplexity = 20 in {
468 // MOVSDrm zeros the high parts of the register; represent this
469 // with SUBREG_TO_REG.
470 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
471 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
472 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
473 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
474 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
475 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
476 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
477 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
478 def : Pat<(v2f64 (X86vzload addr:$src)),
479 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
482 // Extract and store.
483 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
486 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
488 // Shuffle with MOVSD
489 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
490 (MOVSDrr VR128:$src1, FR64:$src2)>;
491 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
492 (MOVSDrr (v2i64 VR128:$src1),
493 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
494 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
495 (MOVSDrr (v2f64 VR128:$src1),
496 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
497 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
498 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
499 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
500 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
502 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
503 // is during lowering, where it's not possible to recognize the fold cause
504 // it has two uses through a bitcast. One use disappears at isel time and the
505 // fold opportunity reappears.
506 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
507 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
508 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
509 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
512 let Predicates = [HasAVX] in {
513 let AddedComplexity = 15 in {
514 // Extract the low 32-bit value from one vector and insert it into another.
515 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
516 (VMOVSSrr (v4f32 VR128:$src1),
517 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
518 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
519 (VMOVSSrr (v4i32 VR128:$src1),
520 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
522 // Extract the low 64-bit value from one vector and insert it into another.
523 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
524 (VMOVSDrr (v2f64 VR128:$src1),
525 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
526 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
527 (VMOVSDrr (v2i64 VR128:$src1),
528 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
530 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
531 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
532 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
533 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
534 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
536 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
537 // MOVS{S,D} to the lower bits.
538 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
539 (VMOVSSrr (v4f32 (AVX_SET0PS)), FR32:$src)>;
540 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
541 (VMOVSSrr (v4f32 (AVX_SET0PS)),
542 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
543 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
544 (VMOVSSrr (v4i32 (AVX_SET0PI)),
545 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
546 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
547 (VMOVSDrr (v2f64 (AVX_SET0PS)), FR64:$src)>;
550 let AddedComplexity = 20 in {
551 // MOVSSrm zeros the high parts of the register; represent this
552 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
553 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
554 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
555 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
556 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
557 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
558 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
560 // MOVSDrm zeros the high parts of the register; represent this
561 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
562 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
563 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
564 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
565 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
566 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
567 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
568 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
569 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
570 def : Pat<(v2f64 (X86vzload addr:$src)),
571 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
573 // Represent the same patterns above but in the form they appear for
575 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
576 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
577 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
578 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
579 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
580 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
582 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
583 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
584 (SUBREG_TO_REG (i32 0),
585 (v4f32 (VMOVSSrr (v4f32 (AVX_SET0PS)), FR32:$src)),
587 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
588 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
589 (SUBREG_TO_REG (i64 0),
590 (v2f64 (VMOVSDrr (v2f64 (AVX_SET0PS)), FR64:$src)),
593 // Extract and store.
594 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
597 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
598 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
601 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
603 // Shuffle with VMOVSS
604 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
605 (VMOVSSrr VR128:$src1, FR32:$src2)>;
606 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
607 (VMOVSSrr (v4i32 VR128:$src1),
608 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
609 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
610 (VMOVSSrr (v4f32 VR128:$src1),
611 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
613 // Shuffle with VMOVSD
614 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
615 (VMOVSDrr VR128:$src1, FR64:$src2)>;
616 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
617 (VMOVSDrr (v2i64 VR128:$src1),
618 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
619 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
620 (VMOVSDrr (v2f64 VR128:$src1),
621 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
622 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
623 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
625 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
626 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
629 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
630 // is during lowering, where it's not possible to recognize the fold cause
631 // it has two uses through a bitcast. One use disappears at isel time and the
632 // fold opportunity reappears.
633 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
634 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
636 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
637 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
641 //===----------------------------------------------------------------------===//
642 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
643 //===----------------------------------------------------------------------===//
645 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
646 X86MemOperand x86memop, PatFrag ld_frag,
647 string asm, Domain d,
648 bit IsReMaterializable = 1> {
649 let neverHasSideEffects = 1 in
650 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
651 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
652 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
653 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
654 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
655 [(set RC:$dst, (ld_frag addr:$src))], d>;
658 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
659 "movaps", SSEPackedSingle>, TB, VEX;
660 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
661 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
662 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
663 "movups", SSEPackedSingle>, TB, VEX;
664 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
665 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
667 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
668 "movaps", SSEPackedSingle>, TB, VEX;
669 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
670 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
671 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
672 "movups", SSEPackedSingle>, TB, VEX;
673 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
674 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
675 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
676 "movaps", SSEPackedSingle>, TB;
677 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
678 "movapd", SSEPackedDouble>, TB, OpSize;
679 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
680 "movups", SSEPackedSingle>, TB;
681 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
682 "movupd", SSEPackedDouble, 0>, TB, OpSize;
684 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
685 "movaps\t{$src, $dst|$dst, $src}",
686 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
687 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
688 "movapd\t{$src, $dst|$dst, $src}",
689 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
690 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
691 "movups\t{$src, $dst|$dst, $src}",
692 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
693 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
694 "movupd\t{$src, $dst|$dst, $src}",
695 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
696 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
697 "movaps\t{$src, $dst|$dst, $src}",
698 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
699 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
700 "movapd\t{$src, $dst|$dst, $src}",
701 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
702 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
703 "movups\t{$src, $dst|$dst, $src}",
704 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
705 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
706 "movupd\t{$src, $dst|$dst, $src}",
707 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
709 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
710 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
711 (VMOVUPSYmr addr:$dst, VR256:$src)>;
713 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
714 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
715 (VMOVUPDYmr addr:$dst, VR256:$src)>;
717 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
718 "movaps\t{$src, $dst|$dst, $src}",
719 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
720 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
721 "movapd\t{$src, $dst|$dst, $src}",
722 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
723 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
724 "movups\t{$src, $dst|$dst, $src}",
725 [(store (v4f32 VR128:$src), addr:$dst)]>;
726 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
727 "movupd\t{$src, $dst|$dst, $src}",
728 [(store (v2f64 VR128:$src), addr:$dst)]>;
730 let Predicates = [HasAVX] in {
731 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
732 (VMOVUPSmr addr:$dst, VR128:$src)>;
733 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
734 (VMOVUPDmr addr:$dst, VR128:$src)>;
737 let Predicates = [HasSSE1] in
738 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
739 (MOVUPSmr addr:$dst, VR128:$src)>;
740 let Predicates = [HasSSE2] in
741 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
742 (MOVUPDmr addr:$dst, VR128:$src)>;
744 // Use movaps / movups for SSE integer load / store (one byte shorter).
745 // The instructions selected below are then converted to MOVDQA/MOVDQU
746 // during the SSE domain pass.
747 let Predicates = [HasSSE1] in {
748 def : Pat<(alignedloadv4i32 addr:$src),
749 (MOVAPSrm addr:$src)>;
750 def : Pat<(loadv4i32 addr:$src),
751 (MOVUPSrm addr:$src)>;
752 def : Pat<(alignedloadv2i64 addr:$src),
753 (MOVAPSrm addr:$src)>;
754 def : Pat<(loadv2i64 addr:$src),
755 (MOVUPSrm addr:$src)>;
757 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
758 (MOVAPSmr addr:$dst, VR128:$src)>;
759 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
760 (MOVAPSmr addr:$dst, VR128:$src)>;
761 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
762 (MOVAPSmr addr:$dst, VR128:$src)>;
763 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
764 (MOVAPSmr addr:$dst, VR128:$src)>;
765 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
766 (MOVUPSmr addr:$dst, VR128:$src)>;
767 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
768 (MOVUPSmr addr:$dst, VR128:$src)>;
769 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
770 (MOVUPSmr addr:$dst, VR128:$src)>;
771 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
772 (MOVUPSmr addr:$dst, VR128:$src)>;
775 // Use vmovaps/vmovups for AVX integer load/store.
776 let Predicates = [HasAVX] in {
777 // 128-bit load/store
778 def : Pat<(alignedloadv4i32 addr:$src),
779 (VMOVAPSrm addr:$src)>;
780 def : Pat<(loadv4i32 addr:$src),
781 (VMOVUPSrm addr:$src)>;
782 def : Pat<(alignedloadv2i64 addr:$src),
783 (VMOVAPSrm addr:$src)>;
784 def : Pat<(loadv2i64 addr:$src),
785 (VMOVUPSrm addr:$src)>;
787 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
788 (VMOVAPSmr addr:$dst, VR128:$src)>;
789 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
790 (VMOVAPSmr addr:$dst, VR128:$src)>;
791 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
792 (VMOVAPSmr addr:$dst, VR128:$src)>;
793 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
794 (VMOVAPSmr addr:$dst, VR128:$src)>;
795 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
796 (VMOVUPSmr addr:$dst, VR128:$src)>;
797 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
798 (VMOVUPSmr addr:$dst, VR128:$src)>;
799 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
800 (VMOVUPSmr addr:$dst, VR128:$src)>;
801 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
802 (VMOVUPSmr addr:$dst, VR128:$src)>;
804 // 256-bit load/store
805 def : Pat<(alignedloadv4i64 addr:$src),
806 (VMOVAPSYrm addr:$src)>;
807 def : Pat<(loadv4i64 addr:$src),
808 (VMOVUPSYrm addr:$src)>;
809 def : Pat<(alignedloadv8i32 addr:$src),
810 (VMOVAPSYrm addr:$src)>;
811 def : Pat<(loadv8i32 addr:$src),
812 (VMOVUPSYrm addr:$src)>;
813 def : Pat<(alignedstore (v4i64 VR256:$src), addr:$dst),
814 (VMOVAPSYmr addr:$dst, VR256:$src)>;
815 def : Pat<(alignedstore (v8i32 VR256:$src), addr:$dst),
816 (VMOVAPSYmr addr:$dst, VR256:$src)>;
817 def : Pat<(alignedstore (v16i16 VR256:$src), addr:$dst),
818 (VMOVAPSYmr addr:$dst, VR256:$src)>;
819 def : Pat<(alignedstore (v32i8 VR256:$src), addr:$dst),
820 (VMOVAPSYmr addr:$dst, VR256:$src)>;
821 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
822 (VMOVUPSYmr addr:$dst, VR256:$src)>;
823 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
824 (VMOVUPSYmr addr:$dst, VR256:$src)>;
825 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
826 (VMOVUPSYmr addr:$dst, VR256:$src)>;
827 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
828 (VMOVUPSYmr addr:$dst, VR256:$src)>;
831 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
832 // bits are disregarded. FIXME: Set encoding to pseudo!
833 let neverHasSideEffects = 1 in {
834 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
835 "movaps\t{$src, $dst|$dst, $src}", []>;
836 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
837 "movapd\t{$src, $dst|$dst, $src}", []>;
838 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
839 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
840 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
841 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
844 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
845 // bits are disregarded. FIXME: Set encoding to pseudo!
846 let canFoldAsLoad = 1, isReMaterializable = 1 in {
847 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
848 "movaps\t{$src, $dst|$dst, $src}",
849 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
850 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
851 "movapd\t{$src, $dst|$dst, $src}",
852 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
853 let isCodeGenOnly = 1 in {
854 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
855 "movaps\t{$src, $dst|$dst, $src}",
856 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
857 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
858 "movapd\t{$src, $dst|$dst, $src}",
859 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
863 //===----------------------------------------------------------------------===//
864 // SSE 1 & 2 - Move Low packed FP Instructions
865 //===----------------------------------------------------------------------===//
867 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
868 PatFrag mov_frag, string base_opc,
870 def PSrm : PI<opc, MRMSrcMem,
871 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
872 !strconcat(base_opc, "s", asm_opr),
875 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
876 SSEPackedSingle>, TB;
878 def PDrm : PI<opc, MRMSrcMem,
879 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
880 !strconcat(base_opc, "d", asm_opr),
881 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
882 (scalar_to_vector (loadf64 addr:$src2)))))],
883 SSEPackedDouble>, TB, OpSize;
886 let AddedComplexity = 20 in {
887 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
888 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
890 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
891 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
892 "\t{$src2, $dst|$dst, $src2}">;
895 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
896 "movlps\t{$src, $dst|$dst, $src}",
897 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
898 (iPTR 0))), addr:$dst)]>, VEX;
899 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
900 "movlpd\t{$src, $dst|$dst, $src}",
901 [(store (f64 (vector_extract (v2f64 VR128:$src),
902 (iPTR 0))), addr:$dst)]>, VEX;
903 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
904 "movlps\t{$src, $dst|$dst, $src}",
905 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
906 (iPTR 0))), addr:$dst)]>;
907 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
908 "movlpd\t{$src, $dst|$dst, $src}",
909 [(store (f64 (vector_extract (v2f64 VR128:$src),
910 (iPTR 0))), addr:$dst)]>;
912 let Predicates = [HasAVX] in {
913 let AddedComplexity = 20 in {
914 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
915 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
916 (VMOVLPSrm VR128:$src1, addr:$src2)>;
917 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
918 (VMOVLPSrm VR128:$src1, addr:$src2)>;
919 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
920 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
921 (VMOVLPDrm VR128:$src1, addr:$src2)>;
922 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
923 (VMOVLPDrm VR128:$src1, addr:$src2)>;
926 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
927 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
928 (VMOVLPSmr addr:$src1, VR128:$src2)>;
929 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
930 VR128:$src2)), addr:$src1),
931 (VMOVLPSmr addr:$src1, VR128:$src2)>;
933 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
934 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
935 (VMOVLPDmr addr:$src1, VR128:$src2)>;
936 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
937 (VMOVLPDmr addr:$src1, VR128:$src2)>;
939 // Shuffle with VMOVLPS
940 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
941 (VMOVLPSrm VR128:$src1, addr:$src2)>;
942 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
943 (VMOVLPSrm VR128:$src1, addr:$src2)>;
944 def : Pat<(X86Movlps VR128:$src1,
945 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
946 (VMOVLPSrm VR128:$src1, addr:$src2)>;
948 // Shuffle with VMOVLPD
949 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
950 (VMOVLPDrm VR128:$src1, addr:$src2)>;
951 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
952 (VMOVLPDrm VR128:$src1, addr:$src2)>;
953 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
954 (scalar_to_vector (loadf64 addr:$src2)))),
955 (VMOVLPDrm VR128:$src1, addr:$src2)>;
958 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
960 (VMOVLPSmr addr:$src1, VR128:$src2)>;
961 def : Pat<(store (v4i32 (X86Movlps
962 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
963 (VMOVLPSmr addr:$src1, VR128:$src2)>;
964 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
966 (VMOVLPDmr addr:$src1, VR128:$src2)>;
967 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
969 (VMOVLPDmr addr:$src1, VR128:$src2)>;
972 let Predicates = [HasSSE1] in {
973 let AddedComplexity = 20 in {
974 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
975 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
976 (MOVLPSrm VR128:$src1, addr:$src2)>;
977 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
978 (MOVLPSrm VR128:$src1, addr:$src2)>;
981 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
982 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
983 (MOVLPSmr addr:$src1, VR128:$src2)>;
984 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
985 VR128:$src2)), addr:$src1),
986 (MOVLPSmr addr:$src1, VR128:$src2)>;
988 // Shuffle with MOVLPS
989 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
990 (MOVLPSrm VR128:$src1, addr:$src2)>;
991 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
992 (MOVLPSrm VR128:$src1, addr:$src2)>;
993 def : Pat<(X86Movlps VR128:$src1,
994 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
995 (MOVLPSrm VR128:$src1, addr:$src2)>;
998 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1000 (MOVLPSmr addr:$src1, VR128:$src2)>;
1001 def : Pat<(store (v4i32 (X86Movlps
1002 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1004 (MOVLPSmr addr:$src1, VR128:$src2)>;
1007 let Predicates = [HasSSE2] in {
1008 let AddedComplexity = 20 in {
1009 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1010 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1011 (MOVLPDrm VR128:$src1, addr:$src2)>;
1012 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1013 (MOVLPDrm VR128:$src1, addr:$src2)>;
1016 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1017 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1018 (MOVLPDmr addr:$src1, VR128:$src2)>;
1019 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1020 (MOVLPDmr addr:$src1, VR128:$src2)>;
1022 // Shuffle with MOVLPD
1023 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1024 (MOVLPDrm VR128:$src1, addr:$src2)>;
1025 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1026 (MOVLPDrm VR128:$src1, addr:$src2)>;
1027 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1028 (scalar_to_vector (loadf64 addr:$src2)))),
1029 (MOVLPDrm VR128:$src1, addr:$src2)>;
1032 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1034 (MOVLPDmr addr:$src1, VR128:$src2)>;
1035 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1037 (MOVLPDmr addr:$src1, VR128:$src2)>;
1040 //===----------------------------------------------------------------------===//
1041 // SSE 1 & 2 - Move Hi packed FP Instructions
1042 //===----------------------------------------------------------------------===//
1044 let AddedComplexity = 20 in {
1045 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1046 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1048 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1049 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1050 "\t{$src2, $dst|$dst, $src2}">;
1053 // v2f64 extract element 1 is always custom lowered to unpack high to low
1054 // and extract element 0 so the non-store version isn't too horrible.
1055 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1056 "movhps\t{$src, $dst|$dst, $src}",
1057 [(store (f64 (vector_extract
1058 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1059 (undef)), (iPTR 0))), addr:$dst)]>,
1061 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1062 "movhpd\t{$src, $dst|$dst, $src}",
1063 [(store (f64 (vector_extract
1064 (v2f64 (unpckh VR128:$src, (undef))),
1065 (iPTR 0))), addr:$dst)]>,
1067 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1068 "movhps\t{$src, $dst|$dst, $src}",
1069 [(store (f64 (vector_extract
1070 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1071 (undef)), (iPTR 0))), addr:$dst)]>;
1072 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1073 "movhpd\t{$src, $dst|$dst, $src}",
1074 [(store (f64 (vector_extract
1075 (v2f64 (unpckh VR128:$src, (undef))),
1076 (iPTR 0))), addr:$dst)]>;
1078 let Predicates = [HasAVX] in {
1080 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1081 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1082 def : Pat<(X86Movlhps VR128:$src1,
1083 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1084 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1085 def : Pat<(X86Movlhps VR128:$src1,
1086 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1087 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1089 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1090 // is during lowering, where it's not possible to recognize the load fold cause
1091 // it has two uses through a bitcast. One use disappears at isel time and the
1092 // fold opportunity reappears.
1093 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1094 (scalar_to_vector (loadf64 addr:$src2)))),
1095 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1097 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1098 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1099 (scalar_to_vector (loadf64 addr:$src2)))),
1100 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1103 def : Pat<(store (f64 (vector_extract
1104 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1105 (VMOVHPSmr addr:$dst, VR128:$src)>;
1106 def : Pat<(store (f64 (vector_extract
1107 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1108 (VMOVHPDmr addr:$dst, VR128:$src)>;
1111 let Predicates = [HasSSE1] in {
1113 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1114 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1115 def : Pat<(X86Movlhps VR128:$src1,
1116 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1117 (MOVHPSrm VR128:$src1, addr:$src2)>;
1118 def : Pat<(X86Movlhps VR128:$src1,
1119 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1120 (MOVHPSrm VR128:$src1, addr:$src2)>;
1123 def : Pat<(store (f64 (vector_extract
1124 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1125 (MOVHPSmr addr:$dst, VR128:$src)>;
1128 let Predicates = [HasSSE2] in {
1129 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1130 // is during lowering, where it's not possible to recognize the load fold cause
1131 // it has two uses through a bitcast. One use disappears at isel time and the
1132 // fold opportunity reappears.
1133 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1134 (scalar_to_vector (loadf64 addr:$src2)))),
1135 (MOVHPDrm VR128:$src1, addr:$src2)>;
1137 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1138 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1139 (scalar_to_vector (loadf64 addr:$src2)))),
1140 (MOVHPDrm VR128:$src1, addr:$src2)>;
1143 def : Pat<(store (f64 (vector_extract
1144 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
1145 (MOVHPDmr addr:$dst, VR128:$src)>;
1148 //===----------------------------------------------------------------------===//
1149 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1150 //===----------------------------------------------------------------------===//
1152 let AddedComplexity = 20 in {
1153 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1154 (ins VR128:$src1, VR128:$src2),
1155 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1157 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
1159 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1160 (ins VR128:$src1, VR128:$src2),
1161 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1163 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
1166 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1167 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1168 (ins VR128:$src1, VR128:$src2),
1169 "movlhps\t{$src2, $dst|$dst, $src2}",
1171 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
1172 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1173 (ins VR128:$src1, VR128:$src2),
1174 "movhlps\t{$src2, $dst|$dst, $src2}",
1176 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
1179 let Predicates = [HasAVX] in {
1181 let AddedComplexity = 20 in {
1182 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1183 (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1184 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1185 (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1187 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1188 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1189 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1191 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1192 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1193 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1194 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1195 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1196 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1199 let AddedComplexity = 20 in {
1200 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1201 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1202 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1204 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1205 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1206 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1207 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1208 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1211 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1212 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1213 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1214 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1217 let Predicates = [HasSSE1] in {
1219 let AddedComplexity = 20 in {
1220 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1221 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1222 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1223 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1225 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1226 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1227 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1229 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1230 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1231 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1232 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1233 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1234 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1237 let AddedComplexity = 20 in {
1238 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1239 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1240 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1242 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1243 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1244 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1245 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1246 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1249 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1250 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1251 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1252 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1255 //===----------------------------------------------------------------------===//
1256 // SSE 1 & 2 - Conversion Instructions
1257 //===----------------------------------------------------------------------===//
1259 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1260 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1262 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1263 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
1264 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1265 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
1268 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1269 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1270 string asm, Domain d> {
1271 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1272 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
1273 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1274 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
1277 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1278 X86MemOperand x86memop, string asm> {
1279 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1280 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1281 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1282 (ins DstRC:$src1, x86memop:$src),
1283 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1286 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1287 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
1288 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1289 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1291 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1292 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
1293 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1294 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
1297 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1298 // register, but the same isn't true when only using memory operands,
1299 // provide other assembly "l" and "q" forms to address this explicitly
1300 // where appropriate to do so.
1301 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
1303 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
1305 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
1307 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
1309 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
1312 let Predicates = [HasAVX] in {
1313 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1314 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1315 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1316 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1317 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1318 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1319 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1320 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1322 def : Pat<(f32 (sint_to_fp GR32:$src)),
1323 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1324 def : Pat<(f32 (sint_to_fp GR64:$src)),
1325 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1326 def : Pat<(f64 (sint_to_fp GR32:$src)),
1327 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1328 def : Pat<(f64 (sint_to_fp GR64:$src)),
1329 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1332 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1333 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
1334 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1335 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1336 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1337 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
1338 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1339 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1340 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1341 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
1342 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1343 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1344 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1345 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
1346 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1347 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1349 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1350 // and/or XMM operand(s).
1352 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1353 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1355 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1356 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1357 [(set DstRC:$dst, (Int SrcRC:$src))]>;
1358 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1359 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1360 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
1363 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1364 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1365 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
1366 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1368 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1369 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1370 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
1371 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1372 (ins DstRC:$src1, x86memop:$src2),
1374 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1375 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1376 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
1379 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1380 f128mem, load, "cvtsd2si">, XD, VEX;
1381 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1382 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
1385 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
1386 // Get rid of this hack or rename the intrinsics, there are several
1387 // intructions that only match with the intrinsic form, why create duplicates
1388 // to let them be recognized by the assembler?
1389 let Pattern = []<dag> in {
1390 defm VCVTSD2SI : sse12_cvt_s<0x2D, FR64, GR32, undef, f64mem, load,
1391 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
1392 defm VCVTSD2SI64 : sse12_cvt_s<0x2D, FR64, GR64, undef, f64mem, load,
1393 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
1395 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1396 f128mem, load, "cvtsd2si{l}">, XD;
1397 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1398 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
1401 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1402 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
1403 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1404 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
1406 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1407 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
1408 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1409 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
1412 let Constraints = "$src1 = $dst" in {
1413 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1414 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1416 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1417 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1418 "cvtsi2ss{q}">, XS, REX_W;
1419 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1420 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1422 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1423 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1424 "cvtsi2sd">, XD, REX_W;
1429 // Aliases for intrinsics
1430 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1431 f32mem, load, "cvttss2si">, XS, VEX;
1432 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1433 int_x86_sse_cvttss2si64, f32mem, load,
1434 "cvttss2si">, XS, VEX, VEX_W;
1435 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1436 f128mem, load, "cvttsd2si">, XD, VEX;
1437 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1438 int_x86_sse2_cvttsd2si64, f128mem, load,
1439 "cvttsd2si">, XD, VEX, VEX_W;
1440 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1441 f32mem, load, "cvttss2si">, XS;
1442 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1443 int_x86_sse_cvttss2si64, f32mem, load,
1444 "cvttss2si{q}">, XS, REX_W;
1445 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1446 f128mem, load, "cvttsd2si">, XD;
1447 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1448 int_x86_sse2_cvttsd2si64, f128mem, load,
1449 "cvttsd2si{q}">, XD, REX_W;
1451 let Pattern = []<dag> in {
1452 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1453 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
1454 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1455 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1457 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1458 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1459 SSEPackedSingle>, TB, VEX;
1460 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1461 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1462 SSEPackedSingle>, TB, VEX;
1465 let Pattern = []<dag> in {
1466 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1467 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
1468 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1469 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1470 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1471 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1472 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
1475 let Predicates = [HasSSE1] in {
1476 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1477 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1478 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1479 (CVTSS2SIrm addr:$src)>;
1480 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1481 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1482 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1483 (CVTSS2SI64rm addr:$src)>;
1486 let Predicates = [HasAVX] in {
1487 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1488 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1489 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1490 (VCVTSS2SIrm addr:$src)>;
1491 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1492 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1493 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1494 (VCVTSS2SI64rm addr:$src)>;
1499 // Convert scalar double to scalar single
1500 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1501 (ins FR64:$src1, FR64:$src2),
1502 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1504 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1505 (ins FR64:$src1, f64mem:$src2),
1506 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1507 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
1509 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1512 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1513 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1514 [(set FR32:$dst, (fround FR64:$src))]>;
1515 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1516 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1517 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1518 Requires<[HasSSE2, OptForSize]>;
1520 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1521 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1523 let Constraints = "$src1 = $dst" in
1524 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1525 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1527 // Convert scalar single to scalar double
1528 // SSE2 instructions with XS prefix
1529 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1530 (ins FR32:$src1, FR32:$src2),
1531 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1532 []>, XS, Requires<[HasAVX]>, VEX_4V;
1533 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1534 (ins FR32:$src1, f32mem:$src2),
1535 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1536 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
1538 let Predicates = [HasAVX] in {
1539 def : Pat<(f64 (fextend FR32:$src)),
1540 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1541 def : Pat<(fextend (loadf32 addr:$src)),
1542 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1543 def : Pat<(extloadf32 addr:$src),
1544 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1547 def : Pat<(extloadf32 addr:$src),
1548 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1549 Requires<[HasAVX, OptForSpeed]>;
1551 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1552 "cvtss2sd\t{$src, $dst|$dst, $src}",
1553 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1554 Requires<[HasSSE2]>;
1555 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1556 "cvtss2sd\t{$src, $dst|$dst, $src}",
1557 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1558 Requires<[HasSSE2, OptForSize]>;
1560 // extload f32 -> f64. This matches load+fextend because we have a hack in
1561 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1563 // Since these loads aren't folded into the fextend, we have to match it
1565 def : Pat<(fextend (loadf32 addr:$src)),
1566 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1567 def : Pat<(extloadf32 addr:$src),
1568 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1570 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1571 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1572 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1573 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1574 VR128:$src2))]>, XS, VEX_4V,
1576 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1577 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1578 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1579 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1580 (load addr:$src2)))]>, XS, VEX_4V,
1582 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1583 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1584 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1585 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1586 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1587 VR128:$src2))]>, XS,
1588 Requires<[HasSSE2]>;
1589 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1590 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1591 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1592 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1593 (load addr:$src2)))]>, XS,
1594 Requires<[HasSSE2]>;
1597 // Convert doubleword to packed single/double fp
1598 // SSE2 instructions without OpSize prefix
1599 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1600 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1601 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1602 TB, VEX, Requires<[HasAVX]>;
1603 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1604 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1605 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1606 (bitconvert (memopv2i64 addr:$src))))]>,
1607 TB, VEX, Requires<[HasAVX]>;
1608 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1609 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1610 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1611 TB, Requires<[HasSSE2]>;
1612 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1613 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1614 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1615 (bitconvert (memopv2i64 addr:$src))))]>,
1616 TB, Requires<[HasSSE2]>;
1618 // FIXME: why the non-intrinsic version is described as SSE3?
1619 // SSE2 instructions with XS prefix
1620 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1621 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1622 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1623 XS, VEX, Requires<[HasAVX]>;
1624 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1625 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1626 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1627 (bitconvert (memopv2i64 addr:$src))))]>,
1628 XS, VEX, Requires<[HasAVX]>;
1629 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1630 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1631 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1632 XS, Requires<[HasSSE2]>;
1633 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1634 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1635 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1636 (bitconvert (memopv2i64 addr:$src))))]>,
1637 XS, Requires<[HasSSE2]>;
1640 // Convert packed single/double fp to doubleword
1641 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1642 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1643 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1644 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1645 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1646 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1647 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1648 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1649 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1650 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1651 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1652 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1654 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1655 "cvtps2dq\t{$src, $dst|$dst, $src}",
1656 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1658 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1660 "cvtps2dq\t{$src, $dst|$dst, $src}",
1661 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1662 (memop addr:$src)))]>, VEX;
1663 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1664 "cvtps2dq\t{$src, $dst|$dst, $src}",
1665 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1666 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1667 "cvtps2dq\t{$src, $dst|$dst, $src}",
1668 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1669 (memop addr:$src)))]>;
1671 // SSE2 packed instructions with XD prefix
1672 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1673 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1674 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1675 XD, VEX, Requires<[HasAVX]>;
1676 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1677 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1678 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1679 (memop addr:$src)))]>,
1680 XD, VEX, Requires<[HasAVX]>;
1681 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1682 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1683 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1684 XD, Requires<[HasSSE2]>;
1685 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1686 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1687 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1688 (memop addr:$src)))]>,
1689 XD, Requires<[HasSSE2]>;
1692 // Convert with truncation packed single/double fp to doubleword
1693 // SSE2 packed instructions with XS prefix
1694 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1695 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1696 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1697 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1698 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1699 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1700 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1701 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1702 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1703 "cvttps2dq\t{$src, $dst|$dst, $src}",
1705 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1706 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1707 "cvttps2dq\t{$src, $dst|$dst, $src}",
1709 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1711 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1712 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1714 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1715 XS, VEX, Requires<[HasAVX]>;
1716 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1717 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1718 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1719 (memop addr:$src)))]>,
1720 XS, VEX, Requires<[HasAVX]>;
1722 let Predicates = [HasSSE2] in {
1723 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1724 (Int_CVTDQ2PSrr VR128:$src)>;
1725 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1726 (CVTTPS2DQrr VR128:$src)>;
1729 let Predicates = [HasAVX] in {
1730 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1731 (Int_VCVTDQ2PSrr VR128:$src)>;
1732 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1733 (VCVTTPS2DQrr VR128:$src)>;
1734 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1735 (VCVTDQ2PSYrr VR256:$src)>;
1736 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1737 (VCVTTPS2DQYrr VR256:$src)>;
1740 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
1742 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1743 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
1745 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
1747 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1748 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1749 (memop addr:$src)))]>, VEX;
1750 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1751 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1752 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1753 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1754 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1755 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1756 (memop addr:$src)))]>;
1758 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1759 // register, but the same isn't true when using memory operands instead.
1760 // Provide other assembly rr and rm forms to address this explicitly.
1761 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1762 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1763 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1764 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1767 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1768 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1769 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1770 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1773 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1774 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1775 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1776 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1778 // Convert packed single to packed double
1779 let Predicates = [HasAVX] in {
1780 // SSE2 instructions without OpSize prefix
1781 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1782 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1783 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1784 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1785 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1786 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1787 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1788 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1790 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1791 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1792 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1793 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1795 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1796 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1797 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1798 TB, VEX, Requires<[HasAVX]>;
1799 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1800 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1801 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1802 (load addr:$src)))]>,
1803 TB, VEX, Requires<[HasAVX]>;
1804 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1805 "cvtps2pd\t{$src, $dst|$dst, $src}",
1806 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1807 TB, Requires<[HasSSE2]>;
1808 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1809 "cvtps2pd\t{$src, $dst|$dst, $src}",
1810 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1811 (load addr:$src)))]>,
1812 TB, Requires<[HasSSE2]>;
1814 // Convert packed double to packed single
1815 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1816 // register, but the same isn't true when using memory operands instead.
1817 // Provide other assembly rr and rm forms to address this explicitly.
1818 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1819 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1820 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1821 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1824 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1825 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1826 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1827 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1830 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1831 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1832 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1833 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1834 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1835 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1836 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1837 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1840 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1841 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1842 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1843 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1845 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1846 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1847 (memop addr:$src)))]>;
1848 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1849 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1850 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1851 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1852 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1853 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1854 (memop addr:$src)))]>;
1856 // AVX 256-bit register conversion intrinsics
1857 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1858 // whenever possible to avoid declaring two versions of each one.
1859 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1860 (VCVTDQ2PSYrr VR256:$src)>;
1861 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1862 (VCVTDQ2PSYrm addr:$src)>;
1864 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1865 (VCVTPD2PSYrr VR256:$src)>;
1866 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1867 (VCVTPD2PSYrm addr:$src)>;
1869 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1870 (VCVTPS2DQYrr VR256:$src)>;
1871 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1872 (VCVTPS2DQYrm addr:$src)>;
1874 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1875 (VCVTPS2PDYrr VR128:$src)>;
1876 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1877 (VCVTPS2PDYrm addr:$src)>;
1879 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1880 (VCVTTPD2DQYrr VR256:$src)>;
1881 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1882 (VCVTTPD2DQYrm addr:$src)>;
1884 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1885 (VCVTTPS2DQYrr VR256:$src)>;
1886 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1887 (VCVTTPS2DQYrm addr:$src)>;
1889 // Match fround and fextend for 128/256-bit conversions
1890 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1891 (VCVTPD2PSYrr VR256:$src)>;
1892 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1893 (VCVTPD2PSYrm addr:$src)>;
1895 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1896 (VCVTPS2PDYrr VR128:$src)>;
1897 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1898 (VCVTPS2PDYrm addr:$src)>;
1900 //===----------------------------------------------------------------------===//
1901 // SSE 1 & 2 - Compare Instructions
1902 //===----------------------------------------------------------------------===//
1904 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1905 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1906 string asm, string asm_alt> {
1907 let isAsmParserOnly = 1 in {
1908 def rr : SIi8<0xC2, MRMSrcReg,
1909 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1912 def rm : SIi8<0xC2, MRMSrcMem,
1913 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1917 // Accept explicit immediate argument form instead of comparison code.
1918 def rr_alt : SIi8<0xC2, MRMSrcReg,
1919 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1922 def rm_alt : SIi8<0xC2, MRMSrcMem,
1923 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1927 let neverHasSideEffects = 1 in {
1928 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1929 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1930 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1932 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1933 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1934 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1938 let Constraints = "$src1 = $dst" in {
1939 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
1940 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
1941 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1942 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
1943 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
1944 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
1945 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1946 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
1947 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
1948 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
1949 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1950 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
1951 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
1952 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
1953 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1954 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
1956 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1957 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
1958 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
1959 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1960 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
1961 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
1962 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1963 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
1964 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1965 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1966 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
1967 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1968 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1971 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1972 Intrinsic Int, string asm> {
1973 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1974 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1975 [(set VR128:$dst, (Int VR128:$src1,
1976 VR128:$src, imm:$cc))]>;
1977 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1978 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1979 [(set VR128:$dst, (Int VR128:$src1,
1980 (load addr:$src), imm:$cc))]>;
1983 // Aliases to match intrinsics which expect XMM operand(s).
1984 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1985 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1987 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1988 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1990 let Constraints = "$src1 = $dst" in {
1991 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1992 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1993 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1994 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1998 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1999 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2000 ValueType vt, X86MemOperand x86memop,
2001 PatFrag ld_frag, string OpcodeStr, Domain d> {
2002 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2003 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2004 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
2005 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2006 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2007 [(set EFLAGS, (OpNode (vt RC:$src1),
2008 (ld_frag addr:$src2)))], d>;
2011 let Defs = [EFLAGS] in {
2012 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2013 "ucomiss", SSEPackedSingle>, TB, VEX;
2014 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2015 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2016 let Pattern = []<dag> in {
2017 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2018 "comiss", SSEPackedSingle>, TB, VEX;
2019 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2020 "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2023 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2024 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2025 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2026 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2028 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2029 load, "comiss", SSEPackedSingle>, TB, VEX;
2030 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2031 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2032 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2033 "ucomiss", SSEPackedSingle>, TB;
2034 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2035 "ucomisd", SSEPackedDouble>, TB, OpSize;
2037 let Pattern = []<dag> in {
2038 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2039 "comiss", SSEPackedSingle>, TB;
2040 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2041 "comisd", SSEPackedDouble>, TB, OpSize;
2044 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2045 load, "ucomiss", SSEPackedSingle>, TB;
2046 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2047 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2049 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2050 "comiss", SSEPackedSingle>, TB;
2051 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2052 "comisd", SSEPackedDouble>, TB, OpSize;
2053 } // Defs = [EFLAGS]
2055 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
2056 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2057 Intrinsic Int, string asm, string asm_alt,
2059 let isAsmParserOnly = 1 in {
2060 def rri : PIi8<0xC2, MRMSrcReg,
2061 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
2062 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
2063 def rmi : PIi8<0xC2, MRMSrcMem,
2064 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
2065 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
2068 // Accept explicit immediate argument form instead of comparison code.
2069 def rri_alt : PIi8<0xC2, MRMSrcReg,
2070 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
2072 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2073 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
2077 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2078 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
2079 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
2080 SSEPackedSingle>, TB, VEX_4V;
2081 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2082 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
2083 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
2084 SSEPackedDouble>, TB, OpSize, VEX_4V;
2085 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
2086 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
2087 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
2088 SSEPackedSingle>, TB, VEX_4V;
2089 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
2090 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
2091 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
2092 SSEPackedDouble>, TB, OpSize, VEX_4V;
2093 let Constraints = "$src1 = $dst" in {
2094 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2095 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
2096 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
2097 SSEPackedSingle>, TB;
2098 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2099 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
2100 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
2101 SSEPackedDouble>, TB, OpSize;
2104 let Predicates = [HasSSE1] in {
2105 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2106 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2107 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2108 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2111 let Predicates = [HasSSE2] in {
2112 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2113 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2114 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2115 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2118 let Predicates = [HasAVX] in {
2119 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2120 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2121 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2122 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2123 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2124 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2125 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2126 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2128 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2129 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2130 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2131 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2132 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2133 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2134 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2135 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2138 //===----------------------------------------------------------------------===//
2139 // SSE 1 & 2 - Shuffle Instructions
2140 //===----------------------------------------------------------------------===//
2142 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2143 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2144 ValueType vt, string asm, PatFrag mem_frag,
2145 Domain d, bit IsConvertibleToThreeAddress = 0> {
2146 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2147 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
2148 [(set RC:$dst, (vt (shufp:$src3
2149 RC:$src1, (mem_frag addr:$src2))))], d>;
2150 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2151 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2152 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2154 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
2157 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2158 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2159 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2160 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2161 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2162 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2163 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2164 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2165 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2166 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2167 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2168 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2170 let Constraints = "$src1 = $dst" in {
2171 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2172 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2173 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2175 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2176 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2177 memopv2f64, SSEPackedDouble>, TB, OpSize;
2180 let Predicates = [HasSSE1] in {
2181 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2182 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2183 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2184 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2185 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2186 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2187 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2188 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2189 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2190 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2191 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2192 // fall back to this for SSE1)
2193 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2194 (SHUFPSrri VR128:$src2, VR128:$src1,
2195 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2196 // Special unary SHUFPSrri case.
2197 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2198 (SHUFPSrri VR128:$src1, VR128:$src1,
2199 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2202 let Predicates = [HasSSE2] in {
2203 // Special binary v4i32 shuffle cases with SHUFPS.
2204 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2205 (SHUFPSrri VR128:$src1, VR128:$src2,
2206 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2207 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2208 (bc_v4i32 (memopv2i64 addr:$src2)))),
2209 (SHUFPSrmi VR128:$src1, addr:$src2,
2210 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2211 // Special unary SHUFPDrri cases.
2212 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2213 (SHUFPDrri VR128:$src1, VR128:$src1,
2214 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2215 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2216 (SHUFPDrri VR128:$src1, VR128:$src1,
2217 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2218 // Special binary v2i64 shuffle cases using SHUFPDrri.
2219 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2220 (SHUFPDrri VR128:$src1, VR128:$src2,
2221 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2222 // Generic SHUFPD patterns
2223 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2224 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2225 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2226 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2227 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2228 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2229 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2232 let Predicates = [HasAVX] in {
2233 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2234 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2235 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2236 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2237 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2238 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2239 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2240 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2241 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2242 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2243 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2244 // fall back to this for SSE1)
2245 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2246 (VSHUFPSrri VR128:$src2, VR128:$src1,
2247 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2248 // Special unary SHUFPSrri case.
2249 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2250 (VSHUFPSrri VR128:$src1, VR128:$src1,
2251 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2252 // Special binary v4i32 shuffle cases with SHUFPS.
2253 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2254 (VSHUFPSrri VR128:$src1, VR128:$src2,
2255 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2256 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2257 (bc_v4i32 (memopv2i64 addr:$src2)))),
2258 (VSHUFPSrmi VR128:$src1, addr:$src2,
2259 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2260 // Special unary SHUFPDrri cases.
2261 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2262 (VSHUFPDrri VR128:$src1, VR128:$src1,
2263 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2264 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2265 (VSHUFPDrri VR128:$src1, VR128:$src1,
2266 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2267 // Special binary v2i64 shuffle cases using SHUFPDrri.
2268 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2269 (VSHUFPDrri VR128:$src1, VR128:$src2,
2270 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2272 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2273 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2274 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2275 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2276 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2277 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2278 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2281 def : Pat<(v8i32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2282 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2283 def : Pat<(v8i32 (X86Shufps VR256:$src1,
2284 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2285 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2287 def : Pat<(v8f32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2288 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2289 def : Pat<(v8f32 (X86Shufps VR256:$src1,
2290 (memopv8f32 addr:$src2), (i8 imm:$imm))),
2291 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2293 def : Pat<(v4i64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2294 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2295 def : Pat<(v4i64 (X86Shufpd VR256:$src1,
2296 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2297 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2299 def : Pat<(v4f64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2300 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2301 def : Pat<(v4f64 (X86Shufpd VR256:$src1,
2302 (memopv4f64 addr:$src2), (i8 imm:$imm))),
2303 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2306 //===----------------------------------------------------------------------===//
2307 // SSE 1 & 2 - Unpack Instructions
2308 //===----------------------------------------------------------------------===//
2310 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2311 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
2312 PatFrag mem_frag, RegisterClass RC,
2313 X86MemOperand x86memop, string asm,
2315 def rr : PI<opc, MRMSrcReg,
2316 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2318 (vt (OpNode RC:$src1, RC:$src2)))], d>;
2319 def rm : PI<opc, MRMSrcMem,
2320 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2322 (vt (OpNode RC:$src1,
2323 (mem_frag addr:$src2))))], d>;
2326 let AddedComplexity = 10 in {
2327 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2328 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2329 SSEPackedSingle>, TB, VEX_4V;
2330 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2331 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2332 SSEPackedDouble>, TB, OpSize, VEX_4V;
2333 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2334 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2335 SSEPackedSingle>, TB, VEX_4V;
2336 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2337 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2338 SSEPackedDouble>, TB, OpSize, VEX_4V;
2340 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
2341 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2342 SSEPackedSingle>, TB, VEX_4V;
2343 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
2344 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2345 SSEPackedDouble>, TB, OpSize, VEX_4V;
2346 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
2347 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2348 SSEPackedSingle>, TB, VEX_4V;
2349 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
2350 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2351 SSEPackedDouble>, TB, OpSize, VEX_4V;
2353 let Constraints = "$src1 = $dst" in {
2354 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2355 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2356 SSEPackedSingle>, TB;
2357 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2358 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2359 SSEPackedDouble>, TB, OpSize;
2360 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2361 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2362 SSEPackedSingle>, TB;
2363 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2364 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2365 SSEPackedDouble>, TB, OpSize;
2366 } // Constraints = "$src1 = $dst"
2367 } // AddedComplexity
2369 let Predicates = [HasSSE1] in {
2370 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2371 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
2372 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2373 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
2374 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2375 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
2376 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2377 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
2380 let Predicates = [HasSSE2] in {
2381 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2382 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
2383 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2384 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
2385 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2386 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
2387 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2388 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
2390 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2391 // problem is during lowering, where it's not possible to recognize the load
2392 // fold cause it has two uses through a bitcast. One use disappears at isel
2393 // time and the fold opportunity reappears.
2394 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2395 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2397 let AddedComplexity = 10 in
2398 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2399 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2402 let Predicates = [HasAVX] in {
2403 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2404 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
2405 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2406 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
2407 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2408 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
2409 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2410 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
2412 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
2413 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2414 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2415 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2416 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2417 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2418 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
2419 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2420 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
2421 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2422 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2423 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2424 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
2425 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2426 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2427 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2429 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2430 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
2431 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2432 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
2433 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2434 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
2435 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2436 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
2438 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
2439 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2440 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2441 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2442 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
2443 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2444 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2445 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2446 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
2447 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2448 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2449 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2450 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
2451 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2452 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2453 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2455 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2456 // problem is during lowering, where it's not possible to recognize the load
2457 // fold cause it has two uses through a bitcast. One use disappears at isel
2458 // time and the fold opportunity reappears.
2459 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2460 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2461 let AddedComplexity = 10 in
2462 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2463 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2466 //===----------------------------------------------------------------------===//
2467 // SSE 1 & 2 - Extract Floating-Point Sign mask
2468 //===----------------------------------------------------------------------===//
2470 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2471 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2473 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2474 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2475 [(set GR32:$dst, (Int RC:$src))], d>;
2476 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2477 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
2480 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2481 SSEPackedSingle>, TB;
2482 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2483 SSEPackedDouble>, TB, OpSize;
2485 def : Pat<(i32 (X86fgetsign FR32:$src)),
2486 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2487 sub_ss))>, Requires<[HasSSE1]>;
2488 def : Pat<(i64 (X86fgetsign FR32:$src)),
2489 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2490 sub_ss))>, Requires<[HasSSE1]>;
2491 def : Pat<(i32 (X86fgetsign FR64:$src)),
2492 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2493 sub_sd))>, Requires<[HasSSE2]>;
2494 def : Pat<(i64 (X86fgetsign FR64:$src)),
2495 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2496 sub_sd))>, Requires<[HasSSE2]>;
2498 let Predicates = [HasAVX] in {
2499 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2500 "movmskps", SSEPackedSingle>, TB, VEX;
2501 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2502 "movmskpd", SSEPackedDouble>, TB,
2504 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2505 "movmskps", SSEPackedSingle>, TB, VEX;
2506 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2507 "movmskpd", SSEPackedDouble>, TB,
2510 def : Pat<(i32 (X86fgetsign FR32:$src)),
2511 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2513 def : Pat<(i64 (X86fgetsign FR32:$src)),
2514 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2516 def : Pat<(i32 (X86fgetsign FR64:$src)),
2517 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2519 def : Pat<(i64 (X86fgetsign FR64:$src)),
2520 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2524 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2525 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2526 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2527 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2529 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2530 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2531 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2532 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2536 //===----------------------------------------------------------------------===//
2537 // SSE 1 & 2 - Logical Instructions
2538 //===----------------------------------------------------------------------===//
2540 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2542 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2544 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2545 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2547 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2548 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2550 let Constraints = "$src1 = $dst" in {
2551 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2552 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2554 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2555 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2559 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2560 let mayLoad = 0 in {
2561 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2562 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2563 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2566 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2567 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2569 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2571 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2573 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2574 // are all promoted to v2i64, and the patterns are covered by the int
2575 // version. This is needed in SSE only, because v2i64 isn't supported on
2576 // SSE1, but only on SSE2.
2577 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2578 !strconcat(OpcodeStr, "ps"), f128mem, [],
2579 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2580 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2582 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2583 !strconcat(OpcodeStr, "pd"), f128mem,
2584 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2585 (bc_v2i64 (v2f64 VR128:$src2))))],
2586 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2587 (memopv2i64 addr:$src2)))], 0>,
2589 let Constraints = "$src1 = $dst" in {
2590 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2591 !strconcat(OpcodeStr, "ps"), f128mem,
2592 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2593 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2594 (memopv2i64 addr:$src2)))]>, TB;
2596 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2597 !strconcat(OpcodeStr, "pd"), f128mem,
2598 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2599 (bc_v2i64 (v2f64 VR128:$src2))))],
2600 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2601 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2605 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2607 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2609 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2610 !strconcat(OpcodeStr, "ps"), f256mem,
2611 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2612 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2613 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2615 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2616 !strconcat(OpcodeStr, "pd"), f256mem,
2617 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2618 (bc_v4i64 (v4f64 VR256:$src2))))],
2619 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2620 (memopv4i64 addr:$src2)))], 0>,
2624 // AVX 256-bit packed logical ops forms
2625 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2626 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2627 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2628 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2630 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2631 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2632 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2633 let isCommutable = 0 in
2634 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2636 //===----------------------------------------------------------------------===//
2637 // SSE 1 & 2 - Arithmetic Instructions
2638 //===----------------------------------------------------------------------===//
2640 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2643 /// In addition, we also have a special variant of the scalar form here to
2644 /// represent the associated intrinsic operation. This form is unlike the
2645 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2646 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2648 /// These three forms can each be reg+reg or reg+mem.
2651 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2653 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2655 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2656 OpNode, FR32, f32mem, Is2Addr>, XS;
2657 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2658 OpNode, FR64, f64mem, Is2Addr>, XD;
2661 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2663 let mayLoad = 0 in {
2664 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2665 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2666 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2667 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2671 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2673 let mayLoad = 0 in {
2674 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2675 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2676 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2677 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2681 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2683 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2684 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2685 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2686 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2689 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2691 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2692 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2693 SSEPackedSingle, Is2Addr>, TB;
2695 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2696 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2697 SSEPackedDouble, Is2Addr>, TB, OpSize;
2700 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2701 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2702 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2703 SSEPackedSingle, 0>, TB;
2705 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2706 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2707 SSEPackedDouble, 0>, TB, OpSize;
2710 // Binary Arithmetic instructions
2711 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2712 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
2713 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2714 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2715 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2716 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
2717 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2718 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2720 let isCommutable = 0 in {
2721 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2722 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
2723 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2724 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2725 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2726 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
2727 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2728 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2729 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2730 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
2731 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2732 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2733 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2734 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2735 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2736 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
2737 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2738 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2739 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2740 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2743 let Constraints = "$src1 = $dst" in {
2744 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2745 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2746 basic_sse12_fp_binop_s_int<0x58, "add">;
2747 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2748 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2749 basic_sse12_fp_binop_s_int<0x59, "mul">;
2751 let isCommutable = 0 in {
2752 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2753 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2754 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2755 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2756 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2757 basic_sse12_fp_binop_s_int<0x5E, "div">;
2758 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2759 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2760 basic_sse12_fp_binop_s_int<0x5F, "max">,
2761 basic_sse12_fp_binop_p_int<0x5F, "max">;
2762 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2763 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2764 basic_sse12_fp_binop_s_int<0x5D, "min">,
2765 basic_sse12_fp_binop_p_int<0x5D, "min">;
2770 /// In addition, we also have a special variant of the scalar form here to
2771 /// represent the associated intrinsic operation. This form is unlike the
2772 /// plain scalar form, in that it takes an entire vector (instead of a
2773 /// scalar) and leaves the top elements undefined.
2775 /// And, we have a special variant form for a full-vector intrinsic form.
2777 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2778 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2779 SDNode OpNode, Intrinsic F32Int> {
2780 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2781 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2782 [(set FR32:$dst, (OpNode FR32:$src))]>;
2783 // For scalar unary operations, fold a load into the operation
2784 // only in OptForSize mode. It eliminates an instruction, but it also
2785 // eliminates a whole-register clobber (the load), so it introduces a
2786 // partial register update condition.
2787 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2788 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2789 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2790 Requires<[HasSSE1, OptForSize]>;
2791 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2792 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2793 [(set VR128:$dst, (F32Int VR128:$src))]>;
2794 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2795 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2796 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2799 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2800 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2801 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2802 !strconcat(OpcodeStr,
2803 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2804 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2805 !strconcat(OpcodeStr,
2806 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2807 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2808 (ins ssmem:$src1, VR128:$src2),
2809 !strconcat(OpcodeStr,
2810 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2813 /// sse1_fp_unop_p - SSE1 unops in packed form.
2814 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2815 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2816 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2817 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2818 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2819 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2820 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2823 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2824 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2825 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2826 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2827 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2828 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2829 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2830 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2833 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2834 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2835 Intrinsic V4F32Int> {
2836 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2837 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2838 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2839 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2840 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2841 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2844 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2845 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2846 Intrinsic V4F32Int> {
2847 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2848 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2849 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2850 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2851 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2852 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2855 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2856 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2857 SDNode OpNode, Intrinsic F64Int> {
2858 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2859 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2860 [(set FR64:$dst, (OpNode FR64:$src))]>;
2861 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2862 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2863 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2864 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2865 Requires<[HasSSE2, OptForSize]>;
2866 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2867 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2868 [(set VR128:$dst, (F64Int VR128:$src))]>;
2869 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2870 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2871 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2874 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2875 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2876 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2877 !strconcat(OpcodeStr,
2878 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2879 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2880 !strconcat(OpcodeStr,
2881 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2882 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2883 (ins VR128:$src1, sdmem:$src2),
2884 !strconcat(OpcodeStr,
2885 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2888 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2889 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2891 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2892 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2893 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2894 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2895 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2896 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2899 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2900 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2901 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2902 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2903 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2904 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2905 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2906 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2909 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2910 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2911 Intrinsic V2F64Int> {
2912 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2913 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2914 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2915 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2916 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2917 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2920 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2921 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2922 Intrinsic V2F64Int> {
2923 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2924 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2925 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2926 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2927 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2928 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2931 let Predicates = [HasAVX] in {
2933 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
2934 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V;
2936 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
2937 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
2938 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2939 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2940 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
2941 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
2942 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
2943 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
2946 // Reciprocal approximations. Note that these typically require refinement
2947 // in order to obtain suitable precision.
2948 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V;
2949 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
2950 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
2951 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
2952 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
2954 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V;
2955 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
2956 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
2957 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
2958 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
2961 def : Pat<(f32 (fsqrt FR32:$src)),
2962 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2963 def : Pat<(f32 (fsqrt (load addr:$src))),
2964 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2965 Requires<[HasAVX, OptForSize]>;
2966 def : Pat<(f64 (fsqrt FR64:$src)),
2967 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
2968 def : Pat<(f64 (fsqrt (load addr:$src))),
2969 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
2970 Requires<[HasAVX, OptForSize]>;
2972 def : Pat<(f32 (X86frsqrt FR32:$src)),
2973 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2974 def : Pat<(f32 (X86frsqrt (load addr:$src))),
2975 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2976 Requires<[HasAVX, OptForSize]>;
2978 def : Pat<(f32 (X86frcp FR32:$src)),
2979 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2980 def : Pat<(f32 (X86frcp (load addr:$src))),
2981 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
2982 Requires<[HasAVX, OptForSize]>;
2984 let Predicates = [HasAVX] in {
2985 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
2986 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
2987 (VSQRTSSr (f32 (IMPLICIT_DEF)),
2988 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
2990 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
2991 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
2993 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
2994 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
2995 (VSQRTSDr (f64 (IMPLICIT_DEF)),
2996 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
2998 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
2999 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3001 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3002 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3003 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3004 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3006 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3007 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3009 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3010 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3011 (VRCPSSr (f32 (IMPLICIT_DEF)),
3012 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3014 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3015 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3019 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
3020 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
3021 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
3022 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
3023 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
3024 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
3026 // Reciprocal approximations. Note that these typically require refinement
3027 // in order to obtain suitable precision.
3028 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
3029 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
3030 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
3031 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
3032 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
3033 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
3035 // There is no f64 version of the reciprocal approximation instructions.
3037 //===----------------------------------------------------------------------===//
3038 // SSE 1 & 2 - Non-temporal stores
3039 //===----------------------------------------------------------------------===//
3041 let AddedComplexity = 400 in { // Prefer non-temporal versions
3042 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3043 (ins f128mem:$dst, VR128:$src),
3044 "movntps\t{$src, $dst|$dst, $src}",
3045 [(alignednontemporalstore (v4f32 VR128:$src),
3047 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3048 (ins f128mem:$dst, VR128:$src),
3049 "movntpd\t{$src, $dst|$dst, $src}",
3050 [(alignednontemporalstore (v2f64 VR128:$src),
3052 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
3053 (ins f128mem:$dst, VR128:$src),
3054 "movntdq\t{$src, $dst|$dst, $src}",
3055 [(alignednontemporalstore (v2f64 VR128:$src),
3058 let ExeDomain = SSEPackedInt in
3059 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3060 (ins f128mem:$dst, VR128:$src),
3061 "movntdq\t{$src, $dst|$dst, $src}",
3062 [(alignednontemporalstore (v4f32 VR128:$src),
3065 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3066 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3068 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3069 (ins f256mem:$dst, VR256:$src),
3070 "movntps\t{$src, $dst|$dst, $src}",
3071 [(alignednontemporalstore (v8f32 VR256:$src),
3073 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3074 (ins f256mem:$dst, VR256:$src),
3075 "movntpd\t{$src, $dst|$dst, $src}",
3076 [(alignednontemporalstore (v4f64 VR256:$src),
3078 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
3079 (ins f256mem:$dst, VR256:$src),
3080 "movntdq\t{$src, $dst|$dst, $src}",
3081 [(alignednontemporalstore (v4f64 VR256:$src),
3083 let ExeDomain = SSEPackedInt in
3084 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3085 (ins f256mem:$dst, VR256:$src),
3086 "movntdq\t{$src, $dst|$dst, $src}",
3087 [(alignednontemporalstore (v8f32 VR256:$src),
3091 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
3092 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3093 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
3094 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
3095 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
3096 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
3098 let AddedComplexity = 400 in { // Prefer non-temporal versions
3099 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3100 "movntps\t{$src, $dst|$dst, $src}",
3101 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3102 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3103 "movntpd\t{$src, $dst|$dst, $src}",
3104 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
3106 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3107 "movntdq\t{$src, $dst|$dst, $src}",
3108 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
3110 let ExeDomain = SSEPackedInt in
3111 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3112 "movntdq\t{$src, $dst|$dst, $src}",
3113 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3115 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3116 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3118 // There is no AVX form for instructions below this point
3119 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3120 "movnti{l}\t{$src, $dst|$dst, $src}",
3121 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
3122 TB, Requires<[HasSSE2]>;
3123 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3124 "movnti{q}\t{$src, $dst|$dst, $src}",
3125 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
3126 TB, Requires<[HasSSE2]>;
3129 //===----------------------------------------------------------------------===//
3130 // SSE 1 & 2 - Prefetch and memory fence
3131 //===----------------------------------------------------------------------===//
3133 // Prefetch intrinsic.
3134 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
3135 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
3136 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
3137 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
3138 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
3139 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
3140 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
3141 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
3144 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3145 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3146 TB, Requires<[HasSSE2]>;
3148 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3149 // was introduced with SSE2, it's backward compatible.
3150 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3152 // Load, store, and memory fence
3153 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3154 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
3155 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3156 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3157 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3158 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3160 def : Pat<(X86SFence), (SFENCE)>;
3161 def : Pat<(X86LFence), (LFENCE)>;
3162 def : Pat<(X86MFence), (MFENCE)>;
3164 //===----------------------------------------------------------------------===//
3165 // SSE 1 & 2 - Load/Store XCSR register
3166 //===----------------------------------------------------------------------===//
3168 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3169 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
3170 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3171 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
3173 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3174 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
3175 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3176 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
3178 //===---------------------------------------------------------------------===//
3179 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3180 //===---------------------------------------------------------------------===//
3182 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3184 let neverHasSideEffects = 1 in {
3185 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3186 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3187 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3188 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3190 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3191 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
3192 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3193 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
3195 let canFoldAsLoad = 1, mayLoad = 1 in {
3196 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3197 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3198 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3199 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3200 let Predicates = [HasAVX] in {
3201 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3202 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3203 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3204 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3208 let mayStore = 1 in {
3209 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3210 (ins i128mem:$dst, VR128:$src),
3211 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3212 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3213 (ins i256mem:$dst, VR256:$src),
3214 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3215 let Predicates = [HasAVX] in {
3216 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3217 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3218 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3219 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3223 let neverHasSideEffects = 1 in
3224 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3225 "movdqa\t{$src, $dst|$dst, $src}", []>;
3227 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3228 "movdqu\t{$src, $dst|$dst, $src}",
3229 []>, XS, Requires<[HasSSE2]>;
3231 let canFoldAsLoad = 1, mayLoad = 1 in {
3232 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3233 "movdqa\t{$src, $dst|$dst, $src}",
3234 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
3235 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3236 "movdqu\t{$src, $dst|$dst, $src}",
3237 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
3238 XS, Requires<[HasSSE2]>;
3241 let mayStore = 1 in {
3242 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3243 "movdqa\t{$src, $dst|$dst, $src}",
3244 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
3245 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3246 "movdqu\t{$src, $dst|$dst, $src}",
3247 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
3248 XS, Requires<[HasSSE2]>;
3251 // Intrinsic forms of MOVDQU load and store
3252 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3253 "vmovdqu\t{$src, $dst|$dst, $src}",
3254 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3255 XS, VEX, Requires<[HasAVX]>;
3257 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3258 "movdqu\t{$src, $dst|$dst, $src}",
3259 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3260 XS, Requires<[HasSSE2]>;
3262 } // ExeDomain = SSEPackedInt
3264 let Predicates = [HasAVX] in {
3265 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
3266 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3267 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3270 //===---------------------------------------------------------------------===//
3271 // SSE2 - Packed Integer Arithmetic Instructions
3272 //===---------------------------------------------------------------------===//
3274 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3276 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3277 bit IsCommutable = 0, bit Is2Addr = 1> {
3278 let isCommutable = IsCommutable in
3279 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3280 (ins VR128:$src1, VR128:$src2),
3282 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3283 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3284 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
3285 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3286 (ins VR128:$src1, i128mem:$src2),
3288 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3289 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3290 [(set VR128:$dst, (IntId VR128:$src1,
3291 (bitconvert (memopv2i64 addr:$src2))))]>;
3294 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
3295 string OpcodeStr, Intrinsic IntId,
3296 Intrinsic IntId2, bit Is2Addr = 1> {
3297 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3298 (ins VR128:$src1, VR128:$src2),
3300 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3301 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3302 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
3303 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3304 (ins VR128:$src1, i128mem:$src2),
3306 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3307 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3308 [(set VR128:$dst, (IntId VR128:$src1,
3309 (bitconvert (memopv2i64 addr:$src2))))]>;
3310 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
3311 (ins VR128:$src1, i32i8imm:$src2),
3313 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3314 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3315 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
3318 /// PDI_binop_rm - Simple SSE2 binary operator.
3319 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3320 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
3321 let isCommutable = IsCommutable in
3322 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3323 (ins VR128:$src1, VR128:$src2),
3325 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3326 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3327 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
3328 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3329 (ins VR128:$src1, i128mem:$src2),
3331 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3332 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3333 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
3334 (bitconvert (memopv2i64 addr:$src2)))))]>;
3337 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
3339 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
3340 /// to collapse (bitconvert VT to VT) into its operand.
3342 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
3343 bit IsCommutable = 0, bit Is2Addr = 1> {
3344 let isCommutable = IsCommutable in
3345 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3346 (ins VR128:$src1, VR128:$src2),
3348 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3349 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3350 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
3351 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3352 (ins VR128:$src1, i128mem:$src2),
3354 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3355 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3356 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
3359 } // ExeDomain = SSEPackedInt
3361 // 128-bit Integer Arithmetic
3363 let Predicates = [HasAVX] in {
3364 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
3365 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
3366 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
3367 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
3368 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
3369 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
3370 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
3371 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
3372 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
3375 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
3377 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
3379 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
3381 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
3383 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
3385 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
3387 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
3389 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
3391 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
3393 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
3395 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
3397 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
3399 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
3401 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
3403 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
3405 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
3407 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
3409 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
3411 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
3415 let Constraints = "$src1 = $dst" in {
3416 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
3417 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
3418 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
3419 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
3420 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
3421 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
3422 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
3423 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
3424 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
3427 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
3428 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
3429 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
3430 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
3431 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
3432 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
3433 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
3434 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
3435 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
3436 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
3437 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
3438 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
3439 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
3440 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
3441 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
3442 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
3443 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
3444 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
3445 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
3447 } // Constraints = "$src1 = $dst"
3449 //===---------------------------------------------------------------------===//
3450 // SSE2 - Packed Integer Logical Instructions
3451 //===---------------------------------------------------------------------===//
3453 let Predicates = [HasAVX] in {
3454 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3455 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
3457 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3458 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
3460 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3461 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
3464 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3465 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
3467 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3468 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
3470 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3471 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
3474 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3475 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
3477 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3478 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
3481 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
3482 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
3483 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
3485 let ExeDomain = SSEPackedInt in {
3486 let neverHasSideEffects = 1 in {
3487 // 128-bit logical shifts.
3488 def VPSLLDQri : PDIi8<0x73, MRM7r,
3489 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3490 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3492 def VPSRLDQri : PDIi8<0x73, MRM3r,
3493 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3494 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3496 // PSRADQri doesn't exist in SSE[1-3].
3498 def VPANDNrr : PDI<0xDF, MRMSrcReg,
3499 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3500 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3502 (v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
3504 def VPANDNrm : PDI<0xDF, MRMSrcMem,
3505 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3506 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3507 [(set VR128:$dst, (X86andnp VR128:$src1,
3508 (memopv2i64 addr:$src2)))]>, VEX_4V;
3512 let Constraints = "$src1 = $dst" in {
3513 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
3514 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
3515 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
3516 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
3517 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
3518 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
3520 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
3521 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
3522 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
3523 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
3524 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
3525 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
3527 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
3528 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
3529 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
3530 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
3532 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
3533 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
3534 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
3536 let ExeDomain = SSEPackedInt in {
3537 let neverHasSideEffects = 1 in {
3538 // 128-bit logical shifts.
3539 def PSLLDQri : PDIi8<0x73, MRM7r,
3540 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3541 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
3542 def PSRLDQri : PDIi8<0x73, MRM3r,
3543 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3544 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
3545 // PSRADQri doesn't exist in SSE[1-3].
3547 def PANDNrr : PDI<0xDF, MRMSrcReg,
3548 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3549 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3551 def PANDNrm : PDI<0xDF, MRMSrcMem,
3552 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3553 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3555 } // Constraints = "$src1 = $dst"
3557 let Predicates = [HasAVX] in {
3558 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3559 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3560 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3561 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3562 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3563 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
3564 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3565 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
3566 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3567 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3569 // Shift up / down and insert zero's.
3570 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3571 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3572 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3573 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3576 let Predicates = [HasSSE2] in {
3577 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3578 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3579 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3580 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3581 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3582 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
3583 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3584 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
3585 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3586 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3588 // Shift up / down and insert zero's.
3589 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3590 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3591 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3592 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3595 //===---------------------------------------------------------------------===//
3596 // SSE2 - Packed Integer Comparison Instructions
3597 //===---------------------------------------------------------------------===//
3599 let Predicates = [HasAVX] in {
3600 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
3602 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
3604 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
3606 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
3608 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
3610 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
3613 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3614 (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
3615 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3616 (VPCMPEQBrm VR128:$src1, addr:$src2)>;
3617 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3618 (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
3619 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3620 (VPCMPEQWrm VR128:$src1, addr:$src2)>;
3621 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3622 (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
3623 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3624 (VPCMPEQDrm VR128:$src1, addr:$src2)>;
3626 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3627 (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
3628 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3629 (VPCMPGTBrm VR128:$src1, addr:$src2)>;
3630 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3631 (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
3632 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3633 (VPCMPGTWrm VR128:$src1, addr:$src2)>;
3634 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3635 (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
3636 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3637 (VPCMPGTDrm VR128:$src1, addr:$src2)>;
3640 let Constraints = "$src1 = $dst" in {
3641 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
3642 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
3643 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
3644 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
3645 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
3646 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
3647 } // Constraints = "$src1 = $dst"
3649 let Predicates = [HasSSE2] in {
3650 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3651 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
3652 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3653 (PCMPEQBrm VR128:$src1, addr:$src2)>;
3654 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3655 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
3656 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3657 (PCMPEQWrm VR128:$src1, addr:$src2)>;
3658 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3659 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
3660 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3661 (PCMPEQDrm VR128:$src1, addr:$src2)>;
3663 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3664 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
3665 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3666 (PCMPGTBrm VR128:$src1, addr:$src2)>;
3667 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3668 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
3669 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3670 (PCMPGTWrm VR128:$src1, addr:$src2)>;
3671 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3672 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
3673 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3674 (PCMPGTDrm VR128:$src1, addr:$src2)>;
3677 //===---------------------------------------------------------------------===//
3678 // SSE2 - Packed Integer Pack Instructions
3679 //===---------------------------------------------------------------------===//
3681 let Predicates = [HasAVX] in {
3682 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
3684 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
3686 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
3690 let Constraints = "$src1 = $dst" in {
3691 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
3692 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
3693 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
3694 } // Constraints = "$src1 = $dst"
3696 //===---------------------------------------------------------------------===//
3697 // SSE2 - Packed Integer Shuffle Instructions
3698 //===---------------------------------------------------------------------===//
3700 let ExeDomain = SSEPackedInt in {
3701 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
3703 def ri : Ii8<0x70, MRMSrcReg,
3704 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3705 !strconcat(OpcodeStr,
3706 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3707 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
3709 def mi : Ii8<0x70, MRMSrcMem,
3710 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
3711 !strconcat(OpcodeStr,
3712 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3713 [(set VR128:$dst, (vt (pshuf_frag:$src2
3714 (bc_frag (memopv2i64 addr:$src1)),
3717 } // ExeDomain = SSEPackedInt
3719 let Predicates = [HasAVX] in {
3720 let AddedComplexity = 5 in
3721 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
3724 // SSE2 with ImmT == Imm8 and XS prefix.
3725 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
3728 // SSE2 with ImmT == Imm8 and XD prefix.
3729 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
3732 let AddedComplexity = 5 in
3733 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3734 (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3735 // Unary v4f32 shuffle with VPSHUF* in order to fold a load.
3736 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3737 (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3739 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3741 (VPSHUFDmi addr:$src1, imm:$imm)>;
3742 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3744 (VPSHUFDmi addr:$src1, imm:$imm)>;
3745 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3746 (VPSHUFDri VR128:$src1, imm:$imm)>;
3747 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3748 (VPSHUFDri VR128:$src1, imm:$imm)>;
3749 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3750 (VPSHUFHWri VR128:$src, imm:$imm)>;
3751 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3753 (VPSHUFHWmi addr:$src, imm:$imm)>;
3754 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3755 (VPSHUFLWri VR128:$src, imm:$imm)>;
3756 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3758 (VPSHUFLWmi addr:$src, imm:$imm)>;
3761 let Predicates = [HasSSE2] in {
3762 let AddedComplexity = 5 in
3763 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
3765 // SSE2 with ImmT == Imm8 and XS prefix.
3766 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
3768 // SSE2 with ImmT == Imm8 and XD prefix.
3769 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
3771 let AddedComplexity = 5 in
3772 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3773 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3774 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3775 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3776 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3778 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3780 (PSHUFDmi addr:$src1, imm:$imm)>;
3781 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3783 (PSHUFDmi addr:$src1, imm:$imm)>;
3784 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3785 (PSHUFDri VR128:$src1, imm:$imm)>;
3786 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3787 (PSHUFDri VR128:$src1, imm:$imm)>;
3788 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3789 (PSHUFHWri VR128:$src, imm:$imm)>;
3790 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3792 (PSHUFHWmi addr:$src, imm:$imm)>;
3793 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3794 (PSHUFLWri VR128:$src, imm:$imm)>;
3795 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3797 (PSHUFLWmi addr:$src, imm:$imm)>;
3800 //===---------------------------------------------------------------------===//
3801 // SSE2 - Packed Integer Unpack Instructions
3802 //===---------------------------------------------------------------------===//
3804 let ExeDomain = SSEPackedInt in {
3805 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
3806 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
3807 def rr : PDI<opc, MRMSrcReg,
3808 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3810 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3811 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3812 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
3813 def rm : PDI<opc, MRMSrcMem,
3814 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3816 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3817 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3818 [(set VR128:$dst, (OpNode VR128:$src1,
3819 (bc_frag (memopv2i64
3823 let Predicates = [HasAVX] in {
3824 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
3825 bc_v16i8, 0>, VEX_4V;
3826 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
3827 bc_v8i16, 0>, VEX_4V;
3828 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
3829 bc_v4i32, 0>, VEX_4V;
3831 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3832 /// knew to collapse (bitconvert VT to VT) into its operand.
3833 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3834 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3835 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3836 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3837 VR128:$src2)))]>, VEX_4V;
3838 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3839 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3840 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3841 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3842 (memopv2i64 addr:$src2))))]>, VEX_4V;
3844 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
3845 bc_v16i8, 0>, VEX_4V;
3846 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
3847 bc_v8i16, 0>, VEX_4V;
3848 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
3849 bc_v4i32, 0>, VEX_4V;
3851 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3852 /// knew to collapse (bitconvert VT to VT) into its operand.
3853 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3854 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3855 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3856 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3857 VR128:$src2)))]>, VEX_4V;
3858 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3859 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3860 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3861 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3862 (memopv2i64 addr:$src2))))]>, VEX_4V;
3865 let Constraints = "$src1 = $dst" in {
3866 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
3867 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
3868 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
3870 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3871 /// knew to collapse (bitconvert VT to VT) into its operand.
3872 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3873 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3874 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3876 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
3877 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3878 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3879 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3881 (v2i64 (X86Punpcklqdq VR128:$src1,
3882 (memopv2i64 addr:$src2))))]>;
3884 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
3885 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
3886 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
3888 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3889 /// knew to collapse (bitconvert VT to VT) into its operand.
3890 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3891 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3892 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3894 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
3895 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3896 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3897 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3899 (v2i64 (X86Punpckhqdq VR128:$src1,
3900 (memopv2i64 addr:$src2))))]>;
3902 } // ExeDomain = SSEPackedInt
3904 // Splat v2f64 / v2i64
3905 let AddedComplexity = 10 in {
3906 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3907 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3908 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3909 (VPUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasAVX]>;
3912 //===---------------------------------------------------------------------===//
3913 // SSE2 - Packed Integer Extract and Insert
3914 //===---------------------------------------------------------------------===//
3916 let ExeDomain = SSEPackedInt in {
3917 multiclass sse2_pinsrw<bit Is2Addr = 1> {
3918 def rri : Ii8<0xC4, MRMSrcReg,
3919 (outs VR128:$dst), (ins VR128:$src1,
3920 GR32:$src2, i32i8imm:$src3),
3922 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3923 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3925 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
3926 def rmi : Ii8<0xC4, MRMSrcMem,
3927 (outs VR128:$dst), (ins VR128:$src1,
3928 i16mem:$src2, i32i8imm:$src3),
3930 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3931 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3933 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
3938 let Predicates = [HasAVX] in
3939 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
3940 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
3941 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3942 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
3943 imm:$src2))]>, TB, OpSize, VEX;
3944 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
3945 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
3946 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3947 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
3951 let Predicates = [HasAVX] in {
3952 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
3953 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
3954 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
3955 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
3956 []>, TB, OpSize, VEX_4V;
3959 let Constraints = "$src1 = $dst" in
3960 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
3962 } // ExeDomain = SSEPackedInt
3964 //===---------------------------------------------------------------------===//
3965 // SSE2 - Packed Mask Creation
3966 //===---------------------------------------------------------------------===//
3968 let ExeDomain = SSEPackedInt in {
3970 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
3971 "pmovmskb\t{$src, $dst|$dst, $src}",
3972 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
3973 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
3974 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
3975 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
3976 "pmovmskb\t{$src, $dst|$dst, $src}",
3977 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
3979 } // ExeDomain = SSEPackedInt
3981 //===---------------------------------------------------------------------===//
3982 // SSE2 - Conditional Store
3983 //===---------------------------------------------------------------------===//
3985 let ExeDomain = SSEPackedInt in {
3988 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
3989 (ins VR128:$src, VR128:$mask),
3990 "maskmovdqu\t{$mask, $src|$src, $mask}",
3991 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
3993 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
3994 (ins VR128:$src, VR128:$mask),
3995 "maskmovdqu\t{$mask, $src|$src, $mask}",
3996 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
3999 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4000 "maskmovdqu\t{$mask, $src|$src, $mask}",
4001 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
4003 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4004 "maskmovdqu\t{$mask, $src|$src, $mask}",
4005 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
4007 } // ExeDomain = SSEPackedInt
4009 //===---------------------------------------------------------------------===//
4010 // SSE2 - Move Doubleword
4011 //===---------------------------------------------------------------------===//
4013 //===---------------------------------------------------------------------===//
4014 // Move Int Doubleword to Packed Double Int
4016 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4017 "movd\t{$src, $dst|$dst, $src}",
4019 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
4020 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4021 "movd\t{$src, $dst|$dst, $src}",
4023 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
4025 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4026 "mov{d|q}\t{$src, $dst|$dst, $src}",
4028 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
4029 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4030 "mov{d|q}\t{$src, $dst|$dst, $src}",
4031 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
4033 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4034 "movd\t{$src, $dst|$dst, $src}",
4036 (v4i32 (scalar_to_vector GR32:$src)))]>;
4037 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4038 "movd\t{$src, $dst|$dst, $src}",
4040 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
4041 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4042 "mov{d|q}\t{$src, $dst|$dst, $src}",
4044 (v2i64 (scalar_to_vector GR64:$src)))]>;
4045 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4046 "mov{d|q}\t{$src, $dst|$dst, $src}",
4047 [(set FR64:$dst, (bitconvert GR64:$src))]>;
4049 //===---------------------------------------------------------------------===//
4050 // Move Int Doubleword to Single Scalar
4052 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4053 "movd\t{$src, $dst|$dst, $src}",
4054 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
4056 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4057 "movd\t{$src, $dst|$dst, $src}",
4058 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4060 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4061 "movd\t{$src, $dst|$dst, $src}",
4062 [(set FR32:$dst, (bitconvert GR32:$src))]>;
4064 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4065 "movd\t{$src, $dst|$dst, $src}",
4066 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
4068 //===---------------------------------------------------------------------===//
4069 // Move Packed Doubleword Int to Packed Double Int
4071 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4072 "movd\t{$src, $dst|$dst, $src}",
4073 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4075 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4076 (ins i32mem:$dst, VR128:$src),
4077 "movd\t{$src, $dst|$dst, $src}",
4078 [(store (i32 (vector_extract (v4i32 VR128:$src),
4079 (iPTR 0))), addr:$dst)]>, VEX;
4080 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4081 "movd\t{$src, $dst|$dst, $src}",
4082 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4084 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4085 "movd\t{$src, $dst|$dst, $src}",
4086 [(store (i32 (vector_extract (v4i32 VR128:$src),
4087 (iPTR 0))), addr:$dst)]>;
4089 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4090 "mov{d|q}\t{$src, $dst|$dst, $src}",
4091 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4093 //===---------------------------------------------------------------------===//
4094 // Bitcast FR64 <-> GR64
4096 let Predicates = [HasAVX] in
4097 def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4098 "vmovq\t{$src, $dst|$dst, $src}",
4099 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4101 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4102 "mov{d|q}\t{$src, $dst|$dst, $src}",
4103 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4104 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4105 "movq\t{$src, $dst|$dst, $src}",
4106 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4108 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4109 "movq\t{$src, $dst|$dst, $src}",
4110 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
4111 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4112 "mov{d|q}\t{$src, $dst|$dst, $src}",
4113 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4114 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4115 "movq\t{$src, $dst|$dst, $src}",
4116 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4118 //===---------------------------------------------------------------------===//
4119 // Move Scalar Single to Double Int
4121 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4122 "movd\t{$src, $dst|$dst, $src}",
4123 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
4124 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4125 "movd\t{$src, $dst|$dst, $src}",
4126 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
4127 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4128 "movd\t{$src, $dst|$dst, $src}",
4129 [(set GR32:$dst, (bitconvert FR32:$src))]>;
4130 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4131 "movd\t{$src, $dst|$dst, $src}",
4132 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
4134 //===---------------------------------------------------------------------===//
4135 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4137 let AddedComplexity = 15 in {
4138 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4139 "movd\t{$src, $dst|$dst, $src}",
4140 [(set VR128:$dst, (v4i32 (X86vzmovl
4141 (v4i32 (scalar_to_vector GR32:$src)))))]>,
4143 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4144 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4145 [(set VR128:$dst, (v2i64 (X86vzmovl
4146 (v2i64 (scalar_to_vector GR64:$src)))))]>,
4149 let AddedComplexity = 15 in {
4150 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4151 "movd\t{$src, $dst|$dst, $src}",
4152 [(set VR128:$dst, (v4i32 (X86vzmovl
4153 (v4i32 (scalar_to_vector GR32:$src)))))]>;
4154 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4155 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4156 [(set VR128:$dst, (v2i64 (X86vzmovl
4157 (v2i64 (scalar_to_vector GR64:$src)))))]>;
4160 let AddedComplexity = 20 in {
4161 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4162 "movd\t{$src, $dst|$dst, $src}",
4164 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4165 (loadi32 addr:$src))))))]>,
4167 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4168 "movd\t{$src, $dst|$dst, $src}",
4170 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4171 (loadi32 addr:$src))))))]>;
4174 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4175 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4176 (MOVZDI2PDIrm addr:$src)>;
4177 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4178 (MOVZDI2PDIrm addr:$src)>;
4179 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4180 (MOVZDI2PDIrm addr:$src)>;
4183 let Predicates = [HasAVX] in {
4184 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4185 let AddedComplexity = 20 in {
4186 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4187 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrm addr:$src), sub_xmm)>;
4188 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4189 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrm addr:$src), sub_xmm)>;
4190 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4191 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrm addr:$src), sub_xmm)>;
4193 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4194 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4195 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4196 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4197 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4198 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4199 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4202 // These are the correct encodings of the instructions so that we know how to
4203 // read correct assembly, even though we continue to emit the wrong ones for
4204 // compatibility with Darwin's buggy assembler.
4205 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4206 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4207 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4208 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4209 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4210 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4211 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4212 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4213 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4214 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4215 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4216 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4218 //===---------------------------------------------------------------------===//
4219 // SSE2 - Move Quadword
4220 //===---------------------------------------------------------------------===//
4222 //===---------------------------------------------------------------------===//
4223 // Move Quadword Int to Packed Quadword Int
4225 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4226 "vmovq\t{$src, $dst|$dst, $src}",
4228 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4229 VEX, Requires<[HasAVX]>;
4230 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4231 "movq\t{$src, $dst|$dst, $src}",
4233 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4234 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4236 //===---------------------------------------------------------------------===//
4237 // Move Packed Quadword Int to Quadword Int
4239 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4240 "movq\t{$src, $dst|$dst, $src}",
4241 [(store (i64 (vector_extract (v2i64 VR128:$src),
4242 (iPTR 0))), addr:$dst)]>, VEX;
4243 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4244 "movq\t{$src, $dst|$dst, $src}",
4245 [(store (i64 (vector_extract (v2i64 VR128:$src),
4246 (iPTR 0))), addr:$dst)]>;
4248 //===---------------------------------------------------------------------===//
4249 // Store / copy lower 64-bits of a XMM register.
4251 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4252 "movq\t{$src, $dst|$dst, $src}",
4253 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4254 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4255 "movq\t{$src, $dst|$dst, $src}",
4256 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
4258 let AddedComplexity = 20 in
4259 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4260 "vmovq\t{$src, $dst|$dst, $src}",
4262 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4263 (loadi64 addr:$src))))))]>,
4264 XS, VEX, Requires<[HasAVX]>;
4266 let AddedComplexity = 20 in
4267 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4268 "movq\t{$src, $dst|$dst, $src}",
4270 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4271 (loadi64 addr:$src))))))]>,
4272 XS, Requires<[HasSSE2]>;
4274 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4275 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4276 (MOVZQI2PQIrm addr:$src)>;
4277 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4278 (MOVZQI2PQIrm addr:$src)>;
4279 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4282 let Predicates = [HasAVX], AddedComplexity = 20 in {
4283 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4284 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
4285 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4286 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
4287 def : Pat<(v2i64 (X86vzload addr:$src)),
4288 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
4291 //===---------------------------------------------------------------------===//
4292 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4293 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4295 let AddedComplexity = 15 in
4296 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4297 "vmovq\t{$src, $dst|$dst, $src}",
4298 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4299 XS, VEX, Requires<[HasAVX]>;
4300 let AddedComplexity = 15 in
4301 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4302 "movq\t{$src, $dst|$dst, $src}",
4303 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4304 XS, Requires<[HasSSE2]>;
4306 let AddedComplexity = 20 in
4307 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4308 "vmovq\t{$src, $dst|$dst, $src}",
4309 [(set VR128:$dst, (v2i64 (X86vzmovl
4310 (loadv2i64 addr:$src))))]>,
4311 XS, VEX, Requires<[HasAVX]>;
4312 let AddedComplexity = 20 in {
4313 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4314 "movq\t{$src, $dst|$dst, $src}",
4315 [(set VR128:$dst, (v2i64 (X86vzmovl
4316 (loadv2i64 addr:$src))))]>,
4317 XS, Requires<[HasSSE2]>;
4320 let AddedComplexity = 20 in {
4321 let Predicates = [HasSSE2] in {
4322 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4323 (MOVZPQILo2PQIrm addr:$src)>;
4324 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4325 (MOVZPQILo2PQIrr VR128:$src)>;
4327 let Predicates = [HasAVX] in {
4328 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4329 (SUBREG_TO_REG (i64 0), (VMOVZPQILo2PQIrm addr:$src), sub_xmm)>;
4330 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4331 (SUBREG_TO_REG (i64 0), (MOVZPQILo2PQIrr VR128:$src), sub_xmm)>;
4335 // Instructions to match in the assembler
4336 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4337 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4338 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4339 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4340 // Recognize "movd" with GR64 destination, but encode as a "movq"
4341 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4342 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4344 // Instructions for the disassembler
4345 // xr = XMM register
4348 let Predicates = [HasAVX] in
4349 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4350 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4351 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4352 "movq\t{$src, $dst|$dst, $src}", []>, XS;
4354 //===---------------------------------------------------------------------===//
4355 // SSE3 - Conversion Instructions
4356 //===---------------------------------------------------------------------===//
4358 // Convert Packed Double FP to Packed DW Integers
4359 let Predicates = [HasAVX] in {
4360 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4361 // register, but the same isn't true when using memory operands instead.
4362 // Provide other assembly rr and rm forms to address this explicitly.
4363 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4364 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4365 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4366 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4369 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4370 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4371 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4372 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4375 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4376 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4377 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4378 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4381 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4382 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4383 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4384 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4386 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4387 (VCVTPD2DQYrr VR256:$src)>;
4388 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4389 (VCVTPD2DQYrm addr:$src)>;
4391 // Convert Packed DW Integers to Packed Double FP
4392 let Predicates = [HasAVX] in {
4393 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4394 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4395 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4396 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4397 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4398 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4399 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4400 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4403 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4404 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4405 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4406 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4408 // AVX 256-bit register conversion intrinsics
4409 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4410 (VCVTDQ2PDYrr VR128:$src)>;
4411 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
4412 (VCVTDQ2PDYrm addr:$src)>;
4414 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4415 (VCVTPD2DQYrr VR256:$src)>;
4416 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4417 (VCVTPD2DQYrm addr:$src)>;
4419 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4420 (VCVTDQ2PDYrr VR128:$src)>;
4421 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
4422 (VCVTDQ2PDYrm addr:$src)>;
4424 //===---------------------------------------------------------------------===//
4425 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4426 //===---------------------------------------------------------------------===//
4427 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4428 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4429 X86MemOperand x86memop> {
4430 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4431 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4432 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
4433 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4434 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4435 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
4438 let Predicates = [HasAVX] in {
4439 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4440 v4f32, VR128, memopv4f32, f128mem>, VEX;
4441 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4442 v4f32, VR128, memopv4f32, f128mem>, VEX;
4443 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4444 v8f32, VR256, memopv8f32, f256mem>, VEX;
4445 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4446 v8f32, VR256, memopv8f32, f256mem>, VEX;
4448 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4449 memopv4f32, f128mem>;
4450 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4451 memopv4f32, f128mem>;
4453 let Predicates = [HasSSE3] in {
4454 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4455 (MOVSHDUPrr VR128:$src)>;
4456 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4457 (MOVSHDUPrm addr:$src)>;
4458 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4459 (MOVSLDUPrr VR128:$src)>;
4460 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4461 (MOVSLDUPrm addr:$src)>;
4464 let Predicates = [HasAVX] in {
4465 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4466 (VMOVSHDUPrr VR128:$src)>;
4467 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4468 (VMOVSHDUPrm addr:$src)>;
4469 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4470 (VMOVSLDUPrr VR128:$src)>;
4471 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4472 (VMOVSLDUPrm addr:$src)>;
4473 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4474 (VMOVSHDUPYrr VR256:$src)>;
4475 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4476 (VMOVSHDUPYrm addr:$src)>;
4477 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4478 (VMOVSLDUPYrr VR256:$src)>;
4479 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4480 (VMOVSLDUPYrm addr:$src)>;
4483 //===---------------------------------------------------------------------===//
4484 // SSE3 - Replicate Double FP - MOVDDUP
4485 //===---------------------------------------------------------------------===//
4487 multiclass sse3_replicate_dfp<string OpcodeStr> {
4488 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4489 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4490 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
4491 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4492 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4494 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
4498 // FIXME: Merge with above classe when there're patterns for the ymm version
4499 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4500 let Predicates = [HasAVX] in {
4501 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4502 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4504 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4505 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4510 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4511 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4512 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4514 let Predicates = [HasSSE3] in {
4515 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4517 (MOVDDUPrm addr:$src)>;
4518 let AddedComplexity = 5 in {
4519 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4520 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4521 (MOVDDUPrm addr:$src)>;
4522 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4523 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4524 (MOVDDUPrm addr:$src)>;
4526 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4527 (MOVDDUPrm addr:$src)>;
4528 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4529 (MOVDDUPrm addr:$src)>;
4530 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4531 (MOVDDUPrm addr:$src)>;
4532 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4533 (MOVDDUPrm addr:$src)>;
4534 def : Pat<(X86Movddup (bc_v2f64
4535 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4536 (MOVDDUPrm addr:$src)>;
4539 let Predicates = [HasAVX] in {
4540 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4542 (VMOVDDUPrm addr:$src)>;
4543 let AddedComplexity = 5 in {
4544 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4545 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4546 (VMOVDDUPrm addr:$src)>;
4547 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4548 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4549 (VMOVDDUPrm addr:$src)>;
4551 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4552 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4553 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4554 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4555 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4556 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4557 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4558 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4559 def : Pat<(X86Movddup (bc_v2f64
4560 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4561 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4564 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4565 (VMOVDDUPYrm addr:$src)>;
4566 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4567 (VMOVDDUPYrm addr:$src)>;
4568 def : Pat<(X86Movddup (v4f64 (scalar_to_vector (loadf64 addr:$src)))),
4569 (VMOVDDUPYrm addr:$src)>;
4570 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4571 (VMOVDDUPYrm addr:$src)>;
4572 def : Pat<(X86Movddup (v4f64 VR256:$src)),
4573 (VMOVDDUPYrr VR256:$src)>;
4574 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4575 (VMOVDDUPYrr VR256:$src)>;
4578 //===---------------------------------------------------------------------===//
4579 // SSE3 - Move Unaligned Integer
4580 //===---------------------------------------------------------------------===//
4582 let Predicates = [HasAVX] in {
4583 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4584 "vlddqu\t{$src, $dst|$dst, $src}",
4585 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4586 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4587 "vlddqu\t{$src, $dst|$dst, $src}",
4588 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4590 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4591 "lddqu\t{$src, $dst|$dst, $src}",
4592 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
4594 //===---------------------------------------------------------------------===//
4595 // SSE3 - Arithmetic
4596 //===---------------------------------------------------------------------===//
4598 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4599 X86MemOperand x86memop, bit Is2Addr = 1> {
4600 def rr : I<0xD0, MRMSrcReg,
4601 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4603 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4604 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4605 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
4606 def rm : I<0xD0, MRMSrcMem,
4607 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4609 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4610 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4611 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
4614 let Predicates = [HasAVX],
4615 ExeDomain = SSEPackedDouble in {
4616 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4617 f128mem, 0>, TB, XD, VEX_4V;
4618 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4619 f128mem, 0>, TB, OpSize, VEX_4V;
4620 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4621 f256mem, 0>, TB, XD, VEX_4V;
4622 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4623 f256mem, 0>, TB, OpSize, VEX_4V;
4625 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
4626 ExeDomain = SSEPackedDouble in {
4627 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4629 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4630 f128mem>, TB, OpSize;
4633 //===---------------------------------------------------------------------===//
4634 // SSE3 Instructions
4635 //===---------------------------------------------------------------------===//
4638 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4639 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
4640 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4642 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4643 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4644 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
4646 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4648 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4649 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4650 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
4652 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4653 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
4654 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4656 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4657 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4658 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
4660 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4662 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4663 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4664 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
4667 let Predicates = [HasAVX] in {
4668 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4669 int_x86_sse3_hadd_ps, 0>, VEX_4V;
4670 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4671 int_x86_sse3_hadd_pd, 0>, VEX_4V;
4672 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4673 int_x86_sse3_hsub_ps, 0>, VEX_4V;
4674 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4675 int_x86_sse3_hsub_pd, 0>, VEX_4V;
4676 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4677 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
4678 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4679 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
4680 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4681 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
4682 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4683 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
4686 let Constraints = "$src1 = $dst" in {
4687 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
4688 int_x86_sse3_hadd_ps>;
4689 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
4690 int_x86_sse3_hadd_pd>;
4691 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
4692 int_x86_sse3_hsub_ps>;
4693 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
4694 int_x86_sse3_hsub_pd>;
4697 //===---------------------------------------------------------------------===//
4698 // SSSE3 - Packed Absolute Instructions
4699 //===---------------------------------------------------------------------===//
4702 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4703 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4704 PatFrag mem_frag128, Intrinsic IntId128> {
4705 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4707 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4708 [(set VR128:$dst, (IntId128 VR128:$src))]>,
4711 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4713 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4716 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
4719 let Predicates = [HasAVX] in {
4720 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
4721 int_x86_ssse3_pabs_b_128>, VEX;
4722 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
4723 int_x86_ssse3_pabs_w_128>, VEX;
4724 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
4725 int_x86_ssse3_pabs_d_128>, VEX;
4728 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
4729 int_x86_ssse3_pabs_b_128>;
4730 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
4731 int_x86_ssse3_pabs_w_128>;
4732 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
4733 int_x86_ssse3_pabs_d_128>;
4735 //===---------------------------------------------------------------------===//
4736 // SSSE3 - Packed Binary Operator Instructions
4737 //===---------------------------------------------------------------------===//
4739 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
4740 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
4741 PatFrag mem_frag128, Intrinsic IntId128,
4743 let isCommutable = 1 in
4744 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4745 (ins VR128:$src1, VR128:$src2),
4747 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4748 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4749 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4751 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4752 (ins VR128:$src1, i128mem:$src2),
4754 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4755 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4757 (IntId128 VR128:$src1,
4758 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4761 let Predicates = [HasAVX] in {
4762 let isCommutable = 0 in {
4763 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
4764 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
4765 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
4766 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
4767 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
4768 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
4769 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
4770 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
4771 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
4772 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
4773 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
4774 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
4775 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
4776 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
4777 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
4778 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
4779 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
4780 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
4781 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
4782 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
4783 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
4784 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
4786 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
4787 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
4790 // None of these have i8 immediate fields.
4791 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
4792 let isCommutable = 0 in {
4793 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
4794 int_x86_ssse3_phadd_w_128>;
4795 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
4796 int_x86_ssse3_phadd_d_128>;
4797 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
4798 int_x86_ssse3_phadd_sw_128>;
4799 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
4800 int_x86_ssse3_phsub_w_128>;
4801 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
4802 int_x86_ssse3_phsub_d_128>;
4803 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
4804 int_x86_ssse3_phsub_sw_128>;
4805 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
4806 int_x86_ssse3_pmadd_ub_sw_128>;
4807 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
4808 int_x86_ssse3_pshuf_b_128>;
4809 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
4810 int_x86_ssse3_psign_b_128>;
4811 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
4812 int_x86_ssse3_psign_w_128>;
4813 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
4814 int_x86_ssse3_psign_d_128>;
4816 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
4817 int_x86_ssse3_pmul_hr_sw_128>;
4820 let Predicates = [HasSSSE3] in {
4821 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4822 (PSHUFBrr128 VR128:$src, VR128:$mask)>;
4823 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4824 (PSHUFBrm128 VR128:$src, addr:$mask)>;
4826 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4827 (PSIGNBrr128 VR128:$src1, VR128:$src2)>;
4828 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4829 (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
4830 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4831 (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
4834 let Predicates = [HasAVX] in {
4835 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4836 (VPSHUFBrr128 VR128:$src, VR128:$mask)>;
4837 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4838 (VPSHUFBrm128 VR128:$src, addr:$mask)>;
4840 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4841 (VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
4842 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4843 (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
4844 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4845 (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
4848 //===---------------------------------------------------------------------===//
4849 // SSSE3 - Packed Align Instruction Patterns
4850 //===---------------------------------------------------------------------===//
4852 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
4853 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
4854 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4856 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4858 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4860 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
4861 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4863 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4865 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4869 let Predicates = [HasAVX] in
4870 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
4871 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
4872 defm PALIGN : ssse3_palign<"palignr">;
4874 let Predicates = [HasSSSE3] in {
4875 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4876 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4877 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4878 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4879 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4880 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4881 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4882 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4885 let Predicates = [HasAVX] in {
4886 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4887 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4888 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4889 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4890 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4891 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4892 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4893 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4896 //===---------------------------------------------------------------------===//
4897 // SSSE3 - Thread synchronization
4898 //===---------------------------------------------------------------------===//
4900 let usesCustomInserter = 1 in {
4901 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
4902 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
4903 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
4904 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
4907 let Uses = [EAX, ECX, EDX] in
4908 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
4909 Requires<[HasSSE3]>;
4910 let Uses = [ECX, EAX] in
4911 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
4912 Requires<[HasSSE3]>;
4914 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
4915 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
4917 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
4918 Requires<[In32BitMode]>;
4919 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
4920 Requires<[In64BitMode]>;
4922 //===----------------------------------------------------------------------===//
4923 // SSE4.1 - Packed Move with Sign/Zero Extend
4924 //===----------------------------------------------------------------------===//
4926 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4927 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4928 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4929 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4931 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4932 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4934 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
4938 let Predicates = [HasAVX] in {
4939 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
4941 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
4943 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
4945 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
4947 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
4949 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
4953 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4954 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4955 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4956 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4957 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4958 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4960 let Predicates = [HasSSE41] in {
4961 // Common patterns involving scalar load.
4962 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4963 (PMOVSXBWrm addr:$src)>;
4964 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4965 (PMOVSXBWrm addr:$src)>;
4967 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4968 (PMOVSXWDrm addr:$src)>;
4969 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4970 (PMOVSXWDrm addr:$src)>;
4972 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4973 (PMOVSXDQrm addr:$src)>;
4974 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4975 (PMOVSXDQrm addr:$src)>;
4977 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4978 (PMOVZXBWrm addr:$src)>;
4979 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4980 (PMOVZXBWrm addr:$src)>;
4982 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4983 (PMOVZXWDrm addr:$src)>;
4984 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4985 (PMOVZXWDrm addr:$src)>;
4987 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4988 (PMOVZXDQrm addr:$src)>;
4989 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4990 (PMOVZXDQrm addr:$src)>;
4993 let Predicates = [HasAVX] in {
4994 // Common patterns involving scalar load.
4995 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4996 (VPMOVSXBWrm addr:$src)>;
4997 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4998 (VPMOVSXBWrm addr:$src)>;
5000 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5001 (VPMOVSXWDrm addr:$src)>;
5002 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5003 (VPMOVSXWDrm addr:$src)>;
5005 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5006 (VPMOVSXDQrm addr:$src)>;
5007 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5008 (VPMOVSXDQrm addr:$src)>;
5010 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5011 (VPMOVZXBWrm addr:$src)>;
5012 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5013 (VPMOVZXBWrm addr:$src)>;
5015 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5016 (VPMOVZXWDrm addr:$src)>;
5017 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5018 (VPMOVZXWDrm addr:$src)>;
5020 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5021 (VPMOVZXDQrm addr:$src)>;
5022 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5023 (VPMOVZXDQrm addr:$src)>;
5027 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5028 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5029 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5030 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5032 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5033 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5035 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5039 let Predicates = [HasAVX] in {
5040 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5042 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5044 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5046 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5050 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5051 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5052 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5053 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5055 let Predicates = [HasSSE41] in {
5056 // Common patterns involving scalar load
5057 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5058 (PMOVSXBDrm addr:$src)>;
5059 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5060 (PMOVSXWQrm addr:$src)>;
5062 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5063 (PMOVZXBDrm addr:$src)>;
5064 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5065 (PMOVZXWQrm addr:$src)>;
5068 let Predicates = [HasAVX] in {
5069 // Common patterns involving scalar load
5070 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5071 (VPMOVSXBDrm addr:$src)>;
5072 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5073 (VPMOVSXWQrm addr:$src)>;
5075 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5076 (VPMOVZXBDrm addr:$src)>;
5077 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5078 (VPMOVZXWQrm addr:$src)>;
5081 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5082 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5083 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5084 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5086 // Expecting a i16 load any extended to i32 value.
5087 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5088 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5089 [(set VR128:$dst, (IntId (bitconvert
5090 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5094 let Predicates = [HasAVX] in {
5095 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5097 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5100 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5101 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5103 let Predicates = [HasSSE41] in {
5104 // Common patterns involving scalar load
5105 def : Pat<(int_x86_sse41_pmovsxbq
5106 (bitconvert (v4i32 (X86vzmovl
5107 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5108 (PMOVSXBQrm addr:$src)>;
5110 def : Pat<(int_x86_sse41_pmovzxbq
5111 (bitconvert (v4i32 (X86vzmovl
5112 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5113 (PMOVZXBQrm addr:$src)>;
5116 let Predicates = [HasAVX] in {
5117 // Common patterns involving scalar load
5118 def : Pat<(int_x86_sse41_pmovsxbq
5119 (bitconvert (v4i32 (X86vzmovl
5120 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5121 (VPMOVSXBQrm addr:$src)>;
5123 def : Pat<(int_x86_sse41_pmovzxbq
5124 (bitconvert (v4i32 (X86vzmovl
5125 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5126 (VPMOVZXBQrm addr:$src)>;
5129 //===----------------------------------------------------------------------===//
5130 // SSE4.1 - Extract Instructions
5131 //===----------------------------------------------------------------------===//
5133 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5134 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5135 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5136 (ins VR128:$src1, i32i8imm:$src2),
5137 !strconcat(OpcodeStr,
5138 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5139 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5141 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5142 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5143 !strconcat(OpcodeStr,
5144 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5147 // There's an AssertZext in the way of writing the store pattern
5148 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5151 let Predicates = [HasAVX] in {
5152 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5153 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5154 (ins VR128:$src1, i32i8imm:$src2),
5155 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5158 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5161 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5162 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5163 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5164 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5165 !strconcat(OpcodeStr,
5166 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5169 // There's an AssertZext in the way of writing the store pattern
5170 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5173 let Predicates = [HasAVX] in
5174 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5176 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5179 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5180 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5181 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5182 (ins VR128:$src1, i32i8imm:$src2),
5183 !strconcat(OpcodeStr,
5184 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5186 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5187 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5188 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5189 !strconcat(OpcodeStr,
5190 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5191 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5192 addr:$dst)]>, OpSize;
5195 let Predicates = [HasAVX] in
5196 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5198 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5200 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5201 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5202 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5203 (ins VR128:$src1, i32i8imm:$src2),
5204 !strconcat(OpcodeStr,
5205 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5207 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5208 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5209 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5210 !strconcat(OpcodeStr,
5211 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5212 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5213 addr:$dst)]>, OpSize, REX_W;
5216 let Predicates = [HasAVX] in
5217 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5219 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5221 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5223 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5224 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5225 (ins VR128:$src1, i32i8imm:$src2),
5226 !strconcat(OpcodeStr,
5227 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5229 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5231 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5232 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5233 !strconcat(OpcodeStr,
5234 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5235 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5236 addr:$dst)]>, OpSize;
5239 let Predicates = [HasAVX] in {
5240 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5241 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5242 (ins VR128:$src1, i32i8imm:$src2),
5243 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5246 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5248 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5249 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5252 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5253 Requires<[HasSSE41]>;
5254 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5257 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5260 //===----------------------------------------------------------------------===//
5261 // SSE4.1 - Insert Instructions
5262 //===----------------------------------------------------------------------===//
5264 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5265 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5266 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5268 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5270 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5272 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5273 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5274 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5276 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5278 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5280 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5281 imm:$src3))]>, OpSize;
5284 let Predicates = [HasAVX] in
5285 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5286 let Constraints = "$src1 = $dst" in
5287 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5289 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5290 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5291 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5293 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5297 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5299 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5300 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5302 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5304 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5306 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5307 imm:$src3)))]>, OpSize;
5310 let Predicates = [HasAVX] in
5311 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5312 let Constraints = "$src1 = $dst" in
5313 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5315 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5316 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5317 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5319 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5321 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5323 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5325 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5326 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5328 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5330 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5332 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5333 imm:$src3)))]>, OpSize;
5336 let Predicates = [HasAVX] in
5337 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5338 let Constraints = "$src1 = $dst" in
5339 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5341 // insertps has a few different modes, there's the first two here below which
5342 // are optimized inserts that won't zero arbitrary elements in the destination
5343 // vector. The next one matches the intrinsic and could zero arbitrary elements
5344 // in the target vector.
5345 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5346 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5347 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5349 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5351 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5353 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5355 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5356 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5358 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5360 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5362 (X86insrtps VR128:$src1,
5363 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
5364 imm:$src3))]>, OpSize;
5367 let Constraints = "$src1 = $dst" in
5368 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
5369 let Predicates = [HasAVX] in
5370 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
5372 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5373 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5375 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5376 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5377 Requires<[HasSSE41]>;
5379 //===----------------------------------------------------------------------===//
5380 // SSE4.1 - Round Instructions
5381 //===----------------------------------------------------------------------===//
5383 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
5384 X86MemOperand x86memop, RegisterClass RC,
5385 PatFrag mem_frag32, PatFrag mem_frag64,
5386 Intrinsic V4F32Int, Intrinsic V2F64Int> {
5387 // Intrinsic operation, reg.
5388 // Vector intrinsic operation, reg
5389 def PSr : SS4AIi8<opcps, MRMSrcReg,
5390 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5391 !strconcat(OpcodeStr,
5392 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5393 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
5396 // Vector intrinsic operation, mem
5397 def PSm : Ii8<opcps, MRMSrcMem,
5398 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
5399 !strconcat(OpcodeStr,
5400 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5402 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
5404 Requires<[HasSSE41]>;
5406 // Vector intrinsic operation, reg
5407 def PDr : SS4AIi8<opcpd, MRMSrcReg,
5408 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5409 !strconcat(OpcodeStr,
5410 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5411 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
5414 // Vector intrinsic operation, mem
5415 def PDm : SS4AIi8<opcpd, MRMSrcMem,
5416 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
5417 !strconcat(OpcodeStr,
5418 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5420 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
5424 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
5425 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
5426 // Intrinsic operation, reg.
5427 // Vector intrinsic operation, reg
5428 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
5429 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5430 !strconcat(OpcodeStr,
5431 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5434 // Vector intrinsic operation, mem
5435 def PSm_AVX : Ii8<opcps, MRMSrcMem,
5436 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5437 !strconcat(OpcodeStr,
5438 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5439 []>, TA, OpSize, Requires<[HasSSE41]>;
5441 // Vector intrinsic operation, reg
5442 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
5443 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5444 !strconcat(OpcodeStr,
5445 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5448 // Vector intrinsic operation, mem
5449 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
5450 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5451 !strconcat(OpcodeStr,
5452 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5456 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
5459 Intrinsic F64Int, bit Is2Addr = 1> {
5460 // Intrinsic operation, reg.
5461 def SSr : SS4AIi8<opcss, MRMSrcReg,
5462 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5464 !strconcat(OpcodeStr,
5465 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5466 !strconcat(OpcodeStr,
5467 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5468 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5471 // Intrinsic operation, mem.
5472 def SSm : SS4AIi8<opcss, MRMSrcMem,
5473 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5475 !strconcat(OpcodeStr,
5476 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5477 !strconcat(OpcodeStr,
5478 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5480 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
5483 // Intrinsic operation, reg.
5484 def SDr : SS4AIi8<opcsd, MRMSrcReg,
5485 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5487 !strconcat(OpcodeStr,
5488 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5489 !strconcat(OpcodeStr,
5490 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5491 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5494 // Intrinsic operation, mem.
5495 def SDm : SS4AIi8<opcsd, MRMSrcMem,
5496 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5498 !strconcat(OpcodeStr,
5499 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5500 !strconcat(OpcodeStr,
5501 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5503 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
5507 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
5509 // Intrinsic operation, reg.
5510 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
5511 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5512 !strconcat(OpcodeStr,
5513 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5516 // Intrinsic operation, mem.
5517 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
5518 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5519 !strconcat(OpcodeStr,
5520 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5523 // Intrinsic operation, reg.
5524 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
5525 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5526 !strconcat(OpcodeStr,
5527 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5530 // Intrinsic operation, mem.
5531 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
5532 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5533 !strconcat(OpcodeStr,
5534 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5538 // FP round - roundss, roundps, roundsd, roundpd
5539 let Predicates = [HasAVX] in {
5541 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
5542 memopv4f32, memopv2f64,
5543 int_x86_sse41_round_ps,
5544 int_x86_sse41_round_pd>, VEX;
5545 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
5546 memopv8f32, memopv4f64,
5547 int_x86_avx_round_ps_256,
5548 int_x86_avx_round_pd_256>, VEX;
5549 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
5550 int_x86_sse41_round_ss,
5551 int_x86_sse41_round_sd, 0>, VEX_4V;
5553 // Instructions for the assembler
5554 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
5556 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
5558 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
5561 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
5562 memopv4f32, memopv2f64,
5563 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
5564 let Constraints = "$src1 = $dst" in
5565 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
5566 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
5568 //===----------------------------------------------------------------------===//
5569 // SSE4.1 - Packed Bit Test
5570 //===----------------------------------------------------------------------===//
5572 // ptest instruction we'll lower to this in X86ISelLowering primarily from
5573 // the intel intrinsic that corresponds to this.
5574 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5575 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5576 "vptest\t{$src2, $src1|$src1, $src2}",
5577 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5579 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5580 "vptest\t{$src2, $src1|$src1, $src2}",
5581 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5584 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
5585 "vptest\t{$src2, $src1|$src1, $src2}",
5586 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
5588 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
5589 "vptest\t{$src2, $src1|$src1, $src2}",
5590 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
5594 let Defs = [EFLAGS] in {
5595 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5596 "ptest \t{$src2, $src1|$src1, $src2}",
5597 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5599 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5600 "ptest \t{$src2, $src1|$src1, $src2}",
5601 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5605 // The bit test instructions below are AVX only
5606 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
5607 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
5608 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
5609 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5610 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
5611 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
5612 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5613 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
5617 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5618 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
5619 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
5620 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
5621 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
5624 //===----------------------------------------------------------------------===//
5625 // SSE4.1 - Misc Instructions
5626 //===----------------------------------------------------------------------===//
5628 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
5629 "popcnt{w}\t{$src, $dst|$dst, $src}",
5630 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
5631 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
5632 "popcnt{w}\t{$src, $dst|$dst, $src}",
5633 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
5635 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
5636 "popcnt{l}\t{$src, $dst|$dst, $src}",
5637 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
5638 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
5639 "popcnt{l}\t{$src, $dst|$dst, $src}",
5640 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
5642 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
5643 "popcnt{q}\t{$src, $dst|$dst, $src}",
5644 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
5645 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
5646 "popcnt{q}\t{$src, $dst|$dst, $src}",
5647 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
5651 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
5652 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
5653 Intrinsic IntId128> {
5654 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5656 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5657 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
5658 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5660 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5663 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
5666 let Predicates = [HasAVX] in
5667 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
5668 int_x86_sse41_phminposuw>, VEX;
5669 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
5670 int_x86_sse41_phminposuw>;
5672 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
5673 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
5674 Intrinsic IntId128, bit Is2Addr = 1> {
5675 let isCommutable = 1 in
5676 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5677 (ins VR128:$src1, VR128:$src2),
5679 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5680 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5681 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
5682 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5683 (ins VR128:$src1, i128mem:$src2),
5685 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5686 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5688 (IntId128 VR128:$src1,
5689 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5692 let Predicates = [HasAVX] in {
5693 let isCommutable = 0 in
5694 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
5696 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
5698 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
5700 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
5702 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
5704 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
5706 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
5708 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
5710 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
5712 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
5714 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
5717 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5718 (VPCMPEQQrr VR128:$src1, VR128:$src2)>;
5719 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5720 (VPCMPEQQrm VR128:$src1, addr:$src2)>;
5723 let Constraints = "$src1 = $dst" in {
5724 let isCommutable = 0 in
5725 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
5726 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
5727 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
5728 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
5729 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
5730 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
5731 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
5732 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
5733 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
5734 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
5735 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
5738 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5739 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
5740 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5741 (PCMPEQQrm VR128:$src1, addr:$src2)>;
5743 /// SS48I_binop_rm - Simple SSE41 binary operator.
5744 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5745 ValueType OpVT, bit Is2Addr = 1> {
5746 let isCommutable = 1 in
5747 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5748 (ins VR128:$src1, VR128:$src2),
5750 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5751 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5752 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
5754 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5755 (ins VR128:$src1, i128mem:$src2),
5757 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5758 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5759 [(set VR128:$dst, (OpNode VR128:$src1,
5760 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
5764 let Predicates = [HasAVX] in
5765 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
5766 let Constraints = "$src1 = $dst" in
5767 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
5769 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
5770 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
5771 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
5772 X86MemOperand x86memop, bit Is2Addr = 1> {
5773 let isCommutable = 1 in
5774 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
5775 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
5777 !strconcat(OpcodeStr,
5778 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5779 !strconcat(OpcodeStr,
5780 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5781 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
5783 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
5784 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
5786 !strconcat(OpcodeStr,
5787 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5788 !strconcat(OpcodeStr,
5789 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5792 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
5796 let Predicates = [HasAVX] in {
5797 let isCommutable = 0 in {
5798 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
5799 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5800 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
5801 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5802 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
5803 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5804 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
5805 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5806 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
5807 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5808 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
5809 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5811 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
5812 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5813 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
5814 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5815 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
5816 VR256, memopv32i8, i256mem, 0>, VEX_4V;
5819 let Constraints = "$src1 = $dst" in {
5820 let isCommutable = 0 in {
5821 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
5822 VR128, memopv16i8, i128mem>;
5823 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
5824 VR128, memopv16i8, i128mem>;
5825 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
5826 VR128, memopv16i8, i128mem>;
5827 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
5828 VR128, memopv16i8, i128mem>;
5830 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
5831 VR128, memopv16i8, i128mem>;
5832 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
5833 VR128, memopv16i8, i128mem>;
5836 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
5837 let Predicates = [HasAVX] in {
5838 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
5839 RegisterClass RC, X86MemOperand x86memop,
5840 PatFrag mem_frag, Intrinsic IntId> {
5841 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
5842 (ins RC:$src1, RC:$src2, RC:$src3),
5843 !strconcat(OpcodeStr,
5844 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5845 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
5846 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5848 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
5849 (ins RC:$src1, x86memop:$src2, RC:$src3),
5850 !strconcat(OpcodeStr,
5851 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5853 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
5855 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5859 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
5860 memopv16i8, int_x86_sse41_blendvpd>;
5861 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
5862 memopv16i8, int_x86_sse41_blendvps>;
5863 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
5864 memopv16i8, int_x86_sse41_pblendvb>;
5865 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
5866 memopv32i8, int_x86_avx_blendv_pd_256>;
5867 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
5868 memopv32i8, int_x86_avx_blendv_ps_256>;
5870 let Predicates = [HasAVX] in {
5871 def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, VR128:$mask),
5872 (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5873 def : Pat<(X86blendvpd VR128:$src1, VR128:$src2, VR128:$mask),
5874 (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5875 def : Pat<(X86blendvps VR128:$src1, VR128:$src2, VR128:$mask),
5876 (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5879 /// SS41I_ternary_int - SSE 4.1 ternary operator
5880 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
5881 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5882 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5883 (ins VR128:$src1, VR128:$src2),
5884 !strconcat(OpcodeStr,
5885 "\t{$src2, $dst|$dst, $src2}"),
5886 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
5889 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5890 (ins VR128:$src1, i128mem:$src2),
5891 !strconcat(OpcodeStr,
5892 "\t{$src2, $dst|$dst, $src2}"),
5895 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
5899 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
5900 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
5901 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
5903 let Predicates = [HasSSE41] in {
5904 def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, XMM0),
5905 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
5906 def : Pat<(X86blendvpd VR128:$src1, VR128:$src2, XMM0),
5907 (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
5908 def : Pat<(X86blendvps VR128:$src1, VR128:$src2, XMM0),
5909 (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
5912 let Predicates = [HasAVX] in
5913 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5914 "vmovntdqa\t{$src, $dst|$dst, $src}",
5915 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
5917 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5918 "movntdqa\t{$src, $dst|$dst, $src}",
5919 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
5922 //===----------------------------------------------------------------------===//
5923 // SSE4.2 - Compare Instructions
5924 //===----------------------------------------------------------------------===//
5926 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
5927 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
5928 Intrinsic IntId128, bit Is2Addr = 1> {
5929 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
5930 (ins VR128:$src1, VR128:$src2),
5932 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5933 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5934 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5936 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
5937 (ins VR128:$src1, i128mem:$src2),
5939 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5940 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5942 (IntId128 VR128:$src1,
5943 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5946 let Predicates = [HasAVX] in {
5947 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
5950 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
5951 (VPCMPGTQrr VR128:$src1, VR128:$src2)>;
5952 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
5953 (VPCMPGTQrm VR128:$src1, addr:$src2)>;
5956 let Constraints = "$src1 = $dst" in
5957 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
5959 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
5960 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
5961 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
5962 (PCMPGTQrm VR128:$src1, addr:$src2)>;
5964 //===----------------------------------------------------------------------===//
5965 // SSE4.2 - String/text Processing Instructions
5966 //===----------------------------------------------------------------------===//
5968 // Packed Compare Implicit Length Strings, Return Mask
5969 multiclass pseudo_pcmpistrm<string asm> {
5970 def REG : PseudoI<(outs VR128:$dst),
5971 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5972 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
5974 def MEM : PseudoI<(outs VR128:$dst),
5975 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5976 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
5977 VR128:$src1, (load addr:$src2), imm:$src3))]>;
5980 let Defs = [EFLAGS], usesCustomInserter = 1 in {
5981 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
5982 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
5985 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
5986 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5987 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5988 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5989 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5990 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5991 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
5994 let Defs = [XMM0, EFLAGS] in {
5995 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
5996 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5997 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
5998 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
5999 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6000 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6003 // Packed Compare Explicit Length Strings, Return Mask
6004 multiclass pseudo_pcmpestrm<string asm> {
6005 def REG : PseudoI<(outs VR128:$dst),
6006 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6007 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6008 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6009 def MEM : PseudoI<(outs VR128:$dst),
6010 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6011 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6012 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6015 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6016 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6017 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6020 let Predicates = [HasAVX],
6021 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
6022 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6023 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6024 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6025 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6026 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6027 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6030 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
6031 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6032 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6033 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6034 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6035 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6036 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6039 // Packed Compare Implicit Length Strings, Return Index
6040 let Defs = [ECX, EFLAGS] in {
6041 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6042 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6043 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6044 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6045 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6046 (implicit EFLAGS)]>, OpSize;
6047 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6048 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6049 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6050 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6051 (implicit EFLAGS)]>, OpSize;
6055 let Predicates = [HasAVX] in {
6056 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6058 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6060 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6062 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6064 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6066 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6070 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6071 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6072 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6073 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6074 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6075 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6077 // Packed Compare Explicit Length Strings, Return Index
6078 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6079 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6080 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6081 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6082 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6083 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6084 (implicit EFLAGS)]>, OpSize;
6085 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6086 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6087 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6089 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6090 (implicit EFLAGS)]>, OpSize;
6094 let Predicates = [HasAVX] in {
6095 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6097 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6099 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6101 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6103 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6105 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6109 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6110 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6111 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6112 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6113 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6114 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6116 //===----------------------------------------------------------------------===//
6117 // SSE4.2 - CRC Instructions
6118 //===----------------------------------------------------------------------===//
6120 // No CRC instructions have AVX equivalents
6122 // crc intrinsic instruction
6123 // This set of instructions are only rm, the only difference is the size
6125 let Constraints = "$src1 = $dst" in {
6126 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6127 (ins GR32:$src1, i8mem:$src2),
6128 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6130 (int_x86_sse42_crc32_32_8 GR32:$src1,
6131 (load addr:$src2)))]>;
6132 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6133 (ins GR32:$src1, GR8:$src2),
6134 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6136 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6137 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6138 (ins GR32:$src1, i16mem:$src2),
6139 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6141 (int_x86_sse42_crc32_32_16 GR32:$src1,
6142 (load addr:$src2)))]>,
6144 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6145 (ins GR32:$src1, GR16:$src2),
6146 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6148 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6150 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6151 (ins GR32:$src1, i32mem:$src2),
6152 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6154 (int_x86_sse42_crc32_32_32 GR32:$src1,
6155 (load addr:$src2)))]>;
6156 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6157 (ins GR32:$src1, GR32:$src2),
6158 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6160 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6161 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6162 (ins GR64:$src1, i8mem:$src2),
6163 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6165 (int_x86_sse42_crc32_64_8 GR64:$src1,
6166 (load addr:$src2)))]>,
6168 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6169 (ins GR64:$src1, GR8:$src2),
6170 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6172 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6174 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6175 (ins GR64:$src1, i64mem:$src2),
6176 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6178 (int_x86_sse42_crc32_64_64 GR64:$src1,
6179 (load addr:$src2)))]>,
6181 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6182 (ins GR64:$src1, GR64:$src2),
6183 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6185 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6189 //===----------------------------------------------------------------------===//
6190 // AES-NI Instructions
6191 //===----------------------------------------------------------------------===//
6193 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
6194 Intrinsic IntId128, bit Is2Addr = 1> {
6195 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
6196 (ins VR128:$src1, VR128:$src2),
6198 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6199 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6200 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6202 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
6203 (ins VR128:$src1, i128mem:$src2),
6205 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6206 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6208 (IntId128 VR128:$src1,
6209 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6212 // Perform One Round of an AES Encryption/Decryption Flow
6213 let Predicates = [HasAVX, HasAES] in {
6214 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
6215 int_x86_aesni_aesenc, 0>, VEX_4V;
6216 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
6217 int_x86_aesni_aesenclast, 0>, VEX_4V;
6218 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
6219 int_x86_aesni_aesdec, 0>, VEX_4V;
6220 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
6221 int_x86_aesni_aesdeclast, 0>, VEX_4V;
6224 let Constraints = "$src1 = $dst" in {
6225 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
6226 int_x86_aesni_aesenc>;
6227 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
6228 int_x86_aesni_aesenclast>;
6229 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
6230 int_x86_aesni_aesdec>;
6231 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
6232 int_x86_aesni_aesdeclast>;
6235 let Predicates = [HasAES] in {
6236 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6237 (AESENCrr VR128:$src1, VR128:$src2)>;
6238 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6239 (AESENCrm VR128:$src1, addr:$src2)>;
6240 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6241 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
6242 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6243 (AESENCLASTrm VR128:$src1, addr:$src2)>;
6244 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6245 (AESDECrr VR128:$src1, VR128:$src2)>;
6246 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6247 (AESDECrm VR128:$src1, addr:$src2)>;
6248 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6249 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
6250 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6251 (AESDECLASTrm VR128:$src1, addr:$src2)>;
6254 let Predicates = [HasAVX, HasAES], AddedComplexity = 20 in {
6255 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6256 (VAESENCrr VR128:$src1, VR128:$src2)>;
6257 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6258 (VAESENCrm VR128:$src1, addr:$src2)>;
6259 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6260 (VAESENCLASTrr VR128:$src1, VR128:$src2)>;
6261 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6262 (VAESENCLASTrm VR128:$src1, addr:$src2)>;
6263 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6264 (VAESDECrr VR128:$src1, VR128:$src2)>;
6265 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6266 (VAESDECrm VR128:$src1, addr:$src2)>;
6267 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6268 (VAESDECLASTrr VR128:$src1, VR128:$src2)>;
6269 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6270 (VAESDECLASTrm VR128:$src1, addr:$src2)>;
6273 // Perform the AES InvMixColumn Transformation
6274 let Predicates = [HasAVX, HasAES] in {
6275 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6277 "vaesimc\t{$src1, $dst|$dst, $src1}",
6279 (int_x86_aesni_aesimc VR128:$src1))]>,
6281 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6282 (ins i128mem:$src1),
6283 "vaesimc\t{$src1, $dst|$dst, $src1}",
6285 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6288 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6290 "aesimc\t{$src1, $dst|$dst, $src1}",
6292 (int_x86_aesni_aesimc VR128:$src1))]>,
6294 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6295 (ins i128mem:$src1),
6296 "aesimc\t{$src1, $dst|$dst, $src1}",
6298 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6301 // AES Round Key Generation Assist
6302 let Predicates = [HasAVX, HasAES] in {
6303 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6304 (ins VR128:$src1, i8imm:$src2),
6305 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6307 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6309 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6310 (ins i128mem:$src1, i8imm:$src2),
6311 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6313 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
6317 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6318 (ins VR128:$src1, i8imm:$src2),
6319 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6321 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6323 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6324 (ins i128mem:$src1, i8imm:$src2),
6325 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6327 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
6331 //===----------------------------------------------------------------------===//
6332 // CLMUL Instructions
6333 //===----------------------------------------------------------------------===//
6335 // Carry-less Multiplication instructions
6336 let Constraints = "$src1 = $dst" in {
6337 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6338 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6339 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6342 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6343 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6344 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6348 // AVX carry-less Multiplication instructions
6349 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6350 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6351 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6354 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6355 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6356 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6360 multiclass pclmul_alias<string asm, int immop> {
6361 def : InstAlias<!strconcat("pclmul", asm,
6362 "dq {$src, $dst|$dst, $src}"),
6363 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
6365 def : InstAlias<!strconcat("pclmul", asm,
6366 "dq {$src, $dst|$dst, $src}"),
6367 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
6369 def : InstAlias<!strconcat("vpclmul", asm,
6370 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6371 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
6373 def : InstAlias<!strconcat("vpclmul", asm,
6374 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6375 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
6377 defm : pclmul_alias<"hqhq", 0x11>;
6378 defm : pclmul_alias<"hqlq", 0x01>;
6379 defm : pclmul_alias<"lqhq", 0x10>;
6380 defm : pclmul_alias<"lqlq", 0x00>;
6382 //===----------------------------------------------------------------------===//
6384 //===----------------------------------------------------------------------===//
6386 //===----------------------------------------------------------------------===//
6387 // VBROADCAST - Load from memory and broadcast to all elements of the
6388 // destination operand
6390 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
6391 X86MemOperand x86memop, Intrinsic Int> :
6392 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
6393 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6394 [(set RC:$dst, (Int addr:$src))]>, VEX;
6396 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
6397 int_x86_avx_vbroadcastss>;
6398 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
6399 int_x86_avx_vbroadcastss_256>;
6400 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
6401 int_x86_avx_vbroadcast_sd_256>;
6402 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
6403 int_x86_avx_vbroadcastf128_pd_256>;
6405 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
6406 (VBROADCASTF128 addr:$src)>;
6408 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
6409 (VBROADCASTSSY addr:$src)>;
6410 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
6411 (VBROADCASTSD addr:$src)>;
6412 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
6413 (VBROADCASTSSY addr:$src)>;
6414 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
6415 (VBROADCASTSD addr:$src)>;
6417 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
6418 (VBROADCASTSS addr:$src)>;
6419 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
6420 (VBROADCASTSS addr:$src)>;
6422 //===----------------------------------------------------------------------===//
6423 // VINSERTF128 - Insert packed floating-point values
6425 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
6426 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
6427 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6429 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
6430 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
6431 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6434 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
6435 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6436 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
6437 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6438 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
6439 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6441 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
6443 (VINSERTF128rr VR256:$src1, VR128:$src2,
6444 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6445 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
6447 (VINSERTF128rr VR256:$src1, VR128:$src2,
6448 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6449 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
6451 (VINSERTF128rr VR256:$src1, VR128:$src2,
6452 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6453 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
6455 (VINSERTF128rr VR256:$src1, VR128:$src2,
6456 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6457 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
6459 (VINSERTF128rr VR256:$src1, VR128:$src2,
6460 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6461 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
6463 (VINSERTF128rr VR256:$src1, VR128:$src2,
6464 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6466 //===----------------------------------------------------------------------===//
6467 // VEXTRACTF128 - Extract packed floating-point values
6469 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
6470 (ins VR256:$src1, i8imm:$src2),
6471 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6473 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
6474 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
6475 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6478 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
6479 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6480 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
6481 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6482 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
6483 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6485 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6486 (v4f32 (VEXTRACTF128rr
6487 (v8f32 VR256:$src1),
6488 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6489 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6490 (v2f64 (VEXTRACTF128rr
6491 (v4f64 VR256:$src1),
6492 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6493 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6494 (v4i32 (VEXTRACTF128rr
6495 (v8i32 VR256:$src1),
6496 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6497 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6498 (v2i64 (VEXTRACTF128rr
6499 (v4i64 VR256:$src1),
6500 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6501 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6502 (v8i16 (VEXTRACTF128rr
6503 (v16i16 VR256:$src1),
6504 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6505 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6506 (v16i8 (VEXTRACTF128rr
6507 (v32i8 VR256:$src1),
6508 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6510 //===----------------------------------------------------------------------===//
6511 // VMASKMOV - Conditional SIMD Packed Loads and Stores
6513 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
6514 Intrinsic IntLd, Intrinsic IntLd256,
6515 Intrinsic IntSt, Intrinsic IntSt256,
6516 PatFrag pf128, PatFrag pf256> {
6517 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
6518 (ins VR128:$src1, f128mem:$src2),
6519 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6520 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
6522 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
6523 (ins VR256:$src1, f256mem:$src2),
6524 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6525 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
6527 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
6528 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
6529 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6530 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
6531 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
6532 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
6533 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6534 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
6537 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
6538 int_x86_avx_maskload_ps,
6539 int_x86_avx_maskload_ps_256,
6540 int_x86_avx_maskstore_ps,
6541 int_x86_avx_maskstore_ps_256,
6542 memopv4f32, memopv8f32>;
6543 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
6544 int_x86_avx_maskload_pd,
6545 int_x86_avx_maskload_pd_256,
6546 int_x86_avx_maskstore_pd,
6547 int_x86_avx_maskstore_pd_256,
6548 memopv2f64, memopv4f64>;
6550 //===----------------------------------------------------------------------===//
6551 // VPERMIL - Permute Single and Double Floating-Point Values
6553 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
6554 RegisterClass RC, X86MemOperand x86memop_f,
6555 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
6556 Intrinsic IntVar, Intrinsic IntImm> {
6557 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
6558 (ins RC:$src1, RC:$src2),
6559 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6560 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
6561 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
6562 (ins RC:$src1, x86memop_i:$src2),
6563 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6564 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
6566 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
6567 (ins RC:$src1, i8imm:$src2),
6568 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6569 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
6570 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
6571 (ins x86memop_f:$src1, i8imm:$src2),
6572 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6573 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
6576 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
6577 memopv4f32, memopv4i32,
6578 int_x86_avx_vpermilvar_ps,
6579 int_x86_avx_vpermil_ps>;
6580 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
6581 memopv8f32, memopv8i32,
6582 int_x86_avx_vpermilvar_ps_256,
6583 int_x86_avx_vpermil_ps_256>;
6584 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
6585 memopv2f64, memopv2i64,
6586 int_x86_avx_vpermilvar_pd,
6587 int_x86_avx_vpermil_pd>;
6588 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
6589 memopv4f64, memopv4i64,
6590 int_x86_avx_vpermilvar_pd_256,
6591 int_x86_avx_vpermil_pd_256>;
6593 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6594 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6595 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6596 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6597 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6598 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6599 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6600 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6602 //===----------------------------------------------------------------------===//
6603 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
6605 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
6606 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
6607 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6609 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
6610 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
6611 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6614 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
6615 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6616 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
6617 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6618 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
6619 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6621 def : Pat<(int_x86_avx_vperm2f128_ps_256
6622 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
6623 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6624 def : Pat<(int_x86_avx_vperm2f128_pd_256
6625 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
6626 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6627 def : Pat<(int_x86_avx_vperm2f128_si_256
6628 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
6629 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6631 def : Pat<(v8f32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6632 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6633 def : Pat<(v8i32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6634 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6635 def : Pat<(v4i64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6636 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6637 def : Pat<(v4f64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6638 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6639 def : Pat<(v32i8 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6640 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6641 def : Pat<(v16i16 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6642 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6644 //===----------------------------------------------------------------------===//
6645 // VZERO - Zero YMM registers
6647 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
6648 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
6649 // Zero All YMM registers
6650 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
6651 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
6653 // Zero Upper bits of YMM registers
6654 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
6655 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;