1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // Non-instruction patterns
120 //===----------------------------------------------------------------------===//
122 // A vector extract of the first f32/f64 position is a subregister copy
123 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
124 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
125 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
126 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
128 // A 128-bit subvector extract from the first 256-bit vector position
129 // is a subregister copy that needs no instruction.
130 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
131 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
132 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
133 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
135 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
136 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
137 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
138 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
140 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
141 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
142 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
143 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
145 // A 128-bit subvector insert to the first 256-bit vector position
146 // is a subregister copy that needs no instruction.
147 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
148 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
149 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
150 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
151 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
152 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
153 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
154 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
155 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
156 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
157 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
158 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
160 // Implicitly promote a 32-bit scalar to a vector.
161 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
162 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
163 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
164 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
165 // Implicitly promote a 64-bit scalar to a vector.
166 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
167 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
168 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
169 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
171 // Bitcasts between 128-bit vector types. Return the original type since
172 // no instruction is needed for the conversion
173 let Predicates = [HasXMMInt] in {
174 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
175 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
176 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
177 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
178 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
179 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
180 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
181 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
182 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
183 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
184 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
185 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
186 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
187 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
188 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
189 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
190 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
191 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
192 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
193 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
194 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
195 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
196 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
197 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
198 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
199 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
200 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
201 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
202 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
203 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
206 // Bitcasts between 256-bit vector types. Return the original type since
207 // no instruction is needed for the conversion
208 let Predicates = [HasAVX] in {
209 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
210 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
211 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
212 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
213 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
214 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
215 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
216 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
217 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
218 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
219 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
220 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
221 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
222 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
223 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
224 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
225 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
226 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
227 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
228 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
229 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
230 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
231 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
232 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
233 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
234 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
235 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
236 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
237 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
238 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
241 // Alias instructions that map fld0 to pxor for sse.
242 // FIXME: Set encoding to pseudo!
243 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
244 canFoldAsLoad = 1 in {
245 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
246 [(set FR32:$dst, fp32imm0)]>,
247 Requires<[HasSSE1]>, TB, OpSize;
248 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
249 [(set FR64:$dst, fpimm0)]>,
250 Requires<[HasSSE2]>, TB, OpSize;
251 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
252 [(set FR32:$dst, fp32imm0)]>,
253 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
254 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
255 [(set FR64:$dst, fpimm0)]>,
256 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
259 //===----------------------------------------------------------------------===//
260 // AVX & SSE - Zero/One Vectors
261 //===----------------------------------------------------------------------===//
263 // Alias instruction that maps zero vector to pxor / xorp* for sse.
264 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
265 // swizzled by ExecutionDepsFix to pxor.
266 // We set canFoldAsLoad because this can be converted to a constant-pool
267 // load of an all-zeros value if folding it would be beneficial.
268 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
270 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
273 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
274 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
275 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
276 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
277 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
278 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
281 // The same as done above but for AVX. The 256-bit ISA does not support PI,
282 // and doesn't need it because on sandy bridge the register is set to zero
283 // at the rename stage without using any execution unit, so SET0PSY
284 // and SET0PDY can be used for vector int instructions without penalty
285 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
286 // JIT implementatioan, it does not expand the instructions below like
287 // X86MCInstLower does.
288 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
289 isCodeGenOnly = 1, Predicates = [HasAVX] in {
290 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
291 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
292 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
293 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
297 // AVX has no support for 256-bit integer instructions, but since the 128-bit
298 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
299 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
300 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
301 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
303 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
304 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
305 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
307 // We set canFoldAsLoad because this can be converted to a constant-pool
308 // load of an all-ones value if folding it would be beneficial.
309 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
310 // JIT implementation, it does not expand the instructions below like
311 // X86MCInstLower does.
312 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
313 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
314 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
315 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
316 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
317 isCodeGenOnly = 1, ExeDomain = SSEPackedInt, Predicates = [HasAVX] in
318 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
319 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
322 //===----------------------------------------------------------------------===//
323 // SSE 1 & 2 - Move FP Scalar Instructions
325 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
326 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
327 // is used instead. Register-to-register movss/movsd is not modeled as an
328 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
329 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
330 //===----------------------------------------------------------------------===//
332 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
333 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
334 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
336 // Loading from memory automatically zeroing upper bits.
337 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
338 PatFrag mem_pat, string OpcodeStr> :
339 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
340 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
341 [(set RC:$dst, (mem_pat addr:$src))]>;
344 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
345 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
346 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
347 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
349 // For the disassembler
350 let isCodeGenOnly = 1 in {
351 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
352 (ins VR128:$src1, FR32:$src2),
353 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
355 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
356 (ins VR128:$src1, FR64:$src2),
357 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
361 let canFoldAsLoad = 1, isReMaterializable = 1 in {
362 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
363 let AddedComplexity = 20 in
364 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
367 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
368 "movss\t{$src, $dst|$dst, $src}",
369 [(store FR32:$src, addr:$dst)]>, XS, VEX;
370 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
371 "movsd\t{$src, $dst|$dst, $src}",
372 [(store FR64:$src, addr:$dst)]>, XD, VEX;
375 let Constraints = "$src1 = $dst" in {
376 def MOVSSrr : sse12_move_rr<FR32, v4f32,
377 "movss\t{$src2, $dst|$dst, $src2}">, XS;
378 def MOVSDrr : sse12_move_rr<FR64, v2f64,
379 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
381 // For the disassembler
382 let isCodeGenOnly = 1 in {
383 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
384 (ins VR128:$src1, FR32:$src2),
385 "movss\t{$src2, $dst|$dst, $src2}", []>, XS;
386 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
387 (ins VR128:$src1, FR64:$src2),
388 "movsd\t{$src2, $dst|$dst, $src2}", []>, XD;
392 let canFoldAsLoad = 1, isReMaterializable = 1 in {
393 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
395 let AddedComplexity = 20 in
396 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
399 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
400 "movss\t{$src, $dst|$dst, $src}",
401 [(store FR32:$src, addr:$dst)]>;
402 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
403 "movsd\t{$src, $dst|$dst, $src}",
404 [(store FR64:$src, addr:$dst)]>;
407 let Predicates = [HasSSE1] in {
408 let AddedComplexity = 15 in {
409 // Extract the low 32-bit value from one vector and insert it into another.
410 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
411 (MOVSSrr (v4f32 VR128:$src1),
412 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
413 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
414 (MOVSSrr (v4i32 VR128:$src1),
415 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
417 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
418 // MOVSS to the lower bits.
419 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
420 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
421 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
422 (MOVSSrr (v4f32 (V_SET0)),
423 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
424 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
425 (MOVSSrr (v4i32 (V_SET0)),
426 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
429 let AddedComplexity = 20 in {
430 // MOVSSrm zeros the high parts of the register; represent this
431 // with SUBREG_TO_REG.
432 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
433 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
434 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
435 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
436 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
437 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
440 // Extract and store.
441 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
444 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
446 // Shuffle with MOVSS
447 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
448 (MOVSSrr VR128:$src1, FR32:$src2)>;
449 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
450 (MOVSSrr (v4i32 VR128:$src1),
451 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
452 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
453 (MOVSSrr (v4f32 VR128:$src1),
454 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
457 let Predicates = [HasSSE2] in {
458 let AddedComplexity = 15 in {
459 // Extract the low 64-bit value from one vector and insert it into another.
460 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
461 (MOVSDrr (v2f64 VR128:$src1),
462 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
463 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
464 (MOVSDrr (v2i64 VR128:$src1),
465 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
467 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
468 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
469 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
470 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
471 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
473 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
474 // MOVSD to the lower bits.
475 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
476 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
479 let AddedComplexity = 20 in {
480 // MOVSDrm zeros the high parts of the register; represent this
481 // with SUBREG_TO_REG.
482 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
483 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
484 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
485 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
486 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
487 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
488 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
489 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
490 def : Pat<(v2f64 (X86vzload addr:$src)),
491 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
494 // Extract and store.
495 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
498 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
500 // Shuffle with MOVSD
501 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
502 (MOVSDrr VR128:$src1, FR64:$src2)>;
503 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
504 (MOVSDrr (v2i64 VR128:$src1),
505 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
506 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
507 (MOVSDrr (v2f64 VR128:$src1),
508 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
509 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
510 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
511 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
512 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
514 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
515 // is during lowering, where it's not possible to recognize the fold cause
516 // it has two uses through a bitcast. One use disappears at isel time and the
517 // fold opportunity reappears.
518 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
519 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
520 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
521 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
524 let Predicates = [HasAVX] in {
525 let AddedComplexity = 15 in {
526 // Extract the low 32-bit value from one vector and insert it into another.
527 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
528 (VMOVSSrr (v4f32 VR128:$src1),
529 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
530 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
531 (VMOVSSrr (v4i32 VR128:$src1),
532 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
534 // Extract the low 64-bit value from one vector and insert it into another.
535 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
536 (VMOVSDrr (v2f64 VR128:$src1),
537 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
538 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
539 (VMOVSDrr (v2i64 VR128:$src1),
540 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
542 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
543 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
544 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
545 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
546 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>;
548 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
549 // MOVS{S,D} to the lower bits.
550 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
551 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
552 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
553 (VMOVSSrr (v4f32 (V_SET0)),
554 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
555 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
556 (VMOVSSrr (v4i32 (V_SET0)),
557 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
558 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
559 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
562 let AddedComplexity = 20 in {
563 // MOVSSrm zeros the high parts of the register; represent this
564 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
565 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
566 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
567 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
568 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
569 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
570 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
572 // MOVSDrm zeros the high parts of the register; represent this
573 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
574 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
575 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
576 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
577 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
578 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
579 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
580 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
581 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
582 def : Pat<(v2f64 (X86vzload addr:$src)),
583 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
585 // Represent the same patterns above but in the form they appear for
587 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
588 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
589 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
590 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
591 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
592 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
594 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
595 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
596 (SUBREG_TO_REG (i32 0),
597 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
599 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
600 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
601 (SUBREG_TO_REG (i64 0),
602 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
605 // Extract and store.
606 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
609 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
610 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
613 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
615 // Shuffle with VMOVSS
616 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
617 (VMOVSSrr VR128:$src1, FR32:$src2)>;
618 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
619 (VMOVSSrr (v4i32 VR128:$src1),
620 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
621 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
622 (VMOVSSrr (v4f32 VR128:$src1),
623 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
625 // Shuffle with VMOVSD
626 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
627 (VMOVSDrr VR128:$src1, FR64:$src2)>;
628 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
629 (VMOVSDrr (v2i64 VR128:$src1),
630 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
631 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
632 (VMOVSDrr (v2f64 VR128:$src1),
633 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
634 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
635 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
637 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
638 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
641 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
642 // is during lowering, where it's not possible to recognize the fold cause
643 // it has two uses through a bitcast. One use disappears at isel time and the
644 // fold opportunity reappears.
645 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
646 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
648 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
649 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
653 //===----------------------------------------------------------------------===//
654 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
655 //===----------------------------------------------------------------------===//
657 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
658 X86MemOperand x86memop, PatFrag ld_frag,
659 string asm, Domain d,
660 bit IsReMaterializable = 1> {
661 let neverHasSideEffects = 1 in
662 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
663 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
664 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
665 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
666 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
667 [(set RC:$dst, (ld_frag addr:$src))], d>;
670 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
671 "movaps", SSEPackedSingle>, TB, VEX;
672 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
673 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
674 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
675 "movups", SSEPackedSingle>, TB, VEX;
676 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
677 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
679 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
680 "movaps", SSEPackedSingle>, TB, VEX;
681 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
682 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
683 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
684 "movups", SSEPackedSingle>, TB, VEX;
685 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
686 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
687 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
688 "movaps", SSEPackedSingle>, TB;
689 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
690 "movapd", SSEPackedDouble>, TB, OpSize;
691 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
692 "movups", SSEPackedSingle>, TB;
693 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
694 "movupd", SSEPackedDouble, 0>, TB, OpSize;
696 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
697 "movaps\t{$src, $dst|$dst, $src}",
698 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
699 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
700 "movapd\t{$src, $dst|$dst, $src}",
701 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
702 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
703 "movups\t{$src, $dst|$dst, $src}",
704 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
705 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
706 "movupd\t{$src, $dst|$dst, $src}",
707 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
708 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
709 "movaps\t{$src, $dst|$dst, $src}",
710 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)]>, VEX;
711 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
712 "movapd\t{$src, $dst|$dst, $src}",
713 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)]>, VEX;
714 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
715 "movups\t{$src, $dst|$dst, $src}",
716 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
717 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
718 "movupd\t{$src, $dst|$dst, $src}",
719 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
722 let isCodeGenOnly = 1 in {
723 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
725 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
726 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
728 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
729 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
731 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
732 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
734 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
735 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
737 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
738 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
740 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
741 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
743 "movups\t{$src, $dst|$dst, $src}", []>, VEX;
744 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
746 "movupd\t{$src, $dst|$dst, $src}", []>, VEX;
749 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
750 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
751 (VMOVUPSYmr addr:$dst, VR256:$src)>;
753 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
754 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
755 (VMOVUPDYmr addr:$dst, VR256:$src)>;
757 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
758 "movaps\t{$src, $dst|$dst, $src}",
759 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
760 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
761 "movapd\t{$src, $dst|$dst, $src}",
762 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
763 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
764 "movups\t{$src, $dst|$dst, $src}",
765 [(store (v4f32 VR128:$src), addr:$dst)]>;
766 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
767 "movupd\t{$src, $dst|$dst, $src}",
768 [(store (v2f64 VR128:$src), addr:$dst)]>;
771 let isCodeGenOnly = 1 in {
772 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
773 "movaps\t{$src, $dst|$dst, $src}", []>;
774 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
775 "movapd\t{$src, $dst|$dst, $src}", []>;
776 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
777 "movups\t{$src, $dst|$dst, $src}", []>;
778 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
779 "movupd\t{$src, $dst|$dst, $src}", []>;
782 let Predicates = [HasAVX] in {
783 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
784 (VMOVUPSmr addr:$dst, VR128:$src)>;
785 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
786 (VMOVUPDmr addr:$dst, VR128:$src)>;
789 let Predicates = [HasSSE1] in
790 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
791 (MOVUPSmr addr:$dst, VR128:$src)>;
792 let Predicates = [HasSSE2] in
793 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
794 (MOVUPDmr addr:$dst, VR128:$src)>;
796 // Use movaps / movups for SSE integer load / store (one byte shorter).
797 // The instructions selected below are then converted to MOVDQA/MOVDQU
798 // during the SSE domain pass.
799 let Predicates = [HasSSE1] in {
800 def : Pat<(alignedloadv4i32 addr:$src),
801 (MOVAPSrm addr:$src)>;
802 def : Pat<(loadv4i32 addr:$src),
803 (MOVUPSrm addr:$src)>;
804 def : Pat<(alignedloadv2i64 addr:$src),
805 (MOVAPSrm addr:$src)>;
806 def : Pat<(loadv2i64 addr:$src),
807 (MOVUPSrm addr:$src)>;
809 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
810 (MOVAPSmr addr:$dst, VR128:$src)>;
811 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
812 (MOVAPSmr addr:$dst, VR128:$src)>;
813 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
814 (MOVAPSmr addr:$dst, VR128:$src)>;
815 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
816 (MOVAPSmr addr:$dst, VR128:$src)>;
817 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
818 (MOVUPSmr addr:$dst, VR128:$src)>;
819 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
820 (MOVUPSmr addr:$dst, VR128:$src)>;
821 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
822 (MOVUPSmr addr:$dst, VR128:$src)>;
823 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
824 (MOVUPSmr addr:$dst, VR128:$src)>;
827 // Use vmovaps/vmovups for AVX integer load/store.
828 let Predicates = [HasAVX] in {
829 // 128-bit load/store
830 def : Pat<(alignedloadv4i32 addr:$src),
831 (VMOVAPSrm addr:$src)>;
832 def : Pat<(loadv4i32 addr:$src),
833 (VMOVUPSrm addr:$src)>;
834 def : Pat<(alignedloadv2i64 addr:$src),
835 (VMOVAPSrm addr:$src)>;
836 def : Pat<(loadv2i64 addr:$src),
837 (VMOVUPSrm addr:$src)>;
839 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
840 (VMOVAPSmr addr:$dst, VR128:$src)>;
841 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
842 (VMOVAPSmr addr:$dst, VR128:$src)>;
843 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
844 (VMOVAPSmr addr:$dst, VR128:$src)>;
845 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
846 (VMOVAPSmr addr:$dst, VR128:$src)>;
847 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
848 (VMOVUPSmr addr:$dst, VR128:$src)>;
849 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
850 (VMOVUPSmr addr:$dst, VR128:$src)>;
851 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
852 (VMOVUPSmr addr:$dst, VR128:$src)>;
853 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
854 (VMOVUPSmr addr:$dst, VR128:$src)>;
856 // 256-bit load/store
857 def : Pat<(alignedloadv4i64 addr:$src),
858 (VMOVAPSYrm addr:$src)>;
859 def : Pat<(loadv4i64 addr:$src),
860 (VMOVUPSYrm addr:$src)>;
861 def : Pat<(alignedloadv8i32 addr:$src),
862 (VMOVAPSYrm addr:$src)>;
863 def : Pat<(loadv8i32 addr:$src),
864 (VMOVUPSYrm addr:$src)>;
865 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
866 (VMOVAPSYmr addr:$dst, VR256:$src)>;
867 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
868 (VMOVAPSYmr addr:$dst, VR256:$src)>;
869 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
870 (VMOVAPSYmr addr:$dst, VR256:$src)>;
871 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
872 (VMOVAPSYmr addr:$dst, VR256:$src)>;
873 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
874 (VMOVUPSYmr addr:$dst, VR256:$src)>;
875 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
876 (VMOVUPSYmr addr:$dst, VR256:$src)>;
877 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
878 (VMOVUPSYmr addr:$dst, VR256:$src)>;
879 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
880 (VMOVUPSYmr addr:$dst, VR256:$src)>;
883 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
884 // bits are disregarded. FIXME: Set encoding to pseudo!
885 let neverHasSideEffects = 1 in {
886 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
887 "movaps\t{$src, $dst|$dst, $src}", []>;
888 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
889 "movapd\t{$src, $dst|$dst, $src}", []>;
890 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
891 "movaps\t{$src, $dst|$dst, $src}", []>, VEX;
892 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
893 "movapd\t{$src, $dst|$dst, $src}", []>, VEX;
896 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
897 // bits are disregarded. FIXME: Set encoding to pseudo!
898 let canFoldAsLoad = 1, isReMaterializable = 1 in {
899 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
900 "movaps\t{$src, $dst|$dst, $src}",
901 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
902 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
903 "movapd\t{$src, $dst|$dst, $src}",
904 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
905 let isCodeGenOnly = 1 in {
906 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
907 "movaps\t{$src, $dst|$dst, $src}",
908 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>, VEX;
909 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
910 "movapd\t{$src, $dst|$dst, $src}",
911 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>, VEX;
915 //===----------------------------------------------------------------------===//
916 // SSE 1 & 2 - Move Low packed FP Instructions
917 //===----------------------------------------------------------------------===//
919 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
920 PatFrag mov_frag, string base_opc,
922 def PSrm : PI<opc, MRMSrcMem,
923 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
924 !strconcat(base_opc, "s", asm_opr),
927 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
928 SSEPackedSingle>, TB;
930 def PDrm : PI<opc, MRMSrcMem,
931 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
932 !strconcat(base_opc, "d", asm_opr),
933 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
934 (scalar_to_vector (loadf64 addr:$src2)))))],
935 SSEPackedDouble>, TB, OpSize;
938 let AddedComplexity = 20 in {
939 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
940 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
942 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
943 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
944 "\t{$src2, $dst|$dst, $src2}">;
947 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
948 "movlps\t{$src, $dst|$dst, $src}",
949 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
950 (iPTR 0))), addr:$dst)]>, VEX;
951 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
952 "movlpd\t{$src, $dst|$dst, $src}",
953 [(store (f64 (vector_extract (v2f64 VR128:$src),
954 (iPTR 0))), addr:$dst)]>, VEX;
955 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
956 "movlps\t{$src, $dst|$dst, $src}",
957 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
958 (iPTR 0))), addr:$dst)]>;
959 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
960 "movlpd\t{$src, $dst|$dst, $src}",
961 [(store (f64 (vector_extract (v2f64 VR128:$src),
962 (iPTR 0))), addr:$dst)]>;
964 let Predicates = [HasAVX] in {
965 let AddedComplexity = 20 in {
966 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
967 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
968 (VMOVLPSrm VR128:$src1, addr:$src2)>;
969 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
970 (VMOVLPSrm VR128:$src1, addr:$src2)>;
971 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
972 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
973 (VMOVLPDrm VR128:$src1, addr:$src2)>;
974 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
975 (VMOVLPDrm VR128:$src1, addr:$src2)>;
978 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
979 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
980 (VMOVLPSmr addr:$src1, VR128:$src2)>;
981 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
982 VR128:$src2)), addr:$src1),
983 (VMOVLPSmr addr:$src1, VR128:$src2)>;
985 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
986 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
987 (VMOVLPDmr addr:$src1, VR128:$src2)>;
988 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
989 (VMOVLPDmr addr:$src1, VR128:$src2)>;
991 // Shuffle with VMOVLPS
992 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
993 (VMOVLPSrm VR128:$src1, addr:$src2)>;
994 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
995 (VMOVLPSrm VR128:$src1, addr:$src2)>;
996 def : Pat<(X86Movlps VR128:$src1,
997 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
998 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1000 // Shuffle with VMOVLPD
1001 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1002 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1003 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1004 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1005 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1006 (scalar_to_vector (loadf64 addr:$src2)))),
1007 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1010 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1012 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1013 def : Pat<(store (v4i32 (X86Movlps
1014 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1015 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1016 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1018 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1019 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1021 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1024 let Predicates = [HasSSE1] in {
1025 let AddedComplexity = 20 in {
1026 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1027 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
1028 (MOVLPSrm VR128:$src1, addr:$src2)>;
1029 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
1030 (MOVLPSrm VR128:$src1, addr:$src2)>;
1033 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1034 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1035 (MOVLPSmr addr:$src1, VR128:$src2)>;
1036 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)),
1037 VR128:$src2)), addr:$src1),
1038 (MOVLPSmr addr:$src1, VR128:$src2)>;
1040 // Shuffle with MOVLPS
1041 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1042 (MOVLPSrm VR128:$src1, addr:$src2)>;
1043 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1044 (MOVLPSrm VR128:$src1, addr:$src2)>;
1045 def : Pat<(X86Movlps VR128:$src1,
1046 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1047 (MOVLPSrm VR128:$src1, addr:$src2)>;
1050 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1052 (MOVLPSmr addr:$src1, VR128:$src2)>;
1053 def : Pat<(store (v4i32 (X86Movlps
1054 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1056 (MOVLPSmr addr:$src1, VR128:$src2)>;
1059 let Predicates = [HasSSE2] in {
1060 let AddedComplexity = 20 in {
1061 // vector_shuffle v1, (load v2) <2, 1> using MOVLPS
1062 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
1063 (MOVLPDrm VR128:$src1, addr:$src2)>;
1064 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
1065 (MOVLPDrm VR128:$src1, addr:$src2)>;
1068 // (store (vector_shuffle (load addr), v2, <2, 1>), addr) using MOVLPS
1069 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1070 (MOVLPDmr addr:$src1, VR128:$src2)>;
1071 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
1072 (MOVLPDmr addr:$src1, VR128:$src2)>;
1074 // Shuffle with MOVLPD
1075 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1076 (MOVLPDrm VR128:$src1, addr:$src2)>;
1077 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1078 (MOVLPDrm VR128:$src1, addr:$src2)>;
1079 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
1080 (scalar_to_vector (loadf64 addr:$src2)))),
1081 (MOVLPDrm VR128:$src1, addr:$src2)>;
1084 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1086 (MOVLPDmr addr:$src1, VR128:$src2)>;
1087 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1089 (MOVLPDmr addr:$src1, VR128:$src2)>;
1092 //===----------------------------------------------------------------------===//
1093 // SSE 1 & 2 - Move Hi packed FP Instructions
1094 //===----------------------------------------------------------------------===//
1096 let AddedComplexity = 20 in {
1097 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1098 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1100 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1101 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
1102 "\t{$src2, $dst|$dst, $src2}">;
1105 // v2f64 extract element 1 is always custom lowered to unpack high to low
1106 // and extract element 0 so the non-store version isn't too horrible.
1107 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1108 "movhps\t{$src, $dst|$dst, $src}",
1109 [(store (f64 (vector_extract
1110 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1111 (undef)), (iPTR 0))), addr:$dst)]>,
1113 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1114 "movhpd\t{$src, $dst|$dst, $src}",
1115 [(store (f64 (vector_extract
1116 (v2f64 (unpckh VR128:$src, (undef))),
1117 (iPTR 0))), addr:$dst)]>,
1119 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1120 "movhps\t{$src, $dst|$dst, $src}",
1121 [(store (f64 (vector_extract
1122 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
1123 (undef)), (iPTR 0))), addr:$dst)]>;
1124 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1125 "movhpd\t{$src, $dst|$dst, $src}",
1126 [(store (f64 (vector_extract
1127 (v2f64 (unpckh VR128:$src, (undef))),
1128 (iPTR 0))), addr:$dst)]>;
1130 let Predicates = [HasAVX] in {
1132 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1133 (VMOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1134 def : Pat<(X86Movlhps VR128:$src1,
1135 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1136 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1137 def : Pat<(X86Movlhps VR128:$src1,
1138 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1139 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1141 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1142 // is during lowering, where it's not possible to recognize the load fold cause
1143 // it has two uses through a bitcast. One use disappears at isel time and the
1144 // fold opportunity reappears.
1145 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1146 (scalar_to_vector (loadf64 addr:$src2)))),
1147 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1149 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1150 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1151 (scalar_to_vector (loadf64 addr:$src2)))),
1152 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1155 def : Pat<(store (f64 (vector_extract
1156 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1157 (VMOVHPSmr addr:$dst, VR128:$src)>;
1158 def : Pat<(store (f64 (vector_extract
1159 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1160 (VMOVHPDmr addr:$dst, VR128:$src)>;
1163 let Predicates = [HasSSE1] in {
1165 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1166 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
1167 def : Pat<(X86Movlhps VR128:$src1,
1168 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1169 (MOVHPSrm VR128:$src1, addr:$src2)>;
1170 def : Pat<(X86Movlhps VR128:$src1,
1171 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1172 (MOVHPSrm VR128:$src1, addr:$src2)>;
1175 def : Pat<(store (f64 (vector_extract
1176 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))), addr:$dst),
1177 (MOVHPSmr addr:$dst, VR128:$src)>;
1180 let Predicates = [HasSSE2] in {
1181 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
1182 // is during lowering, where it's not possible to recognize the load fold cause
1183 // it has two uses through a bitcast. One use disappears at isel time and the
1184 // fold opportunity reappears.
1185 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
1186 (scalar_to_vector (loadf64 addr:$src2)))),
1187 (MOVHPDrm VR128:$src1, addr:$src2)>;
1189 // FIXME: This should be matched by a X86Movhpd instead. Same as above
1190 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
1191 (scalar_to_vector (loadf64 addr:$src2)))),
1192 (MOVHPDrm VR128:$src1, addr:$src2)>;
1195 def : Pat<(store (f64 (vector_extract
1196 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
1197 (MOVHPDmr addr:$dst, VR128:$src)>;
1200 //===----------------------------------------------------------------------===//
1201 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1202 //===----------------------------------------------------------------------===//
1204 let AddedComplexity = 20 in {
1205 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1206 (ins VR128:$src1, VR128:$src2),
1207 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1209 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
1211 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1212 (ins VR128:$src1, VR128:$src2),
1213 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1215 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
1218 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1219 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1220 (ins VR128:$src1, VR128:$src2),
1221 "movlhps\t{$src2, $dst|$dst, $src2}",
1223 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
1224 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1225 (ins VR128:$src1, VR128:$src2),
1226 "movhlps\t{$src2, $dst|$dst, $src2}",
1228 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
1231 let Predicates = [HasAVX] in {
1233 let AddedComplexity = 20 in {
1234 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1235 (VMOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1236 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1237 (VMOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1239 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1240 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1241 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1243 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1244 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1245 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1246 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1247 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1248 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1251 let AddedComplexity = 20 in {
1252 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1253 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1254 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1256 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1257 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1258 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1259 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1260 (VMOVHLPSrr VR128:$src1, VR128:$src1)>;
1263 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1264 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1265 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1266 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1269 let Predicates = [HasSSE1] in {
1271 let AddedComplexity = 20 in {
1272 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1273 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1274 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1275 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1277 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1278 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
1279 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1281 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
1282 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1283 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1284 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1285 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1286 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1289 let AddedComplexity = 20 in {
1290 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1291 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
1292 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1294 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1295 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
1296 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1297 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
1298 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1301 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
1302 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1303 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1304 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1307 //===----------------------------------------------------------------------===//
1308 // SSE 1 & 2 - Conversion Instructions
1309 //===----------------------------------------------------------------------===//
1311 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1312 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1314 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1315 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
1316 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1317 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
1320 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1321 X86MemOperand x86memop, string asm> {
1322 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, []>;
1324 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, []>;
1327 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1328 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1329 string asm, Domain d> {
1330 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1331 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
1332 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1333 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
1336 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1337 X86MemOperand x86memop, string asm> {
1338 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1339 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1341 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1342 (ins DstRC:$src1, x86memop:$src),
1343 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1346 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1347 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
1348 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1349 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1351 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1352 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
1353 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1354 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
1357 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1358 // register, but the same isn't true when only using memory operands,
1359 // provide other assembly "l" and "q" forms to address this explicitly
1360 // where appropriate to do so.
1361 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
1363 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
1365 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
1367 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
1369 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
1372 let Predicates = [HasAVX] in {
1373 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1374 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1375 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1376 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1377 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1378 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1379 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1380 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1382 def : Pat<(f32 (sint_to_fp GR32:$src)),
1383 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1384 def : Pat<(f32 (sint_to_fp GR64:$src)),
1385 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1386 def : Pat<(f64 (sint_to_fp GR32:$src)),
1387 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1388 def : Pat<(f64 (sint_to_fp GR64:$src)),
1389 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1392 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1393 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
1394 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1395 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1396 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1397 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
1398 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1399 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1400 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1401 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
1402 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1403 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1404 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1405 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
1406 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1407 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
1409 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1410 // and/or XMM operand(s).
1412 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1413 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1415 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1416 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1417 [(set DstRC:$dst, (Int SrcRC:$src))]>;
1418 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1419 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1420 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
1423 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1424 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1425 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
1426 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1428 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1429 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1430 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
1431 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1432 (ins DstRC:$src1, x86memop:$src2),
1434 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1435 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1436 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
1439 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1440 f128mem, load, "cvtsd2si">, XD, VEX;
1441 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1442 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
1445 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
1446 // Get rid of this hack or rename the intrinsics, there are several
1447 // intructions that only match with the intrinsic form, why create duplicates
1448 // to let them be recognized by the assembler?
1449 defm VCVTSD2SI : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
1450 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
1451 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
1452 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
1454 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1455 f128mem, load, "cvtsd2si{l}">, XD;
1456 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1457 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
1460 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1461 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
1462 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1463 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
1465 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1466 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
1467 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1468 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
1471 let Constraints = "$src1 = $dst" in {
1472 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1473 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1475 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1476 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1477 "cvtsi2ss{q}">, XS, REX_W;
1478 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1479 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1481 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1482 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1483 "cvtsi2sd">, XD, REX_W;
1488 // Aliases for intrinsics
1489 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1490 f32mem, load, "cvttss2si">, XS, VEX;
1491 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1492 int_x86_sse_cvttss2si64, f32mem, load,
1493 "cvttss2si">, XS, VEX, VEX_W;
1494 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1495 f128mem, load, "cvttsd2si">, XD, VEX;
1496 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1497 int_x86_sse2_cvttsd2si64, f128mem, load,
1498 "cvttsd2si">, XD, VEX, VEX_W;
1499 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1500 f32mem, load, "cvttss2si">, XS;
1501 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1502 int_x86_sse_cvttss2si64, f32mem, load,
1503 "cvttss2si{q}">, XS, REX_W;
1504 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1505 f128mem, load, "cvttsd2si">, XD;
1506 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1507 int_x86_sse2_cvttsd2si64, f128mem, load,
1508 "cvttsd2si{q}">, XD, REX_W;
1510 let Pattern = []<dag> in {
1511 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1512 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
1513 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1514 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
1516 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1517 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1518 SSEPackedSingle>, TB, VEX;
1519 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1520 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1521 SSEPackedSingle>, TB, VEX;
1524 let Pattern = []<dag> in {
1525 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1526 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
1527 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1528 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
1529 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1530 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1531 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
1534 let Predicates = [HasSSE1] in {
1535 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1536 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1537 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1538 (CVTSS2SIrm addr:$src)>;
1539 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1540 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1541 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1542 (CVTSS2SI64rm addr:$src)>;
1545 let Predicates = [HasAVX] in {
1546 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1547 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1548 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1549 (VCVTSS2SIrm addr:$src)>;
1550 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1551 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1552 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1553 (VCVTSS2SI64rm addr:$src)>;
1558 // Convert scalar double to scalar single
1559 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1560 (ins FR64:$src1, FR64:$src2),
1561 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
1564 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1565 (ins FR64:$src1, f64mem:$src2),
1566 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1567 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
1569 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1572 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1573 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1574 [(set FR32:$dst, (fround FR64:$src))]>;
1575 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1576 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1577 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1578 Requires<[HasSSE2, OptForSize]>;
1580 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1581 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
1583 let Constraints = "$src1 = $dst" in
1584 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1585 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
1587 // Convert scalar single to scalar double
1588 // SSE2 instructions with XS prefix
1589 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1590 (ins FR32:$src1, FR32:$src2),
1591 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1592 []>, XS, Requires<[HasAVX]>, VEX_4V;
1594 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1595 (ins FR32:$src1, f32mem:$src2),
1596 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1597 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
1599 let Predicates = [HasAVX] in {
1600 def : Pat<(f64 (fextend FR32:$src)),
1601 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1602 def : Pat<(fextend (loadf32 addr:$src)),
1603 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1604 def : Pat<(extloadf32 addr:$src),
1605 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1608 def : Pat<(extloadf32 addr:$src),
1609 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1610 Requires<[HasAVX, OptForSpeed]>;
1612 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1613 "cvtss2sd\t{$src, $dst|$dst, $src}",
1614 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1615 Requires<[HasSSE2]>;
1616 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1617 "cvtss2sd\t{$src, $dst|$dst, $src}",
1618 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1619 Requires<[HasSSE2, OptForSize]>;
1621 // extload f32 -> f64. This matches load+fextend because we have a hack in
1622 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1624 // Since these loads aren't folded into the fextend, we have to match it
1626 def : Pat<(fextend (loadf32 addr:$src)),
1627 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1628 def : Pat<(extloadf32 addr:$src),
1629 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1631 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1632 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1633 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1634 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1635 VR128:$src2))]>, XS, VEX_4V,
1637 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1638 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1639 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1640 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1641 (load addr:$src2)))]>, XS, VEX_4V,
1643 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1644 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1645 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1646 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1647 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1648 VR128:$src2))]>, XS,
1649 Requires<[HasSSE2]>;
1650 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1651 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1652 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1653 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1654 (load addr:$src2)))]>, XS,
1655 Requires<[HasSSE2]>;
1658 // Convert doubleword to packed single/double fp
1659 // SSE2 instructions without OpSize prefix
1660 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1661 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1662 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1663 TB, VEX, Requires<[HasAVX]>;
1664 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1665 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1666 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1667 (bitconvert (memopv2i64 addr:$src))))]>,
1668 TB, VEX, Requires<[HasAVX]>;
1669 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1670 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1671 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1672 TB, Requires<[HasSSE2]>;
1673 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1674 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1675 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1676 (bitconvert (memopv2i64 addr:$src))))]>,
1677 TB, Requires<[HasSSE2]>;
1679 // FIXME: why the non-intrinsic version is described as SSE3?
1680 // SSE2 instructions with XS prefix
1681 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1682 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1683 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1684 XS, VEX, Requires<[HasAVX]>;
1685 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1686 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1687 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1688 (bitconvert (memopv2i64 addr:$src))))]>,
1689 XS, VEX, Requires<[HasAVX]>;
1690 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1691 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1692 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1693 XS, Requires<[HasSSE2]>;
1694 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1695 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1696 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1697 (bitconvert (memopv2i64 addr:$src))))]>,
1698 XS, Requires<[HasSSE2]>;
1701 // Convert packed single/double fp to doubleword
1702 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1703 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1704 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1705 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1706 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1707 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1708 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1709 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1710 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1711 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1712 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1713 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1715 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1716 "cvtps2dq\t{$src, $dst|$dst, $src}",
1717 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1719 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1721 "cvtps2dq\t{$src, $dst|$dst, $src}",
1722 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1723 (memop addr:$src)))]>, VEX;
1724 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1725 "cvtps2dq\t{$src, $dst|$dst, $src}",
1726 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1727 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1728 "cvtps2dq\t{$src, $dst|$dst, $src}",
1729 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1730 (memop addr:$src)))]>;
1732 // SSE2 packed instructions with XD prefix
1733 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1734 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1735 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1736 XD, VEX, Requires<[HasAVX]>;
1737 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1738 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1739 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1740 (memop addr:$src)))]>,
1741 XD, VEX, Requires<[HasAVX]>;
1742 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1743 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1744 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1745 XD, Requires<[HasSSE2]>;
1746 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1747 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1748 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1749 (memop addr:$src)))]>,
1750 XD, Requires<[HasSSE2]>;
1753 // Convert with truncation packed single/double fp to doubleword
1754 // SSE2 packed instructions with XS prefix
1755 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1756 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1758 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1759 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1760 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1761 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1763 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1764 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1765 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1766 "cvttps2dq\t{$src, $dst|$dst, $src}",
1768 (int_x86_sse2_cvttps2dq VR128:$src))]>;
1769 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1770 "cvttps2dq\t{$src, $dst|$dst, $src}",
1772 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
1774 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1775 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1777 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1778 XS, VEX, Requires<[HasAVX]>;
1779 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1780 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1781 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1782 (memop addr:$src)))]>,
1783 XS, VEX, Requires<[HasAVX]>;
1785 let Predicates = [HasSSE2] in {
1786 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1787 (Int_CVTDQ2PSrr VR128:$src)>;
1788 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1789 (CVTTPS2DQrr VR128:$src)>;
1792 let Predicates = [HasAVX] in {
1793 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1794 (Int_VCVTDQ2PSrr VR128:$src)>;
1795 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1796 (VCVTTPS2DQrr VR128:$src)>;
1797 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1798 (VCVTDQ2PSYrr VR256:$src)>;
1799 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1800 (VCVTTPS2DQYrr VR256:$src)>;
1803 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1804 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1806 (int_x86_sse2_cvttpd2dq VR128:$src))]>, VEX;
1807 let isCodeGenOnly = 1 in
1808 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1809 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1810 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1811 (memop addr:$src)))]>, VEX;
1812 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1813 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1814 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1815 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1816 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1817 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1818 (memop addr:$src)))]>;
1820 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1821 // register, but the same isn't true when using memory operands instead.
1822 // Provide other assembly rr and rm forms to address this explicitly.
1823 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1824 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1827 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1828 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1829 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1830 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1833 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1834 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1835 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1836 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1838 // Convert packed single to packed double
1839 let Predicates = [HasAVX] in {
1840 // SSE2 instructions without OpSize prefix
1841 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1842 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1843 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1844 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1845 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1846 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1847 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1848 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, TB, VEX;
1850 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1851 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1852 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1853 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1855 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1856 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1857 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1858 TB, VEX, Requires<[HasAVX]>;
1859 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1860 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1861 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1862 (load addr:$src)))]>,
1863 TB, VEX, Requires<[HasAVX]>;
1864 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1865 "cvtps2pd\t{$src, $dst|$dst, $src}",
1866 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1867 TB, Requires<[HasSSE2]>;
1868 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1869 "cvtps2pd\t{$src, $dst|$dst, $src}",
1870 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1871 (load addr:$src)))]>,
1872 TB, Requires<[HasSSE2]>;
1874 // Convert packed double to packed single
1875 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1876 // register, but the same isn't true when using memory operands instead.
1877 // Provide other assembly rr and rm forms to address this explicitly.
1878 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1879 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1880 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1881 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1884 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1885 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1886 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1887 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1890 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1891 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1892 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1893 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1894 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1895 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1896 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1897 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1900 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1901 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1902 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1903 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1905 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1906 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1907 (memop addr:$src)))]>;
1908 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1909 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1910 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1911 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1912 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1913 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1914 (memop addr:$src)))]>;
1916 // AVX 256-bit register conversion intrinsics
1917 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1918 // whenever possible to avoid declaring two versions of each one.
1919 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1920 (VCVTDQ2PSYrr VR256:$src)>;
1921 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1922 (VCVTDQ2PSYrm addr:$src)>;
1924 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1925 (VCVTPD2PSYrr VR256:$src)>;
1926 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1927 (VCVTPD2PSYrm addr:$src)>;
1929 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1930 (VCVTPS2DQYrr VR256:$src)>;
1931 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1932 (VCVTPS2DQYrm addr:$src)>;
1934 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1935 (VCVTPS2PDYrr VR128:$src)>;
1936 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1937 (VCVTPS2PDYrm addr:$src)>;
1939 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1940 (VCVTTPD2DQYrr VR256:$src)>;
1941 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1942 (VCVTTPD2DQYrm addr:$src)>;
1944 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1945 (VCVTTPS2DQYrr VR256:$src)>;
1946 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1947 (VCVTTPS2DQYrm addr:$src)>;
1949 // Match fround and fextend for 128/256-bit conversions
1950 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
1951 (VCVTPD2PSYrr VR256:$src)>;
1952 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
1953 (VCVTPD2PSYrm addr:$src)>;
1955 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
1956 (VCVTPS2PDYrr VR128:$src)>;
1957 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
1958 (VCVTPS2PDYrm addr:$src)>;
1960 //===----------------------------------------------------------------------===//
1961 // SSE 1 & 2 - Compare Instructions
1962 //===----------------------------------------------------------------------===//
1964 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1965 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1966 SDNode OpNode, ValueType VT, PatFrag ld_frag,
1967 string asm, string asm_alt> {
1968 def rr : SIi8<0xC2, MRMSrcReg,
1969 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
1970 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))]>;
1971 def rm : SIi8<0xC2, MRMSrcMem,
1972 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, SSECC:$cc), asm,
1973 [(set RC:$dst, (OpNode (VT RC:$src1),
1974 (ld_frag addr:$src2), imm:$cc))]>;
1976 // Accept explicit immediate argument form instead of comparison code.
1977 let neverHasSideEffects = 1 in {
1978 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
1979 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, []>;
1981 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
1982 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, []>;
1986 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
1987 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1988 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1990 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
1991 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1992 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1995 let Constraints = "$src1 = $dst" in {
1996 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, X86cmpss, f32, loadf32,
1997 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1998 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2000 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, X86cmpsd, f64, loadf64,
2001 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2002 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}">,
2006 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
2007 Intrinsic Int, string asm> {
2008 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2009 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
2010 [(set VR128:$dst, (Int VR128:$src1,
2011 VR128:$src, imm:$cc))]>;
2012 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2013 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
2014 [(set VR128:$dst, (Int VR128:$src1,
2015 (load addr:$src), imm:$cc))]>;
2018 // Aliases to match intrinsics which expect XMM operand(s).
2019 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2020 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
2022 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2023 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
2025 let Constraints = "$src1 = $dst" in {
2026 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
2027 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
2028 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
2029 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
2033 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2034 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2035 ValueType vt, X86MemOperand x86memop,
2036 PatFrag ld_frag, string OpcodeStr, Domain d> {
2037 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2038 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2039 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
2040 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2041 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2042 [(set EFLAGS, (OpNode (vt RC:$src1),
2043 (ld_frag addr:$src2)))], d>;
2046 let Defs = [EFLAGS] in {
2047 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2048 "ucomiss", SSEPackedSingle>, TB, VEX;
2049 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2050 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2051 let Pattern = []<dag> in {
2052 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2053 "comiss", SSEPackedSingle>, TB, VEX;
2054 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2055 "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2058 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2059 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2060 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2061 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2063 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2064 load, "comiss", SSEPackedSingle>, TB, VEX;
2065 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2066 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2067 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2068 "ucomiss", SSEPackedSingle>, TB;
2069 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2070 "ucomisd", SSEPackedDouble>, TB, OpSize;
2072 let Pattern = []<dag> in {
2073 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2074 "comiss", SSEPackedSingle>, TB;
2075 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2076 "comisd", SSEPackedDouble>, TB, OpSize;
2079 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2080 load, "ucomiss", SSEPackedSingle>, TB;
2081 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2082 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2084 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2085 "comiss", SSEPackedSingle>, TB;
2086 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2087 "comisd", SSEPackedDouble>, TB, OpSize;
2088 } // Defs = [EFLAGS]
2090 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
2091 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2092 Intrinsic Int, string asm, string asm_alt,
2094 let isAsmParserOnly = 1 in {
2095 def rri : PIi8<0xC2, MRMSrcReg,
2096 (outs RC:$dst), (ins RC:$src1, RC:$src2, SSECC:$cc), asm,
2097 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))], d>;
2098 def rmi : PIi8<0xC2, MRMSrcMem,
2099 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, SSECC:$cc), asm,
2100 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))], d>;
2103 // Accept explicit immediate argument form instead of comparison code.
2104 def rri_alt : PIi8<0xC2, MRMSrcReg,
2105 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2107 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2108 (outs RC:$dst), (ins RC:$src1, f128mem:$src2, i8imm:$cc),
2112 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2113 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2114 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2115 SSEPackedSingle>, TB, VEX_4V;
2116 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2117 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2118 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2119 SSEPackedDouble>, TB, OpSize, VEX_4V;
2120 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
2121 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2122 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2123 SSEPackedSingle>, TB, VEX_4V;
2124 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
2125 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2126 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2127 SSEPackedDouble>, TB, OpSize, VEX_4V;
2128 let Constraints = "$src1 = $dst" in {
2129 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
2130 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2131 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2132 SSEPackedSingle>, TB;
2133 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
2134 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2135 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2136 SSEPackedDouble>, TB, OpSize;
2139 let Predicates = [HasSSE1] in {
2140 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2141 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2142 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2143 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2146 let Predicates = [HasSSE2] in {
2147 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2148 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2149 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2150 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2153 let Predicates = [HasAVX] in {
2154 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2155 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2156 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2157 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2158 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2159 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2160 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2161 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2163 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2164 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2165 def : Pat<(v8i32 (X86cmpps (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2166 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2167 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2168 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2169 def : Pat<(v4i64 (X86cmppd (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2170 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2173 //===----------------------------------------------------------------------===//
2174 // SSE 1 & 2 - Shuffle Instructions
2175 //===----------------------------------------------------------------------===//
2177 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2178 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2179 ValueType vt, string asm, PatFrag mem_frag,
2180 Domain d, bit IsConvertibleToThreeAddress = 0> {
2181 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2182 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
2183 [(set RC:$dst, (vt (shufp:$src3
2184 RC:$src1, (mem_frag addr:$src2))))], d>;
2185 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2186 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2187 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2189 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
2192 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2193 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2194 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2195 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2196 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2197 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2198 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2199 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2200 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2201 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2202 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2203 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2205 let Constraints = "$src1 = $dst" in {
2206 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2207 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2208 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2210 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2211 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2212 memopv2f64, SSEPackedDouble>, TB, OpSize;
2215 let Predicates = [HasSSE1] in {
2216 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2217 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2218 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2219 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2220 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2221 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2222 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2223 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2224 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2225 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2226 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2227 // fall back to this for SSE1)
2228 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2229 (SHUFPSrri VR128:$src2, VR128:$src1,
2230 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2231 // Special unary SHUFPSrri case.
2232 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2233 (SHUFPSrri VR128:$src1, VR128:$src1,
2234 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2237 let Predicates = [HasSSE2] in {
2238 // Special binary v4i32 shuffle cases with SHUFPS.
2239 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2240 (SHUFPSrri VR128:$src1, VR128:$src2,
2241 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2242 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2243 (bc_v4i32 (memopv2i64 addr:$src2)))),
2244 (SHUFPSrmi VR128:$src1, addr:$src2,
2245 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2246 // Special unary SHUFPDrri cases.
2247 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2248 (SHUFPDrri VR128:$src1, VR128:$src1,
2249 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2250 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2251 (SHUFPDrri VR128:$src1, VR128:$src1,
2252 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2253 // Special binary v2i64 shuffle cases using SHUFPDrri.
2254 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2255 (SHUFPDrri VR128:$src1, VR128:$src2,
2256 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2257 // Generic SHUFPD patterns
2258 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2259 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2260 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2261 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2262 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2263 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2264 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2267 let Predicates = [HasAVX] in {
2268 def : Pat<(v4f32 (X86Shufps VR128:$src1,
2269 (memopv4f32 addr:$src2), (i8 imm:$imm))),
2270 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2271 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2272 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2273 def : Pat<(v4i32 (X86Shufps VR128:$src1,
2274 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2275 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2276 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2277 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2278 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
2279 // fall back to this for SSE1)
2280 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
2281 (VSHUFPSrri VR128:$src2, VR128:$src1,
2282 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2283 // Special unary SHUFPSrri case.
2284 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2285 (VSHUFPSrri VR128:$src1, VR128:$src1,
2286 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2287 // Special binary v4i32 shuffle cases with SHUFPS.
2288 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2289 (VSHUFPSrri VR128:$src1, VR128:$src2,
2290 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2291 def : Pat<(v4i32 (shufp:$src3 VR128:$src1,
2292 (bc_v4i32 (memopv2i64 addr:$src2)))),
2293 (VSHUFPSrmi VR128:$src1, addr:$src2,
2294 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2295 // Special unary SHUFPDrri cases.
2296 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2297 (VSHUFPDrri VR128:$src1, VR128:$src1,
2298 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2299 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2300 (VSHUFPDrri VR128:$src1, VR128:$src1,
2301 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2302 // Special binary v2i64 shuffle cases using SHUFPDrri.
2303 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2304 (VSHUFPDrri VR128:$src1, VR128:$src2,
2305 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2307 def : Pat<(v2f64 (X86Shufps VR128:$src1,
2308 (memopv2f64 addr:$src2), (i8 imm:$imm))),
2309 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2310 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2311 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2312 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2313 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2316 def : Pat<(v8i32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2317 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2318 def : Pat<(v8i32 (X86Shufps VR256:$src1,
2319 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2320 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2322 def : Pat<(v8f32 (X86Shufps VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2323 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2324 def : Pat<(v8f32 (X86Shufps VR256:$src1,
2325 (memopv8f32 addr:$src2), (i8 imm:$imm))),
2326 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2328 def : Pat<(v4i64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2329 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2330 def : Pat<(v4i64 (X86Shufpd VR256:$src1,
2331 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2332 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2334 def : Pat<(v4f64 (X86Shufpd VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2335 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2336 def : Pat<(v4f64 (X86Shufpd VR256:$src1,
2337 (memopv4f64 addr:$src2), (i8 imm:$imm))),
2338 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2341 //===----------------------------------------------------------------------===//
2342 // SSE 1 & 2 - Unpack Instructions
2343 //===----------------------------------------------------------------------===//
2345 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2346 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
2347 PatFrag mem_frag, RegisterClass RC,
2348 X86MemOperand x86memop, string asm,
2350 def rr : PI<opc, MRMSrcReg,
2351 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2353 (vt (OpNode RC:$src1, RC:$src2)))], d>;
2354 def rm : PI<opc, MRMSrcMem,
2355 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2357 (vt (OpNode RC:$src1,
2358 (mem_frag addr:$src2))))], d>;
2361 let AddedComplexity = 10 in {
2362 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2363 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2364 SSEPackedSingle>, TB, VEX_4V;
2365 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2366 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2367 SSEPackedDouble>, TB, OpSize, VEX_4V;
2368 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2369 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2370 SSEPackedSingle>, TB, VEX_4V;
2371 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2372 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2373 SSEPackedDouble>, TB, OpSize, VEX_4V;
2375 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
2376 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2377 SSEPackedSingle>, TB, VEX_4V;
2378 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
2379 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2380 SSEPackedDouble>, TB, OpSize, VEX_4V;
2381 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
2382 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2383 SSEPackedSingle>, TB, VEX_4V;
2384 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
2385 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2386 SSEPackedDouble>, TB, OpSize, VEX_4V;
2388 let Constraints = "$src1 = $dst" in {
2389 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
2390 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2391 SSEPackedSingle>, TB;
2392 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
2393 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2394 SSEPackedDouble>, TB, OpSize;
2395 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
2396 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2397 SSEPackedSingle>, TB;
2398 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
2399 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2400 SSEPackedDouble>, TB, OpSize;
2401 } // Constraints = "$src1 = $dst"
2402 } // AddedComplexity
2404 let Predicates = [HasSSE1] in {
2405 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2406 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
2407 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2408 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
2409 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2410 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
2411 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2412 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
2415 let Predicates = [HasSSE2] in {
2416 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2417 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
2418 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2419 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
2420 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2421 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
2422 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2423 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
2425 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2426 // problem is during lowering, where it's not possible to recognize the load
2427 // fold cause it has two uses through a bitcast. One use disappears at isel
2428 // time and the fold opportunity reappears.
2429 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2430 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2432 let AddedComplexity = 10 in
2433 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2434 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2437 let Predicates = [HasAVX] in {
2438 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
2439 (VUNPCKLPSrm VR128:$src1, addr:$src2)>;
2440 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
2441 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
2442 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
2443 (VUNPCKHPSrm VR128:$src1, addr:$src2)>;
2444 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
2445 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
2447 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
2448 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2449 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2450 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2451 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
2452 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2453 def : Pat<(v8i32 (X86Unpcklpsy VR256:$src1, (memopv8i32 addr:$src2))),
2454 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2455 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
2456 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2457 def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2458 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2459 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, (memopv8i32 addr:$src2))),
2460 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2461 def : Pat<(v8i32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
2462 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2464 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
2465 (VUNPCKLPDrm VR128:$src1, addr:$src2)>;
2466 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
2467 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
2468 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
2469 (VUNPCKHPDrm VR128:$src1, addr:$src2)>;
2470 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
2471 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
2473 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
2474 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2475 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2476 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2477 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, (memopv4i64 addr:$src2))),
2478 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2479 def : Pat<(v4i64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
2480 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2481 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
2482 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2483 def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2484 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2485 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, (memopv4i64 addr:$src2))),
2486 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2487 def : Pat<(v4i64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
2488 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2490 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the
2491 // problem is during lowering, where it's not possible to recognize the load
2492 // fold cause it has two uses through a bitcast. One use disappears at isel
2493 // time and the fold opportunity reappears.
2494 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2495 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2496 let AddedComplexity = 10 in
2497 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2498 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2501 //===----------------------------------------------------------------------===//
2502 // SSE 1 & 2 - Extract Floating-Point Sign mask
2503 //===----------------------------------------------------------------------===//
2505 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2506 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2508 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2509 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2510 [(set GR32:$dst, (Int RC:$src))], d>;
2511 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2512 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
2515 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2516 SSEPackedSingle>, TB;
2517 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2518 SSEPackedDouble>, TB, OpSize;
2520 def : Pat<(i32 (X86fgetsign FR32:$src)),
2521 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2522 sub_ss))>, Requires<[HasSSE1]>;
2523 def : Pat<(i64 (X86fgetsign FR32:$src)),
2524 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2525 sub_ss))>, Requires<[HasSSE1]>;
2526 def : Pat<(i32 (X86fgetsign FR64:$src)),
2527 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2528 sub_sd))>, Requires<[HasSSE2]>;
2529 def : Pat<(i64 (X86fgetsign FR64:$src)),
2530 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2531 sub_sd))>, Requires<[HasSSE2]>;
2533 let Predicates = [HasAVX] in {
2534 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2535 "movmskps", SSEPackedSingle>, TB, VEX;
2536 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2537 "movmskpd", SSEPackedDouble>, TB,
2539 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2540 "movmskps", SSEPackedSingle>, TB, VEX;
2541 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2542 "movmskpd", SSEPackedDouble>, TB,
2545 def : Pat<(i32 (X86fgetsign FR32:$src)),
2546 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2548 def : Pat<(i64 (X86fgetsign FR32:$src)),
2549 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2551 def : Pat<(i32 (X86fgetsign FR64:$src)),
2552 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2554 def : Pat<(i64 (X86fgetsign FR64:$src)),
2555 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2559 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2560 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2561 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2562 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2564 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2565 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, TB, VEX;
2566 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2567 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, TB,
2571 //===----------------------------------------------------------------------===//
2572 // SSE 1 & 2 - Logical Instructions
2573 //===----------------------------------------------------------------------===//
2575 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2577 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2579 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2580 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, TB, VEX_4V;
2582 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2583 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, TB, OpSize, VEX_4V;
2585 let Constraints = "$src1 = $dst" in {
2586 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2587 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
2589 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2590 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
2594 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2595 let mayLoad = 0 in {
2596 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
2597 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
2598 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
2601 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2602 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
2604 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2606 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2608 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2609 // are all promoted to v2i64, and the patterns are covered by the int
2610 // version. This is needed in SSE only, because v2i64 isn't supported on
2611 // SSE1, but only on SSE2.
2612 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2613 !strconcat(OpcodeStr, "ps"), f128mem, [],
2614 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2615 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2617 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2618 !strconcat(OpcodeStr, "pd"), f128mem,
2619 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2620 (bc_v2i64 (v2f64 VR128:$src2))))],
2621 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2622 (memopv2i64 addr:$src2)))], 0>,
2624 let Constraints = "$src1 = $dst" in {
2625 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2626 !strconcat(OpcodeStr, "ps"), f128mem,
2627 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2628 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2629 (memopv2i64 addr:$src2)))]>, TB;
2631 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2632 !strconcat(OpcodeStr, "pd"), f128mem,
2633 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2634 (bc_v2i64 (v2f64 VR128:$src2))))],
2635 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2636 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2640 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2642 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2644 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2645 !strconcat(OpcodeStr, "ps"), f256mem,
2646 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2647 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2648 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2650 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2651 !strconcat(OpcodeStr, "pd"), f256mem,
2652 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2653 (bc_v4i64 (v4f64 VR256:$src2))))],
2654 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2655 (memopv4i64 addr:$src2)))], 0>,
2659 // AVX 256-bit packed logical ops forms
2660 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2661 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2662 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2663 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2665 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2666 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2667 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2668 let isCommutable = 0 in
2669 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2671 //===----------------------------------------------------------------------===//
2672 // SSE 1 & 2 - Arithmetic Instructions
2673 //===----------------------------------------------------------------------===//
2675 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2678 /// In addition, we also have a special variant of the scalar form here to
2679 /// represent the associated intrinsic operation. This form is unlike the
2680 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2681 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2683 /// These three forms can each be reg+reg or reg+mem.
2686 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2688 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2690 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2691 OpNode, FR32, f32mem, Is2Addr>, XS;
2692 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2693 OpNode, FR64, f64mem, Is2Addr>, XD;
2696 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2698 let mayLoad = 0 in {
2699 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2700 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
2701 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2702 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
2706 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2708 let mayLoad = 0 in {
2709 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2710 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
2711 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2712 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
2716 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2718 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2719 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
2720 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2721 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
2724 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2726 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2727 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2728 SSEPackedSingle, Is2Addr>, TB;
2730 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2731 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2732 SSEPackedDouble, Is2Addr>, TB, OpSize;
2735 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
2736 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2737 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2738 SSEPackedSingle, 0>, TB;
2740 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2741 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2742 SSEPackedDouble, 0>, TB, OpSize;
2745 // Binary Arithmetic instructions
2746 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
2747 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
2748 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
2749 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
2750 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
2751 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
2752 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
2753 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
2755 let isCommutable = 0 in {
2756 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
2757 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
2758 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
2759 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
2760 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
2761 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
2762 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
2763 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
2764 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
2765 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
2766 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
2767 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
2768 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
2769 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
2770 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
2771 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
2772 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
2773 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
2774 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
2775 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
2778 let Constraints = "$src1 = $dst" in {
2779 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
2780 basic_sse12_fp_binop_p<0x58, "add", fadd>,
2781 basic_sse12_fp_binop_s_int<0x58, "add">;
2782 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
2783 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
2784 basic_sse12_fp_binop_s_int<0x59, "mul">;
2786 let isCommutable = 0 in {
2787 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
2788 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
2789 basic_sse12_fp_binop_s_int<0x5C, "sub">;
2790 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
2791 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
2792 basic_sse12_fp_binop_s_int<0x5E, "div">;
2793 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
2794 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
2795 basic_sse12_fp_binop_s_int<0x5F, "max">,
2796 basic_sse12_fp_binop_p_int<0x5F, "max">;
2797 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
2798 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
2799 basic_sse12_fp_binop_s_int<0x5D, "min">,
2800 basic_sse12_fp_binop_p_int<0x5D, "min">;
2805 /// In addition, we also have a special variant of the scalar form here to
2806 /// represent the associated intrinsic operation. This form is unlike the
2807 /// plain scalar form, in that it takes an entire vector (instead of a
2808 /// scalar) and leaves the top elements undefined.
2810 /// And, we have a special variant form for a full-vector intrinsic form.
2812 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2813 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2814 SDNode OpNode, Intrinsic F32Int> {
2815 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2816 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2817 [(set FR32:$dst, (OpNode FR32:$src))]>;
2818 // For scalar unary operations, fold a load into the operation
2819 // only in OptForSize mode. It eliminates an instruction, but it also
2820 // eliminates a whole-register clobber (the load), so it introduces a
2821 // partial register update condition.
2822 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
2823 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2824 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
2825 Requires<[HasSSE1, OptForSize]>;
2826 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2827 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2828 [(set VR128:$dst, (F32Int VR128:$src))]>;
2829 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
2830 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
2831 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
2834 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
2835 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2836 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
2837 !strconcat(OpcodeStr,
2838 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2840 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
2841 !strconcat(OpcodeStr,
2842 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2843 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
2844 (ins ssmem:$src1, VR128:$src2),
2845 !strconcat(OpcodeStr,
2846 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2849 /// sse1_fp_unop_p - SSE1 unops in packed form.
2850 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2851 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2852 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2853 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
2854 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2855 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2856 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
2859 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
2860 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2861 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2862 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2863 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
2864 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2865 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2866 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
2869 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
2870 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2871 Intrinsic V4F32Int> {
2872 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2873 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2874 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
2875 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2876 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2877 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
2880 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
2881 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2882 Intrinsic V4F32Int> {
2883 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2884 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2885 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
2886 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2887 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2888 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
2891 /// sse2_fp_unop_s - SSE2 unops in scalar form.
2892 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
2893 SDNode OpNode, Intrinsic F64Int> {
2894 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
2895 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2896 [(set FR64:$dst, (OpNode FR64:$src))]>;
2897 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2898 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
2899 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2900 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
2901 Requires<[HasSSE2, OptForSize]>;
2902 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2903 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2904 [(set VR128:$dst, (F64Int VR128:$src))]>;
2905 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
2906 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
2907 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
2910 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
2911 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
2912 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
2913 !strconcat(OpcodeStr,
2914 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2915 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
2916 !strconcat(OpcodeStr,
2917 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2918 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
2919 (ins VR128:$src1, sdmem:$src2),
2920 !strconcat(OpcodeStr,
2921 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
2924 /// sse2_fp_unop_p - SSE2 unops in vector forms.
2925 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
2927 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2928 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2929 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
2930 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2931 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2932 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
2935 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
2936 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2937 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2938 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2939 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
2940 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2941 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2942 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
2945 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
2946 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2947 Intrinsic V2F64Int> {
2948 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2949 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2950 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
2951 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2952 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2953 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
2956 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
2957 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
2958 Intrinsic V2F64Int> {
2959 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2960 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2961 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
2962 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2963 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2964 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
2967 let Predicates = [HasAVX] in {
2969 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
2970 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V;
2972 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
2973 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
2974 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2975 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
2976 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
2977 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
2978 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
2979 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
2982 // Reciprocal approximations. Note that these typically require refinement
2983 // in order to obtain suitable precision.
2984 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V;
2985 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
2986 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
2987 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
2988 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
2990 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V;
2991 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
2992 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
2993 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
2994 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
2997 def : Pat<(f32 (fsqrt FR32:$src)),
2998 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
2999 def : Pat<(f32 (fsqrt (load addr:$src))),
3000 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3001 Requires<[HasAVX, OptForSize]>;
3002 def : Pat<(f64 (fsqrt FR64:$src)),
3003 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3004 def : Pat<(f64 (fsqrt (load addr:$src))),
3005 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3006 Requires<[HasAVX, OptForSize]>;
3008 def : Pat<(f32 (X86frsqrt FR32:$src)),
3009 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3010 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3011 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3012 Requires<[HasAVX, OptForSize]>;
3014 def : Pat<(f32 (X86frcp FR32:$src)),
3015 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3016 def : Pat<(f32 (X86frcp (load addr:$src))),
3017 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3018 Requires<[HasAVX, OptForSize]>;
3020 let Predicates = [HasAVX] in {
3021 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3022 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3023 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3024 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3026 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3027 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3029 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3030 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3031 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3032 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3034 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3035 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3037 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3038 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3039 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3040 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3042 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3043 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3045 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3046 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3047 (VRCPSSr (f32 (IMPLICIT_DEF)),
3048 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3050 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3051 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3055 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
3056 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
3057 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
3058 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
3059 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
3060 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
3062 // Reciprocal approximations. Note that these typically require refinement
3063 // in order to obtain suitable precision.
3064 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
3065 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
3066 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
3067 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
3068 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
3069 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
3071 // There is no f64 version of the reciprocal approximation instructions.
3073 //===----------------------------------------------------------------------===//
3074 // SSE 1 & 2 - Non-temporal stores
3075 //===----------------------------------------------------------------------===//
3077 let AddedComplexity = 400 in { // Prefer non-temporal versions
3078 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3079 (ins f128mem:$dst, VR128:$src),
3080 "movntps\t{$src, $dst|$dst, $src}",
3081 [(alignednontemporalstore (v4f32 VR128:$src),
3083 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3084 (ins f128mem:$dst, VR128:$src),
3085 "movntpd\t{$src, $dst|$dst, $src}",
3086 [(alignednontemporalstore (v2f64 VR128:$src),
3088 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
3089 (ins f128mem:$dst, VR128:$src),
3090 "movntdq\t{$src, $dst|$dst, $src}",
3091 [(alignednontemporalstore (v2f64 VR128:$src),
3094 let ExeDomain = SSEPackedInt in
3095 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3096 (ins f128mem:$dst, VR128:$src),
3097 "movntdq\t{$src, $dst|$dst, $src}",
3098 [(alignednontemporalstore (v4f32 VR128:$src),
3101 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3102 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3104 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3105 (ins f256mem:$dst, VR256:$src),
3106 "movntps\t{$src, $dst|$dst, $src}",
3107 [(alignednontemporalstore (v8f32 VR256:$src),
3109 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3110 (ins f256mem:$dst, VR256:$src),
3111 "movntpd\t{$src, $dst|$dst, $src}",
3112 [(alignednontemporalstore (v4f64 VR256:$src),
3114 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
3115 (ins f256mem:$dst, VR256:$src),
3116 "movntdq\t{$src, $dst|$dst, $src}",
3117 [(alignednontemporalstore (v4f64 VR256:$src),
3119 let ExeDomain = SSEPackedInt in
3120 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3121 (ins f256mem:$dst, VR256:$src),
3122 "movntdq\t{$src, $dst|$dst, $src}",
3123 [(alignednontemporalstore (v8f32 VR256:$src),
3127 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
3128 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3129 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
3130 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
3131 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
3132 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
3134 let AddedComplexity = 400 in { // Prefer non-temporal versions
3135 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3136 "movntps\t{$src, $dst|$dst, $src}",
3137 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3138 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3139 "movntpd\t{$src, $dst|$dst, $src}",
3140 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
3142 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3143 "movntdq\t{$src, $dst|$dst, $src}",
3144 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
3146 let ExeDomain = SSEPackedInt in
3147 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3148 "movntdq\t{$src, $dst|$dst, $src}",
3149 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
3151 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3152 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3154 // There is no AVX form for instructions below this point
3155 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3156 "movnti{l}\t{$src, $dst|$dst, $src}",
3157 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
3158 TB, Requires<[HasSSE2]>;
3159 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3160 "movnti{q}\t{$src, $dst|$dst, $src}",
3161 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
3162 TB, Requires<[HasSSE2]>;
3165 //===----------------------------------------------------------------------===//
3166 // SSE 1 & 2 - Prefetch and memory fence
3167 //===----------------------------------------------------------------------===//
3169 // Prefetch intrinsic.
3170 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
3171 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
3172 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
3173 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
3174 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
3175 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
3176 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
3177 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
3180 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3181 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3182 TB, Requires<[HasSSE2]>;
3184 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3185 // was introduced with SSE2, it's backward compatible.
3186 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3188 // Load, store, and memory fence
3189 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3190 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
3191 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3192 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3193 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3194 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3196 def : Pat<(X86SFence), (SFENCE)>;
3197 def : Pat<(X86LFence), (LFENCE)>;
3198 def : Pat<(X86MFence), (MFENCE)>;
3200 //===----------------------------------------------------------------------===//
3201 // SSE 1 & 2 - Load/Store XCSR register
3202 //===----------------------------------------------------------------------===//
3204 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3205 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
3206 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3207 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
3209 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3210 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
3211 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3212 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
3214 //===---------------------------------------------------------------------===//
3215 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3216 //===---------------------------------------------------------------------===//
3218 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3220 let neverHasSideEffects = 1 in {
3221 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3222 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3223 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3224 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3226 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3227 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3228 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3229 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3232 let isCodeGenOnly = 1 in {
3233 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3234 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3235 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3236 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3237 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3238 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3239 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3240 "movdqu\t{$src, $dst|$dst, $src}", []>, VEX;
3243 let canFoldAsLoad = 1, mayLoad = 1 in {
3244 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3245 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3246 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3247 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3248 let Predicates = [HasAVX] in {
3249 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3250 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3251 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3252 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3256 let mayStore = 1 in {
3257 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3258 (ins i128mem:$dst, VR128:$src),
3259 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3260 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3261 (ins i256mem:$dst, VR256:$src),
3262 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
3263 let Predicates = [HasAVX] in {
3264 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3265 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3266 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3267 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
3271 let neverHasSideEffects = 1 in
3272 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3273 "movdqa\t{$src, $dst|$dst, $src}", []>;
3275 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3276 "movdqu\t{$src, $dst|$dst, $src}",
3277 []>, XS, Requires<[HasSSE2]>;
3280 let isCodeGenOnly = 1 in {
3281 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3282 "movdqa\t{$src, $dst|$dst, $src}", []>;
3284 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3285 "movdqu\t{$src, $dst|$dst, $src}",
3286 []>, XS, Requires<[HasSSE2]>;
3289 let canFoldAsLoad = 1, mayLoad = 1 in {
3290 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3291 "movdqa\t{$src, $dst|$dst, $src}",
3292 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
3293 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3294 "movdqu\t{$src, $dst|$dst, $src}",
3295 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
3296 XS, Requires<[HasSSE2]>;
3299 let mayStore = 1 in {
3300 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3301 "movdqa\t{$src, $dst|$dst, $src}",
3302 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
3303 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3304 "movdqu\t{$src, $dst|$dst, $src}",
3305 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
3306 XS, Requires<[HasSSE2]>;
3309 // Intrinsic forms of MOVDQU load and store
3310 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3311 "vmovdqu\t{$src, $dst|$dst, $src}",
3312 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3313 XS, VEX, Requires<[HasAVX]>;
3315 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3316 "movdqu\t{$src, $dst|$dst, $src}",
3317 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
3318 XS, Requires<[HasSSE2]>;
3320 } // ExeDomain = SSEPackedInt
3322 let Predicates = [HasAVX] in {
3323 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
3324 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3325 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3328 //===---------------------------------------------------------------------===//
3329 // SSE2 - Packed Integer Arithmetic Instructions
3330 //===---------------------------------------------------------------------===//
3332 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3334 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3335 bit IsCommutable = 0, bit Is2Addr = 1> {
3336 let isCommutable = IsCommutable in
3337 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3338 (ins VR128:$src1, VR128:$src2),
3340 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3341 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3342 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
3343 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3344 (ins VR128:$src1, i128mem:$src2),
3346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3347 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3348 [(set VR128:$dst, (IntId VR128:$src1,
3349 (bitconvert (memopv2i64 addr:$src2))))]>;
3352 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
3353 string OpcodeStr, Intrinsic IntId,
3354 Intrinsic IntId2, bit Is2Addr = 1> {
3355 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3356 (ins VR128:$src1, VR128:$src2),
3358 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3359 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3360 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
3361 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3362 (ins VR128:$src1, i128mem:$src2),
3364 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3365 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3366 [(set VR128:$dst, (IntId VR128:$src1,
3367 (bitconvert (memopv2i64 addr:$src2))))]>;
3368 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
3369 (ins VR128:$src1, i32i8imm:$src2),
3371 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3372 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3373 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
3376 /// PDI_binop_rm - Simple SSE2 binary operator.
3377 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3378 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
3379 let isCommutable = IsCommutable in
3380 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3381 (ins VR128:$src1, VR128:$src2),
3383 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3384 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3385 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
3386 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3387 (ins VR128:$src1, i128mem:$src2),
3389 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3390 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3391 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
3392 (bitconvert (memopv2i64 addr:$src2)))))]>;
3395 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
3397 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
3398 /// to collapse (bitconvert VT to VT) into its operand.
3400 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
3401 bit IsCommutable = 0, bit Is2Addr = 1> {
3402 let isCommutable = IsCommutable in
3403 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
3404 (ins VR128:$src1, VR128:$src2),
3406 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3407 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3408 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
3409 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
3410 (ins VR128:$src1, i128mem:$src2),
3412 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3413 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3414 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
3417 } // ExeDomain = SSEPackedInt
3419 // 128-bit Integer Arithmetic
3421 let Predicates = [HasAVX] in {
3422 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
3423 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
3424 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
3425 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
3426 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
3427 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
3428 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
3429 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
3430 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
3433 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
3435 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
3437 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
3439 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
3441 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
3443 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
3445 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
3447 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
3449 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
3451 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
3453 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
3455 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
3457 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
3459 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
3461 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
3463 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
3465 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
3467 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
3469 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
3473 let Constraints = "$src1 = $dst" in {
3474 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
3475 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
3476 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
3477 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
3478 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
3479 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
3480 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
3481 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
3482 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
3485 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
3486 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
3487 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
3488 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
3489 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
3490 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
3491 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
3492 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
3493 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
3494 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
3495 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
3496 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
3497 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
3498 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
3499 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
3500 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
3501 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
3502 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
3503 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
3505 } // Constraints = "$src1 = $dst"
3507 //===---------------------------------------------------------------------===//
3508 // SSE2 - Packed Integer Logical Instructions
3509 //===---------------------------------------------------------------------===//
3511 let Predicates = [HasAVX] in {
3512 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
3513 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
3515 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
3516 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
3518 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
3519 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
3522 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
3523 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
3525 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
3526 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
3528 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
3529 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
3532 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
3533 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
3535 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
3536 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
3539 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
3540 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
3541 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
3543 let ExeDomain = SSEPackedInt in {
3544 let neverHasSideEffects = 1 in {
3545 // 128-bit logical shifts.
3546 def VPSLLDQri : PDIi8<0x73, MRM7r,
3547 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3548 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3550 def VPSRLDQri : PDIi8<0x73, MRM3r,
3551 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3552 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
3554 // PSRADQri doesn't exist in SSE[1-3].
3556 def VPANDNrr : PDI<0xDF, MRMSrcReg,
3557 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3558 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3560 (v2i64 (X86andnp VR128:$src1, VR128:$src2)))]>,VEX_4V;
3562 def VPANDNrm : PDI<0xDF, MRMSrcMem,
3563 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3564 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3565 [(set VR128:$dst, (X86andnp VR128:$src1,
3566 (memopv2i64 addr:$src2)))]>, VEX_4V;
3570 let Constraints = "$src1 = $dst" in {
3571 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
3572 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
3573 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
3574 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
3575 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
3576 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
3578 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
3579 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
3580 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
3581 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
3582 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
3583 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
3585 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
3586 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
3587 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
3588 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
3590 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
3591 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
3592 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
3594 let ExeDomain = SSEPackedInt in {
3595 let neverHasSideEffects = 1 in {
3596 // 128-bit logical shifts.
3597 def PSLLDQri : PDIi8<0x73, MRM7r,
3598 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3599 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
3600 def PSRLDQri : PDIi8<0x73, MRM3r,
3601 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3602 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
3603 // PSRADQri doesn't exist in SSE[1-3].
3605 def PANDNrr : PDI<0xDF, MRMSrcReg,
3606 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3607 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3609 def PANDNrm : PDI<0xDF, MRMSrcMem,
3610 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3611 "pandn\t{$src2, $dst|$dst, $src2}", []>;
3613 } // Constraints = "$src1 = $dst"
3615 let Predicates = [HasAVX] in {
3616 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3617 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3618 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3619 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3620 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3621 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
3622 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3623 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
3624 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3625 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3627 // Shift up / down and insert zero's.
3628 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3629 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3630 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3631 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3634 let Predicates = [HasSSE2] in {
3635 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
3636 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3637 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
3638 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3639 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
3640 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
3641 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
3642 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
3643 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
3644 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
3646 // Shift up / down and insert zero's.
3647 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
3648 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3649 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
3650 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
3653 //===---------------------------------------------------------------------===//
3654 // SSE2 - Packed Integer Comparison Instructions
3655 //===---------------------------------------------------------------------===//
3657 let Predicates = [HasAVX] in {
3658 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
3660 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
3662 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
3664 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
3666 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
3668 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
3671 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3672 (VPCMPEQBrr VR128:$src1, VR128:$src2)>;
3673 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3674 (VPCMPEQBrm VR128:$src1, addr:$src2)>;
3675 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3676 (VPCMPEQWrr VR128:$src1, VR128:$src2)>;
3677 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3678 (VPCMPEQWrm VR128:$src1, addr:$src2)>;
3679 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3680 (VPCMPEQDrr VR128:$src1, VR128:$src2)>;
3681 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3682 (VPCMPEQDrm VR128:$src1, addr:$src2)>;
3684 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3685 (VPCMPGTBrr VR128:$src1, VR128:$src2)>;
3686 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3687 (VPCMPGTBrm VR128:$src1, addr:$src2)>;
3688 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3689 (VPCMPGTWrr VR128:$src1, VR128:$src2)>;
3690 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3691 (VPCMPGTWrm VR128:$src1, addr:$src2)>;
3692 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3693 (VPCMPGTDrr VR128:$src1, VR128:$src2)>;
3694 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3695 (VPCMPGTDrm VR128:$src1, addr:$src2)>;
3698 let Constraints = "$src1 = $dst" in {
3699 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
3700 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
3701 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
3702 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
3703 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
3704 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
3705 } // Constraints = "$src1 = $dst"
3707 let Predicates = [HasSSE2] in {
3708 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
3709 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
3710 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
3711 (PCMPEQBrm VR128:$src1, addr:$src2)>;
3712 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
3713 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
3714 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
3715 (PCMPEQWrm VR128:$src1, addr:$src2)>;
3716 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
3717 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
3718 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
3719 (PCMPEQDrm VR128:$src1, addr:$src2)>;
3721 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
3722 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
3723 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
3724 (PCMPGTBrm VR128:$src1, addr:$src2)>;
3725 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
3726 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
3727 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
3728 (PCMPGTWrm VR128:$src1, addr:$src2)>;
3729 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
3730 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
3731 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
3732 (PCMPGTDrm VR128:$src1, addr:$src2)>;
3735 //===---------------------------------------------------------------------===//
3736 // SSE2 - Packed Integer Pack Instructions
3737 //===---------------------------------------------------------------------===//
3739 let Predicates = [HasAVX] in {
3740 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
3742 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
3744 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
3748 let Constraints = "$src1 = $dst" in {
3749 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
3750 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
3751 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
3752 } // Constraints = "$src1 = $dst"
3754 //===---------------------------------------------------------------------===//
3755 // SSE2 - Packed Integer Shuffle Instructions
3756 //===---------------------------------------------------------------------===//
3758 let ExeDomain = SSEPackedInt in {
3759 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
3761 def ri : Ii8<0x70, MRMSrcReg,
3762 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
3763 !strconcat(OpcodeStr,
3764 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3765 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
3767 def mi : Ii8<0x70, MRMSrcMem,
3768 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
3769 !strconcat(OpcodeStr,
3770 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3771 [(set VR128:$dst, (vt (pshuf_frag:$src2
3772 (bc_frag (memopv2i64 addr:$src1)),
3775 } // ExeDomain = SSEPackedInt
3777 let Predicates = [HasAVX] in {
3778 let AddedComplexity = 5 in
3779 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize,
3782 // SSE2 with ImmT == Imm8 and XS prefix.
3783 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
3786 // SSE2 with ImmT == Imm8 and XD prefix.
3787 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
3790 let AddedComplexity = 5 in
3791 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3792 (VPSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3793 // Unary v4f32 shuffle with VPSHUF* in order to fold a load.
3794 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3795 (VPSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3797 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3799 (VPSHUFDmi addr:$src1, imm:$imm)>;
3800 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3802 (VPSHUFDmi addr:$src1, imm:$imm)>;
3803 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3804 (VPSHUFDri VR128:$src1, imm:$imm)>;
3805 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3806 (VPSHUFDri VR128:$src1, imm:$imm)>;
3807 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3808 (VPSHUFHWri VR128:$src, imm:$imm)>;
3809 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3811 (VPSHUFHWmi addr:$src, imm:$imm)>;
3812 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3813 (VPSHUFLWri VR128:$src, imm:$imm)>;
3814 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3816 (VPSHUFLWmi addr:$src, imm:$imm)>;
3819 let Predicates = [HasSSE2] in {
3820 let AddedComplexity = 5 in
3821 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
3823 // SSE2 with ImmT == Imm8 and XS prefix.
3824 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
3826 // SSE2 with ImmT == Imm8 and XD prefix.
3827 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
3829 let AddedComplexity = 5 in
3830 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3831 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3832 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3833 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3834 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>;
3836 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
3838 (PSHUFDmi addr:$src1, imm:$imm)>;
3839 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
3841 (PSHUFDmi addr:$src1, imm:$imm)>;
3842 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3843 (PSHUFDri VR128:$src1, imm:$imm)>;
3844 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
3845 (PSHUFDri VR128:$src1, imm:$imm)>;
3846 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
3847 (PSHUFHWri VR128:$src, imm:$imm)>;
3848 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)),
3850 (PSHUFHWmi addr:$src, imm:$imm)>;
3851 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
3852 (PSHUFLWri VR128:$src, imm:$imm)>;
3853 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)),
3855 (PSHUFLWmi addr:$src, imm:$imm)>;
3858 //===---------------------------------------------------------------------===//
3859 // SSE2 - Packed Integer Unpack Instructions
3860 //===---------------------------------------------------------------------===//
3862 let ExeDomain = SSEPackedInt in {
3863 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
3864 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
3865 def rr : PDI<opc, MRMSrcReg,
3866 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3868 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3869 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3870 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))]>;
3871 def rm : PDI<opc, MRMSrcMem,
3872 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3874 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
3875 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3876 [(set VR128:$dst, (OpNode VR128:$src1,
3877 (bc_frag (memopv2i64
3881 let Predicates = [HasAVX] in {
3882 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Punpcklbw,
3883 bc_v16i8, 0>, VEX_4V;
3884 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Punpcklwd,
3885 bc_v8i16, 0>, VEX_4V;
3886 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Punpckldq,
3887 bc_v4i32, 0>, VEX_4V;
3889 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3890 /// knew to collapse (bitconvert VT to VT) into its operand.
3891 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3892 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3893 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3894 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3895 VR128:$src2)))]>, VEX_4V;
3896 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3897 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3898 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3899 [(set VR128:$dst, (v2i64 (X86Punpcklqdq VR128:$src1,
3900 (memopv2i64 addr:$src2))))]>, VEX_4V;
3902 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Punpckhbw,
3903 bc_v16i8, 0>, VEX_4V;
3904 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Punpckhwd,
3905 bc_v8i16, 0>, VEX_4V;
3906 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Punpckhdq,
3907 bc_v4i32, 0>, VEX_4V;
3909 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3910 /// knew to collapse (bitconvert VT to VT) into its operand.
3911 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3912 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3913 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3914 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3915 VR128:$src2)))]>, VEX_4V;
3916 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3917 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3918 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3919 [(set VR128:$dst, (v2i64 (X86Punpckhqdq VR128:$src1,
3920 (memopv2i64 addr:$src2))))]>, VEX_4V;
3923 let Constraints = "$src1 = $dst" in {
3924 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Punpcklbw, bc_v16i8>;
3925 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Punpcklwd, bc_v8i16>;
3926 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Punpckldq, bc_v4i32>;
3928 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3929 /// knew to collapse (bitconvert VT to VT) into its operand.
3930 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
3931 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3932 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3934 (v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)))]>;
3935 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
3936 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3937 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
3939 (v2i64 (X86Punpcklqdq VR128:$src1,
3940 (memopv2i64 addr:$src2))))]>;
3942 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Punpckhbw, bc_v16i8>;
3943 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Punpckhwd, bc_v8i16>;
3944 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Punpckhdq, bc_v4i32>;
3946 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
3947 /// knew to collapse (bitconvert VT to VT) into its operand.
3948 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
3949 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3950 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3952 (v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)))]>;
3953 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
3954 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
3955 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
3957 (v2i64 (X86Punpckhqdq VR128:$src1,
3958 (memopv2i64 addr:$src2))))]>;
3960 } // ExeDomain = SSEPackedInt
3962 // Splat v2f64 / v2i64
3963 let AddedComplexity = 10 in {
3964 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3965 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3966 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3967 (VPUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasAVX]>;
3970 //===---------------------------------------------------------------------===//
3971 // SSE2 - Packed Integer Extract and Insert
3972 //===---------------------------------------------------------------------===//
3974 let ExeDomain = SSEPackedInt in {
3975 multiclass sse2_pinsrw<bit Is2Addr = 1> {
3976 def rri : Ii8<0xC4, MRMSrcReg,
3977 (outs VR128:$dst), (ins VR128:$src1,
3978 GR32:$src2, i32i8imm:$src3),
3980 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3981 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3983 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
3984 def rmi : Ii8<0xC4, MRMSrcMem,
3985 (outs VR128:$dst), (ins VR128:$src1,
3986 i16mem:$src2, i32i8imm:$src3),
3988 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
3989 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3991 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
3996 let Predicates = [HasAVX] in
3997 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
3998 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
3999 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4000 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4001 imm:$src2))]>, TB, OpSize, VEX;
4002 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4003 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4004 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4005 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4009 let Predicates = [HasAVX] in {
4010 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4011 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4012 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4013 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4014 []>, TB, OpSize, VEX_4V;
4017 let Constraints = "$src1 = $dst" in
4018 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4020 } // ExeDomain = SSEPackedInt
4022 //===---------------------------------------------------------------------===//
4023 // SSE2 - Packed Mask Creation
4024 //===---------------------------------------------------------------------===//
4026 let ExeDomain = SSEPackedInt in {
4028 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4029 "pmovmskb\t{$src, $dst|$dst, $src}",
4030 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
4031 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4032 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4033 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4034 "pmovmskb\t{$src, $dst|$dst, $src}",
4035 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
4037 } // ExeDomain = SSEPackedInt
4039 //===---------------------------------------------------------------------===//
4040 // SSE2 - Conditional Store
4041 //===---------------------------------------------------------------------===//
4043 let ExeDomain = SSEPackedInt in {
4046 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4047 (ins VR128:$src, VR128:$mask),
4048 "maskmovdqu\t{$mask, $src|$src, $mask}",
4049 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
4051 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4052 (ins VR128:$src, VR128:$mask),
4053 "maskmovdqu\t{$mask, $src|$src, $mask}",
4054 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
4057 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4058 "maskmovdqu\t{$mask, $src|$src, $mask}",
4059 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
4061 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4062 "maskmovdqu\t{$mask, $src|$src, $mask}",
4063 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
4065 } // ExeDomain = SSEPackedInt
4067 //===---------------------------------------------------------------------===//
4068 // SSE2 - Move Doubleword
4069 //===---------------------------------------------------------------------===//
4071 //===---------------------------------------------------------------------===//
4072 // Move Int Doubleword to Packed Double Int
4074 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4075 "movd\t{$src, $dst|$dst, $src}",
4077 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
4078 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4079 "movd\t{$src, $dst|$dst, $src}",
4081 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
4083 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4084 "mov{d|q}\t{$src, $dst|$dst, $src}",
4086 (v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
4087 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4088 "mov{d|q}\t{$src, $dst|$dst, $src}",
4089 [(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
4091 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4092 "movd\t{$src, $dst|$dst, $src}",
4094 (v4i32 (scalar_to_vector GR32:$src)))]>;
4095 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4096 "movd\t{$src, $dst|$dst, $src}",
4098 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
4099 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4100 "mov{d|q}\t{$src, $dst|$dst, $src}",
4102 (v2i64 (scalar_to_vector GR64:$src)))]>;
4103 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4104 "mov{d|q}\t{$src, $dst|$dst, $src}",
4105 [(set FR64:$dst, (bitconvert GR64:$src))]>;
4107 //===---------------------------------------------------------------------===//
4108 // Move Int Doubleword to Single Scalar
4110 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4111 "movd\t{$src, $dst|$dst, $src}",
4112 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
4114 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4115 "movd\t{$src, $dst|$dst, $src}",
4116 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
4118 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4119 "movd\t{$src, $dst|$dst, $src}",
4120 [(set FR32:$dst, (bitconvert GR32:$src))]>;
4122 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4123 "movd\t{$src, $dst|$dst, $src}",
4124 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
4126 //===---------------------------------------------------------------------===//
4127 // Move Packed Doubleword Int to Packed Double Int
4129 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4130 "movd\t{$src, $dst|$dst, $src}",
4131 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4133 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4134 (ins i32mem:$dst, VR128:$src),
4135 "movd\t{$src, $dst|$dst, $src}",
4136 [(store (i32 (vector_extract (v4i32 VR128:$src),
4137 (iPTR 0))), addr:$dst)]>, VEX;
4138 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4139 "movd\t{$src, $dst|$dst, $src}",
4140 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4142 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4143 "movd\t{$src, $dst|$dst, $src}",
4144 [(store (i32 (vector_extract (v4i32 VR128:$src),
4145 (iPTR 0))), addr:$dst)]>;
4147 //===---------------------------------------------------------------------===//
4148 // Move Packed Doubleword Int first element to Doubleword Int
4150 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4151 "mov{d|q}\t{$src, $dst|$dst, $src}",
4152 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4154 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4156 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4157 "mov{d|q}\t{$src, $dst|$dst, $src}",
4158 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4161 //===---------------------------------------------------------------------===//
4162 // Bitcast FR64 <-> GR64
4164 let Predicates = [HasAVX] in
4165 def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4166 "vmovq\t{$src, $dst|$dst, $src}",
4167 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4169 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4170 "mov{d|q}\t{$src, $dst|$dst, $src}",
4171 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4172 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4173 "movq\t{$src, $dst|$dst, $src}",
4174 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4176 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4177 "movq\t{$src, $dst|$dst, $src}",
4178 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
4179 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4180 "mov{d|q}\t{$src, $dst|$dst, $src}",
4181 [(set GR64:$dst, (bitconvert FR64:$src))]>;
4182 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4183 "movq\t{$src, $dst|$dst, $src}",
4184 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
4186 //===---------------------------------------------------------------------===//
4187 // Move Scalar Single to Double Int
4189 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4190 "movd\t{$src, $dst|$dst, $src}",
4191 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
4192 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4193 "movd\t{$src, $dst|$dst, $src}",
4194 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
4195 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4196 "movd\t{$src, $dst|$dst, $src}",
4197 [(set GR32:$dst, (bitconvert FR32:$src))]>;
4198 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4199 "movd\t{$src, $dst|$dst, $src}",
4200 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
4202 //===---------------------------------------------------------------------===//
4203 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4205 let AddedComplexity = 15 in {
4206 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4207 "movd\t{$src, $dst|$dst, $src}",
4208 [(set VR128:$dst, (v4i32 (X86vzmovl
4209 (v4i32 (scalar_to_vector GR32:$src)))))]>,
4211 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4212 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4213 [(set VR128:$dst, (v2i64 (X86vzmovl
4214 (v2i64 (scalar_to_vector GR64:$src)))))]>,
4217 let AddedComplexity = 15 in {
4218 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4219 "movd\t{$src, $dst|$dst, $src}",
4220 [(set VR128:$dst, (v4i32 (X86vzmovl
4221 (v4i32 (scalar_to_vector GR32:$src)))))]>;
4222 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4223 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4224 [(set VR128:$dst, (v2i64 (X86vzmovl
4225 (v2i64 (scalar_to_vector GR64:$src)))))]>;
4228 let AddedComplexity = 20 in {
4229 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4230 "movd\t{$src, $dst|$dst, $src}",
4232 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4233 (loadi32 addr:$src))))))]>,
4235 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4236 "movd\t{$src, $dst|$dst, $src}",
4238 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4239 (loadi32 addr:$src))))))]>;
4242 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4243 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4244 (MOVZDI2PDIrm addr:$src)>;
4245 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4246 (MOVZDI2PDIrm addr:$src)>;
4247 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4248 (MOVZDI2PDIrm addr:$src)>;
4251 let Predicates = [HasAVX] in {
4252 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4253 let AddedComplexity = 20 in {
4254 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
4255 (VMOVZDI2PDIrm addr:$src)>;
4256 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4257 (VMOVZDI2PDIrm addr:$src)>;
4258 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4259 (VMOVZDI2PDIrm addr:$src)>;
4261 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4262 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4263 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4264 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4265 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4266 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4267 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4270 // These are the correct encodings of the instructions so that we know how to
4271 // read correct assembly, even though we continue to emit the wrong ones for
4272 // compatibility with Darwin's buggy assembler.
4273 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4274 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4275 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4276 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4277 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4278 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4279 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4280 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4281 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4282 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4283 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4284 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4286 //===---------------------------------------------------------------------===//
4287 // SSE2 - Move Quadword
4288 //===---------------------------------------------------------------------===//
4290 //===---------------------------------------------------------------------===//
4291 // Move Quadword Int to Packed Quadword Int
4293 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4294 "vmovq\t{$src, $dst|$dst, $src}",
4296 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4297 VEX, Requires<[HasAVX]>;
4298 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4299 "movq\t{$src, $dst|$dst, $src}",
4301 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4302 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4304 //===---------------------------------------------------------------------===//
4305 // Move Packed Quadword Int to Quadword Int
4307 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4308 "movq\t{$src, $dst|$dst, $src}",
4309 [(store (i64 (vector_extract (v2i64 VR128:$src),
4310 (iPTR 0))), addr:$dst)]>, VEX;
4311 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4312 "movq\t{$src, $dst|$dst, $src}",
4313 [(store (i64 (vector_extract (v2i64 VR128:$src),
4314 (iPTR 0))), addr:$dst)]>;
4316 //===---------------------------------------------------------------------===//
4317 // Store / copy lower 64-bits of a XMM register.
4319 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4320 "movq\t{$src, $dst|$dst, $src}",
4321 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4322 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4323 "movq\t{$src, $dst|$dst, $src}",
4324 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
4326 let AddedComplexity = 20 in
4327 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4328 "vmovq\t{$src, $dst|$dst, $src}",
4330 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4331 (loadi64 addr:$src))))))]>,
4332 XS, VEX, Requires<[HasAVX]>;
4334 let AddedComplexity = 20 in
4335 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4336 "movq\t{$src, $dst|$dst, $src}",
4338 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4339 (loadi64 addr:$src))))))]>,
4340 XS, Requires<[HasSSE2]>;
4342 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4343 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4344 (MOVZQI2PQIrm addr:$src)>;
4345 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4346 (MOVZQI2PQIrm addr:$src)>;
4347 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4350 let Predicates = [HasAVX], AddedComplexity = 20 in {
4351 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4352 (VMOVZQI2PQIrm addr:$src)>;
4353 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4354 (VMOVZQI2PQIrm addr:$src)>;
4355 def : Pat<(v2i64 (X86vzload addr:$src)),
4356 (VMOVZQI2PQIrm addr:$src)>;
4359 //===---------------------------------------------------------------------===//
4360 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4361 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4363 let AddedComplexity = 15 in
4364 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4365 "vmovq\t{$src, $dst|$dst, $src}",
4366 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4367 XS, VEX, Requires<[HasAVX]>;
4368 let AddedComplexity = 15 in
4369 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4370 "movq\t{$src, $dst|$dst, $src}",
4371 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
4372 XS, Requires<[HasSSE2]>;
4374 let AddedComplexity = 20 in
4375 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4376 "vmovq\t{$src, $dst|$dst, $src}",
4377 [(set VR128:$dst, (v2i64 (X86vzmovl
4378 (loadv2i64 addr:$src))))]>,
4379 XS, VEX, Requires<[HasAVX]>;
4380 let AddedComplexity = 20 in {
4381 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4382 "movq\t{$src, $dst|$dst, $src}",
4383 [(set VR128:$dst, (v2i64 (X86vzmovl
4384 (loadv2i64 addr:$src))))]>,
4385 XS, Requires<[HasSSE2]>;
4388 let AddedComplexity = 20 in {
4389 let Predicates = [HasSSE2] in {
4390 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4391 (MOVZPQILo2PQIrm addr:$src)>;
4392 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4393 (MOVZPQILo2PQIrr VR128:$src)>;
4395 let Predicates = [HasAVX] in {
4396 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
4397 (VMOVZPQILo2PQIrm addr:$src)>;
4398 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4399 (VMOVZPQILo2PQIrr VR128:$src)>;
4403 // Instructions to match in the assembler
4404 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4405 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4406 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4407 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4408 // Recognize "movd" with GR64 destination, but encode as a "movq"
4409 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4410 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
4412 // Instructions for the disassembler
4413 // xr = XMM register
4416 let Predicates = [HasAVX] in
4417 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4418 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4419 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4420 "movq\t{$src, $dst|$dst, $src}", []>, XS;
4422 //===---------------------------------------------------------------------===//
4423 // SSE3 - Conversion Instructions
4424 //===---------------------------------------------------------------------===//
4426 // Convert Packed Double FP to Packed DW Integers
4427 let Predicates = [HasAVX] in {
4428 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4429 // register, but the same isn't true when using memory operands instead.
4430 // Provide other assembly rr and rm forms to address this explicitly.
4431 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4432 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4433 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4434 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4437 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4438 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4439 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4440 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4443 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4444 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4445 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4446 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4449 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4450 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4451 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4452 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
4454 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4455 (VCVTPD2DQYrr VR256:$src)>;
4456 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4457 (VCVTPD2DQYrm addr:$src)>;
4459 // Convert Packed DW Integers to Packed Double FP
4460 let Predicates = [HasAVX] in {
4461 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4462 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4463 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4464 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4465 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4466 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4467 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4468 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4471 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4472 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4473 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4474 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
4476 // AVX 256-bit register conversion intrinsics
4477 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4478 (VCVTDQ2PDYrr VR128:$src)>;
4479 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
4480 (VCVTDQ2PDYrm addr:$src)>;
4482 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4483 (VCVTPD2DQYrr VR256:$src)>;
4484 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4485 (VCVTPD2DQYrm addr:$src)>;
4487 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4488 (VCVTDQ2PDYrr VR128:$src)>;
4489 def : Pat<(v4f64 (sint_to_fp (memopv4i32 addr:$src))),
4490 (VCVTDQ2PDYrm addr:$src)>;
4492 //===---------------------------------------------------------------------===//
4493 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4494 //===---------------------------------------------------------------------===//
4495 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4496 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4497 X86MemOperand x86memop> {
4498 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4499 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4500 [(set RC:$dst, (vt (OpNode RC:$src)))]>;
4501 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4502 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4503 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>;
4506 let Predicates = [HasAVX] in {
4507 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4508 v4f32, VR128, memopv4f32, f128mem>, VEX;
4509 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4510 v4f32, VR128, memopv4f32, f128mem>, VEX;
4511 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4512 v8f32, VR256, memopv8f32, f256mem>, VEX;
4513 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4514 v8f32, VR256, memopv8f32, f256mem>, VEX;
4516 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4517 memopv4f32, f128mem>;
4518 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4519 memopv4f32, f128mem>;
4521 let Predicates = [HasSSE3] in {
4522 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4523 (MOVSHDUPrr VR128:$src)>;
4524 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4525 (MOVSHDUPrm addr:$src)>;
4526 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4527 (MOVSLDUPrr VR128:$src)>;
4528 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4529 (MOVSLDUPrm addr:$src)>;
4532 let Predicates = [HasAVX] in {
4533 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4534 (VMOVSHDUPrr VR128:$src)>;
4535 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4536 (VMOVSHDUPrm addr:$src)>;
4537 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4538 (VMOVSLDUPrr VR128:$src)>;
4539 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4540 (VMOVSLDUPrm addr:$src)>;
4541 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4542 (VMOVSHDUPYrr VR256:$src)>;
4543 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4544 (VMOVSHDUPYrm addr:$src)>;
4545 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4546 (VMOVSLDUPYrr VR256:$src)>;
4547 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4548 (VMOVSLDUPYrm addr:$src)>;
4551 //===---------------------------------------------------------------------===//
4552 // SSE3 - Replicate Double FP - MOVDDUP
4553 //===---------------------------------------------------------------------===//
4555 multiclass sse3_replicate_dfp<string OpcodeStr> {
4556 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4557 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4558 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
4559 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4560 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4562 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
4566 // FIXME: Merge with above classe when there're patterns for the ymm version
4567 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4568 let Predicates = [HasAVX] in {
4569 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4570 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4572 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4573 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4578 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4579 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4580 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
4582 let Predicates = [HasSSE3] in {
4583 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4585 (MOVDDUPrm addr:$src)>;
4586 let AddedComplexity = 5 in {
4587 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4588 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4589 (MOVDDUPrm addr:$src)>;
4590 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (MOVDDUPrm addr:$src)>;
4591 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4592 (MOVDDUPrm addr:$src)>;
4594 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4595 (MOVDDUPrm addr:$src)>;
4596 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4597 (MOVDDUPrm addr:$src)>;
4598 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4599 (MOVDDUPrm addr:$src)>;
4600 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4601 (MOVDDUPrm addr:$src)>;
4602 def : Pat<(X86Movddup (bc_v2f64
4603 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4604 (MOVDDUPrm addr:$src)>;
4607 let Predicates = [HasAVX] in {
4608 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
4610 (VMOVDDUPrm addr:$src)>;
4611 let AddedComplexity = 5 in {
4612 def : Pat<(movddup (memopv2f64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4613 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
4614 (VMOVDDUPrm addr:$src)>;
4615 def : Pat<(movddup (memopv2i64 addr:$src), (undef)), (VMOVDDUPrm addr:$src)>;
4616 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
4617 (VMOVDDUPrm addr:$src)>;
4619 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4620 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4621 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4622 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4623 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4624 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4625 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
4626 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4627 def : Pat<(X86Movddup (bc_v2f64
4628 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4629 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4632 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4633 (VMOVDDUPYrm addr:$src)>;
4634 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4635 (VMOVDDUPYrm addr:$src)>;
4636 def : Pat<(X86Movddup (v4f64 (scalar_to_vector (loadf64 addr:$src)))),
4637 (VMOVDDUPYrm addr:$src)>;
4638 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4639 (VMOVDDUPYrm addr:$src)>;
4640 def : Pat<(X86Movddup (v4f64 VR256:$src)),
4641 (VMOVDDUPYrr VR256:$src)>;
4642 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4643 (VMOVDDUPYrr VR256:$src)>;
4646 //===---------------------------------------------------------------------===//
4647 // SSE3 - Move Unaligned Integer
4648 //===---------------------------------------------------------------------===//
4650 let Predicates = [HasAVX] in {
4651 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4652 "vlddqu\t{$src, $dst|$dst, $src}",
4653 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4654 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4655 "vlddqu\t{$src, $dst|$dst, $src}",
4656 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
4658 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4659 "lddqu\t{$src, $dst|$dst, $src}",
4660 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
4662 //===---------------------------------------------------------------------===//
4663 // SSE3 - Arithmetic
4664 //===---------------------------------------------------------------------===//
4666 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4667 X86MemOperand x86memop, bit Is2Addr = 1> {
4668 def rr : I<0xD0, MRMSrcReg,
4669 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4671 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4672 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4673 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
4674 def rm : I<0xD0, MRMSrcMem,
4675 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4677 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4678 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4679 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
4682 let Predicates = [HasAVX],
4683 ExeDomain = SSEPackedDouble in {
4684 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4685 f128mem, 0>, TB, XD, VEX_4V;
4686 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4687 f128mem, 0>, TB, OpSize, VEX_4V;
4688 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4689 f256mem, 0>, TB, XD, VEX_4V;
4690 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4691 f256mem, 0>, TB, OpSize, VEX_4V;
4693 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
4694 ExeDomain = SSEPackedDouble in {
4695 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4697 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4698 f128mem>, TB, OpSize;
4701 //===---------------------------------------------------------------------===//
4702 // SSE3 Instructions
4703 //===---------------------------------------------------------------------===//
4706 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4707 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4708 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4710 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4711 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4712 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
4714 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4716 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4717 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4718 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
4720 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4721 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4722 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4724 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4725 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4726 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))]>;
4728 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4730 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4731 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4732 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))]>;
4735 let Predicates = [HasAVX] in {
4736 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
4737 X86fhadd, 0>, VEX_4V;
4738 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
4739 X86fhadd, 0>, VEX_4V;
4740 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
4741 X86fhsub, 0>, VEX_4V;
4742 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
4743 X86fhsub, 0>, VEX_4V;
4744 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
4745 X86fhadd, 0>, VEX_4V;
4746 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
4747 X86fhadd, 0>, VEX_4V;
4748 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
4749 X86fhsub, 0>, VEX_4V;
4750 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
4751 X86fhsub, 0>, VEX_4V;
4754 let Constraints = "$src1 = $dst" in {
4755 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
4756 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
4757 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
4758 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
4761 //===---------------------------------------------------------------------===//
4762 // SSSE3 - Packed Absolute Instructions
4763 //===---------------------------------------------------------------------===//
4766 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
4767 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
4768 PatFrag mem_frag128, Intrinsic IntId128> {
4769 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4771 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4772 [(set VR128:$dst, (IntId128 VR128:$src))]>,
4775 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4777 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4780 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
4783 let Predicates = [HasAVX] in {
4784 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
4785 int_x86_ssse3_pabs_b_128>, VEX;
4786 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
4787 int_x86_ssse3_pabs_w_128>, VEX;
4788 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
4789 int_x86_ssse3_pabs_d_128>, VEX;
4792 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
4793 int_x86_ssse3_pabs_b_128>;
4794 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
4795 int_x86_ssse3_pabs_w_128>;
4796 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
4797 int_x86_ssse3_pabs_d_128>;
4799 //===---------------------------------------------------------------------===//
4800 // SSSE3 - Packed Binary Operator Instructions
4801 //===---------------------------------------------------------------------===//
4803 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
4804 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
4805 PatFrag mem_frag128, Intrinsic IntId128,
4807 let isCommutable = 1 in
4808 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
4809 (ins VR128:$src1, VR128:$src2),
4811 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4812 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4813 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4815 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
4816 (ins VR128:$src1, i128mem:$src2),
4818 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4819 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4821 (IntId128 VR128:$src1,
4822 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4825 let ImmT = NoImm, Predicates = [HasAVX] in {
4826 let isCommutable = 0 in {
4827 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
4828 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
4829 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
4830 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
4831 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
4832 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
4833 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
4834 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
4835 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
4836 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
4837 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
4838 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
4839 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
4840 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
4841 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
4842 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
4843 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
4844 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
4845 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
4846 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
4847 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
4848 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
4850 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
4851 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
4854 // None of these have i8 immediate fields.
4855 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
4856 let isCommutable = 0 in {
4857 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
4858 int_x86_ssse3_phadd_w_128>;
4859 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
4860 int_x86_ssse3_phadd_d_128>;
4861 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
4862 int_x86_ssse3_phadd_sw_128>;
4863 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
4864 int_x86_ssse3_phsub_w_128>;
4865 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
4866 int_x86_ssse3_phsub_d_128>;
4867 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
4868 int_x86_ssse3_phsub_sw_128>;
4869 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
4870 int_x86_ssse3_pmadd_ub_sw_128>;
4871 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
4872 int_x86_ssse3_pshuf_b_128>;
4873 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
4874 int_x86_ssse3_psign_b_128>;
4875 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
4876 int_x86_ssse3_psign_w_128>;
4877 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
4878 int_x86_ssse3_psign_d_128>;
4880 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
4881 int_x86_ssse3_pmul_hr_sw_128>;
4884 let Predicates = [HasSSSE3] in {
4885 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4886 (PSHUFBrr128 VR128:$src, VR128:$mask)>;
4887 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4888 (PSHUFBrm128 VR128:$src, addr:$mask)>;
4890 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4891 (PSIGNBrr128 VR128:$src1, VR128:$src2)>;
4892 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4893 (PSIGNWrr128 VR128:$src1, VR128:$src2)>;
4894 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4895 (PSIGNDrr128 VR128:$src1, VR128:$src2)>;
4898 let Predicates = [HasAVX] in {
4899 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
4900 (VPSHUFBrr128 VR128:$src, VR128:$mask)>;
4901 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
4902 (VPSHUFBrm128 VR128:$src, addr:$mask)>;
4904 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
4905 (VPSIGNBrr128 VR128:$src1, VR128:$src2)>;
4906 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
4907 (VPSIGNWrr128 VR128:$src1, VR128:$src2)>;
4908 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
4909 (VPSIGNDrr128 VR128:$src1, VR128:$src2)>;
4912 //===---------------------------------------------------------------------===//
4913 // SSSE3 - Packed Align Instruction Patterns
4914 //===---------------------------------------------------------------------===//
4916 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
4917 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
4918 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4920 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4922 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4924 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
4925 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4927 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4929 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4933 let Predicates = [HasAVX] in
4934 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
4935 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
4936 defm PALIGN : ssse3_palign<"palignr">;
4938 let Predicates = [HasSSSE3] in {
4939 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4940 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4941 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4942 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4943 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4944 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4945 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4946 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4949 let Predicates = [HasAVX] in {
4950 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4951 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4952 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4953 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4954 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4955 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4956 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
4957 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
4960 //===---------------------------------------------------------------------===//
4961 // SSSE3 - Thread synchronization
4962 //===---------------------------------------------------------------------===//
4964 let usesCustomInserter = 1 in {
4965 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
4966 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
4967 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
4968 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
4971 let Uses = [EAX, ECX, EDX] in
4972 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
4973 Requires<[HasSSE3]>;
4974 let Uses = [ECX, EAX] in
4975 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
4976 Requires<[HasSSE3]>;
4978 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
4979 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
4981 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
4982 Requires<[In32BitMode]>;
4983 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
4984 Requires<[In64BitMode]>;
4986 //===----------------------------------------------------------------------===//
4987 // SSE4.1 - Packed Move with Sign/Zero Extend
4988 //===----------------------------------------------------------------------===//
4990 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4991 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4992 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4993 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4995 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4996 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4998 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5002 let Predicates = [HasAVX] in {
5003 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5005 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5007 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5009 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5011 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5013 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5017 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5018 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5019 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5020 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5021 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5022 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5024 let Predicates = [HasSSE41] in {
5025 // Common patterns involving scalar load.
5026 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5027 (PMOVSXBWrm addr:$src)>;
5028 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5029 (PMOVSXBWrm addr:$src)>;
5031 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5032 (PMOVSXWDrm addr:$src)>;
5033 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5034 (PMOVSXWDrm addr:$src)>;
5036 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5037 (PMOVSXDQrm addr:$src)>;
5038 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5039 (PMOVSXDQrm addr:$src)>;
5041 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5042 (PMOVZXBWrm addr:$src)>;
5043 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5044 (PMOVZXBWrm addr:$src)>;
5046 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5047 (PMOVZXWDrm addr:$src)>;
5048 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5049 (PMOVZXWDrm addr:$src)>;
5051 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5052 (PMOVZXDQrm addr:$src)>;
5053 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5054 (PMOVZXDQrm addr:$src)>;
5057 let Predicates = [HasAVX] in {
5058 // Common patterns involving scalar load.
5059 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5060 (VPMOVSXBWrm addr:$src)>;
5061 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5062 (VPMOVSXBWrm addr:$src)>;
5064 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5065 (VPMOVSXWDrm addr:$src)>;
5066 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5067 (VPMOVSXWDrm addr:$src)>;
5069 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5070 (VPMOVSXDQrm addr:$src)>;
5071 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5072 (VPMOVSXDQrm addr:$src)>;
5074 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5075 (VPMOVZXBWrm addr:$src)>;
5076 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5077 (VPMOVZXBWrm addr:$src)>;
5079 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5080 (VPMOVZXWDrm addr:$src)>;
5081 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5082 (VPMOVZXWDrm addr:$src)>;
5084 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5085 (VPMOVZXDQrm addr:$src)>;
5086 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5087 (VPMOVZXDQrm addr:$src)>;
5091 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5092 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5093 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5094 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5096 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5097 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5099 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5103 let Predicates = [HasAVX] in {
5104 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5106 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5108 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5110 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5114 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5115 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5116 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5117 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5119 let Predicates = [HasSSE41] in {
5120 // Common patterns involving scalar load
5121 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5122 (PMOVSXBDrm addr:$src)>;
5123 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5124 (PMOVSXWQrm addr:$src)>;
5126 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5127 (PMOVZXBDrm addr:$src)>;
5128 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5129 (PMOVZXWQrm addr:$src)>;
5132 let Predicates = [HasAVX] in {
5133 // Common patterns involving scalar load
5134 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5135 (VPMOVSXBDrm addr:$src)>;
5136 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5137 (VPMOVSXWQrm addr:$src)>;
5139 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5140 (VPMOVZXBDrm addr:$src)>;
5141 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5142 (VPMOVZXWQrm addr:$src)>;
5145 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5146 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5147 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5148 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5150 // Expecting a i16 load any extended to i32 value.
5151 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5152 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5153 [(set VR128:$dst, (IntId (bitconvert
5154 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5158 let Predicates = [HasAVX] in {
5159 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5161 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5164 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5165 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5167 let Predicates = [HasSSE41] in {
5168 // Common patterns involving scalar load
5169 def : Pat<(int_x86_sse41_pmovsxbq
5170 (bitconvert (v4i32 (X86vzmovl
5171 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5172 (PMOVSXBQrm addr:$src)>;
5174 def : Pat<(int_x86_sse41_pmovzxbq
5175 (bitconvert (v4i32 (X86vzmovl
5176 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5177 (PMOVZXBQrm addr:$src)>;
5180 let Predicates = [HasAVX] in {
5181 // Common patterns involving scalar load
5182 def : Pat<(int_x86_sse41_pmovsxbq
5183 (bitconvert (v4i32 (X86vzmovl
5184 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5185 (VPMOVSXBQrm addr:$src)>;
5187 def : Pat<(int_x86_sse41_pmovzxbq
5188 (bitconvert (v4i32 (X86vzmovl
5189 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5190 (VPMOVZXBQrm addr:$src)>;
5193 //===----------------------------------------------------------------------===//
5194 // SSE4.1 - Extract Instructions
5195 //===----------------------------------------------------------------------===//
5197 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5198 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5199 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5200 (ins VR128:$src1, i32i8imm:$src2),
5201 !strconcat(OpcodeStr,
5202 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5203 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5205 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5206 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5207 !strconcat(OpcodeStr,
5208 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5211 // There's an AssertZext in the way of writing the store pattern
5212 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5215 let Predicates = [HasAVX] in {
5216 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5217 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5218 (ins VR128:$src1, i32i8imm:$src2),
5219 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5222 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5225 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5226 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5227 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5228 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5229 !strconcat(OpcodeStr,
5230 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5233 // There's an AssertZext in the way of writing the store pattern
5234 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5237 let Predicates = [HasAVX] in
5238 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5240 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5243 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5244 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5245 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5246 (ins VR128:$src1, i32i8imm:$src2),
5247 !strconcat(OpcodeStr,
5248 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5250 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5251 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5252 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5253 !strconcat(OpcodeStr,
5254 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5255 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5256 addr:$dst)]>, OpSize;
5259 let Predicates = [HasAVX] in
5260 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5262 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5264 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5265 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5266 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5267 (ins VR128:$src1, i32i8imm:$src2),
5268 !strconcat(OpcodeStr,
5269 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5271 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5272 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5273 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5274 !strconcat(OpcodeStr,
5275 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5276 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5277 addr:$dst)]>, OpSize, REX_W;
5280 let Predicates = [HasAVX] in
5281 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5283 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5285 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5287 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5288 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5289 (ins VR128:$src1, i32i8imm:$src2),
5290 !strconcat(OpcodeStr,
5291 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5293 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5295 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5296 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5297 !strconcat(OpcodeStr,
5298 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5299 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5300 addr:$dst)]>, OpSize;
5303 let Predicates = [HasAVX] in {
5304 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5305 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5306 (ins VR128:$src1, i32i8imm:$src2),
5307 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5310 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5312 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5313 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5316 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5317 Requires<[HasSSE41]>;
5318 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5321 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5324 //===----------------------------------------------------------------------===//
5325 // SSE4.1 - Insert Instructions
5326 //===----------------------------------------------------------------------===//
5328 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5329 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5330 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5332 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5334 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5336 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5337 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5338 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
5340 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5342 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5344 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
5345 imm:$src3))]>, OpSize;
5348 let Predicates = [HasAVX] in
5349 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
5350 let Constraints = "$src1 = $dst" in
5351 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
5353 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
5354 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5355 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5357 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5359 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5361 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
5363 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5364 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
5366 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5368 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5370 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
5371 imm:$src3)))]>, OpSize;
5374 let Predicates = [HasAVX] in
5375 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
5376 let Constraints = "$src1 = $dst" in
5377 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
5379 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
5380 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5381 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
5383 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5385 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5387 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
5389 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5390 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
5392 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5394 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5396 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
5397 imm:$src3)))]>, OpSize;
5400 let Predicates = [HasAVX] in
5401 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
5402 let Constraints = "$src1 = $dst" in
5403 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
5405 // insertps has a few different modes, there's the first two here below which
5406 // are optimized inserts that won't zero arbitrary elements in the destination
5407 // vector. The next one matches the intrinsic and could zero arbitrary elements
5408 // in the target vector.
5409 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
5410 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5411 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
5413 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5415 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5417 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
5419 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5420 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
5422 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5424 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5426 (X86insrtps VR128:$src1,
5427 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
5428 imm:$src3))]>, OpSize;
5431 let Constraints = "$src1 = $dst" in
5432 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
5433 let Predicates = [HasAVX] in
5434 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
5436 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5437 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5439 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
5440 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
5441 Requires<[HasSSE41]>;
5443 //===----------------------------------------------------------------------===//
5444 // SSE4.1 - Round Instructions
5445 //===----------------------------------------------------------------------===//
5447 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
5448 X86MemOperand x86memop, RegisterClass RC,
5449 PatFrag mem_frag32, PatFrag mem_frag64,
5450 Intrinsic V4F32Int, Intrinsic V2F64Int> {
5451 // Intrinsic operation, reg.
5452 // Vector intrinsic operation, reg
5453 def PSr : SS4AIi8<opcps, MRMSrcReg,
5454 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5455 !strconcat(OpcodeStr,
5456 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5457 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
5460 // Vector intrinsic operation, mem
5461 def PSm : Ii8<opcps, MRMSrcMem,
5462 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5463 !strconcat(OpcodeStr,
5464 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5466 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
5468 Requires<[HasSSE41]>;
5470 // Vector intrinsic operation, reg
5471 def PDr : SS4AIi8<opcpd, MRMSrcReg,
5472 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5473 !strconcat(OpcodeStr,
5474 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5475 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
5478 // Vector intrinsic operation, mem
5479 def PDm : SS4AIi8<opcpd, MRMSrcMem,
5480 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5481 !strconcat(OpcodeStr,
5482 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5484 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
5488 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
5489 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
5490 // Intrinsic operation, reg.
5491 // Vector intrinsic operation, reg
5492 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
5493 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5494 !strconcat(OpcodeStr,
5495 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5498 // Vector intrinsic operation, mem
5499 def PSm_AVX : Ii8<opcps, MRMSrcMem,
5500 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5501 !strconcat(OpcodeStr,
5502 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5503 []>, TA, OpSize, Requires<[HasSSE41]>;
5505 // Vector intrinsic operation, reg
5506 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
5507 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
5508 !strconcat(OpcodeStr,
5509 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5512 // Vector intrinsic operation, mem
5513 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
5514 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
5515 !strconcat(OpcodeStr,
5516 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5520 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
5523 Intrinsic F64Int, bit Is2Addr = 1> {
5524 // Intrinsic operation, reg.
5525 def SSr : SS4AIi8<opcss, MRMSrcReg,
5526 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5528 !strconcat(OpcodeStr,
5529 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5530 !strconcat(OpcodeStr,
5531 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5532 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5535 // Intrinsic operation, mem.
5536 def SSm : SS4AIi8<opcss, MRMSrcMem,
5537 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5539 !strconcat(OpcodeStr,
5540 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5541 !strconcat(OpcodeStr,
5542 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5544 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
5547 // Intrinsic operation, reg.
5548 def SDr : SS4AIi8<opcsd, MRMSrcReg,
5549 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5551 !strconcat(OpcodeStr,
5552 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5553 !strconcat(OpcodeStr,
5554 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5555 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
5558 // Intrinsic operation, mem.
5559 def SDm : SS4AIi8<opcsd, MRMSrcMem,
5560 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5562 !strconcat(OpcodeStr,
5563 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5564 !strconcat(OpcodeStr,
5565 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5567 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
5571 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
5573 // Intrinsic operation, reg.
5574 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
5575 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5576 !strconcat(OpcodeStr,
5577 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5580 // Intrinsic operation, mem.
5581 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
5582 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
5583 !strconcat(OpcodeStr,
5584 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5587 // Intrinsic operation, reg.
5588 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
5589 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
5590 !strconcat(OpcodeStr,
5591 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5594 // Intrinsic operation, mem.
5595 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
5596 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
5597 !strconcat(OpcodeStr,
5598 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5602 // FP round - roundss, roundps, roundsd, roundpd
5603 let Predicates = [HasAVX] in {
5605 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
5606 memopv4f32, memopv2f64,
5607 int_x86_sse41_round_ps,
5608 int_x86_sse41_round_pd>, VEX;
5609 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
5610 memopv8f32, memopv4f64,
5611 int_x86_avx_round_ps_256,
5612 int_x86_avx_round_pd_256>, VEX;
5613 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
5614 int_x86_sse41_round_ss,
5615 int_x86_sse41_round_sd, 0>, VEX_4V;
5617 // Instructions for the assembler
5618 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
5620 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
5622 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
5625 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
5626 memopv4f32, memopv2f64,
5627 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
5628 let Constraints = "$src1 = $dst" in
5629 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
5630 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
5632 //===----------------------------------------------------------------------===//
5633 // SSE4.1 - Packed Bit Test
5634 //===----------------------------------------------------------------------===//
5636 // ptest instruction we'll lower to this in X86ISelLowering primarily from
5637 // the intel intrinsic that corresponds to this.
5638 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5639 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5640 "vptest\t{$src2, $src1|$src1, $src2}",
5641 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5643 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5644 "vptest\t{$src2, $src1|$src1, $src2}",
5645 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5648 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
5649 "vptest\t{$src2, $src1|$src1, $src2}",
5650 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
5652 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
5653 "vptest\t{$src2, $src1|$src1, $src2}",
5654 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
5658 let Defs = [EFLAGS] in {
5659 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
5660 "ptest \t{$src2, $src1|$src1, $src2}",
5661 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
5663 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
5664 "ptest \t{$src2, $src1|$src1, $src2}",
5665 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
5669 // The bit test instructions below are AVX only
5670 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
5671 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
5672 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
5673 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5674 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
5675 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
5676 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
5677 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
5681 let Defs = [EFLAGS], Predicates = [HasAVX] in {
5682 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
5683 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
5684 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
5685 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
5688 //===----------------------------------------------------------------------===//
5689 // SSE4.1 - Misc Instructions
5690 //===----------------------------------------------------------------------===//
5692 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
5693 "popcnt{w}\t{$src, $dst|$dst, $src}",
5694 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
5695 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
5696 "popcnt{w}\t{$src, $dst|$dst, $src}",
5697 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
5699 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
5700 "popcnt{l}\t{$src, $dst|$dst, $src}",
5701 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
5702 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
5703 "popcnt{l}\t{$src, $dst|$dst, $src}",
5704 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
5706 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
5707 "popcnt{q}\t{$src, $dst|$dst, $src}",
5708 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
5709 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
5710 "popcnt{q}\t{$src, $dst|$dst, $src}",
5711 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
5715 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
5716 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
5717 Intrinsic IntId128> {
5718 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5720 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5721 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
5722 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5724 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5727 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
5730 let Predicates = [HasAVX] in
5731 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
5732 int_x86_sse41_phminposuw>, VEX;
5733 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
5734 int_x86_sse41_phminposuw>;
5736 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
5737 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
5738 Intrinsic IntId128, bit Is2Addr = 1> {
5739 let isCommutable = 1 in
5740 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5741 (ins VR128:$src1, VR128:$src2),
5743 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5744 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5745 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
5746 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5747 (ins VR128:$src1, i128mem:$src2),
5749 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5750 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5752 (IntId128 VR128:$src1,
5753 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5756 let Predicates = [HasAVX] in {
5757 let isCommutable = 0 in
5758 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
5760 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
5762 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
5764 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
5766 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
5768 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
5770 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
5772 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
5774 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
5776 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
5778 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
5781 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5782 (VPCMPEQQrr VR128:$src1, VR128:$src2)>;
5783 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5784 (VPCMPEQQrm VR128:$src1, addr:$src2)>;
5787 let Constraints = "$src1 = $dst" in {
5788 let isCommutable = 0 in
5789 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
5790 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
5791 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
5792 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
5793 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
5794 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
5795 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
5796 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
5797 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
5798 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
5799 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
5802 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
5803 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
5804 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
5805 (PCMPEQQrm VR128:$src1, addr:$src2)>;
5807 /// SS48I_binop_rm - Simple SSE41 binary operator.
5808 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5809 ValueType OpVT, bit Is2Addr = 1> {
5810 let isCommutable = 1 in
5811 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5812 (ins VR128:$src1, VR128:$src2),
5814 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5815 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5816 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
5818 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5819 (ins VR128:$src1, i128mem:$src2),
5821 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5822 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5823 [(set VR128:$dst, (OpNode VR128:$src1,
5824 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
5828 let Predicates = [HasAVX] in
5829 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
5830 let Constraints = "$src1 = $dst" in
5831 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
5833 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
5834 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
5835 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
5836 X86MemOperand x86memop, bit Is2Addr = 1> {
5837 let isCommutable = 1 in
5838 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
5839 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
5841 !strconcat(OpcodeStr,
5842 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5843 !strconcat(OpcodeStr,
5844 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5845 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
5847 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
5848 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
5850 !strconcat(OpcodeStr,
5851 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5852 !strconcat(OpcodeStr,
5853 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5856 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
5860 let Predicates = [HasAVX] in {
5861 let isCommutable = 0 in {
5862 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
5863 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5864 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
5865 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5866 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
5867 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5868 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
5869 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
5870 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
5871 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5872 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
5873 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5875 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
5876 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5877 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
5878 VR128, memopv16i8, i128mem, 0>, VEX_4V;
5879 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
5880 VR256, memopv32i8, i256mem, 0>, VEX_4V;
5883 let Constraints = "$src1 = $dst" in {
5884 let isCommutable = 0 in {
5885 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
5886 VR128, memopv16i8, i128mem>;
5887 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
5888 VR128, memopv16i8, i128mem>;
5889 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
5890 VR128, memopv16i8, i128mem>;
5891 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
5892 VR128, memopv16i8, i128mem>;
5894 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
5895 VR128, memopv16i8, i128mem>;
5896 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
5897 VR128, memopv16i8, i128mem>;
5900 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
5901 let Predicates = [HasAVX] in {
5902 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
5903 RegisterClass RC, X86MemOperand x86memop,
5904 PatFrag mem_frag, Intrinsic IntId> {
5905 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
5906 (ins RC:$src1, RC:$src2, RC:$src3),
5907 !strconcat(OpcodeStr,
5908 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5909 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
5910 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5912 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
5913 (ins RC:$src1, x86memop:$src2, RC:$src3),
5914 !strconcat(OpcodeStr,
5915 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5917 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
5919 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
5923 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
5924 memopv16i8, int_x86_sse41_blendvpd>;
5925 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
5926 memopv16i8, int_x86_sse41_blendvps>;
5927 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
5928 memopv16i8, int_x86_sse41_pblendvb>;
5929 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
5930 memopv32i8, int_x86_avx_blendv_pd_256>;
5931 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
5932 memopv32i8, int_x86_avx_blendv_ps_256>;
5934 let Predicates = [HasAVX] in {
5935 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
5936 (v16i8 VR128:$src2))),
5937 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5938 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
5939 (v4i32 VR128:$src2))),
5940 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5941 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
5942 (v4f32 VR128:$src2))),
5943 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5944 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
5945 (v2i64 VR128:$src2))),
5946 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5947 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
5948 (v2f64 VR128:$src2))),
5949 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
5950 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
5951 (v8i32 VR256:$src2))),
5952 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5953 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
5954 (v8f32 VR256:$src2))),
5955 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5956 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
5957 (v4i64 VR256:$src2))),
5958 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5959 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
5960 (v4f64 VR256:$src2))),
5961 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
5964 /// SS41I_ternary_int - SSE 4.1 ternary operator
5965 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
5966 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5967 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
5968 (ins VR128:$src1, VR128:$src2),
5969 !strconcat(OpcodeStr,
5970 "\t{$src2, $dst|$dst, $src2}"),
5971 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
5974 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
5975 (ins VR128:$src1, i128mem:$src2),
5976 !strconcat(OpcodeStr,
5977 "\t{$src2, $dst|$dst, $src2}"),
5980 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
5984 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
5985 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
5986 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
5988 let Predicates = [HasSSE41] in {
5989 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
5990 (v16i8 VR128:$src2))),
5991 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
5992 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
5993 (v4i32 VR128:$src2))),
5994 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
5995 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
5996 (v4f32 VR128:$src2))),
5997 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
5998 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
5999 (v2i64 VR128:$src2))),
6000 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6001 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6002 (v2f64 VR128:$src2))),
6003 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6006 let Predicates = [HasAVX] in
6007 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6008 "vmovntdqa\t{$src, $dst|$dst, $src}",
6009 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6011 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6012 "movntdqa\t{$src, $dst|$dst, $src}",
6013 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6016 //===----------------------------------------------------------------------===//
6017 // SSE4.2 - Compare Instructions
6018 //===----------------------------------------------------------------------===//
6020 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
6021 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
6022 Intrinsic IntId128, bit Is2Addr = 1> {
6023 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
6024 (ins VR128:$src1, VR128:$src2),
6026 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6027 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6028 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6030 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
6031 (ins VR128:$src1, i128mem:$src2),
6033 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6034 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6036 (IntId128 VR128:$src1,
6037 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6040 let Predicates = [HasAVX] in {
6041 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
6044 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6045 (VPCMPGTQrr VR128:$src1, VR128:$src2)>;
6046 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6047 (VPCMPGTQrm VR128:$src1, addr:$src2)>;
6050 let Constraints = "$src1 = $dst" in
6051 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
6053 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
6054 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
6055 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
6056 (PCMPGTQrm VR128:$src1, addr:$src2)>;
6058 //===----------------------------------------------------------------------===//
6059 // SSE4.2 - String/text Processing Instructions
6060 //===----------------------------------------------------------------------===//
6062 // Packed Compare Implicit Length Strings, Return Mask
6063 multiclass pseudo_pcmpistrm<string asm> {
6064 def REG : PseudoI<(outs VR128:$dst),
6065 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6066 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6068 def MEM : PseudoI<(outs VR128:$dst),
6069 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6070 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6071 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6074 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6075 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6076 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6079 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
6080 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6081 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6082 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6083 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6084 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6085 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6088 let Defs = [XMM0, EFLAGS] in {
6089 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6090 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6091 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6092 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6093 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6094 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6097 // Packed Compare Explicit Length Strings, Return Mask
6098 multiclass pseudo_pcmpestrm<string asm> {
6099 def REG : PseudoI<(outs VR128:$dst),
6100 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6101 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6102 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6103 def MEM : PseudoI<(outs VR128:$dst),
6104 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6105 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6106 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6109 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6110 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6111 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6114 let Predicates = [HasAVX],
6115 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
6116 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6117 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6118 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6119 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6120 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6121 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6124 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
6125 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6126 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6127 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6128 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6129 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6130 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6133 // Packed Compare Implicit Length Strings, Return Index
6134 let Defs = [ECX, EFLAGS] in {
6135 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6136 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6137 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6138 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6139 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6140 (implicit EFLAGS)]>, OpSize;
6141 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6142 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6143 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6144 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6145 (implicit EFLAGS)]>, OpSize;
6149 let Predicates = [HasAVX] in {
6150 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6152 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6154 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6156 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6158 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6160 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6164 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6165 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6166 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6167 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6168 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6169 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6171 // Packed Compare Explicit Length Strings, Return Index
6172 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6173 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6174 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6175 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6176 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6177 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6178 (implicit EFLAGS)]>, OpSize;
6179 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6180 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6181 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6183 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6184 (implicit EFLAGS)]>, OpSize;
6188 let Predicates = [HasAVX] in {
6189 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6191 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6193 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6195 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6197 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6199 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6203 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6204 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6205 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6206 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6207 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6208 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6210 //===----------------------------------------------------------------------===//
6211 // SSE4.2 - CRC Instructions
6212 //===----------------------------------------------------------------------===//
6214 // No CRC instructions have AVX equivalents
6216 // crc intrinsic instruction
6217 // This set of instructions are only rm, the only difference is the size
6219 let Constraints = "$src1 = $dst" in {
6220 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
6221 (ins GR32:$src1, i8mem:$src2),
6222 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6224 (int_x86_sse42_crc32_32_8 GR32:$src1,
6225 (load addr:$src2)))]>;
6226 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
6227 (ins GR32:$src1, GR8:$src2),
6228 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6230 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
6231 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6232 (ins GR32:$src1, i16mem:$src2),
6233 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6235 (int_x86_sse42_crc32_32_16 GR32:$src1,
6236 (load addr:$src2)))]>,
6238 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6239 (ins GR32:$src1, GR16:$src2),
6240 "crc32{w} \t{$src2, $src1|$src1, $src2}",
6242 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
6244 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
6245 (ins GR32:$src1, i32mem:$src2),
6246 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6248 (int_x86_sse42_crc32_32_32 GR32:$src1,
6249 (load addr:$src2)))]>;
6250 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
6251 (ins GR32:$src1, GR32:$src2),
6252 "crc32{l} \t{$src2, $src1|$src1, $src2}",
6254 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
6255 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
6256 (ins GR64:$src1, i8mem:$src2),
6257 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6259 (int_x86_sse42_crc32_64_8 GR64:$src1,
6260 (load addr:$src2)))]>,
6262 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
6263 (ins GR64:$src1, GR8:$src2),
6264 "crc32{b} \t{$src2, $src1|$src1, $src2}",
6266 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
6268 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
6269 (ins GR64:$src1, i64mem:$src2),
6270 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6272 (int_x86_sse42_crc32_64_64 GR64:$src1,
6273 (load addr:$src2)))]>,
6275 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
6276 (ins GR64:$src1, GR64:$src2),
6277 "crc32{q} \t{$src2, $src1|$src1, $src2}",
6279 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
6283 //===----------------------------------------------------------------------===//
6284 // AES-NI Instructions
6285 //===----------------------------------------------------------------------===//
6287 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
6288 Intrinsic IntId128, bit Is2Addr = 1> {
6289 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
6290 (ins VR128:$src1, VR128:$src2),
6292 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6293 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6294 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
6296 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
6297 (ins VR128:$src1, i128mem:$src2),
6299 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6300 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6302 (IntId128 VR128:$src1,
6303 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
6306 // Perform One Round of an AES Encryption/Decryption Flow
6307 let Predicates = [HasAVX, HasAES] in {
6308 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
6309 int_x86_aesni_aesenc, 0>, VEX_4V;
6310 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
6311 int_x86_aesni_aesenclast, 0>, VEX_4V;
6312 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
6313 int_x86_aesni_aesdec, 0>, VEX_4V;
6314 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
6315 int_x86_aesni_aesdeclast, 0>, VEX_4V;
6318 let Constraints = "$src1 = $dst" in {
6319 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
6320 int_x86_aesni_aesenc>;
6321 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
6322 int_x86_aesni_aesenclast>;
6323 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
6324 int_x86_aesni_aesdec>;
6325 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
6326 int_x86_aesni_aesdeclast>;
6329 let Predicates = [HasAES] in {
6330 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6331 (AESENCrr VR128:$src1, VR128:$src2)>;
6332 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6333 (AESENCrm VR128:$src1, addr:$src2)>;
6334 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6335 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
6336 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6337 (AESENCLASTrm VR128:$src1, addr:$src2)>;
6338 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6339 (AESDECrr VR128:$src1, VR128:$src2)>;
6340 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6341 (AESDECrm VR128:$src1, addr:$src2)>;
6342 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6343 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
6344 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6345 (AESDECLASTrm VR128:$src1, addr:$src2)>;
6348 let Predicates = [HasAVX, HasAES], AddedComplexity = 20 in {
6349 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
6350 (VAESENCrr VR128:$src1, VR128:$src2)>;
6351 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
6352 (VAESENCrm VR128:$src1, addr:$src2)>;
6353 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
6354 (VAESENCLASTrr VR128:$src1, VR128:$src2)>;
6355 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
6356 (VAESENCLASTrm VR128:$src1, addr:$src2)>;
6357 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
6358 (VAESDECrr VR128:$src1, VR128:$src2)>;
6359 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
6360 (VAESDECrm VR128:$src1, addr:$src2)>;
6361 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
6362 (VAESDECLASTrr VR128:$src1, VR128:$src2)>;
6363 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
6364 (VAESDECLASTrm VR128:$src1, addr:$src2)>;
6367 // Perform the AES InvMixColumn Transformation
6368 let Predicates = [HasAVX, HasAES] in {
6369 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6371 "vaesimc\t{$src1, $dst|$dst, $src1}",
6373 (int_x86_aesni_aesimc VR128:$src1))]>,
6375 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6376 (ins i128mem:$src1),
6377 "vaesimc\t{$src1, $dst|$dst, $src1}",
6379 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6382 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
6384 "aesimc\t{$src1, $dst|$dst, $src1}",
6386 (int_x86_aesni_aesimc VR128:$src1))]>,
6388 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
6389 (ins i128mem:$src1),
6390 "aesimc\t{$src1, $dst|$dst, $src1}",
6392 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
6395 // AES Round Key Generation Assist
6396 let Predicates = [HasAVX, HasAES] in {
6397 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6398 (ins VR128:$src1, i8imm:$src2),
6399 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6401 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6403 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6404 (ins i128mem:$src1, i8imm:$src2),
6405 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6407 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
6411 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
6412 (ins VR128:$src1, i8imm:$src2),
6413 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6415 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
6417 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
6418 (ins i128mem:$src1, i8imm:$src2),
6419 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6421 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
6425 //===----------------------------------------------------------------------===//
6426 // CLMUL Instructions
6427 //===----------------------------------------------------------------------===//
6429 // Carry-less Multiplication instructions
6430 let Constraints = "$src1 = $dst" in {
6431 def PCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6432 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6433 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6436 def PCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6437 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6438 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
6442 // AVX carry-less Multiplication instructions
6443 def VPCLMULQDQrr : AVXCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
6444 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6445 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6448 def VPCLMULQDQrm : AVXCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
6449 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6450 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6454 multiclass pclmul_alias<string asm, int immop> {
6455 def : InstAlias<!strconcat("pclmul", asm,
6456 "dq {$src, $dst|$dst, $src}"),
6457 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
6459 def : InstAlias<!strconcat("pclmul", asm,
6460 "dq {$src, $dst|$dst, $src}"),
6461 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
6463 def : InstAlias<!strconcat("vpclmul", asm,
6464 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6465 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
6467 def : InstAlias<!strconcat("vpclmul", asm,
6468 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
6469 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
6471 defm : pclmul_alias<"hqhq", 0x11>;
6472 defm : pclmul_alias<"hqlq", 0x01>;
6473 defm : pclmul_alias<"lqhq", 0x10>;
6474 defm : pclmul_alias<"lqlq", 0x00>;
6476 //===----------------------------------------------------------------------===//
6478 //===----------------------------------------------------------------------===//
6480 //===----------------------------------------------------------------------===//
6481 // VBROADCAST - Load from memory and broadcast to all elements of the
6482 // destination operand
6484 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
6485 X86MemOperand x86memop, Intrinsic Int> :
6486 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
6487 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6488 [(set RC:$dst, (Int addr:$src))]>, VEX;
6490 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
6491 int_x86_avx_vbroadcastss>;
6492 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
6493 int_x86_avx_vbroadcastss_256>;
6494 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
6495 int_x86_avx_vbroadcast_sd_256>;
6496 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
6497 int_x86_avx_vbroadcastf128_pd_256>;
6499 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
6500 (VBROADCASTF128 addr:$src)>;
6502 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
6503 (VBROADCASTSSY addr:$src)>;
6504 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
6505 (VBROADCASTSD addr:$src)>;
6506 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
6507 (VBROADCASTSSY addr:$src)>;
6508 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
6509 (VBROADCASTSD addr:$src)>;
6511 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
6512 (VBROADCASTSS addr:$src)>;
6513 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
6514 (VBROADCASTSS addr:$src)>;
6516 //===----------------------------------------------------------------------===//
6517 // VINSERTF128 - Insert packed floating-point values
6519 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
6520 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
6521 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6523 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
6524 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
6525 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6528 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
6529 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6530 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
6531 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6532 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
6533 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
6535 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
6537 (VINSERTF128rr VR256:$src1, VR128:$src2,
6538 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6539 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
6541 (VINSERTF128rr VR256:$src1, VR128:$src2,
6542 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6543 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
6545 (VINSERTF128rr VR256:$src1, VR128:$src2,
6546 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6547 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
6549 (VINSERTF128rr VR256:$src1, VR128:$src2,
6550 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6551 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
6553 (VINSERTF128rr VR256:$src1, VR128:$src2,
6554 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6555 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
6557 (VINSERTF128rr VR256:$src1, VR128:$src2,
6558 (INSERT_get_vinsertf128_imm VR256:$ins))>;
6560 //===----------------------------------------------------------------------===//
6561 // VEXTRACTF128 - Extract packed floating-point values
6563 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
6564 (ins VR256:$src1, i8imm:$src2),
6565 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6567 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
6568 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
6569 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6572 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
6573 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6574 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
6575 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6576 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
6577 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
6579 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6580 (v4f32 (VEXTRACTF128rr
6581 (v8f32 VR256:$src1),
6582 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6583 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6584 (v2f64 (VEXTRACTF128rr
6585 (v4f64 VR256:$src1),
6586 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6587 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6588 (v4i32 (VEXTRACTF128rr
6589 (v8i32 VR256:$src1),
6590 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6591 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6592 (v2i64 (VEXTRACTF128rr
6593 (v4i64 VR256:$src1),
6594 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6595 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6596 (v8i16 (VEXTRACTF128rr
6597 (v16i16 VR256:$src1),
6598 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6599 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
6600 (v16i8 (VEXTRACTF128rr
6601 (v32i8 VR256:$src1),
6602 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
6604 //===----------------------------------------------------------------------===//
6605 // VMASKMOV - Conditional SIMD Packed Loads and Stores
6607 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
6608 Intrinsic IntLd, Intrinsic IntLd256,
6609 Intrinsic IntSt, Intrinsic IntSt256,
6610 PatFrag pf128, PatFrag pf256> {
6611 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
6612 (ins VR128:$src1, f128mem:$src2),
6613 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6614 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
6616 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
6617 (ins VR256:$src1, f256mem:$src2),
6618 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6619 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
6621 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
6622 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
6623 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6624 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
6625 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
6626 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
6627 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6628 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
6631 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
6632 int_x86_avx_maskload_ps,
6633 int_x86_avx_maskload_ps_256,
6634 int_x86_avx_maskstore_ps,
6635 int_x86_avx_maskstore_ps_256,
6636 memopv4f32, memopv8f32>;
6637 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
6638 int_x86_avx_maskload_pd,
6639 int_x86_avx_maskload_pd_256,
6640 int_x86_avx_maskstore_pd,
6641 int_x86_avx_maskstore_pd_256,
6642 memopv2f64, memopv4f64>;
6644 //===----------------------------------------------------------------------===//
6645 // VPERMIL - Permute Single and Double Floating-Point Values
6647 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
6648 RegisterClass RC, X86MemOperand x86memop_f,
6649 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
6650 Intrinsic IntVar, Intrinsic IntImm> {
6651 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
6652 (ins RC:$src1, RC:$src2),
6653 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6654 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
6655 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
6656 (ins RC:$src1, x86memop_i:$src2),
6657 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6658 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
6660 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
6661 (ins RC:$src1, i8imm:$src2),
6662 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6663 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
6664 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
6665 (ins x86memop_f:$src1, i8imm:$src2),
6666 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6667 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
6670 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
6671 memopv4f32, memopv4i32,
6672 int_x86_avx_vpermilvar_ps,
6673 int_x86_avx_vpermil_ps>;
6674 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
6675 memopv8f32, memopv8i32,
6676 int_x86_avx_vpermilvar_ps_256,
6677 int_x86_avx_vpermil_ps_256>;
6678 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
6679 memopv2f64, memopv2i64,
6680 int_x86_avx_vpermilvar_pd,
6681 int_x86_avx_vpermil_pd>;
6682 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
6683 memopv4f64, memopv4i64,
6684 int_x86_avx_vpermilvar_pd_256,
6685 int_x86_avx_vpermil_pd_256>;
6687 def : Pat<(v8f32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6688 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6689 def : Pat<(v4f64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6690 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6691 def : Pat<(v8i32 (X86VPermilpsy VR256:$src1, (i8 imm:$imm))),
6692 (VPERMILPSYri VR256:$src1, imm:$imm)>;
6693 def : Pat<(v4i64 (X86VPermilpdy VR256:$src1, (i8 imm:$imm))),
6694 (VPERMILPDYri VR256:$src1, imm:$imm)>;
6696 //===----------------------------------------------------------------------===//
6697 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
6699 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
6700 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
6701 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6703 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
6704 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
6705 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
6708 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
6709 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6710 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
6711 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6712 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
6713 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
6715 def : Pat<(int_x86_avx_vperm2f128_ps_256
6716 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
6717 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6718 def : Pat<(int_x86_avx_vperm2f128_pd_256
6719 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
6720 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6721 def : Pat<(int_x86_avx_vperm2f128_si_256
6722 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
6723 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
6725 def : Pat<(v8f32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6726 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6727 def : Pat<(v8i32 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6728 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6729 def : Pat<(v4i64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6730 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6731 def : Pat<(v4f64 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6732 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6733 def : Pat<(v32i8 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6734 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6735 def : Pat<(v16i16 (X86VPerm2f128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
6736 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
6738 //===----------------------------------------------------------------------===//
6739 // VZERO - Zero YMM registers
6741 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
6742 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
6743 // Zero All YMM registers
6744 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
6745 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
6747 // Zero Upper bits of YMM registers
6748 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
6749 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;