1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<0, 2, [SDTCisVT<0, v4f32>,
74 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
76 //===----------------------------------------------------------------------===//
77 // SSE Complex Patterns
78 //===----------------------------------------------------------------------===//
80 // These are 'extloads' from a scalar to the low element of a vector, zeroing
81 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
83 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
84 [SDNPHasChain, SDNPMayLoad]>;
85 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
86 [SDNPHasChain, SDNPMayLoad]>;
88 def ssmem : Operand<v4f32> {
89 let PrintMethod = "printf32mem";
90 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
91 let ParserMatchClass = X86MemAsmOperand;
93 def sdmem : Operand<v2f64> {
94 let PrintMethod = "printf64mem";
95 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
96 let ParserMatchClass = X86MemAsmOperand;
99 //===----------------------------------------------------------------------===//
100 // SSE pattern fragments
101 //===----------------------------------------------------------------------===//
103 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
104 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
105 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
106 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
108 // Like 'store', but always requires vector alignment.
109 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
110 (store node:$val, node:$ptr), [{
111 return cast<StoreSDNode>(N)->getAlignment() >= 16;
114 // Like 'load', but always requires vector alignment.
115 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
116 return cast<LoadSDNode>(N)->getAlignment() >= 16;
119 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
120 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
121 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
122 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
123 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
124 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
126 // Like 'load', but uses special alignment checks suitable for use in
127 // memory operands in most SSE instructions, which are required to
128 // be naturally aligned on some targets but not on others.
129 // FIXME: Actually implement support for targets that don't require the
130 // alignment. This probably wants a subtarget predicate.
131 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
132 return cast<LoadSDNode>(N)->getAlignment() >= 16;
135 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
136 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
137 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
138 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
139 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
140 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
141 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
143 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
145 // FIXME: 8 byte alignment for mmx reads is not required
146 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
147 return cast<LoadSDNode>(N)->getAlignment() >= 8;
150 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
151 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
152 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
153 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
155 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
156 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
157 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
158 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
159 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
160 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
162 def vzmovl_v2i64 : PatFrag<(ops node:$src),
163 (bitconvert (v2i64 (X86vzmovl
164 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
165 def vzmovl_v4i32 : PatFrag<(ops node:$src),
166 (bitconvert (v4i32 (X86vzmovl
167 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
169 def vzload_v2i64 : PatFrag<(ops node:$src),
170 (bitconvert (v2i64 (X86vzload node:$src)))>;
173 def fp32imm0 : PatLeaf<(f32 fpimm), [{
174 return N->isExactlyValue(+0.0);
177 def PSxLDQ_imm : SDNodeXForm<imm, [{
178 // Transformation function: imm >> 3
179 return getI32Imm(N->getZExtValue() >> 3);
182 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
184 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
185 return getI8Imm(X86::getShuffleSHUFImmediate(N));
188 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
190 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
191 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
194 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
196 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
197 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
200 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
201 (vector_shuffle node:$lhs, node:$rhs), [{
202 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
203 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
206 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
207 (vector_shuffle node:$lhs, node:$rhs), [{
208 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
211 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
212 (vector_shuffle node:$lhs, node:$rhs), [{
213 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
216 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
217 (vector_shuffle node:$lhs, node:$rhs), [{
218 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
221 def movhp : PatFrag<(ops node:$lhs, node:$rhs),
222 (vector_shuffle node:$lhs, node:$rhs), [{
223 return X86::isMOVHPMask(cast<ShuffleVectorSDNode>(N));
226 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
227 (vector_shuffle node:$lhs, node:$rhs), [{
228 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
231 def movl : PatFrag<(ops node:$lhs, node:$rhs),
232 (vector_shuffle node:$lhs, node:$rhs), [{
233 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
236 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
237 (vector_shuffle node:$lhs, node:$rhs), [{
238 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
241 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
242 (vector_shuffle node:$lhs, node:$rhs), [{
243 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
246 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
247 (vector_shuffle node:$lhs, node:$rhs), [{
248 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
251 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
252 (vector_shuffle node:$lhs, node:$rhs), [{
253 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
256 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
257 (vector_shuffle node:$lhs, node:$rhs), [{
258 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
261 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
262 (vector_shuffle node:$lhs, node:$rhs), [{
263 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
266 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
267 (vector_shuffle node:$lhs, node:$rhs), [{
268 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
269 }], SHUFFLE_get_shuf_imm>;
271 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
272 (vector_shuffle node:$lhs, node:$rhs), [{
273 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
274 }], SHUFFLE_get_shuf_imm>;
276 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
277 (vector_shuffle node:$lhs, node:$rhs), [{
278 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
279 }], SHUFFLE_get_pshufhw_imm>;
281 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
282 (vector_shuffle node:$lhs, node:$rhs), [{
283 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
284 }], SHUFFLE_get_pshuflw_imm>;
286 //===----------------------------------------------------------------------===//
287 // SSE scalar FP Instructions
288 //===----------------------------------------------------------------------===//
290 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
291 // scheduler into a branch sequence.
292 // These are expanded by the scheduler.
293 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
294 def CMOV_FR32 : I<0, Pseudo,
295 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
296 "#CMOV_FR32 PSEUDO!",
297 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
299 def CMOV_FR64 : I<0, Pseudo,
300 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
301 "#CMOV_FR64 PSEUDO!",
302 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
304 def CMOV_V4F32 : I<0, Pseudo,
305 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
306 "#CMOV_V4F32 PSEUDO!",
308 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
310 def CMOV_V2F64 : I<0, Pseudo,
311 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
312 "#CMOV_V2F64 PSEUDO!",
314 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
316 def CMOV_V2I64 : I<0, Pseudo,
317 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
318 "#CMOV_V2I64 PSEUDO!",
320 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
324 //===----------------------------------------------------------------------===//
326 //===----------------------------------------------------------------------===//
329 let neverHasSideEffects = 1 in
330 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
331 "movss\t{$src, $dst|$dst, $src}", []>;
332 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
333 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
334 "movss\t{$src, $dst|$dst, $src}",
335 [(set FR32:$dst, (loadf32 addr:$src))]>;
336 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
337 "movss\t{$src, $dst|$dst, $src}",
338 [(store FR32:$src, addr:$dst)]>;
340 // Conversion instructions
341 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
342 "cvttss2si\t{$src, $dst|$dst, $src}",
343 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
344 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
345 "cvttss2si\t{$src, $dst|$dst, $src}",
346 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
347 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
348 "cvtsi2ss\t{$src, $dst|$dst, $src}",
349 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
350 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
351 "cvtsi2ss\t{$src, $dst|$dst, $src}",
352 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
354 // Match intrinsics which expect XMM operand(s).
355 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
356 "cvtss2si\t{$src, $dst|$dst, $src}",
357 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
358 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
359 "cvtss2si\t{$src, $dst|$dst, $src}",
360 [(set GR32:$dst, (int_x86_sse_cvtss2si
361 (load addr:$src)))]>;
363 // Match intrinisics which expect MM and XMM operand(s).
364 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
365 "cvtps2pi\t{$src, $dst|$dst, $src}",
366 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
367 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
368 "cvtps2pi\t{$src, $dst|$dst, $src}",
369 [(set VR64:$dst, (int_x86_sse_cvtps2pi
370 (load addr:$src)))]>;
371 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
372 "cvttps2pi\t{$src, $dst|$dst, $src}",
373 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
374 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
375 "cvttps2pi\t{$src, $dst|$dst, $src}",
376 [(set VR64:$dst, (int_x86_sse_cvttps2pi
377 (load addr:$src)))]>;
378 let Constraints = "$src1 = $dst" in {
379 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
380 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
381 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
382 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
384 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
385 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
386 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
387 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
388 (load addr:$src2)))]>;
391 // Aliases for intrinsics
392 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
393 "cvttss2si\t{$src, $dst|$dst, $src}",
395 (int_x86_sse_cvttss2si VR128:$src))]>;
396 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
397 "cvttss2si\t{$src, $dst|$dst, $src}",
399 (int_x86_sse_cvttss2si(load addr:$src)))]>;
401 let Constraints = "$src1 = $dst" in {
402 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
403 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
404 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
405 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
407 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
408 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
409 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
410 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
411 (loadi32 addr:$src2)))]>;
414 // Comparison instructions
415 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
416 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
417 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
418 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
420 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
421 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
422 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
425 let Defs = [EFLAGS] in {
426 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
427 "ucomiss\t{$src2, $src1|$src1, $src2}",
428 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
429 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
430 "ucomiss\t{$src2, $src1|$src1, $src2}",
431 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
435 // Aliases to match intrinsics which expect XMM operand(s).
436 let Constraints = "$src1 = $dst" in {
437 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
438 (outs VR128:$dst), (ins VR128:$src1, VR128:$src,
440 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
441 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
442 VR128:$src, imm:$cc))]>;
443 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
444 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src,
446 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
447 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
448 (load addr:$src), imm:$cc))]>;
451 let Defs = [EFLAGS] in {
452 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
453 "ucomiss\t{$src2, $src1|$src1, $src2}",
454 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
456 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
457 "ucomiss\t{$src2, $src1|$src1, $src2}",
458 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
461 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
462 "comiss\t{$src2, $src1|$src1, $src2}",
463 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
465 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
466 "comiss\t{$src2, $src1|$src1, $src2}",
467 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
471 // Aliases of packed SSE1 instructions for scalar use. These all have names
472 // that start with 'Fs'.
474 // Alias instructions that map fld0 to pxor for sse.
475 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
476 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
477 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
478 Requires<[HasSSE1]>, TB, OpSize;
480 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
482 let neverHasSideEffects = 1 in
483 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
484 "movaps\t{$src, $dst|$dst, $src}", []>;
486 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
488 let canFoldAsLoad = 1 in
489 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
490 "movaps\t{$src, $dst|$dst, $src}",
491 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
493 // Alias bitwise logical operations using SSE logical ops on packed FP values.
494 let Constraints = "$src1 = $dst" in {
495 let isCommutable = 1 in {
496 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst),
497 (ins FR32:$src1, FR32:$src2),
498 "andps\t{$src2, $dst|$dst, $src2}",
499 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
500 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst),
501 (ins FR32:$src1, FR32:$src2),
502 "orps\t{$src2, $dst|$dst, $src2}",
503 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
504 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst),
505 (ins FR32:$src1, FR32:$src2),
506 "xorps\t{$src2, $dst|$dst, $src2}",
507 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
510 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst),
511 (ins FR32:$src1, f128mem:$src2),
512 "andps\t{$src2, $dst|$dst, $src2}",
513 [(set FR32:$dst, (X86fand FR32:$src1,
514 (memopfsf32 addr:$src2)))]>;
515 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst),
516 (ins FR32:$src1, f128mem:$src2),
517 "orps\t{$src2, $dst|$dst, $src2}",
518 [(set FR32:$dst, (X86for FR32:$src1,
519 (memopfsf32 addr:$src2)))]>;
520 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst),
521 (ins FR32:$src1, f128mem:$src2),
522 "xorps\t{$src2, $dst|$dst, $src2}",
523 [(set FR32:$dst, (X86fxor FR32:$src1,
524 (memopfsf32 addr:$src2)))]>;
526 let neverHasSideEffects = 1 in {
527 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
528 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
529 "andnps\t{$src2, $dst|$dst, $src2}", []>;
531 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
532 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
533 "andnps\t{$src2, $dst|$dst, $src2}", []>;
537 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
539 /// In addition, we also have a special variant of the scalar form here to
540 /// represent the associated intrinsic operation. This form is unlike the
541 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
542 /// and leaves the top elements unmodified (therefore these cannot be commuted).
544 /// These three forms can each be reg+reg or reg+mem, so there are a total of
545 /// six "instructions".
547 let Constraints = "$src1 = $dst" in {
548 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
549 SDNode OpNode, Intrinsic F32Int,
550 bit Commutable = 0> {
551 // Scalar operation, reg+reg.
552 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
553 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
554 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
555 let isCommutable = Commutable;
558 // Scalar operation, reg+mem.
559 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
560 (ins FR32:$src1, f32mem:$src2),
561 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
562 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
564 // Vector operation, reg+reg.
565 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
566 (ins VR128:$src1, VR128:$src2),
567 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
568 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
569 let isCommutable = Commutable;
572 // Vector operation, reg+mem.
573 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
574 (ins VR128:$src1, f128mem:$src2),
575 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
576 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
578 // Intrinsic operation, reg+reg.
579 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
580 (ins VR128:$src1, VR128:$src2),
581 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
582 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]>;
584 // Intrinsic operation, reg+mem.
585 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
586 (ins VR128:$src1, ssmem:$src2),
587 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
588 [(set VR128:$dst, (F32Int VR128:$src1,
589 sse_load_f32:$src2))]>;
593 // Arithmetic instructions
594 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
595 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
596 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
597 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
599 /// sse1_fp_binop_rm - Other SSE1 binops
601 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
602 /// instructions for a full-vector intrinsic form. Operations that map
603 /// onto C operators don't use this form since they just use the plain
604 /// vector form instead of having a separate vector intrinsic form.
606 /// This provides a total of eight "instructions".
608 let Constraints = "$src1 = $dst" in {
609 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
613 bit Commutable = 0> {
615 // Scalar operation, reg+reg.
616 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
617 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
618 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
619 let isCommutable = Commutable;
622 // Scalar operation, reg+mem.
623 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
624 (ins FR32:$src1, f32mem:$src2),
625 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
626 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
628 // Vector operation, reg+reg.
629 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
630 (ins VR128:$src1, VR128:$src2),
631 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
632 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
633 let isCommutable = Commutable;
636 // Vector operation, reg+mem.
637 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
638 (ins VR128:$src1, f128mem:$src2),
639 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
640 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
642 // Intrinsic operation, reg+reg.
643 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
644 (ins VR128:$src1, VR128:$src2),
645 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
646 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
647 let isCommutable = Commutable;
650 // Intrinsic operation, reg+mem.
651 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
652 (ins VR128:$src1, ssmem:$src2),
653 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
654 [(set VR128:$dst, (F32Int VR128:$src1,
655 sse_load_f32:$src2))]>;
657 // Vector intrinsic operation, reg+reg.
658 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
659 (ins VR128:$src1, VR128:$src2),
660 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
661 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
662 let isCommutable = Commutable;
665 // Vector intrinsic operation, reg+mem.
666 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
667 (ins VR128:$src1, f128mem:$src2),
668 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
669 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
673 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
674 int_x86_sse_max_ss, int_x86_sse_max_ps>;
675 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
676 int_x86_sse_min_ss, int_x86_sse_min_ps>;
678 //===----------------------------------------------------------------------===//
679 // SSE packed FP Instructions
682 let neverHasSideEffects = 1 in
683 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
684 "movaps\t{$src, $dst|$dst, $src}", []>;
685 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
686 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
687 "movaps\t{$src, $dst|$dst, $src}",
688 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
690 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
691 "movaps\t{$src, $dst|$dst, $src}",
692 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
694 let neverHasSideEffects = 1 in
695 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
696 "movups\t{$src, $dst|$dst, $src}", []>;
697 let canFoldAsLoad = 1 in
698 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
699 "movups\t{$src, $dst|$dst, $src}",
700 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
701 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
702 "movups\t{$src, $dst|$dst, $src}",
703 [(store (v4f32 VR128:$src), addr:$dst)]>;
705 // Intrinsic forms of MOVUPS load and store
706 let canFoldAsLoad = 1 in
707 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
708 "movups\t{$src, $dst|$dst, $src}",
709 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
710 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
711 "movups\t{$src, $dst|$dst, $src}",
712 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
714 let Constraints = "$src1 = $dst" in {
715 let AddedComplexity = 20 in {
716 def MOVLPSrm : PSI<0x12, MRMSrcMem,
717 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
718 "movlps\t{$src2, $dst|$dst, $src2}",
721 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
722 def MOVHPSrm : PSI<0x16, MRMSrcMem,
723 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
724 "movhps\t{$src2, $dst|$dst, $src2}",
727 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
729 } // Constraints = "$src1 = $dst"
732 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
733 "movlps\t{$src, $dst|$dst, $src}",
734 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
735 (iPTR 0))), addr:$dst)]>;
737 // v2f64 extract element 1 is always custom lowered to unpack high to low
738 // and extract element 0 so the non-store version isn't too horrible.
739 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
740 "movhps\t{$src, $dst|$dst, $src}",
741 [(store (f64 (vector_extract
742 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
743 (undef)), (iPTR 0))), addr:$dst)]>;
745 let Constraints = "$src1 = $dst" in {
746 let AddedComplexity = 20 in {
747 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
748 (ins VR128:$src1, VR128:$src2),
749 "movlhps\t{$src2, $dst|$dst, $src2}",
751 (v4f32 (movhp VR128:$src1, VR128:$src2)))]>;
753 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
754 (ins VR128:$src1, VR128:$src2),
755 "movhlps\t{$src2, $dst|$dst, $src2}",
757 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
759 } // Constraints = "$src1 = $dst"
761 let AddedComplexity = 20 in {
762 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
763 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
764 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
765 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
772 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
774 /// In addition, we also have a special variant of the scalar form here to
775 /// represent the associated intrinsic operation. This form is unlike the
776 /// plain scalar form, in that it takes an entire vector (instead of a
777 /// scalar) and leaves the top elements undefined.
779 /// And, we have a special variant form for a full-vector intrinsic form.
781 /// These four forms can each have a reg or a mem operand, so there are a
782 /// total of eight "instructions".
784 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
788 bit Commutable = 0> {
789 // Scalar operation, reg.
790 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
791 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
792 [(set FR32:$dst, (OpNode FR32:$src))]> {
793 let isCommutable = Commutable;
796 // Scalar operation, mem.
797 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
798 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
799 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
801 // Vector operation, reg.
802 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
803 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
804 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
805 let isCommutable = Commutable;
808 // Vector operation, mem.
809 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
810 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
811 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
813 // Intrinsic operation, reg.
814 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
815 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
816 [(set VR128:$dst, (F32Int VR128:$src))]> {
817 let isCommutable = Commutable;
820 // Intrinsic operation, mem.
821 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
822 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
823 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
825 // Vector intrinsic operation, reg
826 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
827 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
828 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
829 let isCommutable = Commutable;
832 // Vector intrinsic operation, mem
833 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
834 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
835 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
839 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
840 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
842 // Reciprocal approximations. Note that these typically require refinement
843 // in order to obtain suitable precision.
844 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
845 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
846 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
847 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
850 let Constraints = "$src1 = $dst" in {
851 let isCommutable = 1 in {
852 def ANDPSrr : PSI<0x54, MRMSrcReg,
853 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
854 "andps\t{$src2, $dst|$dst, $src2}",
855 [(set VR128:$dst, (v2i64
856 (and VR128:$src1, VR128:$src2)))]>;
857 def ORPSrr : PSI<0x56, MRMSrcReg,
858 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
859 "orps\t{$src2, $dst|$dst, $src2}",
860 [(set VR128:$dst, (v2i64
861 (or VR128:$src1, VR128:$src2)))]>;
862 def XORPSrr : PSI<0x57, MRMSrcReg,
863 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
864 "xorps\t{$src2, $dst|$dst, $src2}",
865 [(set VR128:$dst, (v2i64
866 (xor VR128:$src1, VR128:$src2)))]>;
869 def ANDPSrm : PSI<0x54, MRMSrcMem,
870 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
871 "andps\t{$src2, $dst|$dst, $src2}",
872 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
873 (memopv2i64 addr:$src2)))]>;
874 def ORPSrm : PSI<0x56, MRMSrcMem,
875 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
876 "orps\t{$src2, $dst|$dst, $src2}",
877 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
878 (memopv2i64 addr:$src2)))]>;
879 def XORPSrm : PSI<0x57, MRMSrcMem,
880 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
881 "xorps\t{$src2, $dst|$dst, $src2}",
882 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
883 (memopv2i64 addr:$src2)))]>;
884 def ANDNPSrr : PSI<0x55, MRMSrcReg,
885 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
886 "andnps\t{$src2, $dst|$dst, $src2}",
888 (v2i64 (and (xor VR128:$src1,
889 (bc_v2i64 (v4i32 immAllOnesV))),
891 def ANDNPSrm : PSI<0x55, MRMSrcMem,
892 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
893 "andnps\t{$src2, $dst|$dst, $src2}",
895 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
896 (bc_v2i64 (v4i32 immAllOnesV))),
897 (memopv2i64 addr:$src2))))]>;
900 let Constraints = "$src1 = $dst" in {
901 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
902 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
903 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
904 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
905 VR128:$src, imm:$cc))]>;
906 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
907 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
908 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
909 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
910 (memop addr:$src), imm:$cc))]>;
912 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
913 (CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>;
914 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
915 (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>;
917 // Shuffle and unpack instructions
918 let Constraints = "$src1 = $dst" in {
919 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
920 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
921 (outs VR128:$dst), (ins VR128:$src1,
922 VR128:$src2, i8imm:$src3),
923 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
925 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
926 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
927 (outs VR128:$dst), (ins VR128:$src1,
928 f128mem:$src2, i8imm:$src3),
929 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
932 VR128:$src1, (memopv4f32 addr:$src2))))]>;
934 let AddedComplexity = 10 in {
935 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
936 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
937 "unpckhps\t{$src2, $dst|$dst, $src2}",
939 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
940 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
941 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
942 "unpckhps\t{$src2, $dst|$dst, $src2}",
944 (v4f32 (unpckh VR128:$src1,
945 (memopv4f32 addr:$src2))))]>;
947 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
948 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
949 "unpcklps\t{$src2, $dst|$dst, $src2}",
951 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
952 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
953 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
954 "unpcklps\t{$src2, $dst|$dst, $src2}",
956 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
958 } // Constraints = "$src1 = $dst"
961 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
962 "movmskps\t{$src, $dst|$dst, $src}",
963 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
964 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
965 "movmskpd\t{$src, $dst|$dst, $src}",
966 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
968 // Prefetch intrinsic.
969 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
970 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
971 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
972 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
973 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
974 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
975 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
976 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
978 // Non-temporal stores
979 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
980 "movntps\t{$src, $dst|$dst, $src}",
981 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
983 // Load, store, and memory fence
984 def SFENCE : PSI<0xAE, MRM7r, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
987 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
988 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
989 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
990 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
992 // Alias instructions that map zero vector to pxor / xorp* for sse.
993 // We set canFoldAsLoad because this can be converted to a constant-pool
994 // load of an all-zeros value if folding it would be beneficial.
995 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
996 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
998 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1000 let Predicates = [HasSSE1] in {
1001 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
1002 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
1003 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
1004 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1005 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1008 // FR32 to 128-bit vector conversion.
1009 let isAsCheapAsAMove = 1 in
1010 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
1011 "movss\t{$src, $dst|$dst, $src}",
1013 (v4f32 (scalar_to_vector FR32:$src)))]>;
1014 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1015 "movss\t{$src, $dst|$dst, $src}",
1017 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1019 // FIXME: may not be able to eliminate this movss with coalescing the src and
1020 // dest register classes are different. We really want to write this pattern
1022 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1023 // (f32 FR32:$src)>;
1024 let isAsCheapAsAMove = 1 in
1025 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1026 "movss\t{$src, $dst|$dst, $src}",
1027 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1029 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1030 "movss\t{$src, $dst|$dst, $src}",
1031 [(store (f32 (vector_extract (v4f32 VR128:$src),
1032 (iPTR 0))), addr:$dst)]>;
1035 // Move to lower bits of a VR128, leaving upper bits alone.
1036 // Three operand (but two address) aliases.
1037 let Constraints = "$src1 = $dst" in {
1038 let neverHasSideEffects = 1 in
1039 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1040 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1041 "movss\t{$src2, $dst|$dst, $src2}", []>;
1043 let AddedComplexity = 15 in
1044 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1045 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1046 "movss\t{$src2, $dst|$dst, $src2}",
1048 (v4f32 (movl VR128:$src1, VR128:$src2)))]>;
1051 // Move to lower bits of a VR128 and zeroing upper bits.
1052 // Loading from memory automatically zeroing upper bits.
1053 let AddedComplexity = 20 in
1054 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1055 "movss\t{$src, $dst|$dst, $src}",
1056 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1057 (loadf32 addr:$src))))))]>;
1059 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1060 (MOVZSS2PSrm addr:$src)>;
1062 //===---------------------------------------------------------------------===//
1063 // SSE2 Instructions
1064 //===---------------------------------------------------------------------===//
1066 // Move Instructions
1067 let neverHasSideEffects = 1 in
1068 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1069 "movsd\t{$src, $dst|$dst, $src}", []>;
1070 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1071 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1072 "movsd\t{$src, $dst|$dst, $src}",
1073 [(set FR64:$dst, (loadf64 addr:$src))]>;
1074 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1075 "movsd\t{$src, $dst|$dst, $src}",
1076 [(store FR64:$src, addr:$dst)]>;
1078 // Conversion instructions
1079 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1080 "cvttsd2si\t{$src, $dst|$dst, $src}",
1081 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1082 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1083 "cvttsd2si\t{$src, $dst|$dst, $src}",
1084 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1085 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1086 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1087 [(set FR32:$dst, (fround FR64:$src))]>;
1088 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1089 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1090 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1091 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1092 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1093 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1094 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1095 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1096 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1098 // SSE2 instructions with XS prefix
1099 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1100 "cvtss2sd\t{$src, $dst|$dst, $src}",
1101 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1102 Requires<[HasSSE2]>;
1103 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1104 "cvtss2sd\t{$src, $dst|$dst, $src}",
1105 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1106 Requires<[HasSSE2]>;
1108 // Match intrinsics which expect XMM operand(s).
1109 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1110 "cvtsd2si\t{$src, $dst|$dst, $src}",
1111 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1112 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1113 "cvtsd2si\t{$src, $dst|$dst, $src}",
1114 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1115 (load addr:$src)))]>;
1117 // Match intrinisics which expect MM and XMM operand(s).
1118 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1119 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1120 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1121 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1122 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1123 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1124 (memop addr:$src)))]>;
1125 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1126 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1127 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1128 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1129 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1130 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1131 (memop addr:$src)))]>;
1132 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1133 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1134 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1135 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1136 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1137 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1138 (load addr:$src)))]>;
1140 // Aliases for intrinsics
1141 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1142 "cvttsd2si\t{$src, $dst|$dst, $src}",
1144 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1145 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1146 "cvttsd2si\t{$src, $dst|$dst, $src}",
1147 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1148 (load addr:$src)))]>;
1150 // Comparison instructions
1151 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1152 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1153 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1154 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1156 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1157 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1158 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1161 let Defs = [EFLAGS] in {
1162 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1163 "ucomisd\t{$src2, $src1|$src1, $src2}",
1164 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1165 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1166 "ucomisd\t{$src2, $src1|$src1, $src2}",
1167 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1168 (implicit EFLAGS)]>;
1169 } // Defs = [EFLAGS]
1171 // Aliases to match intrinsics which expect XMM operand(s).
1172 let Constraints = "$src1 = $dst" in {
1173 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1174 (outs VR128:$dst), (ins VR128:$src1, VR128:$src,
1176 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1177 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1178 VR128:$src, imm:$cc))]>;
1179 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1180 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src,
1182 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1183 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1184 (load addr:$src), imm:$cc))]>;
1187 let Defs = [EFLAGS] in {
1188 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1189 "ucomisd\t{$src2, $src1|$src1, $src2}",
1190 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1191 (implicit EFLAGS)]>;
1192 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1193 "ucomisd\t{$src2, $src1|$src1, $src2}",
1194 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1195 (implicit EFLAGS)]>;
1197 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1198 "comisd\t{$src2, $src1|$src1, $src2}",
1199 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1200 (implicit EFLAGS)]>;
1201 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1202 "comisd\t{$src2, $src1|$src1, $src2}",
1203 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1204 (implicit EFLAGS)]>;
1205 } // Defs = [EFLAGS]
1207 // Aliases of packed SSE2 instructions for scalar use. These all have names
1208 // that start with 'Fs'.
1210 // Alias instructions that map fld0 to pxor for sse.
1211 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1212 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1213 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1214 Requires<[HasSSE2]>, TB, OpSize;
1216 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1218 let neverHasSideEffects = 1 in
1219 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1220 "movapd\t{$src, $dst|$dst, $src}", []>;
1222 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1224 let canFoldAsLoad = 1 in
1225 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1226 "movapd\t{$src, $dst|$dst, $src}",
1227 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1229 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1230 let Constraints = "$src1 = $dst" in {
1231 let isCommutable = 1 in {
1232 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1233 (ins FR64:$src1, FR64:$src2),
1234 "andpd\t{$src2, $dst|$dst, $src2}",
1235 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1236 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1237 (ins FR64:$src1, FR64:$src2),
1238 "orpd\t{$src2, $dst|$dst, $src2}",
1239 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1240 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1241 (ins FR64:$src1, FR64:$src2),
1242 "xorpd\t{$src2, $dst|$dst, $src2}",
1243 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1246 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1247 (ins FR64:$src1, f128mem:$src2),
1248 "andpd\t{$src2, $dst|$dst, $src2}",
1249 [(set FR64:$dst, (X86fand FR64:$src1,
1250 (memopfsf64 addr:$src2)))]>;
1251 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1252 (ins FR64:$src1, f128mem:$src2),
1253 "orpd\t{$src2, $dst|$dst, $src2}",
1254 [(set FR64:$dst, (X86for FR64:$src1,
1255 (memopfsf64 addr:$src2)))]>;
1256 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1257 (ins FR64:$src1, f128mem:$src2),
1258 "xorpd\t{$src2, $dst|$dst, $src2}",
1259 [(set FR64:$dst, (X86fxor FR64:$src1,
1260 (memopfsf64 addr:$src2)))]>;
1262 let neverHasSideEffects = 1 in {
1263 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1264 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1265 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1267 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1268 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1269 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1273 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1275 /// In addition, we also have a special variant of the scalar form here to
1276 /// represent the associated intrinsic operation. This form is unlike the
1277 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1278 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1280 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1281 /// six "instructions".
1283 let Constraints = "$src1 = $dst" in {
1284 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1285 SDNode OpNode, Intrinsic F64Int,
1286 bit Commutable = 0> {
1287 // Scalar operation, reg+reg.
1288 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1289 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1290 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1291 let isCommutable = Commutable;
1294 // Scalar operation, reg+mem.
1295 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1296 (ins FR64:$src1, f64mem:$src2),
1297 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1298 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1300 // Vector operation, reg+reg.
1301 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1302 (ins VR128:$src1, VR128:$src2),
1303 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1304 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1305 let isCommutable = Commutable;
1308 // Vector operation, reg+mem.
1309 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1310 (ins VR128:$src1, f128mem:$src2),
1311 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1312 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1314 // Intrinsic operation, reg+reg.
1315 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1316 (ins VR128:$src1, VR128:$src2),
1317 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1318 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]>;
1320 // Intrinsic operation, reg+mem.
1321 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1322 (ins VR128:$src1, sdmem:$src2),
1323 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1324 [(set VR128:$dst, (F64Int VR128:$src1,
1325 sse_load_f64:$src2))]>;
1329 // Arithmetic instructions
1330 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1331 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1332 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1333 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1335 /// sse2_fp_binop_rm - Other SSE2 binops
1337 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1338 /// instructions for a full-vector intrinsic form. Operations that map
1339 /// onto C operators don't use this form since they just use the plain
1340 /// vector form instead of having a separate vector intrinsic form.
1342 /// This provides a total of eight "instructions".
1344 let Constraints = "$src1 = $dst" in {
1345 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1349 bit Commutable = 0> {
1351 // Scalar operation, reg+reg.
1352 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1353 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1354 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1355 let isCommutable = Commutable;
1358 // Scalar operation, reg+mem.
1359 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1360 (ins FR64:$src1, f64mem:$src2),
1361 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1362 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1364 // Vector operation, reg+reg.
1365 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1366 (ins VR128:$src1, VR128:$src2),
1367 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1368 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1369 let isCommutable = Commutable;
1372 // Vector operation, reg+mem.
1373 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1374 (ins VR128:$src1, f128mem:$src2),
1375 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1376 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1378 // Intrinsic operation, reg+reg.
1379 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1380 (ins VR128:$src1, VR128:$src2),
1381 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1382 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1383 let isCommutable = Commutable;
1386 // Intrinsic operation, reg+mem.
1387 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1388 (ins VR128:$src1, sdmem:$src2),
1389 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1390 [(set VR128:$dst, (F64Int VR128:$src1,
1391 sse_load_f64:$src2))]>;
1393 // Vector intrinsic operation, reg+reg.
1394 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1395 (ins VR128:$src1, VR128:$src2),
1396 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1397 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1398 let isCommutable = Commutable;
1401 // Vector intrinsic operation, reg+mem.
1402 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1403 (ins VR128:$src1, f128mem:$src2),
1404 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1405 [(set VR128:$dst, (V2F64Int VR128:$src1,
1406 (memopv2f64 addr:$src2)))]>;
1410 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1411 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1412 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1413 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1415 //===---------------------------------------------------------------------===//
1416 // SSE packed FP Instructions
1418 // Move Instructions
1419 let neverHasSideEffects = 1 in
1420 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1421 "movapd\t{$src, $dst|$dst, $src}", []>;
1422 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1423 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1424 "movapd\t{$src, $dst|$dst, $src}",
1425 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1427 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1428 "movapd\t{$src, $dst|$dst, $src}",
1429 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1431 let neverHasSideEffects = 1 in
1432 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1433 "movupd\t{$src, $dst|$dst, $src}", []>;
1434 let canFoldAsLoad = 1 in
1435 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1436 "movupd\t{$src, $dst|$dst, $src}",
1437 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1438 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1439 "movupd\t{$src, $dst|$dst, $src}",
1440 [(store (v2f64 VR128:$src), addr:$dst)]>;
1442 // Intrinsic forms of MOVUPD load and store
1443 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1444 "movupd\t{$src, $dst|$dst, $src}",
1445 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1446 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1447 "movupd\t{$src, $dst|$dst, $src}",
1448 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1450 let Constraints = "$src1 = $dst" in {
1451 let AddedComplexity = 20 in {
1452 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1453 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1454 "movlpd\t{$src2, $dst|$dst, $src2}",
1456 (v2f64 (movlp VR128:$src1,
1457 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1458 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1459 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1460 "movhpd\t{$src2, $dst|$dst, $src2}",
1462 (v2f64 (movhp VR128:$src1,
1463 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1464 } // AddedComplexity
1465 } // Constraints = "$src1 = $dst"
1467 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1468 "movlpd\t{$src, $dst|$dst, $src}",
1469 [(store (f64 (vector_extract (v2f64 VR128:$src),
1470 (iPTR 0))), addr:$dst)]>;
1472 // v2f64 extract element 1 is always custom lowered to unpack high to low
1473 // and extract element 0 so the non-store version isn't too horrible.
1474 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1475 "movhpd\t{$src, $dst|$dst, $src}",
1476 [(store (f64 (vector_extract
1477 (v2f64 (unpckh VR128:$src, (undef))),
1478 (iPTR 0))), addr:$dst)]>;
1480 // SSE2 instructions without OpSize prefix
1481 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1482 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1483 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1484 TB, Requires<[HasSSE2]>;
1485 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1486 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1487 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1488 (bitconvert (memopv2i64 addr:$src))))]>,
1489 TB, Requires<[HasSSE2]>;
1491 // SSE2 instructions with XS prefix
1492 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1493 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1494 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1495 XS, Requires<[HasSSE2]>;
1496 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1497 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1498 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1499 (bitconvert (memopv2i64 addr:$src))))]>,
1500 XS, Requires<[HasSSE2]>;
1502 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1503 "cvtps2dq\t{$src, $dst|$dst, $src}",
1504 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1505 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1506 "cvtps2dq\t{$src, $dst|$dst, $src}",
1507 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1508 (memop addr:$src)))]>;
1509 // SSE2 packed instructions with XS prefix
1510 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1511 "cvttps2dq\t{$src, $dst|$dst, $src}",
1512 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1513 XS, Requires<[HasSSE2]>;
1514 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1515 "cvttps2dq\t{$src, $dst|$dst, $src}",
1516 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1517 (memop addr:$src)))]>,
1518 XS, Requires<[HasSSE2]>;
1520 // SSE2 packed instructions with XD prefix
1521 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1522 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1523 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1524 XD, Requires<[HasSSE2]>;
1525 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1526 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1527 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1528 (memop addr:$src)))]>,
1529 XD, Requires<[HasSSE2]>;
1531 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1532 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1533 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1534 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1535 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1536 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1537 (memop addr:$src)))]>;
1539 // SSE2 instructions without OpSize prefix
1540 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1541 "cvtps2pd\t{$src, $dst|$dst, $src}",
1542 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1543 TB, Requires<[HasSSE2]>;
1544 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1545 "cvtps2pd\t{$src, $dst|$dst, $src}",
1546 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1547 (load addr:$src)))]>,
1548 TB, Requires<[HasSSE2]>;
1550 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1551 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1552 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1553 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1554 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1555 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1556 (memop addr:$src)))]>;
1558 // Match intrinsics which expect XMM operand(s).
1559 // Aliases for intrinsics
1560 let Constraints = "$src1 = $dst" in {
1561 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1562 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1563 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1564 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1566 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1567 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1568 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1569 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1570 (loadi32 addr:$src2)))]>;
1571 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1572 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1573 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1574 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1576 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1577 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1578 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1579 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1580 (load addr:$src2)))]>;
1581 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1582 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1583 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1584 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1585 VR128:$src2))]>, XS,
1586 Requires<[HasSSE2]>;
1587 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1588 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1589 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1590 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1591 (load addr:$src2)))]>, XS,
1592 Requires<[HasSSE2]>;
1597 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1599 /// In addition, we also have a special variant of the scalar form here to
1600 /// represent the associated intrinsic operation. This form is unlike the
1601 /// plain scalar form, in that it takes an entire vector (instead of a
1602 /// scalar) and leaves the top elements undefined.
1604 /// And, we have a special variant form for a full-vector intrinsic form.
1606 /// These four forms can each have a reg or a mem operand, so there are a
1607 /// total of eight "instructions".
1609 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1613 bit Commutable = 0> {
1614 // Scalar operation, reg.
1615 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1616 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1617 [(set FR64:$dst, (OpNode FR64:$src))]> {
1618 let isCommutable = Commutable;
1621 // Scalar operation, mem.
1622 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1623 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1624 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1626 // Vector operation, reg.
1627 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1628 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1629 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1630 let isCommutable = Commutable;
1633 // Vector operation, mem.
1634 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1635 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1636 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1638 // Intrinsic operation, reg.
1639 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1640 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1641 [(set VR128:$dst, (F64Int VR128:$src))]> {
1642 let isCommutable = Commutable;
1645 // Intrinsic operation, mem.
1646 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1647 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1648 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1650 // Vector intrinsic operation, reg
1651 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1652 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1653 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1654 let isCommutable = Commutable;
1657 // Vector intrinsic operation, mem
1658 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1659 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1660 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1664 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1665 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1667 // There is no f64 version of the reciprocal approximation instructions.
1670 let Constraints = "$src1 = $dst" in {
1671 let isCommutable = 1 in {
1672 def ANDPDrr : PDI<0x54, MRMSrcReg,
1673 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1674 "andpd\t{$src2, $dst|$dst, $src2}",
1676 (and (bc_v2i64 (v2f64 VR128:$src1)),
1677 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1678 def ORPDrr : PDI<0x56, MRMSrcReg,
1679 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1680 "orpd\t{$src2, $dst|$dst, $src2}",
1682 (or (bc_v2i64 (v2f64 VR128:$src1)),
1683 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1684 def XORPDrr : PDI<0x57, MRMSrcReg,
1685 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1686 "xorpd\t{$src2, $dst|$dst, $src2}",
1688 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1689 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1692 def ANDPDrm : PDI<0x54, MRMSrcMem,
1693 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1694 "andpd\t{$src2, $dst|$dst, $src2}",
1696 (and (bc_v2i64 (v2f64 VR128:$src1)),
1697 (memopv2i64 addr:$src2)))]>;
1698 def ORPDrm : PDI<0x56, MRMSrcMem,
1699 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1700 "orpd\t{$src2, $dst|$dst, $src2}",
1702 (or (bc_v2i64 (v2f64 VR128:$src1)),
1703 (memopv2i64 addr:$src2)))]>;
1704 def XORPDrm : PDI<0x57, MRMSrcMem,
1705 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1706 "xorpd\t{$src2, $dst|$dst, $src2}",
1708 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1709 (memopv2i64 addr:$src2)))]>;
1710 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1711 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1712 "andnpd\t{$src2, $dst|$dst, $src2}",
1714 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1715 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1716 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1717 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1718 "andnpd\t{$src2, $dst|$dst, $src2}",
1720 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1721 (memopv2i64 addr:$src2)))]>;
1724 let Constraints = "$src1 = $dst" in {
1725 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1726 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1727 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1728 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1729 VR128:$src, imm:$cc))]>;
1730 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1731 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1732 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1733 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1734 (memop addr:$src), imm:$cc))]>;
1736 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1737 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1738 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1739 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1741 // Shuffle and unpack instructions
1742 let Constraints = "$src1 = $dst" in {
1743 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1744 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1745 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1747 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1748 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1749 (outs VR128:$dst), (ins VR128:$src1,
1750 f128mem:$src2, i8imm:$src3),
1751 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1754 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1756 let AddedComplexity = 10 in {
1757 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1758 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1759 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1761 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1762 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1763 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1764 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1766 (v2f64 (unpckh VR128:$src1,
1767 (memopv2f64 addr:$src2))))]>;
1769 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1770 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1771 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1773 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1774 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1775 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1776 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1778 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1779 } // AddedComplexity
1780 } // Constraints = "$src1 = $dst"
1783 //===---------------------------------------------------------------------===//
1784 // SSE integer instructions
1786 // Move Instructions
1787 let neverHasSideEffects = 1 in
1788 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1789 "movdqa\t{$src, $dst|$dst, $src}", []>;
1790 let canFoldAsLoad = 1, mayLoad = 1 in
1791 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1792 "movdqa\t{$src, $dst|$dst, $src}",
1793 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1795 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1796 "movdqa\t{$src, $dst|$dst, $src}",
1797 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1798 let canFoldAsLoad = 1, mayLoad = 1 in
1799 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1800 "movdqu\t{$src, $dst|$dst, $src}",
1801 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1802 XS, Requires<[HasSSE2]>;
1804 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1805 "movdqu\t{$src, $dst|$dst, $src}",
1806 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1807 XS, Requires<[HasSSE2]>;
1809 // Intrinsic forms of MOVDQU load and store
1810 let canFoldAsLoad = 1 in
1811 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1812 "movdqu\t{$src, $dst|$dst, $src}",
1813 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1814 XS, Requires<[HasSSE2]>;
1815 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1816 "movdqu\t{$src, $dst|$dst, $src}",
1817 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1818 XS, Requires<[HasSSE2]>;
1820 let Constraints = "$src1 = $dst" in {
1822 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1823 bit Commutable = 0> {
1824 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1825 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1826 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1827 let isCommutable = Commutable;
1829 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1830 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1831 [(set VR128:$dst, (IntId VR128:$src1,
1832 (bitconvert (memopv2i64 addr:$src2))))]>;
1835 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1837 Intrinsic IntId, Intrinsic IntId2> {
1838 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1,
1840 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1841 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1842 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1,
1844 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1845 [(set VR128:$dst, (IntId VR128:$src1,
1846 (bitconvert (memopv2i64 addr:$src2))))]>;
1847 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1,
1849 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1850 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1853 /// PDI_binop_rm - Simple SSE2 binary operator.
1854 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1855 ValueType OpVT, bit Commutable = 0> {
1856 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1,
1858 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1859 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1860 let isCommutable = Commutable;
1862 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1,
1864 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1865 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1866 (bitconvert (memopv2i64 addr:$src2)))))]>;
1869 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1871 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1872 /// to collapse (bitconvert VT to VT) into its operand.
1874 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1875 bit Commutable = 0> {
1876 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1877 (ins VR128:$src1, VR128:$src2),
1878 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1879 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1880 let isCommutable = Commutable;
1882 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1883 (ins VR128:$src1, i128mem:$src2),
1884 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1885 [(set VR128:$dst, (OpNode VR128:$src1,
1886 (memopv2i64 addr:$src2)))]>;
1889 } // Constraints = "$src1 = $dst"
1891 // 128-bit Integer Arithmetic
1893 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1894 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1895 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1896 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1898 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1899 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1900 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1901 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1903 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1904 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1905 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1906 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1908 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1909 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1910 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1911 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1913 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1915 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1916 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1917 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1919 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1921 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1922 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1925 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1926 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1927 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1928 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1929 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
1932 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1933 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1934 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
1935 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
1936 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
1937 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
1939 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
1940 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
1941 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
1942 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
1943 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
1944 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
1946 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
1947 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
1948 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
1949 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
1951 // 128-bit logical shifts.
1952 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1953 def PSLLDQri : PDIi8<0x73, MRM7r,
1954 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1955 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1956 def PSRLDQri : PDIi8<0x73, MRM3r,
1957 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1958 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1959 // PSRADQri doesn't exist in SSE[1-3].
1962 let Predicates = [HasSSE2] in {
1963 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1964 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1965 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1966 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1967 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
1968 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
1969 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
1970 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
1971 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1972 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1974 // Shift up / down and insert zero's.
1975 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
1976 (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1977 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
1978 (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1982 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1983 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1984 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1986 let Constraints = "$src1 = $dst" in {
1987 def PANDNrr : PDI<0xDF, MRMSrcReg,
1988 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1989 "pandn\t{$src2, $dst|$dst, $src2}",
1990 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1993 def PANDNrm : PDI<0xDF, MRMSrcMem,
1994 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1995 "pandn\t{$src2, $dst|$dst, $src2}",
1996 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1997 (memopv2i64 addr:$src2))))]>;
2000 // SSE2 Integer comparison
2001 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2002 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2003 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2004 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2005 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2006 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2008 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2009 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2010 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2011 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2012 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2013 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2014 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2015 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2016 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2017 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2018 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2019 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2021 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2022 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2023 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2024 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2025 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2026 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2027 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2028 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2029 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2030 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2031 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2032 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2035 // Pack instructions
2036 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2037 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2038 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2040 // Shuffle and unpack instructions
2041 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2042 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2043 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2044 [(set VR128:$dst, (v4i32 (pshufd:$src2
2045 VR128:$src1, (undef))))]>;
2046 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2047 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2048 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2049 [(set VR128:$dst, (v4i32 (pshufd:$src2
2050 (bc_v4i32(memopv2i64 addr:$src1)),
2053 // SSE2 with ImmT == Imm8 and XS prefix.
2054 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2055 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2056 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2057 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2059 XS, Requires<[HasSSE2]>;
2060 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2061 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2062 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2063 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2064 (bc_v8i16 (memopv2i64 addr:$src1)),
2066 XS, Requires<[HasSSE2]>;
2068 // SSE2 with ImmT == Imm8 and XD prefix.
2069 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2070 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2071 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2072 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2074 XD, Requires<[HasSSE2]>;
2075 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2076 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2077 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2078 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2079 (bc_v8i16 (memopv2i64 addr:$src1)),
2081 XD, Requires<[HasSSE2]>;
2084 let Constraints = "$src1 = $dst" in {
2085 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2086 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2087 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2089 (v16i8 (unpckl VR128:$src1, VR128:$src2)))]>;
2090 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2091 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2092 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2094 (unpckl VR128:$src1,
2095 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2096 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2097 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2098 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2100 (v8i16 (unpckl VR128:$src1, VR128:$src2)))]>;
2101 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2102 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2103 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2105 (unpckl VR128:$src1,
2106 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2107 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2108 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2109 "punpckldq\t{$src2, $dst|$dst, $src2}",
2111 (v4i32 (unpckl VR128:$src1, VR128:$src2)))]>;
2112 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2113 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2114 "punpckldq\t{$src2, $dst|$dst, $src2}",
2116 (unpckl VR128:$src1,
2117 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2118 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2119 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2120 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2122 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2123 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2124 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2125 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2127 (v2i64 (unpckl VR128:$src1,
2128 (memopv2i64 addr:$src2))))]>;
2130 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2131 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2132 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2134 (v16i8 (unpckh VR128:$src1, VR128:$src2)))]>;
2135 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2136 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2137 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2139 (unpckh VR128:$src1,
2140 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2141 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2142 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2143 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2145 (v8i16 (unpckh VR128:$src1, VR128:$src2)))]>;
2146 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2147 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2148 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2150 (unpckh VR128:$src1,
2151 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2152 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2153 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2154 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2156 (v4i32 (unpckh VR128:$src1, VR128:$src2)))]>;
2157 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2158 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2159 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2161 (unpckh VR128:$src1,
2162 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2163 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2164 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2165 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2167 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2168 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2169 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2170 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2172 (v2i64 (unpckh VR128:$src1,
2173 (memopv2i64 addr:$src2))))]>;
2177 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2178 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2179 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2180 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2182 let Constraints = "$src1 = $dst" in {
2183 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2184 (outs VR128:$dst), (ins VR128:$src1,
2185 GR32:$src2, i32i8imm:$src3),
2186 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2188 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2189 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2190 (outs VR128:$dst), (ins VR128:$src1,
2191 i16mem:$src2, i32i8imm:$src3),
2192 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2194 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2199 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2200 "pmovmskb\t{$src, $dst|$dst, $src}",
2201 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2203 // Conditional store
2205 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2206 "maskmovdqu\t{$mask, $src|$src, $mask}",
2207 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2210 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2211 "maskmovdqu\t{$mask, $src|$src, $mask}",
2212 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2214 // Non-temporal stores
2215 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2216 "movntpd\t{$src, $dst|$dst, $src}",
2217 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2218 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2219 "movntdq\t{$src, $dst|$dst, $src}",
2220 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2221 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2222 "movnti\t{$src, $dst|$dst, $src}",
2223 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2224 TB, Requires<[HasSSE2]>;
2227 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2228 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2229 TB, Requires<[HasSSE2]>;
2231 // Load, store, and memory fence
2232 def LFENCE : I<0xAE, MRM5r, (outs), (ins),
2233 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2234 def MFENCE : I<0xAE, MRM6r, (outs), (ins),
2235 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2237 //TODO: custom lower this so as to never even generate the noop
2238 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2240 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2241 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2242 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2245 // Alias instructions that map zero vector to pxor / xorp* for sse.
2246 // We set canFoldAsLoad because this can be converted to a constant-pool
2247 // load of an all-ones value if folding it would be beneficial.
2248 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1 in
2249 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2250 "pcmpeqd\t$dst, $dst",
2251 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2253 // FR64 to 128-bit vector conversion.
2254 let isAsCheapAsAMove = 1 in
2255 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2256 "movsd\t{$src, $dst|$dst, $src}",
2258 (v2f64 (scalar_to_vector FR64:$src)))]>;
2259 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2260 "movsd\t{$src, $dst|$dst, $src}",
2262 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2264 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2265 "movd\t{$src, $dst|$dst, $src}",
2267 (v4i32 (scalar_to_vector GR32:$src)))]>;
2268 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2269 "movd\t{$src, $dst|$dst, $src}",
2271 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2273 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2274 "movd\t{$src, $dst|$dst, $src}",
2275 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2277 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2278 "movd\t{$src, $dst|$dst, $src}",
2279 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2281 // SSE2 instructions with XS prefix
2282 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2283 "movq\t{$src, $dst|$dst, $src}",
2285 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2286 Requires<[HasSSE2]>;
2287 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2288 "movq\t{$src, $dst|$dst, $src}",
2289 [(store (i64 (vector_extract (v2i64 VR128:$src),
2290 (iPTR 0))), addr:$dst)]>;
2292 // FIXME: may not be able to eliminate this movss with coalescing the src and
2293 // dest register classes are different. We really want to write this pattern
2295 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2296 // (f32 FR32:$src)>;
2297 let isAsCheapAsAMove = 1 in
2298 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2299 "movsd\t{$src, $dst|$dst, $src}",
2300 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2302 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2303 "movsd\t{$src, $dst|$dst, $src}",
2304 [(store (f64 (vector_extract (v2f64 VR128:$src),
2305 (iPTR 0))), addr:$dst)]>;
2306 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2307 "movd\t{$src, $dst|$dst, $src}",
2308 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2310 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2311 "movd\t{$src, $dst|$dst, $src}",
2312 [(store (i32 (vector_extract (v4i32 VR128:$src),
2313 (iPTR 0))), addr:$dst)]>;
2315 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2316 "movd\t{$src, $dst|$dst, $src}",
2317 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2318 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2319 "movd\t{$src, $dst|$dst, $src}",
2320 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2323 // Move to lower bits of a VR128, leaving upper bits alone.
2324 // Three operand (but two address) aliases.
2325 let Constraints = "$src1 = $dst" in {
2326 let neverHasSideEffects = 1 in
2327 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2328 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2329 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2331 let AddedComplexity = 15 in
2332 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2333 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2334 "movsd\t{$src2, $dst|$dst, $src2}",
2336 (v2f64 (movl VR128:$src1, VR128:$src2)))]>;
2339 // Store / copy lower 64-bits of a XMM register.
2340 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2341 "movq\t{$src, $dst|$dst, $src}",
2342 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2344 // Move to lower bits of a VR128 and zeroing upper bits.
2345 // Loading from memory automatically zeroing upper bits.
2346 let AddedComplexity = 20 in {
2347 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2348 "movsd\t{$src, $dst|$dst, $src}",
2350 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2351 (loadf64 addr:$src))))))]>;
2353 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2354 (MOVZSD2PDrm addr:$src)>;
2355 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2356 (MOVZSD2PDrm addr:$src)>;
2357 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2360 // movd / movq to XMM register zero-extends
2361 let AddedComplexity = 15 in {
2362 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2363 "movd\t{$src, $dst|$dst, $src}",
2364 [(set VR128:$dst, (v4i32 (X86vzmovl
2365 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2366 // This is X86-64 only.
2367 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2368 "mov{d|q}\t{$src, $dst|$dst, $src}",
2369 [(set VR128:$dst, (v2i64 (X86vzmovl
2370 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2373 let AddedComplexity = 20 in {
2374 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2375 "movd\t{$src, $dst|$dst, $src}",
2377 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2378 (loadi32 addr:$src))))))]>;
2380 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2381 (MOVZDI2PDIrm addr:$src)>;
2382 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2383 (MOVZDI2PDIrm addr:$src)>;
2384 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2385 (MOVZDI2PDIrm addr:$src)>;
2387 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2388 "movq\t{$src, $dst|$dst, $src}",
2390 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2391 (loadi64 addr:$src))))))]>, XS,
2392 Requires<[HasSSE2]>;
2394 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2395 (MOVZQI2PQIrm addr:$src)>;
2396 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2397 (MOVZQI2PQIrm addr:$src)>;
2398 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2401 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2402 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2403 let AddedComplexity = 15 in
2404 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2405 "movq\t{$src, $dst|$dst, $src}",
2406 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2407 XS, Requires<[HasSSE2]>;
2409 let AddedComplexity = 20 in {
2410 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2411 "movq\t{$src, $dst|$dst, $src}",
2412 [(set VR128:$dst, (v2i64 (X86vzmovl
2413 (loadv2i64 addr:$src))))]>,
2414 XS, Requires<[HasSSE2]>;
2416 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2417 (MOVZPQILo2PQIrm addr:$src)>;
2420 //===---------------------------------------------------------------------===//
2421 // SSE3 Instructions
2422 //===---------------------------------------------------------------------===//
2424 // Move Instructions
2425 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2426 "movshdup\t{$src, $dst|$dst, $src}",
2427 [(set VR128:$dst, (v4f32 (movshdup
2428 VR128:$src, (undef))))]>;
2429 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2430 "movshdup\t{$src, $dst|$dst, $src}",
2431 [(set VR128:$dst, (movshdup
2432 (memopv4f32 addr:$src), (undef)))]>;
2434 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2435 "movsldup\t{$src, $dst|$dst, $src}",
2436 [(set VR128:$dst, (v4f32 (movsldup
2437 VR128:$src, (undef))))]>;
2438 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2439 "movsldup\t{$src, $dst|$dst, $src}",
2440 [(set VR128:$dst, (movsldup
2441 (memopv4f32 addr:$src), (undef)))]>;
2443 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2444 "movddup\t{$src, $dst|$dst, $src}",
2445 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2446 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2447 "movddup\t{$src, $dst|$dst, $src}",
2449 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2452 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2454 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2456 let AddedComplexity = 5 in {
2457 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2458 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2459 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2460 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2461 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2462 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2463 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2464 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2468 let Constraints = "$src1 = $dst" in {
2469 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2470 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2471 "addsubps\t{$src2, $dst|$dst, $src2}",
2472 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2474 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2475 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2476 "addsubps\t{$src2, $dst|$dst, $src2}",
2477 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2478 (memop addr:$src2)))]>;
2479 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2480 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2481 "addsubpd\t{$src2, $dst|$dst, $src2}",
2482 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2484 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2485 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2486 "addsubpd\t{$src2, $dst|$dst, $src2}",
2487 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2488 (memop addr:$src2)))]>;
2491 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2492 "lddqu\t{$src, $dst|$dst, $src}",
2493 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2496 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2497 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2498 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2499 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2500 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2501 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2502 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2503 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2504 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2505 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2506 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2507 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2508 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2509 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2510 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2511 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2513 let Constraints = "$src1 = $dst" in {
2514 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2515 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2516 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2517 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2518 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2519 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2520 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2521 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2524 // Thread synchronization
2525 def MONITOR : I<0x01, MRM1r, (outs), (ins), "monitor",
2526 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2527 def MWAIT : I<0x01, MRM1r, (outs), (ins), "mwait",
2528 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2530 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2531 let AddedComplexity = 15 in
2532 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2533 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2534 let AddedComplexity = 20 in
2535 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2536 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2538 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2539 let AddedComplexity = 15 in
2540 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2541 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2542 let AddedComplexity = 20 in
2543 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2544 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2546 //===---------------------------------------------------------------------===//
2547 // SSSE3 Instructions
2548 //===---------------------------------------------------------------------===//
2550 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2551 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2552 Intrinsic IntId64, Intrinsic IntId128> {
2553 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2554 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2555 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2557 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2558 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2560 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2562 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2564 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2565 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2568 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2570 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2573 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2576 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2577 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2578 Intrinsic IntId64, Intrinsic IntId128> {
2579 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2581 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2582 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2584 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2586 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2589 (bitconvert (memopv4i16 addr:$src))))]>;
2591 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2593 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2594 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2597 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2599 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2602 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2605 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2606 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2607 Intrinsic IntId64, Intrinsic IntId128> {
2608 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2610 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2611 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2613 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2615 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2618 (bitconvert (memopv2i32 addr:$src))))]>;
2620 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2622 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2623 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2626 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2628 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2631 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2634 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2635 int_x86_ssse3_pabs_b,
2636 int_x86_ssse3_pabs_b_128>;
2637 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2638 int_x86_ssse3_pabs_w,
2639 int_x86_ssse3_pabs_w_128>;
2640 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2641 int_x86_ssse3_pabs_d,
2642 int_x86_ssse3_pabs_d_128>;
2644 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2645 let Constraints = "$src1 = $dst" in {
2646 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2647 Intrinsic IntId64, Intrinsic IntId128,
2648 bit Commutable = 0> {
2649 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2650 (ins VR64:$src1, VR64:$src2),
2651 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2652 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2653 let isCommutable = Commutable;
2655 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2656 (ins VR64:$src1, i64mem:$src2),
2657 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2659 (IntId64 VR64:$src1,
2660 (bitconvert (memopv8i8 addr:$src2))))]>;
2662 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2663 (ins VR128:$src1, VR128:$src2),
2664 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2665 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2667 let isCommutable = Commutable;
2669 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2670 (ins VR128:$src1, i128mem:$src2),
2671 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2673 (IntId128 VR128:$src1,
2674 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2678 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2679 let Constraints = "$src1 = $dst" in {
2680 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2681 Intrinsic IntId64, Intrinsic IntId128,
2682 bit Commutable = 0> {
2683 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2684 (ins VR64:$src1, VR64:$src2),
2685 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2686 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2687 let isCommutable = Commutable;
2689 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2690 (ins VR64:$src1, i64mem:$src2),
2691 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2693 (IntId64 VR64:$src1,
2694 (bitconvert (memopv4i16 addr:$src2))))]>;
2696 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2697 (ins VR128:$src1, VR128:$src2),
2698 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2699 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2701 let isCommutable = Commutable;
2703 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2704 (ins VR128:$src1, i128mem:$src2),
2705 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2707 (IntId128 VR128:$src1,
2708 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2712 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2713 let Constraints = "$src1 = $dst" in {
2714 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2715 Intrinsic IntId64, Intrinsic IntId128,
2716 bit Commutable = 0> {
2717 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2718 (ins VR64:$src1, VR64:$src2),
2719 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2720 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2721 let isCommutable = Commutable;
2723 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2724 (ins VR64:$src1, i64mem:$src2),
2725 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2727 (IntId64 VR64:$src1,
2728 (bitconvert (memopv2i32 addr:$src2))))]>;
2730 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2731 (ins VR128:$src1, VR128:$src2),
2732 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2733 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2735 let isCommutable = Commutable;
2737 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2738 (ins VR128:$src1, i128mem:$src2),
2739 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2741 (IntId128 VR128:$src1,
2742 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2746 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2747 int_x86_ssse3_phadd_w,
2748 int_x86_ssse3_phadd_w_128>;
2749 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2750 int_x86_ssse3_phadd_d,
2751 int_x86_ssse3_phadd_d_128>;
2752 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2753 int_x86_ssse3_phadd_sw,
2754 int_x86_ssse3_phadd_sw_128>;
2755 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2756 int_x86_ssse3_phsub_w,
2757 int_x86_ssse3_phsub_w_128>;
2758 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2759 int_x86_ssse3_phsub_d,
2760 int_x86_ssse3_phsub_d_128>;
2761 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2762 int_x86_ssse3_phsub_sw,
2763 int_x86_ssse3_phsub_sw_128>;
2764 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2765 int_x86_ssse3_pmadd_ub_sw,
2766 int_x86_ssse3_pmadd_ub_sw_128>;
2767 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2768 int_x86_ssse3_pmul_hr_sw,
2769 int_x86_ssse3_pmul_hr_sw_128, 1>;
2770 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2771 int_x86_ssse3_pshuf_b,
2772 int_x86_ssse3_pshuf_b_128>;
2773 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2774 int_x86_ssse3_psign_b,
2775 int_x86_ssse3_psign_b_128>;
2776 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2777 int_x86_ssse3_psign_w,
2778 int_x86_ssse3_psign_w_128>;
2779 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2780 int_x86_ssse3_psign_d,
2781 int_x86_ssse3_psign_d_128>;
2783 let Constraints = "$src1 = $dst" in {
2784 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2785 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2786 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2788 (int_x86_ssse3_palign_r
2789 VR64:$src1, VR64:$src2,
2791 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2792 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2793 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2795 (int_x86_ssse3_palign_r
2797 (bitconvert (memopv2i32 addr:$src2)),
2800 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2801 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2802 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2804 (int_x86_ssse3_palign_r_128
2805 VR128:$src1, VR128:$src2,
2806 imm:$src3))]>, OpSize;
2807 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2808 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2809 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2811 (int_x86_ssse3_palign_r_128
2813 (bitconvert (memopv4i32 addr:$src2)),
2814 imm:$src3))]>, OpSize;
2817 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2818 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2819 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2820 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2822 //===---------------------------------------------------------------------===//
2823 // Non-Instruction Patterns
2824 //===---------------------------------------------------------------------===//
2826 // extload f32 -> f64. This matches load+fextend because we have a hack in
2827 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2829 // Since these loads aren't folded into the fextend, we have to match it
2831 let Predicates = [HasSSE2] in
2832 def : Pat<(fextend (loadf32 addr:$src)),
2833 (CVTSS2SDrm addr:$src)>;
2836 let Predicates = [HasSSE2] in {
2837 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2838 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2839 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2840 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2841 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2842 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2843 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2844 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2845 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2846 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2847 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2848 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2849 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2850 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2851 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2852 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2853 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2854 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2855 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2856 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2857 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2858 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2859 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2860 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2861 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2862 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2863 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2864 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2865 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2866 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2869 // Move scalar to XMM zero-extended
2870 // movd to XMM register zero-extends
2871 let AddedComplexity = 15 in {
2872 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2873 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2874 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2875 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2876 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE1]>;
2877 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2878 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2879 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2880 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE1]>;
2883 // Splat v2f64 / v2i64
2884 let AddedComplexity = 10 in {
2885 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2886 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2887 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
2888 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2889 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
2890 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2891 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
2892 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2895 // Special unary SHUFPSrri case.
2896 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2897 (SHUFPSrri VR128:$src1, VR128:$src1,
2898 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2899 Requires<[HasSSE1]>;
2900 let AddedComplexity = 5 in
2901 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
2902 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2903 Requires<[HasSSE2]>;
2904 // Special unary SHUFPDrri case.
2905 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2906 (SHUFPDrri VR128:$src1, VR128:$src1,
2907 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2908 Requires<[HasSSE2]>;
2909 // Special unary SHUFPDrri case.
2910 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2911 (SHUFPDrri VR128:$src1, VR128:$src1,
2912 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2913 Requires<[HasSSE2]>;
2914 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2915 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
2916 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2917 Requires<[HasSSE2]>;
2919 // Special binary v4i32 shuffle cases with SHUFPS.
2920 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2921 (SHUFPSrri VR128:$src1, VR128:$src2,
2922 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2923 Requires<[HasSSE2]>;
2924 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
2925 (SHUFPSrmi VR128:$src1, addr:$src2,
2926 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2927 Requires<[HasSSE2]>;
2928 // Special binary v2i64 shuffle cases using SHUFPDrri.
2929 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2930 (SHUFPDrri VR128:$src1, VR128:$src2,
2931 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2932 Requires<[HasSSE2]>;
2934 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2935 let AddedComplexity = 15 in {
2936 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
2937 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2938 Requires<[OptForSpeed, HasSSE2]>;
2939 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
2940 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2941 Requires<[OptForSpeed, HasSSE2]>;
2943 let AddedComplexity = 10 in {
2944 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
2945 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2946 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
2947 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2948 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
2949 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2950 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
2951 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2954 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2955 let AddedComplexity = 15 in {
2956 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
2957 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2958 Requires<[OptForSpeed, HasSSE2]>;
2959 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
2960 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2961 Requires<[OptForSpeed, HasSSE2]>;
2963 let AddedComplexity = 10 in {
2964 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
2965 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2966 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
2967 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2968 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
2969 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2970 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
2971 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2974 let AddedComplexity = 20 in {
2975 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2976 def : Pat<(v4i32 (movhp VR128:$src1, VR128:$src2)),
2977 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2979 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2980 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
2981 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2983 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2984 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
2985 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2986 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
2987 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2990 let AddedComplexity = 20 in {
2991 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2992 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2993 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
2994 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2995 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
2996 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2997 def : Pat<(v4f32 (movhp VR128:$src1, (load addr:$src2))),
2998 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2999 def : Pat<(v2f64 (movhp VR128:$src1, (load addr:$src2))),
3000 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3002 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3003 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3004 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3005 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3006 def : Pat<(v4i32 (movhp VR128:$src1, (load addr:$src2))),
3007 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3008 def : Pat<(v2i64 (movhp VR128:$src1, (load addr:$src2))),
3009 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3012 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3013 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
3014 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3015 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3016 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3017 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3018 def : Pat<(store (v4f32 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
3019 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3020 def : Pat<(store (v2f64 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
3021 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3023 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3025 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3026 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3027 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3028 def : Pat<(store (v4i32 (movhp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3030 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3031 def : Pat<(store (v2i64 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
3032 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3035 let AddedComplexity = 15 in {
3036 // Setting the lowest element in the vector.
3037 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3038 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3039 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3040 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3042 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
3043 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3044 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3045 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3046 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3049 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3050 // fall back to this for SSE1)
3051 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3052 (SHUFPSrri VR128:$src2, VR128:$src1,
3053 (SHUFFLE_get_shuf_imm VR128:$src3))>, Requires<[HasSSE1]>;
3055 // Set lowest element and zero upper elements.
3056 let AddedComplexity = 15 in
3057 def : Pat<(v2f64 (movl immAllZerosV_bc, VR128:$src)),
3058 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3059 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3060 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3062 // Some special case pandn patterns.
3063 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3065 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3066 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3068 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3069 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3071 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3073 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3074 (memop addr:$src2))),
3075 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3076 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3077 (memop addr:$src2))),
3078 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3079 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3080 (memop addr:$src2))),
3081 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3083 // vector -> vector casts
3084 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3085 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3086 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3087 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3088 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3089 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3090 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3091 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3093 // Use movaps / movups for SSE integer load / store (one byte shorter).
3094 def : Pat<(alignedloadv4i32 addr:$src),
3095 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3096 def : Pat<(loadv4i32 addr:$src),
3097 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3098 def : Pat<(alignedloadv2i64 addr:$src),
3099 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3100 def : Pat<(loadv2i64 addr:$src),
3101 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3103 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3104 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3105 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3106 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3107 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3108 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3109 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3110 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3111 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3112 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3113 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3114 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3115 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3116 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3117 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3118 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3120 //===----------------------------------------------------------------------===//
3121 // SSE4.1 Instructions
3122 //===----------------------------------------------------------------------===//
3124 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3127 Intrinsic V2F64Int> {
3128 // Intrinsic operation, reg.
3129 // Vector intrinsic operation, reg
3130 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3131 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3132 !strconcat(OpcodeStr,
3133 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3134 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3137 // Vector intrinsic operation, mem
3138 def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
3139 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3140 !strconcat(OpcodeStr,
3141 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3143 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3146 // Vector intrinsic operation, reg
3147 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3148 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3149 !strconcat(OpcodeStr,
3150 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3151 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3154 // Vector intrinsic operation, mem
3155 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3156 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3157 !strconcat(OpcodeStr,
3158 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3160 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3164 let Constraints = "$src1 = $dst" in {
3165 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3169 // Intrinsic operation, reg.
3170 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3172 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3173 !strconcat(OpcodeStr,
3174 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3176 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3179 // Intrinsic operation, mem.
3180 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3182 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3183 !strconcat(OpcodeStr,
3184 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3186 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3189 // Intrinsic operation, reg.
3190 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3192 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3193 !strconcat(OpcodeStr,
3194 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3196 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3199 // Intrinsic operation, mem.
3200 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3202 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3203 !strconcat(OpcodeStr,
3204 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3206 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3211 // FP round - roundss, roundps, roundsd, roundpd
3212 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3213 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3214 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3215 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3217 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3218 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3219 Intrinsic IntId128> {
3220 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3222 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3223 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3224 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3226 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3229 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3232 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3233 int_x86_sse41_phminposuw>;
3235 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3236 let Constraints = "$src1 = $dst" in {
3237 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3238 Intrinsic IntId128, bit Commutable = 0> {
3239 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3240 (ins VR128:$src1, VR128:$src2),
3241 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3242 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3244 let isCommutable = Commutable;
3246 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3247 (ins VR128:$src1, i128mem:$src2),
3248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3250 (IntId128 VR128:$src1,
3251 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3255 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3256 int_x86_sse41_pcmpeqq, 1>;
3257 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3258 int_x86_sse41_packusdw, 0>;
3259 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3260 int_x86_sse41_pminsb, 1>;
3261 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3262 int_x86_sse41_pminsd, 1>;
3263 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3264 int_x86_sse41_pminud, 1>;
3265 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3266 int_x86_sse41_pminuw, 1>;
3267 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3268 int_x86_sse41_pmaxsb, 1>;
3269 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3270 int_x86_sse41_pmaxsd, 1>;
3271 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3272 int_x86_sse41_pmaxud, 1>;
3273 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3274 int_x86_sse41_pmaxuw, 1>;
3276 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3278 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3279 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3280 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3281 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3283 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3284 let Constraints = "$src1 = $dst" in {
3285 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3286 SDNode OpNode, Intrinsic IntId128,
3287 bit Commutable = 0> {
3288 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3289 (ins VR128:$src1, VR128:$src2),
3290 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3291 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3292 VR128:$src2))]>, OpSize {
3293 let isCommutable = Commutable;
3295 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3296 (ins VR128:$src1, VR128:$src2),
3297 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3298 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3300 let isCommutable = Commutable;
3302 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3303 (ins VR128:$src1, i128mem:$src2),
3304 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3306 (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
3307 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3308 (ins VR128:$src1, i128mem:$src2),
3309 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3311 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3315 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3316 int_x86_sse41_pmulld, 1>;
3318 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3319 let Constraints = "$src1 = $dst" in {
3320 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3321 Intrinsic IntId128, bit Commutable = 0> {
3322 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3323 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3324 !strconcat(OpcodeStr,
3325 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3327 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3329 let isCommutable = Commutable;
3331 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3332 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3333 !strconcat(OpcodeStr,
3334 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3336 (IntId128 VR128:$src1,
3337 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3342 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3343 int_x86_sse41_blendps, 0>;
3344 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3345 int_x86_sse41_blendpd, 0>;
3346 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3347 int_x86_sse41_pblendw, 0>;
3348 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3349 int_x86_sse41_dpps, 1>;
3350 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3351 int_x86_sse41_dppd, 1>;
3352 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3353 int_x86_sse41_mpsadbw, 1>;
3356 /// SS41I_ternary_int - SSE 4.1 ternary operator
3357 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3358 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3359 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3360 (ins VR128:$src1, VR128:$src2),
3361 !strconcat(OpcodeStr,
3362 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3363 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3366 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3367 (ins VR128:$src1, i128mem:$src2),
3368 !strconcat(OpcodeStr,
3369 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3372 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3376 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3377 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3378 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3381 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3382 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3383 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3384 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3386 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3387 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3389 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3393 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3394 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3395 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3396 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3397 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3398 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3400 // Common patterns involving scalar load.
3401 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3402 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3403 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3404 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3406 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3407 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3408 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3409 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3411 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3412 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3413 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3414 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3416 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3417 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3418 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3419 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3421 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3422 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3423 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3424 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3426 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3427 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3428 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3429 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3432 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3433 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3434 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3435 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3437 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3438 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3440 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3444 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3445 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3446 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3447 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3449 // Common patterns involving scalar load
3450 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3451 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3452 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3453 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3455 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3456 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3457 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3458 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3461 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3462 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3463 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3464 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3466 // Expecting a i16 load any extended to i32 value.
3467 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3468 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3469 [(set VR128:$dst, (IntId (bitconvert
3470 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3474 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3475 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3477 // Common patterns involving scalar load
3478 def : Pat<(int_x86_sse41_pmovsxbq
3479 (bitconvert (v4i32 (X86vzmovl
3480 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3481 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3483 def : Pat<(int_x86_sse41_pmovzxbq
3484 (bitconvert (v4i32 (X86vzmovl
3485 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3486 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3489 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3490 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3491 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3492 (ins VR128:$src1, i32i8imm:$src2),
3493 !strconcat(OpcodeStr,
3494 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3495 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3497 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3498 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3499 !strconcat(OpcodeStr,
3500 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3503 // There's an AssertZext in the way of writing the store pattern
3504 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3507 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3510 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3511 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3512 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3513 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3514 !strconcat(OpcodeStr,
3515 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3518 // There's an AssertZext in the way of writing the store pattern
3519 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3522 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3525 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3526 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3527 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3528 (ins VR128:$src1, i32i8imm:$src2),
3529 !strconcat(OpcodeStr,
3530 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3532 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3533 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3534 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3535 !strconcat(OpcodeStr,
3536 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3537 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3538 addr:$dst)]>, OpSize;
3541 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3544 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3546 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3547 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3548 (ins VR128:$src1, i32i8imm:$src2),
3549 !strconcat(OpcodeStr,
3550 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3552 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3554 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3555 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3556 !strconcat(OpcodeStr,
3557 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3558 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3559 addr:$dst)]>, OpSize;
3562 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3564 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3565 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3568 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3569 Requires<[HasSSE41]>;
3571 let Constraints = "$src1 = $dst" in {
3572 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3573 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3574 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3575 !strconcat(OpcodeStr,
3576 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3578 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3579 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3580 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3581 !strconcat(OpcodeStr,
3582 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3584 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3585 imm:$src3))]>, OpSize;
3589 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3591 let Constraints = "$src1 = $dst" in {
3592 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3593 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3594 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3595 !strconcat(OpcodeStr,
3596 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3598 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3600 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3601 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3602 !strconcat(OpcodeStr,
3603 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3605 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3606 imm:$src3)))]>, OpSize;
3610 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3612 // insertps has a few different modes, there's the first two here below which
3613 // are optimized inserts that won't zero arbitrary elements in the destination
3614 // vector. The next one matches the intrinsic and could zero arbitrary elements
3615 // in the target vector.
3616 let Constraints = "$src1 = $dst" in {
3617 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3618 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3619 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3620 !strconcat(OpcodeStr,
3621 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3623 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3625 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3626 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3627 !strconcat(OpcodeStr,
3628 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3630 (X86insrtps VR128:$src1,
3631 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3632 imm:$src3))]>, OpSize;
3636 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3638 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3639 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3641 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3642 // the intel intrinsic that corresponds to this.
3643 let Defs = [EFLAGS] in {
3644 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3645 "ptest \t{$src2, $src1|$src1, $src2}",
3646 [(X86ptest VR128:$src1, VR128:$src2),
3647 (implicit EFLAGS)]>, OpSize;
3648 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3649 "ptest \t{$src2, $src1|$src1, $src2}",
3650 [(X86ptest VR128:$src1, (load addr:$src2)),
3651 (implicit EFLAGS)]>, OpSize;
3654 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3655 "movntdqa\t{$src, $dst|$dst, $src}",
3656 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
3658 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3659 let Constraints = "$src1 = $dst" in {
3660 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3661 Intrinsic IntId128, bit Commutable = 0> {
3662 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3663 (ins VR128:$src1, VR128:$src2),
3664 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3665 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3667 let isCommutable = Commutable;
3669 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3670 (ins VR128:$src1, i128mem:$src2),
3671 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3673 (IntId128 VR128:$src1,
3674 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3678 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3680 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3681 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3682 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3683 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3685 // crc intrinsic instruction
3686 // This set of instructions are only rm, the only difference is the size
3688 let Constraints = "$src1 = $dst" in {
3689 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3690 (ins GR32:$src1, i8mem:$src2),
3691 "crc32 \t{$src2, $src1|$src1, $src2}",
3693 (int_x86_sse42_crc32_8 GR32:$src1,
3694 (load addr:$src2)))]>, OpSize;
3695 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3696 (ins GR32:$src1, GR8:$src2),
3697 "crc32 \t{$src2, $src1|$src1, $src2}",
3699 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>,
3701 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3702 (ins GR32:$src1, i16mem:$src2),
3703 "crc32 \t{$src2, $src1|$src1, $src2}",
3705 (int_x86_sse42_crc32_16 GR32:$src1,
3706 (load addr:$src2)))]>,
3708 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3709 (ins GR32:$src1, GR16:$src2),
3710 "crc32 \t{$src2, $src1|$src1, $src2}",
3712 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3714 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3715 (ins GR32:$src1, i32mem:$src2),
3716 "crc32 \t{$src2, $src1|$src1, $src2}",
3718 (int_x86_sse42_crc32_32 GR32:$src1,
3719 (load addr:$src2)))]>, OpSize;
3720 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3721 (ins GR32:$src1, GR32:$src2),
3722 "crc32 \t{$src2, $src1|$src1, $src2}",
3724 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>,
3726 def CRC64m64 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3727 (ins GR64:$src1, i64mem:$src2),
3728 "crc32 \t{$src2, $src1|$src1, $src2}",
3730 (int_x86_sse42_crc32_64 GR64:$src1,
3731 (load addr:$src2)))]>,
3733 def CRC64r64 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3734 (ins GR64:$src1, GR64:$src2),
3735 "crc32 \t{$src2, $src1|$src1, $src2}",
3737 (int_x86_sse42_crc32_64 GR64:$src1, GR64:$src2))]>,