1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // SSE specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
22 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
23 [SDNPCommutative, SDNPAssociative]>;
24 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
25 [SDNPCommutative, SDNPAssociative]>;
26 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
28 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
30 def X86s2vec : SDNode<"X86ISD::S2VEC",
31 SDTypeProfile<1, 1, []>, []>;
32 def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
33 SDTypeProfile<1, 1, []>, []>;
34 def X86pextrw : SDNode<"X86ISD::PEXTRW",
35 SDTypeProfile<1, 2, []>, []>;
36 def X86pinsrw : SDNode<"X86ISD::PINSRW",
37 SDTypeProfile<1, 3, []>, []>;
39 //===----------------------------------------------------------------------===//
40 // SSE pattern fragments
41 //===----------------------------------------------------------------------===//
43 def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
44 def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
46 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
47 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
48 def loadv16i8 : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>;
49 def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>;
50 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
51 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
53 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
54 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
55 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
56 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
57 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
58 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
60 def fp32imm0 : PatLeaf<(f32 fpimm), [{
61 return N->isExactlyValue(+0.0);
64 def PSxLDQ_imm : SDNodeXForm<imm, [{
65 // Transformation function: imm >> 3
66 return getI32Imm(N->getValue() >> 3);
69 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
71 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
72 return getI8Imm(X86::getShuffleSHUFImmediate(N));
75 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
77 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
78 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
81 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
83 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
84 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
87 def SSE_splat_mask : PatLeaf<(build_vector), [{
88 return X86::isSplatMask(N);
89 }], SHUFFLE_get_shuf_imm>;
91 def MOVLHPS_shuffle_mask : PatLeaf<(build_vector), [{
92 return X86::isMOVLHPSMask(N);
95 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
96 return X86::isMOVHLPSMask(N);
99 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
100 return X86::isMOVHPMask(N);
103 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
104 return X86::isMOVLPMask(N);
107 def MOVS_shuffle_mask : PatLeaf<(build_vector), [{
108 return X86::isMOVSMask(N);
111 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
112 return X86::isUNPCKLMask(N);
115 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
116 return X86::isUNPCKHMask(N);
119 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
120 return X86::isUNPCKL_v_undef_Mask(N);
123 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
124 return X86::isPSHUFDMask(N);
125 }], SHUFFLE_get_shuf_imm>;
127 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
128 return X86::isPSHUFHWMask(N);
129 }], SHUFFLE_get_pshufhw_imm>;
131 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
132 return X86::isPSHUFLWMask(N);
133 }], SHUFFLE_get_pshuflw_imm>;
135 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
136 return X86::isPSHUFDMask(N);
137 }], SHUFFLE_get_shuf_imm>;
139 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
140 return X86::isSHUFPMask(N);
141 }], SHUFFLE_get_shuf_imm>;
143 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
144 return X86::isSHUFPMask(N);
145 }], SHUFFLE_get_shuf_imm>;
147 //===----------------------------------------------------------------------===//
148 // SSE scalar FP Instructions
149 //===----------------------------------------------------------------------===//
151 // Instruction templates
152 // SSI - SSE1 instructions with XS prefix.
153 // SDI - SSE2 instructions with XD prefix.
154 // PSI - SSE1 instructions with TB prefix.
155 // PDI - SSE2 instructions with TB and OpSize prefixes.
156 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
157 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
158 // S3SI - SSE3 instructions with XD prefix.
159 // S3DI - SSE3 instructions with TB and OpSize prefixes.
160 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
161 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
162 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
163 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
164 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
165 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
166 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
167 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
168 class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
169 : X86Inst<o, F, Imm8, ops, asm>, TB, Requires<[HasSSE1]> {
170 let Pattern = pattern;
172 class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
173 : X86Inst<o, F, Imm8, ops, asm>, TB, OpSize, Requires<[HasSSE2]> {
174 let Pattern = pattern;
176 class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
177 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
178 class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
179 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
181 //===----------------------------------------------------------------------===//
182 // Helpers for defining instructions that directly correspond to intrinsics.
183 class SS_Intr<bits<8> o, string asm, Intrinsic IntId>
184 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
185 [(set VR128:$dst, (v4f32 (IntId VR128:$src)))]>;
186 class SS_Intm<bits<8> o, string asm, Intrinsic IntId>
187 : SSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
188 [(set VR128:$dst, (v4f32 (IntId (load addr:$src))))]>;
189 class SD_Intr<bits<8> o, string asm, Intrinsic IntId>
190 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
191 [(set VR128:$dst, (v2f64 (IntId VR128:$src)))]>;
192 class SD_Intm<bits<8> o, string asm, Intrinsic IntId>
193 : SDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
194 [(set VR128:$dst, (v2f64 (IntId (load addr:$src))))]>;
196 class SS_Intrr<bits<8> o, string asm, Intrinsic IntId>
197 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
198 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
199 class SS_Intrm<bits<8> o, string asm, Intrinsic IntId>
200 : SSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
201 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
202 class SD_Intrr<bits<8> o, string asm, Intrinsic IntId>
203 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
204 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
205 class SD_Intrm<bits<8> o, string asm, Intrinsic IntId>
206 : SDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
207 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
209 class PS_Intr<bits<8> o, string asm, Intrinsic IntId>
210 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
211 [(set VR128:$dst, (IntId VR128:$src))]>;
212 class PS_Intm<bits<8> o, string asm, Intrinsic IntId>
213 : PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
214 [(set VR128:$dst, (IntId (loadv4f32 addr:$src)))]>;
215 class PD_Intr<bits<8> o, string asm, Intrinsic IntId>
216 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
217 [(set VR128:$dst, (IntId VR128:$src))]>;
218 class PD_Intm<bits<8> o, string asm, Intrinsic IntId>
219 : PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
220 [(set VR128:$dst, (IntId (loadv2f64 addr:$src)))]>;
222 class PS_Intrr<bits<8> o, string asm, Intrinsic IntId>
223 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
224 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
225 class PS_Intrm<bits<8> o, string asm, Intrinsic IntId>
226 : PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
227 [(set VR128:$dst, (IntId VR128:$src1, (loadv4f32 addr:$src2)))]>;
228 class PD_Intrr<bits<8> o, string asm, Intrinsic IntId>
229 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
230 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
231 class PD_Intrm<bits<8> o, string asm, Intrinsic IntId>
232 : PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
233 [(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))]>;
235 class S3S_Intrr<bits<8> o, string asm, Intrinsic IntId>
236 : S3SI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
237 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
238 class S3S_Intrm<bits<8> o, string asm, Intrinsic IntId>
239 : S3SI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
240 [(set VR128:$dst, (v4f32 (IntId VR128:$src1,
241 (loadv4f32 addr:$src2))))]>;
242 class S3D_Intrr<bits<8> o, string asm, Intrinsic IntId>
243 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
244 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
245 class S3D_Intrm<bits<8> o, string asm, Intrinsic IntId>
246 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
247 [(set VR128:$dst, (v2f64 (IntId VR128:$src1,
248 (loadv2f64 addr:$src2))))]>;
250 // Some 'special' instructions
251 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
252 "#IMPLICIT_DEF $dst",
253 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
254 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
255 "#IMPLICIT_DEF $dst",
256 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
258 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
259 // scheduler into a branch sequence.
260 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
261 def CMOV_FR32 : I<0, Pseudo,
262 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
263 "#CMOV_FR32 PSEUDO!",
264 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
265 def CMOV_FR64 : I<0, Pseudo,
266 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
267 "#CMOV_FR64 PSEUDO!",
268 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
269 def CMOV_V4F32 : I<0, Pseudo,
270 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
271 "#CMOV_V4F32 PSEUDO!",
273 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
274 def CMOV_V2F64 : I<0, Pseudo,
275 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
276 "#CMOV_V2F64 PSEUDO!",
278 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
279 def CMOV_V2I64 : I<0, Pseudo,
280 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
281 "#CMOV_V2I64 PSEUDO!",
283 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
287 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
288 "movss {$src, $dst|$dst, $src}", []>;
289 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
290 "movss {$src, $dst|$dst, $src}",
291 [(set FR32:$dst, (loadf32 addr:$src))]>;
292 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
293 "movsd {$src, $dst|$dst, $src}", []>;
294 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
295 "movsd {$src, $dst|$dst, $src}",
296 [(set FR64:$dst, (loadf64 addr:$src))]>;
298 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
299 "movss {$src, $dst|$dst, $src}",
300 [(store FR32:$src, addr:$dst)]>;
301 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
302 "movsd {$src, $dst|$dst, $src}",
303 [(store FR64:$src, addr:$dst)]>;
305 // Arithmetic instructions
306 let isTwoAddress = 1 in {
307 let isCommutable = 1 in {
308 def ADDSSrr : SSI<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
309 "addss {$src2, $dst|$dst, $src2}",
310 [(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>;
311 def ADDSDrr : SDI<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
312 "addsd {$src2, $dst|$dst, $src2}",
313 [(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>;
314 def MULSSrr : SSI<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
315 "mulss {$src2, $dst|$dst, $src2}",
316 [(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>;
317 def MULSDrr : SDI<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
318 "mulsd {$src2, $dst|$dst, $src2}",
319 [(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>;
322 def ADDSSrm : SSI<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
323 "addss {$src2, $dst|$dst, $src2}",
324 [(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>;
325 def ADDSDrm : SDI<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
326 "addsd {$src2, $dst|$dst, $src2}",
327 [(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>;
328 def MULSSrm : SSI<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
329 "mulss {$src2, $dst|$dst, $src2}",
330 [(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>;
331 def MULSDrm : SDI<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
332 "mulsd {$src2, $dst|$dst, $src2}",
333 [(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>;
335 def DIVSSrr : SSI<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
336 "divss {$src2, $dst|$dst, $src2}",
337 [(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>;
338 def DIVSSrm : SSI<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
339 "divss {$src2, $dst|$dst, $src2}",
340 [(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>;
341 def DIVSDrr : SDI<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
342 "divsd {$src2, $dst|$dst, $src2}",
343 [(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>;
344 def DIVSDrm : SDI<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
345 "divsd {$src2, $dst|$dst, $src2}",
346 [(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>;
348 def SUBSSrr : SSI<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
349 "subss {$src2, $dst|$dst, $src2}",
350 [(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>;
351 def SUBSSrm : SSI<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
352 "subss {$src2, $dst|$dst, $src2}",
353 [(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>;
354 def SUBSDrr : SDI<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
355 "subsd {$src2, $dst|$dst, $src2}",
356 [(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>;
357 def SUBSDrm : SDI<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
358 "subsd {$src2, $dst|$dst, $src2}",
359 [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>;
362 def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
363 "sqrtss {$src, $dst|$dst, $src}",
364 [(set FR32:$dst, (fsqrt FR32:$src))]>;
365 def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
366 "sqrtss {$src, $dst|$dst, $src}",
367 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
368 def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
369 "sqrtsd {$src, $dst|$dst, $src}",
370 [(set FR64:$dst, (fsqrt FR64:$src))]>;
371 def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
372 "sqrtsd {$src, $dst|$dst, $src}",
373 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
375 def RSQRTSSr : SSI<0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
376 "rsqrtss {$src, $dst|$dst, $src}", []>;
377 def RSQRTSSm : SSI<0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
378 "rsqrtss {$src, $dst|$dst, $src}", []>;
379 def RCPSSr : SSI<0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
380 "rcpss {$src, $dst|$dst, $src}", []>;
381 def RCPSSm : SSI<0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
382 "rcpss {$src, $dst|$dst, $src}", []>;
384 let isTwoAddress = 1 in {
385 def MAXSSrr : SSI<0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
386 "maxss {$src2, $dst|$dst, $src2}", []>;
387 def MAXSSrm : SSI<0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
388 "maxss {$src2, $dst|$dst, $src2}", []>;
389 def MAXSDrr : SDI<0x5F, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
390 "maxsd {$src2, $dst|$dst, $src2}", []>;
391 def MAXSDrm : SDI<0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
392 "maxsd {$src2, $dst|$dst, $src2}", []>;
393 def MINSSrr : SSI<0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
394 "minss {$src2, $dst|$dst, $src2}", []>;
395 def MINSSrm : SSI<0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
396 "minss {$src2, $dst|$dst, $src2}", []>;
397 def MINSDrr : SDI<0x5D, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
398 "minsd {$src2, $dst|$dst, $src2}", []>;
399 def MINSDrm : SDI<0x5D, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
400 "minsd {$src2, $dst|$dst, $src2}", []>;
403 // Aliases to match intrinsics which expect XMM operand(s).
404 let isTwoAddress = 1 in {
405 let isCommutable = 1 in {
406 def Int_ADDSSrr : SS_Intrr<0x58, "addss {$src2, $dst|$dst, $src2}",
408 def Int_ADDSDrr : SD_Intrr<0x58, "addsd {$src2, $dst|$dst, $src2}",
409 int_x86_sse2_add_sd>;
410 def Int_MULSSrr : SS_Intrr<0x59, "mulss {$src2, $dst|$dst, $src2}",
412 def Int_MULSDrr : SD_Intrr<0x59, "mulsd {$src2, $dst|$dst, $src2}",
413 int_x86_sse2_mul_sd>;
416 def Int_ADDSSrm : SS_Intrm<0x58, "addss {$src2, $dst|$dst, $src2}",
418 def Int_ADDSDrm : SD_Intrm<0x58, "addsd {$src2, $dst|$dst, $src2}",
419 int_x86_sse2_add_sd>;
420 def Int_MULSSrm : SS_Intrm<0x59, "mulss {$src2, $dst|$dst, $src2}",
422 def Int_MULSDrm : SD_Intrm<0x59, "mulsd {$src2, $dst|$dst, $src2}",
423 int_x86_sse2_mul_sd>;
425 def Int_DIVSSrr : SS_Intrr<0x5E, "divss {$src2, $dst|$dst, $src2}",
427 def Int_DIVSSrm : SS_Intrm<0x5E, "divss {$src2, $dst|$dst, $src2}",
429 def Int_DIVSDrr : SD_Intrr<0x5E, "divsd {$src2, $dst|$dst, $src2}",
430 int_x86_sse2_div_sd>;
431 def Int_DIVSDrm : SD_Intrm<0x5E, "divsd {$src2, $dst|$dst, $src2}",
432 int_x86_sse2_div_sd>;
434 def Int_SUBSSrr : SS_Intrr<0x5C, "subss {$src2, $dst|$dst, $src2}",
436 def Int_SUBSSrm : SS_Intrm<0x5C, "subss {$src2, $dst|$dst, $src2}",
438 def Int_SUBSDrr : SD_Intrr<0x5C, "subsd {$src2, $dst|$dst, $src2}",
439 int_x86_sse2_sub_sd>;
440 def Int_SUBSDrm : SD_Intrm<0x5C, "subsd {$src2, $dst|$dst, $src2}",
441 int_x86_sse2_sub_sd>;
444 def Int_SQRTSSr : SS_Intr<0x51, "sqrtss {$src, $dst|$dst, $src}",
445 int_x86_sse_sqrt_ss>;
446 def Int_SQRTSSm : SS_Intm<0x51, "sqrtss {$src, $dst|$dst, $src}",
447 int_x86_sse_sqrt_ss>;
448 def Int_SQRTSDr : SD_Intr<0x51, "sqrtsd {$src, $dst|$dst, $src}",
449 int_x86_sse2_sqrt_sd>;
450 def Int_SQRTSDm : SD_Intm<0x51, "sqrtsd {$src, $dst|$dst, $src}",
451 int_x86_sse2_sqrt_sd>;
453 def Int_RSQRTSSr : SS_Intr<0x52, "rsqrtss {$src, $dst|$dst, $src}",
454 int_x86_sse_rsqrt_ss>;
455 def Int_RSQRTSSm : SS_Intm<0x52, "rsqrtss {$src, $dst|$dst, $src}",
456 int_x86_sse_rsqrt_ss>;
457 def Int_RCPSSr : SS_Intr<0x53, "rcpss {$src, $dst|$dst, $src}",
459 def Int_RCPSSm : SS_Intm<0x53, "rcpss {$src, $dst|$dst, $src}",
462 let isTwoAddress = 1 in {
463 def Int_MAXSSrr : SS_Intrr<0x5F, "maxss {$src2, $dst|$dst, $src2}",
465 def Int_MAXSSrm : SS_Intrm<0x5F, "maxss {$src2, $dst|$dst, $src2}",
467 def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
468 int_x86_sse2_max_sd>;
469 def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
470 int_x86_sse2_max_sd>;
471 def Int_MINSSrr : SS_Intrr<0x5D, "minss {$src2, $dst|$dst, $src2}",
473 def Int_MINSSrm : SS_Intrm<0x5D, "minss {$src2, $dst|$dst, $src2}",
475 def Int_MINSDrr : SD_Intrr<0x5D, "minsd {$src2, $dst|$dst, $src2}",
476 int_x86_sse2_min_sd>;
477 def Int_MINSDrm : SD_Intrm<0x5D, "minsd {$src2, $dst|$dst, $src2}",
478 int_x86_sse2_min_sd>;
481 // Conversion instructions
482 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, FR32:$src),
483 "cvtss2si {$src, $dst|$dst, $src}", []>;
484 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
485 "cvtss2si {$src, $dst|$dst, $src}", []>;
487 def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
488 "cvttss2si {$src, $dst|$dst, $src}",
489 [(set R32:$dst, (fp_to_sint FR32:$src))]>;
490 def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
491 "cvttss2si {$src, $dst|$dst, $src}",
492 [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
493 def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
494 "cvttsd2si {$src, $dst|$dst, $src}",
495 [(set R32:$dst, (fp_to_sint FR64:$src))]>;
496 def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
497 "cvttsd2si {$src, $dst|$dst, $src}",
498 [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
499 def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
500 "cvtsd2ss {$src, $dst|$dst, $src}",
501 [(set FR32:$dst, (fround FR64:$src))]>;
502 def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
503 "cvtsd2ss {$src, $dst|$dst, $src}",
504 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
505 def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
506 "cvtsi2ss {$src, $dst|$dst, $src}",
507 [(set FR32:$dst, (sint_to_fp R32:$src))]>;
508 def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
509 "cvtsi2ss {$src, $dst|$dst, $src}",
510 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
511 def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
512 "cvtsi2sd {$src, $dst|$dst, $src}",
513 [(set FR64:$dst, (sint_to_fp R32:$src))]>;
514 def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
515 "cvtsi2sd {$src, $dst|$dst, $src}",
516 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
517 // SSE2 instructions with XS prefix
518 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
519 "cvtss2sd {$src, $dst|$dst, $src}",
520 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
522 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
523 "cvtss2sd {$src, $dst|$dst, $src}",
524 [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS,
527 // Comparison instructions
528 let isTwoAddress = 1 in {
529 def CMPSSrr : SSI<0xC2, MRMSrcReg,
530 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
531 "cmp${cc}ss {$src, $dst|$dst, $src}",
533 def CMPSSrm : SSI<0xC2, MRMSrcMem,
534 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
535 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
536 def CMPSDrr : SDI<0xC2, MRMSrcReg,
537 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
538 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
539 def CMPSDrm : SDI<0xC2, MRMSrcMem,
540 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
541 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
544 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
545 "ucomiss {$src2, $src1|$src1, $src2}",
546 [(X86cmp FR32:$src1, FR32:$src2)]>;
547 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
548 "ucomiss {$src2, $src1|$src1, $src2}",
549 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
550 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
551 "ucomisd {$src2, $src1|$src1, $src2}",
552 [(X86cmp FR64:$src1, FR64:$src2)]>;
553 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
554 "ucomisd {$src2, $src1|$src1, $src2}",
555 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
557 // Aliases to match intrinsics which expect XMM operand(s).
558 let isTwoAddress = 1 in {
559 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
560 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
561 "cmp${cc}ss {$src, $dst|$dst, $src}",
562 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
563 VR128:$src, imm:$cc))]>;
564 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
565 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
566 "cmp${cc}ss {$src, $dst|$dst, $src}",
567 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
568 (load addr:$src), imm:$cc))]>;
569 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
570 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
571 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
572 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
573 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
574 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
577 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
578 "ucomiss {$src2, $src1|$src1, $src2}",
579 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
580 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
581 "ucomiss {$src2, $src1|$src1, $src2}",
582 [(X86ucomi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
583 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
584 "ucomisd {$src2, $src1|$src1, $src2}",
585 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
586 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
587 "ucomisd {$src2, $src1|$src1, $src2}",
588 [(X86ucomi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
590 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
591 "comiss {$src2, $src1|$src1, $src2}",
592 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
593 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
594 "comiss {$src2, $src1|$src1, $src2}",
595 [(X86comi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
596 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
597 "comisd {$src2, $src1|$src1, $src2}",
598 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
599 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
600 "comisd {$src2, $src1|$src1, $src2}",
601 [(X86comi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
603 // Aliases of packed instructions for scalar use. These all have names that
606 // Alias instructions that map fld0 to pxor for sse.
607 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
608 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
609 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
610 Requires<[HasSSE1]>, TB, OpSize;
611 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
612 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
613 Requires<[HasSSE2]>, TB, OpSize;
615 // Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
616 // Upper bits are disregarded.
617 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
618 "movaps {$src, $dst|$dst, $src}", []>;
619 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
620 "movapd {$src, $dst|$dst, $src}", []>;
622 // Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
623 // Upper bits are disregarded.
624 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
625 "movaps {$src, $dst|$dst, $src}",
626 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
627 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
628 "movapd {$src, $dst|$dst, $src}",
629 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
631 // Alias bitwise logical operations using SSE logical ops on packed FP values.
632 let isTwoAddress = 1 in {
633 let isCommutable = 1 in {
634 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
635 "andps {$src2, $dst|$dst, $src2}",
636 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
637 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
638 "andpd {$src2, $dst|$dst, $src2}",
639 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
640 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
641 "orps {$src2, $dst|$dst, $src2}", []>;
642 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
643 "orpd {$src2, $dst|$dst, $src2}", []>;
644 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
645 "xorps {$src2, $dst|$dst, $src2}",
646 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
647 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
648 "xorpd {$src2, $dst|$dst, $src2}",
649 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
651 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
652 "andps {$src2, $dst|$dst, $src2}",
653 [(set FR32:$dst, (X86fand FR32:$src1,
654 (X86loadpf32 addr:$src2)))]>;
655 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
656 "andpd {$src2, $dst|$dst, $src2}",
657 [(set FR64:$dst, (X86fand FR64:$src1,
658 (X86loadpf64 addr:$src2)))]>;
659 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
660 "orps {$src2, $dst|$dst, $src2}", []>;
661 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
662 "orpd {$src2, $dst|$dst, $src2}", []>;
663 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
664 "xorps {$src2, $dst|$dst, $src2}",
665 [(set FR32:$dst, (X86fxor FR32:$src1,
666 (X86loadpf32 addr:$src2)))]>;
667 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
668 "xorpd {$src2, $dst|$dst, $src2}",
669 [(set FR64:$dst, (X86fxor FR64:$src1,
670 (X86loadpf64 addr:$src2)))]>;
672 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
673 "andnps {$src2, $dst|$dst, $src2}", []>;
674 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
675 "andnps {$src2, $dst|$dst, $src2}", []>;
676 def FsANDNPDrr : PDI<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
677 "andnpd {$src2, $dst|$dst, $src2}", []>;
678 def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
679 "andnpd {$src2, $dst|$dst, $src2}", []>;
682 //===----------------------------------------------------------------------===//
683 // SSE packed FP Instructions
684 //===----------------------------------------------------------------------===//
686 // Some 'special' instructions
687 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
688 "#IMPLICIT_DEF $dst",
689 [(set VR128:$dst, (v4f32 (undef)))]>,
693 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
694 "movaps {$src, $dst|$dst, $src}", []>;
695 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
696 "movaps {$src, $dst|$dst, $src}",
697 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
698 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
699 "movapd {$src, $dst|$dst, $src}", []>;
700 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
701 "movapd {$src, $dst|$dst, $src}",
702 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
704 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
705 "movaps {$src, $dst|$dst, $src}",
706 [(store (v4f32 VR128:$src), addr:$dst)]>;
707 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
708 "movapd {$src, $dst|$dst, $src}",
709 [(store (v2f64 VR128:$src), addr:$dst)]>;
711 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
712 "movups {$src, $dst|$dst, $src}", []>;
713 def MOVUPSrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
714 "movups {$src, $dst|$dst, $src}",
715 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
716 def MOVUPSmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
717 "movups {$src, $dst|$dst, $src}",
718 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
719 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
720 "movupd {$src, $dst|$dst, $src}", []>;
721 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
722 "movupd {$src, $dst|$dst, $src}",
723 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
724 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
725 "movupd {$src, $dst|$dst, $src}",
726 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
728 let isTwoAddress = 1 in {
729 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
730 "movlps {$src2, $dst|$dst, $src2}",
732 (v4f32 (vector_shuffle VR128:$src1,
733 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
734 MOVLP_shuffle_mask)))]>;
735 def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
736 "movlpd {$src2, $dst|$dst, $src2}",
738 (v2f64 (vector_shuffle VR128:$src1,
739 (scalar_to_vector (loadf64 addr:$src2)),
740 MOVLP_shuffle_mask)))]>;
741 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
742 "movhps {$src2, $dst|$dst, $src2}",
744 (v4f32 (vector_shuffle VR128:$src1,
745 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
746 MOVHP_shuffle_mask)))]>;
747 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
748 "movhpd {$src2, $dst|$dst, $src2}",
750 (v2f64 (vector_shuffle VR128:$src1,
751 (scalar_to_vector (loadf64 addr:$src2)),
752 MOVHP_shuffle_mask)))]>;
755 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
756 "movlps {$src, $dst|$dst, $src}",
757 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
758 (i32 0))), addr:$dst)]>;
759 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
760 "movlpd {$src, $dst|$dst, $src}",
761 [(store (f64 (vector_extract (v2f64 VR128:$src),
762 (i32 0))), addr:$dst)]>;
764 // v2f64 extract element 1 is always custom lowered to unpack high to low
765 // and extract element 0 so the non-store version isn't too horrible.
766 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
767 "movhps {$src, $dst|$dst, $src}",
768 [(store (f64 (vector_extract
769 (v2f64 (vector_shuffle
770 (bc_v2f64 (v4f32 VR128:$src)), (undef),
771 UNPCKH_shuffle_mask)), (i32 0))),
773 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
774 "movhpd {$src, $dst|$dst, $src}",
775 [(store (f64 (vector_extract
776 (v2f64 (vector_shuffle VR128:$src, (undef),
777 UNPCKH_shuffle_mask)), (i32 0))),
780 let isTwoAddress = 1 in {
781 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
782 "movlhps {$src2, $dst|$dst, $src2}",
784 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
785 MOVLHPS_shuffle_mask)))]>;
787 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
788 "movhlps {$src2, $dst|$dst, $src2}",
790 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
791 MOVHLPS_shuffle_mask)))]>;
794 // Conversion instructions
795 def CVTPI2PSr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
796 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
797 def CVTPI2PSm : PSI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
798 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
799 def CVTPI2PDr : PDI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
800 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
801 def CVTPI2PDm : PDI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
802 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
804 // SSE2 instructions without OpSize prefix
805 def CVTDQ2PSr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
806 "cvtdq2ps {$src, $dst|$dst, $src}", []>, TB,
808 def CVTDQ2PSm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
809 "cvtdq2ps {$src, $dst|$dst, $src}", []>, TB,
812 // SSE2 instructions with XS prefix
813 def CVTDQ2PDr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR64:$src),
814 "cvtdq2pd {$src, $dst|$dst, $src}", []>,
815 XS, Requires<[HasSSE2]>;
816 def CVTDQ2PDm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
817 "cvtdq2pd {$src, $dst|$dst, $src}", []>,
818 XS, Requires<[HasSSE2]>;
820 def CVTPS2PIr : PSI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
821 "cvtps2pi {$src, $dst|$dst, $src}", []>;
822 def CVTPS2PIm : PSI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
823 "cvtps2pi {$src, $dst|$dst, $src}", []>;
824 def CVTPD2PIr : PDI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
825 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
826 def CVTPD2PIm : PDI<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
827 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
829 def CVTPS2DQr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
830 "cvtps2dq {$src, $dst|$dst, $src}", []>;
831 def CVTPS2DQm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
832 "cvtps2dq {$src, $dst|$dst, $src}", []>;
833 // SSE2 packed instructions with XD prefix
834 def CVTPD2DQr : SDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
835 "cvtpd2dq {$src, $dst|$dst, $src}", []>;
836 def CVTPD2DQm : SDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
837 "cvtpd2dq {$src, $dst|$dst, $src}", []>;
839 // SSE2 instructions without OpSize prefix
840 def CVTPS2PDr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
841 "cvtps2pd {$src, $dst|$dst, $src}", []>, TB,
843 def CVTPS2PDm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
844 "cvtps2pd {$src, $dst|$dst, $src}", []>, TB,
847 def CVTPD2PSr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
848 "cvtpd2ps {$src, $dst|$dst, $src}", []>;
849 def CVTPD2PSm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
850 "cvtpd2ps {$src, $dst|$dst, $src}", []>;
853 let isTwoAddress = 1 in {
854 let isCommutable = 1 in {
855 def ADDPSrr : PSI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
856 "addps {$src2, $dst|$dst, $src2}",
857 [(set VR128:$dst, (v4f32 (fadd VR128:$src1, VR128:$src2)))]>;
858 def ADDPDrr : PDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
859 "addpd {$src2, $dst|$dst, $src2}",
860 [(set VR128:$dst, (v2f64 (fadd VR128:$src1, VR128:$src2)))]>;
861 def MULPSrr : PSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
862 "mulps {$src2, $dst|$dst, $src2}",
863 [(set VR128:$dst, (v4f32 (fmul VR128:$src1, VR128:$src2)))]>;
864 def MULPDrr : PDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
865 "mulpd {$src2, $dst|$dst, $src2}",
866 [(set VR128:$dst, (v2f64 (fmul VR128:$src1, VR128:$src2)))]>;
869 def ADDPSrm : PSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
870 "addps {$src2, $dst|$dst, $src2}",
871 [(set VR128:$dst, (v4f32 (fadd VR128:$src1,
872 (load addr:$src2))))]>;
873 def ADDPDrm : PDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
874 "addpd {$src2, $dst|$dst, $src2}",
875 [(set VR128:$dst, (v2f64 (fadd VR128:$src1,
876 (load addr:$src2))))]>;
877 def MULPSrm : PSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
878 "mulps {$src2, $dst|$dst, $src2}",
879 [(set VR128:$dst, (v4f32 (fmul VR128:$src1,
880 (load addr:$src2))))]>;
881 def MULPDrm : PDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
882 "mulpd {$src2, $dst|$dst, $src2}",
883 [(set VR128:$dst, (v2f64 (fmul VR128:$src1,
884 (load addr:$src2))))]>;
886 def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
887 "divps {$src2, $dst|$dst, $src2}",
888 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1, VR128:$src2)))]>;
889 def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
890 "divps {$src2, $dst|$dst, $src2}",
891 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1,
892 (load addr:$src2))))]>;
893 def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
894 "divpd {$src2, $dst|$dst, $src2}",
895 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1, VR128:$src2)))]>;
896 def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
897 "divpd {$src2, $dst|$dst, $src2}",
898 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1,
899 (load addr:$src2))))]>;
901 def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
902 "subps {$src2, $dst|$dst, $src2}",
903 [(set VR128:$dst, (v4f32 (fsub VR128:$src1, VR128:$src2)))]>;
904 def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
905 "subps {$src2, $dst|$dst, $src2}",
906 [(set VR128:$dst, (v4f32 (fsub VR128:$src1,
907 (load addr:$src2))))]>;
908 def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
909 "subpd {$src2, $dst|$dst, $src2}",
910 [(set VR128:$dst, (v2f64 (fsub VR128:$src1, VR128:$src2)))]>;
911 def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
912 "subpd {$src2, $dst|$dst, $src2}",
913 [(set VR128:$dst, (v2f64 (fsub VR128:$src1,
914 (load addr:$src2))))]>;
917 def SQRTPSr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}",
918 int_x86_sse_sqrt_ps>;
919 def SQRTPSm : PS_Intm<0x51, "sqrtps {$src, $dst|$dst, $src}",
920 int_x86_sse_sqrt_ps>;
921 def SQRTPDr : PD_Intr<0x51, "sqrtpd {$src, $dst|$dst, $src}",
922 int_x86_sse2_sqrt_pd>;
923 def SQRTPDm : PD_Intm<0x51, "sqrtpd {$src, $dst|$dst, $src}",
924 int_x86_sse2_sqrt_pd>;
926 def RSQRTPSr : PS_Intr<0x52, "rsqrtps {$src, $dst|$dst, $src}",
927 int_x86_sse_rsqrt_ps>;
928 def RSQRTPSm : PS_Intm<0x52, "rsqrtps {$src, $dst|$dst, $src}",
929 int_x86_sse_rsqrt_ps>;
930 def RCPPSr : PS_Intr<0x53, "rcpps {$src, $dst|$dst, $src}",
932 def RCPPSm : PS_Intm<0x53, "rcpps {$src, $dst|$dst, $src}",
935 let isTwoAddress = 1 in {
936 def MAXPSrr : PS_Intrr<0x5F, "maxps {$src2, $dst|$dst, $src2}",
938 def MAXPSrm : PS_Intrm<0x5F, "maxps {$src2, $dst|$dst, $src2}",
940 def MAXPDrr : PD_Intrr<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
941 int_x86_sse2_max_pd>;
942 def MAXPDrm : PD_Intrm<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
943 int_x86_sse2_max_pd>;
944 def MINPSrr : PS_Intrr<0x5D, "minps {$src2, $dst|$dst, $src2}",
946 def MINPSrm : PS_Intrm<0x5D, "minps {$src2, $dst|$dst, $src2}",
948 def MINPDrr : PD_Intrr<0x5D, "minpd {$src2, $dst|$dst, $src2}",
949 int_x86_sse2_min_pd>;
950 def MINPDrm : PD_Intrm<0x5D, "minpd {$src2, $dst|$dst, $src2}",
951 int_x86_sse2_min_pd>;
955 let isTwoAddress = 1 in {
956 let isCommutable = 1 in {
957 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
958 "andps {$src2, $dst|$dst, $src2}",
960 (and (bc_v4i32 (v4f32 VR128:$src1)),
961 (bc_v4i32 (v4f32 VR128:$src2))))]>;
962 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
963 "andpd {$src2, $dst|$dst, $src2}",
965 (and (bc_v2i64 (v2f64 VR128:$src1)),
966 (bc_v2i64 (v2f64 VR128:$src2))))]>;
967 def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
968 "orps {$src2, $dst|$dst, $src2}",
970 (or (bc_v4i32 (v4f32 VR128:$src1)),
971 (bc_v4i32 (v4f32 VR128:$src2))))]>;
972 def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
973 "orpd {$src2, $dst|$dst, $src2}",
975 (or (bc_v2i64 (v2f64 VR128:$src1)),
976 (bc_v2i64 (v2f64 VR128:$src2))))]>;
977 def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
978 "xorps {$src2, $dst|$dst, $src2}",
980 (xor (bc_v4i32 (v4f32 VR128:$src1)),
981 (bc_v4i32 (v4f32 VR128:$src2))))]>;
982 def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
983 "xorpd {$src2, $dst|$dst, $src2}",
985 (xor (bc_v2i64 (v2f64 VR128:$src1)),
986 (bc_v2i64 (v2f64 VR128:$src2))))]>;
988 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
989 "andps {$src2, $dst|$dst, $src2}",
991 (and (bc_v4i32 (v4f32 VR128:$src1)),
992 (bc_v4i32 (loadv4f32 addr:$src2))))]>;
993 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
994 "andpd {$src2, $dst|$dst, $src2}",
996 (and (bc_v2i64 (v2f64 VR128:$src1)),
997 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
998 def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
999 "orps {$src2, $dst|$dst, $src2}",
1001 (or (bc_v4i32 (v4f32 VR128:$src1)),
1002 (bc_v4i32 (loadv4f32 addr:$src2))))]>;
1003 def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1004 "orpd {$src2, $dst|$dst, $src2}",
1006 (or (bc_v2i64 (v2f64 VR128:$src1)),
1007 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1008 def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1009 "xorps {$src2, $dst|$dst, $src2}",
1011 (xor (bc_v4i32 (v4f32 VR128:$src1)),
1012 (bc_v4i32 (loadv4f32 addr:$src2))))]>;
1013 def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1014 "xorpd {$src2, $dst|$dst, $src2}",
1016 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1017 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1018 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1019 "andnps {$src2, $dst|$dst, $src2}",
1021 (and (vnot (bc_v4i32 (v4f32 VR128:$src1))),
1022 (bc_v4i32 (v4f32 VR128:$src2))))]>;
1023 def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1024 "andnps {$src2, $dst|$dst, $src2}",
1026 (and (vnot (bc_v4i32 (v4f32 VR128:$src1))),
1027 (bc_v4i32 (loadv4f32 addr:$src2))))]>;
1028 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1029 "andnpd {$src2, $dst|$dst, $src2}",
1031 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1032 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1033 def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1034 "andnpd {$src2, $dst|$dst, $src2}",
1036 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1037 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1040 let isTwoAddress = 1 in {
1041 def CMPPSrr : PSIi8<0xC2, MRMSrcReg,
1042 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1043 "cmp${cc}ps {$src, $dst|$dst, $src}",
1044 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1045 VR128:$src, imm:$cc))]>;
1046 def CMPPSrm : PSIi8<0xC2, MRMSrcMem,
1047 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1048 "cmp${cc}ps {$src, $dst|$dst, $src}",
1049 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1050 (load addr:$src), imm:$cc))]>;
1051 def CMPPDrr : PDIi8<0xC2, MRMSrcReg,
1052 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1053 "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
1054 def CMPPDrm : PDIi8<0xC2, MRMSrcMem,
1055 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1056 "cmp${cc}pd {$src, $dst|$dst, $src}", []>;
1059 // Shuffle and unpack instructions
1060 let isTwoAddress = 1 in {
1061 def SHUFPSrr : PSIi8<0xC6, MRMSrcReg,
1062 (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
1063 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1064 [(set VR128:$dst, (v4f32 (vector_shuffle
1065 VR128:$src1, VR128:$src2,
1066 SHUFP_shuffle_mask:$src3)))]>;
1067 def SHUFPSrm : PSIi8<0xC6, MRMSrcMem,
1068 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
1069 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1070 [(set VR128:$dst, (v4f32 (vector_shuffle
1071 VR128:$src1, (load addr:$src2),
1072 SHUFP_shuffle_mask:$src3)))]>;
1073 def SHUFPDrr : PDIi8<0xC6, MRMSrcReg,
1074 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1075 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1076 [(set VR128:$dst, (v2f64 (vector_shuffle
1077 VR128:$src1, VR128:$src2,
1078 SHUFP_shuffle_mask:$src3)))]>;
1079 def SHUFPDrm : PDIi8<0xC6, MRMSrcMem,
1080 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
1081 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1082 [(set VR128:$dst, (v2f64 (vector_shuffle
1083 VR128:$src1, (load addr:$src2),
1084 SHUFP_shuffle_mask:$src3)))]>;
1086 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1087 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1088 "unpckhps {$src2, $dst|$dst, $src2}",
1089 [(set VR128:$dst, (v4f32 (vector_shuffle
1090 VR128:$src1, VR128:$src2,
1091 UNPCKH_shuffle_mask)))]>;
1092 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1093 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1094 "unpckhps {$src2, $dst|$dst, $src2}",
1095 [(set VR128:$dst, (v4f32 (vector_shuffle
1096 VR128:$src1, (load addr:$src2),
1097 UNPCKH_shuffle_mask)))]>;
1098 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1099 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1100 "unpckhpd {$src2, $dst|$dst, $src2}",
1101 [(set VR128:$dst, (v2f64 (vector_shuffle
1102 VR128:$src1, VR128:$src2,
1103 UNPCKH_shuffle_mask)))]>;
1104 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1105 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1106 "unpckhpd {$src2, $dst|$dst, $src2}",
1107 [(set VR128:$dst, (v2f64 (vector_shuffle
1108 VR128:$src1, (load addr:$src2),
1109 UNPCKH_shuffle_mask)))]>;
1111 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1112 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1113 "unpcklps {$src2, $dst|$dst, $src2}",
1114 [(set VR128:$dst, (v4f32 (vector_shuffle
1115 VR128:$src1, VR128:$src2,
1116 UNPCKL_shuffle_mask)))]>;
1117 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1118 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1119 "unpcklps {$src2, $dst|$dst, $src2}",
1120 [(set VR128:$dst, (v4f32 (vector_shuffle
1121 VR128:$src1, (load addr:$src2),
1122 UNPCKL_shuffle_mask)))]>;
1123 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1124 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1125 "unpcklpd {$src2, $dst|$dst, $src2}",
1126 [(set VR128:$dst, (v2f64 (vector_shuffle
1127 VR128:$src1, VR128:$src2,
1128 UNPCKL_shuffle_mask)))]>;
1129 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1130 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1131 "unpcklpd {$src2, $dst|$dst, $src2}",
1132 [(set VR128:$dst, (v2f64 (vector_shuffle
1133 VR128:$src1, (load addr:$src2),
1134 UNPCKL_shuffle_mask)))]>;
1138 let isTwoAddress = 1 in {
1139 def HADDPSrr : S3S_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1140 int_x86_sse3_hadd_ps>;
1141 def HADDPSrm : S3S_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1142 int_x86_sse3_hadd_ps>;
1143 def HADDPDrr : S3D_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1144 int_x86_sse3_hadd_pd>;
1145 def HADDPDrm : S3D_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1146 int_x86_sse3_hadd_pd>;
1147 def HSUBPSrr : S3S_Intrr<0x7C, "hsubps {$src2, $dst|$dst, $src2}",
1148 int_x86_sse3_hsub_ps>;
1149 def HSUBPSrm : S3S_Intrm<0x7C, "hsubps {$src2, $dst|$dst, $src2}",
1150 int_x86_sse3_hsub_ps>;
1151 def HSUBPDrr : S3D_Intrr<0x7C, "hsubpd {$src2, $dst|$dst, $src2}",
1152 int_x86_sse3_hsub_pd>;
1153 def HSUBPDrm : S3D_Intrm<0x7C, "hsubpd {$src2, $dst|$dst, $src2}",
1154 int_x86_sse3_hsub_pd>;
1157 //===----------------------------------------------------------------------===//
1158 // SSE integer instructions
1159 //===----------------------------------------------------------------------===//
1161 // Move Instructions
1162 def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1163 "movdqa {$src, $dst|$dst, $src}", []>;
1164 def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1165 "movdqa {$src, $dst|$dst, $src}",
1166 [(set VR128:$dst, (loadv4i32 addr:$src))]>;
1167 def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1168 "movdqa {$src, $dst|$dst, $src}",
1169 [(store (v4i32 VR128:$src), addr:$dst)]>;
1171 // 128-bit Integer Arithmetic
1172 let isTwoAddress = 1 in {
1173 let isCommutable = 1 in {
1174 def PADDBrr : PDI<0xFC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1175 "paddb {$src2, $dst|$dst, $src2}",
1176 [(set VR128:$dst, (v16i8 (add VR128:$src1, VR128:$src2)))]>;
1177 def PADDWrr : PDI<0xFD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1178 "paddw {$src2, $dst|$dst, $src2}",
1179 [(set VR128:$dst, (v8i16 (add VR128:$src1, VR128:$src2)))]>;
1180 def PADDDrr : PDI<0xFE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1181 "paddd {$src2, $dst|$dst, $src2}",
1182 [(set VR128:$dst, (v4i32 (add VR128:$src1, VR128:$src2)))]>;
1184 def PADDQrr : PDI<0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1185 "paddq {$src2, $dst|$dst, $src2}",
1186 [(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>;
1188 def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1189 "paddb {$src2, $dst|$dst, $src2}",
1190 [(set VR128:$dst, (v16i8 (add VR128:$src1,
1191 (load addr:$src2))))]>;
1192 def PADDWrm : PDI<0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1193 "paddw {$src2, $dst|$dst, $src2}",
1194 [(set VR128:$dst, (v8i16 (add VR128:$src1,
1195 (load addr:$src2))))]>;
1196 def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1197 "paddd {$src2, $dst|$dst, $src2}",
1198 [(set VR128:$dst, (v4i32 (add VR128:$src1,
1199 (load addr:$src2))))]>;
1200 def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1201 "paddd {$src2, $dst|$dst, $src2}",
1202 [(set VR128:$dst, (v2i64 (add VR128:$src1,
1203 (load addr:$src2))))]>;
1205 def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1206 "psubb {$src2, $dst|$dst, $src2}",
1207 [(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))]>;
1208 def PSUBWrr : PDI<0xF9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1209 "psubw {$src2, $dst|$dst, $src2}",
1210 [(set VR128:$dst, (v8i16 (sub VR128:$src1, VR128:$src2)))]>;
1211 def PSUBDrr : PDI<0xFA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1212 "psubd {$src2, $dst|$dst, $src2}",
1213 [(set VR128:$dst, (v4i32 (sub VR128:$src1, VR128:$src2)))]>;
1214 def PSUBQrr : PDI<0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1215 "psubq {$src2, $dst|$dst, $src2}",
1216 [(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>;
1218 def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1219 "psubb {$src2, $dst|$dst, $src2}",
1220 [(set VR128:$dst, (v16i8 (sub VR128:$src1,
1221 (load addr:$src2))))]>;
1222 def PSUBWrm : PDI<0xF9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1223 "psubw {$src2, $dst|$dst, $src2}",
1224 [(set VR128:$dst, (v8i16 (sub VR128:$src1,
1225 (load addr:$src2))))]>;
1226 def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1227 "psubd {$src2, $dst|$dst, $src2}",
1228 [(set VR128:$dst, (v4i32 (sub VR128:$src1,
1229 (load addr:$src2))))]>;
1230 def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1231 "psubd {$src2, $dst|$dst, $src2}",
1232 [(set VR128:$dst, (v2i64 (sub VR128:$src1,
1233 (load addr:$src2))))]>;
1236 let isTwoAddress = 1 in {
1237 def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1238 "pslldq {$src2, $dst|$dst, $src2}", []>;
1239 def PSRLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1240 "psrldq {$src2, $dst|$dst, $src2}", []>;
1244 let isTwoAddress = 1 in {
1245 let isCommutable = 1 in {
1246 def PANDrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1247 "pand {$src2, $dst|$dst, $src2}",
1248 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1250 def PANDrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1251 "pand {$src2, $dst|$dst, $src2}",
1252 [(set VR128:$dst, (v2i64 (and VR128:$src1,
1253 (load addr:$src2))))]>;
1254 def PORrr : PDI<0xEB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1255 "por {$src2, $dst|$dst, $src2}",
1256 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1258 def PORrm : PDI<0xEB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1259 "por {$src2, $dst|$dst, $src2}",
1260 [(set VR128:$dst, (v2i64 (or VR128:$src1,
1261 (load addr:$src2))))]>;
1262 def PXORrr : PDI<0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1263 "pxor {$src2, $dst|$dst, $src2}",
1264 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1266 def PXORrm : PDI<0xEF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1267 "pxor {$src2, $dst|$dst, $src2}",
1268 [(set VR128:$dst, (v2i64 (xor VR128:$src1,
1269 (load addr:$src2))))]>;
1272 def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1273 "pandn {$src2, $dst|$dst, $src2}",
1274 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1277 def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1278 "pandn {$src2, $dst|$dst, $src2}",
1279 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1280 (load addr:$src2))))]>;
1283 // Pack instructions
1284 let isTwoAddress = 1 in {
1285 def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1287 "packsswb {$src2, $dst|$dst, $src2}",
1288 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1291 def PACKSSWBrm : PDI<0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1293 "packsswb {$src2, $dst|$dst, $src2}",
1294 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1296 (bc_v8i16 (loadv2f64 addr:$src2)))))]>;
1297 def PACKSSDWrr : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1299 "packssdw {$src2, $dst|$dst, $src2}",
1300 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1303 def PACKSSDWrm : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1305 "packssdw {$src2, $dst|$dst, $src2}",
1306 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1308 (bc_v4i32 (loadv2i64 addr:$src2)))))]>;
1309 def PACKUSWBrr : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1311 "packuswb {$src2, $dst|$dst, $src2}",
1312 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1315 def PACKUSWBrm : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1317 "packuswb {$src2, $dst|$dst, $src2}",
1318 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1320 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1323 // Shuffle and unpack instructions
1324 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1325 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1326 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1327 [(set VR128:$dst, (v4i32 (vector_shuffle
1328 VR128:$src1, (undef),
1329 PSHUFD_shuffle_mask:$src2)))]>;
1330 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1331 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1332 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1333 [(set VR128:$dst, (v4i32 (vector_shuffle
1334 (load addr:$src1), (undef),
1335 PSHUFD_shuffle_mask:$src2)))]>;
1337 // SSE2 with ImmT == Imm8 and XS prefix.
1338 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1339 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1340 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1341 [(set VR128:$dst, (v8i16 (vector_shuffle
1342 VR128:$src1, (undef),
1343 PSHUFHW_shuffle_mask:$src2)))]>,
1344 XS, Requires<[HasSSE2]>;
1345 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1346 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1347 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1348 [(set VR128:$dst, (v8i16 (vector_shuffle
1349 (load addr:$src1), (undef),
1350 PSHUFHW_shuffle_mask:$src2)))]>,
1351 XS, Requires<[HasSSE2]>;
1353 // SSE2 with ImmT == Imm8 and XD prefix.
1354 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1355 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1356 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1357 [(set VR128:$dst, (v8i16 (vector_shuffle
1358 VR128:$src1, (undef),
1359 PSHUFLW_shuffle_mask:$src2)))]>,
1360 XD, Requires<[HasSSE2]>;
1361 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1362 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1363 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1364 [(set VR128:$dst, (v8i16 (vector_shuffle
1365 (load addr:$src1), (undef),
1366 PSHUFLW_shuffle_mask:$src2)))]>,
1367 XD, Requires<[HasSSE2]>;
1369 let isTwoAddress = 1 in {
1370 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1371 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1372 "punpcklbw {$src2, $dst|$dst, $src2}",
1374 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1375 UNPCKL_shuffle_mask)))]>;
1376 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1377 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1378 "punpcklbw {$src2, $dst|$dst, $src2}",
1380 (v16i8 (vector_shuffle VR128:$src1, (load addr:$src2),
1381 UNPCKL_shuffle_mask)))]>;
1382 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1383 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1384 "punpcklwd {$src2, $dst|$dst, $src2}",
1386 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1387 UNPCKL_shuffle_mask)))]>;
1388 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1389 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1390 "punpcklwd {$src2, $dst|$dst, $src2}",
1392 (v8i16 (vector_shuffle VR128:$src1, (load addr:$src2),
1393 UNPCKL_shuffle_mask)))]>;
1394 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1395 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1396 "punpckldq {$src2, $dst|$dst, $src2}",
1398 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1399 UNPCKL_shuffle_mask)))]>;
1400 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1401 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1402 "punpckldq {$src2, $dst|$dst, $src2}",
1404 (v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
1405 UNPCKL_shuffle_mask)))]>;
1406 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1407 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1408 "punpcklqdq {$src2, $dst|$dst, $src2}",
1410 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1411 UNPCKL_shuffle_mask)))]>;
1412 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1413 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1414 "punpcklqdq {$src2, $dst|$dst, $src2}",
1416 (v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
1417 UNPCKL_shuffle_mask)))]>;
1419 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1420 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1421 "punpckhbw {$src2, $dst|$dst, $src2}",
1423 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1424 UNPCKH_shuffle_mask)))]>;
1425 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1426 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1427 "punpckhbw {$src2, $dst|$dst, $src2}",
1429 (v16i8 (vector_shuffle VR128:$src1, (load addr:$src2),
1430 UNPCKH_shuffle_mask)))]>;
1431 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1432 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1433 "punpckhwd {$src2, $dst|$dst, $src2}",
1435 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1436 UNPCKH_shuffle_mask)))]>;
1437 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1438 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1439 "punpckhwd {$src2, $dst|$dst, $src2}",
1441 (v8i16 (vector_shuffle VR128:$src1, (load addr:$src2),
1442 UNPCKH_shuffle_mask)))]>;
1443 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1444 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1445 "punpckhdq {$src2, $dst|$dst, $src2}",
1447 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1448 UNPCKH_shuffle_mask)))]>;
1449 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1450 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1451 "punpckhdq {$src2, $dst|$dst, $src2}",
1453 (v4i32 (vector_shuffle VR128:$src1, (load addr:$src2),
1454 UNPCKH_shuffle_mask)))]>;
1455 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1456 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1457 "punpckhdq {$src2, $dst|$dst, $src2}",
1459 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1460 UNPCKH_shuffle_mask)))]>;
1461 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1462 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1463 "punpckhqdq {$src2, $dst|$dst, $src2}",
1465 (v2i64 (vector_shuffle VR128:$src1, (load addr:$src2),
1466 UNPCKH_shuffle_mask)))]>;
1470 def PEXTRWr : PDIi8<0xC5, MRMSrcReg,
1471 (ops R32:$dst, VR128:$src1, i32i8imm:$src2),
1472 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
1473 [(set R32:$dst, (X86pextrw (v8i16 VR128:$src1),
1474 (i32 imm:$src2)))]>;
1475 def PEXTRWm : PDIi8<0xC5, MRMSrcMem,
1476 (ops R32:$dst, i128mem:$src1, i32i8imm:$src2),
1477 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
1478 [(set R32:$dst, (X86pextrw (loadv8i16 addr:$src1),
1479 (i32 imm:$src2)))]>;
1481 let isTwoAddress = 1 in {
1482 def PINSRWr : PDIi8<0xC4, MRMSrcReg,
1483 (ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3),
1484 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1485 [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1486 R32:$src2, (i32 imm:$src3))))]>;
1487 def PINSRWm : PDIi8<0xC4, MRMSrcMem,
1488 (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
1489 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1491 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1492 (i32 (anyext (loadi16 addr:$src2))),
1493 (i32 imm:$src3))))]>;
1496 //===----------------------------------------------------------------------===//
1497 // Miscellaneous Instructions
1498 //===----------------------------------------------------------------------===//
1501 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
1502 "movmskps {$src, $dst|$dst, $src}",
1503 [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1504 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
1505 "movmskpd {$src, $dst|$dst, $src}",
1506 [(set R32:$dst, (int_x86_sse2_movmskpd VR128:$src))]>;
1508 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops R32:$dst, VR128:$src),
1509 "pmovmskb {$src, $dst|$dst, $src}",
1510 [(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
1512 // Conditional store
1513 def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask),
1514 "maskmovdqu {$mask, $src|$src, $mask}",
1515 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
1518 // Prefetching loads
1519 def PREFETCHT0 : I<0x18, MRM1m, (ops i8mem:$src),
1520 "prefetcht0 $src", []>, TB,
1521 Requires<[HasSSE1]>;
1522 def PREFETCHT1 : I<0x18, MRM2m, (ops i8mem:$src),
1523 "prefetcht0 $src", []>, TB,
1524 Requires<[HasSSE1]>;
1525 def PREFETCHT2 : I<0x18, MRM3m, (ops i8mem:$src),
1526 "prefetcht0 $src", []>, TB,
1527 Requires<[HasSSE1]>;
1528 def PREFETCHTNTA : I<0x18, MRM0m, (ops i8mem:$src),
1529 "prefetcht0 $src", []>, TB,
1530 Requires<[HasSSE1]>;
1532 // Non-temporal stores
1533 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1534 "movntps {$src, $dst|$dst, $src}",
1535 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1536 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1537 "movntpd {$src, $dst|$dst, $src}",
1538 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
1539 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1540 "movntdq {$src, $dst|$dst, $src}",
1541 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
1542 def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src),
1543 "movnti {$src, $dst|$dst, $src}",
1544 [(int_x86_sse2_movnt_i addr:$dst, R32:$src)]>,
1545 TB, Requires<[HasSSE2]>;
1548 def SFENCE : I<0xAE, MRM7m, (ops),
1549 "sfence", []>, TB, Requires<[HasSSE1]>;
1552 def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src),
1554 [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
1555 def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
1557 [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
1559 //===----------------------------------------------------------------------===//
1560 // Alias Instructions
1561 //===----------------------------------------------------------------------===//
1563 // Alias instructions that map zero vector to pxor / xorp* for sse.
1564 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1565 def V_SET0_PI : PDI<0xEF, MRMInitReg, (ops VR128:$dst),
1567 [(set VR128:$dst, (v2i64 immAllZerosV))]>;
1568 def V_SET0_PS : PSI<0x57, MRMInitReg, (ops VR128:$dst),
1570 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1571 def V_SET0_PD : PDI<0x57, MRMInitReg, (ops VR128:$dst),
1573 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
1575 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
1576 "pcmpeqd $dst, $dst",
1577 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
1579 // FR32 / FR64 to 128-bit vector conversion.
1580 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
1581 "movss {$src, $dst|$dst, $src}",
1583 (v4f32 (scalar_to_vector FR32:$src)))]>;
1584 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
1585 "movss {$src, $dst|$dst, $src}",
1587 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1588 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
1589 "movsd {$src, $dst|$dst, $src}",
1591 (v2f64 (scalar_to_vector FR64:$src)))]>;
1592 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1593 "movsd {$src, $dst|$dst, $src}",
1595 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
1597 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src),
1598 "movd {$src, $dst|$dst, $src}",
1600 (v4i32 (scalar_to_vector R32:$src)))]>;
1601 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1602 "movd {$src, $dst|$dst, $src}",
1604 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
1605 // SSE2 instructions with XS prefix
1606 def MOVQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
1607 "movq {$src, $dst|$dst, $src}",
1609 (v2i64 (scalar_to_vector VR64:$src)))]>, XS,
1610 Requires<[HasSSE2]>;
1611 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1612 "movq {$src, $dst|$dst, $src}",
1614 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
1615 Requires<[HasSSE2]>;
1616 // FIXME: may not be able to eliminate this movss with coalescing the src and
1617 // dest register classes are different. We really want to write this pattern
1619 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (i32 0))),
1620 // (f32 FR32:$src)>;
1621 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
1622 "movss {$src, $dst|$dst, $src}",
1623 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1625 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
1626 "movss {$src, $dst|$dst, $src}",
1627 [(store (f32 (vector_extract (v4f32 VR128:$src),
1628 (i32 0))), addr:$dst)]>;
1629 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
1630 "movsd {$src, $dst|$dst, $src}",
1631 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
1633 def MOVPDI2DIrr : PDI<0x6E, MRMSrcReg, (ops R32:$dst, VR128:$src),
1634 "movd {$src, $dst|$dst, $src}",
1635 [(set R32:$dst, (vector_extract (v4i32 VR128:$src),
1637 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
1638 "movd {$src, $dst|$dst, $src}",
1639 [(store (i32 (vector_extract (v4i32 VR128:$src),
1640 (i32 0))), addr:$dst)]>;
1642 // Move to lower bits of a VR128, leaving upper bits alone.
1643 // Three operand (but two address) aliases.
1644 let isTwoAddress = 1 in {
1645 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2),
1646 "movss {$src2, $dst|$dst, $src2}", []>;
1647 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2),
1648 "movsd {$src2, $dst|$dst, $src2}", []>;
1649 def MOVLDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, R32:$src2),
1650 "movd {$src2, $dst|$dst, $src2}", []>;
1652 def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1653 "movss {$src2, $dst|$dst, $src2}",
1655 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1656 MOVS_shuffle_mask)))]>;
1657 def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1658 "movsd {$src2, $dst|$dst, $src2}",
1660 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
1661 MOVS_shuffle_mask)))]>;
1664 // Move to lower bits of a VR128 and zeroing upper bits.
1665 // Loading from memory automatically zeroing upper bits.
1666 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
1667 "movss {$src, $dst|$dst, $src}",
1669 (v4f32 (X86zexts2vec (loadf32 addr:$src))))]>;
1670 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1671 "movsd {$src, $dst|$dst, $src}",
1673 (v2f64 (X86zexts2vec (loadf64 addr:$src))))]>;
1674 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1675 "movd {$src, $dst|$dst, $src}",
1677 (v4i32 (X86zexts2vec (loadi32 addr:$src))))]>;
1678 def MOVZQI2PQIrm : PDI<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1679 "movd {$src, $dst|$dst, $src}",
1681 (v2i64 (X86zexts2vec (loadi64 addr:$src))))]>;
1683 //===----------------------------------------------------------------------===//
1684 // Non-Instruction Patterns
1685 //===----------------------------------------------------------------------===//
1687 // 128-bit vector undef's.
1688 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1689 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1690 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1691 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1692 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1694 // 128-bit vector all zero's.
1695 def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0_PI))>, Requires<[HasSSE2]>;
1696 def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0_PI))>, Requires<[HasSSE2]>;
1697 def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0_PI))>, Requires<[HasSSE2]>;
1699 // 128-bit vector all one's.
1700 def : Pat<(v16i8 immAllOnesV), (v16i8 (V_SETALLONES))>, Requires<[HasSSE2]>;
1701 def : Pat<(v8i16 immAllOnesV), (v8i16 (V_SETALLONES))>, Requires<[HasSSE2]>;
1702 def : Pat<(v4i32 immAllOnesV), (v4i32 (V_SETALLONES))>, Requires<[HasSSE2]>;
1703 def : Pat<(v2i64 immAllOnesV), (v2i64 (V_SETALLONES))>, Requires<[HasSSE2]>;
1704 def : Pat<(v4f32 immAllOnesV), (v4f32 (V_SETALLONES))>, Requires<[HasSSE1]>;
1706 // Load 128-bit integer vector values.
1707 def : Pat<(v16i8 (load addr:$src)), (MOVDQArm addr:$src)>,
1708 Requires<[HasSSE2]>;
1709 def : Pat<(v8i16 (load addr:$src)), (MOVDQArm addr:$src)>,
1710 Requires<[HasSSE2]>;
1711 def : Pat<(v4i32 (load addr:$src)), (MOVDQArm addr:$src)>,
1712 Requires<[HasSSE2]>;
1713 def : Pat<(v2i64 (load addr:$src)), (MOVDQArm addr:$src)>,
1714 Requires<[HasSSE2]>;
1716 // Store 128-bit integer vector values.
1717 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1718 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1719 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1720 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1721 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1722 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1723 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1724 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1726 // Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or
1728 def : Pat<(v8i16 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>,
1729 Requires<[HasSSE2]>;
1730 def : Pat<(v16i8 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>,
1731 Requires<[HasSSE2]>;
1734 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>,
1735 Requires<[HasSSE2]>;
1736 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>,
1737 Requires<[HasSSE2]>;
1738 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>,
1739 Requires<[HasSSE2]>;
1740 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>,
1741 Requires<[HasSSE2]>;
1742 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>,
1743 Requires<[HasSSE2]>;
1744 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
1745 Requires<[HasSSE2]>;
1746 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
1747 Requires<[HasSSE2]>;
1748 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
1749 Requires<[HasSSE2]>;
1750 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>,
1751 Requires<[HasSSE2]>;
1752 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>,
1753 Requires<[HasSSE2]>;
1754 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
1755 Requires<[HasSSE2]>;
1756 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
1757 Requires<[HasSSE2]>;
1758 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
1759 Requires<[HasSSE2]>;
1760 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>,
1761 Requires<[HasSSE2]>;
1762 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>,
1763 Requires<[HasSSE2]>;
1764 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
1765 Requires<[HasSSE2]>;
1766 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
1767 Requires<[HasSSE2]>;
1768 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
1769 Requires<[HasSSE2]>;
1770 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>,
1771 Requires<[HasSSE2]>;
1772 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>,
1773 Requires<[HasSSE2]>;
1774 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>,
1775 Requires<[HasSSE2]>;
1776 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>,
1777 Requires<[HasSSE2]>;
1778 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>,
1779 Requires<[HasSSE2]>;
1780 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>,
1781 Requires<[HasSSE2]>;
1782 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>,
1783 Requires<[HasSSE2]>;
1784 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>,
1785 Requires<[HasSSE2]>;
1786 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>,
1787 Requires<[HasSSE2]>;
1788 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>,
1789 Requires<[HasSSE2]>;
1790 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>,
1791 Requires<[HasSSE2]>;
1792 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>,
1793 Requires<[HasSSE2]>;
1795 // Zeroing a VR128 then do a MOVS* to the lower bits.
1796 def : Pat<(v2f64 (X86zexts2vec FR64:$src)),
1797 (MOVLSD2PDrr (V_SET0_PD), FR64:$src)>, Requires<[HasSSE2]>;
1798 def : Pat<(v4f32 (X86zexts2vec FR32:$src)),
1799 (MOVLSS2PSrr (V_SET0_PS), FR32:$src)>, Requires<[HasSSE2]>;
1800 def : Pat<(v4i32 (X86zexts2vec R32:$src)),
1801 (MOVLDI2PDIrr (V_SET0_PI), R32:$src)>, Requires<[HasSSE2]>;
1802 def : Pat<(v8i16 (X86zexts2vec R16:$src)),
1803 (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr16 R16:$src))>, Requires<[HasSSE2]>;
1804 def : Pat<(v16i8 (X86zexts2vec R8:$src)),
1805 (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
1807 // Splat v2f64 / v2i64
1808 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_mask:$sm),
1809 (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
1810 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_mask:$sm),
1811 (v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
1814 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
1815 (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SSE_splat_mask:$sm))>,
1816 Requires<[HasSSE1]>;
1818 // Special pshuf* cases: folding (bit_convert (loadv2i64 addr)).
1819 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src1)), (undef),
1820 PSHUFD_shuffle_mask:$src2)),
1821 (PSHUFDmi addr:$src1, PSHUFD_shuffle_mask:$src2)>,
1822 Requires<[HasSSE2]>;
1823 def : Pat<(v8i16 (vector_shuffle (bc_v8i16 (loadv2i64 addr:$src1)), (undef),
1824 PSHUFHW_shuffle_mask:$src2)),
1825 (PSHUFHWmi addr:$src1, PSHUFHW_shuffle_mask:$src2)>,
1826 Requires<[HasSSE2]>;
1827 def : Pat<(v8i16 (vector_shuffle (bc_v8i16 (loadv2i64 addr:$src1)), (undef),
1828 PSHUFLW_shuffle_mask:$src2)),
1829 (PSHUFLWmi addr:$src1, PSHUFHW_shuffle_mask:$src2)>,
1830 Requires<[HasSSE2]>;
1833 // Special unary SHUFPSrr case.
1834 // FIXME: when we want non two-address code, then we should use PSHUFD?
1835 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
1836 SHUFP_unary_shuffle_mask:$sm),
1837 (v4f32 (SHUFPSrr VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm))>,
1838 Requires<[HasSSE1]>;
1839 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
1840 def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
1841 SHUFP_unary_shuffle_mask:$sm),
1842 (v4f32 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm))>,
1843 Requires<[HasSSE2]>;
1844 // Special binary v4i32 shuffle cases with SHUFPS.
1845 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
1846 PSHUFD_binary_shuffle_mask:$sm),
1847 (v4i32 (SHUFPSrr VR128:$src1, VR128:$src2,
1848 PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
1849 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (load addr:$src2),
1850 PSHUFD_binary_shuffle_mask:$sm),
1851 (v4i32 (SHUFPSrm VR128:$src1, addr:$src2,
1852 PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
1854 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
1855 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
1856 UNPCKL_v_undef_shuffle_mask)),
1857 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1858 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
1859 UNPCKL_v_undef_shuffle_mask)),
1860 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1861 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
1862 UNPCKL_v_undef_shuffle_mask)),
1863 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1864 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
1865 UNPCKL_v_undef_shuffle_mask)),
1866 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
1868 // 128-bit logical shifts
1869 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1870 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1871 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1872 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1875 def : Pat<(and (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)),
1876 (ANDPSrm VR128:$src1, addr:$src2)>;
1877 def : Pat<(and (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)),
1878 (ANDPDrm VR128:$src1, addr:$src2)>;
1879 def : Pat<(or (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)),
1880 (ORPSrm VR128:$src1, addr:$src2)>;
1881 def : Pat<(or (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)),
1882 (ORPDrm VR128:$src1, addr:$src2)>;
1883 def : Pat<(xor (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)),
1884 (XORPSrm VR128:$src1, addr:$src2)>;
1885 def : Pat<(xor (bc_v2i64 (v2f64 VR128:$src1)), (loadv2i64 addr:$src2)),
1886 (XORPDrm VR128:$src1, addr:$src2)>;
1887 def : Pat<(and (vnot (bc_v4i32 (v4f32 VR128:$src1))), (loadv4i32 addr:$src2)),
1888 (ANDNPSrm VR128:$src1, addr:$src2)>;
1889 def : Pat<(and (vnot (bc_v2i64 (v2f64 VR128:$src1))), (loadv2i64 addr:$src2)),
1890 (ANDNPDrm VR128:$src1, addr:$src2)>;
1892 def : Pat<(bc_v4f32 (v4i32 (and VR128:$src1, VR128:$src2))),
1893 (ANDPSrr VR128:$src1, VR128:$src2)>;
1894 def : Pat<(bc_v4f32 (v4i32 (or VR128:$src1, VR128:$src2))),
1895 (ORPSrr VR128:$src1, VR128:$src2)>;
1896 def : Pat<(bc_v4f32 (v4i32 (xor VR128:$src1, VR128:$src2))),
1897 (XORPSrr VR128:$src1, VR128:$src2)>;
1898 def : Pat<(bc_v4f32 (v4i32 (and (vnot VR128:$src1), VR128:$src2))),
1899 (ANDNPSrr VR128:$src1, VR128:$src2)>;
1901 def : Pat<(bc_v4f32 (v4i32 (and VR128:$src1, (load addr:$src2)))),
1902 (ANDPSrm (v4i32 VR128:$src1), addr:$src2)>;
1903 def : Pat<(bc_v4f32 (v4i32 (or VR128:$src1, (load addr:$src2)))),
1904 (ORPSrm VR128:$src1, addr:$src2)>;
1905 def : Pat<(bc_v4f32 (v4i32 (xor VR128:$src1, (load addr:$src2)))),
1906 (XORPSrm VR128:$src1, addr:$src2)>;
1907 def : Pat<(bc_v4f32 (v4i32 (and (vnot VR128:$src1), (load addr:$src2)))),
1908 (ANDNPSrm VR128:$src1, addr:$src2)>;
1910 def : Pat<(bc_v2f64 (v2i64 (and VR128:$src1, VR128:$src2))),
1911 (ANDPDrr VR128:$src1, VR128:$src2)>;
1912 def : Pat<(bc_v2f64 (v2i64 (or VR128:$src1, VR128:$src2))),
1913 (ORPDrr VR128:$src1, VR128:$src2)>;
1914 def : Pat<(bc_v2f64 (v2i64 (xor VR128:$src1, VR128:$src2))),
1915 (XORPDrr VR128:$src1, VR128:$src2)>;
1916 def : Pat<(bc_v2f64 (v2i64 (and (vnot VR128:$src1), VR128:$src2))),
1917 (ANDNPDrr VR128:$src1, VR128:$src2)>;
1919 def : Pat<(bc_v2f64 (v2i64 (and VR128:$src1, (load addr:$src2)))),
1920 (ANDPSrm (v2i64 VR128:$src1), addr:$src2)>;
1921 def : Pat<(bc_v2f64 (v2i64 (or VR128:$src1, (load addr:$src2)))),
1922 (ORPSrm VR128:$src1, addr:$src2)>;
1923 def : Pat<(bc_v2f64 (v2i64 (xor VR128:$src1, (load addr:$src2)))),
1924 (XORPSrm VR128:$src1, addr:$src2)>;
1925 def : Pat<(bc_v2f64 (v2i64 (and (vnot VR128:$src1), (load addr:$src2)))),
1926 (ANDNPSrm VR128:$src1, addr:$src2)>;
1928 def : Pat<(v4i32 (and VR128:$src1, VR128:$src2)),
1929 (PANDrr VR128:$src1, VR128:$src2)>;
1930 def : Pat<(v8i16 (and VR128:$src1, VR128:$src2)),
1931 (PANDrr VR128:$src1, VR128:$src2)>;
1932 def : Pat<(v16i8 (and VR128:$src1, VR128:$src2)),
1933 (PANDrr VR128:$src1, VR128:$src2)>;
1934 def : Pat<(v4i32 (or VR128:$src1, VR128:$src2)),
1935 (PORrr VR128:$src1, VR128:$src2)>;
1936 def : Pat<(v8i16 (or VR128:$src1, VR128:$src2)),
1937 (PORrr VR128:$src1, VR128:$src2)>;
1938 def : Pat<(v16i8 (or VR128:$src1, VR128:$src2)),
1939 (PORrr VR128:$src1, VR128:$src2)>;
1940 def : Pat<(v4i32 (xor VR128:$src1, VR128:$src2)),
1941 (PXORrr VR128:$src1, VR128:$src2)>;
1942 def : Pat<(v8i16 (xor VR128:$src1, VR128:$src2)),
1943 (PXORrr VR128:$src1, VR128:$src2)>;
1944 def : Pat<(v16i8 (xor VR128:$src1, VR128:$src2)),
1945 (PXORrr VR128:$src1, VR128:$src2)>;
1946 def : Pat<(v4i32 (and (vnot VR128:$src1), VR128:$src2)),
1947 (PANDNrr VR128:$src1, VR128:$src2)>;
1948 def : Pat<(v8i16 (and (vnot VR128:$src1), VR128:$src2)),
1949 (PANDNrr VR128:$src1, VR128:$src2)>;
1950 def : Pat<(v16i8 (and (vnot VR128:$src1), VR128:$src2)),
1951 (PANDNrr VR128:$src1, VR128:$src2)>;
1953 def : Pat<(v4i32 (and VR128:$src1, (load addr:$src2))),
1954 (PANDrm VR128:$src1, addr:$src2)>;
1955 def : Pat<(v8i16 (and VR128:$src1, (load addr:$src2))),
1956 (PANDrm VR128:$src1, addr:$src2)>;
1957 def : Pat<(v16i8 (and VR128:$src1, (load addr:$src2))),
1958 (PANDrm VR128:$src1, addr:$src2)>;
1959 def : Pat<(v4i32 (or VR128:$src1, (load addr:$src2))),
1960 (PORrm VR128:$src1, addr:$src2)>;
1961 def : Pat<(v8i16 (or VR128:$src1, (load addr:$src2))),
1962 (PORrm VR128:$src1, addr:$src2)>;
1963 def : Pat<(v16i8 (or VR128:$src1, (load addr:$src2))),
1964 (PORrm VR128:$src1, addr:$src2)>;
1965 def : Pat<(v4i32 (xor VR128:$src1, (load addr:$src2))),
1966 (PXORrm VR128:$src1, addr:$src2)>;
1967 def : Pat<(v8i16 (xor VR128:$src1, (load addr:$src2))),
1968 (PXORrm VR128:$src1, addr:$src2)>;
1969 def : Pat<(v16i8 (xor VR128:$src1, (load addr:$src2))),
1970 (PXORrm VR128:$src1, addr:$src2)>;
1971 def : Pat<(v4i32 (and (vnot VR128:$src1), (load addr:$src2))),
1972 (PANDNrm VR128:$src1, addr:$src2)>;
1973 def : Pat<(v8i16 (and (vnot VR128:$src1), (load addr:$src2))),
1974 (PANDNrm VR128:$src1, addr:$src2)>;
1975 def : Pat<(v16i8 (and (vnot VR128:$src1), (load addr:$src2))),
1976 (PANDNrm VR128:$src1, addr:$src2)>;