1 //====- X86InstrMMX.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Instruction templates
17 // MMXI - MMX instructions with TB prefix.
18 // MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
19 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
20 class MMXI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
21 : I<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
22 class MMX2I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
23 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
24 class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
25 : X86Inst<o, F, Imm8, ops, asm>, TB, Requires<[HasMMX]> {
26 let Pattern = pattern;
29 // Some 'special' instructions
30 def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
32 [(set VR64:$dst, (v8i8 (undef)))]>,
35 def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
36 def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>;
39 def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src),
40 "movd {$src, $dst|$dst, $src}", []>, TB,
42 def MOVD64rm : I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
43 "movd {$src, $dst|$dst, $src}", []>, TB,
45 def MOVD64mr : I<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
46 "movd {$src, $dst|$dst, $src}", []>, TB,
49 def MOVQ64rr : I<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
50 "movq {$src, $dst|$dst, $src}", []>, TB,
52 def MOVQ64rm : I<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
53 "movq {$src, $dst|$dst, $src}", []>, TB,
55 def MOVQ64mr : I<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
56 "movq {$src, $dst|$dst, $src}", []>, TB,
59 // Conversion instructions
60 def CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
61 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
62 def CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
63 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
64 def CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
65 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
66 def CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
67 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
68 def CVTTPS2PIrr: I<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
69 "cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
71 def CVTTPS2PIrm: I<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
72 "cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
74 def CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
75 "cvtps2pi {$src, $dst|$dst, $src}", []>;
76 def CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
77 "cvtps2pi {$src, $dst|$dst, $src}", []>;
78 def CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
79 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
80 def CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
81 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
83 // Shuffle and unpack instructions
84 def PSHUFWri : MMXIi8<0x70, MRMSrcReg,
85 (ops VR64:$dst, VR64:$src1, i8imm:$src2),
86 "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
87 def PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
88 (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
89 "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
92 def MOVNTQ : I<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
93 "movntq {$src, $dst|$dst, $src}", []>, TB,
96 def MASKMOVQ : I<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
97 "maskmovq {$mask, $src|$src, $mask}", []>, TB,