1 //===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 // All instructions that use MMX should be in this file, even if they also use
17 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
23 let Sched = WriteVecALU in {
24 def MMX_INTALU_ITINS : OpndItins<
25 IIC_MMX_ALU_RR, IIC_MMX_ALU_RM
28 def MMX_INTALUQ_ITINS : OpndItins<
29 IIC_MMX_ALUQ_RR, IIC_MMX_ALUQ_RM
32 def MMX_PHADDSUBW : OpndItins<
33 IIC_MMX_PHADDSUBW_RR, IIC_MMX_PHADDSUBW_RM
36 def MMX_PHADDSUBD : OpndItins<
37 IIC_MMX_PHADDSUBD_RR, IIC_MMX_PHADDSUBD_RM
41 let Sched = WriteVecLogic in
42 def MMX_INTALU_ITINS_VECLOGICSCHED : OpndItins<
43 IIC_MMX_ALU_RR, IIC_MMX_ALU_RM
46 let Sched = WriteVecIMul in
47 def MMX_PMUL_ITINS : OpndItins<
48 IIC_MMX_PMUL, IIC_MMX_PMUL
51 let Sched = WriteVecIMul in {
52 def MMX_PSADBW_ITINS : OpndItins<
53 IIC_MMX_PSADBW, IIC_MMX_PSADBW
56 def MMX_MISC_FUNC_ITINS : OpndItins<
57 IIC_MMX_MISC_FUNC_MEM, IIC_MMX_MISC_FUNC_REG
61 def MMX_SHIFT_ITINS : ShiftOpndItins<
62 IIC_MMX_SHIFT_RR, IIC_MMX_SHIFT_RM, IIC_MMX_SHIFT_RI
65 let Sched = WriteShuffle in {
66 def MMX_UNPCK_H_ITINS : OpndItins<
67 IIC_MMX_UNPCK_H_RR, IIC_MMX_UNPCK_H_RM
70 def MMX_UNPCK_L_ITINS : OpndItins<
71 IIC_MMX_UNPCK_L, IIC_MMX_UNPCK_L
74 def MMX_PCK_ITINS : OpndItins<
75 IIC_MMX_PCK_RR, IIC_MMX_PCK_RM
78 def MMX_PSHUF_ITINS : OpndItins<
79 IIC_MMX_PSHUF, IIC_MMX_PSHUF
83 let Sched = WriteCvtF2I in {
84 def MMX_CVT_PD_ITINS : OpndItins<
85 IIC_MMX_CVT_PD_RR, IIC_MMX_CVT_PD_RM
88 def MMX_CVT_PS_ITINS : OpndItins<
89 IIC_MMX_CVT_PS_RR, IIC_MMX_CVT_PS_RM
93 let Constraints = "$src1 = $dst" in {
94 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
95 // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp.
96 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
97 OpndItins itins, bit Commutable = 0> {
98 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
99 (ins VR64:$src1, VR64:$src2),
100 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
101 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>,
102 Sched<[itins.Sched]> {
103 let isCommutable = Commutable;
105 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
106 (ins VR64:$src1, i64mem:$src2),
107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
108 [(set VR64:$dst, (IntId VR64:$src1,
109 (bitconvert (load_mmx addr:$src2))))],
110 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
113 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
114 string OpcodeStr, Intrinsic IntId,
115 Intrinsic IntId2, ShiftOpndItins itins> {
116 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
117 (ins VR64:$src1, VR64:$src2),
118 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
119 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>,
120 Sched<[WriteVecShift]>;
121 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
122 (ins VR64:$src1, i64mem:$src2),
123 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
124 [(set VR64:$dst, (IntId VR64:$src1,
125 (bitconvert (load_mmx addr:$src2))))],
126 itins.rm>, Sched<[WriteVecShiftLd, ReadAfterLd]>;
127 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
128 (ins VR64:$src1, i32u8imm:$src2),
129 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
130 [(set VR64:$dst, (IntId2 VR64:$src1, imm:$src2))], itins.ri>,
131 Sched<[WriteVecShift]>;
135 /// Unary MMX instructions requiring SSSE3.
136 multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
137 Intrinsic IntId64, OpndItins itins> {
138 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
139 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
140 [(set VR64:$dst, (IntId64 VR64:$src))], itins.rr>,
141 Sched<[itins.Sched]>;
143 def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
144 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
146 (IntId64 (bitconvert (memopmmx addr:$src))))],
147 itins.rm>, Sched<[itins.Sched.Folded]>;
150 /// Binary MMX instructions requiring SSSE3.
151 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
152 multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
153 Intrinsic IntId64, OpndItins itins> {
154 let isCommutable = 0 in
155 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
156 (ins VR64:$src1, VR64:$src2),
157 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
158 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))], itins.rr>,
159 Sched<[itins.Sched]>;
160 def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst),
161 (ins VR64:$src1, i64mem:$src2),
162 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
165 (bitconvert (memopmmx addr:$src2))))], itins.rm>,
166 Sched<[itins.Sched.Folded, ReadAfterLd]>;
170 /// PALIGN MMX instructions (require SSSE3).
171 multiclass ssse3_palign_mm<string asm, Intrinsic IntId> {
172 def R64irr : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
173 (ins VR64:$src1, VR64:$src2, u8imm:$src3),
174 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
175 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>,
176 Sched<[WriteShuffle]>;
177 def R64irm : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
178 (ins VR64:$src1, i64mem:$src2, u8imm:$src3),
179 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
180 [(set VR64:$dst, (IntId VR64:$src1,
181 (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>,
182 Sched<[WriteShuffleLd, ReadAfterLd]>;
185 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
186 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
187 string asm, OpndItins itins, Domain d> {
188 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
189 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr, d>,
190 Sched<[itins.Sched]>;
191 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
192 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm, d>,
193 Sched<[itins.Sched.Folded]>;
196 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
197 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
198 PatFrag ld_frag, string asm, Domain d> {
199 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
200 (ins DstRC:$src1, SrcRC:$src2), asm,
201 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
202 NoItinerary, d>, Sched<[WriteCvtI2F]>;
203 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
204 (ins DstRC:$src1, x86memop:$src2), asm,
205 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
206 NoItinerary, d>, Sched<[WriteCvtI2FLd]>;
209 //===----------------------------------------------------------------------===//
210 // MMX EMMS Instruction
211 //===----------------------------------------------------------------------===//
213 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms",
214 [(int_x86_mmx_emms)], IIC_MMX_EMMS>;
216 //===----------------------------------------------------------------------===//
217 // MMX Scalar Instructions
218 //===----------------------------------------------------------------------===//
220 // Data Transfer Instructions
221 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
222 "movd\t{$src, $dst|$dst, $src}",
224 (x86mmx (scalar_to_vector GR32:$src)))],
225 IIC_MMX_MOV_MM_RM>, Sched<[WriteMove]>;
226 let canFoldAsLoad = 1 in
227 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
228 "movd\t{$src, $dst|$dst, $src}",
230 (x86mmx (scalar_to_vector (loadi32 addr:$src))))],
231 IIC_MMX_MOV_MM_RM>, Sched<[WriteLoad]>;
233 let Predicates = [HasMMX] in {
234 let AddedComplexity = 15 in
235 def : Pat<(x86mmx (MMX_X86movw2d GR32:$src)),
236 (MMX_MOVD64rr GR32:$src)>;
237 let AddedComplexity = 20 in
238 def : Pat<(x86mmx (MMX_X86movw2d (loadi32 addr:$src))),
239 (MMX_MOVD64rm addr:$src)>;
243 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
244 "movd\t{$src, $dst|$dst, $src}", [], IIC_MMX_MOV_MM_RM>,
247 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),
248 "movd\t{$src, $dst|$dst, $src}",
250 (MMX_X86movd2w (x86mmx VR64:$src)))],
251 IIC_MMX_MOV_REG_MM>, Sched<[WriteMove]>;
253 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
254 "movd\t{$src, $dst|$dst, $src}",
255 [(set VR64:$dst, (bitconvert GR64:$src))],
256 IIC_MMX_MOV_MM_RM>, Sched<[WriteMove]>;
258 // These are 64 bit moves, but since the OS X assembler doesn't
259 // recognize a register-register movq, we write them as
261 let SchedRW = [WriteMove] in {
262 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
263 (outs GR64:$dst), (ins VR64:$src),
264 "movd\t{$src, $dst|$dst, $src}",
266 (bitconvert VR64:$src))], IIC_MMX_MOV_REG_MM>;
267 let hasSideEffects = 0 in
268 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
269 "movq\t{$src, $dst|$dst, $src}", [],
271 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
272 def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src),
273 "movq\t{$src, $dst|$dst, $src}", [],
278 let SchedRW = [WriteLoad] in {
279 let canFoldAsLoad = 1 in
280 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
281 "movq\t{$src, $dst|$dst, $src}",
282 [(set VR64:$dst, (load_mmx addr:$src))],
285 let SchedRW = [WriteStore] in
286 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
287 "movq\t{$src, $dst|$dst, $src}",
288 [(store (x86mmx VR64:$src), addr:$dst)],
291 let SchedRW = [WriteMove] in {
292 def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
293 (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}",
296 (i64 (vector_extract (v2i64 VR128:$src),
300 def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst),
301 (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
305 (i64 (bitconvert (x86mmx VR64:$src))))))],
308 let isCodeGenOnly = 1, hasSideEffects = 1 in {
309 def MMX_MOVQ2FR64rr: MMXS2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst),
310 (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}",
311 [], IIC_MMX_MOVQ_RR>;
313 def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst),
314 (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}",
315 [], IIC_MMX_MOVQ_RR>;
319 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
320 "movntq\t{$src, $dst|$dst, $src}",
321 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)],
322 IIC_MMX_MOVQ_RM>, Sched<[WriteStore]>;
324 let Predicates = [HasMMX] in {
325 let AddedComplexity = 15 in
326 // movd to MMX register zero-extends
327 def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))),
328 (MMX_MOVD64rr GR32:$src)>;
329 let AddedComplexity = 20 in
330 def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector (loadi32 addr:$src))))),
331 (MMX_MOVD64rm addr:$src)>;
334 // Arithmetic Instructions
335 defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b,
337 defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w,
339 defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d,
342 defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b,
343 MMX_INTALU_ITINS, 1>;
344 defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w,
345 MMX_INTALU_ITINS, 1>;
346 defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d,
347 MMX_INTALU_ITINS, 1>;
348 defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q,
349 MMX_INTALUQ_ITINS, 1>;
350 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b,
351 MMX_INTALU_ITINS, 1>;
352 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w,
353 MMX_INTALU_ITINS, 1>;
355 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b,
356 MMX_INTALU_ITINS, 1>;
357 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w,
358 MMX_INTALU_ITINS, 1>;
360 defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w,
362 defm MMX_PHADD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d,
364 defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw,
369 defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b,
371 defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w,
373 defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d,
375 defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q,
378 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b,
380 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w,
383 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b,
385 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w,
388 defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w,
390 defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d,
392 defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw,
396 defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w,
399 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w,
401 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w,
403 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq,
405 let isCommutable = 1 in
406 defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw",
407 int_x86_ssse3_pmul_hr_sw, MMX_PMUL_ITINS>;
410 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd,
413 defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw",
414 int_x86_ssse3_pmadd_ub_sw, MMX_PMUL_ITINS>;
415 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b,
416 MMX_MISC_FUNC_ITINS, 1>;
417 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w,
418 MMX_MISC_FUNC_ITINS, 1>;
420 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b,
421 MMX_MISC_FUNC_ITINS, 1>;
422 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w,
423 MMX_MISC_FUNC_ITINS, 1>;
425 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b,
426 MMX_MISC_FUNC_ITINS, 1>;
427 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w,
428 MMX_MISC_FUNC_ITINS, 1>;
430 defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw,
431 MMX_PSADBW_ITINS, 1>;
433 defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b,
434 MMX_MISC_FUNC_ITINS>;
435 defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w,
436 MMX_MISC_FUNC_ITINS>;
437 defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d,
438 MMX_MISC_FUNC_ITINS>;
439 let Constraints = "$src1 = $dst" in
440 defm MMX_PALIGN : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>;
442 // Logical Instructions
443 defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand,
444 MMX_INTALU_ITINS_VECLOGICSCHED, 1>;
445 defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por,
446 MMX_INTALU_ITINS_VECLOGICSCHED, 1>;
447 defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor,
448 MMX_INTALU_ITINS_VECLOGICSCHED, 1>;
449 defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn,
450 MMX_INTALU_ITINS_VECLOGICSCHED>;
452 // Shift Instructions
453 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
454 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w,
456 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
457 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d,
459 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
460 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q,
463 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
464 int_x86_mmx_psll_w, int_x86_mmx_pslli_w,
466 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
467 int_x86_mmx_psll_d, int_x86_mmx_pslli_d,
469 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
470 int_x86_mmx_psll_q, int_x86_mmx_pslli_q,
473 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
474 int_x86_mmx_psra_w, int_x86_mmx_psrai_w,
476 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
477 int_x86_mmx_psra_d, int_x86_mmx_psrai_d,
480 // Comparison Instructions
481 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b,
483 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w,
485 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d,
488 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b,
490 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w,
492 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d,
495 // -- Unpack Instructions
496 defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw",
497 int_x86_mmx_punpckhbw,
499 defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd",
500 int_x86_mmx_punpckhwd,
502 defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq",
503 int_x86_mmx_punpckhdq,
505 defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw",
506 int_x86_mmx_punpcklbw,
508 defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd",
509 int_x86_mmx_punpcklwd,
511 defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq",
512 int_x86_mmx_punpckldq,
515 // -- Pack Instructions
516 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb,
518 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw,
520 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb,
523 // -- Shuffle Instructions
524 defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b,
527 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
528 (outs VR64:$dst), (ins VR64:$src1, u8imm:$src2),
529 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
531 (int_x86_sse_pshuf_w VR64:$src1, imm:$src2))],
532 IIC_MMX_PSHUF>, Sched<[WriteShuffle]>;
533 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
534 (outs VR64:$dst), (ins i64mem:$src1, u8imm:$src2),
535 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
537 (int_x86_sse_pshuf_w (load_mmx addr:$src1),
539 IIC_MMX_PSHUF>, Sched<[WriteShuffleLd]>;
544 // -- Conversion Instructions
545 defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
546 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
547 MMX_CVT_PS_ITINS, SSEPackedSingle>, PS;
548 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
549 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
550 MMX_CVT_PD_ITINS, SSEPackedDouble>, PD;
551 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
552 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
553 MMX_CVT_PS_ITINS, SSEPackedSingle>, PS;
554 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
555 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
556 MMX_CVT_PD_ITINS, SSEPackedDouble>, PD;
557 defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
558 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
559 MMX_CVT_PD_ITINS, SSEPackedDouble>, PD;
560 let Constraints = "$src1 = $dst" in {
561 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
562 int_x86_sse_cvtpi2ps,
563 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
564 SSEPackedSingle>, PS;
568 def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg,
569 (outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2),
570 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
571 [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1,
573 IIC_MMX_PEXTR>, Sched<[WriteShuffle]>;
574 let Constraints = "$src1 = $dst" in {
575 def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg,
577 (ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
578 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
579 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
580 GR32orGR64:$src2, imm:$src3))],
581 IIC_MMX_PINSRW>, Sched<[WriteShuffle]>;
583 def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem,
585 (ins VR64:$src1, i16mem:$src2, i32u8imm:$src3),
586 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
587 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,
588 (i32 (anyext (loadi16 addr:$src2))),
590 IIC_MMX_PINSRW>, Sched<[WriteShuffleLd, ReadAfterLd]>;
594 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
596 "pmovmskb\t{$src, $dst|$dst, $src}",
597 [(set GR32orGR64:$dst,
598 (int_x86_mmx_pmovmskb VR64:$src))]>;
601 // Low word of XMM to MMX.
602 def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1,
603 [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;
605 def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)),
606 (x86mmx (MMX_MOVDQ2Qrr VR128:$src))>;
608 def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))),
609 (x86mmx (MMX_MOVQ64rm addr:$src))>;
612 let SchedRW = [WriteShuffle] in {
614 def MMX_MASKMOVQ : MMXI32<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
615 "maskmovq\t{$mask, $src|$src, $mask}",
616 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)],
619 def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
620 "maskmovq\t{$mask, $src|$src, $mask}",
621 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)],
625 // 64-bit bit convert.
626 let Predicates = [HasSSE2] in {
627 def : Pat<(x86mmx (bitconvert (i64 GR64:$src))),
628 (MMX_MOVD64to64rr GR64:$src)>;
629 def : Pat<(i64 (bitconvert (x86mmx VR64:$src))),
630 (MMX_MOVD64from64rr VR64:$src)>;
631 def : Pat<(f64 (bitconvert (x86mmx VR64:$src))),
632 (MMX_MOVQ2FR64rr VR64:$src)>;
633 def : Pat<(x86mmx (bitconvert (f64 FR64:$src))),
634 (MMX_MOVFR642Qrr FR64:$src)>;