1 //====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 MMX instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Some 'special' instructions
17 let isImplicitDef = 1 in
18 def IMPLICIT_DEF_VR64 : I<0, Pseudo, (outs VR64:$dst), (ins),
20 [(set VR64:$dst, (v8i8 (undef)))]>,
23 // 64-bit vector undef's.
24 def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>;
25 def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
26 def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
27 def : Pat<(v1i64 (undef)), (IMPLICIT_DEF_VR64)>;
29 //===----------------------------------------------------------------------===//
30 // MMX Pattern Fragments
31 //===----------------------------------------------------------------------===//
33 def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
35 def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
36 def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
37 def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
38 def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
44 // MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
46 def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
47 return getI8Imm(X86::getShuffleSHUFImmediate(N));
50 // Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
51 def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
52 return X86::isUNPCKHMask(N);
55 // Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
56 def MMX_UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
57 return X86::isUNPCKLMask(N);
60 // Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
61 def MMX_UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
62 return X86::isUNPCKH_v_undef_Mask(N);
65 // Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
66 def MMX_UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
67 return X86::isUNPCKL_v_undef_Mask(N);
70 // Patterns for shuffling.
71 def MMX_PSHUFW_shuffle_mask : PatLeaf<(build_vector), [{
72 return X86::isPSHUFDMask(N);
73 }], MMX_SHUFFLE_get_shuf_imm>;
75 // Patterns for: vector_shuffle v1, v2, <4, 5, 2, 3>; etc.
76 def MMX_MOVL_shuffle_mask : PatLeaf<(build_vector), [{
77 return X86::isMOVLMask(N);
80 //===----------------------------------------------------------------------===//
82 //===----------------------------------------------------------------------===//
84 let isTwoAddress = 1 in {
85 // MMXI_binop_rm - Simple MMX binary operator.
86 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
87 ValueType OpVT, bit Commutable = 0> {
88 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
89 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
90 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
91 let isCommutable = Commutable;
93 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
94 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
95 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
97 (load_mmx addr:$src2)))))]>;
100 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
101 bit Commutable = 0> {
102 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
103 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
104 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
105 let isCommutable = Commutable;
107 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
108 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
109 [(set VR64:$dst, (IntId VR64:$src1,
110 (bitconvert (load_mmx addr:$src2))))]>;
113 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
115 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
116 // to collapse (bitconvert VT to VT) into its operand.
118 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
119 bit Commutable = 0> {
120 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
121 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
122 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
123 let isCommutable = Commutable;
125 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
126 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
128 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
131 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
132 string OpcodeStr, Intrinsic IntId> {
133 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
134 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
135 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
136 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
137 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
138 [(set VR64:$dst, (IntId VR64:$src1,
139 (bitconvert (load_mmx addr:$src2))))]>;
140 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), (ins VR64:$src1, i32i8imm:$src2),
141 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
142 [(set VR64:$dst, (IntId VR64:$src1,
143 (scalar_to_vector (i32 imm:$src2))))]>;
147 //===----------------------------------------------------------------------===//
148 // MMX EMMS & FEMMS Instructions
149 //===----------------------------------------------------------------------===//
151 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
152 def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
154 //===----------------------------------------------------------------------===//
155 // MMX Scalar Instructions
156 //===----------------------------------------------------------------------===//
158 // Data Transfer Instructions
159 let neverHasSideEffects = 1 in
160 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
161 "movd\t{$src, $dst|$dst, $src}", []>;
162 let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
163 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
164 "movd\t{$src, $dst|$dst, $src}", []>;
166 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
167 "movd\t{$src, $dst|$dst, $src}", []>;
169 let neverHasSideEffects = 1 in
170 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
171 "movd\t{$src, $dst|$dst, $src}", []>;
173 let neverHasSideEffects = 1 in
174 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
175 "movq\t{$src, $dst|$dst, $src}", []>;
176 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
177 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
178 "movq\t{$src, $dst|$dst, $src}",
179 [(set VR64:$dst, (load_mmx addr:$src))]>;
180 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
181 "movq\t{$src, $dst|$dst, $src}",
182 [(store (v1i64 VR64:$src), addr:$dst)]>;
184 def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
185 "movdq2q\t{$src, $dst|$dst, $src}",
187 (v1i64 (vector_extract (v2i64 VR128:$src),
190 def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
191 "movq2dq\t{$src, $dst|$dst, $src}",
193 (bitconvert (v1i64 VR64:$src)))]>;
195 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
196 "movntq\t{$src, $dst|$dst, $src}",
197 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
199 let AddedComplexity = 15 in
200 // movd to MMX register zero-extends
201 def MMX_MOVZDI2PDIrr : MMX2I<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
202 "movd\t{$src, $dst|$dst, $src}",
204 (v2i32 (vector_shuffle immAllZerosV,
205 (v2i32 (scalar_to_vector GR32:$src)),
206 MMX_MOVL_shuffle_mask)))]>;
207 let AddedComplexity = 20 in
208 def MMX_MOVZDI2PDIrm : MMX2I<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
209 "movd\t{$src, $dst|$dst, $src}",
211 (v2i32 (vector_shuffle immAllZerosV,
212 (v2i32 (scalar_to_vector
213 (loadi32 addr:$src))),
214 MMX_MOVL_shuffle_mask)))]>;
216 // Arithmetic Instructions
219 defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
220 defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
221 defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
222 defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>;
224 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
225 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
227 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
228 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
231 defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
232 defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
233 defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
234 defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>;
236 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
237 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
239 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
240 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
243 defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
245 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
246 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
247 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
250 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
252 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
253 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
255 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
256 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
258 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
259 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
261 defm MMX_PSADBW : MMXI_binop_rm_int<0xE0, "psadbw", int_x86_mmx_psad_bw, 1>;
263 // Logical Instructions
264 defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
265 defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
266 defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
268 let isTwoAddress = 1 in {
269 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
270 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
271 "pandn\t{$src2, $dst|$dst, $src2}",
272 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
274 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
275 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
276 "pandn\t{$src2, $dst|$dst, $src2}",
277 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
278 (load addr:$src2))))]>;
281 // Shift Instructions
282 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
284 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
286 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
289 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
291 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
293 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
296 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
298 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
301 // Comparison Instructions
302 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
303 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
304 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
306 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
307 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
308 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
310 // Conversion Instructions
312 // -- Unpack Instructions
313 let isTwoAddress = 1 in {
314 // Unpack High Packed Data Instructions
315 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
316 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
317 "punpckhbw\t{$src2, $dst|$dst, $src2}",
319 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
320 MMX_UNPCKH_shuffle_mask)))]>;
321 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
322 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
323 "punpckhbw\t{$src2, $dst|$dst, $src2}",
325 (v8i8 (vector_shuffle VR64:$src1,
326 (bc_v8i8 (load_mmx addr:$src2)),
327 MMX_UNPCKH_shuffle_mask)))]>;
329 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
330 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
331 "punpckhwd\t{$src2, $dst|$dst, $src2}",
333 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
334 MMX_UNPCKH_shuffle_mask)))]>;
335 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
336 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
337 "punpckhwd\t{$src2, $dst|$dst, $src2}",
339 (v4i16 (vector_shuffle VR64:$src1,
340 (bc_v4i16 (load_mmx addr:$src2)),
341 MMX_UNPCKH_shuffle_mask)))]>;
343 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
344 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
345 "punpckhdq\t{$src2, $dst|$dst, $src2}",
347 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
348 MMX_UNPCKH_shuffle_mask)))]>;
349 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
350 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
351 "punpckhdq\t{$src2, $dst|$dst, $src2}",
353 (v2i32 (vector_shuffle VR64:$src1,
354 (bc_v2i32 (load_mmx addr:$src2)),
355 MMX_UNPCKH_shuffle_mask)))]>;
357 // Unpack Low Packed Data Instructions
358 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
359 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
360 "punpcklbw\t{$src2, $dst|$dst, $src2}",
362 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
363 MMX_UNPCKL_shuffle_mask)))]>;
364 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
365 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
366 "punpcklbw\t{$src2, $dst|$dst, $src2}",
368 (v8i8 (vector_shuffle VR64:$src1,
369 (bc_v8i8 (load_mmx addr:$src2)),
370 MMX_UNPCKL_shuffle_mask)))]>;
372 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
373 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
374 "punpcklwd\t{$src2, $dst|$dst, $src2}",
376 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
377 MMX_UNPCKL_shuffle_mask)))]>;
378 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
379 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
380 "punpcklwd\t{$src2, $dst|$dst, $src2}",
382 (v4i16 (vector_shuffle VR64:$src1,
383 (bc_v4i16 (load_mmx addr:$src2)),
384 MMX_UNPCKL_shuffle_mask)))]>;
386 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
387 (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
388 "punpckldq\t{$src2, $dst|$dst, $src2}",
390 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
391 MMX_UNPCKL_shuffle_mask)))]>;
392 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
393 (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
394 "punpckldq\t{$src2, $dst|$dst, $src2}",
396 (v2i32 (vector_shuffle VR64:$src1,
397 (bc_v2i32 (load_mmx addr:$src2)),
398 MMX_UNPCKL_shuffle_mask)))]>;
401 // -- Pack Instructions
402 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
403 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
404 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
406 // -- Shuffle Instructions
407 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
408 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
409 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
411 (v4i16 (vector_shuffle
413 MMX_PSHUFW_shuffle_mask:$src2)))]>;
414 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
415 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
416 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
418 (v4i16 (vector_shuffle
419 (bc_v4i16 (load_mmx addr:$src1)),
421 MMX_PSHUFW_shuffle_mask:$src2)))]>;
423 // -- Conversion Instructions
424 let neverHasSideEffects = 1 in {
425 def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
426 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
428 def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
429 "cvtpd2pi\t{$src, $dst|$dst, $src}", []>;
431 def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
432 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
434 def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
435 "cvtpi2pd\t{$src, $dst|$dst, $src}", []>;
437 def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
438 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
440 def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
441 "cvtpi2ps\t{$src, $dst|$dst, $src}", []>;
443 def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
444 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
446 def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
447 "cvtps2pi\t{$src, $dst|$dst, $src}", []>;
449 def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
450 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
452 def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
453 "cvttpd2pi\t{$src, $dst|$dst, $src}", []>;
455 def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
456 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
458 def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
459 "cvttps2pi\t{$src, $dst|$dst, $src}", []>;
460 } // end neverHasSideEffects
464 def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
465 def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
467 def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
468 (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
469 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
470 [(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
471 (iPTR imm:$src2)))]>;
472 let isTwoAddress = 1 in {
473 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
474 (outs VR64:$dst), (ins VR64:$src1, GR32:$src2, i16i8imm:$src3),
475 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
476 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
477 GR32:$src2, (iPTR imm:$src3))))]>;
478 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
479 (outs VR64:$dst), (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
480 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
482 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
483 (i32 (anyext (loadi16 addr:$src2))),
484 (iPTR imm:$src3))))]>;
488 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
489 "pmovmskb\t{$src, $dst|$dst, $src}",
490 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
494 def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
495 "maskmovq\t{$mask, $src|$src, $mask}",
496 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
498 //===----------------------------------------------------------------------===//
499 // Alias Instructions
500 //===----------------------------------------------------------------------===//
502 // Alias instructions that map zero vector to pxor.
503 let isReMaterializable = 1 in {
504 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins),
506 [(set VR64:$dst, (v2i32 immAllZerosV))]>;
507 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins),
508 "pcmpeqd\t$dst, $dst",
509 [(set VR64:$dst, (v2i32 immAllOnesV))]>;
512 //===----------------------------------------------------------------------===//
513 // Non-Instruction Patterns
514 //===----------------------------------------------------------------------===//
516 // Store 64-bit integer vector values.
517 def : Pat<(store (v8i8 VR64:$src), addr:$dst),
518 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
519 def : Pat<(store (v4i16 VR64:$src), addr:$dst),
520 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
521 def : Pat<(store (v2i32 VR64:$src), addr:$dst),
522 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
523 def : Pat<(store (v1i64 VR64:$src), addr:$dst),
524 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
527 def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
528 def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
529 def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
530 def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
531 def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
532 def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
533 def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
534 def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
535 def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
536 def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
537 def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
538 def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
540 // 64-bit bit convert.
541 def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
542 (MMX_MOVD64to64rr GR64:$src)>;
543 def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
544 (MMX_MOVD64to64rr GR64:$src)>;
545 def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
546 (MMX_MOVD64to64rr GR64:$src)>;
547 def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
548 (MMX_MOVD64to64rr GR64:$src)>;
550 def MMX_X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
552 // Move scalar to XMM zero-extended
553 // movd to XMM register zero-extends
554 let AddedComplexity = 15 in {
555 def : Pat<(v8i8 (vector_shuffle immAllZerosV_bc,
556 (v8i8 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
557 (MMX_MOVZDI2PDIrr GR32:$src)>;
558 def : Pat<(v4i16 (vector_shuffle immAllZerosV_bc,
559 (v4i16 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
560 (MMX_MOVZDI2PDIrr GR32:$src)>;
561 def : Pat<(v2i32 (vector_shuffle immAllZerosV,
562 (v2i32 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
563 (MMX_MOVZDI2PDIrr GR32:$src)>;
566 // Scalar to v2i32 / v4i16 / v8i8. The source may be a GR32, but only the lower
567 // 8 or 16-bits matter.
568 def : Pat<(v8i8 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
569 def : Pat<(v4i16 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
570 def : Pat<(v2i32 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
572 // Patterns to perform canonical versions of vector shuffling.
573 let AddedComplexity = 10 in {
574 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
575 MMX_UNPCKL_v_undef_shuffle_mask)),
576 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
577 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
578 MMX_UNPCKL_v_undef_shuffle_mask)),
579 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
580 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
581 MMX_UNPCKL_v_undef_shuffle_mask)),
582 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
585 let AddedComplexity = 10 in {
586 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
587 MMX_UNPCKH_v_undef_shuffle_mask)),
588 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
589 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
590 MMX_UNPCKH_v_undef_shuffle_mask)),
591 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
592 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
593 MMX_UNPCKH_v_undef_shuffle_mask)),
594 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
597 // Patterns to perform vector shuffling with a zeroed out vector.
598 let AddedComplexity = 20 in {
599 def : Pat<(bc_v2i32 (vector_shuffle immAllZerosV,
600 (v2i32 (scalar_to_vector (load_mmx addr:$src))),
601 MMX_UNPCKL_shuffle_mask)),
602 (MMX_PUNPCKLDQrm VR64:$src, VR64:$src)>;
605 // Some special case PANDN patterns.
606 // FIXME: Get rid of these.
607 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
609 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
610 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
612 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
613 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
615 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
617 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
619 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
620 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV_bc))),
622 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
623 def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV_bc))),
625 (MMX_PANDNrm VR64:$src1, addr:$src2)>;