1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // Format specifies the encoding used by the instruction. This is part of the
17 // ad-hoc solution used to emit machine instruction encodings by our machine
19 class Format<bits<5> val> {
23 def Pseudo : Format<0>; def RawFrm : Format<1>;
24 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
25 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
26 def MRMSrcMem : Format<6>;
27 def MRMS0r : Format<16>; def MRMS1r : Format<17>; def MRMS2r : Format<18>;
28 def MRMS3r : Format<19>; def MRMS4r : Format<20>; def MRMS5r : Format<21>;
29 def MRMS6r : Format<22>; def MRMS7r : Format<23>;
30 def MRMS0m : Format<24>; def MRMS1m : Format<25>; def MRMS2m : Format<26>;
31 def MRMS3m : Format<27>; def MRMS4m : Format<28>; def MRMS5m : Format<29>;
32 def MRMS6m : Format<30>; def MRMS7m : Format<31>;
34 // ArgType - This specifies the argument type used by an instruction. This is
35 // part of the ad-hoc solution used to emit machine instruction encodings by our
36 // machine code emitter.
37 class ArgType<bits<3> val> {
40 def NoArg : ArgType<0>;
41 def Arg8 : ArgType<1>;
42 def Arg16 : ArgType<2>;
43 def Arg32 : ArgType<3>;
44 def Arg64 : ArgType<4>; // 64 bit int argument for FILD64
45 def ArgF32 : ArgType<5>;
46 def ArgF64 : ArgType<6>;
47 def ArgF80 : ArgType<6>;
49 // FPFormat - This specifies what form this FP instruction has. This is used by
50 // the Floating-Point stackifier pass.
51 class FPFormat<bits<3> val> {
54 def NotFP : FPFormat<0>;
55 def ZeroArgFP : FPFormat<1>;
56 def OneArgFP : FPFormat<2>;
57 def OneArgFPRW : FPFormat<3>;
58 def TwoArgFP : FPFormat<4>;
59 def SpecialFP : FPFormat<5>;
62 class X86Inst<string nam, bits<8> opcod, Format f, ArgType a> : Instruction {
63 let Namespace = "X86";
66 bits<8> Opcode = opcod;
68 bits<5> FormBits = Form.Value;
70 bits<3> TypeBits = Type.Value;
72 // Attributes specific to X86 instructions...
73 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
74 bit printImplicitUses = 0; // Should we print implicit uses of this inst?
76 bits<4> Prefix = 0; // Which prefix byte does this inst have?
77 FPFormat FPForm; // What flavor of FP instruction is this?
78 bits<3> FPFormBits = 0;
81 class Imp<list<Register> uses, list<Register> defs> {
82 list<Register> Uses = uses;
83 list<Register> Defs = defs;
86 class Pattern<dag P> {
91 // Prefix byte classes which are used to indicate to the ad-hoc machine code
92 // emitter that various prefix bytes are required.
93 class OpSize { bit hasOpSizePrefix = 1; }
94 class TB { bits<4> Prefix = 1; }
95 class REP { bits<4> Prefix = 2; }
96 class D8 { bits<4> Prefix = 3; }
97 class D9 { bits<4> Prefix = 4; }
98 class DA { bits<4> Prefix = 5; }
99 class DB { bits<4> Prefix = 6; }
100 class DC { bits<4> Prefix = 7; }
101 class DD { bits<4> Prefix = 8; }
102 class DE { bits<4> Prefix = 9; }
103 class DF { bits<4> Prefix = 10; }
107 //===----------------------------------------------------------------------===//
108 // Instruction list...
111 def PHI : X86Inst<"PHI", 0, Pseudo, NoArg>; // PHI node...
113 def NOOP : X86Inst<"nop", 0x90, RawFrm, NoArg>; // nop
115 def ADJCALLSTACKDOWN : X86Inst<"ADJCALLSTACKDOWN", 0, Pseudo, NoArg>;
116 def ADJCALLSTACKUP : X86Inst<"ADJCALLSTACKUP", 0, Pseudo, NoArg>;
117 def IMPLICIT_USE : X86Inst<"IMPLICIT_USE", 0, Pseudo, NoArg>;
118 def IMPLICIT_DEF : X86Inst<"IMPLICIT_DEF", 0, Pseudo, NoArg>;
119 let isTerminator = 1 in
120 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
121 def FP_REG_KILL : X86Inst<"FP_REG_KILL", 0, Pseudo, NoArg>;
122 //===----------------------------------------------------------------------===//
123 // Control Flow Instructions...
126 // Return instruction...
127 let isTerminator = 1, isReturn = 1 in
128 def RET : X86Inst<"ret", 0xC3, RawFrm, NoArg>, Pattern<(retvoid)>;
130 // All branches are RawFrm, Void, Branch, and Terminators
131 let isBranch = 1, isTerminator = 1 in
132 class IBr<string name, bits<8> opcode> : X86Inst<name, opcode, RawFrm, NoArg>;
134 def JMP : IBr<"jmp", 0xE9>, Pattern<(br basicblock)>;
135 def JB : IBr<"jb" , 0x82>, TB;
136 def JAE : IBr<"jae", 0x83>, TB;
137 def JE : IBr<"je" , 0x84>, TB, Pattern<(isVoid (unspec1 basicblock))>;
138 def JNE : IBr<"jne", 0x85>, TB;
139 def JBE : IBr<"jbe", 0x86>, TB;
140 def JA : IBr<"ja" , 0x87>, TB;
141 def JS : IBr<"js" , 0x88>, TB;
142 def JNS : IBr<"jns", 0x89>, TB;
143 def JL : IBr<"jl" , 0x8C>, TB;
144 def JGE : IBr<"jge", 0x8D>, TB;
145 def JLE : IBr<"jle", 0x8E>, TB;
146 def JG : IBr<"jg" , 0x8F>, TB;
149 //===----------------------------------------------------------------------===//
150 // Call Instructions...
153 // All calls clobber the non-callee saved registers...
154 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
155 def CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoArg>;
156 def CALLr32 : X86Inst<"call", 0xFF, MRMS2r, Arg32>;
157 def CALLm32 : X86Inst<"call", 0xFF, MRMS2m, Arg32>;
161 //===----------------------------------------------------------------------===//
162 // Miscellaneous Instructions...
164 def LEAVE : X86Inst<"leave", 0xC9, RawFrm, NoArg>, Imp<[EBP], [EBP]>;
166 let isTwoAddress = 1 in // R32 = bswap R32
167 def BSWAPr32 : X86Inst<"bswap", 0xC8, AddRegFrm, Arg32>, TB;
169 def XCHGrr8 : X86Inst<"xchg", 0x86, MRMDestReg, Arg8>; // xchg R8, R8
170 def XCHGrr16 : X86Inst<"xchg", 0x87, MRMDestReg, Arg16>, OpSize;// xchg R16, R16
171 def XCHGrr32 : X86Inst<"xchg", 0x87, MRMDestReg, Arg32>; // xchg R32, R32
173 def LEAr16 : X86Inst<"lea", 0x8D, MRMSrcMem, Arg16>, OpSize; // R16 = lea [mem]
174 def LEAr32 : X86Inst<"lea", 0x8D, MRMSrcMem, Arg32>; // R32 = lea [mem]
177 def REP_MOVSB : X86Inst<"rep movsb", 0xA4, RawFrm, NoArg>, REP,
178 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
179 def REP_MOVSW : X86Inst<"rep movsw", 0xA5, RawFrm, NoArg>, REP, OpSize,
180 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
181 def REP_MOVSD : X86Inst<"rep movsd", 0xA5, RawFrm, NoArg>, REP,
182 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>;
184 def REP_STOSB : X86Inst<"rep stosb", 0xAA, RawFrm, NoArg>, REP,
185 Imp<[AL,ECX,EDI], [ECX,EDI]>;
186 def REP_STOSW : X86Inst<"rep stosw", 0xAB, RawFrm, NoArg>, REP, OpSize,
187 Imp<[AX,ECX,EDI], [ECX,EDI]>;
188 def REP_STOSD : X86Inst<"rep stosd", 0xAB, RawFrm, NoArg>, REP,
189 Imp<[EAX,ECX,EDI], [ECX,EDI]>;
191 //===----------------------------------------------------------------------===//
192 // Move Instructions...
194 def MOVrr8 : X86Inst<"mov", 0x88, MRMDestReg, Arg8>, Pattern<(set R8 , R8 )>;
195 def MOVrr16 : X86Inst<"mov", 0x89, MRMDestReg, Arg16>, OpSize, Pattern<(set R16, R16)>;
196 def MOVrr32 : X86Inst<"mov", 0x89, MRMDestReg, Arg32>, Pattern<(set R32, R32)>;
197 def MOVir8 : X86Inst<"mov", 0xB0, AddRegFrm , Arg8>, Pattern<(set R8 , imm )>;
198 def MOVir16 : X86Inst<"mov", 0xB8, AddRegFrm , Arg16>, OpSize, Pattern<(set R16, imm)>;
199 def MOVir32 : X86Inst<"mov", 0xB8, AddRegFrm , Arg32>, Pattern<(set R32, imm)>;
200 def MOVim8 : X86Inst<"mov", 0xC6, MRMS0m , Arg8>; // [mem] = imm8
201 def MOVim16 : X86Inst<"mov", 0xC7, MRMS0m , Arg16>, OpSize; // [mem] = imm16
202 def MOVim32 : X86Inst<"mov", 0xC7, MRMS0m , Arg32>; // [mem] = imm32
204 def MOVmr8 : X86Inst<"mov", 0x8A, MRMSrcMem , Arg8>; // R8 = [mem]
205 def MOVmr16 : X86Inst<"mov", 0x8B, MRMSrcMem , Arg16>, OpSize, // R16 = [mem]
206 Pattern<(set R16, (load (plus R32, (plus (times imm, R32), imm))))>;
207 def MOVmr32 : X86Inst<"mov", 0x8B, MRMSrcMem , Arg32>, // R32 = [mem]
208 Pattern<(set R32, (load (plus R32, (plus (times imm, R32), imm))))>;
210 def MOVrm8 : X86Inst<"mov", 0x88, MRMDestMem, Arg8>; // [mem] = R8
211 def MOVrm16 : X86Inst<"mov", 0x89, MRMDestMem, Arg16>, OpSize; // [mem] = R16
212 def MOVrm32 : X86Inst<"mov", 0x89, MRMDestMem, Arg32>; // [mem] = R32
214 //===----------------------------------------------------------------------===//
215 // Fixed-Register Multiplication and Division Instructions...
218 // Extra precision multiplication
219 def MULr8 : X86Inst<"mul", 0xF6, MRMS4r, Arg8 >, Imp<[AL],[AX]>; // AL,AH = AL*R8
220 def MULr16 : X86Inst<"mul", 0xF7, MRMS4r, Arg16>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
221 def MULr32 : X86Inst<"mul", 0xF7, MRMS4r, Arg32>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
223 // unsigned division/remainder
224 def DIVr8 : X86Inst<"div", 0xF6, MRMS6r, Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
225 def DIVr16 : X86Inst<"div", 0xF7, MRMS6r, Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
226 def DIVr32 : X86Inst<"div", 0xF7, MRMS6r, Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
228 // signed division/remainder
229 def IDIVr8 : X86Inst<"idiv",0xF6, MRMS7r, Arg8 >, Imp<[AX],[AX]>; // AX/r8 = AL,AH
230 def IDIVr16: X86Inst<"idiv",0xF7, MRMS7r, Arg16>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
231 def IDIVr32: X86Inst<"idiv",0xF7, MRMS7r, Arg32>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
233 // Sign-extenders for division
234 def CBW : X86Inst<"cbw", 0x98, RawFrm, Arg8 >, Imp<[AL],[AH]>; // AX = signext(AL)
235 def CWD : X86Inst<"cwd", 0x99, RawFrm, Arg8 >, Imp<[AX],[DX]>; // DX:AX = signext(AX)
236 def CDQ : X86Inst<"cdq", 0x99, RawFrm, Arg8 >, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
238 //===----------------------------------------------------------------------===//
239 // Two address Instructions...
241 let isTwoAddress = 1 in { // Define some helper classes to make defs shorter.
242 class I2A8 <string n, bits<8> o, Format F> : X86Inst<n, o, F, Arg8>;
243 class I2A16<string n, bits<8> o, Format F> : X86Inst<n, o, F, Arg16>;
244 class I2A32<string n, bits<8> o, Format F> : X86Inst<n, o, F, Arg32>;
247 // unary instructions
248 def NEGr8 : I2A8 <"neg", 0xF6, MRMS3r>; // R8 = -R8 = 0-R8
249 def NEGr16 : I2A16<"neg", 0xF7, MRMS3r>, OpSize; // R16 = -R16 = 0-R16
250 def NEGr32 : I2A32<"neg", 0xF7, MRMS3r>; // R32 = -R32 = 0-R32
251 def NOTr8 : I2A8 <"not", 0xF6, MRMS2r>; // R8 = ~R8 = R8^-1
252 def NOTr16 : I2A16<"not", 0xF7, MRMS2r>, OpSize; // R16 = ~R16 = R16^-1
253 def NOTr32 : I2A32<"not", 0xF7, MRMS2r>; // R32 = ~R32 = R32^-1
255 def INCr8 : I2A8 <"inc", 0xFE, MRMS0r>; // R8 = R8 +1
256 def INCr16 : I2A16<"inc", 0xFF, MRMS0r>, OpSize; // R16 = R16+1
257 def INCr32 : I2A32<"inc", 0xFF, MRMS0r>; // R32 = R32+1
258 def DECr8 : I2A8 <"dec", 0xFE, MRMS1r>; // R8 = R8 -1
259 def DECr16 : I2A16<"dec", 0xFF, MRMS1r>, OpSize; // R16 = R16-1
260 def DECr32 : I2A32<"dec", 0xFF, MRMS1r>; // R32 = R32-1
265 def ADDrr8 : I2A8 <"add", 0x00, MRMDestReg>, Pattern<(set R8 , (plus R8 , R8 ))>;
266 def ADDrr16 : I2A16<"add", 0x01, MRMDestReg>, OpSize, Pattern<(set R16, (plus R16, R16))>;
267 def ADDrr32 : I2A32<"add", 0x01, MRMDestReg>, Pattern<(set R32, (plus R32, R32))>;
268 def ADDri8 : I2A8 <"add", 0x80, MRMS0r >, Pattern<(set R8 , (plus R8 , imm))>;
269 def ADDri16 : I2A16<"add", 0x81, MRMS0r >, OpSize, Pattern<(set R16, (plus R16, imm))>;
270 def ADDri32 : I2A32<"add", 0x81, MRMS0r >, Pattern<(set R32, (plus R32, imm))>;
271 def ADDri16b : I2A8 <"add", 0x83, MRMS0r >, OpSize; // ADDri with sign extended 8 bit imm
272 def ADDri32b : I2A8 <"add", 0x83, MRMS0r >;
274 def ADCrr32 : I2A32<"adc", 0x11, MRMDestReg>; // R32 += imm32+Carry
276 def SUBrr8 : I2A8 <"sub", 0x28, MRMDestReg>, Pattern<(set R8 , (minus R8 , R8 ))>;
277 def SUBrr16 : I2A16<"sub", 0x29, MRMDestReg>, OpSize, Pattern<(set R16, (minus R16, R16))>;
278 def SUBrr32 : I2A32<"sub", 0x29, MRMDestReg>, Pattern<(set R32, (minus R32, R32))>;
279 def SUBri8 : I2A8 <"sub", 0x80, MRMS5r >, Pattern<(set R8 , (minus R8 , imm))>;
280 def SUBri16 : I2A16<"sub", 0x81, MRMS5r >, OpSize, Pattern<(set R16, (minus R16, imm))>;
281 def SUBri32 : I2A32<"sub", 0x81, MRMS5r >, Pattern<(set R32, (minus R32, imm))>;
282 def SUBri16b : I2A8 <"sub", 0x83, MRMS5r >, OpSize;
283 def SUBri32b : I2A8 <"sub", 0x83, MRMS5r >;
285 def SBBrr32 : I2A32<"sbb", 0x19, MRMDestReg>; // R32 -= R32+Carry
287 def IMULrr16 : I2A16<"imul", 0xAF, MRMSrcReg>, TB, OpSize, Pattern<(set R16, (times R16, R16))>;
288 def IMULrr32 : I2A32<"imul", 0xAF, MRMSrcReg>, TB , Pattern<(set R32, (times R32, R32))>;
290 // These are suprisingly enough not two addres instructions!
291 def IMULri16 : X86Inst<"imul", 0x69, MRMSrcReg, Arg16>, OpSize;
292 def IMULri32 : X86Inst<"imul", 0x69, MRMSrcReg, Arg32>;
293 def IMULri16b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8>, OpSize;
294 def IMULri32b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8>;
297 // Logical operators...
298 def ANDrr8 : I2A8 <"and", 0x20, MRMDestReg>, Pattern<(set R8 , (and R8 , R8 ))>;
299 def ANDrr16 : I2A16<"and", 0x21, MRMDestReg>, OpSize, Pattern<(set R16, (and R16, R16))>;
300 def ANDrr32 : I2A32<"and", 0x21, MRMDestReg>, Pattern<(set R32, (and R32, R32))>;
301 def ANDri8 : I2A8 <"and", 0x80, MRMS4r >, Pattern<(set R8 , (and R8 , imm))>;
302 def ANDri16 : I2A16<"and", 0x81, MRMS4r >, OpSize, Pattern<(set R16, (and R16, imm))>;
303 def ANDri32 : I2A32<"and", 0x81, MRMS4r >, Pattern<(set R32, (and R32, imm))>;
304 def ANDri16b : I2A8 <"and", 0x83, MRMS4r >, OpSize;
305 def ANDri32b : I2A8 <"and", 0x83, MRMS4r >;
307 def ORrr8 : I2A8 <"or" , 0x08, MRMDestReg>, Pattern<(set R8 , (or R8 , R8 ))>;
308 def ORrr16 : I2A16<"or" , 0x09, MRMDestReg>, OpSize, Pattern<(set R16, (or R16, R16))>;
309 def ORrr32 : I2A32<"or" , 0x09, MRMDestReg>, Pattern<(set R32, (or R32, R32))>;
310 def ORri8 : I2A8 <"or" , 0x80, MRMS1r >, Pattern<(set R8 , (or R8 , imm))>;
311 def ORri16 : I2A16<"or" , 0x81, MRMS1r >, OpSize, Pattern<(set R16, (or R16, imm))>;
312 def ORri32 : I2A32<"or" , 0x81, MRMS1r >, Pattern<(set R32, (or R32, imm))>;
313 def ORri16b : I2A8 <"or" , 0x83, MRMS1r >, OpSize;
314 def ORri32b : I2A8 <"or" , 0x83, MRMS1r >;
317 def XORrr8 : I2A8 <"xor", 0x30, MRMDestReg>, Pattern<(set R8 , (xor R8 , R8 ))>;
318 def XORrr16 : I2A16<"xor", 0x31, MRMDestReg>, OpSize, Pattern<(set R16, (xor R16, R16))>;
319 def XORrr32 : I2A32<"xor", 0x31, MRMDestReg>, Pattern<(set R32, (xor R32, R32))>;
320 def XORri8 : I2A8 <"xor", 0x80, MRMS6r >, Pattern<(set R8 , (xor R8 , imm))>;
321 def XORri16 : I2A16<"xor", 0x81, MRMS6r >, OpSize, Pattern<(set R16, (xor R16, imm))>;
322 def XORri32 : I2A32<"xor", 0x81, MRMS6r >, Pattern<(set R32, (xor R32, imm))>;
323 def XORri16b : I2A8 <"xor", 0x83, MRMS6r >, OpSize;
324 def XORri32b : I2A8 <"xor", 0x83, MRMS6r >;
326 // Test instructions are just like AND, except they don't generate a result.
327 def TESTrr8 : X86Inst<"test", 0x84, MRMDestReg, Arg8 >; // flags = R8 & R8
328 def TESTrr16 : X86Inst<"test", 0x85, MRMDestReg, Arg16>, OpSize; // flags = R16 & R16
329 def TESTrr32 : X86Inst<"test", 0x85, MRMDestReg, Arg32>; // flags = R32 & R32
330 def TESTri8 : X86Inst<"test", 0xF6, MRMS0r , Arg8 >; // flags = R8 & imm8
331 def TESTri16 : X86Inst<"test", 0xF7, MRMS0r , Arg16>, OpSize; // flags = R16 & imm16
332 def TESTri32 : X86Inst<"test", 0xF7, MRMS0r , Arg32>; // flags = R32 & imm32
334 // Shift instructions
335 class UsesCL { list<Register> Uses = [CL]; bit printImplicitUses = 1; }
337 def SHLrr8 : I2A8 <"shl", 0xD2, MRMS4r > , UsesCL; // R8 <<= cl
338 def SHLrr16 : I2A8 <"shl", 0xD3, MRMS4r >, OpSize, UsesCL; // R16 <<= cl
339 def SHLrr32 : I2A8 <"shl", 0xD3, MRMS4r > , UsesCL; // R32 <<= cl
340 def SHLir8 : I2A8 <"shl", 0xC0, MRMS4r >; // R8 <<= imm8
341 def SHLir16 : I2A8 <"shl", 0xC1, MRMS4r >, OpSize; // R16 <<= imm16
342 def SHLir32 : I2A8 <"shl", 0xC1, MRMS4r >; // R32 <<= imm32
343 def SHRrr8 : I2A8 <"shr", 0xD2, MRMS5r > , UsesCL; // R8 >>= cl
344 def SHRrr16 : I2A8 <"shr", 0xD3, MRMS5r >, OpSize, UsesCL; // R16 >>= cl
345 def SHRrr32 : I2A8 <"shr", 0xD3, MRMS5r > , UsesCL; // R32 >>= cl
346 def SHRir8 : I2A8 <"shr", 0xC0, MRMS5r >; // R8 >>= imm8
347 def SHRir16 : I2A8 <"shr", 0xC1, MRMS5r >, OpSize; // R16 >>= imm16
348 def SHRir32 : I2A8 <"shr", 0xC1, MRMS5r >; // R32 >>= imm32
349 def SARrr8 : I2A8 <"sar", 0xD2, MRMS7r > , UsesCL; // R8 >>>= cl
350 def SARrr16 : I2A8 <"sar", 0xD3, MRMS7r >, OpSize, UsesCL; // R16 >>>= cl
351 def SARrr32 : I2A8 <"sar", 0xD3, MRMS7r > , UsesCL; // R32 >>>= cl
352 def SARir8 : I2A8 <"sar", 0xC0, MRMS7r >; // R8 >>>= imm8
353 def SARir16 : I2A8 <"sar", 0xC1, MRMS7r >, OpSize; // R16 >>>= imm16
354 def SARir32 : I2A8 <"sar", 0xC1, MRMS7r >; // R32 >>>= imm32
356 def SHLDrr32 : I2A8 <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl
357 def SHLDir32 : I2A8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8
358 def SHRDrr32 : I2A8 <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl
359 def SHRDir32 : I2A8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8
361 // Condition code ops, incl. set if equal/not equal/...
362 def SAHF : X86Inst<"sahf" , 0x9E, RawFrm, Arg8>, Imp<[AH],[]>; // flags = AH
363 def SETBr : X86Inst<"setb" , 0x92, MRMS0r, Arg8>, TB; // R8 = < unsign
364 def SETAEr : X86Inst<"setae", 0x93, MRMS0r, Arg8>, TB; // R8 = >= unsign
365 def SETEr : X86Inst<"sete" , 0x94, MRMS0r, Arg8>, TB; // R8 = ==
366 def SETNEr : X86Inst<"setne", 0x95, MRMS0r, Arg8>, TB; // R8 = !=
367 def SETBEr : X86Inst<"setbe", 0x96, MRMS0r, Arg8>, TB; // R8 = <= unsign
368 def SETAr : X86Inst<"seta" , 0x97, MRMS0r, Arg8>, TB; // R8 = > signed
369 def SETSr : X86Inst<"sets" , 0x98, MRMS0r, Arg8>, TB; // R8 = <sign bit>
370 def SETNSr : X86Inst<"setns", 0x99, MRMS0r, Arg8>, TB; // R8 = !<sign bit>
371 def SETLr : X86Inst<"setl" , 0x9C, MRMS0r, Arg8>, TB; // R8 = < signed
372 def SETGEr : X86Inst<"setge", 0x9D, MRMS0r, Arg8>, TB; // R8 = >= signed
373 def SETLEr : X86Inst<"setle", 0x9E, MRMS0r, Arg8>, TB; // R8 = <= signed
374 def SETGr : X86Inst<"setg" , 0x9F, MRMS0r, Arg8>, TB; // R8 = < signed
376 // Conditional moves. These are modelled as X = cmovXX Y, Z. Eventually
377 // register allocated to cmovXX XY, Z
378 def CMOVErr16 : I2A16<"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R16 = R16
379 def CMOVNErr32: I2A32<"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32
381 // Integer comparisons
382 def CMPrr8 : X86Inst<"cmp", 0x38, MRMDestReg, Arg8 >; // compare R8, R8
383 def CMPrr16 : X86Inst<"cmp", 0x39, MRMDestReg, Arg16>, OpSize; // compare R16, R16
384 def CMPrr32 : X86Inst<"cmp", 0x39, MRMDestReg, Arg32>, // compare R32, R32
385 Pattern<(isVoid (unspec2 R32, R32))>;
386 def CMPri8 : X86Inst<"cmp", 0x80, MRMS7r , Arg8 >; // compare R8, imm8
387 def CMPri16 : X86Inst<"cmp", 0x81, MRMS7r , Arg16>, OpSize; // compare R16, imm16
388 def CMPri32 : X86Inst<"cmp", 0x81, MRMS7r , Arg32>; // compare R32, imm32
390 // Sign/Zero extenders
391 def MOVSXr16r8 : X86Inst<"movsx", 0xBE, MRMSrcReg, Arg8>, TB, OpSize; // R16 = signext(R8)
392 def MOVSXr32r8 : X86Inst<"movsx", 0xBE, MRMSrcReg, Arg8>, TB; // R32 = signext(R8)
393 def MOVSXr32r16: X86Inst<"movsx", 0xBF, MRMSrcReg, Arg8>, TB; // R32 = signext(R16)
394 def MOVZXr16r8 : X86Inst<"movzx", 0xB6, MRMSrcReg, Arg8>, TB, OpSize; // R16 = zeroext(R8)
395 def MOVZXr32r8 : X86Inst<"movzx", 0xB6, MRMSrcReg, Arg8>, TB; // R32 = zeroext(R8)
396 def MOVZXr32r16: X86Inst<"movzx", 0xB7, MRMSrcReg, Arg8>, TB; // R32 = zeroext(R16)
399 //===----------------------------------------------------------------------===//
400 // Floating point support
401 //===----------------------------------------------------------------------===//
403 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
405 // Floating point pseudo instructions...
406 class FPInst<string n, bits<8> o, Format F, ArgType t, FPFormat fp>
407 : X86Inst<n, o, F, t> { let FPForm = fp; let FPFormBits = FPForm.Value; }
409 // Pseudo instructions for floating point. We use these pseudo instructions
410 // because they can be expanded by the fp spackifier into one of many different
411 // forms of instructions for doing these operations. Until the stackifier runs,
412 // we prefer to be abstract.
413 def FpMOV : FPInst<"FMOV", 0, Pseudo, ArgF80, SpecialFP>; // f1 = fmov f2
414 def FpADD : FPInst<"FADD", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fadd f2, f3
415 def FpSUB : FPInst<"FSUB", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fsub f2, f3
416 def FpMUL : FPInst<"FMUL", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fmul f2, f3
417 def FpDIV : FPInst<"FDIV", 0, Pseudo, ArgF80, TwoArgFP>; // f1 = fdiv f2, f3
419 def FpUCOM : FPInst<"FUCOM", 0, Pseudo, ArgF80, TwoArgFP>; // FPSW = fucom f1, f2
421 def FpGETRESULT : FPInst<"FGETRESULT",0, Pseudo, ArgF80, SpecialFP>; // FPR = ST(0)
423 def FpSETRESULT : FPInst<"FSETRESULT",0, Pseudo, ArgF80, SpecialFP>; // ST(0) = FPR
425 // Floating point loads & stores...
426 def FLDrr : FPInst<"fld" , 0xC0, AddRegFrm, ArgF80, NotFP>, D9; // push(ST(i))
427 def FLDr32 : FPInst<"fld" , 0xD9, MRMS0m , ArgF32, ZeroArgFP>; // load float
428 def FLDr64 : FPInst<"fld" , 0xDD, MRMS0m , ArgF64, ZeroArgFP>; // load double
429 def FLDr80 : FPInst<"fld" , 0xDB, MRMS5m , ArgF80, ZeroArgFP>; // load extended
430 def FILDr16 : FPInst<"fild" , 0xDF, MRMS0m , Arg16 , ZeroArgFP>; // load signed short
431 def FILDr32 : FPInst<"fild" , 0xDB, MRMS0m , Arg32 , ZeroArgFP>; // load signed int
432 def FILDr64 : FPInst<"fild" , 0xDF, MRMS5m , Arg64 , ZeroArgFP>; // load signed long
434 def FSTr32 : FPInst<"fst" , 0xD9, MRMS2m , ArgF32, OneArgFP>; // store float
435 def FSTr64 : FPInst<"fst" , 0xDD, MRMS2m , ArgF64, OneArgFP>; // store double
436 def FSTPr32 : FPInst<"fstp", 0xD9, MRMS3m , ArgF32, OneArgFP>; // store float, pop
437 def FSTPr64 : FPInst<"fstp", 0xDD, MRMS3m , ArgF64, OneArgFP>; // store double, pop
438 def FSTPr80 : FPInst<"fstp", 0xDB, MRMS7m , ArgF80, OneArgFP>; // store extended, pop
439 def FSTrr : FPInst<"fst" , 0xD0, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0)
440 def FSTPrr : FPInst<"fstp", 0xD8, AddRegFrm, ArgF80, NotFP >, DD; // ST(i) = ST(0), pop
442 def FISTr16 : FPInst<"fist", 0xDF, MRMS2m, Arg16 , OneArgFP>; // store signed short
443 def FISTr32 : FPInst<"fist", 0xDB, MRMS2m, Arg32 , OneArgFP>; // store signed int
444 def FISTPr16 : FPInst<"fistp", 0xDF, MRMS3m, Arg16 , NotFP >; // store signed short, pop
445 def FISTPr32 : FPInst<"fistp", 0xDB, MRMS3m, Arg32 , NotFP >; // store signed int, pop
446 def FISTPr64 : FPInst<"fistpll", 0xDF, MRMS7m, Arg64 , OneArgFP>; // store signed long, pop
448 def FXCH : FPInst<"fxch", 0xC8, AddRegFrm, ArgF80, NotFP>, D9; // fxch ST(i), ST(0)
450 // Floating point constant loads...
451 def FLD0 : FPInst<"fldz", 0xEE, RawFrm, ArgF80, ZeroArgFP>, D9;
452 def FLD1 : FPInst<"fld1", 0xE8, RawFrm, ArgF80, ZeroArgFP>, D9;
455 // Unary operations...
456 def FCHS : FPInst<"fchs", 0xE0, RawFrm, ArgF80, OneArgFPRW>, D9; // f1 = fchs f2
458 def FTST : FPInst<"ftst", 0xE4, RawFrm, ArgF80, OneArgFP>, D9; // ftst ST(0)
460 // Binary arithmetic operations...
461 class FPST0rInst<string n, bits<8> o>
462 : X86Inst<n, o, AddRegFrm, ArgF80>, D8 {
463 list<Register> Uses = [ST0];
464 list<Register> Defs = [ST0];
466 class FPrST0Inst<string n, bits<8> o>
467 : X86Inst<n, o, AddRegFrm, ArgF80>, DC {
468 bit printImplicitUses = 1;
469 list<Register> Uses = [ST0];
471 class FPrST0PInst<string n, bits<8> o>
472 : X86Inst<n, o, AddRegFrm, ArgF80>, DE {
473 list<Register> Uses = [ST0];
476 def FADDST0r : FPST0rInst <"fadd", 0xC0>;
477 def FADDrST0 : FPrST0Inst <"fadd", 0xC0>;
478 def FADDPrST0 : FPrST0PInst<"faddp", 0xC0>;
480 def FSUBRST0r : FPST0rInst <"fsubr", 0xE8>;
481 def FSUBrST0 : FPrST0Inst <"fsub", 0xE8>;
482 def FSUBPrST0 : FPrST0PInst<"fsubp", 0xE8>;
484 def FSUBST0r : FPST0rInst <"fsub", 0xE0>;
485 def FSUBRrST0 : FPrST0Inst <"fsubr", 0xE0>;
486 def FSUBRPrST0 : FPrST0PInst<"fsubrp", 0xE0>;
488 def FMULST0r : FPST0rInst <"fmul", 0xC8>;
489 def FMULrST0 : FPrST0Inst <"fmul", 0xC8>;
490 def FMULPrST0 : FPrST0PInst<"fmulp", 0xC8>;
492 def FDIVRST0r : FPST0rInst <"fdivr", 0xF8>;
493 def FDIVrST0 : FPrST0Inst <"fdiv", 0xF8>;
494 def FDIVPrST0 : FPrST0PInst<"fdivp", 0xF8>;
496 def FDIVST0r : FPST0rInst <"fdiv", 0xF0>; // ST(0) = ST(0) / ST(i)
497 def FDIVRrST0 : FPrST0Inst <"fdivr", 0xF0>; // ST(i) = ST(0) / ST(i)
498 def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop
500 // Floating point compares
501 def FUCOMr : X86Inst<"fucom" , 0xE0, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
502 def FUCOMPr : X86Inst<"fucomp" , 0xE8, AddRegFrm, ArgF80>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
503 def FUCOMPPr : X86Inst<"fucompp", 0xE9, RawFrm , ArgF80>, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
505 // Floating point flag ops
506 def FNSTSWr8 : X86Inst<"fnstsw" , 0xE0, RawFrm , ArgF80>, DF, Imp<[],[AX]>; // AX = fp flags
507 def FNSTCWm16 : X86Inst<"fnstcw" , 0xD9, MRMS7m , Arg16 >; // [mem16] = X87 control world
508 def FLDCWm16 : X86Inst<"fldcw" , 0xD9, MRMS5m , Arg16 >; // X87 control world = [mem16]
511 //===----------------------------------------------------------------------===//
512 // Instruction Expanders
515 def RET_R32 : Expander<(ret R32:$reg),
516 [(MOVrr32 EAX, R32:$reg),
519 // FIXME: This should eventually just be implemented by defining a frameidx as a
520 // value address for a load.
521 def LOAD_FI16 : Expander<(set R16:$dest, (load frameidx:$fi)),
522 [(MOVmr16 R16:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>;
524 def LOAD_FI32 : Expander<(set R32:$dest, (load frameidx:$fi)),
525 [(MOVmr32 R32:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>;
528 def LOAD_R16 : Expander<(set R16:$dest, (load R32:$src)),
529 [(MOVmr16 R16:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>;
531 def LOAD_R32 : Expander<(set R32:$dest, (load R32:$src)),
532 [(MOVmr32 R32:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>;
534 def BR_EQ : Expander<(brcond (seteq R32:$a1, R32:$a2),
535 basicblock:$d1, basicblock:$d2),
536 [(CMPrr32 R32:$a1, R32:$a2),
538 (JMP basicblock:$d2)]>;