3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
44 def SDTX86SetCC_C : SDTypeProfile<1, 2,
46 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
48 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
50 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
52 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
53 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
54 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
56 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
57 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
60 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
62 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
66 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
68 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
70 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
72 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
74 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
76 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
78 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
80 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
81 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
82 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
83 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
85 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
140 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
141 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
142 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
143 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
146 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
147 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
149 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
150 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
152 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
153 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
154 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
155 SDT_X86SegmentBaseAddress, []>;
157 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
160 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
161 [SDNPHasChain, SDNPOptInFlag]>;
163 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
165 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
166 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
168 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
170 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
171 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
172 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
174 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
176 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
179 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
181 //===----------------------------------------------------------------------===//
182 // X86 Operand Definitions.
185 def i32imm_pcrel : Operand<i32> {
186 let PrintMethod = "print_pcrel_imm";
189 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
190 // the index operand of an address, to conform to x86 encoding restrictions.
191 def ptr_rc_nosp : PointerLikeRegClass<1>;
193 // *mem - Operand definitions for the funky X86 addressing mode operands.
195 def X86MemAsmOperand : AsmOperandClass {
199 class X86MemOperand<string printMethod> : Operand<iPTR> {
200 let PrintMethod = printMethod;
201 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
202 let ParserMatchClass = X86MemAsmOperand;
205 def opaque32mem : X86MemOperand<"printopaquemem">;
206 def opaque48mem : X86MemOperand<"printopaquemem">;
207 def opaque80mem : X86MemOperand<"printopaquemem">;
208 def opaque512mem : X86MemOperand<"printopaquemem">;
210 def offset8 : Operand<i64> { let PrintMethod = "print_pcrel_imm"; }
211 def offset16 : Operand<i64> { let PrintMethod = "print_pcrel_imm"; }
212 def offset32 : Operand<i64> { let PrintMethod = "print_pcrel_imm"; }
213 def offset64 : Operand<i64> { let PrintMethod = "print_pcrel_imm"; }
215 def i8mem : X86MemOperand<"printi8mem">;
216 def i16mem : X86MemOperand<"printi16mem">;
217 def i32mem : X86MemOperand<"printi32mem">;
218 def i64mem : X86MemOperand<"printi64mem">;
219 def i128mem : X86MemOperand<"printi128mem">;
220 //def i256mem : X86MemOperand<"printi256mem">;
221 def f32mem : X86MemOperand<"printf32mem">;
222 def f64mem : X86MemOperand<"printf64mem">;
223 def f80mem : X86MemOperand<"printf80mem">;
224 def f128mem : X86MemOperand<"printf128mem">;
225 //def f256mem : X86MemOperand<"printf256mem">;
227 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
228 // plain GR64, so that it doesn't potentially require a REX prefix.
229 def i8mem_NOREX : Operand<i64> {
230 let PrintMethod = "printi8mem";
231 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
232 let ParserMatchClass = X86MemAsmOperand;
235 def lea32mem : Operand<i32> {
236 let PrintMethod = "printlea32mem";
237 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
238 let ParserMatchClass = X86MemAsmOperand;
241 def SSECC : Operand<i8> {
242 let PrintMethod = "printSSECC";
245 def ImmSExt8AsmOperand : AsmOperandClass {
246 let Name = "ImmSExt8";
247 let SuperClass = ImmAsmOperand;
250 // A couple of more descriptive operand definitions.
251 // 16-bits but only 8 bits are significant.
252 def i16i8imm : Operand<i16> {
253 let ParserMatchClass = ImmSExt8AsmOperand;
255 // 32-bits but only 8 bits are significant.
256 def i32i8imm : Operand<i32> {
257 let ParserMatchClass = ImmSExt8AsmOperand;
260 // Branch targets have OtherVT type and print as pc-relative values.
261 def brtarget : Operand<OtherVT> {
262 let PrintMethod = "print_pcrel_imm";
265 def brtarget8 : Operand<OtherVT> {
266 let PrintMethod = "print_pcrel_imm";
269 //===----------------------------------------------------------------------===//
270 // X86 Complex Pattern Definitions.
273 // Define X86 specific addressing mode.
274 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
275 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
276 [add, sub, mul, X86mul_imm, shl, or, frameindex],
278 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
279 [tglobaltlsaddr], []>;
281 //===----------------------------------------------------------------------===//
282 // X86 Instruction Predicate Definitions.
283 def HasMMX : Predicate<"Subtarget->hasMMX()">;
284 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
285 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
286 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
287 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
288 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
289 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
290 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
291 def HasAVX : Predicate<"Subtarget->hasAVX()">;
292 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
293 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
294 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
295 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
296 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
297 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
298 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
299 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
300 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
301 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
302 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
303 "TM.getCodeModel() != CodeModel::Kernel">;
304 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
305 "TM.getCodeModel() == CodeModel::Kernel">;
306 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
307 def OptForSize : Predicate<"OptForSize">;
308 def OptForSpeed : Predicate<"!OptForSize">;
309 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
310 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
312 //===----------------------------------------------------------------------===//
313 // X86 Instruction Format Definitions.
316 include "X86InstrFormats.td"
318 //===----------------------------------------------------------------------===//
319 // Pattern fragments...
322 // X86 specific condition code. These correspond to CondCode in
323 // X86InstrInfo.h. They must be kept in synch.
324 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
325 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
326 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
327 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
328 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
329 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
330 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
331 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
332 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
333 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
334 def X86_COND_NO : PatLeaf<(i8 10)>;
335 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
336 def X86_COND_NS : PatLeaf<(i8 12)>;
337 def X86_COND_O : PatLeaf<(i8 13)>;
338 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
339 def X86_COND_S : PatLeaf<(i8 15)>;
341 def i16immSExt8 : PatLeaf<(i16 imm), [{
342 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
343 // sign extended field.
344 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
347 def i32immSExt8 : PatLeaf<(i32 imm), [{
348 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
349 // sign extended field.
350 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
353 // Helper fragments for loads.
354 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
355 // known to be 32-bit aligned or better. Ditto for i8 to i16.
356 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
357 LoadSDNode *LD = cast<LoadSDNode>(N);
358 if (const Value *Src = LD->getSrcValue())
359 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
360 if (PT->getAddressSpace() > 255)
362 ISD::LoadExtType ExtType = LD->getExtensionType();
363 if (ExtType == ISD::NON_EXTLOAD)
365 if (ExtType == ISD::EXTLOAD)
366 return LD->getAlignment() >= 2 && !LD->isVolatile();
370 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),
372 LoadSDNode *LD = cast<LoadSDNode>(N);
373 if (const Value *Src = LD->getSrcValue())
374 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
375 if (PT->getAddressSpace() > 255)
377 ISD::LoadExtType ExtType = LD->getExtensionType();
378 if (ExtType == ISD::EXTLOAD)
379 return LD->getAlignment() >= 2 && !LD->isVolatile();
383 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
384 LoadSDNode *LD = cast<LoadSDNode>(N);
385 if (const Value *Src = LD->getSrcValue())
386 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
387 if (PT->getAddressSpace() > 255)
389 ISD::LoadExtType ExtType = LD->getExtensionType();
390 if (ExtType == ISD::NON_EXTLOAD)
392 if (ExtType == ISD::EXTLOAD)
393 return LD->getAlignment() >= 4 && !LD->isVolatile();
397 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
398 LoadSDNode *LD = cast<LoadSDNode>(N);
399 if (const Value *Src = LD->getSrcValue())
400 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
401 if (PT->getAddressSpace() > 255)
403 if (LD->isVolatile())
405 ISD::LoadExtType ExtType = LD->getExtensionType();
406 if (ExtType == ISD::NON_EXTLOAD)
408 if (ExtType == ISD::EXTLOAD)
409 return LD->getAlignment() >= 4;
413 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
414 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
415 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
416 return PT->getAddressSpace() == 256;
420 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
421 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
422 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
423 return PT->getAddressSpace() == 257;
427 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
428 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
429 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
430 if (PT->getAddressSpace() > 255)
434 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
435 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
436 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
437 if (PT->getAddressSpace() > 255)
442 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
443 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
444 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
445 if (PT->getAddressSpace() > 255)
449 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
450 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
451 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
452 if (PT->getAddressSpace() > 255)
456 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
457 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
458 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
459 if (PT->getAddressSpace() > 255)
464 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
465 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
466 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
468 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
469 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
470 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
471 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
472 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
473 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
475 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
476 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
477 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
478 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
479 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
480 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
483 // An 'and' node with a single use.
484 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
485 return N->hasOneUse();
487 // An 'srl' node with a single use.
488 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
489 return N->hasOneUse();
491 // An 'trunc' node with a single use.
492 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
493 return N->hasOneUse();
496 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
497 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
498 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
499 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
502 def or_not_add : PatFrag<(ops node:$lhs, node:$rhs),(or node:$lhs, node:$rhs),[{
503 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1));
504 if (!CN) return true;
505 return !CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
508 // 'shld' and 'shrd' instruction patterns. Note that even though these have
509 // the srl and shl in their patterns, the C++ code must still check for them,
510 // because predicates are tested before children nodes are explored.
512 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
513 (or (srl node:$src1, node:$amt1),
514 (shl node:$src2, node:$amt2)), [{
515 assert(N->getOpcode() == ISD::OR);
516 return N->getOperand(0).getOpcode() == ISD::SRL &&
517 N->getOperand(1).getOpcode() == ISD::SHL &&
518 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
519 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
520 N->getOperand(0).getConstantOperandVal(1) ==
521 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
524 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
525 (or (shl node:$src1, node:$amt1),
526 (srl node:$src2, node:$amt2)), [{
527 assert(N->getOpcode() == ISD::OR);
528 return N->getOperand(0).getOpcode() == ISD::SHL &&
529 N->getOperand(1).getOpcode() == ISD::SRL &&
530 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
531 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
532 N->getOperand(0).getConstantOperandVal(1) ==
533 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
536 //===----------------------------------------------------------------------===//
537 // Instruction list...
540 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
541 // a stack adjustment and the codegen must know that they may modify the stack
542 // pointer before prolog-epilog rewriting occurs.
543 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
544 // sub / add which can clobber EFLAGS.
545 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
546 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
548 [(X86callseq_start timm:$amt)]>,
549 Requires<[In32BitMode]>;
550 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
552 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
553 Requires<[In32BitMode]>;
556 // x86-64 va_start lowering magic.
557 let usesCustomInserter = 1 in
558 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
561 i64imm:$regsavefi, i64imm:$offset,
563 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
564 [(X86vastart_save_xmm_regs GR8:$al,
569 let neverHasSideEffects = 1 in {
570 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
571 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
572 "nop{w}\t$zero", []>, TB, OpSize;
573 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
574 "nop{l}\t$zero", []>, TB;
578 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
579 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
580 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
581 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
583 // PIC base construction. This expands to code that looks like this:
586 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
587 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
590 //===----------------------------------------------------------------------===//
591 // Control Flow Instructions...
594 // Return instructions.
595 let isTerminator = 1, isReturn = 1, isBarrier = 1,
596 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
597 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
600 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
602 [(X86retflag timm:$amt)]>;
603 def LRET : I <0xCB, RawFrm, (outs), (ins),
605 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
609 // All branches are RawFrm, Void, Branch, and Terminators
610 let isBranch = 1, isTerminator = 1 in
611 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
612 I<opcode, RawFrm, (outs), ins, asm, pattern>;
614 let isBranch = 1, isBarrier = 1 in {
615 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
616 def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
620 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
621 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
622 [(brind GR32:$dst)]>;
623 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
624 [(brind (loadi32 addr:$dst))]>;
626 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
627 (ins i16imm:$seg, i16imm:$off),
628 "ljmp{w}\t$seg, $off", []>, OpSize;
629 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
630 (ins i16imm:$seg, i32imm:$off),
631 "ljmp{l}\t$seg, $off", []>;
633 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
634 "ljmp{w}\t{*}$dst", []>, OpSize;
635 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
636 "ljmp{l}\t{*}$dst", []>;
639 // Conditional branches
640 let Uses = [EFLAGS] in {
641 // Short conditional jumps
642 def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>;
643 def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>;
644 def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>;
645 def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>;
646 def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>;
647 def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>;
648 def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>;
649 def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>;
650 def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>;
651 def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>;
652 def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>;
653 def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>;
654 def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>;
655 def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>;
656 def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>;
657 def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>;
659 def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
661 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
662 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
663 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
664 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
665 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
666 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
667 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
668 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
669 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
670 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
671 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
672 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
674 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
675 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
676 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
677 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
678 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
679 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
680 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
681 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
683 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
684 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
685 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
686 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
687 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
688 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
689 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
690 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
691 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
692 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
693 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
694 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
699 def LOOP : I<0xE2, RawFrm, (ins brtarget8:$dst), (outs), "loop\t$dst", []>;
700 def LOOPE : I<0xE1, RawFrm, (ins brtarget8:$dst), (outs), "loope\t$dst", []>;
701 def LOOPNE : I<0xE0, RawFrm, (ins brtarget8:$dst), (outs), "loopne\t$dst", []>;
703 //===----------------------------------------------------------------------===//
704 // Call Instructions...
707 // All calls clobber the non-callee saved registers. ESP is marked as
708 // a use to prevent stack-pointer assignments that appear immediately
709 // before calls from potentially appearing dead. Uses for argument
710 // registers are added manually.
711 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
712 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
713 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
714 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
716 def CALLpcrel32 : Ii32<0xE8, RawFrm,
717 (outs), (ins i32imm_pcrel:$dst,variable_ops),
719 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
720 "call\t{*}$dst", [(X86call GR32:$dst)]>;
721 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
722 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
724 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
725 (ins i16imm:$seg, i16imm:$off),
726 "lcall{w}\t$seg, $off", []>, OpSize;
727 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
728 (ins i16imm:$seg, i32imm:$off),
729 "lcall{l}\t$seg, $off", []>;
731 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
732 "lcall{w}\t{*}$dst", []>, OpSize;
733 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
734 "lcall{l}\t{*}$dst", []>;
737 // Constructing a stack frame.
739 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
740 "enter\t$len, $lvl", []>;
744 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
745 def TCRETURNdi : I<0, Pseudo, (outs),
746 (ins i32imm:$dst, i32imm:$offset, variable_ops),
747 "#TC_RETURN $dst $offset",
750 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
751 def TCRETURNri : I<0, Pseudo, (outs),
752 (ins GR32:$dst, i32imm:$offset, variable_ops),
753 "#TC_RETURN $dst $offset",
756 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
757 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL",
759 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
760 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst),
761 "jmp{l}\t{*}$dst # TAILCALL",
763 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
764 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
765 "jmp\t{*}$dst # TAILCALL", []>;
767 //===----------------------------------------------------------------------===//
768 // Miscellaneous Instructions...
770 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
771 def LEAVE : I<0xC9, RawFrm,
772 (outs), (ins), "leave", []>;
774 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
775 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
776 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
777 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
778 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
779 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
780 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
781 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
783 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
785 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
787 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
788 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
790 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
792 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
793 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
796 let mayStore = 1 in {
797 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
799 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
800 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
802 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
804 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
805 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
809 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
810 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
811 "push{l}\t$imm", []>;
812 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
813 "push{l}\t$imm", []>;
814 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
815 "push{l}\t$imm", []>;
818 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
819 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
820 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
822 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
823 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
824 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
827 let isTwoAddress = 1 in // GR32 = bswap GR32
828 def BSWAP32r : I<0xC8, AddRegFrm,
829 (outs GR32:$dst), (ins GR32:$src),
831 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
834 // Bit scan instructions.
835 let Defs = [EFLAGS] in {
836 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
837 "bsf{w}\t{$src, $dst|$dst, $src}",
838 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
839 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
840 "bsf{w}\t{$src, $dst|$dst, $src}",
841 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
842 (implicit EFLAGS)]>, TB;
843 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
844 "bsf{l}\t{$src, $dst|$dst, $src}",
845 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
846 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
847 "bsf{l}\t{$src, $dst|$dst, $src}",
848 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
849 (implicit EFLAGS)]>, TB;
851 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
852 "bsr{w}\t{$src, $dst|$dst, $src}",
853 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
854 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
855 "bsr{w}\t{$src, $dst|$dst, $src}",
856 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
857 (implicit EFLAGS)]>, TB;
858 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
859 "bsr{l}\t{$src, $dst|$dst, $src}",
860 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
861 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
862 "bsr{l}\t{$src, $dst|$dst, $src}",
863 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
864 (implicit EFLAGS)]>, TB;
867 let neverHasSideEffects = 1 in
868 def LEA16r : I<0x8D, MRMSrcMem,
869 (outs GR16:$dst), (ins lea32mem:$src),
870 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
871 let isReMaterializable = 1 in
872 def LEA32r : I<0x8D, MRMSrcMem,
873 (outs GR32:$dst), (ins lea32mem:$src),
874 "lea{l}\t{$src|$dst}, {$dst|$src}",
875 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
877 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
878 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
879 [(X86rep_movs i8)]>, REP;
880 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
881 [(X86rep_movs i16)]>, REP, OpSize;
882 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
883 [(X86rep_movs i32)]>, REP;
886 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
887 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
888 [(X86rep_stos i8)]>, REP;
889 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
890 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
891 [(X86rep_stos i16)]>, REP, OpSize;
892 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
893 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
894 [(X86rep_stos i32)]>, REP;
896 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
897 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
898 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
900 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
901 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
902 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
904 let Defs = [RAX, RDX] in
905 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
908 let isBarrier = 1, hasCtrlDep = 1 in {
909 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
912 def SYSCALL : I<0x05, RawFrm,
913 (outs), (ins), "syscall", []>, TB;
914 def SYSRET : I<0x07, RawFrm,
915 (outs), (ins), "sysret", []>, TB;
916 def SYSENTER : I<0x34, RawFrm,
917 (outs), (ins), "sysenter", []>, TB;
918 def SYSEXIT : I<0x35, RawFrm,
919 (outs), (ins), "sysexit", []>, TB;
921 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
924 //===----------------------------------------------------------------------===//
925 // Input/Output Instructions...
927 let Defs = [AL], Uses = [DX] in
928 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
929 "in{b}\t{%dx, %al|%AL, %DX}", []>;
930 let Defs = [AX], Uses = [DX] in
931 def IN16rr : I<0xED, RawFrm, (outs), (ins),
932 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
933 let Defs = [EAX], Uses = [DX] in
934 def IN32rr : I<0xED, RawFrm, (outs), (ins),
935 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
938 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
939 "in{b}\t{$port, %al|%AL, $port}", []>;
941 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
942 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
944 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
945 "in{l}\t{$port, %eax|%EAX, $port}", []>;
947 let Uses = [DX, AL] in
948 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
949 "out{b}\t{%al, %dx|%DX, %AL}", []>;
950 let Uses = [DX, AX] in
951 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
952 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
953 let Uses = [DX, EAX] in
954 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
955 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
958 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
959 "out{b}\t{%al, $port|$port, %AL}", []>;
961 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
962 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
964 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
965 "out{l}\t{%eax, $port|$port, %EAX}", []>;
967 def IN8 : I<0x6C, RawFrm, (outs), (ins),
969 def IN16 : I<0x6D, RawFrm, (outs), (ins),
970 "ins{w}", []>, OpSize;
971 def IN32 : I<0x6D, RawFrm, (outs), (ins),
974 //===----------------------------------------------------------------------===//
975 // Move Instructions...
977 let neverHasSideEffects = 1 in {
978 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
979 "mov{b}\t{$src, $dst|$dst, $src}", []>;
980 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
981 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
982 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
983 "mov{l}\t{$src, $dst|$dst, $src}", []>;
985 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
986 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
987 "mov{b}\t{$src, $dst|$dst, $src}",
988 [(set GR8:$dst, imm:$src)]>;
989 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
990 "mov{w}\t{$src, $dst|$dst, $src}",
991 [(set GR16:$dst, imm:$src)]>, OpSize;
992 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
993 "mov{l}\t{$src, $dst|$dst, $src}",
994 [(set GR32:$dst, imm:$src)]>;
996 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
997 "mov{b}\t{$src, $dst|$dst, $src}",
998 [(store (i8 imm:$src), addr:$dst)]>;
999 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1000 "mov{w}\t{$src, $dst|$dst, $src}",
1001 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
1002 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1003 "mov{l}\t{$src, $dst|$dst, $src}",
1004 [(store (i32 imm:$src), addr:$dst)]>;
1006 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src),
1007 "mov{b}\t{$src, %al|%al, $src}", []>;
1008 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
1009 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1010 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1011 "mov{l}\t{$src, %eax|%eax, $src}", []>;
1013 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1014 "mov{b}\t{%al, $dst|$dst, %al}", []>;
1015 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1016 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
1017 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1018 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
1020 // Moves to and from segment registers
1021 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1022 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1023 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1024 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1025 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1026 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1027 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1028 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1030 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1031 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1032 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1033 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1034 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1035 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1037 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
1038 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1039 "mov{b}\t{$src, $dst|$dst, $src}",
1040 [(set GR8:$dst, (loadi8 addr:$src))]>;
1041 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1042 "mov{w}\t{$src, $dst|$dst, $src}",
1043 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1044 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1045 "mov{l}\t{$src, $dst|$dst, $src}",
1046 [(set GR32:$dst, (loadi32 addr:$src))]>;
1049 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1050 "mov{b}\t{$src, $dst|$dst, $src}",
1051 [(store GR8:$src, addr:$dst)]>;
1052 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1053 "mov{w}\t{$src, $dst|$dst, $src}",
1054 [(store GR16:$src, addr:$dst)]>, OpSize;
1055 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1056 "mov{l}\t{$src, $dst|$dst, $src}",
1057 [(store GR32:$src, addr:$dst)]>;
1059 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1060 // that they can be used for copying and storing h registers, which can't be
1061 // encoded when a REX prefix is present.
1062 let neverHasSideEffects = 1 in
1063 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1064 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1065 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1067 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1068 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1069 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1071 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1072 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1073 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1074 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1076 // Moves to and from debug registers
1077 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1078 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1079 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1080 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1082 // Moves to and from control registers
1083 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
1084 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1085 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
1086 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1088 //===----------------------------------------------------------------------===//
1089 // Fixed-Register Multiplication and Division Instructions...
1092 // Extra precision multiplication
1093 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1094 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1095 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1096 // This probably ought to be moved to a def : Pat<> if the
1097 // syntax can be accepted.
1098 [(set AL, (mul AL, GR8:$src)),
1099 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1101 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1102 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1104 []>, OpSize; // AX,DX = AX*GR16
1106 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1107 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1109 []>; // EAX,EDX = EAX*GR32
1111 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1112 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1114 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1115 // This probably ought to be moved to a def : Pat<> if the
1116 // syntax can be accepted.
1117 [(set AL, (mul AL, (loadi8 addr:$src))),
1118 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1120 let mayLoad = 1, neverHasSideEffects = 1 in {
1121 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1122 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1124 []>, OpSize; // AX,DX = AX*[mem16]
1126 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1127 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1129 []>; // EAX,EDX = EAX*[mem32]
1132 let neverHasSideEffects = 1 in {
1133 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1134 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1136 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1137 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1138 OpSize; // AX,DX = AX*GR16
1139 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1140 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1141 // EAX,EDX = EAX*GR32
1142 let mayLoad = 1 in {
1143 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1144 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1145 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1146 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1147 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1148 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1149 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1150 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1151 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1153 } // neverHasSideEffects
1155 // unsigned division/remainder
1156 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1157 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1158 "div{b}\t$src", []>;
1159 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1160 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1161 "div{w}\t$src", []>, OpSize;
1162 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1163 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1164 "div{l}\t$src", []>;
1165 let mayLoad = 1 in {
1166 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1167 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1168 "div{b}\t$src", []>;
1169 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1170 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1171 "div{w}\t$src", []>, OpSize;
1172 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1173 // EDX:EAX/[mem32] = EAX,EDX
1174 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1175 "div{l}\t$src", []>;
1178 // Signed division/remainder.
1179 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1180 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1181 "idiv{b}\t$src", []>;
1182 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1183 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1184 "idiv{w}\t$src", []>, OpSize;
1185 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1186 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1187 "idiv{l}\t$src", []>;
1188 let mayLoad = 1, mayLoad = 1 in {
1189 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1190 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1191 "idiv{b}\t$src", []>;
1192 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1193 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1194 "idiv{w}\t$src", []>, OpSize;
1195 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1196 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1197 // EDX:EAX/[mem32] = EAX,EDX
1198 "idiv{l}\t$src", []>;
1201 //===----------------------------------------------------------------------===//
1202 // Two address Instructions.
1204 let isTwoAddress = 1 in {
1206 // Conditional moves
1207 let Uses = [EFLAGS] in {
1209 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1210 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1211 // however that requires promoting the operands, and can induce additional
1212 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1213 // clobber EFLAGS, because if one of the operands is zero, the expansion
1214 // could involve an xor.
1215 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
1216 def CMOV_GR8 : I<0, Pseudo,
1217 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1218 "#CMOV_GR8 PSEUDO!",
1219 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1220 imm:$cond, EFLAGS))]>;
1222 let isCommutable = 1 in {
1223 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1224 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1225 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1226 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1227 X86_COND_B, EFLAGS))]>,
1229 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1230 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1231 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1232 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1233 X86_COND_B, EFLAGS))]>,
1235 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1236 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1237 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1238 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1239 X86_COND_AE, EFLAGS))]>,
1241 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1242 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1243 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1244 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1245 X86_COND_AE, EFLAGS))]>,
1247 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1248 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1249 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1250 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1251 X86_COND_E, EFLAGS))]>,
1253 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1254 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1255 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1256 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1257 X86_COND_E, EFLAGS))]>,
1259 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1260 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1261 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1262 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1263 X86_COND_NE, EFLAGS))]>,
1265 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1266 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1267 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1268 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1269 X86_COND_NE, EFLAGS))]>,
1271 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1272 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1273 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1274 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1275 X86_COND_BE, EFLAGS))]>,
1277 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1278 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1279 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1280 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1281 X86_COND_BE, EFLAGS))]>,
1283 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1284 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1285 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1286 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1287 X86_COND_A, EFLAGS))]>,
1289 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1290 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1291 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1292 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1293 X86_COND_A, EFLAGS))]>,
1295 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1296 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1297 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1298 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1299 X86_COND_L, EFLAGS))]>,
1301 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1302 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1303 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1304 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1305 X86_COND_L, EFLAGS))]>,
1307 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1308 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1309 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1310 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1311 X86_COND_GE, EFLAGS))]>,
1313 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1314 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1315 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1316 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1317 X86_COND_GE, EFLAGS))]>,
1319 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1320 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1321 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1322 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1323 X86_COND_LE, EFLAGS))]>,
1325 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1326 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1327 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1328 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1329 X86_COND_LE, EFLAGS))]>,
1331 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1332 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1333 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1334 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1335 X86_COND_G, EFLAGS))]>,
1337 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1338 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1339 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1340 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1341 X86_COND_G, EFLAGS))]>,
1343 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1344 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1345 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1346 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1347 X86_COND_S, EFLAGS))]>,
1349 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1350 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1351 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1352 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1353 X86_COND_S, EFLAGS))]>,
1355 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1356 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1357 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1358 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1359 X86_COND_NS, EFLAGS))]>,
1361 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1362 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1363 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1364 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1365 X86_COND_NS, EFLAGS))]>,
1367 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1368 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1369 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1370 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1371 X86_COND_P, EFLAGS))]>,
1373 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1374 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1375 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1376 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1377 X86_COND_P, EFLAGS))]>,
1379 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1380 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1381 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1382 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1383 X86_COND_NP, EFLAGS))]>,
1385 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1386 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1387 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1388 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1389 X86_COND_NP, EFLAGS))]>,
1391 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1392 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1393 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1394 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1395 X86_COND_O, EFLAGS))]>,
1397 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1398 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1399 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1400 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1401 X86_COND_O, EFLAGS))]>,
1403 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1404 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1405 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1406 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1407 X86_COND_NO, EFLAGS))]>,
1409 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1410 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1411 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1412 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1413 X86_COND_NO, EFLAGS))]>,
1415 } // isCommutable = 1
1417 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1418 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1419 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1420 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1421 X86_COND_B, EFLAGS))]>,
1423 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1424 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1425 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1426 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1427 X86_COND_B, EFLAGS))]>,
1429 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1430 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1431 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1432 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1433 X86_COND_AE, EFLAGS))]>,
1435 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1436 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1437 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1438 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1439 X86_COND_AE, EFLAGS))]>,
1441 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1442 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1443 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1444 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1445 X86_COND_E, EFLAGS))]>,
1447 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1448 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1449 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1450 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1451 X86_COND_E, EFLAGS))]>,
1453 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1454 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1455 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1456 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1457 X86_COND_NE, EFLAGS))]>,
1459 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1460 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1461 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1462 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1463 X86_COND_NE, EFLAGS))]>,
1465 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1466 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1467 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1468 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1469 X86_COND_BE, EFLAGS))]>,
1471 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1472 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1473 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1474 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1475 X86_COND_BE, EFLAGS))]>,
1477 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1478 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1479 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1480 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1481 X86_COND_A, EFLAGS))]>,
1483 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1484 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1485 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1486 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1487 X86_COND_A, EFLAGS))]>,
1489 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1490 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1491 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1492 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1493 X86_COND_L, EFLAGS))]>,
1495 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1496 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1497 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1498 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1499 X86_COND_L, EFLAGS))]>,
1501 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1502 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1503 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1504 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1505 X86_COND_GE, EFLAGS))]>,
1507 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1508 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1509 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1510 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1511 X86_COND_GE, EFLAGS))]>,
1513 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1514 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1515 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1516 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1517 X86_COND_LE, EFLAGS))]>,
1519 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1520 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1521 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1522 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1523 X86_COND_LE, EFLAGS))]>,
1525 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1526 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1527 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1528 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1529 X86_COND_G, EFLAGS))]>,
1531 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1532 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1533 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1534 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1535 X86_COND_G, EFLAGS))]>,
1537 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1538 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1539 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1540 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1541 X86_COND_S, EFLAGS))]>,
1543 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1544 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1545 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1546 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1547 X86_COND_S, EFLAGS))]>,
1549 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1550 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1551 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1552 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1553 X86_COND_NS, EFLAGS))]>,
1555 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1556 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1557 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1558 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1559 X86_COND_NS, EFLAGS))]>,
1561 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1562 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1563 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1564 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1565 X86_COND_P, EFLAGS))]>,
1567 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1568 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1569 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1570 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1571 X86_COND_P, EFLAGS))]>,
1573 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1574 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1575 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1576 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1577 X86_COND_NP, EFLAGS))]>,
1579 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1580 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1581 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1582 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1583 X86_COND_NP, EFLAGS))]>,
1585 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1586 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1587 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1588 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1589 X86_COND_O, EFLAGS))]>,
1591 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1592 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1593 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1594 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1595 X86_COND_O, EFLAGS))]>,
1597 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1598 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1599 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1600 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1601 X86_COND_NO, EFLAGS))]>,
1603 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1604 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1605 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1606 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1607 X86_COND_NO, EFLAGS))]>,
1609 } // Uses = [EFLAGS]
1612 // unary instructions
1613 let CodeSize = 2 in {
1614 let Defs = [EFLAGS] in {
1615 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1616 [(set GR8:$dst, (ineg GR8:$src)),
1617 (implicit EFLAGS)]>;
1618 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1619 [(set GR16:$dst, (ineg GR16:$src)),
1620 (implicit EFLAGS)]>, OpSize;
1621 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1622 [(set GR32:$dst, (ineg GR32:$src)),
1623 (implicit EFLAGS)]>;
1624 let isTwoAddress = 0 in {
1625 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1626 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1627 (implicit EFLAGS)]>;
1628 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1629 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1630 (implicit EFLAGS)]>, OpSize;
1631 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1632 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1633 (implicit EFLAGS)]>;
1635 } // Defs = [EFLAGS]
1637 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1638 let AddedComplexity = 15 in {
1639 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1640 [(set GR8:$dst, (not GR8:$src))]>;
1641 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1642 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1643 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1644 [(set GR32:$dst, (not GR32:$src))]>;
1646 let isTwoAddress = 0 in {
1647 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1648 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1649 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1650 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1651 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1652 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1656 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1657 let Defs = [EFLAGS] in {
1659 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1660 [(set GR8:$dst, (add GR8:$src, 1)),
1661 (implicit EFLAGS)]>;
1662 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1663 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1665 [(set GR16:$dst, (add GR16:$src, 1)),
1666 (implicit EFLAGS)]>,
1667 OpSize, Requires<[In32BitMode]>;
1668 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1670 [(set GR32:$dst, (add GR32:$src, 1)),
1671 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1673 let isTwoAddress = 0, CodeSize = 2 in {
1674 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1675 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1676 (implicit EFLAGS)]>;
1677 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1678 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1679 (implicit EFLAGS)]>,
1680 OpSize, Requires<[In32BitMode]>;
1681 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1682 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1683 (implicit EFLAGS)]>,
1684 Requires<[In32BitMode]>;
1688 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1689 [(set GR8:$dst, (add GR8:$src, -1)),
1690 (implicit EFLAGS)]>;
1691 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1692 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1694 [(set GR16:$dst, (add GR16:$src, -1)),
1695 (implicit EFLAGS)]>,
1696 OpSize, Requires<[In32BitMode]>;
1697 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1699 [(set GR32:$dst, (add GR32:$src, -1)),
1700 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1703 let isTwoAddress = 0, CodeSize = 2 in {
1704 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1705 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1706 (implicit EFLAGS)]>;
1707 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1708 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1709 (implicit EFLAGS)]>,
1710 OpSize, Requires<[In32BitMode]>;
1711 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1712 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1713 (implicit EFLAGS)]>,
1714 Requires<[In32BitMode]>;
1716 } // Defs = [EFLAGS]
1718 // Logical operators...
1719 let Defs = [EFLAGS] in {
1720 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1721 def AND8rr : I<0x20, MRMDestReg,
1722 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1723 "and{b}\t{$src2, $dst|$dst, $src2}",
1724 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1725 (implicit EFLAGS)]>;
1726 def AND16rr : I<0x21, MRMDestReg,
1727 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1728 "and{w}\t{$src2, $dst|$dst, $src2}",
1729 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1730 (implicit EFLAGS)]>, OpSize;
1731 def AND32rr : I<0x21, MRMDestReg,
1732 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1733 "and{l}\t{$src2, $dst|$dst, $src2}",
1734 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1735 (implicit EFLAGS)]>;
1738 // AND instructions with the destination register in REG and the source register
1739 // in R/M. Included for the disassembler.
1740 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1741 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1742 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1743 (ins GR16:$src1, GR16:$src2),
1744 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1745 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1746 (ins GR32:$src1, GR32:$src2),
1747 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1749 def AND8rm : I<0x22, MRMSrcMem,
1750 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1751 "and{b}\t{$src2, $dst|$dst, $src2}",
1752 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1753 (implicit EFLAGS)]>;
1754 def AND16rm : I<0x23, MRMSrcMem,
1755 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1756 "and{w}\t{$src2, $dst|$dst, $src2}",
1757 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1758 (implicit EFLAGS)]>, OpSize;
1759 def AND32rm : I<0x23, MRMSrcMem,
1760 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1761 "and{l}\t{$src2, $dst|$dst, $src2}",
1762 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1763 (implicit EFLAGS)]>;
1765 def AND8ri : Ii8<0x80, MRM4r,
1766 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1767 "and{b}\t{$src2, $dst|$dst, $src2}",
1768 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1769 (implicit EFLAGS)]>;
1770 def AND16ri : Ii16<0x81, MRM4r,
1771 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1772 "and{w}\t{$src2, $dst|$dst, $src2}",
1773 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1774 (implicit EFLAGS)]>, OpSize;
1775 def AND32ri : Ii32<0x81, MRM4r,
1776 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1777 "and{l}\t{$src2, $dst|$dst, $src2}",
1778 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1779 (implicit EFLAGS)]>;
1780 def AND16ri8 : Ii8<0x83, MRM4r,
1781 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1782 "and{w}\t{$src2, $dst|$dst, $src2}",
1783 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1784 (implicit EFLAGS)]>,
1786 def AND32ri8 : Ii8<0x83, MRM4r,
1787 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1788 "and{l}\t{$src2, $dst|$dst, $src2}",
1789 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1790 (implicit EFLAGS)]>;
1792 let isTwoAddress = 0 in {
1793 def AND8mr : I<0x20, MRMDestMem,
1794 (outs), (ins i8mem :$dst, GR8 :$src),
1795 "and{b}\t{$src, $dst|$dst, $src}",
1796 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1797 (implicit EFLAGS)]>;
1798 def AND16mr : I<0x21, MRMDestMem,
1799 (outs), (ins i16mem:$dst, GR16:$src),
1800 "and{w}\t{$src, $dst|$dst, $src}",
1801 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1802 (implicit EFLAGS)]>,
1804 def AND32mr : I<0x21, MRMDestMem,
1805 (outs), (ins i32mem:$dst, GR32:$src),
1806 "and{l}\t{$src, $dst|$dst, $src}",
1807 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1808 (implicit EFLAGS)]>;
1809 def AND8mi : Ii8<0x80, MRM4m,
1810 (outs), (ins i8mem :$dst, i8imm :$src),
1811 "and{b}\t{$src, $dst|$dst, $src}",
1812 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1813 (implicit EFLAGS)]>;
1814 def AND16mi : Ii16<0x81, MRM4m,
1815 (outs), (ins i16mem:$dst, i16imm:$src),
1816 "and{w}\t{$src, $dst|$dst, $src}",
1817 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1818 (implicit EFLAGS)]>,
1820 def AND32mi : Ii32<0x81, MRM4m,
1821 (outs), (ins i32mem:$dst, i32imm:$src),
1822 "and{l}\t{$src, $dst|$dst, $src}",
1823 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1824 (implicit EFLAGS)]>;
1825 def AND16mi8 : Ii8<0x83, MRM4m,
1826 (outs), (ins i16mem:$dst, i16i8imm :$src),
1827 "and{w}\t{$src, $dst|$dst, $src}",
1828 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1829 (implicit EFLAGS)]>,
1831 def AND32mi8 : Ii8<0x83, MRM4m,
1832 (outs), (ins i32mem:$dst, i32i8imm :$src),
1833 "and{l}\t{$src, $dst|$dst, $src}",
1834 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1835 (implicit EFLAGS)]>;
1837 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1838 "and{b}\t{$src, %al|%al, $src}", []>;
1839 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1840 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1841 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1842 "and{l}\t{$src, %eax|%eax, $src}", []>;
1847 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1848 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1849 (ins GR8 :$src1, GR8 :$src2),
1850 "or{b}\t{$src2, $dst|$dst, $src2}",
1851 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1852 (implicit EFLAGS)]>;
1853 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1854 (ins GR16:$src1, GR16:$src2),
1855 "or{w}\t{$src2, $dst|$dst, $src2}",
1856 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1857 (implicit EFLAGS)]>, OpSize;
1858 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1859 (ins GR32:$src1, GR32:$src2),
1860 "or{l}\t{$src2, $dst|$dst, $src2}",
1861 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1862 (implicit EFLAGS)]>;
1865 // OR instructions with the destination register in REG and the source register
1866 // in R/M. Included for the disassembler.
1867 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1868 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1869 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1870 (ins GR16:$src1, GR16:$src2),
1871 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1872 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1873 (ins GR32:$src1, GR32:$src2),
1874 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1876 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst),
1877 (ins GR8 :$src1, i8mem :$src2),
1878 "or{b}\t{$src2, $dst|$dst, $src2}",
1879 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1880 (implicit EFLAGS)]>;
1881 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst),
1882 (ins GR16:$src1, i16mem:$src2),
1883 "or{w}\t{$src2, $dst|$dst, $src2}",
1884 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1885 (implicit EFLAGS)]>, OpSize;
1886 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst),
1887 (ins GR32:$src1, i32mem:$src2),
1888 "or{l}\t{$src2, $dst|$dst, $src2}",
1889 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1890 (implicit EFLAGS)]>;
1892 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1893 (ins GR8 :$src1, i8imm:$src2),
1894 "or{b}\t{$src2, $dst|$dst, $src2}",
1895 [(set GR8:$dst, (or_not_add GR8:$src1, imm:$src2)),
1896 (implicit EFLAGS)]>;
1897 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1898 (ins GR16:$src1, i16imm:$src2),
1899 "or{w}\t{$src2, $dst|$dst, $src2}",
1900 [(set GR16:$dst, (or_not_add GR16:$src1, imm:$src2)),
1901 (implicit EFLAGS)]>, OpSize;
1902 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1903 (ins GR32:$src1, i32imm:$src2),
1904 "or{l}\t{$src2, $dst|$dst, $src2}",
1905 [(set GR32:$dst, (or_not_add GR32:$src1, imm:$src2)),
1906 (implicit EFLAGS)]>;
1908 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1909 (ins GR16:$src1, i16i8imm:$src2),
1910 "or{w}\t{$src2, $dst|$dst, $src2}",
1911 [(set GR16:$dst, (or_not_add GR16:$src1, i16immSExt8:$src2)),
1912 (implicit EFLAGS)]>, OpSize;
1913 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1914 (ins GR32:$src1, i32i8imm:$src2),
1915 "or{l}\t{$src2, $dst|$dst, $src2}",
1916 [(set GR32:$dst, (or_not_add GR32:$src1, i32immSExt8:$src2)),
1917 (implicit EFLAGS)]>;
1918 let isTwoAddress = 0 in {
1919 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1920 "or{b}\t{$src, $dst|$dst, $src}",
1921 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1922 (implicit EFLAGS)]>;
1923 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1924 "or{w}\t{$src, $dst|$dst, $src}",
1925 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1926 (implicit EFLAGS)]>, OpSize;
1927 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1928 "or{l}\t{$src, $dst|$dst, $src}",
1929 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1930 (implicit EFLAGS)]>;
1931 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1932 "or{b}\t{$src, $dst|$dst, $src}",
1933 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1934 (implicit EFLAGS)]>;
1935 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1936 "or{w}\t{$src, $dst|$dst, $src}",
1937 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1938 (implicit EFLAGS)]>,
1940 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1941 "or{l}\t{$src, $dst|$dst, $src}",
1942 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1943 (implicit EFLAGS)]>;
1944 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1945 "or{w}\t{$src, $dst|$dst, $src}",
1946 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1947 (implicit EFLAGS)]>,
1949 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1950 "or{l}\t{$src, $dst|$dst, $src}",
1951 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1952 (implicit EFLAGS)]>;
1954 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1955 "or{b}\t{$src, %al|%al, $src}", []>;
1956 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1957 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1958 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1959 "or{l}\t{$src, %eax|%eax, $src}", []>;
1960 } // isTwoAddress = 0
1963 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1964 def XOR8rr : I<0x30, MRMDestReg,
1965 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1966 "xor{b}\t{$src2, $dst|$dst, $src2}",
1967 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1968 (implicit EFLAGS)]>;
1969 def XOR16rr : I<0x31, MRMDestReg,
1970 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1971 "xor{w}\t{$src2, $dst|$dst, $src2}",
1972 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1973 (implicit EFLAGS)]>, OpSize;
1974 def XOR32rr : I<0x31, MRMDestReg,
1975 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1976 "xor{l}\t{$src2, $dst|$dst, $src2}",
1977 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1978 (implicit EFLAGS)]>;
1979 } // isCommutable = 1
1981 // XOR instructions with the destination register in REG and the source register
1982 // in R/M. Included for the disassembler.
1983 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1984 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
1985 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
1986 (ins GR16:$src1, GR16:$src2),
1987 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1988 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
1989 (ins GR32:$src1, GR32:$src2),
1990 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
1992 def XOR8rm : I<0x32, MRMSrcMem ,
1993 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1994 "xor{b}\t{$src2, $dst|$dst, $src2}",
1995 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1996 (implicit EFLAGS)]>;
1997 def XOR16rm : I<0x33, MRMSrcMem ,
1998 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1999 "xor{w}\t{$src2, $dst|$dst, $src2}",
2000 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
2001 (implicit EFLAGS)]>,
2003 def XOR32rm : I<0x33, MRMSrcMem ,
2004 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2005 "xor{l}\t{$src2, $dst|$dst, $src2}",
2006 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
2007 (implicit EFLAGS)]>;
2009 def XOR8ri : Ii8<0x80, MRM6r,
2010 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2011 "xor{b}\t{$src2, $dst|$dst, $src2}",
2012 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
2013 (implicit EFLAGS)]>;
2014 def XOR16ri : Ii16<0x81, MRM6r,
2015 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2016 "xor{w}\t{$src2, $dst|$dst, $src2}",
2017 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
2018 (implicit EFLAGS)]>, OpSize;
2019 def XOR32ri : Ii32<0x81, MRM6r,
2020 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2021 "xor{l}\t{$src2, $dst|$dst, $src2}",
2022 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
2023 (implicit EFLAGS)]>;
2024 def XOR16ri8 : Ii8<0x83, MRM6r,
2025 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2026 "xor{w}\t{$src2, $dst|$dst, $src2}",
2027 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
2028 (implicit EFLAGS)]>,
2030 def XOR32ri8 : Ii8<0x83, MRM6r,
2031 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2032 "xor{l}\t{$src2, $dst|$dst, $src2}",
2033 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
2034 (implicit EFLAGS)]>;
2036 let isTwoAddress = 0 in {
2037 def XOR8mr : I<0x30, MRMDestMem,
2038 (outs), (ins i8mem :$dst, GR8 :$src),
2039 "xor{b}\t{$src, $dst|$dst, $src}",
2040 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2041 (implicit EFLAGS)]>;
2042 def XOR16mr : I<0x31, MRMDestMem,
2043 (outs), (ins i16mem:$dst, GR16:$src),
2044 "xor{w}\t{$src, $dst|$dst, $src}",
2045 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2046 (implicit EFLAGS)]>,
2048 def XOR32mr : I<0x31, MRMDestMem,
2049 (outs), (ins i32mem:$dst, GR32:$src),
2050 "xor{l}\t{$src, $dst|$dst, $src}",
2051 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2052 (implicit EFLAGS)]>;
2053 def XOR8mi : Ii8<0x80, MRM6m,
2054 (outs), (ins i8mem :$dst, i8imm :$src),
2055 "xor{b}\t{$src, $dst|$dst, $src}",
2056 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2057 (implicit EFLAGS)]>;
2058 def XOR16mi : Ii16<0x81, MRM6m,
2059 (outs), (ins i16mem:$dst, i16imm:$src),
2060 "xor{w}\t{$src, $dst|$dst, $src}",
2061 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2062 (implicit EFLAGS)]>,
2064 def XOR32mi : Ii32<0x81, MRM6m,
2065 (outs), (ins i32mem:$dst, i32imm:$src),
2066 "xor{l}\t{$src, $dst|$dst, $src}",
2067 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2068 (implicit EFLAGS)]>;
2069 def XOR16mi8 : Ii8<0x83, MRM6m,
2070 (outs), (ins i16mem:$dst, i16i8imm :$src),
2071 "xor{w}\t{$src, $dst|$dst, $src}",
2072 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2073 (implicit EFLAGS)]>,
2075 def XOR32mi8 : Ii8<0x83, MRM6m,
2076 (outs), (ins i32mem:$dst, i32i8imm :$src),
2077 "xor{l}\t{$src, $dst|$dst, $src}",
2078 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2079 (implicit EFLAGS)]>;
2081 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2082 "xor{b}\t{$src, %al|%al, $src}", []>;
2083 def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src),
2084 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2085 def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src),
2086 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2087 } // isTwoAddress = 0
2088 } // Defs = [EFLAGS]
2090 // Shift instructions
2091 let Defs = [EFLAGS] in {
2092 let Uses = [CL] in {
2093 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2094 "shl{b}\t{%cl, $dst|$dst, CL}",
2095 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2096 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2097 "shl{w}\t{%cl, $dst|$dst, CL}",
2098 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2099 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2100 "shl{l}\t{%cl, $dst|$dst, CL}",
2101 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2104 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2105 "shl{b}\t{$src2, $dst|$dst, $src2}",
2106 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2107 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2108 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2109 "shl{w}\t{$src2, $dst|$dst, $src2}",
2110 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2111 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2112 "shl{l}\t{$src2, $dst|$dst, $src2}",
2113 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2115 // NOTE: We don't include patterns for shifts of a register by one, because
2116 // 'add reg,reg' is cheaper.
2118 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2119 "shl{b}\t$dst", []>;
2120 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2121 "shl{w}\t$dst", []>, OpSize;
2122 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2123 "shl{l}\t$dst", []>;
2125 } // isConvertibleToThreeAddress = 1
2127 let isTwoAddress = 0 in {
2128 let Uses = [CL] in {
2129 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2130 "shl{b}\t{%cl, $dst|$dst, CL}",
2131 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2132 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2133 "shl{w}\t{%cl, $dst|$dst, CL}",
2134 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2135 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2136 "shl{l}\t{%cl, $dst|$dst, CL}",
2137 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2139 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2140 "shl{b}\t{$src, $dst|$dst, $src}",
2141 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2142 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2143 "shl{w}\t{$src, $dst|$dst, $src}",
2144 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2146 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2147 "shl{l}\t{$src, $dst|$dst, $src}",
2148 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2151 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2153 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2154 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2156 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2158 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2160 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2163 let Uses = [CL] in {
2164 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2165 "shr{b}\t{%cl, $dst|$dst, CL}",
2166 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2167 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2168 "shr{w}\t{%cl, $dst|$dst, CL}",
2169 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2170 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2171 "shr{l}\t{%cl, $dst|$dst, CL}",
2172 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2175 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2176 "shr{b}\t{$src2, $dst|$dst, $src2}",
2177 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2178 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2179 "shr{w}\t{$src2, $dst|$dst, $src2}",
2180 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2181 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2182 "shr{l}\t{$src2, $dst|$dst, $src2}",
2183 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2186 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2188 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2189 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2191 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2192 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2194 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2196 let isTwoAddress = 0 in {
2197 let Uses = [CL] in {
2198 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2199 "shr{b}\t{%cl, $dst|$dst, CL}",
2200 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2201 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2202 "shr{w}\t{%cl, $dst|$dst, CL}",
2203 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2205 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2206 "shr{l}\t{%cl, $dst|$dst, CL}",
2207 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2209 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2210 "shr{b}\t{$src, $dst|$dst, $src}",
2211 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2212 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2213 "shr{w}\t{$src, $dst|$dst, $src}",
2214 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2216 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2217 "shr{l}\t{$src, $dst|$dst, $src}",
2218 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2221 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2223 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2224 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2226 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2227 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2229 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2232 let Uses = [CL] in {
2233 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2234 "sar{b}\t{%cl, $dst|$dst, CL}",
2235 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2236 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2237 "sar{w}\t{%cl, $dst|$dst, CL}",
2238 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2239 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2240 "sar{l}\t{%cl, $dst|$dst, CL}",
2241 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2244 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2245 "sar{b}\t{$src2, $dst|$dst, $src2}",
2246 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2247 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2248 "sar{w}\t{$src2, $dst|$dst, $src2}",
2249 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2251 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2252 "sar{l}\t{$src2, $dst|$dst, $src2}",
2253 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2256 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2258 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2259 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2261 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2262 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2264 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2266 let isTwoAddress = 0 in {
2267 let Uses = [CL] in {
2268 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2269 "sar{b}\t{%cl, $dst|$dst, CL}",
2270 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2271 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2272 "sar{w}\t{%cl, $dst|$dst, CL}",
2273 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2274 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2275 "sar{l}\t{%cl, $dst|$dst, CL}",
2276 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2278 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2279 "sar{b}\t{$src, $dst|$dst, $src}",
2280 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2281 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2282 "sar{w}\t{$src, $dst|$dst, $src}",
2283 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2285 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2286 "sar{l}\t{$src, $dst|$dst, $src}",
2287 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2290 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2292 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2293 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2295 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2297 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2299 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2302 // Rotate instructions
2304 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2305 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2306 def RCL8m1 : I<0xD0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src),
2307 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2308 let Uses = [CL] in {
2309 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2310 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2311 def RCL8mCL : I<0xD2, MRM2m, (outs i8mem:$dst), (ins i8mem:$src),
2312 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2314 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2315 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2316 def RCL8mi : Ii8<0xC0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt),
2317 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2319 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2320 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2321 def RCL16m1 : I<0xD1, MRM2m, (outs i16mem:$dst), (ins i16mem:$src),
2322 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2323 let Uses = [CL] in {
2324 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2325 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2326 def RCL16mCL : I<0xD3, MRM2m, (outs i16mem:$dst), (ins i16mem:$src),
2327 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2329 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2330 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2331 def RCL16mi : Ii8<0xC1, MRM2m, (outs i16mem:$dst),
2332 (ins i16mem:$src, i8imm:$cnt),
2333 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2335 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2336 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2337 def RCL32m1 : I<0xD1, MRM2m, (outs i32mem:$dst), (ins i32mem:$src),
2338 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2339 let Uses = [CL] in {
2340 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2341 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2342 def RCL32mCL : I<0xD3, MRM2m, (outs i32mem:$dst), (ins i32mem:$src),
2343 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2345 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2346 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2347 def RCL32mi : Ii8<0xC1, MRM2m, (outs i32mem:$dst),
2348 (ins i32mem:$src, i8imm:$cnt),
2349 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2351 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2352 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2353 def RCR8m1 : I<0xD0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src),
2354 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2355 let Uses = [CL] in {
2356 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2357 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2358 def RCR8mCL : I<0xD2, MRM3m, (outs i8mem:$dst), (ins i8mem:$src),
2359 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2361 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2362 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2363 def RCR8mi : Ii8<0xC0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt),
2364 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2366 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2367 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2368 def RCR16m1 : I<0xD1, MRM3m, (outs i16mem:$dst), (ins i16mem:$src),
2369 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2370 let Uses = [CL] in {
2371 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2372 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2373 def RCR16mCL : I<0xD3, MRM3m, (outs i16mem:$dst), (ins i16mem:$src),
2374 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2376 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2377 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2378 def RCR16mi : Ii8<0xC1, MRM3m, (outs i16mem:$dst),
2379 (ins i16mem:$src, i8imm:$cnt),
2380 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2382 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2383 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2384 def RCR32m1 : I<0xD1, MRM3m, (outs i32mem:$dst), (ins i32mem:$src),
2385 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2386 let Uses = [CL] in {
2387 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2388 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2389 def RCR32mCL : I<0xD3, MRM3m, (outs i32mem:$dst), (ins i32mem:$src),
2390 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2392 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2393 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2394 def RCR32mi : Ii8<0xC1, MRM3m, (outs i32mem:$dst),
2395 (ins i32mem:$src, i8imm:$cnt),
2396 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2398 // FIXME: provide shorter instructions when imm8 == 1
2399 let Uses = [CL] in {
2400 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2401 "rol{b}\t{%cl, $dst|$dst, CL}",
2402 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2403 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2404 "rol{w}\t{%cl, $dst|$dst, CL}",
2405 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2406 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2407 "rol{l}\t{%cl, $dst|$dst, CL}",
2408 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2411 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2412 "rol{b}\t{$src2, $dst|$dst, $src2}",
2413 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2414 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2415 "rol{w}\t{$src2, $dst|$dst, $src2}",
2416 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2418 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2419 "rol{l}\t{$src2, $dst|$dst, $src2}",
2420 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2423 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2425 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2426 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2428 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2429 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2431 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2433 let isTwoAddress = 0 in {
2434 let Uses = [CL] in {
2435 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2436 "rol{b}\t{%cl, $dst|$dst, CL}",
2437 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2438 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2439 "rol{w}\t{%cl, $dst|$dst, CL}",
2440 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2441 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2442 "rol{l}\t{%cl, $dst|$dst, CL}",
2443 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2445 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2446 "rol{b}\t{$src, $dst|$dst, $src}",
2447 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2448 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2449 "rol{w}\t{$src, $dst|$dst, $src}",
2450 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2452 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2453 "rol{l}\t{$src, $dst|$dst, $src}",
2454 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2457 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2459 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2460 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2462 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2464 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2466 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2469 let Uses = [CL] in {
2470 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2471 "ror{b}\t{%cl, $dst|$dst, CL}",
2472 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2473 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2474 "ror{w}\t{%cl, $dst|$dst, CL}",
2475 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2476 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2477 "ror{l}\t{%cl, $dst|$dst, CL}",
2478 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2481 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2482 "ror{b}\t{$src2, $dst|$dst, $src2}",
2483 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2484 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2485 "ror{w}\t{$src2, $dst|$dst, $src2}",
2486 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2488 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2489 "ror{l}\t{$src2, $dst|$dst, $src2}",
2490 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2493 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2495 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2496 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2498 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2499 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2501 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2503 let isTwoAddress = 0 in {
2504 let Uses = [CL] in {
2505 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2506 "ror{b}\t{%cl, $dst|$dst, CL}",
2507 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2508 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2509 "ror{w}\t{%cl, $dst|$dst, CL}",
2510 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2511 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2512 "ror{l}\t{%cl, $dst|$dst, CL}",
2513 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2515 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2516 "ror{b}\t{$src, $dst|$dst, $src}",
2517 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2518 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2519 "ror{w}\t{$src, $dst|$dst, $src}",
2520 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2522 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2523 "ror{l}\t{$src, $dst|$dst, $src}",
2524 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2527 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2529 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2530 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2532 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2534 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2536 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2541 // Double shift instructions (generalizations of rotate)
2542 let Uses = [CL] in {
2543 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2544 (ins GR32:$src1, GR32:$src2),
2545 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2546 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2547 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2548 (ins GR32:$src1, GR32:$src2),
2549 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2550 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2551 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2552 (ins GR16:$src1, GR16:$src2),
2553 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2554 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2556 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2557 (ins GR16:$src1, GR16:$src2),
2558 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2559 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2563 let isCommutable = 1 in { // These instructions commute to each other.
2564 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2566 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2567 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2568 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2571 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2573 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2574 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2575 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2578 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2580 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2581 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2582 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2585 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2587 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2588 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2589 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2594 let isTwoAddress = 0 in {
2595 let Uses = [CL] in {
2596 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2597 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2598 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2600 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2601 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2602 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2605 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2606 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2607 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2608 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2609 (i8 imm:$src3)), addr:$dst)]>,
2611 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2612 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2613 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2614 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2615 (i8 imm:$src3)), addr:$dst)]>,
2618 let Uses = [CL] in {
2619 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2620 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2621 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2622 addr:$dst)]>, TB, OpSize;
2623 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2624 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2625 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2626 addr:$dst)]>, TB, OpSize;
2628 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2629 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2630 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2631 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2632 (i8 imm:$src3)), addr:$dst)]>,
2634 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2635 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2636 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2637 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2638 (i8 imm:$src3)), addr:$dst)]>,
2641 } // Defs = [EFLAGS]
2645 let Defs = [EFLAGS] in {
2646 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2647 // Register-Register Addition
2648 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2649 (ins GR8 :$src1, GR8 :$src2),
2650 "add{b}\t{$src2, $dst|$dst, $src2}",
2651 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2652 (implicit EFLAGS)]>;
2654 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2655 // Register-Register Addition
2656 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2657 (ins GR16:$src1, GR16:$src2),
2658 "add{w}\t{$src2, $dst|$dst, $src2}",
2659 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2660 (implicit EFLAGS)]>, OpSize;
2661 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2662 (ins GR32:$src1, GR32:$src2),
2663 "add{l}\t{$src2, $dst|$dst, $src2}",
2664 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2665 (implicit EFLAGS)]>;
2666 } // end isConvertibleToThreeAddress
2667 } // end isCommutable
2669 // Register-Memory Addition
2670 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2671 (ins GR8 :$src1, i8mem :$src2),
2672 "add{b}\t{$src2, $dst|$dst, $src2}",
2673 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2674 (implicit EFLAGS)]>;
2675 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2676 (ins GR16:$src1, i16mem:$src2),
2677 "add{w}\t{$src2, $dst|$dst, $src2}",
2678 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2679 (implicit EFLAGS)]>, OpSize;
2680 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2681 (ins GR32:$src1, i32mem:$src2),
2682 "add{l}\t{$src2, $dst|$dst, $src2}",
2683 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2684 (implicit EFLAGS)]>;
2686 // Register-Register Addition - Equivalent to the normal rr forms (ADD8rr,
2687 // ADD16rr, and ADD32rr), but differently encoded.
2688 def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2689 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2690 def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2691 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2692 def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2693 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2695 // Register-Integer Addition
2696 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2697 "add{b}\t{$src2, $dst|$dst, $src2}",
2698 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2699 (implicit EFLAGS)]>;
2701 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2702 // Register-Integer Addition
2703 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2704 (ins GR16:$src1, i16imm:$src2),
2705 "add{w}\t{$src2, $dst|$dst, $src2}",
2706 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2707 (implicit EFLAGS)]>, OpSize;
2708 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2709 (ins GR32:$src1, i32imm:$src2),
2710 "add{l}\t{$src2, $dst|$dst, $src2}",
2711 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2712 (implicit EFLAGS)]>;
2713 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2714 (ins GR16:$src1, i16i8imm:$src2),
2715 "add{w}\t{$src2, $dst|$dst, $src2}",
2716 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2717 (implicit EFLAGS)]>, OpSize;
2718 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2719 (ins GR32:$src1, i32i8imm:$src2),
2720 "add{l}\t{$src2, $dst|$dst, $src2}",
2721 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2722 (implicit EFLAGS)]>;
2725 let isTwoAddress = 0 in {
2726 // Memory-Register Addition
2727 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2728 "add{b}\t{$src2, $dst|$dst, $src2}",
2729 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2730 (implicit EFLAGS)]>;
2731 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2732 "add{w}\t{$src2, $dst|$dst, $src2}",
2733 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2734 (implicit EFLAGS)]>, OpSize;
2735 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2736 "add{l}\t{$src2, $dst|$dst, $src2}",
2737 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2738 (implicit EFLAGS)]>;
2739 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2740 "add{b}\t{$src2, $dst|$dst, $src2}",
2741 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2742 (implicit EFLAGS)]>;
2743 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2744 "add{w}\t{$src2, $dst|$dst, $src2}",
2745 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2746 (implicit EFLAGS)]>, OpSize;
2747 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2748 "add{l}\t{$src2, $dst|$dst, $src2}",
2749 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2750 (implicit EFLAGS)]>;
2751 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2752 "add{w}\t{$src2, $dst|$dst, $src2}",
2753 [(store (add (load addr:$dst), i16immSExt8:$src2),
2755 (implicit EFLAGS)]>, OpSize;
2756 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2757 "add{l}\t{$src2, $dst|$dst, $src2}",
2758 [(store (add (load addr:$dst), i32immSExt8:$src2),
2760 (implicit EFLAGS)]>;
2763 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2764 "add{b}\t{$src, %al|%al, $src}", []>;
2765 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2766 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2767 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2768 "add{l}\t{$src, %eax|%eax, $src}", []>;
2771 let Uses = [EFLAGS] in {
2772 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2773 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2774 "adc{b}\t{$src2, $dst|$dst, $src2}",
2775 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2776 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2777 (ins GR16:$src1, GR16:$src2),
2778 "adc{w}\t{$src2, $dst|$dst, $src2}",
2779 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2780 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2781 (ins GR32:$src1, GR32:$src2),
2782 "adc{l}\t{$src2, $dst|$dst, $src2}",
2783 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2786 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2787 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2788 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2789 (ins GR16:$src1, GR16:$src2),
2790 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2791 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2792 (ins GR32:$src1, GR32:$src2),
2793 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2795 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2796 (ins GR8:$src1, i8mem:$src2),
2797 "adc{b}\t{$src2, $dst|$dst, $src2}",
2798 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2799 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2800 (ins GR16:$src1, i16mem:$src2),
2801 "adc{w}\t{$src2, $dst|$dst, $src2}",
2802 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2804 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2805 (ins GR32:$src1, i32mem:$src2),
2806 "adc{l}\t{$src2, $dst|$dst, $src2}",
2807 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2808 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2809 "adc{b}\t{$src2, $dst|$dst, $src2}",
2810 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2811 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2812 (ins GR16:$src1, i16imm:$src2),
2813 "adc{w}\t{$src2, $dst|$dst, $src2}",
2814 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2815 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2816 (ins GR16:$src1, i16i8imm:$src2),
2817 "adc{w}\t{$src2, $dst|$dst, $src2}",
2818 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2820 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2821 (ins GR32:$src1, i32imm:$src2),
2822 "adc{l}\t{$src2, $dst|$dst, $src2}",
2823 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2824 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2825 (ins GR32:$src1, i32i8imm:$src2),
2826 "adc{l}\t{$src2, $dst|$dst, $src2}",
2827 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2829 let isTwoAddress = 0 in {
2830 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2831 "adc{b}\t{$src2, $dst|$dst, $src2}",
2832 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2833 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2834 "adc{w}\t{$src2, $dst|$dst, $src2}",
2835 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2837 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2838 "adc{l}\t{$src2, $dst|$dst, $src2}",
2839 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2840 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2841 "adc{b}\t{$src2, $dst|$dst, $src2}",
2842 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2843 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2844 "adc{w}\t{$src2, $dst|$dst, $src2}",
2845 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2847 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2848 "adc{w}\t{$src2, $dst|$dst, $src2}",
2849 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2851 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2852 "adc{l}\t{$src2, $dst|$dst, $src2}",
2853 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2854 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2855 "adc{l}\t{$src2, $dst|$dst, $src2}",
2856 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2858 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2859 "adc{b}\t{$src, %al|%al, $src}", []>;
2860 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2861 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2862 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2863 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2865 } // Uses = [EFLAGS]
2867 // Register-Register Subtraction
2868 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2869 "sub{b}\t{$src2, $dst|$dst, $src2}",
2870 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2871 (implicit EFLAGS)]>;
2872 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2873 "sub{w}\t{$src2, $dst|$dst, $src2}",
2874 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2875 (implicit EFLAGS)]>, OpSize;
2876 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2877 "sub{l}\t{$src2, $dst|$dst, $src2}",
2878 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2879 (implicit EFLAGS)]>;
2881 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2882 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2883 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2884 (ins GR16:$src1, GR16:$src2),
2885 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2886 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2887 (ins GR32:$src1, GR32:$src2),
2888 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2890 // Register-Memory Subtraction
2891 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2892 (ins GR8 :$src1, i8mem :$src2),
2893 "sub{b}\t{$src2, $dst|$dst, $src2}",
2894 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2895 (implicit EFLAGS)]>;
2896 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2897 (ins GR16:$src1, i16mem:$src2),
2898 "sub{w}\t{$src2, $dst|$dst, $src2}",
2899 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2900 (implicit EFLAGS)]>, OpSize;
2901 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2902 (ins GR32:$src1, i32mem:$src2),
2903 "sub{l}\t{$src2, $dst|$dst, $src2}",
2904 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2905 (implicit EFLAGS)]>;
2907 // Register-Integer Subtraction
2908 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2909 (ins GR8:$src1, i8imm:$src2),
2910 "sub{b}\t{$src2, $dst|$dst, $src2}",
2911 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2912 (implicit EFLAGS)]>;
2913 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2914 (ins GR16:$src1, i16imm:$src2),
2915 "sub{w}\t{$src2, $dst|$dst, $src2}",
2916 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2917 (implicit EFLAGS)]>, OpSize;
2918 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2919 (ins GR32:$src1, i32imm:$src2),
2920 "sub{l}\t{$src2, $dst|$dst, $src2}",
2921 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2922 (implicit EFLAGS)]>;
2923 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2924 (ins GR16:$src1, i16i8imm:$src2),
2925 "sub{w}\t{$src2, $dst|$dst, $src2}",
2926 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2927 (implicit EFLAGS)]>, OpSize;
2928 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2929 (ins GR32:$src1, i32i8imm:$src2),
2930 "sub{l}\t{$src2, $dst|$dst, $src2}",
2931 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2932 (implicit EFLAGS)]>;
2934 let isTwoAddress = 0 in {
2935 // Memory-Register Subtraction
2936 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2937 "sub{b}\t{$src2, $dst|$dst, $src2}",
2938 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2939 (implicit EFLAGS)]>;
2940 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2941 "sub{w}\t{$src2, $dst|$dst, $src2}",
2942 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2943 (implicit EFLAGS)]>, OpSize;
2944 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2945 "sub{l}\t{$src2, $dst|$dst, $src2}",
2946 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2947 (implicit EFLAGS)]>;
2949 // Memory-Integer Subtraction
2950 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2951 "sub{b}\t{$src2, $dst|$dst, $src2}",
2952 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2953 (implicit EFLAGS)]>;
2954 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2955 "sub{w}\t{$src2, $dst|$dst, $src2}",
2956 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2957 (implicit EFLAGS)]>, OpSize;
2958 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2959 "sub{l}\t{$src2, $dst|$dst, $src2}",
2960 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2961 (implicit EFLAGS)]>;
2962 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2963 "sub{w}\t{$src2, $dst|$dst, $src2}",
2964 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2966 (implicit EFLAGS)]>, OpSize;
2967 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2968 "sub{l}\t{$src2, $dst|$dst, $src2}",
2969 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2971 (implicit EFLAGS)]>;
2973 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
2974 "sub{b}\t{$src, %al|%al, $src}", []>;
2975 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
2976 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2977 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
2978 "sub{l}\t{$src, %eax|%eax, $src}", []>;
2981 let Uses = [EFLAGS] in {
2982 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2983 (ins GR8:$src1, GR8:$src2),
2984 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2985 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2986 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2987 (ins GR16:$src1, GR16:$src2),
2988 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2989 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2990 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2991 (ins GR32:$src1, GR32:$src2),
2992 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2993 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2995 let isTwoAddress = 0 in {
2996 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2997 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2998 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2999 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3000 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3001 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3003 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3004 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3005 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3006 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3007 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3008 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3009 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3010 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3011 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3013 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3014 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3015 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3017 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3018 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3019 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3020 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3021 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3022 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3024 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3025 "sbb{b}\t{$src, %al|%al, $src}", []>;
3026 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3027 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3028 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3029 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3032 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3033 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3034 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3035 (ins GR16:$src1, GR16:$src2),
3036 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3037 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3038 (ins GR32:$src1, GR32:$src2),
3039 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3041 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3042 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3043 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3044 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3045 (ins GR16:$src1, i16mem:$src2),
3046 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3047 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3049 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3050 (ins GR32:$src1, i32mem:$src2),
3051 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3052 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3053 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3054 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3055 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3056 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3057 (ins GR16:$src1, i16imm:$src2),
3058 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3059 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3060 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3061 (ins GR16:$src1, i16i8imm:$src2),
3062 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3063 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3065 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3066 (ins GR32:$src1, i32imm:$src2),
3067 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3068 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3069 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3070 (ins GR32:$src1, i32i8imm:$src2),
3071 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3072 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3073 } // Uses = [EFLAGS]
3074 } // Defs = [EFLAGS]
3076 let Defs = [EFLAGS] in {
3077 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3078 // Register-Register Signed Integer Multiply
3079 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3080 "imul{w}\t{$src2, $dst|$dst, $src2}",
3081 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
3082 (implicit EFLAGS)]>, TB, OpSize;
3083 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3084 "imul{l}\t{$src2, $dst|$dst, $src2}",
3085 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
3086 (implicit EFLAGS)]>, TB;
3089 // Register-Memory Signed Integer Multiply
3090 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3091 (ins GR16:$src1, i16mem:$src2),
3092 "imul{w}\t{$src2, $dst|$dst, $src2}",
3093 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
3094 (implicit EFLAGS)]>, TB, OpSize;
3095 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3096 (ins GR32:$src1, i32mem:$src2),
3097 "imul{l}\t{$src2, $dst|$dst, $src2}",
3098 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
3099 (implicit EFLAGS)]>, TB;
3100 } // Defs = [EFLAGS]
3101 } // end Two Address instructions
3103 // Suprisingly enough, these are not two address instructions!
3104 let Defs = [EFLAGS] in {
3105 // Register-Integer Signed Integer Multiply
3106 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3107 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3108 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3109 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
3110 (implicit EFLAGS)]>, OpSize;
3111 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3112 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3113 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3114 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
3115 (implicit EFLAGS)]>;
3116 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3117 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3118 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3119 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
3120 (implicit EFLAGS)]>, OpSize;
3121 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3122 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3123 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3124 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
3125 (implicit EFLAGS)]>;
3127 // Memory-Integer Signed Integer Multiply
3128 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3129 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3130 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3131 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
3132 (implicit EFLAGS)]>, OpSize;
3133 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3134 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3135 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3136 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
3137 (implicit EFLAGS)]>;
3138 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3139 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3140 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3141 [(set GR16:$dst, (mul (load addr:$src1),
3142 i16immSExt8:$src2)),
3143 (implicit EFLAGS)]>, OpSize;
3144 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3145 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3146 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3147 [(set GR32:$dst, (mul (load addr:$src1),
3148 i32immSExt8:$src2)),
3149 (implicit EFLAGS)]>;
3150 } // Defs = [EFLAGS]
3152 //===----------------------------------------------------------------------===//
3153 // Test instructions are just like AND, except they don't generate a result.
3155 let Defs = [EFLAGS] in {
3156 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3157 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
3158 "test{b}\t{$src2, $src1|$src1, $src2}",
3159 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
3160 (implicit EFLAGS)]>;
3161 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3162 "test{w}\t{$src2, $src1|$src1, $src2}",
3163 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
3164 (implicit EFLAGS)]>,
3166 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3167 "test{l}\t{$src2, $src1|$src1, $src2}",
3168 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
3169 (implicit EFLAGS)]>;
3172 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3173 "test{b}\t{$src, %al|%al, $src}", []>;
3174 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3175 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3176 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3177 "test{l}\t{$src, %eax|%eax, $src}", []>;
3179 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3180 "test{b}\t{$src2, $src1|$src1, $src2}",
3181 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
3182 (implicit EFLAGS)]>;
3183 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3184 "test{w}\t{$src2, $src1|$src1, $src2}",
3185 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
3186 (implicit EFLAGS)]>, OpSize;
3187 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3188 "test{l}\t{$src2, $src1|$src1, $src2}",
3189 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
3190 (implicit EFLAGS)]>;
3192 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3193 (outs), (ins GR8:$src1, i8imm:$src2),
3194 "test{b}\t{$src2, $src1|$src1, $src2}",
3195 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
3196 (implicit EFLAGS)]>;
3197 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3198 (outs), (ins GR16:$src1, i16imm:$src2),
3199 "test{w}\t{$src2, $src1|$src1, $src2}",
3200 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
3201 (implicit EFLAGS)]>, OpSize;
3202 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3203 (outs), (ins GR32:$src1, i32imm:$src2),
3204 "test{l}\t{$src2, $src1|$src1, $src2}",
3205 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
3206 (implicit EFLAGS)]>;
3208 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3209 (outs), (ins i8mem:$src1, i8imm:$src2),
3210 "test{b}\t{$src2, $src1|$src1, $src2}",
3211 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
3212 (implicit EFLAGS)]>;
3213 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3214 (outs), (ins i16mem:$src1, i16imm:$src2),
3215 "test{w}\t{$src2, $src1|$src1, $src2}",
3216 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
3217 (implicit EFLAGS)]>, OpSize;
3218 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3219 (outs), (ins i32mem:$src1, i32imm:$src2),
3220 "test{l}\t{$src2, $src1|$src1, $src2}",
3221 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
3222 (implicit EFLAGS)]>;
3223 } // Defs = [EFLAGS]
3226 // Condition code ops, incl. set if equal/not equal/...
3227 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3228 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3229 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3230 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3232 let Uses = [EFLAGS] in {
3233 // Use sbb to materialize carry bit.
3235 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3236 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins),
3237 "sbb{b}\t$dst, $dst",
3238 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3239 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins),
3240 "sbb{w}\t$dst, $dst",
3241 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3243 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins),
3244 "sbb{l}\t$dst, $dst",
3245 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3248 def SETEr : I<0x94, MRM0r,
3249 (outs GR8 :$dst), (ins),
3251 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3253 def SETEm : I<0x94, MRM0m,
3254 (outs), (ins i8mem:$dst),
3256 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3259 def SETNEr : I<0x95, MRM0r,
3260 (outs GR8 :$dst), (ins),
3262 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3264 def SETNEm : I<0x95, MRM0m,
3265 (outs), (ins i8mem:$dst),
3267 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3270 def SETLr : I<0x9C, MRM0r,
3271 (outs GR8 :$dst), (ins),
3273 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3274 TB; // GR8 = < signed
3275 def SETLm : I<0x9C, MRM0m,
3276 (outs), (ins i8mem:$dst),
3278 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3279 TB; // [mem8] = < signed
3281 def SETGEr : I<0x9D, MRM0r,
3282 (outs GR8 :$dst), (ins),
3284 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3285 TB; // GR8 = >= signed
3286 def SETGEm : I<0x9D, MRM0m,
3287 (outs), (ins i8mem:$dst),
3289 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3290 TB; // [mem8] = >= signed
3292 def SETLEr : I<0x9E, MRM0r,
3293 (outs GR8 :$dst), (ins),
3295 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3296 TB; // GR8 = <= signed
3297 def SETLEm : I<0x9E, MRM0m,
3298 (outs), (ins i8mem:$dst),
3300 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3301 TB; // [mem8] = <= signed
3303 def SETGr : I<0x9F, MRM0r,
3304 (outs GR8 :$dst), (ins),
3306 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3307 TB; // GR8 = > signed
3308 def SETGm : I<0x9F, MRM0m,
3309 (outs), (ins i8mem:$dst),
3311 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3312 TB; // [mem8] = > signed
3314 def SETBr : I<0x92, MRM0r,
3315 (outs GR8 :$dst), (ins),
3317 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3318 TB; // GR8 = < unsign
3319 def SETBm : I<0x92, MRM0m,
3320 (outs), (ins i8mem:$dst),
3322 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3323 TB; // [mem8] = < unsign
3325 def SETAEr : I<0x93, MRM0r,
3326 (outs GR8 :$dst), (ins),
3328 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3329 TB; // GR8 = >= unsign
3330 def SETAEm : I<0x93, MRM0m,
3331 (outs), (ins i8mem:$dst),
3333 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3334 TB; // [mem8] = >= unsign
3336 def SETBEr : I<0x96, MRM0r,
3337 (outs GR8 :$dst), (ins),
3339 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3340 TB; // GR8 = <= unsign
3341 def SETBEm : I<0x96, MRM0m,
3342 (outs), (ins i8mem:$dst),
3344 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3345 TB; // [mem8] = <= unsign
3347 def SETAr : I<0x97, MRM0r,
3348 (outs GR8 :$dst), (ins),
3350 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3351 TB; // GR8 = > signed
3352 def SETAm : I<0x97, MRM0m,
3353 (outs), (ins i8mem:$dst),
3355 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3356 TB; // [mem8] = > signed
3358 def SETSr : I<0x98, MRM0r,
3359 (outs GR8 :$dst), (ins),
3361 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3362 TB; // GR8 = <sign bit>
3363 def SETSm : I<0x98, MRM0m,
3364 (outs), (ins i8mem:$dst),
3366 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3367 TB; // [mem8] = <sign bit>
3368 def SETNSr : I<0x99, MRM0r,
3369 (outs GR8 :$dst), (ins),
3371 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3372 TB; // GR8 = !<sign bit>
3373 def SETNSm : I<0x99, MRM0m,
3374 (outs), (ins i8mem:$dst),
3376 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3377 TB; // [mem8] = !<sign bit>
3379 def SETPr : I<0x9A, MRM0r,
3380 (outs GR8 :$dst), (ins),
3382 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3384 def SETPm : I<0x9A, MRM0m,
3385 (outs), (ins i8mem:$dst),
3387 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3388 TB; // [mem8] = parity
3389 def SETNPr : I<0x9B, MRM0r,
3390 (outs GR8 :$dst), (ins),
3392 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3393 TB; // GR8 = not parity
3394 def SETNPm : I<0x9B, MRM0m,
3395 (outs), (ins i8mem:$dst),
3397 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3398 TB; // [mem8] = not parity
3400 def SETOr : I<0x90, MRM0r,
3401 (outs GR8 :$dst), (ins),
3403 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3404 TB; // GR8 = overflow
3405 def SETOm : I<0x90, MRM0m,
3406 (outs), (ins i8mem:$dst),
3408 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3409 TB; // [mem8] = overflow
3410 def SETNOr : I<0x91, MRM0r,
3411 (outs GR8 :$dst), (ins),
3413 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3414 TB; // GR8 = not overflow
3415 def SETNOm : I<0x91, MRM0m,
3416 (outs), (ins i8mem:$dst),
3418 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3419 TB; // [mem8] = not overflow
3420 } // Uses = [EFLAGS]
3423 // Integer comparisons
3424 let Defs = [EFLAGS] in {
3425 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3426 "cmp{b}\t{$src, %al|%al, $src}", []>;
3427 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3428 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3429 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3430 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3432 def CMP8rr : I<0x38, MRMDestReg,
3433 (outs), (ins GR8 :$src1, GR8 :$src2),
3434 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3435 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
3436 def CMP16rr : I<0x39, MRMDestReg,
3437 (outs), (ins GR16:$src1, GR16:$src2),
3438 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3439 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
3440 def CMP32rr : I<0x39, MRMDestReg,
3441 (outs), (ins GR32:$src1, GR32:$src2),
3442 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3443 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
3444 def CMP8mr : I<0x38, MRMDestMem,
3445 (outs), (ins i8mem :$src1, GR8 :$src2),
3446 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3447 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
3448 (implicit EFLAGS)]>;
3449 def CMP16mr : I<0x39, MRMDestMem,
3450 (outs), (ins i16mem:$src1, GR16:$src2),
3451 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3452 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
3453 (implicit EFLAGS)]>, OpSize;
3454 def CMP32mr : I<0x39, MRMDestMem,
3455 (outs), (ins i32mem:$src1, GR32:$src2),
3456 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3457 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
3458 (implicit EFLAGS)]>;
3459 def CMP8rm : I<0x3A, MRMSrcMem,
3460 (outs), (ins GR8 :$src1, i8mem :$src2),
3461 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3462 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
3463 (implicit EFLAGS)]>;
3464 def CMP16rm : I<0x3B, MRMSrcMem,
3465 (outs), (ins GR16:$src1, i16mem:$src2),
3466 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3467 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
3468 (implicit EFLAGS)]>, OpSize;
3469 def CMP32rm : I<0x3B, MRMSrcMem,
3470 (outs), (ins GR32:$src1, i32mem:$src2),
3471 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3472 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
3473 (implicit EFLAGS)]>;
3474 def CMP8mrmrr : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3475 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3476 def CMP16mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3477 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3478 def CMP32mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3479 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3480 def CMP8ri : Ii8<0x80, MRM7r,
3481 (outs), (ins GR8:$src1, i8imm:$src2),
3482 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3483 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
3484 def CMP16ri : Ii16<0x81, MRM7r,
3485 (outs), (ins GR16:$src1, i16imm:$src2),
3486 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3487 [(X86cmp GR16:$src1, imm:$src2),
3488 (implicit EFLAGS)]>, OpSize;
3489 def CMP32ri : Ii32<0x81, MRM7r,
3490 (outs), (ins GR32:$src1, i32imm:$src2),
3491 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3492 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
3493 def CMP8mi : Ii8 <0x80, MRM7m,
3494 (outs), (ins i8mem :$src1, i8imm :$src2),
3495 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3496 [(X86cmp (loadi8 addr:$src1), imm:$src2),
3497 (implicit EFLAGS)]>;
3498 def CMP16mi : Ii16<0x81, MRM7m,
3499 (outs), (ins i16mem:$src1, i16imm:$src2),
3500 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3501 [(X86cmp (loadi16 addr:$src1), imm:$src2),
3502 (implicit EFLAGS)]>, OpSize;
3503 def CMP32mi : Ii32<0x81, MRM7m,
3504 (outs), (ins i32mem:$src1, i32imm:$src2),
3505 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3506 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3507 (implicit EFLAGS)]>;
3508 def CMP16ri8 : Ii8<0x83, MRM7r,
3509 (outs), (ins GR16:$src1, i16i8imm:$src2),
3510 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3511 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3512 (implicit EFLAGS)]>, OpSize;
3513 def CMP16mi8 : Ii8<0x83, MRM7m,
3514 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3515 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3516 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3517 (implicit EFLAGS)]>, OpSize;
3518 def CMP32mi8 : Ii8<0x83, MRM7m,
3519 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3520 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3521 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3522 (implicit EFLAGS)]>;
3523 def CMP32ri8 : Ii8<0x83, MRM7r,
3524 (outs), (ins GR32:$src1, i32i8imm:$src2),
3525 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3526 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3527 (implicit EFLAGS)]>;
3528 } // Defs = [EFLAGS]
3531 // TODO: BTC, BTR, and BTS
3532 let Defs = [EFLAGS] in {
3533 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3534 "bt{w}\t{$src2, $src1|$src1, $src2}",
3535 [(X86bt GR16:$src1, GR16:$src2),
3536 (implicit EFLAGS)]>, OpSize, TB;
3537 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3538 "bt{l}\t{$src2, $src1|$src1, $src2}",
3539 [(X86bt GR32:$src1, GR32:$src2),
3540 (implicit EFLAGS)]>, TB;
3542 // Unlike with the register+register form, the memory+register form of the
3543 // bt instruction does not ignore the high bits of the index. From ISel's
3544 // perspective, this is pretty bizarre. Make these instructions disassembly
3547 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3548 "bt{w}\t{$src2, $src1|$src1, $src2}",
3549 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3550 // (implicit EFLAGS)]
3552 >, OpSize, TB, Requires<[FastBTMem]>;
3553 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3554 "bt{l}\t{$src2, $src1|$src1, $src2}",
3555 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3556 // (implicit EFLAGS)]
3558 >, TB, Requires<[FastBTMem]>;
3560 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3561 "bt{w}\t{$src2, $src1|$src1, $src2}",
3562 [(X86bt GR16:$src1, i16immSExt8:$src2),
3563 (implicit EFLAGS)]>, OpSize, TB;
3564 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3565 "bt{l}\t{$src2, $src1|$src1, $src2}",
3566 [(X86bt GR32:$src1, i32immSExt8:$src2),
3567 (implicit EFLAGS)]>, TB;
3568 // Note that these instructions don't need FastBTMem because that
3569 // only applies when the other operand is in a register. When it's
3570 // an immediate, bt is still fast.
3571 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3572 "bt{w}\t{$src2, $src1|$src1, $src2}",
3573 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3574 (implicit EFLAGS)]>, OpSize, TB;
3575 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3576 "bt{l}\t{$src2, $src1|$src1, $src2}",
3577 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3578 (implicit EFLAGS)]>, TB;
3580 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3581 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3582 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3583 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3584 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3585 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3586 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3587 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3588 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3589 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3590 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3591 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3592 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3593 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3594 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3595 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3597 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3598 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3599 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3600 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3601 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3602 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3603 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3604 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3605 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3606 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3607 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3608 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3609 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3610 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3611 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3612 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3614 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3615 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3616 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3617 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3618 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3619 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3620 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3621 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3622 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3623 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3624 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3625 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3626 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3627 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3628 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3629 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3630 } // Defs = [EFLAGS]
3632 // Sign/Zero extenders
3633 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3634 // of the register here. This has a smaller encoding and avoids a
3635 // partial-register update. Actual movsbw included for the disassembler.
3636 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3637 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3638 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3639 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3640 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3641 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3642 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3643 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3644 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3645 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3646 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3647 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3648 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3649 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3650 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3651 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3652 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3653 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3654 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3655 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3657 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3658 // of the register here. This has a smaller encoding and avoids a
3659 // partial-register update. Actual movzbw included for the disassembler.
3660 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3661 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3662 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3663 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3664 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3665 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3666 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3667 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3668 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3669 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3670 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3671 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3672 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3673 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3674 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3675 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3676 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3677 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3678 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3679 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3681 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3682 // except that they use GR32_NOREX for the output operand register class
3683 // instead of GR32. This allows them to operate on h registers on x86-64.
3684 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3685 (outs GR32_NOREX:$dst), (ins GR8:$src),
3686 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3689 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3690 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3691 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3694 let neverHasSideEffects = 1 in {
3695 let Defs = [AX], Uses = [AL] in
3696 def CBW : I<0x98, RawFrm, (outs), (ins),
3697 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3698 let Defs = [EAX], Uses = [AX] in
3699 def CWDE : I<0x98, RawFrm, (outs), (ins),
3700 "{cwtl|cwde}", []>; // EAX = signext(AX)
3702 let Defs = [AX,DX], Uses = [AX] in
3703 def CWD : I<0x99, RawFrm, (outs), (ins),
3704 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3705 let Defs = [EAX,EDX], Uses = [EAX] in
3706 def CDQ : I<0x99, RawFrm, (outs), (ins),
3707 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3710 //===----------------------------------------------------------------------===//
3711 // Alias Instructions
3712 //===----------------------------------------------------------------------===//
3714 // Alias instructions that map movr0 to xor.
3715 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3716 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3717 isCodeGenOnly = 1 in {
3718 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3719 "xor{b}\t$dst, $dst",
3720 [(set GR8:$dst, 0)]>;
3722 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3723 // encoding and avoids a partial-register update sometimes, but doing so
3724 // at isel time interferes with rematerialization in the current register
3725 // allocator. For now, this is rewritten when the instruction is lowered
3727 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3729 [(set GR16:$dst, 0)]>, OpSize;
3731 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3732 "xor{l}\t$dst, $dst",
3733 [(set GR32:$dst, 0)]>;
3736 //===----------------------------------------------------------------------===//
3737 // Thread Local Storage Instructions
3740 // All calls clobber the non-callee saved registers. ESP is marked as
3741 // a use to prevent stack-pointer assignments that appear immediately
3742 // before calls from potentially appearing dead.
3743 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3744 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3745 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3746 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3748 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3749 "leal\t$sym, %eax; "
3750 "call\t___tls_get_addr@PLT",
3751 [(X86tlsaddr tls32addr:$sym)]>,
3752 Requires<[In32BitMode]>;
3754 let AddedComplexity = 5, isCodeGenOnly = 1 in
3755 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3756 "movl\t%gs:$src, $dst",
3757 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3759 let AddedComplexity = 5, isCodeGenOnly = 1 in
3760 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3761 "movl\t%fs:$src, $dst",
3762 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3764 //===----------------------------------------------------------------------===//
3765 // EH Pseudo Instructions
3767 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3768 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3769 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3770 "ret\t#eh_return, addr: $addr",
3771 [(X86ehret GR32:$addr)]>;
3775 //===----------------------------------------------------------------------===//
3779 // Atomic swap. These are just normal xchg instructions. But since a memory
3780 // operand is referenced, the atomicity is ensured.
3781 let Constraints = "$val = $dst" in {
3782 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3783 (ins GR32:$val, i32mem:$ptr),
3784 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3785 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3786 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3787 (ins GR16:$val, i16mem:$ptr),
3788 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3789 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3791 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3792 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3793 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3795 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3796 "xchg{l}\t{$val, $src|$src, $val}", []>;
3797 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3798 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3799 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3800 "xchg{b}\t{$val, $src|$src, $val}", []>;
3803 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3804 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3805 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3806 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3808 // Atomic compare and swap.
3809 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3810 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3812 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3813 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3815 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3816 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3819 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3822 let Defs = [AX, EFLAGS], Uses = [AX] in {
3823 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3825 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3826 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3828 let Defs = [AL, EFLAGS], Uses = [AL] in {
3829 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3831 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3832 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3835 // Atomic exchange and add
3836 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3837 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3839 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3840 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3842 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3844 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3845 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3847 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3849 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3850 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3854 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3855 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3856 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3857 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3858 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3859 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3861 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3862 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3863 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3864 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3865 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3866 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3868 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3869 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3870 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3871 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3872 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3873 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3875 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3876 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3877 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3878 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3879 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3880 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3882 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3883 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3884 "cmpxchg8b\t$dst", []>, TB;
3886 // Optimized codegen when the non-memory output is not used.
3887 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3888 let Defs = [EFLAGS] in {
3889 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3891 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3892 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3894 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3895 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3897 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3898 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3900 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3901 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3903 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3904 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3906 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3907 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3909 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3910 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3912 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3914 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3916 "inc{b}\t$dst", []>, LOCK;
3917 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3919 "inc{w}\t$dst", []>, OpSize, LOCK;
3920 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3922 "inc{l}\t$dst", []>, LOCK;
3924 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3926 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3927 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3929 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3930 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3932 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3933 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3935 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3936 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3938 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3939 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3941 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3942 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3944 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3945 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3947 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3949 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3951 "dec{b}\t$dst", []>, LOCK;
3952 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3954 "dec{w}\t$dst", []>, OpSize, LOCK;
3955 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3957 "dec{l}\t$dst", []>, LOCK;
3960 // Atomic exchange, and, or, xor
3961 let Constraints = "$val = $dst", Defs = [EFLAGS],
3962 usesCustomInserter = 1 in {
3963 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3964 "#ATOMAND32 PSEUDO!",
3965 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3966 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3967 "#ATOMOR32 PSEUDO!",
3968 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3969 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3970 "#ATOMXOR32 PSEUDO!",
3971 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3972 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3973 "#ATOMNAND32 PSEUDO!",
3974 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3975 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3976 "#ATOMMIN32 PSEUDO!",
3977 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3978 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3979 "#ATOMMAX32 PSEUDO!",
3980 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3981 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3982 "#ATOMUMIN32 PSEUDO!",
3983 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3984 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3985 "#ATOMUMAX32 PSEUDO!",
3986 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3988 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3989 "#ATOMAND16 PSEUDO!",
3990 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3991 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3992 "#ATOMOR16 PSEUDO!",
3993 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3994 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3995 "#ATOMXOR16 PSEUDO!",
3996 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3997 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3998 "#ATOMNAND16 PSEUDO!",
3999 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4000 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4001 "#ATOMMIN16 PSEUDO!",
4002 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4003 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4004 "#ATOMMAX16 PSEUDO!",
4005 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4006 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4007 "#ATOMUMIN16 PSEUDO!",
4008 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4009 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4010 "#ATOMUMAX16 PSEUDO!",
4011 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4013 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4014 "#ATOMAND8 PSEUDO!",
4015 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4016 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4018 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4019 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4020 "#ATOMXOR8 PSEUDO!",
4021 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4022 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4023 "#ATOMNAND8 PSEUDO!",
4024 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4027 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4028 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4029 Uses = [EAX, EBX, ECX, EDX],
4030 mayLoad = 1, mayStore = 1,
4031 usesCustomInserter = 1 in {
4032 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4033 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4034 "#ATOMAND6432 PSEUDO!", []>;
4035 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4036 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4037 "#ATOMOR6432 PSEUDO!", []>;
4038 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4039 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4040 "#ATOMXOR6432 PSEUDO!", []>;
4041 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4042 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4043 "#ATOMNAND6432 PSEUDO!", []>;
4044 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4045 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4046 "#ATOMADD6432 PSEUDO!", []>;
4047 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4048 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4049 "#ATOMSUB6432 PSEUDO!", []>;
4050 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4051 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4052 "#ATOMSWAP6432 PSEUDO!", []>;
4055 // Segmentation support instructions.
4057 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4058 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4059 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4060 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4062 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4063 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4064 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4065 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4066 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4068 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4069 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4070 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4071 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4072 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4073 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4074 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4075 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4077 def INVLPG : I<0x01, RawFrm, (outs), (ins), "invlpg", []>, TB;
4079 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4080 "str{w}\t{$dst}", []>, TB;
4081 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4082 "str{w}\t{$dst}", []>, TB;
4083 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4084 "ltr{w}\t{$src}", []>, TB;
4085 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4086 "ltr{w}\t{$src}", []>, TB;
4088 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4089 "push{w}\t%fs", []>, OpSize, TB;
4090 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4091 "push{l}\t%fs", []>, TB;
4092 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4093 "push{w}\t%gs", []>, OpSize, TB;
4094 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4095 "push{l}\t%gs", []>, TB;
4097 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4098 "pop{w}\t%fs", []>, OpSize, TB;
4099 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4100 "pop{l}\t%fs", []>, TB;
4101 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4102 "pop{w}\t%gs", []>, OpSize, TB;
4103 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4104 "pop{l}\t%gs", []>, TB;
4106 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4107 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4108 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4109 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4110 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4111 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4112 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4113 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4114 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4115 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4116 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4117 "les{l}\t{$src, $dst|$dst, $src}", []>;
4118 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4119 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4120 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4121 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4122 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4123 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4124 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4125 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4127 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4128 "verr\t$seg", []>, TB;
4129 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4130 "verr\t$seg", []>, TB;
4131 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4132 "verw\t$seg", []>, TB;
4133 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4134 "verw\t$seg", []>, TB;
4136 // Descriptor-table support instructions
4138 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4139 "sgdt\t$dst", []>, TB;
4140 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4141 "sidt\t$dst", []>, TB;
4142 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4143 "sldt{w}\t$dst", []>, TB;
4144 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4145 "sldt{w}\t$dst", []>, TB;
4146 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4147 "lgdt\t$src", []>, TB;
4148 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4149 "lidt\t$src", []>, TB;
4150 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4151 "lldt{w}\t$src", []>, TB;
4152 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4153 "lldt{w}\t$src", []>, TB;
4155 // String manipulation instructions
4157 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4158 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4159 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4161 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4162 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4163 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4165 // CPU flow control instructions
4167 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4168 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4170 // FPU control instructions
4172 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4174 // Flag instructions
4176 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4177 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4178 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4179 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4180 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4181 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4182 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4184 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4186 // Table lookup instructions
4188 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4190 // Specialized register support
4192 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4193 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4194 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4196 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4197 "smsw{w}\t$dst", []>, OpSize, TB;
4198 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4199 "smsw{l}\t$dst", []>, TB;
4200 // For memory operands, there is only a 16-bit form
4201 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4202 "smsw{w}\t$dst", []>, TB;
4204 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4205 "lmsw{w}\t$src", []>, TB;
4206 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4207 "lmsw{w}\t$src", []>, TB;
4209 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4211 // Cache instructions
4213 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4214 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4219 def INVEPT : I<0x38, RawFrm, (outs), (ins), "invept", []>, OpSize, TB;
4221 def INVVPID : I<0x38, RawFrm, (outs), (ins), "invvpid", []>, OpSize, TB;
4223 def VMCALL : I<0x01, RawFrm, (outs), (ins), "vmcall", []>, TB;
4224 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4225 "vmclear\t$vmcs", []>, OpSize, TB;
4227 def VMLAUNCH : I<0x01, RawFrm, (outs), (ins), "vmlaunch", []>, TB;
4229 def VMRESUME : I<0x01, RawFrm, (outs), (ins), "vmresume", []>, TB;
4230 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4231 "vmptrld\t$vmcs", []>, TB;
4232 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4233 "vmptrst\t$vmcs", []>, TB;
4234 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4235 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4236 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4237 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4238 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4239 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4240 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4241 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4242 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4243 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4244 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4245 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4246 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4247 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4248 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4249 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4251 def VMXOFF : I<0x01, RawFrm, (outs), (ins), "vmxoff", []>, OpSize;
4252 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4253 "vmxon\t{$vmxon}", []>, XD;
4255 //===----------------------------------------------------------------------===//
4256 // Non-Instruction Patterns
4257 //===----------------------------------------------------------------------===//
4259 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4260 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4261 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4262 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4263 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4264 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4265 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4267 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4268 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4269 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4270 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4271 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4272 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4273 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4274 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4275 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4276 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4278 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4279 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4280 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4281 (MOV32mi addr:$dst, texternalsym:$src)>;
4282 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4283 (MOV32mi addr:$dst, tblockaddress:$src)>;
4287 def : Pat<(X86tcret GR32:$dst, imm:$off),
4288 (TCRETURNri GR32:$dst, imm:$off)>;
4290 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4291 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4293 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4294 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4296 // Normal calls, with various flavors of addresses.
4297 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4298 (CALLpcrel32 tglobaladdr:$dst)>;
4299 def : Pat<(X86call (i32 texternalsym:$dst)),
4300 (CALLpcrel32 texternalsym:$dst)>;
4301 def : Pat<(X86call (i32 imm:$dst)),
4302 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4304 // X86 specific add which produces a flag.
4305 def : Pat<(addc GR32:$src1, GR32:$src2),
4306 (ADD32rr GR32:$src1, GR32:$src2)>;
4307 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4308 (ADD32rm GR32:$src1, addr:$src2)>;
4309 def : Pat<(addc GR32:$src1, imm:$src2),
4310 (ADD32ri GR32:$src1, imm:$src2)>;
4311 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4312 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4314 def : Pat<(subc GR32:$src1, GR32:$src2),
4315 (SUB32rr GR32:$src1, GR32:$src2)>;
4316 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4317 (SUB32rm GR32:$src1, addr:$src2)>;
4318 def : Pat<(subc GR32:$src1, imm:$src2),
4319 (SUB32ri GR32:$src1, imm:$src2)>;
4320 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4321 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4325 // TEST R,R is smaller than CMP R,0
4326 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
4327 (TEST8rr GR8:$src1, GR8:$src1)>;
4328 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
4329 (TEST16rr GR16:$src1, GR16:$src1)>;
4330 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
4331 (TEST32rr GR32:$src1, GR32:$src1)>;
4333 // Conditional moves with folded loads with operands swapped and conditions
4335 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4336 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4337 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4338 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4339 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4340 (CMOVB16rm GR16:$src2, addr:$src1)>;
4341 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4342 (CMOVB32rm GR32:$src2, addr:$src1)>;
4343 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4344 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4345 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4346 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4347 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4348 (CMOVE16rm GR16:$src2, addr:$src1)>;
4349 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4350 (CMOVE32rm GR32:$src2, addr:$src1)>;
4351 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4352 (CMOVA16rm GR16:$src2, addr:$src1)>;
4353 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4354 (CMOVA32rm GR32:$src2, addr:$src1)>;
4355 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4356 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4357 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4358 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4359 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4360 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4361 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4362 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4363 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4364 (CMOVL16rm GR16:$src2, addr:$src1)>;
4365 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4366 (CMOVL32rm GR32:$src2, addr:$src1)>;
4367 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4368 (CMOVG16rm GR16:$src2, addr:$src1)>;
4369 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4370 (CMOVG32rm GR32:$src2, addr:$src1)>;
4371 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4372 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4373 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4374 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4375 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4376 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4377 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4378 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4379 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4380 (CMOVP16rm GR16:$src2, addr:$src1)>;
4381 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4382 (CMOVP32rm GR32:$src2, addr:$src1)>;
4383 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4384 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4385 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4386 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4387 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4388 (CMOVS16rm GR16:$src2, addr:$src1)>;
4389 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4390 (CMOVS32rm GR32:$src2, addr:$src1)>;
4391 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4392 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4393 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4394 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4395 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4396 (CMOVO16rm GR16:$src2, addr:$src1)>;
4397 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4398 (CMOVO32rm GR32:$src2, addr:$src1)>;
4400 // zextload bool -> zextload byte
4401 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4402 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4403 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4405 // extload bool -> extload byte
4406 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4407 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4408 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4409 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4410 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4411 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4413 // anyext. Define these to do an explicit zero-extend to
4414 // avoid partial-register updates.
4415 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4416 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4417 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
4419 // (and (i32 load), 255) -> (zextload i8)
4420 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
4421 (MOVZX32rm8 addr:$src)>;
4422 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
4423 (MOVZX32rm16 addr:$src)>;
4425 //===----------------------------------------------------------------------===//
4427 //===----------------------------------------------------------------------===//
4429 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4430 // +128 doesn't, so in this special case use a sub instead of an add.
4431 def : Pat<(add GR16:$src1, 128),
4432 (SUB16ri8 GR16:$src1, -128)>;
4433 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4434 (SUB16mi8 addr:$dst, -128)>;
4435 def : Pat<(add GR32:$src1, 128),
4436 (SUB32ri8 GR32:$src1, -128)>;
4437 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4438 (SUB32mi8 addr:$dst, -128)>;
4440 // r & (2^16-1) ==> movz
4441 def : Pat<(and GR32:$src1, 0xffff),
4442 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4443 // r & (2^8-1) ==> movz
4444 def : Pat<(and GR32:$src1, 0xff),
4445 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4448 Requires<[In32BitMode]>;
4449 // r & (2^8-1) ==> movz
4450 def : Pat<(and GR16:$src1, 0xff),
4451 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4454 Requires<[In32BitMode]>;
4456 // sext_inreg patterns
4457 def : Pat<(sext_inreg GR32:$src, i16),
4458 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4459 def : Pat<(sext_inreg GR32:$src, i8),
4460 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4463 Requires<[In32BitMode]>;
4464 def : Pat<(sext_inreg GR16:$src, i8),
4465 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4468 Requires<[In32BitMode]>;
4471 def : Pat<(i16 (trunc GR32:$src)),
4472 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4473 def : Pat<(i8 (trunc GR32:$src)),
4474 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4476 Requires<[In32BitMode]>;
4477 def : Pat<(i8 (trunc GR16:$src)),
4478 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4480 Requires<[In32BitMode]>;
4482 // h-register tricks
4483 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4484 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4485 x86_subreg_8bit_hi)>,
4486 Requires<[In32BitMode]>;
4487 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4488 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4489 x86_subreg_8bit_hi)>,
4490 Requires<[In32BitMode]>;
4491 def : Pat<(srl GR16:$src, (i8 8)),
4494 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4495 x86_subreg_8bit_hi)),
4497 Requires<[In32BitMode]>;
4498 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4499 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4501 x86_subreg_8bit_hi))>,
4502 Requires<[In32BitMode]>;
4503 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4504 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4506 x86_subreg_8bit_hi))>,
4507 Requires<[In32BitMode]>;
4508 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4509 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4511 x86_subreg_8bit_hi))>,
4512 Requires<[In32BitMode]>;
4514 // (shl x, 1) ==> (add x, x)
4515 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4516 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4517 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4519 // (shl x (and y, 31)) ==> (shl x, y)
4520 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
4521 (SHL8rCL GR8:$src1)>;
4522 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
4523 (SHL16rCL GR16:$src1)>;
4524 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
4525 (SHL32rCL GR32:$src1)>;
4526 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4527 (SHL8mCL addr:$dst)>;
4528 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4529 (SHL16mCL addr:$dst)>;
4530 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4531 (SHL32mCL addr:$dst)>;
4533 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
4534 (SHR8rCL GR8:$src1)>;
4535 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
4536 (SHR16rCL GR16:$src1)>;
4537 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
4538 (SHR32rCL GR32:$src1)>;
4539 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4540 (SHR8mCL addr:$dst)>;
4541 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4542 (SHR16mCL addr:$dst)>;
4543 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4544 (SHR32mCL addr:$dst)>;
4546 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
4547 (SAR8rCL GR8:$src1)>;
4548 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
4549 (SAR16rCL GR16:$src1)>;
4550 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
4551 (SAR32rCL GR32:$src1)>;
4552 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4553 (SAR8mCL addr:$dst)>;
4554 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4555 (SAR16mCL addr:$dst)>;
4556 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4557 (SAR32mCL addr:$dst)>;
4559 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
4560 def : Pat<(or (srl GR32:$src1, CL:$amt),
4561 (shl GR32:$src2, (sub 32, CL:$amt))),
4562 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4564 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
4565 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4566 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4568 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
4569 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4570 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4572 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4573 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4575 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4577 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
4578 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4580 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
4581 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
4582 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4584 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
4585 def : Pat<(or (shl GR32:$src1, CL:$amt),
4586 (srl GR32:$src2, (sub 32, CL:$amt))),
4587 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4589 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
4590 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4591 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4593 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
4594 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4595 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4597 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4598 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4600 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4602 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
4603 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4605 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
4606 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
4607 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4609 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
4610 def : Pat<(or (srl GR16:$src1, CL:$amt),
4611 (shl GR16:$src2, (sub 16, CL:$amt))),
4612 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4614 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
4615 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4616 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4618 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
4619 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4620 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4622 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4623 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4625 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4627 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
4628 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4630 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
4631 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
4632 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4634 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
4635 def : Pat<(or (shl GR16:$src1, CL:$amt),
4636 (srl GR16:$src2, (sub 16, CL:$amt))),
4637 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4639 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
4640 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4641 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4643 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
4644 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4645 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4647 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4648 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4650 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4652 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
4653 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4655 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
4656 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
4657 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4659 // (anyext (setcc_carry)) -> (setcc_carry)
4660 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4662 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4665 // (or x, c) -> (add x, c) if masked bits are known zero.
4666 def : Pat<(parallel (or_is_add GR8:$src1, imm:$src2),
4668 (ADD8ri GR8:$src1, imm:$src2)>;
4669 def : Pat<(parallel (or_is_add GR16:$src1, imm:$src2),
4671 (ADD16ri GR16:$src1, imm:$src2)>;
4672 def : Pat<(parallel (or_is_add GR32:$src1, imm:$src2),
4674 (ADD32ri GR32:$src1, imm:$src2)>;
4675 def : Pat<(parallel (or_is_add GR16:$src1, i16immSExt8:$src2),
4677 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4678 def : Pat<(parallel (or_is_add GR32:$src1, i32immSExt8:$src2),
4680 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4682 //===----------------------------------------------------------------------===//
4683 // EFLAGS-defining Patterns
4684 //===----------------------------------------------------------------------===//
4686 // Register-Register Addition with EFLAGS result
4687 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
4689 (ADD8rr GR8:$src1, GR8:$src2)>;
4690 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
4692 (ADD16rr GR16:$src1, GR16:$src2)>;
4693 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
4695 (ADD32rr GR32:$src1, GR32:$src2)>;
4697 // Register-Memory Addition with EFLAGS result
4698 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
4700 (ADD8rm GR8:$src1, addr:$src2)>;
4701 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
4703 (ADD16rm GR16:$src1, addr:$src2)>;
4704 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
4706 (ADD32rm GR32:$src1, addr:$src2)>;
4708 // Register-Integer Addition with EFLAGS result
4709 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
4711 (ADD8ri GR8:$src1, imm:$src2)>;
4712 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
4714 (ADD16ri GR16:$src1, imm:$src2)>;
4715 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
4717 (ADD32ri GR32:$src1, imm:$src2)>;
4718 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
4720 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4721 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
4723 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4725 // Memory-Register Addition with EFLAGS result
4726 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
4729 (ADD8mr addr:$dst, GR8:$src2)>;
4730 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
4733 (ADD16mr addr:$dst, GR16:$src2)>;
4734 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
4737 (ADD32mr addr:$dst, GR32:$src2)>;
4739 // Memory-Integer Addition with EFLAGS result
4740 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
4743 (ADD8mi addr:$dst, imm:$src2)>;
4744 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
4747 (ADD16mi addr:$dst, imm:$src2)>;
4748 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
4751 (ADD32mi addr:$dst, imm:$src2)>;
4752 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4755 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
4756 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4759 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
4761 // Register-Register Subtraction with EFLAGS result
4762 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
4764 (SUB8rr GR8:$src1, GR8:$src2)>;
4765 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
4767 (SUB16rr GR16:$src1, GR16:$src2)>;
4768 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
4770 (SUB32rr GR32:$src1, GR32:$src2)>;
4772 // Register-Memory Subtraction with EFLAGS result
4773 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
4775 (SUB8rm GR8:$src1, addr:$src2)>;
4776 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
4778 (SUB16rm GR16:$src1, addr:$src2)>;
4779 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
4781 (SUB32rm GR32:$src1, addr:$src2)>;
4783 // Register-Integer Subtraction with EFLAGS result
4784 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
4786 (SUB8ri GR8:$src1, imm:$src2)>;
4787 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
4789 (SUB16ri GR16:$src1, imm:$src2)>;
4790 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
4792 (SUB32ri GR32:$src1, imm:$src2)>;
4793 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
4795 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4796 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
4798 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4800 // Memory-Register Subtraction with EFLAGS result
4801 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
4804 (SUB8mr addr:$dst, GR8:$src2)>;
4805 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
4808 (SUB16mr addr:$dst, GR16:$src2)>;
4809 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
4812 (SUB32mr addr:$dst, GR32:$src2)>;
4814 // Memory-Integer Subtraction with EFLAGS result
4815 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
4818 (SUB8mi addr:$dst, imm:$src2)>;
4819 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
4822 (SUB16mi addr:$dst, imm:$src2)>;
4823 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4826 (SUB32mi addr:$dst, imm:$src2)>;
4827 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4830 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4831 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4834 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4837 // Register-Register Signed Integer Multiply with EFLAGS result
4838 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4840 (IMUL16rr GR16:$src1, GR16:$src2)>;
4841 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4843 (IMUL32rr GR32:$src1, GR32:$src2)>;
4845 // Register-Memory Signed Integer Multiply with EFLAGS result
4846 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4848 (IMUL16rm GR16:$src1, addr:$src2)>;
4849 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4851 (IMUL32rm GR32:$src1, addr:$src2)>;
4853 // Register-Integer Signed Integer Multiply with EFLAGS result
4854 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4856 (IMUL16rri GR16:$src1, imm:$src2)>;
4857 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4859 (IMUL32rri GR32:$src1, imm:$src2)>;
4860 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4862 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4863 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4865 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4867 // Memory-Integer Signed Integer Multiply with EFLAGS result
4868 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4870 (IMUL16rmi addr:$src1, imm:$src2)>;
4871 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4873 (IMUL32rmi addr:$src1, imm:$src2)>;
4874 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4876 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4877 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4879 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4881 // Optimize multiply by 2 with EFLAGS result.
4882 let AddedComplexity = 2 in {
4883 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4885 (ADD16rr GR16:$src1, GR16:$src1)>;
4887 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4889 (ADD32rr GR32:$src1, GR32:$src1)>;
4892 // INC and DEC with EFLAGS result. Note that these do not set CF.
4893 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4895 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4898 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4900 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4904 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4905 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4906 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4908 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4909 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4910 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4911 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4913 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4915 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4916 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4917 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4919 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4920 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4921 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4922 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4924 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4926 // Register-Register Or with EFLAGS result
4927 def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
4929 (OR8rr GR8:$src1, GR8:$src2)>;
4930 def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2),
4932 (OR16rr GR16:$src1, GR16:$src2)>;
4933 def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2),
4935 (OR32rr GR32:$src1, GR32:$src2)>;
4937 // Register-Memory Or with EFLAGS result
4938 def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)),
4940 (OR8rm GR8:$src1, addr:$src2)>;
4941 def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)),
4943 (OR16rm GR16:$src1, addr:$src2)>;
4944 def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)),
4946 (OR32rm GR32:$src1, addr:$src2)>;
4948 // Register-Integer Or with EFLAGS result
4949 def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2),
4951 (OR8ri GR8:$src1, imm:$src2)>;
4952 def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2),
4954 (OR16ri GR16:$src1, imm:$src2)>;
4955 def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2),
4957 (OR32ri GR32:$src1, imm:$src2)>;
4958 def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
4960 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4961 def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
4963 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4965 // Memory-Register Or with EFLAGS result
4966 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
4969 (OR8mr addr:$dst, GR8:$src2)>;
4970 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2),
4973 (OR16mr addr:$dst, GR16:$src2)>;
4974 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2),
4977 (OR32mr addr:$dst, GR32:$src2)>;
4979 // Memory-Integer Or with EFLAGS result
4980 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2),
4983 (OR8mi addr:$dst, imm:$src2)>;
4984 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2),
4987 (OR16mi addr:$dst, imm:$src2)>;
4988 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2),
4991 (OR32mi addr:$dst, imm:$src2)>;
4992 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4995 (OR16mi8 addr:$dst, i16immSExt8:$src2)>;
4996 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4999 (OR32mi8 addr:$dst, i32immSExt8:$src2)>;
5001 // Register-Register XOr with EFLAGS result
5002 def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
5004 (XOR8rr GR8:$src1, GR8:$src2)>;
5005 def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2),
5007 (XOR16rr GR16:$src1, GR16:$src2)>;
5008 def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2),
5010 (XOR32rr GR32:$src1, GR32:$src2)>;
5012 // Register-Memory XOr with EFLAGS result
5013 def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)),
5015 (XOR8rm GR8:$src1, addr:$src2)>;
5016 def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)),
5018 (XOR16rm GR16:$src1, addr:$src2)>;
5019 def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)),
5021 (XOR32rm GR32:$src1, addr:$src2)>;
5023 // Register-Integer XOr with EFLAGS result
5024 def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2),
5026 (XOR8ri GR8:$src1, imm:$src2)>;
5027 def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2),
5029 (XOR16ri GR16:$src1, imm:$src2)>;
5030 def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2),
5032 (XOR32ri GR32:$src1, imm:$src2)>;
5033 def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2),
5035 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
5036 def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
5038 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
5040 // Memory-Register XOr with EFLAGS result
5041 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
5044 (XOR8mr addr:$dst, GR8:$src2)>;
5045 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2),
5048 (XOR16mr addr:$dst, GR16:$src2)>;
5049 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2),
5052 (XOR32mr addr:$dst, GR32:$src2)>;
5054 // Memory-Integer XOr with EFLAGS result
5055 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2),
5058 (XOR8mi addr:$dst, imm:$src2)>;
5059 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2),
5062 (XOR16mi addr:$dst, imm:$src2)>;
5063 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2),
5066 (XOR32mi addr:$dst, imm:$src2)>;
5067 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5070 (XOR16mi8 addr:$dst, i16immSExt8:$src2)>;
5071 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5074 (XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
5076 // Register-Register And with EFLAGS result
5077 def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
5079 (AND8rr GR8:$src1, GR8:$src2)>;
5080 def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2),
5082 (AND16rr GR16:$src1, GR16:$src2)>;
5083 def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2),
5085 (AND32rr GR32:$src1, GR32:$src2)>;
5087 // Register-Memory And with EFLAGS result
5088 def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)),
5090 (AND8rm GR8:$src1, addr:$src2)>;
5091 def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)),
5093 (AND16rm GR16:$src1, addr:$src2)>;
5094 def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)),
5096 (AND32rm GR32:$src1, addr:$src2)>;
5098 // Register-Integer And with EFLAGS result
5099 def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2),
5101 (AND8ri GR8:$src1, imm:$src2)>;
5102 def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2),
5104 (AND16ri GR16:$src1, imm:$src2)>;
5105 def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2),
5107 (AND32ri GR32:$src1, imm:$src2)>;
5108 def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2),
5110 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
5111 def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
5113 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
5115 // Memory-Register And with EFLAGS result
5116 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
5119 (AND8mr addr:$dst, GR8:$src2)>;
5120 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2),
5123 (AND16mr addr:$dst, GR16:$src2)>;
5124 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2),
5127 (AND32mr addr:$dst, GR32:$src2)>;
5129 // Memory-Integer And with EFLAGS result
5130 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2),
5133 (AND8mi addr:$dst, imm:$src2)>;
5134 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2),
5137 (AND16mi addr:$dst, imm:$src2)>;
5138 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2),
5141 (AND32mi addr:$dst, imm:$src2)>;
5142 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5145 (AND16mi8 addr:$dst, i16immSExt8:$src2)>;
5146 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5149 (AND32mi8 addr:$dst, i32immSExt8:$src2)>;
5151 // -disable-16bit support.
5152 def : Pat<(truncstorei16 (i32 imm:$src), addr:$dst),
5153 (MOV16mi addr:$dst, imm:$src)>;
5154 def : Pat<(truncstorei16 GR32:$src, addr:$dst),
5155 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
5156 def : Pat<(i32 (sextloadi16 addr:$dst)),
5157 (MOVSX32rm16 addr:$dst)>;
5158 def : Pat<(i32 (zextloadi16 addr:$dst)),
5159 (MOVZX32rm16 addr:$dst)>;
5160 def : Pat<(i32 (extloadi16 addr:$dst)),
5161 (MOVZX32rm16 addr:$dst)>;
5163 //===----------------------------------------------------------------------===//
5164 // Floating Point Stack Support
5165 //===----------------------------------------------------------------------===//
5167 include "X86InstrFPStack.td"
5169 //===----------------------------------------------------------------------===//
5171 //===----------------------------------------------------------------------===//
5173 include "X86Instr64bit.td"
5175 //===----------------------------------------------------------------------===//
5176 // XMM Floating point support (requires SSE / SSE2)
5177 //===----------------------------------------------------------------------===//
5179 include "X86InstrSSE.td"
5181 //===----------------------------------------------------------------------===//
5182 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
5183 //===----------------------------------------------------------------------===//
5185 include "X86InstrMMX.td"