1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
30 def SDTX86BrCond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
33 def SDTX86SetCC : SDTypeProfile<1, 1,
34 [SDTCisVT<0, i8>, SDTCisVT<1, i8>]>;
36 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
38 def SDT_X86CallSeqStart : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
39 def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
42 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
44 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
46 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
48 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
51 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
53 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest,
54 [SDNPHasChain, SDNPOutFlag]>;
56 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov,
57 [SDNPInFlag, SDNPOutFlag]>;
58 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
59 [SDNPHasChain, SDNPInFlag]>;
60 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC,
61 [SDNPInFlag, SDNPOutFlag]>;
63 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
64 [SDNPHasChain, SDNPOptInFlag]>;
66 def X86callseq_start :
67 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
68 [SDNPHasChain, SDNPOutFlag]>;
70 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
71 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
73 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
74 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
76 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
77 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
79 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
80 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
81 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
82 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
84 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
85 [SDNPHasChain, SDNPOutFlag]>;
87 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
88 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
90 //===----------------------------------------------------------------------===//
91 // X86 Operand Definitions.
94 // *mem - Operand definitions for the funky X86 addressing mode operands.
96 class X86MemOperand<string printMethod> : Operand<iPTR> {
97 let PrintMethod = printMethod;
98 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
101 def i8mem : X86MemOperand<"printi8mem">;
102 def i16mem : X86MemOperand<"printi16mem">;
103 def i32mem : X86MemOperand<"printi32mem">;
104 def i64mem : X86MemOperand<"printi64mem">;
105 def i128mem : X86MemOperand<"printi128mem">;
106 def f32mem : X86MemOperand<"printf32mem">;
107 def f64mem : X86MemOperand<"printf64mem">;
108 def f128mem : X86MemOperand<"printf128mem">;
110 def lea32mem : Operand<i32> {
111 let PrintMethod = "printi32mem";
112 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
115 def SSECC : Operand<i8> {
116 let PrintMethod = "printSSECC";
119 def piclabel: Operand<i32> {
120 let PrintMethod = "printPICLabel";
123 // A couple of more descriptive operand definitions.
124 // 16-bits but only 8 bits are significant.
125 def i16i8imm : Operand<i16>;
126 // 32-bits but only 8 bits are significant.
127 def i32i8imm : Operand<i32>;
129 // Branch targets have OtherVT type.
130 def brtarget : Operand<OtherVT>;
132 //===----------------------------------------------------------------------===//
133 // X86 Complex Pattern Definitions.
136 // Define X86 specific addressing mode.
137 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
138 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
139 [add, mul, shl, or, frameindex], []>;
141 //===----------------------------------------------------------------------===//
142 // X86 Instruction Format Definitions.
145 // Format specifies the encoding used by the instruction. This is part of the
146 // ad-hoc solution used to emit machine instruction encodings by our machine
148 class Format<bits<6> val> {
152 def Pseudo : Format<0>; def RawFrm : Format<1>;
153 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
154 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
155 def MRMSrcMem : Format<6>;
156 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
157 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
158 def MRM6r : Format<22>; def MRM7r : Format<23>;
159 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
160 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
161 def MRM6m : Format<30>; def MRM7m : Format<31>;
162 def MRMInitReg : Format<32>;
164 //===----------------------------------------------------------------------===//
165 // X86 Instruction Predicate Definitions.
166 def HasMMX : Predicate<"Subtarget->hasMMX()">;
167 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
168 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
169 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
170 def FPStack : Predicate<"!Subtarget->hasSSE2()">;
171 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
172 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
173 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
174 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
175 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
177 //===----------------------------------------------------------------------===//
178 // X86 specific pattern fragments.
181 // ImmType - This specifies the immediate type used by an instruction. This is
182 // part of the ad-hoc solution used to emit machine instruction encodings by our
183 // machine code emitter.
184 class ImmType<bits<3> val> {
187 def NoImm : ImmType<0>;
188 def Imm8 : ImmType<1>;
189 def Imm16 : ImmType<2>;
190 def Imm32 : ImmType<3>;
191 def Imm64 : ImmType<4>;
193 // FPFormat - This specifies what form this FP instruction has. This is used by
194 // the Floating-Point stackifier pass.
195 class FPFormat<bits<3> val> {
198 def NotFP : FPFormat<0>;
199 def ZeroArgFP : FPFormat<1>;
200 def OneArgFP : FPFormat<2>;
201 def OneArgFPRW : FPFormat<3>;
202 def TwoArgFP : FPFormat<4>;
203 def CompareFP : FPFormat<5>;
204 def CondMovFP : FPFormat<6>;
205 def SpecialFP : FPFormat<7>;
208 class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr>
210 let Namespace = "X86";
212 bits<8> Opcode = opcod;
214 bits<6> FormBits = Form.Value;
216 bits<3> ImmTypeBits = ImmT.Value;
218 dag OperandList = ops;
219 string AsmString = AsmStr;
222 // Attributes specific to X86 instructions...
224 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
225 bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
227 bits<4> Prefix = 0; // Which prefix byte does this inst have?
228 bit hasREX_WPrefix = 0; // Does this inst requires the REX.W prefix?
229 FPFormat FPForm; // What flavor of FP instruction is this?
230 bits<3> FPFormBits = 0;
234 // Prefix byte classes which are used to indicate to the ad-hoc machine code
235 // emitter that various prefix bytes are required.
236 class OpSize { bit hasOpSizePrefix = 1; }
237 class AdSize { bit hasAdSizePrefix = 1; }
238 class REX_W { bit hasREX_WPrefix = 1; }
239 class TB { bits<4> Prefix = 1; }
240 class REP { bits<4> Prefix = 2; }
241 class D8 { bits<4> Prefix = 3; }
242 class D9 { bits<4> Prefix = 4; }
243 class DA { bits<4> Prefix = 5; }
244 class DB { bits<4> Prefix = 6; }
245 class DC { bits<4> Prefix = 7; }
246 class DD { bits<4> Prefix = 8; }
247 class DE { bits<4> Prefix = 9; }
248 class DF { bits<4> Prefix = 10; }
249 class XD { bits<4> Prefix = 11; }
250 class XS { bits<4> Prefix = 12; }
253 //===----------------------------------------------------------------------===//
254 // Pattern fragments...
257 // X86 specific condition code. These correspond to CondCode in
258 // X86ISelLowering.h. They must be kept in synch.
259 def X86_COND_A : PatLeaf<(i8 0)>;
260 def X86_COND_AE : PatLeaf<(i8 1)>;
261 def X86_COND_B : PatLeaf<(i8 2)>;
262 def X86_COND_BE : PatLeaf<(i8 3)>;
263 def X86_COND_E : PatLeaf<(i8 4)>;
264 def X86_COND_G : PatLeaf<(i8 5)>;
265 def X86_COND_GE : PatLeaf<(i8 6)>;
266 def X86_COND_L : PatLeaf<(i8 7)>;
267 def X86_COND_LE : PatLeaf<(i8 8)>;
268 def X86_COND_NE : PatLeaf<(i8 9)>;
269 def X86_COND_NO : PatLeaf<(i8 10)>;
270 def X86_COND_NP : PatLeaf<(i8 11)>;
271 def X86_COND_NS : PatLeaf<(i8 12)>;
272 def X86_COND_O : PatLeaf<(i8 13)>;
273 def X86_COND_P : PatLeaf<(i8 14)>;
274 def X86_COND_S : PatLeaf<(i8 15)>;
276 def i16immSExt8 : PatLeaf<(i16 imm), [{
277 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
278 // sign extended field.
279 return (int16_t)N->getValue() == (int8_t)N->getValue();
282 def i32immSExt8 : PatLeaf<(i32 imm), [{
283 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
284 // sign extended field.
285 return (int32_t)N->getValue() == (int8_t)N->getValue();
288 // Helper fragments for loads.
289 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
290 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
291 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
292 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
294 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
295 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
297 def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextloadi1 node:$ptr))>;
298 def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextloadi1 node:$ptr))>;
299 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
300 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
301 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
303 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
304 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
305 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
306 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
307 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
308 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
310 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
311 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
312 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
313 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
314 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
315 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
317 //===----------------------------------------------------------------------===//
318 // Instruction templates...
321 class I<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
322 : X86Inst<o, f, NoImm, ops, asm> {
323 let Pattern = pattern;
326 class Ii8 <bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
327 : X86Inst<o, f, Imm8 , ops, asm> {
328 let Pattern = pattern;
331 class Ii16<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
332 : X86Inst<o, f, Imm16, ops, asm> {
333 let Pattern = pattern;
336 class Ii32<bits<8> o, Format f, dag ops, string asm, list<dag> pattern>
337 : X86Inst<o, f, Imm32, ops, asm> {
338 let Pattern = pattern;
342 //===----------------------------------------------------------------------===//
343 // Instruction list...
346 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
347 // a stack adjustment and the codegen must know that they may modify the stack
348 // pointer before prolog-epilog rewriting occurs.
349 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops i32imm:$amt), "#ADJCALLSTACKDOWN",
350 [(X86callseq_start imm:$amt)]>, Imp<[ESP],[ESP]>;
351 def ADJCALLSTACKUP : I<0, Pseudo, (ops i32imm:$amt1, i32imm:$amt2),
353 [(X86callseq_end imm:$amt1, imm:$amt2)]>,
355 def IMPLICIT_USE : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_USE", []>;
356 def IMPLICIT_DEF : I<0, Pseudo, (ops variable_ops), "#IMPLICIT_DEF", []>;
357 def IMPLICIT_DEF_GR8 : I<0, Pseudo, (ops GR8:$dst),
358 "#IMPLICIT_DEF $dst",
359 [(set GR8:$dst, (undef))]>;
360 def IMPLICIT_DEF_GR16 : I<0, Pseudo, (ops GR16:$dst),
361 "#IMPLICIT_DEF $dst",
362 [(set GR16:$dst, (undef))]>;
363 def IMPLICIT_DEF_GR32 : I<0, Pseudo, (ops GR32:$dst),
364 "#IMPLICIT_DEF $dst",
365 [(set GR32:$dst, (undef))]>;
368 def NOOP : I<0x90, RawFrm, (ops), "nop", []>;
371 def TRUNC_32_to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR32_:$src),
372 "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}", []>;
373 def TRUNC_16_to8 : I<0x88, MRMDestReg, (ops GR8:$dst, GR16_:$src),
374 "mov{b} {${src:subreg8}, $dst|$dst, ${src:subreg8}}", []>;
375 def TRUNC_32to16 : I<0x89, MRMDestReg, (ops GR16:$dst, GR32:$src),
376 "mov{w} {${src:subreg16}, $dst|$dst, ${src:subreg16}}",
377 [(set GR16:$dst, (trunc GR32:$src))]>;
379 //===----------------------------------------------------------------------===//
380 // Control Flow Instructions...
383 // Return instructions.
384 let isTerminator = 1, isReturn = 1, isBarrier = 1,
385 hasCtrlDep = 1, noResults = 1 in {
386 def RET : I<0xC3, RawFrm, (ops), "ret", [(X86retflag 0)]>;
387 def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt",
388 [(X86retflag imm:$amt)]>;
391 // All branches are RawFrm, Void, Branch, and Terminators
392 let isBranch = 1, isTerminator = 1, noResults = 1 in
393 class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> :
394 I<opcode, RawFrm, ops, asm, pattern>;
397 let isBranch = 1, isBarrier = 1 in
398 def JMP : IBr<0xE9, (ops brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
400 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in {
401 def JMP32r : I<0xFF, MRM4r, (ops GR32:$dst), "jmp{l} {*}$dst",
402 [(brind GR32:$dst)]>;
403 def JMP32m : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp{l} {*}$dst",
404 [(brind (loadi32 addr:$dst))]>;
407 // Conditional branches
408 def JE : IBr<0x84, (ops brtarget:$dst), "je $dst",
409 [(X86brcond bb:$dst, X86_COND_E)]>, TB;
410 def JNE : IBr<0x85, (ops brtarget:$dst), "jne $dst",
411 [(X86brcond bb:$dst, X86_COND_NE)]>, TB;
412 def JL : IBr<0x8C, (ops brtarget:$dst), "jl $dst",
413 [(X86brcond bb:$dst, X86_COND_L)]>, TB;
414 def JLE : IBr<0x8E, (ops brtarget:$dst), "jle $dst",
415 [(X86brcond bb:$dst, X86_COND_LE)]>, TB;
416 def JG : IBr<0x8F, (ops brtarget:$dst), "jg $dst",
417 [(X86brcond bb:$dst, X86_COND_G)]>, TB;
418 def JGE : IBr<0x8D, (ops brtarget:$dst), "jge $dst",
419 [(X86brcond bb:$dst, X86_COND_GE)]>, TB;
421 def JB : IBr<0x82, (ops brtarget:$dst), "jb $dst",
422 [(X86brcond bb:$dst, X86_COND_B)]>, TB;
423 def JBE : IBr<0x86, (ops brtarget:$dst), "jbe $dst",
424 [(X86brcond bb:$dst, X86_COND_BE)]>, TB;
425 def JA : IBr<0x87, (ops brtarget:$dst), "ja $dst",
426 [(X86brcond bb:$dst, X86_COND_A)]>, TB;
427 def JAE : IBr<0x83, (ops brtarget:$dst), "jae $dst",
428 [(X86brcond bb:$dst, X86_COND_AE)]>, TB;
430 def JS : IBr<0x88, (ops brtarget:$dst), "js $dst",
431 [(X86brcond bb:$dst, X86_COND_S)]>, TB;
432 def JNS : IBr<0x89, (ops brtarget:$dst), "jns $dst",
433 [(X86brcond bb:$dst, X86_COND_NS)]>, TB;
434 def JP : IBr<0x8A, (ops brtarget:$dst), "jp $dst",
435 [(X86brcond bb:$dst, X86_COND_P)]>, TB;
436 def JNP : IBr<0x8B, (ops brtarget:$dst), "jnp $dst",
437 [(X86brcond bb:$dst, X86_COND_NP)]>, TB;
438 def JO : IBr<0x80, (ops brtarget:$dst), "jo $dst",
439 [(X86brcond bb:$dst, X86_COND_O)]>, TB;
440 def JNO : IBr<0x81, (ops brtarget:$dst), "jno $dst",
441 [(X86brcond bb:$dst, X86_COND_NO)]>, TB;
443 //===----------------------------------------------------------------------===//
444 // Call Instructions...
446 let isCall = 1, noResults = 1 in
447 // All calls clobber the non-callee saved registers...
448 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
449 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
450 def CALLpcrel32 : I<0xE8, RawFrm, (ops i32imm:$dst, variable_ops),
451 "call ${dst:call}", []>;
452 def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
453 "call {*}$dst", [(X86call GR32:$dst)]>;
454 def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst, variable_ops),
459 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
460 def TAILJMPd : IBr<0xE9, (ops i32imm:$dst), "jmp ${dst:call} # TAIL CALL",
462 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
463 def TAILJMPr : I<0xFF, MRM4r, (ops GR32:$dst), "jmp {*}$dst # TAIL CALL",
465 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
466 def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst),
467 "jmp {*}$dst # TAIL CALL", []>;
469 //===----------------------------------------------------------------------===//
470 // Miscellaneous Instructions...
472 def LEAVE : I<0xC9, RawFrm,
473 (ops), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>;
474 def POP32r : I<0x58, AddRegFrm,
475 (ops GR32:$reg), "pop{l} $reg", []>, Imp<[ESP],[ESP]>;
477 def MovePCtoStack : I<0, Pseudo, (ops piclabel:$label),
480 let isTwoAddress = 1 in // GR32 = bswap GR32
481 def BSWAP32r : I<0xC8, AddRegFrm,
482 (ops GR32:$dst, GR32:$src),
484 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
486 def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
487 (ops GR8:$src1, GR8:$src2),
488 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
489 def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16
490 (ops GR16:$src1, GR16:$src2),
491 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
492 def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
493 (ops GR32:$src1, GR32:$src2),
494 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
496 def XCHG8mr : I<0x86, MRMDestMem,
497 (ops i8mem:$src1, GR8:$src2),
498 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
499 def XCHG16mr : I<0x87, MRMDestMem,
500 (ops i16mem:$src1, GR16:$src2),
501 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
502 def XCHG32mr : I<0x87, MRMDestMem,
503 (ops i32mem:$src1, GR32:$src2),
504 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
505 def XCHG8rm : I<0x86, MRMSrcMem,
506 (ops GR8:$src1, i8mem:$src2),
507 "xchg{b} {$src2|$src1}, {$src1|$src2}", []>;
508 def XCHG16rm : I<0x87, MRMSrcMem,
509 (ops GR16:$src1, i16mem:$src2),
510 "xchg{w} {$src2|$src1}, {$src1|$src2}", []>, OpSize;
511 def XCHG32rm : I<0x87, MRMSrcMem,
512 (ops GR32:$src1, i32mem:$src2),
513 "xchg{l} {$src2|$src1}, {$src1|$src2}", []>;
515 def LEA16r : I<0x8D, MRMSrcMem,
516 (ops GR16:$dst, i32mem:$src),
517 "lea{w} {$src|$dst}, {$dst|$src}", []>, OpSize;
518 def LEA32r : I<0x8D, MRMSrcMem,
519 (ops GR32:$dst, lea32mem:$src),
520 "lea{l} {$src|$dst}, {$dst|$src}",
521 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
523 def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}",
525 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
526 def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}",
527 [(X86rep_movs i16)]>,
528 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
529 def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsl|rep movsd}",
530 [(X86rep_movs i32)]>,
531 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
533 def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}",
535 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
536 def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}",
537 [(X86rep_stos i16)]>,
538 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
539 def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}",
540 [(X86rep_stos i32)]>,
541 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
543 def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>,
544 TB, Imp<[],[RAX,RDX]>;
546 //===----------------------------------------------------------------------===//
547 // Input/Output Instructions...
549 def IN8rr : I<0xEC, RawFrm, (ops),
550 "in{b} {%dx, %al|%AL, %DX}",
551 []>, Imp<[DX], [AL]>;
552 def IN16rr : I<0xED, RawFrm, (ops),
553 "in{w} {%dx, %ax|%AX, %DX}",
554 []>, Imp<[DX], [AX]>, OpSize;
555 def IN32rr : I<0xED, RawFrm, (ops),
556 "in{l} {%dx, %eax|%EAX, %DX}",
557 []>, Imp<[DX],[EAX]>;
559 def IN8ri : Ii8<0xE4, RawFrm, (ops i16i8imm:$port),
560 "in{b} {$port, %al|%AL, $port}",
563 def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
564 "in{w} {$port, %ax|%AX, $port}",
566 Imp<[], [AX]>, OpSize;
567 def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
568 "in{l} {$port, %eax|%EAX, $port}",
572 def OUT8rr : I<0xEE, RawFrm, (ops),
573 "out{b} {%al, %dx|%DX, %AL}",
574 []>, Imp<[DX, AL], []>;
575 def OUT16rr : I<0xEF, RawFrm, (ops),
576 "out{w} {%ax, %dx|%DX, %AX}",
577 []>, Imp<[DX, AX], []>, OpSize;
578 def OUT32rr : I<0xEF, RawFrm, (ops),
579 "out{l} {%eax, %dx|%DX, %EAX}",
580 []>, Imp<[DX, EAX], []>;
582 def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
583 "out{b} {%al, $port|$port, %AL}",
586 def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
587 "out{w} {%ax, $port|$port, %AX}",
589 Imp<[AX], []>, OpSize;
590 def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
591 "out{l} {%eax, $port|$port, %EAX}",
595 //===----------------------------------------------------------------------===//
596 // Move Instructions...
598 def MOV8rr : I<0x88, MRMDestReg, (ops GR8 :$dst, GR8 :$src),
599 "mov{b} {$src, $dst|$dst, $src}", []>;
600 def MOV16rr : I<0x89, MRMDestReg, (ops GR16:$dst, GR16:$src),
601 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
602 def MOV32rr : I<0x89, MRMDestReg, (ops GR32:$dst, GR32:$src),
603 "mov{l} {$src, $dst|$dst, $src}", []>;
604 let isReMaterializable = 1 in {
605 def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops GR8 :$dst, i8imm :$src),
606 "mov{b} {$src, $dst|$dst, $src}",
607 [(set GR8:$dst, imm:$src)]>;
608 def MOV16ri : Ii16<0xB8, AddRegFrm, (ops GR16:$dst, i16imm:$src),
609 "mov{w} {$src, $dst|$dst, $src}",
610 [(set GR16:$dst, imm:$src)]>, OpSize;
611 def MOV32ri : Ii32<0xB8, AddRegFrm, (ops GR32:$dst, i32imm:$src),
612 "mov{l} {$src, $dst|$dst, $src}",
613 [(set GR32:$dst, imm:$src)]>;
615 def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
616 "mov{b} {$src, $dst|$dst, $src}",
617 [(store (i8 imm:$src), addr:$dst)]>;
618 def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src),
619 "mov{w} {$src, $dst|$dst, $src}",
620 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
621 def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src),
622 "mov{l} {$src, $dst|$dst, $src}",
623 [(store (i32 imm:$src), addr:$dst)]>;
625 def MOV8rm : I<0x8A, MRMSrcMem, (ops GR8 :$dst, i8mem :$src),
626 "mov{b} {$src, $dst|$dst, $src}",
627 [(set GR8:$dst, (load addr:$src))]>;
628 def MOV16rm : I<0x8B, MRMSrcMem, (ops GR16:$dst, i16mem:$src),
629 "mov{w} {$src, $dst|$dst, $src}",
630 [(set GR16:$dst, (load addr:$src))]>, OpSize;
631 def MOV32rm : I<0x8B, MRMSrcMem, (ops GR32:$dst, i32mem:$src),
632 "mov{l} {$src, $dst|$dst, $src}",
633 [(set GR32:$dst, (load addr:$src))]>;
635 def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, GR8 :$src),
636 "mov{b} {$src, $dst|$dst, $src}",
637 [(store GR8:$src, addr:$dst)]>;
638 def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16:$src),
639 "mov{w} {$src, $dst|$dst, $src}",
640 [(store GR16:$src, addr:$dst)]>, OpSize;
641 def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32:$src),
642 "mov{l} {$src, $dst|$dst, $src}",
643 [(store GR32:$src, addr:$dst)]>;
645 //===----------------------------------------------------------------------===//
646 // Fixed-Register Multiplication and Division Instructions...
649 // Extra precision multiplication
650 def MUL8r : I<0xF6, MRM4r, (ops GR8:$src), "mul{b} $src",
651 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
652 // This probably ought to be moved to a def : Pat<> if the
653 // syntax can be accepted.
654 [(set AL, (mul AL, GR8:$src))]>,
655 Imp<[AL],[AX]>; // AL,AH = AL*GR8
656 def MUL16r : I<0xF7, MRM4r, (ops GR16:$src), "mul{w} $src", []>,
657 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
658 def MUL32r : I<0xF7, MRM4r, (ops GR32:$src), "mul{l} $src", []>,
659 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
660 def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src),
662 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
663 // This probably ought to be moved to a def : Pat<> if the
664 // syntax can be accepted.
665 [(set AL, (mul AL, (loadi8 addr:$src)))]>,
666 Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
667 def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src),
668 "mul{w} $src", []>, Imp<[AX],[AX,DX]>,
669 OpSize; // AX,DX = AX*[mem16]
670 def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src),
671 "mul{l} $src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
673 def IMUL8r : I<0xF6, MRM5r, (ops GR8:$src), "imul{b} $src", []>,
674 Imp<[AL],[AX]>; // AL,AH = AL*GR8
675 def IMUL16r : I<0xF7, MRM5r, (ops GR16:$src), "imul{w} $src", []>,
676 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
677 def IMUL32r : I<0xF7, MRM5r, (ops GR32:$src), "imul{l} $src", []>,
678 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
679 def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src),
680 "imul{b} $src", []>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
681 def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src),
682 "imul{w} $src", []>, Imp<[AX],[AX,DX]>,
683 OpSize; // AX,DX = AX*[mem16]
684 def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src),
686 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
688 // unsigned division/remainder
689 def DIV8r : I<0xF6, MRM6r, (ops GR8:$src), // AX/r8 = AL,AH
690 "div{b} $src", []>, Imp<[AX],[AX]>;
691 def DIV16r : I<0xF7, MRM6r, (ops GR16:$src), // DX:AX/r16 = AX,DX
692 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
693 def DIV32r : I<0xF7, MRM6r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX
694 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
695 def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH
696 "div{b} $src", []>, Imp<[AX],[AX]>;
697 def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
698 "div{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
699 def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
700 "div{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
702 // Signed division/remainder.
703 def IDIV8r : I<0xF6, MRM7r, (ops GR8:$src), // AX/r8 = AL,AH
704 "idiv{b} $src", []>, Imp<[AX],[AX]>;
705 def IDIV16r: I<0xF7, MRM7r, (ops GR16:$src), // DX:AX/r16 = AX,DX
706 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
707 def IDIV32r: I<0xF7, MRM7r, (ops GR32:$src), // EDX:EAX/r32 = EAX,EDX
708 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
709 def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH
710 "idiv{b} $src", []>, Imp<[AX],[AX]>;
711 def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX
712 "idiv{w} $src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
713 def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
714 "idiv{l} $src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
717 //===----------------------------------------------------------------------===//
718 // Two address Instructions...
720 let isTwoAddress = 1 in {
723 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
724 (ops GR16:$dst, GR16:$src1, GR16:$src2),
725 "cmovb {$src2, $dst|$dst, $src2}",
726 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
729 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
730 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
731 "cmovb {$src2, $dst|$dst, $src2}",
732 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
735 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
736 (ops GR32:$dst, GR32:$src1, GR32:$src2),
737 "cmovb {$src2, $dst|$dst, $src2}",
738 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
741 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
742 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
743 "cmovb {$src2, $dst|$dst, $src2}",
744 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
748 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
749 (ops GR16:$dst, GR16:$src1, GR16:$src2),
750 "cmovae {$src2, $dst|$dst, $src2}",
751 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
754 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
755 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
756 "cmovae {$src2, $dst|$dst, $src2}",
757 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
760 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
761 (ops GR32:$dst, GR32:$src1, GR32:$src2),
762 "cmovae {$src2, $dst|$dst, $src2}",
763 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
766 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
767 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
768 "cmovae {$src2, $dst|$dst, $src2}",
769 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
773 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
774 (ops GR16:$dst, GR16:$src1, GR16:$src2),
775 "cmove {$src2, $dst|$dst, $src2}",
776 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
779 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
780 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
781 "cmove {$src2, $dst|$dst, $src2}",
782 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
785 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
786 (ops GR32:$dst, GR32:$src1, GR32:$src2),
787 "cmove {$src2, $dst|$dst, $src2}",
788 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
791 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
792 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
793 "cmove {$src2, $dst|$dst, $src2}",
794 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
798 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
799 (ops GR16:$dst, GR16:$src1, GR16:$src2),
800 "cmovne {$src2, $dst|$dst, $src2}",
801 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
804 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
805 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
806 "cmovne {$src2, $dst|$dst, $src2}",
807 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
810 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
811 (ops GR32:$dst, GR32:$src1, GR32:$src2),
812 "cmovne {$src2, $dst|$dst, $src2}",
813 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
816 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
817 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
818 "cmovne {$src2, $dst|$dst, $src2}",
819 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
823 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
824 (ops GR16:$dst, GR16:$src1, GR16:$src2),
825 "cmovbe {$src2, $dst|$dst, $src2}",
826 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
829 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
830 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
831 "cmovbe {$src2, $dst|$dst, $src2}",
832 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
835 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
836 (ops GR32:$dst, GR32:$src1, GR32:$src2),
837 "cmovbe {$src2, $dst|$dst, $src2}",
838 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
841 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
842 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
843 "cmovbe {$src2, $dst|$dst, $src2}",
844 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
848 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
849 (ops GR16:$dst, GR16:$src1, GR16:$src2),
850 "cmova {$src2, $dst|$dst, $src2}",
851 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
854 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
855 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
856 "cmova {$src2, $dst|$dst, $src2}",
857 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
860 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
861 (ops GR32:$dst, GR32:$src1, GR32:$src2),
862 "cmova {$src2, $dst|$dst, $src2}",
863 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
866 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
867 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
868 "cmova {$src2, $dst|$dst, $src2}",
869 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
873 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
874 (ops GR16:$dst, GR16:$src1, GR16:$src2),
875 "cmovl {$src2, $dst|$dst, $src2}",
876 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
879 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
880 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
881 "cmovl {$src2, $dst|$dst, $src2}",
882 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
885 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
886 (ops GR32:$dst, GR32:$src1, GR32:$src2),
887 "cmovl {$src2, $dst|$dst, $src2}",
888 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
891 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
892 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
893 "cmovl {$src2, $dst|$dst, $src2}",
894 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
898 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
899 (ops GR16:$dst, GR16:$src1, GR16:$src2),
900 "cmovge {$src2, $dst|$dst, $src2}",
901 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
904 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
905 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
906 "cmovge {$src2, $dst|$dst, $src2}",
907 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
910 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
911 (ops GR32:$dst, GR32:$src1, GR32:$src2),
912 "cmovge {$src2, $dst|$dst, $src2}",
913 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
916 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
917 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
918 "cmovge {$src2, $dst|$dst, $src2}",
919 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
923 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
924 (ops GR16:$dst, GR16:$src1, GR16:$src2),
925 "cmovle {$src2, $dst|$dst, $src2}",
926 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
929 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
930 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
931 "cmovle {$src2, $dst|$dst, $src2}",
932 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
935 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
936 (ops GR32:$dst, GR32:$src1, GR32:$src2),
937 "cmovle {$src2, $dst|$dst, $src2}",
938 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
941 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
942 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
943 "cmovle {$src2, $dst|$dst, $src2}",
944 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
948 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
949 (ops GR16:$dst, GR16:$src1, GR16:$src2),
950 "cmovg {$src2, $dst|$dst, $src2}",
951 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
954 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
955 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
956 "cmovg {$src2, $dst|$dst, $src2}",
957 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
960 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
961 (ops GR32:$dst, GR32:$src1, GR32:$src2),
962 "cmovg {$src2, $dst|$dst, $src2}",
963 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
966 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
967 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
968 "cmovg {$src2, $dst|$dst, $src2}",
969 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
973 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
974 (ops GR16:$dst, GR16:$src1, GR16:$src2),
975 "cmovs {$src2, $dst|$dst, $src2}",
976 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
979 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
980 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
981 "cmovs {$src2, $dst|$dst, $src2}",
982 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
985 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
986 (ops GR32:$dst, GR32:$src1, GR32:$src2),
987 "cmovs {$src2, $dst|$dst, $src2}",
988 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
991 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
992 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
993 "cmovs {$src2, $dst|$dst, $src2}",
994 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
998 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
999 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1000 "cmovns {$src2, $dst|$dst, $src2}",
1001 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1004 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1005 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1006 "cmovns {$src2, $dst|$dst, $src2}",
1007 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1010 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1011 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1012 "cmovns {$src2, $dst|$dst, $src2}",
1013 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1016 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1017 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1018 "cmovns {$src2, $dst|$dst, $src2}",
1019 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1023 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1024 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1025 "cmovp {$src2, $dst|$dst, $src2}",
1026 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1029 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1030 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1031 "cmovp {$src2, $dst|$dst, $src2}",
1032 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1035 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1036 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1037 "cmovp {$src2, $dst|$dst, $src2}",
1038 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1041 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1042 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1043 "cmovp {$src2, $dst|$dst, $src2}",
1044 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1048 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1049 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1050 "cmovnp {$src2, $dst|$dst, $src2}",
1051 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1054 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1055 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1056 "cmovnp {$src2, $dst|$dst, $src2}",
1057 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1060 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1061 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1062 "cmovnp {$src2, $dst|$dst, $src2}",
1063 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1066 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1067 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1068 "cmovnp {$src2, $dst|$dst, $src2}",
1069 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1074 // unary instructions
1075 let CodeSize = 2 in {
1076 def NEG8r : I<0xF6, MRM3r, (ops GR8 :$dst, GR8 :$src), "neg{b} $dst",
1077 [(set GR8:$dst, (ineg GR8:$src))]>;
1078 def NEG16r : I<0xF7, MRM3r, (ops GR16:$dst, GR16:$src), "neg{w} $dst",
1079 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
1080 def NEG32r : I<0xF7, MRM3r, (ops GR32:$dst, GR32:$src), "neg{l} $dst",
1081 [(set GR32:$dst, (ineg GR32:$src))]>;
1082 let isTwoAddress = 0 in {
1083 def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst",
1084 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
1085 def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst",
1086 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1087 def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst",
1088 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
1092 def NOT8r : I<0xF6, MRM2r, (ops GR8 :$dst, GR8 :$src), "not{b} $dst",
1093 [(set GR8:$dst, (not GR8:$src))]>;
1094 def NOT16r : I<0xF7, MRM2r, (ops GR16:$dst, GR16:$src), "not{w} $dst",
1095 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1096 def NOT32r : I<0xF7, MRM2r, (ops GR32:$dst, GR32:$src), "not{l} $dst",
1097 [(set GR32:$dst, (not GR32:$src))]>;
1098 let isTwoAddress = 0 in {
1099 def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst",
1100 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1101 def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst",
1102 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1103 def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst",
1104 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1108 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1110 def INC8r : I<0xFE, MRM0r, (ops GR8 :$dst, GR8 :$src), "inc{b} $dst",
1111 [(set GR8:$dst, (add GR8:$src, 1))]>;
1112 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1113 def INC16r : I<0x40, AddRegFrm, (ops GR16:$dst, GR16:$src), "inc{w} $dst",
1114 [(set GR16:$dst, (add GR16:$src, 1))]>,
1115 OpSize, Requires<[In32BitMode]>;
1116 def INC32r : I<0x40, AddRegFrm, (ops GR32:$dst, GR32:$src), "inc{l} $dst",
1117 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1119 let isTwoAddress = 0, CodeSize = 2 in {
1120 def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst",
1121 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1122 def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst",
1123 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize;
1124 def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst",
1125 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>;
1129 def DEC8r : I<0xFE, MRM1r, (ops GR8 :$dst, GR8 :$src), "dec{b} $dst",
1130 [(set GR8:$dst, (add GR8:$src, -1))]>;
1131 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1132 def DEC16r : I<0x48, AddRegFrm, (ops GR16:$dst, GR16:$src), "dec{w} $dst",
1133 [(set GR16:$dst, (add GR16:$src, -1))]>,
1134 OpSize, Requires<[In32BitMode]>;
1135 def DEC32r : I<0x48, AddRegFrm, (ops GR32:$dst, GR32:$src), "dec{l} $dst",
1136 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1139 let isTwoAddress = 0, CodeSize = 2 in {
1140 def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst",
1141 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1142 def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst",
1143 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize;
1144 def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst",
1145 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>;
1148 // Logical operators...
1149 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1150 def AND8rr : I<0x20, MRMDestReg,
1151 (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1152 "and{b} {$src2, $dst|$dst, $src2}",
1153 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1154 def AND16rr : I<0x21, MRMDestReg,
1155 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1156 "and{w} {$src2, $dst|$dst, $src2}",
1157 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1158 def AND32rr : I<0x21, MRMDestReg,
1159 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1160 "and{l} {$src2, $dst|$dst, $src2}",
1161 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1164 def AND8rm : I<0x22, MRMSrcMem,
1165 (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1166 "and{b} {$src2, $dst|$dst, $src2}",
1167 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1168 def AND16rm : I<0x23, MRMSrcMem,
1169 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1170 "and{w} {$src2, $dst|$dst, $src2}",
1171 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1172 def AND32rm : I<0x23, MRMSrcMem,
1173 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1174 "and{l} {$src2, $dst|$dst, $src2}",
1175 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1177 def AND8ri : Ii8<0x80, MRM4r,
1178 (ops GR8 :$dst, GR8 :$src1, i8imm :$src2),
1179 "and{b} {$src2, $dst|$dst, $src2}",
1180 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1181 def AND16ri : Ii16<0x81, MRM4r,
1182 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1183 "and{w} {$src2, $dst|$dst, $src2}",
1184 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1185 def AND32ri : Ii32<0x81, MRM4r,
1186 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1187 "and{l} {$src2, $dst|$dst, $src2}",
1188 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1189 def AND16ri8 : Ii8<0x83, MRM4r,
1190 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1191 "and{w} {$src2, $dst|$dst, $src2}",
1192 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1194 def AND32ri8 : Ii8<0x83, MRM4r,
1195 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1196 "and{l} {$src2, $dst|$dst, $src2}",
1197 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1199 let isTwoAddress = 0 in {
1200 def AND8mr : I<0x20, MRMDestMem,
1201 (ops i8mem :$dst, GR8 :$src),
1202 "and{b} {$src, $dst|$dst, $src}",
1203 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1204 def AND16mr : I<0x21, MRMDestMem,
1205 (ops i16mem:$dst, GR16:$src),
1206 "and{w} {$src, $dst|$dst, $src}",
1207 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1209 def AND32mr : I<0x21, MRMDestMem,
1210 (ops i32mem:$dst, GR32:$src),
1211 "and{l} {$src, $dst|$dst, $src}",
1212 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1213 def AND8mi : Ii8<0x80, MRM4m,
1214 (ops i8mem :$dst, i8imm :$src),
1215 "and{b} {$src, $dst|$dst, $src}",
1216 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1217 def AND16mi : Ii16<0x81, MRM4m,
1218 (ops i16mem:$dst, i16imm:$src),
1219 "and{w} {$src, $dst|$dst, $src}",
1220 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1222 def AND32mi : Ii32<0x81, MRM4m,
1223 (ops i32mem:$dst, i32imm:$src),
1224 "and{l} {$src, $dst|$dst, $src}",
1225 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1226 def AND16mi8 : Ii8<0x83, MRM4m,
1227 (ops i16mem:$dst, i16i8imm :$src),
1228 "and{w} {$src, $dst|$dst, $src}",
1229 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1231 def AND32mi8 : Ii8<0x83, MRM4m,
1232 (ops i32mem:$dst, i32i8imm :$src),
1233 "and{l} {$src, $dst|$dst, $src}",
1234 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1238 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1239 def OR8rr : I<0x08, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1240 "or{b} {$src2, $dst|$dst, $src2}",
1241 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1242 def OR16rr : I<0x09, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1243 "or{w} {$src2, $dst|$dst, $src2}",
1244 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1245 def OR32rr : I<0x09, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1246 "or{l} {$src2, $dst|$dst, $src2}",
1247 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1249 def OR8rm : I<0x0A, MRMSrcMem , (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1250 "or{b} {$src2, $dst|$dst, $src2}",
1251 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1252 def OR16rm : I<0x0B, MRMSrcMem , (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1253 "or{w} {$src2, $dst|$dst, $src2}",
1254 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1255 def OR32rm : I<0x0B, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1256 "or{l} {$src2, $dst|$dst, $src2}",
1257 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1259 def OR8ri : Ii8 <0x80, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1260 "or{b} {$src2, $dst|$dst, $src2}",
1261 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1262 def OR16ri : Ii16<0x81, MRM1r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1263 "or{w} {$src2, $dst|$dst, $src2}",
1264 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1265 def OR32ri : Ii32<0x81, MRM1r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1266 "or{l} {$src2, $dst|$dst, $src2}",
1267 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1269 def OR16ri8 : Ii8<0x83, MRM1r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1270 "or{w} {$src2, $dst|$dst, $src2}",
1271 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1272 def OR32ri8 : Ii8<0x83, MRM1r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1273 "or{l} {$src2, $dst|$dst, $src2}",
1274 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1275 let isTwoAddress = 0 in {
1276 def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, GR8:$src),
1277 "or{b} {$src, $dst|$dst, $src}",
1278 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1279 def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, GR16:$src),
1280 "or{w} {$src, $dst|$dst, $src}",
1281 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1282 def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, GR32:$src),
1283 "or{l} {$src, $dst|$dst, $src}",
1284 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1285 def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src),
1286 "or{b} {$src, $dst|$dst, $src}",
1287 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1288 def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src),
1289 "or{w} {$src, $dst|$dst, $src}",
1290 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1292 def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src),
1293 "or{l} {$src, $dst|$dst, $src}",
1294 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1295 def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i16i8imm:$src),
1296 "or{w} {$src, $dst|$dst, $src}",
1297 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1299 def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i32i8imm:$src),
1300 "or{l} {$src, $dst|$dst, $src}",
1301 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1305 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1306 def XOR8rr : I<0x30, MRMDestReg,
1307 (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1308 "xor{b} {$src2, $dst|$dst, $src2}",
1309 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1310 def XOR16rr : I<0x31, MRMDestReg,
1311 (ops GR16:$dst, GR16:$src1, GR16:$src2),
1312 "xor{w} {$src2, $dst|$dst, $src2}",
1313 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1314 def XOR32rr : I<0x31, MRMDestReg,
1315 (ops GR32:$dst, GR32:$src1, GR32:$src2),
1316 "xor{l} {$src2, $dst|$dst, $src2}",
1317 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1320 def XOR8rm : I<0x32, MRMSrcMem ,
1321 (ops GR8 :$dst, GR8:$src1, i8mem :$src2),
1322 "xor{b} {$src2, $dst|$dst, $src2}",
1323 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1324 def XOR16rm : I<0x33, MRMSrcMem ,
1325 (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1326 "xor{w} {$src2, $dst|$dst, $src2}",
1327 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1328 def XOR32rm : I<0x33, MRMSrcMem ,
1329 (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1330 "xor{l} {$src2, $dst|$dst, $src2}",
1331 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1333 def XOR8ri : Ii8<0x80, MRM6r,
1334 (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1335 "xor{b} {$src2, $dst|$dst, $src2}",
1336 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1337 def XOR16ri : Ii16<0x81, MRM6r,
1338 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1339 "xor{w} {$src2, $dst|$dst, $src2}",
1340 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1341 def XOR32ri : Ii32<0x81, MRM6r,
1342 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1343 "xor{l} {$src2, $dst|$dst, $src2}",
1344 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1345 def XOR16ri8 : Ii8<0x83, MRM6r,
1346 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1347 "xor{w} {$src2, $dst|$dst, $src2}",
1348 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1350 def XOR32ri8 : Ii8<0x83, MRM6r,
1351 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1352 "xor{l} {$src2, $dst|$dst, $src2}",
1353 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1354 let isTwoAddress = 0 in {
1355 def XOR8mr : I<0x30, MRMDestMem,
1356 (ops i8mem :$dst, GR8 :$src),
1357 "xor{b} {$src, $dst|$dst, $src}",
1358 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1359 def XOR16mr : I<0x31, MRMDestMem,
1360 (ops i16mem:$dst, GR16:$src),
1361 "xor{w} {$src, $dst|$dst, $src}",
1362 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1364 def XOR32mr : I<0x31, MRMDestMem,
1365 (ops i32mem:$dst, GR32:$src),
1366 "xor{l} {$src, $dst|$dst, $src}",
1367 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1368 def XOR8mi : Ii8<0x80, MRM6m,
1369 (ops i8mem :$dst, i8imm :$src),
1370 "xor{b} {$src, $dst|$dst, $src}",
1371 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1372 def XOR16mi : Ii16<0x81, MRM6m,
1373 (ops i16mem:$dst, i16imm:$src),
1374 "xor{w} {$src, $dst|$dst, $src}",
1375 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1377 def XOR32mi : Ii32<0x81, MRM6m,
1378 (ops i32mem:$dst, i32imm:$src),
1379 "xor{l} {$src, $dst|$dst, $src}",
1380 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1381 def XOR16mi8 : Ii8<0x83, MRM6m,
1382 (ops i16mem:$dst, i16i8imm :$src),
1383 "xor{w} {$src, $dst|$dst, $src}",
1384 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1386 def XOR32mi8 : Ii8<0x83, MRM6m,
1387 (ops i32mem:$dst, i32i8imm :$src),
1388 "xor{l} {$src, $dst|$dst, $src}",
1389 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1392 // Shift instructions
1393 def SHL8rCL : I<0xD2, MRM4r, (ops GR8 :$dst, GR8 :$src),
1394 "shl{b} {%cl, $dst|$dst, %CL}",
1395 [(set GR8:$dst, (shl GR8:$src, CL))]>, Imp<[CL],[]>;
1396 def SHL16rCL : I<0xD3, MRM4r, (ops GR16:$dst, GR16:$src),
1397 "shl{w} {%cl, $dst|$dst, %CL}",
1398 [(set GR16:$dst, (shl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1399 def SHL32rCL : I<0xD3, MRM4r, (ops GR32:$dst, GR32:$src),
1400 "shl{l} {%cl, $dst|$dst, %CL}",
1401 [(set GR32:$dst, (shl GR32:$src, CL))]>, Imp<[CL],[]>;
1403 def SHL8ri : Ii8<0xC0, MRM4r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1404 "shl{b} {$src2, $dst|$dst, $src2}",
1405 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1406 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1407 def SHL16ri : Ii8<0xC1, MRM4r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1408 "shl{w} {$src2, $dst|$dst, $src2}",
1409 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1410 def SHL32ri : Ii8<0xC1, MRM4r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1411 "shl{l} {$src2, $dst|$dst, $src2}",
1412 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1415 // Shift left by one. Not used because (add x, x) is slightly cheaper.
1416 def SHL8r1 : I<0xD0, MRM4r, (ops GR8 :$dst, GR8 :$src1),
1418 def SHL16r1 : I<0xD1, MRM4r, (ops GR16:$dst, GR16:$src1),
1419 "shl{w} $dst", []>, OpSize;
1420 def SHL32r1 : I<0xD1, MRM4r, (ops GR32:$dst, GR32:$src1),
1423 let isTwoAddress = 0 in {
1424 def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst),
1425 "shl{b} {%cl, $dst|$dst, %CL}",
1426 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>,
1428 def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst),
1429 "shl{w} {%cl, $dst|$dst, %CL}",
1430 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>,
1431 Imp<[CL],[]>, OpSize;
1432 def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst),
1433 "shl{l} {%cl, $dst|$dst, %CL}",
1434 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>,
1436 def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src),
1437 "shl{b} {$src, $dst|$dst, $src}",
1438 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1439 def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src),
1440 "shl{w} {$src, $dst|$dst, $src}",
1441 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1443 def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src),
1444 "shl{l} {$src, $dst|$dst, $src}",
1445 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1448 def SHL8m1 : I<0xD0, MRM4m, (ops i8mem :$dst),
1450 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1451 def SHL16m1 : I<0xD1, MRM4m, (ops i16mem:$dst),
1453 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1455 def SHL32m1 : I<0xD1, MRM4m, (ops i32mem:$dst),
1457 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1460 def SHR8rCL : I<0xD2, MRM5r, (ops GR8 :$dst, GR8 :$src),
1461 "shr{b} {%cl, $dst|$dst, %CL}",
1462 [(set GR8:$dst, (srl GR8:$src, CL))]>, Imp<[CL],[]>;
1463 def SHR16rCL : I<0xD3, MRM5r, (ops GR16:$dst, GR16:$src),
1464 "shr{w} {%cl, $dst|$dst, %CL}",
1465 [(set GR16:$dst, (srl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1466 def SHR32rCL : I<0xD3, MRM5r, (ops GR32:$dst, GR32:$src),
1467 "shr{l} {%cl, $dst|$dst, %CL}",
1468 [(set GR32:$dst, (srl GR32:$src, CL))]>, Imp<[CL],[]>;
1470 def SHR8ri : Ii8<0xC0, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1471 "shr{b} {$src2, $dst|$dst, $src2}",
1472 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1473 def SHR16ri : Ii8<0xC1, MRM5r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1474 "shr{w} {$src2, $dst|$dst, $src2}",
1475 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1476 def SHR32ri : Ii8<0xC1, MRM5r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1477 "shr{l} {$src2, $dst|$dst, $src2}",
1478 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1481 def SHR8r1 : I<0xD0, MRM5r, (ops GR8:$dst, GR8:$src1),
1483 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1484 def SHR16r1 : I<0xD1, MRM5r, (ops GR16:$dst, GR16:$src1),
1486 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1487 def SHR32r1 : I<0xD1, MRM5r, (ops GR32:$dst, GR32:$src1),
1489 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1491 let isTwoAddress = 0 in {
1492 def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst),
1493 "shr{b} {%cl, $dst|$dst, %CL}",
1494 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>,
1496 def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst),
1497 "shr{w} {%cl, $dst|$dst, %CL}",
1498 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1499 Imp<[CL],[]>, OpSize;
1500 def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst),
1501 "shr{l} {%cl, $dst|$dst, %CL}",
1502 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>,
1504 def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src),
1505 "shr{b} {$src, $dst|$dst, $src}",
1506 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1507 def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src),
1508 "shr{w} {$src, $dst|$dst, $src}",
1509 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1511 def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src),
1512 "shr{l} {$src, $dst|$dst, $src}",
1513 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1516 def SHR8m1 : I<0xD0, MRM5m, (ops i8mem :$dst),
1518 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1519 def SHR16m1 : I<0xD1, MRM5m, (ops i16mem:$dst),
1521 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1522 def SHR32m1 : I<0xD1, MRM5m, (ops i32mem:$dst),
1524 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1527 def SAR8rCL : I<0xD2, MRM7r, (ops GR8 :$dst, GR8 :$src),
1528 "sar{b} {%cl, $dst|$dst, %CL}",
1529 [(set GR8:$dst, (sra GR8:$src, CL))]>, Imp<[CL],[]>;
1530 def SAR16rCL : I<0xD3, MRM7r, (ops GR16:$dst, GR16:$src),
1531 "sar{w} {%cl, $dst|$dst, %CL}",
1532 [(set GR16:$dst, (sra GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1533 def SAR32rCL : I<0xD3, MRM7r, (ops GR32:$dst, GR32:$src),
1534 "sar{l} {%cl, $dst|$dst, %CL}",
1535 [(set GR32:$dst, (sra GR32:$src, CL))]>, Imp<[CL],[]>;
1537 def SAR8ri : Ii8<0xC0, MRM7r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1538 "sar{b} {$src2, $dst|$dst, $src2}",
1539 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1540 def SAR16ri : Ii8<0xC1, MRM7r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1541 "sar{w} {$src2, $dst|$dst, $src2}",
1542 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1544 def SAR32ri : Ii8<0xC1, MRM7r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1545 "sar{l} {$src2, $dst|$dst, $src2}",
1546 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1549 def SAR8r1 : I<0xD0, MRM7r, (ops GR8 :$dst, GR8 :$src1),
1551 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1552 def SAR16r1 : I<0xD1, MRM7r, (ops GR16:$dst, GR16:$src1),
1554 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1555 def SAR32r1 : I<0xD1, MRM7r, (ops GR32:$dst, GR32:$src1),
1557 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1559 let isTwoAddress = 0 in {
1560 def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst),
1561 "sar{b} {%cl, $dst|$dst, %CL}",
1562 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>,
1564 def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst),
1565 "sar{w} {%cl, $dst|$dst, %CL}",
1566 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>,
1567 Imp<[CL],[]>, OpSize;
1568 def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst),
1569 "sar{l} {%cl, $dst|$dst, %CL}",
1570 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>,
1572 def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src),
1573 "sar{b} {$src, $dst|$dst, $src}",
1574 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1575 def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src),
1576 "sar{w} {$src, $dst|$dst, $src}",
1577 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1579 def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src),
1580 "sar{l} {$src, $dst|$dst, $src}",
1581 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1584 def SAR8m1 : I<0xD0, MRM7m, (ops i8mem :$dst),
1586 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1587 def SAR16m1 : I<0xD1, MRM7m, (ops i16mem:$dst),
1589 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1591 def SAR32m1 : I<0xD1, MRM7m, (ops i32mem:$dst),
1593 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1596 // Rotate instructions
1597 // FIXME: provide shorter instructions when imm8 == 1
1598 def ROL8rCL : I<0xD2, MRM0r, (ops GR8 :$dst, GR8 :$src),
1599 "rol{b} {%cl, $dst|$dst, %CL}",
1600 [(set GR8:$dst, (rotl GR8:$src, CL))]>, Imp<[CL],[]>;
1601 def ROL16rCL : I<0xD3, MRM0r, (ops GR16:$dst, GR16:$src),
1602 "rol{w} {%cl, $dst|$dst, %CL}",
1603 [(set GR16:$dst, (rotl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1604 def ROL32rCL : I<0xD3, MRM0r, (ops GR32:$dst, GR32:$src),
1605 "rol{l} {%cl, $dst|$dst, %CL}",
1606 [(set GR32:$dst, (rotl GR32:$src, CL))]>, Imp<[CL],[]>;
1608 def ROL8ri : Ii8<0xC0, MRM0r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1609 "rol{b} {$src2, $dst|$dst, $src2}",
1610 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1611 def ROL16ri : Ii8<0xC1, MRM0r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1612 "rol{w} {$src2, $dst|$dst, $src2}",
1613 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1614 def ROL32ri : Ii8<0xC1, MRM0r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1615 "rol{l} {$src2, $dst|$dst, $src2}",
1616 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1619 def ROL8r1 : I<0xD0, MRM0r, (ops GR8 :$dst, GR8 :$src1),
1621 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1622 def ROL16r1 : I<0xD1, MRM0r, (ops GR16:$dst, GR16:$src1),
1624 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1625 def ROL32r1 : I<0xD1, MRM0r, (ops GR32:$dst, GR32:$src1),
1627 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1629 let isTwoAddress = 0 in {
1630 def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst),
1631 "rol{b} {%cl, $dst|$dst, %CL}",
1632 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>,
1634 def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst),
1635 "rol{w} {%cl, $dst|$dst, %CL}",
1636 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>,
1637 Imp<[CL],[]>, OpSize;
1638 def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst),
1639 "rol{l} {%cl, $dst|$dst, %CL}",
1640 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>,
1642 def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src),
1643 "rol{b} {$src, $dst|$dst, $src}",
1644 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1645 def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src),
1646 "rol{w} {$src, $dst|$dst, $src}",
1647 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1649 def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src),
1650 "rol{l} {$src, $dst|$dst, $src}",
1651 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1654 def ROL8m1 : I<0xD0, MRM0m, (ops i8mem :$dst),
1656 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1657 def ROL16m1 : I<0xD1, MRM0m, (ops i16mem:$dst),
1659 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1661 def ROL32m1 : I<0xD1, MRM0m, (ops i32mem:$dst),
1663 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1666 def ROR8rCL : I<0xD2, MRM1r, (ops GR8 :$dst, GR8 :$src),
1667 "ror{b} {%cl, $dst|$dst, %CL}",
1668 [(set GR8:$dst, (rotr GR8:$src, CL))]>, Imp<[CL],[]>;
1669 def ROR16rCL : I<0xD3, MRM1r, (ops GR16:$dst, GR16:$src),
1670 "ror{w} {%cl, $dst|$dst, %CL}",
1671 [(set GR16:$dst, (rotr GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1672 def ROR32rCL : I<0xD3, MRM1r, (ops GR32:$dst, GR32:$src),
1673 "ror{l} {%cl, $dst|$dst, %CL}",
1674 [(set GR32:$dst, (rotr GR32:$src, CL))]>, Imp<[CL],[]>;
1676 def ROR8ri : Ii8<0xC0, MRM1r, (ops GR8 :$dst, GR8 :$src1, i8imm:$src2),
1677 "ror{b} {$src2, $dst|$dst, $src2}",
1678 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1679 def ROR16ri : Ii8<0xC1, MRM1r, (ops GR16:$dst, GR16:$src1, i8imm:$src2),
1680 "ror{w} {$src2, $dst|$dst, $src2}",
1681 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1682 def ROR32ri : Ii8<0xC1, MRM1r, (ops GR32:$dst, GR32:$src1, i8imm:$src2),
1683 "ror{l} {$src2, $dst|$dst, $src2}",
1684 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1687 def ROR8r1 : I<0xD0, MRM1r, (ops GR8 :$dst, GR8 :$src1),
1689 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1690 def ROR16r1 : I<0xD1, MRM1r, (ops GR16:$dst, GR16:$src1),
1692 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1693 def ROR32r1 : I<0xD1, MRM1r, (ops GR32:$dst, GR32:$src1),
1695 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1697 let isTwoAddress = 0 in {
1698 def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst),
1699 "ror{b} {%cl, $dst|$dst, %CL}",
1700 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>,
1702 def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst),
1703 "ror{w} {%cl, $dst|$dst, %CL}",
1704 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>,
1705 Imp<[CL],[]>, OpSize;
1706 def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst),
1707 "ror{l} {%cl, $dst|$dst, %CL}",
1708 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>,
1710 def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src),
1711 "ror{b} {$src, $dst|$dst, $src}",
1712 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1713 def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src),
1714 "ror{w} {$src, $dst|$dst, $src}",
1715 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1717 def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src),
1718 "ror{l} {$src, $dst|$dst, $src}",
1719 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1722 def ROR8m1 : I<0xD0, MRM1m, (ops i8mem :$dst),
1724 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1725 def ROR16m1 : I<0xD1, MRM1m, (ops i16mem:$dst),
1727 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1729 def ROR32m1 : I<0xD1, MRM1m, (ops i32mem:$dst),
1731 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1736 // Double shift instructions (generalizations of rotate)
1737 def SHLD32rrCL : I<0xA5, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1738 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1739 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>,
1741 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1742 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1743 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>,
1745 def SHLD16rrCL : I<0xA5, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1746 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1747 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1748 Imp<[CL],[]>, TB, OpSize;
1749 def SHRD16rrCL : I<0xAD, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1750 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1751 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1752 Imp<[CL],[]>, TB, OpSize;
1754 let isCommutable = 1 in { // These instructions commute to each other.
1755 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1756 (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3),
1757 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1758 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1761 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1762 (ops GR32:$dst, GR32:$src1, GR32:$src2, i8imm:$src3),
1763 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1764 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1767 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1768 (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3),
1769 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1770 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1773 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1774 (ops GR16:$dst, GR16:$src1, GR16:$src2, i8imm:$src3),
1775 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1776 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1781 let isTwoAddress = 0 in {
1782 def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1783 "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1784 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1787 def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1788 "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}",
1789 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1792 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1793 (ops i32mem:$dst, GR32:$src2, i8imm:$src3),
1794 "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1795 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1796 (i8 imm:$src3)), addr:$dst)]>,
1798 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1799 (ops i32mem:$dst, GR32:$src2, i8imm:$src3),
1800 "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}",
1801 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1802 (i8 imm:$src3)), addr:$dst)]>,
1805 def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1806 "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1807 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1809 Imp<[CL],[]>, TB, OpSize;
1810 def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1811 "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}",
1812 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1814 Imp<[CL],[]>, TB, OpSize;
1815 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1816 (ops i16mem:$dst, GR16:$src2, i8imm:$src3),
1817 "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1818 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1819 (i8 imm:$src3)), addr:$dst)]>,
1821 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1822 (ops i16mem:$dst, GR16:$src2, i8imm:$src3),
1823 "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}",
1824 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1825 (i8 imm:$src3)), addr:$dst)]>,
1831 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1832 def ADD8rr : I<0x00, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1833 "add{b} {$src2, $dst|$dst, $src2}",
1834 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1835 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1836 def ADD16rr : I<0x01, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1837 "add{w} {$src2, $dst|$dst, $src2}",
1838 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1839 def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1840 "add{l} {$src2, $dst|$dst, $src2}",
1841 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1842 } // end isConvertibleToThreeAddress
1843 } // end isCommutable
1844 def ADD8rm : I<0x02, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1845 "add{b} {$src2, $dst|$dst, $src2}",
1846 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1847 def ADD16rm : I<0x03, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1848 "add{w} {$src2, $dst|$dst, $src2}",
1849 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>, OpSize;
1850 def ADD32rm : I<0x03, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1851 "add{l} {$src2, $dst|$dst, $src2}",
1852 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1854 def ADD8ri : Ii8<0x80, MRM0r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1855 "add{b} {$src2, $dst|$dst, $src2}",
1856 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1858 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1859 def ADD16ri : Ii16<0x81, MRM0r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1860 "add{w} {$src2, $dst|$dst, $src2}",
1861 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1862 def ADD32ri : Ii32<0x81, MRM0r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1863 "add{l} {$src2, $dst|$dst, $src2}",
1864 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1865 def ADD16ri8 : Ii8<0x83, MRM0r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1866 "add{w} {$src2, $dst|$dst, $src2}",
1867 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>,
1869 def ADD32ri8 : Ii8<0x83, MRM0r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1870 "add{l} {$src2, $dst|$dst, $src2}",
1871 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1874 let isTwoAddress = 0 in {
1875 def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, GR8 :$src2),
1876 "add{b} {$src2, $dst|$dst, $src2}",
1877 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1878 def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1879 "add{w} {$src2, $dst|$dst, $src2}",
1880 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1882 def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1883 "add{l} {$src2, $dst|$dst, $src2}",
1884 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1885 def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2),
1886 "add{b} {$src2, $dst|$dst, $src2}",
1887 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1888 def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2),
1889 "add{w} {$src2, $dst|$dst, $src2}",
1890 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1892 def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2),
1893 "add{l} {$src2, $dst|$dst, $src2}",
1894 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1895 def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i16i8imm :$src2),
1896 "add{w} {$src2, $dst|$dst, $src2}",
1897 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1899 def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i32i8imm :$src2),
1900 "add{l} {$src2, $dst|$dst, $src2}",
1901 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1904 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1905 def ADC32rr : I<0x11, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1906 "adc{l} {$src2, $dst|$dst, $src2}",
1907 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1909 def ADC32rm : I<0x13, MRMSrcMem , (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1910 "adc{l} {$src2, $dst|$dst, $src2}",
1911 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1912 def ADC32ri : Ii32<0x81, MRM2r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1913 "adc{l} {$src2, $dst|$dst, $src2}",
1914 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1915 def ADC32ri8 : Ii8<0x83, MRM2r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1916 "adc{l} {$src2, $dst|$dst, $src2}",
1917 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1919 let isTwoAddress = 0 in {
1920 def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1921 "adc{l} {$src2, $dst|$dst, $src2}",
1922 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1923 def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2),
1924 "adc{l} {$src2, $dst|$dst, $src2}",
1925 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1926 def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i32i8imm :$src2),
1927 "adc{l} {$src2, $dst|$dst, $src2}",
1928 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1931 def SUB8rr : I<0x28, MRMDestReg, (ops GR8 :$dst, GR8 :$src1, GR8 :$src2),
1932 "sub{b} {$src2, $dst|$dst, $src2}",
1933 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
1934 def SUB16rr : I<0x29, MRMDestReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
1935 "sub{w} {$src2, $dst|$dst, $src2}",
1936 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
1937 def SUB32rr : I<0x29, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1938 "sub{l} {$src2, $dst|$dst, $src2}",
1939 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
1940 def SUB8rm : I<0x2A, MRMSrcMem, (ops GR8 :$dst, GR8 :$src1, i8mem :$src2),
1941 "sub{b} {$src2, $dst|$dst, $src2}",
1942 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
1943 def SUB16rm : I<0x2B, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
1944 "sub{w} {$src2, $dst|$dst, $src2}",
1945 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
1946 def SUB32rm : I<0x2B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
1947 "sub{l} {$src2, $dst|$dst, $src2}",
1948 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
1950 def SUB8ri : Ii8 <0x80, MRM5r, (ops GR8:$dst, GR8:$src1, i8imm:$src2),
1951 "sub{b} {$src2, $dst|$dst, $src2}",
1952 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
1953 def SUB16ri : Ii16<0x81, MRM5r, (ops GR16:$dst, GR16:$src1, i16imm:$src2),
1954 "sub{w} {$src2, $dst|$dst, $src2}",
1955 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
1956 def SUB32ri : Ii32<0x81, MRM5r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
1957 "sub{l} {$src2, $dst|$dst, $src2}",
1958 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
1959 def SUB16ri8 : Ii8<0x83, MRM5r, (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
1960 "sub{w} {$src2, $dst|$dst, $src2}",
1961 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
1963 def SUB32ri8 : Ii8<0x83, MRM5r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
1964 "sub{l} {$src2, $dst|$dst, $src2}",
1965 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
1966 let isTwoAddress = 0 in {
1967 def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, GR8 :$src2),
1968 "sub{b} {$src2, $dst|$dst, $src2}",
1969 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
1970 def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, GR16:$src2),
1971 "sub{w} {$src2, $dst|$dst, $src2}",
1972 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
1974 def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
1975 "sub{l} {$src2, $dst|$dst, $src2}",
1976 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
1977 def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2),
1978 "sub{b} {$src2, $dst|$dst, $src2}",
1979 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1980 def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2),
1981 "sub{w} {$src2, $dst|$dst, $src2}",
1982 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1984 def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2),
1985 "sub{l} {$src2, $dst|$dst, $src2}",
1986 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1987 def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i16i8imm :$src2),
1988 "sub{w} {$src2, $dst|$dst, $src2}",
1989 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1991 def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i32i8imm :$src2),
1992 "sub{l} {$src2, $dst|$dst, $src2}",
1993 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1996 def SBB32rr : I<0x19, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
1997 "sbb{l} {$src2, $dst|$dst, $src2}",
1998 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2000 let isTwoAddress = 0 in {
2001 def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, GR32:$src2),
2002 "sbb{l} {$src2, $dst|$dst, $src2}",
2003 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2004 def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
2005 "sbb{b} {$src2, $dst|$dst, $src2}",
2006 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2007 def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
2008 "sbb{l} {$src2, $dst|$dst, $src2}",
2009 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2010 def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i32i8imm :$src2),
2011 "sbb{l} {$src2, $dst|$dst, $src2}",
2012 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2014 def SBB32rm : I<0x1B, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
2015 "sbb{l} {$src2, $dst|$dst, $src2}",
2016 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2017 def SBB32ri : Ii32<0x81, MRM3r, (ops GR32:$dst, GR32:$src1, i32imm:$src2),
2018 "sbb{l} {$src2, $dst|$dst, $src2}",
2019 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2020 def SBB32ri8 : Ii8<0x83, MRM3r, (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
2021 "sbb{l} {$src2, $dst|$dst, $src2}",
2022 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2024 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2025 def IMUL16rr : I<0xAF, MRMSrcReg, (ops GR16:$dst, GR16:$src1, GR16:$src2),
2026 "imul{w} {$src2, $dst|$dst, $src2}",
2027 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
2028 def IMUL32rr : I<0xAF, MRMSrcReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
2029 "imul{l} {$src2, $dst|$dst, $src2}",
2030 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
2032 def IMUL16rm : I<0xAF, MRMSrcMem, (ops GR16:$dst, GR16:$src1, i16mem:$src2),
2033 "imul{w} {$src2, $dst|$dst, $src2}",
2034 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
2036 def IMUL32rm : I<0xAF, MRMSrcMem, (ops GR32:$dst, GR32:$src1, i32mem:$src2),
2037 "imul{l} {$src2, $dst|$dst, $src2}",
2038 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
2040 } // end Two Address instructions
2042 // Suprisingly enough, these are not two address instructions!
2043 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2044 (ops GR16:$dst, GR16:$src1, i16imm:$src2),
2045 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2046 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
2047 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2048 (ops GR32:$dst, GR32:$src1, i32imm:$src2),
2049 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2050 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
2051 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2052 (ops GR16:$dst, GR16:$src1, i16i8imm:$src2),
2053 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2054 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
2056 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2057 (ops GR32:$dst, GR32:$src1, i32i8imm:$src2),
2058 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2059 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
2061 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2062 (ops GR16:$dst, i16mem:$src1, i16imm:$src2),
2063 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2064 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
2066 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2067 (ops GR32:$dst, i32mem:$src1, i32imm:$src2),
2068 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2069 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
2070 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2071 (ops GR16:$dst, i16mem:$src1, i16i8imm :$src2),
2072 "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}",
2073 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
2075 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2076 (ops GR32:$dst, i32mem:$src1, i32i8imm: $src2),
2077 "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}",
2078 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
2080 //===----------------------------------------------------------------------===//
2081 // Test instructions are just like AND, except they don't generate a result.
2083 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2084 def TEST8rr : I<0x84, MRMDestReg, (ops GR8:$src1, GR8:$src2),
2085 "test{b} {$src2, $src1|$src1, $src2}",
2086 [(X86cmp (and GR8:$src1, GR8:$src2), 0)]>;
2087 def TEST16rr : I<0x85, MRMDestReg, (ops GR16:$src1, GR16:$src2),
2088 "test{w} {$src2, $src1|$src1, $src2}",
2089 [(X86cmp (and GR16:$src1, GR16:$src2), 0)]>, OpSize;
2090 def TEST32rr : I<0x85, MRMDestReg, (ops GR32:$src1, GR32:$src2),
2091 "test{l} {$src2, $src1|$src1, $src2}",
2092 [(X86cmp (and GR32:$src1, GR32:$src2), 0)]>;
2095 def TEST8rm : I<0x84, MRMSrcMem, (ops GR8 :$src1, i8mem :$src2),
2096 "test{b} {$src2, $src1|$src1, $src2}",
2097 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)]>;
2098 def TEST16rm : I<0x85, MRMSrcMem, (ops GR16:$src1, i16mem:$src2),
2099 "test{w} {$src2, $src1|$src1, $src2}",
2100 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)]>,
2102 def TEST32rm : I<0x85, MRMSrcMem, (ops GR32:$src1, i32mem:$src2),
2103 "test{l} {$src2, $src1|$src1, $src2}",
2104 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)]>;
2106 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2107 (ops GR8:$src1, i8imm:$src2),
2108 "test{b} {$src2, $src1|$src1, $src2}",
2109 [(X86cmp (and GR8:$src1, imm:$src2), 0)]>;
2110 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2111 (ops GR16:$src1, i16imm:$src2),
2112 "test{w} {$src2, $src1|$src1, $src2}",
2113 [(X86cmp (and GR16:$src1, imm:$src2), 0)]>, OpSize;
2114 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2115 (ops GR32:$src1, i32imm:$src2),
2116 "test{l} {$src2, $src1|$src1, $src2}",
2117 [(X86cmp (and GR32:$src1, imm:$src2), 0)]>;
2119 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2120 (ops i8mem:$src1, i8imm:$src2),
2121 "test{b} {$src2, $src1|$src1, $src2}",
2122 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)]>;
2123 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2124 (ops i16mem:$src1, i16imm:$src2),
2125 "test{w} {$src2, $src1|$src1, $src2}",
2126 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)]>,
2128 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2129 (ops i32mem:$src1, i32imm:$src2),
2130 "test{l} {$src2, $src1|$src1, $src2}",
2131 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)]>;
2134 // Condition code ops, incl. set if equal/not equal/...
2135 def SAHF : I<0x9E, RawFrm, (ops), "sahf", []>, Imp<[AH],[]>; // flags = AH
2136 def LAHF : I<0x9F, RawFrm, (ops), "lahf", []>, Imp<[],[AH]>; // AH = flags
2138 def SETEr : I<0x94, MRM0r,
2141 [(set GR8:$dst, (X86setcc X86_COND_E))]>,
2143 def SETEm : I<0x94, MRM0m,
2146 [(store (X86setcc X86_COND_E), addr:$dst)]>,
2148 def SETNEr : I<0x95, MRM0r,
2151 [(set GR8:$dst, (X86setcc X86_COND_NE))]>,
2153 def SETNEm : I<0x95, MRM0m,
2156 [(store (X86setcc X86_COND_NE), addr:$dst)]>,
2158 def SETLr : I<0x9C, MRM0r,
2161 [(set GR8:$dst, (X86setcc X86_COND_L))]>,
2162 TB; // GR8 = < signed
2163 def SETLm : I<0x9C, MRM0m,
2166 [(store (X86setcc X86_COND_L), addr:$dst)]>,
2167 TB; // [mem8] = < signed
2168 def SETGEr : I<0x9D, MRM0r,
2171 [(set GR8:$dst, (X86setcc X86_COND_GE))]>,
2172 TB; // GR8 = >= signed
2173 def SETGEm : I<0x9D, MRM0m,
2176 [(store (X86setcc X86_COND_GE), addr:$dst)]>,
2177 TB; // [mem8] = >= signed
2178 def SETLEr : I<0x9E, MRM0r,
2181 [(set GR8:$dst, (X86setcc X86_COND_LE))]>,
2182 TB; // GR8 = <= signed
2183 def SETLEm : I<0x9E, MRM0m,
2186 [(store (X86setcc X86_COND_LE), addr:$dst)]>,
2187 TB; // [mem8] = <= signed
2188 def SETGr : I<0x9F, MRM0r,
2191 [(set GR8:$dst, (X86setcc X86_COND_G))]>,
2192 TB; // GR8 = > signed
2193 def SETGm : I<0x9F, MRM0m,
2196 [(store (X86setcc X86_COND_G), addr:$dst)]>,
2197 TB; // [mem8] = > signed
2199 def SETBr : I<0x92, MRM0r,
2202 [(set GR8:$dst, (X86setcc X86_COND_B))]>,
2203 TB; // GR8 = < unsign
2204 def SETBm : I<0x92, MRM0m,
2207 [(store (X86setcc X86_COND_B), addr:$dst)]>,
2208 TB; // [mem8] = < unsign
2209 def SETAEr : I<0x93, MRM0r,
2212 [(set GR8:$dst, (X86setcc X86_COND_AE))]>,
2213 TB; // GR8 = >= unsign
2214 def SETAEm : I<0x93, MRM0m,
2217 [(store (X86setcc X86_COND_AE), addr:$dst)]>,
2218 TB; // [mem8] = >= unsign
2219 def SETBEr : I<0x96, MRM0r,
2222 [(set GR8:$dst, (X86setcc X86_COND_BE))]>,
2223 TB; // GR8 = <= unsign
2224 def SETBEm : I<0x96, MRM0m,
2227 [(store (X86setcc X86_COND_BE), addr:$dst)]>,
2228 TB; // [mem8] = <= unsign
2229 def SETAr : I<0x97, MRM0r,
2232 [(set GR8:$dst, (X86setcc X86_COND_A))]>,
2233 TB; // GR8 = > signed
2234 def SETAm : I<0x97, MRM0m,
2237 [(store (X86setcc X86_COND_A), addr:$dst)]>,
2238 TB; // [mem8] = > signed
2240 def SETSr : I<0x98, MRM0r,
2243 [(set GR8:$dst, (X86setcc X86_COND_S))]>,
2244 TB; // GR8 = <sign bit>
2245 def SETSm : I<0x98, MRM0m,
2248 [(store (X86setcc X86_COND_S), addr:$dst)]>,
2249 TB; // [mem8] = <sign bit>
2250 def SETNSr : I<0x99, MRM0r,
2253 [(set GR8:$dst, (X86setcc X86_COND_NS))]>,
2254 TB; // GR8 = !<sign bit>
2255 def SETNSm : I<0x99, MRM0m,
2258 [(store (X86setcc X86_COND_NS), addr:$dst)]>,
2259 TB; // [mem8] = !<sign bit>
2260 def SETPr : I<0x9A, MRM0r,
2263 [(set GR8:$dst, (X86setcc X86_COND_P))]>,
2265 def SETPm : I<0x9A, MRM0m,
2268 [(store (X86setcc X86_COND_P), addr:$dst)]>,
2269 TB; // [mem8] = parity
2270 def SETNPr : I<0x9B, MRM0r,
2273 [(set GR8:$dst, (X86setcc X86_COND_NP))]>,
2274 TB; // GR8 = not parity
2275 def SETNPm : I<0x9B, MRM0m,
2278 [(store (X86setcc X86_COND_NP), addr:$dst)]>,
2279 TB; // [mem8] = not parity
2281 // Integer comparisons
2282 def CMP8rr : I<0x38, MRMDestReg,
2283 (ops GR8 :$src1, GR8 :$src2),
2284 "cmp{b} {$src2, $src1|$src1, $src2}",
2285 [(X86cmp GR8:$src1, GR8:$src2)]>;
2286 def CMP16rr : I<0x39, MRMDestReg,
2287 (ops GR16:$src1, GR16:$src2),
2288 "cmp{w} {$src2, $src1|$src1, $src2}",
2289 [(X86cmp GR16:$src1, GR16:$src2)]>, OpSize;
2290 def CMP32rr : I<0x39, MRMDestReg,
2291 (ops GR32:$src1, GR32:$src2),
2292 "cmp{l} {$src2, $src1|$src1, $src2}",
2293 [(X86cmp GR32:$src1, GR32:$src2)]>;
2294 def CMP8mr : I<0x38, MRMDestMem,
2295 (ops i8mem :$src1, GR8 :$src2),
2296 "cmp{b} {$src2, $src1|$src1, $src2}",
2297 [(X86cmp (loadi8 addr:$src1), GR8:$src2)]>;
2298 def CMP16mr : I<0x39, MRMDestMem,
2299 (ops i16mem:$src1, GR16:$src2),
2300 "cmp{w} {$src2, $src1|$src1, $src2}",
2301 [(X86cmp (loadi16 addr:$src1), GR16:$src2)]>, OpSize;
2302 def CMP32mr : I<0x39, MRMDestMem,
2303 (ops i32mem:$src1, GR32:$src2),
2304 "cmp{l} {$src2, $src1|$src1, $src2}",
2305 [(X86cmp (loadi32 addr:$src1), GR32:$src2)]>;
2306 def CMP8rm : I<0x3A, MRMSrcMem,
2307 (ops GR8 :$src1, i8mem :$src2),
2308 "cmp{b} {$src2, $src1|$src1, $src2}",
2309 [(X86cmp GR8:$src1, (loadi8 addr:$src2))]>;
2310 def CMP16rm : I<0x3B, MRMSrcMem,
2311 (ops GR16:$src1, i16mem:$src2),
2312 "cmp{w} {$src2, $src1|$src1, $src2}",
2313 [(X86cmp GR16:$src1, (loadi16 addr:$src2))]>, OpSize;
2314 def CMP32rm : I<0x3B, MRMSrcMem,
2315 (ops GR32:$src1, i32mem:$src2),
2316 "cmp{l} {$src2, $src1|$src1, $src2}",
2317 [(X86cmp GR32:$src1, (loadi32 addr:$src2))]>;
2318 def CMP8ri : Ii8<0x80, MRM7r,
2319 (ops GR8:$src1, i8imm:$src2),
2320 "cmp{b} {$src2, $src1|$src1, $src2}",
2321 [(X86cmp GR8:$src1, imm:$src2)]>;
2322 def CMP16ri : Ii16<0x81, MRM7r,
2323 (ops GR16:$src1, i16imm:$src2),
2324 "cmp{w} {$src2, $src1|$src1, $src2}",
2325 [(X86cmp GR16:$src1, imm:$src2)]>, OpSize;
2326 def CMP32ri : Ii32<0x81, MRM7r,
2327 (ops GR32:$src1, i32imm:$src2),
2328 "cmp{l} {$src2, $src1|$src1, $src2}",
2329 [(X86cmp GR32:$src1, imm:$src2)]>;
2330 def CMP8mi : Ii8 <0x80, MRM7m,
2331 (ops i8mem :$src1, i8imm :$src2),
2332 "cmp{b} {$src2, $src1|$src1, $src2}",
2333 [(X86cmp (loadi8 addr:$src1), imm:$src2)]>;
2334 def CMP16mi : Ii16<0x81, MRM7m,
2335 (ops i16mem:$src1, i16imm:$src2),
2336 "cmp{w} {$src2, $src1|$src1, $src2}",
2337 [(X86cmp (loadi16 addr:$src1), imm:$src2)]>, OpSize;
2338 def CMP32mi : Ii32<0x81, MRM7m,
2339 (ops i32mem:$src1, i32imm:$src2),
2340 "cmp{l} {$src2, $src1|$src1, $src2}",
2341 [(X86cmp (loadi32 addr:$src1), imm:$src2)]>;
2342 def CMP16ri8 : Ii8<0x83, MRM7r,
2343 (ops GR16:$src1, i16i8imm:$src2),
2344 "cmp{w} {$src2, $src1|$src1, $src2}",
2345 [(X86cmp GR16:$src1, i16immSExt8:$src2)]>, OpSize;
2346 def CMP16mi8 : Ii8<0x83, MRM7m,
2347 (ops i16mem:$src1, i16i8imm:$src2),
2348 "cmp{w} {$src2, $src1|$src1, $src2}",
2349 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2)]>, OpSize;
2350 def CMP32mi8 : Ii8<0x83, MRM7m,
2351 (ops i32mem:$src1, i32i8imm:$src2),
2352 "cmp{l} {$src2, $src1|$src1, $src2}",
2353 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2)]>;
2354 def CMP32ri8 : Ii8<0x83, MRM7r,
2355 (ops GR32:$src1, i32i8imm:$src2),
2356 "cmp{l} {$src2, $src1|$src1, $src2}",
2357 [(X86cmp GR32:$src1, i32immSExt8:$src2)]>;
2359 // Sign/Zero extenders
2360 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops GR16:$dst, GR8 :$src),
2361 "movs{bw|x} {$src, $dst|$dst, $src}",
2362 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
2363 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops GR16:$dst, i8mem :$src),
2364 "movs{bw|x} {$src, $dst|$dst, $src}",
2365 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2366 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops GR32:$dst, GR8 :$src),
2367 "movs{bl|x} {$src, $dst|$dst, $src}",
2368 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2369 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops GR32:$dst, i8mem :$src),
2370 "movs{bl|x} {$src, $dst|$dst, $src}",
2371 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2372 def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops GR32:$dst, GR16:$src),
2373 "movs{wl|x} {$src, $dst|$dst, $src}",
2374 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2375 def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops GR32:$dst, i16mem:$src),
2376 "movs{wl|x} {$src, $dst|$dst, $src}",
2377 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2379 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops GR16:$dst, GR8 :$src),
2380 "movz{bw|x} {$src, $dst|$dst, $src}",
2381 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
2382 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops GR16:$dst, i8mem :$src),
2383 "movz{bw|x} {$src, $dst|$dst, $src}",
2384 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2385 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops GR32:$dst, GR8 :$src),
2386 "movz{bl|x} {$src, $dst|$dst, $src}",
2387 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2388 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops GR32:$dst, i8mem :$src),
2389 "movz{bl|x} {$src, $dst|$dst, $src}",
2390 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2391 def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops GR32:$dst, GR16:$src),
2392 "movz{wl|x} {$src, $dst|$dst, $src}",
2393 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2394 def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops GR32:$dst, i16mem:$src),
2395 "movz{wl|x} {$src, $dst|$dst, $src}",
2396 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2398 def CBW : I<0x98, RawFrm, (ops),
2399 "{cbtw|cbw}", []>, Imp<[AL],[AX]>, OpSize; // AX = signext(AL)
2400 def CWDE : I<0x98, RawFrm, (ops),
2401 "{cwtl|cwde}", []>, Imp<[AX],[EAX]>; // EAX = signext(AX)
2403 def CWD : I<0x99, RawFrm, (ops),
2404 "{cwtd|cwd}", []>, Imp<[AX],[AX,DX]>, OpSize; // DX:AX = signext(AX)
2405 def CDQ : I<0x99, RawFrm, (ops),
2406 "{cltd|cdq}", []>, Imp<[EAX],[EAX,EDX]>; // EDX:EAX = signext(EAX)
2409 //===----------------------------------------------------------------------===//
2410 // Alias Instructions
2411 //===----------------------------------------------------------------------===//
2413 // Alias instructions that map movr0 to xor.
2414 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2415 def MOV8r0 : I<0x30, MRMInitReg, (ops GR8 :$dst),
2416 "xor{b} $dst, $dst",
2417 [(set GR8:$dst, 0)]>;
2418 def MOV16r0 : I<0x31, MRMInitReg, (ops GR16:$dst),
2419 "xor{w} $dst, $dst",
2420 [(set GR16:$dst, 0)]>, OpSize;
2421 def MOV32r0 : I<0x31, MRMInitReg, (ops GR32:$dst),
2422 "xor{l} $dst, $dst",
2423 [(set GR32:$dst, 0)]>;
2425 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2426 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2427 def MOV16to16_ : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16:$src),
2428 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2429 def MOV32to32_ : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32:$src),
2430 "mov{l} {$src, $dst|$dst, $src}", []>;
2432 def MOV16_rr : I<0x89, MRMDestReg, (ops GR16_:$dst, GR16_:$src),
2433 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2434 def MOV32_rr : I<0x89, MRMDestReg, (ops GR32_:$dst, GR32_:$src),
2435 "mov{l} {$src, $dst|$dst, $src}", []>;
2436 def MOV16_rm : I<0x8B, MRMSrcMem, (ops GR16_:$dst, i16mem:$src),
2437 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2438 def MOV32_rm : I<0x8B, MRMSrcMem, (ops GR32_:$dst, i32mem:$src),
2439 "mov{l} {$src, $dst|$dst, $src}", []>;
2440 def MOV16_mr : I<0x89, MRMDestMem, (ops i16mem:$dst, GR16_:$src),
2441 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
2442 def MOV32_mr : I<0x89, MRMDestMem, (ops i32mem:$dst, GR32_:$src),
2443 "mov{l} {$src, $dst|$dst, $src}", []>;
2445 //===----------------------------------------------------------------------===//
2446 // DWARF Pseudo Instructions
2449 def DWARF_LOC : I<0, Pseudo, (ops i32imm:$line, i32imm:$col, i32imm:$file),
2450 "; .loc $file, $line, $col",
2451 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2454 //===----------------------------------------------------------------------===//
2455 // Non-Instruction Patterns
2456 //===----------------------------------------------------------------------===//
2458 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2459 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2460 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2461 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2462 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2464 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2465 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2466 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2467 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2468 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2469 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2470 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2471 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2473 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2474 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2475 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2476 (MOV32mi addr:$dst, texternalsym:$src)>;
2479 def : Pat<(X86tailcall GR32:$dst),
2480 (CALL32r GR32:$dst)>;
2482 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2483 (CALLpcrel32 tglobaladdr:$dst)>;
2484 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2485 (CALLpcrel32 texternalsym:$dst)>;
2487 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2488 (CALLpcrel32 tglobaladdr:$dst)>;
2489 def : Pat<(X86call (i32 texternalsym:$dst)),
2490 (CALLpcrel32 texternalsym:$dst)>;
2492 // X86 specific add which produces a flag.
2493 def : Pat<(addc GR32:$src1, GR32:$src2),
2494 (ADD32rr GR32:$src1, GR32:$src2)>;
2495 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2496 (ADD32rm GR32:$src1, addr:$src2)>;
2497 def : Pat<(addc GR32:$src1, imm:$src2),
2498 (ADD32ri GR32:$src1, imm:$src2)>;
2499 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2500 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2502 def : Pat<(subc GR32:$src1, GR32:$src2),
2503 (SUB32rr GR32:$src1, GR32:$src2)>;
2504 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2505 (SUB32rm GR32:$src1, addr:$src2)>;
2506 def : Pat<(subc GR32:$src1, imm:$src2),
2507 (SUB32ri GR32:$src1, imm:$src2)>;
2508 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2509 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2511 def : Pat<(truncstorei1 (i8 imm:$src), addr:$dst),
2512 (MOV8mi addr:$dst, imm:$src)>;
2513 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
2514 (MOV8mr addr:$dst, GR8:$src)>;
2518 // TEST R,R is smaller than CMP R,0
2519 def : Pat<(X86cmp GR8:$src1, 0),
2520 (TEST8rr GR8:$src1, GR8:$src1)>;
2521 def : Pat<(X86cmp GR16:$src1, 0),
2522 (TEST16rr GR16:$src1, GR16:$src1)>;
2523 def : Pat<(X86cmp GR32:$src1, 0),
2524 (TEST32rr GR32:$src1, GR32:$src1)>;
2526 // {s|z}extload bool -> {s|z}extload byte
2527 def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
2528 def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
2529 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2530 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2531 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2533 // extload bool -> extload byte
2534 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2535 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2536 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2537 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
2538 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2539 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2542 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
2543 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
2544 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
2545 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
2546 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
2547 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
2549 //===----------------------------------------------------------------------===//
2551 //===----------------------------------------------------------------------===//
2553 // (shl x, 1) ==> (add x, x)
2554 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2555 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2556 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2558 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2559 def : Pat<(or (srl GR32:$src1, CL:$amt),
2560 (shl GR32:$src2, (sub 32, CL:$amt))),
2561 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2563 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2564 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2565 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2567 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2568 def : Pat<(or (shl GR32:$src1, CL:$amt),
2569 (srl GR32:$src2, (sub 32, CL:$amt))),
2570 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2572 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2573 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2574 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2576 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2577 def : Pat<(or (srl GR16:$src1, CL:$amt),
2578 (shl GR16:$src2, (sub 16, CL:$amt))),
2579 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2581 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2582 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2583 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2585 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2586 def : Pat<(or (shl GR16:$src1, CL:$amt),
2587 (srl GR16:$src2, (sub 16, CL:$amt))),
2588 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2590 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
2591 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2592 (SHLD16mrCL addr:$dst, GR16:$src2)>;
2595 //===----------------------------------------------------------------------===//
2596 // Floating Point Stack Support
2597 //===----------------------------------------------------------------------===//
2599 include "X86InstrFPStack.td"
2601 //===----------------------------------------------------------------------===//
2602 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
2603 //===----------------------------------------------------------------------===//
2605 include "X86InstrMMX.td"
2607 //===----------------------------------------------------------------------===//
2608 // XMM Floating point support (requires SSE / SSE2)
2609 //===----------------------------------------------------------------------===//
2611 include "X86InstrSSE.td"
2613 //===----------------------------------------------------------------------===//
2615 //===----------------------------------------------------------------------===//
2617 include "X86InstrX86-64.td"