3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
44 def SDTX86SetCC_C : SDTypeProfile<1, 2,
46 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
48 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
50 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
52 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
53 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
54 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
56 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
57 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
60 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
62 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
66 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
68 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
70 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
72 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
74 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
76 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
78 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
80 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
81 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
82 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
83 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
85 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
140 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
141 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
142 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
143 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
146 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
147 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
149 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
150 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
152 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
153 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
154 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
155 SDT_X86SegmentBaseAddress, []>;
157 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
160 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
161 [SDNPHasChain, SDNPOptInFlag]>;
163 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
165 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
166 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
168 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
170 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
171 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
172 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
174 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
176 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
179 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
181 //===----------------------------------------------------------------------===//
182 // X86 Operand Definitions.
185 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
186 // the index operand of an address, to conform to x86 encoding restrictions.
187 def ptr_rc_nosp : PointerLikeRegClass<1>;
189 // *mem - Operand definitions for the funky X86 addressing mode operands.
191 def X86MemAsmOperand : AsmOperandClass {
195 def X86AbsMemAsmOperand : AsmOperandClass {
197 let SuperClass = X86MemAsmOperand;
199 def X86NoSegMemAsmOperand : AsmOperandClass {
200 let Name = "NoSegMem";
201 let SuperClass = X86MemAsmOperand;
203 class X86MemOperand<string printMethod> : Operand<iPTR> {
204 let PrintMethod = printMethod;
205 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
206 let ParserMatchClass = X86MemAsmOperand;
209 def opaque32mem : X86MemOperand<"printopaquemem">;
210 def opaque48mem : X86MemOperand<"printopaquemem">;
211 def opaque80mem : X86MemOperand<"printopaquemem">;
212 def opaque512mem : X86MemOperand<"printopaquemem">;
214 def i8mem : X86MemOperand<"printi8mem">;
215 def i16mem : X86MemOperand<"printi16mem">;
216 def i32mem : X86MemOperand<"printi32mem">;
217 def i64mem : X86MemOperand<"printi64mem">;
218 def i128mem : X86MemOperand<"printi128mem">;
219 //def i256mem : X86MemOperand<"printi256mem">;
220 def f32mem : X86MemOperand<"printf32mem">;
221 def f64mem : X86MemOperand<"printf64mem">;
222 def f80mem : X86MemOperand<"printf80mem">;
223 def f128mem : X86MemOperand<"printf128mem">;
224 //def f256mem : X86MemOperand<"printf256mem">;
226 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
227 // plain GR64, so that it doesn't potentially require a REX prefix.
228 def i8mem_NOREX : Operand<i64> {
229 let PrintMethod = "printi8mem";
230 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
231 let ParserMatchClass = X86MemAsmOperand;
234 def lea32mem : Operand<i32> {
235 let PrintMethod = "printlea32mem";
236 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
237 let ParserMatchClass = X86NoSegMemAsmOperand;
240 let ParserMatchClass = X86AbsMemAsmOperand,
241 PrintMethod = "print_pcrel_imm" in {
242 def i32imm_pcrel : Operand<i32>;
244 def offset8 : Operand<i64>;
245 def offset16 : Operand<i64>;
246 def offset32 : Operand<i64>;
247 def offset64 : Operand<i64>;
249 // Branch targets have OtherVT type and print as pc-relative values.
250 def brtarget : Operand<OtherVT>;
251 def brtarget8 : Operand<OtherVT>;
255 def SSECC : Operand<i8> {
256 let PrintMethod = "printSSECC";
259 def ImmSExt8AsmOperand : AsmOperandClass {
260 let Name = "ImmSExt8";
261 let SuperClass = ImmAsmOperand;
264 // A couple of more descriptive operand definitions.
265 // 16-bits but only 8 bits are significant.
266 def i16i8imm : Operand<i16> {
267 let ParserMatchClass = ImmSExt8AsmOperand;
269 // 32-bits but only 8 bits are significant.
270 def i32i8imm : Operand<i32> {
271 let ParserMatchClass = ImmSExt8AsmOperand;
274 //===----------------------------------------------------------------------===//
275 // X86 Complex Pattern Definitions.
278 // Define X86 specific addressing mode.
279 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
280 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
281 [add, sub, mul, X86mul_imm, shl, or, frameindex],
283 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
284 [tglobaltlsaddr], []>;
286 //===----------------------------------------------------------------------===//
287 // X86 Instruction Predicate Definitions.
288 def HasMMX : Predicate<"Subtarget->hasMMX()">;
289 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
290 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
291 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
292 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
293 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
294 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
295 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
296 def HasAVX : Predicate<"Subtarget->hasAVX()">;
297 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
298 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
299 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
300 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
301 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
302 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
303 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
304 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
305 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
306 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
307 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
308 "TM.getCodeModel() != CodeModel::Kernel">;
309 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
310 "TM.getCodeModel() == CodeModel::Kernel">;
311 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
312 def OptForSize : Predicate<"OptForSize">;
313 def OptForSpeed : Predicate<"!OptForSize">;
314 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
315 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
317 //===----------------------------------------------------------------------===//
318 // X86 Instruction Format Definitions.
321 include "X86InstrFormats.td"
323 //===----------------------------------------------------------------------===//
324 // Pattern fragments...
327 // X86 specific condition code. These correspond to CondCode in
328 // X86InstrInfo.h. They must be kept in synch.
329 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
330 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
331 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
332 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
333 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
334 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
335 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
336 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
337 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
338 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
339 def X86_COND_NO : PatLeaf<(i8 10)>;
340 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
341 def X86_COND_NS : PatLeaf<(i8 12)>;
342 def X86_COND_O : PatLeaf<(i8 13)>;
343 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
344 def X86_COND_S : PatLeaf<(i8 15)>;
346 def i16immSExt8 : PatLeaf<(i16 imm), [{
347 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
348 // sign extended field.
349 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
352 def i32immSExt8 : PatLeaf<(i32 imm), [{
353 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
354 // sign extended field.
355 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
358 // Helper fragments for loads.
359 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
360 // known to be 32-bit aligned or better. Ditto for i8 to i16.
361 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
362 LoadSDNode *LD = cast<LoadSDNode>(N);
363 if (const Value *Src = LD->getSrcValue())
364 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
365 if (PT->getAddressSpace() > 255)
367 ISD::LoadExtType ExtType = LD->getExtensionType();
368 if (ExtType == ISD::NON_EXTLOAD)
370 if (ExtType == ISD::EXTLOAD)
371 return LD->getAlignment() >= 2 && !LD->isVolatile();
375 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),
377 LoadSDNode *LD = cast<LoadSDNode>(N);
378 if (const Value *Src = LD->getSrcValue())
379 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
380 if (PT->getAddressSpace() > 255)
382 ISD::LoadExtType ExtType = LD->getExtensionType();
383 if (ExtType == ISD::EXTLOAD)
384 return LD->getAlignment() >= 2 && !LD->isVolatile();
388 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
389 LoadSDNode *LD = cast<LoadSDNode>(N);
390 if (const Value *Src = LD->getSrcValue())
391 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
392 if (PT->getAddressSpace() > 255)
394 ISD::LoadExtType ExtType = LD->getExtensionType();
395 if (ExtType == ISD::NON_EXTLOAD)
397 if (ExtType == ISD::EXTLOAD)
398 return LD->getAlignment() >= 4 && !LD->isVolatile();
402 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
403 LoadSDNode *LD = cast<LoadSDNode>(N);
404 if (const Value *Src = LD->getSrcValue())
405 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
406 if (PT->getAddressSpace() > 255)
408 if (LD->isVolatile())
410 ISD::LoadExtType ExtType = LD->getExtensionType();
411 if (ExtType == ISD::NON_EXTLOAD)
413 if (ExtType == ISD::EXTLOAD)
414 return LD->getAlignment() >= 4;
418 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
419 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
420 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
421 return PT->getAddressSpace() == 256;
425 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
426 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
427 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
428 return PT->getAddressSpace() == 257;
432 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
433 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
434 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
435 if (PT->getAddressSpace() > 255)
439 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
440 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
441 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
442 if (PT->getAddressSpace() > 255)
447 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
448 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
449 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
450 if (PT->getAddressSpace() > 255)
454 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
455 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
456 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
457 if (PT->getAddressSpace() > 255)
461 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
462 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
463 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
464 if (PT->getAddressSpace() > 255)
469 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
470 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
471 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
473 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
474 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
475 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
476 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
477 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
478 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
480 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
481 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
482 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
483 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
484 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
485 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
488 // An 'and' node with a single use.
489 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
490 return N->hasOneUse();
492 // An 'srl' node with a single use.
493 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
494 return N->hasOneUse();
496 // An 'trunc' node with a single use.
497 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
498 return N->hasOneUse();
501 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
502 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
503 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
504 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
506 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
507 APInt Mask = APInt::getAllOnesValue(BitWidth);
508 APInt KnownZero0, KnownOne0;
509 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
510 APInt KnownZero1, KnownOne1;
511 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
512 return (~KnownZero0 & ~KnownZero1) == 0;
516 // 'shld' and 'shrd' instruction patterns. Note that even though these have
517 // the srl and shl in their patterns, the C++ code must still check for them,
518 // because predicates are tested before children nodes are explored.
520 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
521 (or (srl node:$src1, node:$amt1),
522 (shl node:$src2, node:$amt2)), [{
523 assert(N->getOpcode() == ISD::OR);
524 return N->getOperand(0).getOpcode() == ISD::SRL &&
525 N->getOperand(1).getOpcode() == ISD::SHL &&
526 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
527 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
528 N->getOperand(0).getConstantOperandVal(1) ==
529 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
532 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
533 (or (shl node:$src1, node:$amt1),
534 (srl node:$src2, node:$amt2)), [{
535 assert(N->getOpcode() == ISD::OR);
536 return N->getOperand(0).getOpcode() == ISD::SHL &&
537 N->getOperand(1).getOpcode() == ISD::SRL &&
538 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
539 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
540 N->getOperand(0).getConstantOperandVal(1) ==
541 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
544 //===----------------------------------------------------------------------===//
545 // Instruction list...
548 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
549 // a stack adjustment and the codegen must know that they may modify the stack
550 // pointer before prolog-epilog rewriting occurs.
551 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
552 // sub / add which can clobber EFLAGS.
553 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
554 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
556 [(X86callseq_start timm:$amt)]>,
557 Requires<[In32BitMode]>;
558 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
560 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
561 Requires<[In32BitMode]>;
564 // x86-64 va_start lowering magic.
565 let usesCustomInserter = 1 in
566 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
569 i64imm:$regsavefi, i64imm:$offset,
571 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
572 [(X86vastart_save_xmm_regs GR8:$al,
577 let neverHasSideEffects = 1 in {
578 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
579 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
580 "nop{w}\t$zero", []>, TB, OpSize;
581 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
582 "nop{l}\t$zero", []>, TB;
586 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
587 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
588 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
589 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
591 // PIC base construction. This expands to code that looks like this:
594 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
595 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
598 //===----------------------------------------------------------------------===//
599 // Control Flow Instructions...
602 // Return instructions.
603 let isTerminator = 1, isReturn = 1, isBarrier = 1,
604 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
605 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
608 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
610 [(X86retflag timm:$amt)]>;
611 def LRET : I <0xCB, RawFrm, (outs), (ins),
613 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
617 // All branches are RawFrm, Void, Branch, and Terminators
618 let isBranch = 1, isTerminator = 1 in
619 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
620 I<opcode, RawFrm, (outs), ins, asm, pattern>;
622 let isBranch = 1, isBarrier = 1 in {
623 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
624 def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
628 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
629 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
630 [(brind GR32:$dst)]>;
631 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
632 [(brind (loadi32 addr:$dst))]>;
634 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
635 (ins i16imm:$seg, i16imm:$off),
636 "ljmp{w}\t$seg, $off", []>, OpSize;
637 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
638 (ins i16imm:$seg, i32imm:$off),
639 "ljmp{l}\t$seg, $off", []>;
641 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
642 "ljmp{w}\t{*}$dst", []>, OpSize;
643 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
644 "ljmp{l}\t{*}$dst", []>;
647 // Conditional branches
648 let Uses = [EFLAGS] in {
649 // Short conditional jumps
650 def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>;
651 def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>;
652 def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>;
653 def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>;
654 def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>;
655 def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>;
656 def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>;
657 def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>;
658 def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>;
659 def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>;
660 def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>;
661 def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>;
662 def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>;
663 def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>;
664 def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>;
665 def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>;
667 def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
669 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
670 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
671 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
672 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
673 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
674 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
675 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
676 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
677 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
678 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
679 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
680 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
682 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
683 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
684 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
685 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
686 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
687 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
688 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
689 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
691 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
692 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
693 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
694 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
695 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
696 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
697 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
698 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
699 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
700 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
701 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
702 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
707 def LOOP : I<0xE2, RawFrm, (ins brtarget8:$dst), (outs), "loop\t$dst", []>;
708 def LOOPE : I<0xE1, RawFrm, (ins brtarget8:$dst), (outs), "loope\t$dst", []>;
709 def LOOPNE : I<0xE0, RawFrm, (ins brtarget8:$dst), (outs), "loopne\t$dst", []>;
711 //===----------------------------------------------------------------------===//
712 // Call Instructions...
715 // All calls clobber the non-callee saved registers. ESP is marked as
716 // a use to prevent stack-pointer assignments that appear immediately
717 // before calls from potentially appearing dead. Uses for argument
718 // registers are added manually.
719 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
720 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
721 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
722 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
724 def CALLpcrel32 : Ii32<0xE8, RawFrm,
725 (outs), (ins i32imm_pcrel:$dst,variable_ops),
727 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
728 "call\t{*}$dst", [(X86call GR32:$dst)]>;
729 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
730 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
732 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
733 (ins i16imm:$seg, i16imm:$off),
734 "lcall{w}\t$seg, $off", []>, OpSize;
735 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
736 (ins i16imm:$seg, i32imm:$off),
737 "lcall{l}\t$seg, $off", []>;
739 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
740 "lcall{w}\t{*}$dst", []>, OpSize;
741 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
742 "lcall{l}\t{*}$dst", []>;
745 // Constructing a stack frame.
747 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
748 "enter\t$len, $lvl", []>;
752 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
753 def TCRETURNdi : I<0, Pseudo, (outs),
754 (ins i32imm:$dst, i32imm:$offset, variable_ops),
755 "#TC_RETURN $dst $offset",
758 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
759 def TCRETURNri : I<0, Pseudo, (outs),
760 (ins GR32:$dst, i32imm:$offset, variable_ops),
761 "#TC_RETURN $dst $offset",
764 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
765 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst, variable_ops),
766 "jmp\t$dst # TAILCALL",
768 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
769 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst, variable_ops),
770 "jmp{l}\t{*}$dst # TAILCALL",
772 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
773 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst, variable_ops),
774 "jmp\t{*}$dst # TAILCALL", []>;
776 //===----------------------------------------------------------------------===//
777 // Miscellaneous Instructions...
779 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
780 def LEAVE : I<0xC9, RawFrm,
781 (outs), (ins), "leave", []>;
783 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
784 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
785 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
786 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
787 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
788 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
789 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
790 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
792 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
794 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
796 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
797 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
799 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
801 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
802 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
805 let mayStore = 1 in {
806 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
808 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
809 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
811 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
813 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
814 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
818 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
819 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
820 "push{l}\t$imm", []>;
821 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
822 "push{l}\t$imm", []>;
823 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
824 "push{l}\t$imm", []>;
827 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
828 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
829 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
831 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
832 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
833 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
836 let isTwoAddress = 1 in // GR32 = bswap GR32
837 def BSWAP32r : I<0xC8, AddRegFrm,
838 (outs GR32:$dst), (ins GR32:$src),
840 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
843 // Bit scan instructions.
844 let Defs = [EFLAGS] in {
845 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
846 "bsf{w}\t{$src, $dst|$dst, $src}",
847 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
848 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
849 "bsf{w}\t{$src, $dst|$dst, $src}",
850 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
851 (implicit EFLAGS)]>, TB;
852 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
853 "bsf{l}\t{$src, $dst|$dst, $src}",
854 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
855 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
856 "bsf{l}\t{$src, $dst|$dst, $src}",
857 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
858 (implicit EFLAGS)]>, TB;
860 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
861 "bsr{w}\t{$src, $dst|$dst, $src}",
862 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
863 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
864 "bsr{w}\t{$src, $dst|$dst, $src}",
865 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
866 (implicit EFLAGS)]>, TB;
867 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
868 "bsr{l}\t{$src, $dst|$dst, $src}",
869 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
870 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
871 "bsr{l}\t{$src, $dst|$dst, $src}",
872 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
873 (implicit EFLAGS)]>, TB;
876 let neverHasSideEffects = 1 in
877 def LEA16r : I<0x8D, MRMSrcMem,
878 (outs GR16:$dst), (ins lea32mem:$src),
879 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
880 let isReMaterializable = 1 in
881 def LEA32r : I<0x8D, MRMSrcMem,
882 (outs GR32:$dst), (ins lea32mem:$src),
883 "lea{l}\t{$src|$dst}, {$dst|$src}",
884 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
886 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
887 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
888 [(X86rep_movs i8)]>, REP;
889 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
890 [(X86rep_movs i16)]>, REP, OpSize;
891 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
892 [(X86rep_movs i32)]>, REP;
895 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
896 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
897 [(X86rep_stos i8)]>, REP;
898 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
899 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
900 [(X86rep_stos i16)]>, REP, OpSize;
901 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
902 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
903 [(X86rep_stos i32)]>, REP;
905 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
906 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
907 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
909 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
910 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
911 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
913 let Defs = [RAX, RDX] in
914 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
917 let isBarrier = 1, hasCtrlDep = 1 in {
918 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
921 def SYSCALL : I<0x05, RawFrm,
922 (outs), (ins), "syscall", []>, TB;
923 def SYSRET : I<0x07, RawFrm,
924 (outs), (ins), "sysret", []>, TB;
925 def SYSENTER : I<0x34, RawFrm,
926 (outs), (ins), "sysenter", []>, TB;
927 def SYSEXIT : I<0x35, RawFrm,
928 (outs), (ins), "sysexit", []>, TB;
930 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
933 //===----------------------------------------------------------------------===//
934 // Input/Output Instructions...
936 let Defs = [AL], Uses = [DX] in
937 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
938 "in{b}\t{%dx, %al|%AL, %DX}", []>;
939 let Defs = [AX], Uses = [DX] in
940 def IN16rr : I<0xED, RawFrm, (outs), (ins),
941 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
942 let Defs = [EAX], Uses = [DX] in
943 def IN32rr : I<0xED, RawFrm, (outs), (ins),
944 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
947 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
948 "in{b}\t{$port, %al|%AL, $port}", []>;
950 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
951 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
953 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
954 "in{l}\t{$port, %eax|%EAX, $port}", []>;
956 let Uses = [DX, AL] in
957 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
958 "out{b}\t{%al, %dx|%DX, %AL}", []>;
959 let Uses = [DX, AX] in
960 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
961 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
962 let Uses = [DX, EAX] in
963 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
964 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
967 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
968 "out{b}\t{%al, $port|$port, %AL}", []>;
970 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
971 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
973 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
974 "out{l}\t{%eax, $port|$port, %EAX}", []>;
976 def IN8 : I<0x6C, RawFrm, (outs), (ins),
978 def IN16 : I<0x6D, RawFrm, (outs), (ins),
979 "ins{w}", []>, OpSize;
980 def IN32 : I<0x6D, RawFrm, (outs), (ins),
983 //===----------------------------------------------------------------------===//
984 // Move Instructions...
986 let neverHasSideEffects = 1 in {
987 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
988 "mov{b}\t{$src, $dst|$dst, $src}", []>;
989 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
990 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
991 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
992 "mov{l}\t{$src, $dst|$dst, $src}", []>;
994 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
995 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
996 "mov{b}\t{$src, $dst|$dst, $src}",
997 [(set GR8:$dst, imm:$src)]>;
998 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
999 "mov{w}\t{$src, $dst|$dst, $src}",
1000 [(set GR16:$dst, imm:$src)]>, OpSize;
1001 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1002 "mov{l}\t{$src, $dst|$dst, $src}",
1003 [(set GR32:$dst, imm:$src)]>;
1005 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1006 "mov{b}\t{$src, $dst|$dst, $src}",
1007 [(store (i8 imm:$src), addr:$dst)]>;
1008 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1009 "mov{w}\t{$src, $dst|$dst, $src}",
1010 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
1011 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1012 "mov{l}\t{$src, $dst|$dst, $src}",
1013 [(store (i32 imm:$src), addr:$dst)]>;
1015 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src),
1016 "mov{b}\t{$src, %al|%al, $src}", []>;
1017 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
1018 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1019 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1020 "mov{l}\t{$src, %eax|%eax, $src}", []>;
1022 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1023 "mov{b}\t{%al, $dst|$dst, %al}", []>;
1024 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1025 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
1026 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1027 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
1029 // Moves to and from segment registers
1030 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1031 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1032 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1033 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1034 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1035 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1036 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1037 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1039 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1040 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1041 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1042 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1043 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1044 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1046 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
1047 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1048 "mov{b}\t{$src, $dst|$dst, $src}",
1049 [(set GR8:$dst, (loadi8 addr:$src))]>;
1050 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1051 "mov{w}\t{$src, $dst|$dst, $src}",
1052 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1053 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1054 "mov{l}\t{$src, $dst|$dst, $src}",
1055 [(set GR32:$dst, (loadi32 addr:$src))]>;
1058 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1059 "mov{b}\t{$src, $dst|$dst, $src}",
1060 [(store GR8:$src, addr:$dst)]>;
1061 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1062 "mov{w}\t{$src, $dst|$dst, $src}",
1063 [(store GR16:$src, addr:$dst)]>, OpSize;
1064 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1065 "mov{l}\t{$src, $dst|$dst, $src}",
1066 [(store GR32:$src, addr:$dst)]>;
1068 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1069 // that they can be used for copying and storing h registers, which can't be
1070 // encoded when a REX prefix is present.
1071 let neverHasSideEffects = 1 in
1072 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1073 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1074 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1076 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1077 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1078 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1080 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1081 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1082 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1083 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1085 // Moves to and from debug registers
1086 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1087 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1088 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1089 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1091 // Moves to and from control registers
1092 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
1093 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1094 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
1095 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1097 //===----------------------------------------------------------------------===//
1098 // Fixed-Register Multiplication and Division Instructions...
1101 // Extra precision multiplication
1102 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1103 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1104 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1105 // This probably ought to be moved to a def : Pat<> if the
1106 // syntax can be accepted.
1107 [(set AL, (mul AL, GR8:$src)),
1108 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1110 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1111 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1113 []>, OpSize; // AX,DX = AX*GR16
1115 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1116 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1118 []>; // EAX,EDX = EAX*GR32
1120 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1121 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1123 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1124 // This probably ought to be moved to a def : Pat<> if the
1125 // syntax can be accepted.
1126 [(set AL, (mul AL, (loadi8 addr:$src))),
1127 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1129 let mayLoad = 1, neverHasSideEffects = 1 in {
1130 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1131 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1133 []>, OpSize; // AX,DX = AX*[mem16]
1135 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1136 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1138 []>; // EAX,EDX = EAX*[mem32]
1141 let neverHasSideEffects = 1 in {
1142 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1143 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1145 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1146 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1147 OpSize; // AX,DX = AX*GR16
1148 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1149 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1150 // EAX,EDX = EAX*GR32
1151 let mayLoad = 1 in {
1152 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1153 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1154 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1155 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1156 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1157 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1158 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1159 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1160 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1162 } // neverHasSideEffects
1164 // unsigned division/remainder
1165 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1166 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1167 "div{b}\t$src", []>;
1168 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1169 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1170 "div{w}\t$src", []>, OpSize;
1171 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1172 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1173 "div{l}\t$src", []>;
1174 let mayLoad = 1 in {
1175 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1176 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1177 "div{b}\t$src", []>;
1178 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1179 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1180 "div{w}\t$src", []>, OpSize;
1181 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1182 // EDX:EAX/[mem32] = EAX,EDX
1183 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1184 "div{l}\t$src", []>;
1187 // Signed division/remainder.
1188 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1189 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1190 "idiv{b}\t$src", []>;
1191 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1192 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1193 "idiv{w}\t$src", []>, OpSize;
1194 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1195 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1196 "idiv{l}\t$src", []>;
1197 let mayLoad = 1, mayLoad = 1 in {
1198 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1199 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1200 "idiv{b}\t$src", []>;
1201 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1202 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1203 "idiv{w}\t$src", []>, OpSize;
1204 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1205 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1206 // EDX:EAX/[mem32] = EAX,EDX
1207 "idiv{l}\t$src", []>;
1210 //===----------------------------------------------------------------------===//
1211 // Two address Instructions.
1213 let isTwoAddress = 1 in {
1215 // Conditional moves
1216 let Uses = [EFLAGS] in {
1218 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1219 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1220 // however that requires promoting the operands, and can induce additional
1221 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1222 // clobber EFLAGS, because if one of the operands is zero, the expansion
1223 // could involve an xor.
1224 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
1225 def CMOV_GR8 : I<0, Pseudo,
1226 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1227 "#CMOV_GR8 PSEUDO!",
1228 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1229 imm:$cond, EFLAGS))]>;
1231 let isCommutable = 1 in {
1232 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1233 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1234 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1235 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1236 X86_COND_B, EFLAGS))]>,
1238 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1239 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1240 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1241 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1242 X86_COND_B, EFLAGS))]>,
1244 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1245 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1246 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1247 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1248 X86_COND_AE, EFLAGS))]>,
1250 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1251 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1252 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1253 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1254 X86_COND_AE, EFLAGS))]>,
1256 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1257 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1258 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1259 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1260 X86_COND_E, EFLAGS))]>,
1262 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1263 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1264 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1265 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1266 X86_COND_E, EFLAGS))]>,
1268 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1269 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1270 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1271 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1272 X86_COND_NE, EFLAGS))]>,
1274 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1275 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1276 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1277 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1278 X86_COND_NE, EFLAGS))]>,
1280 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1281 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1282 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1283 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1284 X86_COND_BE, EFLAGS))]>,
1286 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1287 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1288 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1289 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1290 X86_COND_BE, EFLAGS))]>,
1292 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1293 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1294 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1295 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1296 X86_COND_A, EFLAGS))]>,
1298 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1299 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1300 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1301 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1302 X86_COND_A, EFLAGS))]>,
1304 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1305 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1306 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1307 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1308 X86_COND_L, EFLAGS))]>,
1310 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1311 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1312 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1314 X86_COND_L, EFLAGS))]>,
1316 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1317 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1318 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1319 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1320 X86_COND_GE, EFLAGS))]>,
1322 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1323 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1324 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1325 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1326 X86_COND_GE, EFLAGS))]>,
1328 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1329 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1330 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1331 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1332 X86_COND_LE, EFLAGS))]>,
1334 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1335 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1336 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1337 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1338 X86_COND_LE, EFLAGS))]>,
1340 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1341 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1342 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1343 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1344 X86_COND_G, EFLAGS))]>,
1346 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1347 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1348 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1349 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1350 X86_COND_G, EFLAGS))]>,
1352 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1353 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1354 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1355 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1356 X86_COND_S, EFLAGS))]>,
1358 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1359 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1360 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1361 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1362 X86_COND_S, EFLAGS))]>,
1364 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1365 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1366 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1367 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1368 X86_COND_NS, EFLAGS))]>,
1370 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1371 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1372 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1373 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1374 X86_COND_NS, EFLAGS))]>,
1376 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1377 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1378 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1379 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1380 X86_COND_P, EFLAGS))]>,
1382 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1383 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1384 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1385 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1386 X86_COND_P, EFLAGS))]>,
1388 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1389 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1390 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1391 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1392 X86_COND_NP, EFLAGS))]>,
1394 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1395 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1396 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1397 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1398 X86_COND_NP, EFLAGS))]>,
1400 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1401 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1402 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1403 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1404 X86_COND_O, EFLAGS))]>,
1406 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1407 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1408 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1409 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1410 X86_COND_O, EFLAGS))]>,
1412 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1413 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1414 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1415 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1416 X86_COND_NO, EFLAGS))]>,
1418 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1419 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1420 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1421 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1422 X86_COND_NO, EFLAGS))]>,
1424 } // isCommutable = 1
1426 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1427 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1428 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1429 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1430 X86_COND_B, EFLAGS))]>,
1432 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1433 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1434 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1435 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1436 X86_COND_B, EFLAGS))]>,
1438 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1439 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1440 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1441 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1442 X86_COND_AE, EFLAGS))]>,
1444 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1445 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1446 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1447 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1448 X86_COND_AE, EFLAGS))]>,
1450 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1451 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1452 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1453 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1454 X86_COND_E, EFLAGS))]>,
1456 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1457 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1458 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1459 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1460 X86_COND_E, EFLAGS))]>,
1462 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1463 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1464 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1465 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1466 X86_COND_NE, EFLAGS))]>,
1468 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1469 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1470 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1471 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1472 X86_COND_NE, EFLAGS))]>,
1474 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1475 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1476 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1477 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1478 X86_COND_BE, EFLAGS))]>,
1480 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1481 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1482 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1483 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1484 X86_COND_BE, EFLAGS))]>,
1486 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1487 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1488 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1489 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1490 X86_COND_A, EFLAGS))]>,
1492 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1493 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1494 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1495 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1496 X86_COND_A, EFLAGS))]>,
1498 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1499 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1500 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1501 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1502 X86_COND_L, EFLAGS))]>,
1504 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1505 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1506 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1507 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1508 X86_COND_L, EFLAGS))]>,
1510 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1511 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1512 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1513 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1514 X86_COND_GE, EFLAGS))]>,
1516 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1517 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1518 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1519 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1520 X86_COND_GE, EFLAGS))]>,
1522 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1523 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1524 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1525 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1526 X86_COND_LE, EFLAGS))]>,
1528 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1529 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1530 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1531 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1532 X86_COND_LE, EFLAGS))]>,
1534 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1535 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1536 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1537 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1538 X86_COND_G, EFLAGS))]>,
1540 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1541 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1542 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1543 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1544 X86_COND_G, EFLAGS))]>,
1546 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1547 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1548 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1549 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1550 X86_COND_S, EFLAGS))]>,
1552 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1553 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1554 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1555 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1556 X86_COND_S, EFLAGS))]>,
1558 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1559 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1560 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1561 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1562 X86_COND_NS, EFLAGS))]>,
1564 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1565 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1566 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1567 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1568 X86_COND_NS, EFLAGS))]>,
1570 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1571 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1572 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1573 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1574 X86_COND_P, EFLAGS))]>,
1576 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1577 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1578 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1579 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1580 X86_COND_P, EFLAGS))]>,
1582 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1583 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1584 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1585 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1586 X86_COND_NP, EFLAGS))]>,
1588 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1589 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1590 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1591 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1592 X86_COND_NP, EFLAGS))]>,
1594 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1595 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1596 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1597 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1598 X86_COND_O, EFLAGS))]>,
1600 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1601 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1602 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1603 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1604 X86_COND_O, EFLAGS))]>,
1606 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1607 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1608 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1609 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1610 X86_COND_NO, EFLAGS))]>,
1612 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1613 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1614 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1615 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1616 X86_COND_NO, EFLAGS))]>,
1618 } // Uses = [EFLAGS]
1621 // unary instructions
1622 let CodeSize = 2 in {
1623 let Defs = [EFLAGS] in {
1624 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1625 [(set GR8:$dst, (ineg GR8:$src)),
1626 (implicit EFLAGS)]>;
1627 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1628 [(set GR16:$dst, (ineg GR16:$src)),
1629 (implicit EFLAGS)]>, OpSize;
1630 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1631 [(set GR32:$dst, (ineg GR32:$src)),
1632 (implicit EFLAGS)]>;
1633 let isTwoAddress = 0 in {
1634 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1635 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1636 (implicit EFLAGS)]>;
1637 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1638 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1639 (implicit EFLAGS)]>, OpSize;
1640 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1641 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1642 (implicit EFLAGS)]>;
1644 } // Defs = [EFLAGS]
1646 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1647 let AddedComplexity = 15 in {
1648 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1649 [(set GR8:$dst, (not GR8:$src))]>;
1650 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1651 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1652 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1653 [(set GR32:$dst, (not GR32:$src))]>;
1655 let isTwoAddress = 0 in {
1656 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1657 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1658 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1659 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1660 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1661 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1665 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1666 let Defs = [EFLAGS] in {
1668 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1669 [(set GR8:$dst, (add GR8:$src, 1)),
1670 (implicit EFLAGS)]>;
1671 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1672 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1674 [(set GR16:$dst, (add GR16:$src, 1)),
1675 (implicit EFLAGS)]>,
1676 OpSize, Requires<[In32BitMode]>;
1677 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1679 [(set GR32:$dst, (add GR32:$src, 1)),
1680 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1682 let isTwoAddress = 0, CodeSize = 2 in {
1683 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1684 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1685 (implicit EFLAGS)]>;
1686 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1687 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1688 (implicit EFLAGS)]>,
1689 OpSize, Requires<[In32BitMode]>;
1690 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1691 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1692 (implicit EFLAGS)]>,
1693 Requires<[In32BitMode]>;
1697 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1698 [(set GR8:$dst, (add GR8:$src, -1)),
1699 (implicit EFLAGS)]>;
1700 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1701 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1703 [(set GR16:$dst, (add GR16:$src, -1)),
1704 (implicit EFLAGS)]>,
1705 OpSize, Requires<[In32BitMode]>;
1706 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1708 [(set GR32:$dst, (add GR32:$src, -1)),
1709 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1712 let isTwoAddress = 0, CodeSize = 2 in {
1713 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1714 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1715 (implicit EFLAGS)]>;
1716 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1717 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1718 (implicit EFLAGS)]>,
1719 OpSize, Requires<[In32BitMode]>;
1720 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1721 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1722 (implicit EFLAGS)]>,
1723 Requires<[In32BitMode]>;
1725 } // Defs = [EFLAGS]
1727 // Logical operators...
1728 let Defs = [EFLAGS] in {
1729 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1730 def AND8rr : I<0x20, MRMDestReg,
1731 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1732 "and{b}\t{$src2, $dst|$dst, $src2}",
1733 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1734 (implicit EFLAGS)]>;
1735 def AND16rr : I<0x21, MRMDestReg,
1736 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1737 "and{w}\t{$src2, $dst|$dst, $src2}",
1738 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1739 (implicit EFLAGS)]>, OpSize;
1740 def AND32rr : I<0x21, MRMDestReg,
1741 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1742 "and{l}\t{$src2, $dst|$dst, $src2}",
1743 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1744 (implicit EFLAGS)]>;
1747 // AND instructions with the destination register in REG and the source register
1748 // in R/M. Included for the disassembler.
1749 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1750 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1751 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1752 (ins GR16:$src1, GR16:$src2),
1753 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1754 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1755 (ins GR32:$src1, GR32:$src2),
1756 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1758 def AND8rm : I<0x22, MRMSrcMem,
1759 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1760 "and{b}\t{$src2, $dst|$dst, $src2}",
1761 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1762 (implicit EFLAGS)]>;
1763 def AND16rm : I<0x23, MRMSrcMem,
1764 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1765 "and{w}\t{$src2, $dst|$dst, $src2}",
1766 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1767 (implicit EFLAGS)]>, OpSize;
1768 def AND32rm : I<0x23, MRMSrcMem,
1769 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1770 "and{l}\t{$src2, $dst|$dst, $src2}",
1771 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1772 (implicit EFLAGS)]>;
1774 def AND8ri : Ii8<0x80, MRM4r,
1775 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1776 "and{b}\t{$src2, $dst|$dst, $src2}",
1777 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1778 (implicit EFLAGS)]>;
1779 def AND16ri : Ii16<0x81, MRM4r,
1780 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1781 "and{w}\t{$src2, $dst|$dst, $src2}",
1782 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1783 (implicit EFLAGS)]>, OpSize;
1784 def AND32ri : Ii32<0x81, MRM4r,
1785 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1786 "and{l}\t{$src2, $dst|$dst, $src2}",
1787 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1788 (implicit EFLAGS)]>;
1789 def AND16ri8 : Ii8<0x83, MRM4r,
1790 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1791 "and{w}\t{$src2, $dst|$dst, $src2}",
1792 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1793 (implicit EFLAGS)]>,
1795 def AND32ri8 : Ii8<0x83, MRM4r,
1796 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1797 "and{l}\t{$src2, $dst|$dst, $src2}",
1798 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1799 (implicit EFLAGS)]>;
1801 let isTwoAddress = 0 in {
1802 def AND8mr : I<0x20, MRMDestMem,
1803 (outs), (ins i8mem :$dst, GR8 :$src),
1804 "and{b}\t{$src, $dst|$dst, $src}",
1805 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1806 (implicit EFLAGS)]>;
1807 def AND16mr : I<0x21, MRMDestMem,
1808 (outs), (ins i16mem:$dst, GR16:$src),
1809 "and{w}\t{$src, $dst|$dst, $src}",
1810 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1811 (implicit EFLAGS)]>,
1813 def AND32mr : I<0x21, MRMDestMem,
1814 (outs), (ins i32mem:$dst, GR32:$src),
1815 "and{l}\t{$src, $dst|$dst, $src}",
1816 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1817 (implicit EFLAGS)]>;
1818 def AND8mi : Ii8<0x80, MRM4m,
1819 (outs), (ins i8mem :$dst, i8imm :$src),
1820 "and{b}\t{$src, $dst|$dst, $src}",
1821 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1822 (implicit EFLAGS)]>;
1823 def AND16mi : Ii16<0x81, MRM4m,
1824 (outs), (ins i16mem:$dst, i16imm:$src),
1825 "and{w}\t{$src, $dst|$dst, $src}",
1826 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1827 (implicit EFLAGS)]>,
1829 def AND32mi : Ii32<0x81, MRM4m,
1830 (outs), (ins i32mem:$dst, i32imm:$src),
1831 "and{l}\t{$src, $dst|$dst, $src}",
1832 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1833 (implicit EFLAGS)]>;
1834 def AND16mi8 : Ii8<0x83, MRM4m,
1835 (outs), (ins i16mem:$dst, i16i8imm :$src),
1836 "and{w}\t{$src, $dst|$dst, $src}",
1837 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1838 (implicit EFLAGS)]>,
1840 def AND32mi8 : Ii8<0x83, MRM4m,
1841 (outs), (ins i32mem:$dst, i32i8imm :$src),
1842 "and{l}\t{$src, $dst|$dst, $src}",
1843 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1844 (implicit EFLAGS)]>;
1846 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1847 "and{b}\t{$src, %al|%al, $src}", []>;
1848 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1849 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1850 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1851 "and{l}\t{$src, %eax|%eax, $src}", []>;
1856 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1857 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1858 (ins GR8 :$src1, GR8 :$src2),
1859 "or{b}\t{$src2, $dst|$dst, $src2}",
1860 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1861 (implicit EFLAGS)]>;
1862 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1863 (ins GR16:$src1, GR16:$src2),
1864 "or{w}\t{$src2, $dst|$dst, $src2}",
1865 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1866 (implicit EFLAGS)]>, OpSize;
1867 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1868 (ins GR32:$src1, GR32:$src2),
1869 "or{l}\t{$src2, $dst|$dst, $src2}",
1870 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1871 (implicit EFLAGS)]>;
1874 // OR instructions with the destination register in REG and the source register
1875 // in R/M. Included for the disassembler.
1876 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1877 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1878 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1879 (ins GR16:$src1, GR16:$src2),
1880 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1881 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1882 (ins GR32:$src1, GR32:$src2),
1883 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1885 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst),
1886 (ins GR8 :$src1, i8mem :$src2),
1887 "or{b}\t{$src2, $dst|$dst, $src2}",
1888 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1889 (implicit EFLAGS)]>;
1890 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst),
1891 (ins GR16:$src1, i16mem:$src2),
1892 "or{w}\t{$src2, $dst|$dst, $src2}",
1893 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1894 (implicit EFLAGS)]>, OpSize;
1895 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst),
1896 (ins GR32:$src1, i32mem:$src2),
1897 "or{l}\t{$src2, $dst|$dst, $src2}",
1898 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1899 (implicit EFLAGS)]>;
1901 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1902 (ins GR8 :$src1, i8imm:$src2),
1903 "or{b}\t{$src2, $dst|$dst, $src2}",
1904 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1905 (implicit EFLAGS)]>;
1906 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1907 (ins GR16:$src1, i16imm:$src2),
1908 "or{w}\t{$src2, $dst|$dst, $src2}",
1909 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1910 (implicit EFLAGS)]>, OpSize;
1911 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1912 (ins GR32:$src1, i32imm:$src2),
1913 "or{l}\t{$src2, $dst|$dst, $src2}",
1914 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1915 (implicit EFLAGS)]>;
1917 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1918 (ins GR16:$src1, i16i8imm:$src2),
1919 "or{w}\t{$src2, $dst|$dst, $src2}",
1920 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1921 (implicit EFLAGS)]>, OpSize;
1922 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1923 (ins GR32:$src1, i32i8imm:$src2),
1924 "or{l}\t{$src2, $dst|$dst, $src2}",
1925 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1926 (implicit EFLAGS)]>;
1927 let isTwoAddress = 0 in {
1928 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1929 "or{b}\t{$src, $dst|$dst, $src}",
1930 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1931 (implicit EFLAGS)]>;
1932 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1933 "or{w}\t{$src, $dst|$dst, $src}",
1934 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1935 (implicit EFLAGS)]>, OpSize;
1936 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1937 "or{l}\t{$src, $dst|$dst, $src}",
1938 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1939 (implicit EFLAGS)]>;
1940 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1941 "or{b}\t{$src, $dst|$dst, $src}",
1942 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1943 (implicit EFLAGS)]>;
1944 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1945 "or{w}\t{$src, $dst|$dst, $src}",
1946 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1947 (implicit EFLAGS)]>,
1949 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1950 "or{l}\t{$src, $dst|$dst, $src}",
1951 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1952 (implicit EFLAGS)]>;
1953 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1954 "or{w}\t{$src, $dst|$dst, $src}",
1955 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1956 (implicit EFLAGS)]>,
1958 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1959 "or{l}\t{$src, $dst|$dst, $src}",
1960 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1961 (implicit EFLAGS)]>;
1963 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1964 "or{b}\t{$src, %al|%al, $src}", []>;
1965 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1966 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1967 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1968 "or{l}\t{$src, %eax|%eax, $src}", []>;
1969 } // isTwoAddress = 0
1972 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1973 def XOR8rr : I<0x30, MRMDestReg,
1974 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1975 "xor{b}\t{$src2, $dst|$dst, $src2}",
1976 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1977 (implicit EFLAGS)]>;
1978 def XOR16rr : I<0x31, MRMDestReg,
1979 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1980 "xor{w}\t{$src2, $dst|$dst, $src2}",
1981 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1982 (implicit EFLAGS)]>, OpSize;
1983 def XOR32rr : I<0x31, MRMDestReg,
1984 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1985 "xor{l}\t{$src2, $dst|$dst, $src2}",
1986 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1987 (implicit EFLAGS)]>;
1988 } // isCommutable = 1
1990 // XOR instructions with the destination register in REG and the source register
1991 // in R/M. Included for the disassembler.
1992 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1993 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
1994 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
1995 (ins GR16:$src1, GR16:$src2),
1996 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1997 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
1998 (ins GR32:$src1, GR32:$src2),
1999 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2001 def XOR8rm : I<0x32, MRMSrcMem ,
2002 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2003 "xor{b}\t{$src2, $dst|$dst, $src2}",
2004 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
2005 (implicit EFLAGS)]>;
2006 def XOR16rm : I<0x33, MRMSrcMem ,
2007 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2008 "xor{w}\t{$src2, $dst|$dst, $src2}",
2009 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
2010 (implicit EFLAGS)]>,
2012 def XOR32rm : I<0x33, MRMSrcMem ,
2013 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2014 "xor{l}\t{$src2, $dst|$dst, $src2}",
2015 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
2016 (implicit EFLAGS)]>;
2018 def XOR8ri : Ii8<0x80, MRM6r,
2019 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2020 "xor{b}\t{$src2, $dst|$dst, $src2}",
2021 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
2022 (implicit EFLAGS)]>;
2023 def XOR16ri : Ii16<0x81, MRM6r,
2024 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2025 "xor{w}\t{$src2, $dst|$dst, $src2}",
2026 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
2027 (implicit EFLAGS)]>, OpSize;
2028 def XOR32ri : Ii32<0x81, MRM6r,
2029 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2030 "xor{l}\t{$src2, $dst|$dst, $src2}",
2031 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
2032 (implicit EFLAGS)]>;
2033 def XOR16ri8 : Ii8<0x83, MRM6r,
2034 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2035 "xor{w}\t{$src2, $dst|$dst, $src2}",
2036 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
2037 (implicit EFLAGS)]>,
2039 def XOR32ri8 : Ii8<0x83, MRM6r,
2040 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2041 "xor{l}\t{$src2, $dst|$dst, $src2}",
2042 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
2043 (implicit EFLAGS)]>;
2045 let isTwoAddress = 0 in {
2046 def XOR8mr : I<0x30, MRMDestMem,
2047 (outs), (ins i8mem :$dst, GR8 :$src),
2048 "xor{b}\t{$src, $dst|$dst, $src}",
2049 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2050 (implicit EFLAGS)]>;
2051 def XOR16mr : I<0x31, MRMDestMem,
2052 (outs), (ins i16mem:$dst, GR16:$src),
2053 "xor{w}\t{$src, $dst|$dst, $src}",
2054 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2055 (implicit EFLAGS)]>,
2057 def XOR32mr : I<0x31, MRMDestMem,
2058 (outs), (ins i32mem:$dst, GR32:$src),
2059 "xor{l}\t{$src, $dst|$dst, $src}",
2060 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2061 (implicit EFLAGS)]>;
2062 def XOR8mi : Ii8<0x80, MRM6m,
2063 (outs), (ins i8mem :$dst, i8imm :$src),
2064 "xor{b}\t{$src, $dst|$dst, $src}",
2065 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2066 (implicit EFLAGS)]>;
2067 def XOR16mi : Ii16<0x81, MRM6m,
2068 (outs), (ins i16mem:$dst, i16imm:$src),
2069 "xor{w}\t{$src, $dst|$dst, $src}",
2070 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2071 (implicit EFLAGS)]>,
2073 def XOR32mi : Ii32<0x81, MRM6m,
2074 (outs), (ins i32mem:$dst, i32imm:$src),
2075 "xor{l}\t{$src, $dst|$dst, $src}",
2076 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2077 (implicit EFLAGS)]>;
2078 def XOR16mi8 : Ii8<0x83, MRM6m,
2079 (outs), (ins i16mem:$dst, i16i8imm :$src),
2080 "xor{w}\t{$src, $dst|$dst, $src}",
2081 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2082 (implicit EFLAGS)]>,
2084 def XOR32mi8 : Ii8<0x83, MRM6m,
2085 (outs), (ins i32mem:$dst, i32i8imm :$src),
2086 "xor{l}\t{$src, $dst|$dst, $src}",
2087 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2088 (implicit EFLAGS)]>;
2090 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2091 "xor{b}\t{$src, %al|%al, $src}", []>;
2092 def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src),
2093 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2094 def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src),
2095 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2096 } // isTwoAddress = 0
2097 } // Defs = [EFLAGS]
2099 // Shift instructions
2100 let Defs = [EFLAGS] in {
2101 let Uses = [CL] in {
2102 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2103 "shl{b}\t{%cl, $dst|$dst, CL}",
2104 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2105 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2106 "shl{w}\t{%cl, $dst|$dst, CL}",
2107 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2108 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2109 "shl{l}\t{%cl, $dst|$dst, CL}",
2110 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2113 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2114 "shl{b}\t{$src2, $dst|$dst, $src2}",
2115 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2116 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2117 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2118 "shl{w}\t{$src2, $dst|$dst, $src2}",
2119 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2120 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2121 "shl{l}\t{$src2, $dst|$dst, $src2}",
2122 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2124 // NOTE: We don't include patterns for shifts of a register by one, because
2125 // 'add reg,reg' is cheaper.
2127 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2128 "shl{b}\t$dst", []>;
2129 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2130 "shl{w}\t$dst", []>, OpSize;
2131 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2132 "shl{l}\t$dst", []>;
2134 } // isConvertibleToThreeAddress = 1
2136 let isTwoAddress = 0 in {
2137 let Uses = [CL] in {
2138 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2139 "shl{b}\t{%cl, $dst|$dst, CL}",
2140 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2141 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2142 "shl{w}\t{%cl, $dst|$dst, CL}",
2143 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2144 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2145 "shl{l}\t{%cl, $dst|$dst, CL}",
2146 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2148 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2149 "shl{b}\t{$src, $dst|$dst, $src}",
2150 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2151 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2152 "shl{w}\t{$src, $dst|$dst, $src}",
2153 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2155 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2156 "shl{l}\t{$src, $dst|$dst, $src}",
2157 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2160 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2162 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2163 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2165 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2167 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2169 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2172 let Uses = [CL] in {
2173 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2174 "shr{b}\t{%cl, $dst|$dst, CL}",
2175 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2176 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2177 "shr{w}\t{%cl, $dst|$dst, CL}",
2178 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2179 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2180 "shr{l}\t{%cl, $dst|$dst, CL}",
2181 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2184 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2185 "shr{b}\t{$src2, $dst|$dst, $src2}",
2186 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2187 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2188 "shr{w}\t{$src2, $dst|$dst, $src2}",
2189 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2190 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2191 "shr{l}\t{$src2, $dst|$dst, $src2}",
2192 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2195 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2197 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2198 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2200 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2201 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2203 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2205 let isTwoAddress = 0 in {
2206 let Uses = [CL] in {
2207 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2208 "shr{b}\t{%cl, $dst|$dst, CL}",
2209 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2210 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2211 "shr{w}\t{%cl, $dst|$dst, CL}",
2212 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2214 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2215 "shr{l}\t{%cl, $dst|$dst, CL}",
2216 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2218 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2219 "shr{b}\t{$src, $dst|$dst, $src}",
2220 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2221 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2222 "shr{w}\t{$src, $dst|$dst, $src}",
2223 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2225 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2226 "shr{l}\t{$src, $dst|$dst, $src}",
2227 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2230 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2232 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2233 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2235 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2236 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2238 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2241 let Uses = [CL] in {
2242 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2243 "sar{b}\t{%cl, $dst|$dst, CL}",
2244 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2245 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2246 "sar{w}\t{%cl, $dst|$dst, CL}",
2247 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2248 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2249 "sar{l}\t{%cl, $dst|$dst, CL}",
2250 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2253 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2254 "sar{b}\t{$src2, $dst|$dst, $src2}",
2255 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2256 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2257 "sar{w}\t{$src2, $dst|$dst, $src2}",
2258 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2260 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2261 "sar{l}\t{$src2, $dst|$dst, $src2}",
2262 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2265 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2267 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2268 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2270 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2271 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2273 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2275 let isTwoAddress = 0 in {
2276 let Uses = [CL] in {
2277 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2278 "sar{b}\t{%cl, $dst|$dst, CL}",
2279 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2280 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2281 "sar{w}\t{%cl, $dst|$dst, CL}",
2282 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2283 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2284 "sar{l}\t{%cl, $dst|$dst, CL}",
2285 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2287 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2288 "sar{b}\t{$src, $dst|$dst, $src}",
2289 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2290 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2291 "sar{w}\t{$src, $dst|$dst, $src}",
2292 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2294 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2295 "sar{l}\t{$src, $dst|$dst, $src}",
2296 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2299 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2301 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2302 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2304 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2306 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2308 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2311 // Rotate instructions
2313 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2314 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2315 def RCL8m1 : I<0xD0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src),
2316 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2317 let Uses = [CL] in {
2318 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2319 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2320 def RCL8mCL : I<0xD2, MRM2m, (outs i8mem:$dst), (ins i8mem:$src),
2321 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2323 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2324 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2325 def RCL8mi : Ii8<0xC0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt),
2326 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2328 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2329 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2330 def RCL16m1 : I<0xD1, MRM2m, (outs i16mem:$dst), (ins i16mem:$src),
2331 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2332 let Uses = [CL] in {
2333 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2334 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2335 def RCL16mCL : I<0xD3, MRM2m, (outs i16mem:$dst), (ins i16mem:$src),
2336 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2338 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2339 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2340 def RCL16mi : Ii8<0xC1, MRM2m, (outs i16mem:$dst),
2341 (ins i16mem:$src, i8imm:$cnt),
2342 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2344 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2345 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2346 def RCL32m1 : I<0xD1, MRM2m, (outs i32mem:$dst), (ins i32mem:$src),
2347 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2348 let Uses = [CL] in {
2349 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2350 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2351 def RCL32mCL : I<0xD3, MRM2m, (outs i32mem:$dst), (ins i32mem:$src),
2352 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2354 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2355 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2356 def RCL32mi : Ii8<0xC1, MRM2m, (outs i32mem:$dst),
2357 (ins i32mem:$src, i8imm:$cnt),
2358 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2360 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2361 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2362 def RCR8m1 : I<0xD0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src),
2363 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2364 let Uses = [CL] in {
2365 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2366 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2367 def RCR8mCL : I<0xD2, MRM3m, (outs i8mem:$dst), (ins i8mem:$src),
2368 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2370 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2371 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2372 def RCR8mi : Ii8<0xC0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt),
2373 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2375 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2376 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2377 def RCR16m1 : I<0xD1, MRM3m, (outs i16mem:$dst), (ins i16mem:$src),
2378 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2379 let Uses = [CL] in {
2380 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2381 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2382 def RCR16mCL : I<0xD3, MRM3m, (outs i16mem:$dst), (ins i16mem:$src),
2383 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2385 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2386 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2387 def RCR16mi : Ii8<0xC1, MRM3m, (outs i16mem:$dst),
2388 (ins i16mem:$src, i8imm:$cnt),
2389 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2391 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2392 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2393 def RCR32m1 : I<0xD1, MRM3m, (outs i32mem:$dst), (ins i32mem:$src),
2394 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2395 let Uses = [CL] in {
2396 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2397 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2398 def RCR32mCL : I<0xD3, MRM3m, (outs i32mem:$dst), (ins i32mem:$src),
2399 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2401 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2402 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2403 def RCR32mi : Ii8<0xC1, MRM3m, (outs i32mem:$dst),
2404 (ins i32mem:$src, i8imm:$cnt),
2405 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2407 // FIXME: provide shorter instructions when imm8 == 1
2408 let Uses = [CL] in {
2409 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2410 "rol{b}\t{%cl, $dst|$dst, CL}",
2411 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2412 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2413 "rol{w}\t{%cl, $dst|$dst, CL}",
2414 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2415 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2416 "rol{l}\t{%cl, $dst|$dst, CL}",
2417 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2420 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2421 "rol{b}\t{$src2, $dst|$dst, $src2}",
2422 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2423 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2424 "rol{w}\t{$src2, $dst|$dst, $src2}",
2425 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2427 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2428 "rol{l}\t{$src2, $dst|$dst, $src2}",
2429 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2432 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2434 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2435 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2437 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2438 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2440 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2442 let isTwoAddress = 0 in {
2443 let Uses = [CL] in {
2444 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2445 "rol{b}\t{%cl, $dst|$dst, CL}",
2446 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2447 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2448 "rol{w}\t{%cl, $dst|$dst, CL}",
2449 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2450 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2451 "rol{l}\t{%cl, $dst|$dst, CL}",
2452 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2454 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2455 "rol{b}\t{$src, $dst|$dst, $src}",
2456 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2457 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2458 "rol{w}\t{$src, $dst|$dst, $src}",
2459 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2461 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2462 "rol{l}\t{$src, $dst|$dst, $src}",
2463 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2466 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2468 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2469 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2471 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2473 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2475 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2478 let Uses = [CL] in {
2479 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2480 "ror{b}\t{%cl, $dst|$dst, CL}",
2481 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2482 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2483 "ror{w}\t{%cl, $dst|$dst, CL}",
2484 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2485 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2486 "ror{l}\t{%cl, $dst|$dst, CL}",
2487 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2490 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2491 "ror{b}\t{$src2, $dst|$dst, $src2}",
2492 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2493 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2494 "ror{w}\t{$src2, $dst|$dst, $src2}",
2495 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2497 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2498 "ror{l}\t{$src2, $dst|$dst, $src2}",
2499 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2502 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2504 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2505 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2507 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2508 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2510 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2512 let isTwoAddress = 0 in {
2513 let Uses = [CL] in {
2514 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2515 "ror{b}\t{%cl, $dst|$dst, CL}",
2516 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2517 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2518 "ror{w}\t{%cl, $dst|$dst, CL}",
2519 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2520 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2521 "ror{l}\t{%cl, $dst|$dst, CL}",
2522 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2524 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2525 "ror{b}\t{$src, $dst|$dst, $src}",
2526 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2527 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2528 "ror{w}\t{$src, $dst|$dst, $src}",
2529 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2531 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2532 "ror{l}\t{$src, $dst|$dst, $src}",
2533 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2536 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2538 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2539 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2541 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2543 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2545 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2550 // Double shift instructions (generalizations of rotate)
2551 let Uses = [CL] in {
2552 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2553 (ins GR32:$src1, GR32:$src2),
2554 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2555 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2556 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2557 (ins GR32:$src1, GR32:$src2),
2558 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2559 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2560 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2561 (ins GR16:$src1, GR16:$src2),
2562 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2563 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2565 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2566 (ins GR16:$src1, GR16:$src2),
2567 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2568 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2572 let isCommutable = 1 in { // These instructions commute to each other.
2573 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2575 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2576 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2577 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2580 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2582 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2583 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2584 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2587 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2589 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2590 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2591 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2594 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2596 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2597 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2598 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2603 let isTwoAddress = 0 in {
2604 let Uses = [CL] in {
2605 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2606 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2607 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2609 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2610 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2611 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2614 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2615 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2616 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2617 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2618 (i8 imm:$src3)), addr:$dst)]>,
2620 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2621 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2622 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2623 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2624 (i8 imm:$src3)), addr:$dst)]>,
2627 let Uses = [CL] in {
2628 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2629 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2630 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2631 addr:$dst)]>, TB, OpSize;
2632 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2633 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2634 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2635 addr:$dst)]>, TB, OpSize;
2637 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2638 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2639 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2640 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2641 (i8 imm:$src3)), addr:$dst)]>,
2643 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2644 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2645 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2646 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2647 (i8 imm:$src3)), addr:$dst)]>,
2650 } // Defs = [EFLAGS]
2654 let Defs = [EFLAGS] in {
2655 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2656 // Register-Register Addition
2657 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2658 (ins GR8 :$src1, GR8 :$src2),
2659 "add{b}\t{$src2, $dst|$dst, $src2}",
2660 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2661 (implicit EFLAGS)]>;
2663 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2664 // Register-Register Addition
2665 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2666 (ins GR16:$src1, GR16:$src2),
2667 "add{w}\t{$src2, $dst|$dst, $src2}",
2668 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2669 (implicit EFLAGS)]>, OpSize;
2670 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2671 (ins GR32:$src1, GR32:$src2),
2672 "add{l}\t{$src2, $dst|$dst, $src2}",
2673 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2674 (implicit EFLAGS)]>;
2675 } // end isConvertibleToThreeAddress
2676 } // end isCommutable
2678 // Register-Memory Addition
2679 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2680 (ins GR8 :$src1, i8mem :$src2),
2681 "add{b}\t{$src2, $dst|$dst, $src2}",
2682 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2683 (implicit EFLAGS)]>;
2684 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2685 (ins GR16:$src1, i16mem:$src2),
2686 "add{w}\t{$src2, $dst|$dst, $src2}",
2687 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2688 (implicit EFLAGS)]>, OpSize;
2689 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2690 (ins GR32:$src1, i32mem:$src2),
2691 "add{l}\t{$src2, $dst|$dst, $src2}",
2692 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2693 (implicit EFLAGS)]>;
2695 // Register-Register Addition - Equivalent to the normal rr forms (ADD8rr,
2696 // ADD16rr, and ADD32rr), but differently encoded.
2697 def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2698 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2699 def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2700 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2701 def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2702 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2704 // Register-Integer Addition
2705 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2706 "add{b}\t{$src2, $dst|$dst, $src2}",
2707 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2708 (implicit EFLAGS)]>;
2710 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2711 // Register-Integer Addition
2712 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2713 (ins GR16:$src1, i16imm:$src2),
2714 "add{w}\t{$src2, $dst|$dst, $src2}",
2715 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2716 (implicit EFLAGS)]>, OpSize;
2717 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2718 (ins GR32:$src1, i32imm:$src2),
2719 "add{l}\t{$src2, $dst|$dst, $src2}",
2720 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2721 (implicit EFLAGS)]>;
2722 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2723 (ins GR16:$src1, i16i8imm:$src2),
2724 "add{w}\t{$src2, $dst|$dst, $src2}",
2725 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2726 (implicit EFLAGS)]>, OpSize;
2727 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2728 (ins GR32:$src1, i32i8imm:$src2),
2729 "add{l}\t{$src2, $dst|$dst, $src2}",
2730 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2731 (implicit EFLAGS)]>;
2734 let isTwoAddress = 0 in {
2735 // Memory-Register Addition
2736 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2737 "add{b}\t{$src2, $dst|$dst, $src2}",
2738 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2739 (implicit EFLAGS)]>;
2740 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2741 "add{w}\t{$src2, $dst|$dst, $src2}",
2742 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2743 (implicit EFLAGS)]>, OpSize;
2744 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2745 "add{l}\t{$src2, $dst|$dst, $src2}",
2746 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2747 (implicit EFLAGS)]>;
2748 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2749 "add{b}\t{$src2, $dst|$dst, $src2}",
2750 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2751 (implicit EFLAGS)]>;
2752 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2753 "add{w}\t{$src2, $dst|$dst, $src2}",
2754 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2755 (implicit EFLAGS)]>, OpSize;
2756 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2757 "add{l}\t{$src2, $dst|$dst, $src2}",
2758 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2759 (implicit EFLAGS)]>;
2760 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2761 "add{w}\t{$src2, $dst|$dst, $src2}",
2762 [(store (add (load addr:$dst), i16immSExt8:$src2),
2764 (implicit EFLAGS)]>, OpSize;
2765 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2766 "add{l}\t{$src2, $dst|$dst, $src2}",
2767 [(store (add (load addr:$dst), i32immSExt8:$src2),
2769 (implicit EFLAGS)]>;
2772 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2773 "add{b}\t{$src, %al|%al, $src}", []>;
2774 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2775 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2776 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2777 "add{l}\t{$src, %eax|%eax, $src}", []>;
2780 let Uses = [EFLAGS] in {
2781 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2782 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2783 "adc{b}\t{$src2, $dst|$dst, $src2}",
2784 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2785 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2786 (ins GR16:$src1, GR16:$src2),
2787 "adc{w}\t{$src2, $dst|$dst, $src2}",
2788 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2789 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2790 (ins GR32:$src1, GR32:$src2),
2791 "adc{l}\t{$src2, $dst|$dst, $src2}",
2792 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2795 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2796 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2797 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2798 (ins GR16:$src1, GR16:$src2),
2799 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2800 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2801 (ins GR32:$src1, GR32:$src2),
2802 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2804 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2805 (ins GR8:$src1, i8mem:$src2),
2806 "adc{b}\t{$src2, $dst|$dst, $src2}",
2807 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2808 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2809 (ins GR16:$src1, i16mem:$src2),
2810 "adc{w}\t{$src2, $dst|$dst, $src2}",
2811 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2813 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2814 (ins GR32:$src1, i32mem:$src2),
2815 "adc{l}\t{$src2, $dst|$dst, $src2}",
2816 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2817 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2818 "adc{b}\t{$src2, $dst|$dst, $src2}",
2819 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2820 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2821 (ins GR16:$src1, i16imm:$src2),
2822 "adc{w}\t{$src2, $dst|$dst, $src2}",
2823 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2824 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2825 (ins GR16:$src1, i16i8imm:$src2),
2826 "adc{w}\t{$src2, $dst|$dst, $src2}",
2827 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2829 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2830 (ins GR32:$src1, i32imm:$src2),
2831 "adc{l}\t{$src2, $dst|$dst, $src2}",
2832 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2833 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2834 (ins GR32:$src1, i32i8imm:$src2),
2835 "adc{l}\t{$src2, $dst|$dst, $src2}",
2836 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2838 let isTwoAddress = 0 in {
2839 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2840 "adc{b}\t{$src2, $dst|$dst, $src2}",
2841 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2842 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2843 "adc{w}\t{$src2, $dst|$dst, $src2}",
2844 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2846 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2847 "adc{l}\t{$src2, $dst|$dst, $src2}",
2848 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2849 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2850 "adc{b}\t{$src2, $dst|$dst, $src2}",
2851 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2852 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2853 "adc{w}\t{$src2, $dst|$dst, $src2}",
2854 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2856 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2857 "adc{w}\t{$src2, $dst|$dst, $src2}",
2858 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2860 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2861 "adc{l}\t{$src2, $dst|$dst, $src2}",
2862 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2863 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2864 "adc{l}\t{$src2, $dst|$dst, $src2}",
2865 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2867 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2868 "adc{b}\t{$src, %al|%al, $src}", []>;
2869 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2870 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2871 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2872 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2874 } // Uses = [EFLAGS]
2876 // Register-Register Subtraction
2877 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2878 "sub{b}\t{$src2, $dst|$dst, $src2}",
2879 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2880 (implicit EFLAGS)]>;
2881 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2882 "sub{w}\t{$src2, $dst|$dst, $src2}",
2883 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2884 (implicit EFLAGS)]>, OpSize;
2885 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2886 "sub{l}\t{$src2, $dst|$dst, $src2}",
2887 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2888 (implicit EFLAGS)]>;
2890 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2891 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2892 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2893 (ins GR16:$src1, GR16:$src2),
2894 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2895 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2896 (ins GR32:$src1, GR32:$src2),
2897 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2899 // Register-Memory Subtraction
2900 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2901 (ins GR8 :$src1, i8mem :$src2),
2902 "sub{b}\t{$src2, $dst|$dst, $src2}",
2903 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2904 (implicit EFLAGS)]>;
2905 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2906 (ins GR16:$src1, i16mem:$src2),
2907 "sub{w}\t{$src2, $dst|$dst, $src2}",
2908 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2909 (implicit EFLAGS)]>, OpSize;
2910 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2911 (ins GR32:$src1, i32mem:$src2),
2912 "sub{l}\t{$src2, $dst|$dst, $src2}",
2913 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2914 (implicit EFLAGS)]>;
2916 // Register-Integer Subtraction
2917 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2918 (ins GR8:$src1, i8imm:$src2),
2919 "sub{b}\t{$src2, $dst|$dst, $src2}",
2920 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2921 (implicit EFLAGS)]>;
2922 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2923 (ins GR16:$src1, i16imm:$src2),
2924 "sub{w}\t{$src2, $dst|$dst, $src2}",
2925 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2926 (implicit EFLAGS)]>, OpSize;
2927 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2928 (ins GR32:$src1, i32imm:$src2),
2929 "sub{l}\t{$src2, $dst|$dst, $src2}",
2930 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2931 (implicit EFLAGS)]>;
2932 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2933 (ins GR16:$src1, i16i8imm:$src2),
2934 "sub{w}\t{$src2, $dst|$dst, $src2}",
2935 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2936 (implicit EFLAGS)]>, OpSize;
2937 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2938 (ins GR32:$src1, i32i8imm:$src2),
2939 "sub{l}\t{$src2, $dst|$dst, $src2}",
2940 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2941 (implicit EFLAGS)]>;
2943 let isTwoAddress = 0 in {
2944 // Memory-Register Subtraction
2945 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2946 "sub{b}\t{$src2, $dst|$dst, $src2}",
2947 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2948 (implicit EFLAGS)]>;
2949 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2950 "sub{w}\t{$src2, $dst|$dst, $src2}",
2951 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2952 (implicit EFLAGS)]>, OpSize;
2953 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2954 "sub{l}\t{$src2, $dst|$dst, $src2}",
2955 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2956 (implicit EFLAGS)]>;
2958 // Memory-Integer Subtraction
2959 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2960 "sub{b}\t{$src2, $dst|$dst, $src2}",
2961 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2962 (implicit EFLAGS)]>;
2963 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2964 "sub{w}\t{$src2, $dst|$dst, $src2}",
2965 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2966 (implicit EFLAGS)]>, OpSize;
2967 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2968 "sub{l}\t{$src2, $dst|$dst, $src2}",
2969 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2970 (implicit EFLAGS)]>;
2971 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2972 "sub{w}\t{$src2, $dst|$dst, $src2}",
2973 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2975 (implicit EFLAGS)]>, OpSize;
2976 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2977 "sub{l}\t{$src2, $dst|$dst, $src2}",
2978 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2980 (implicit EFLAGS)]>;
2982 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
2983 "sub{b}\t{$src, %al|%al, $src}", []>;
2984 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
2985 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2986 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
2987 "sub{l}\t{$src, %eax|%eax, $src}", []>;
2990 let Uses = [EFLAGS] in {
2991 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2992 (ins GR8:$src1, GR8:$src2),
2993 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2994 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2995 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2996 (ins GR16:$src1, GR16:$src2),
2997 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2998 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2999 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3000 (ins GR32:$src1, GR32:$src2),
3001 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3002 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3004 let isTwoAddress = 0 in {
3005 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3006 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3007 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3008 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3009 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3010 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3012 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3013 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3014 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3015 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3016 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3017 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3018 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3019 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3020 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3022 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3023 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3024 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3026 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3027 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3028 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3029 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3030 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3031 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3033 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3034 "sbb{b}\t{$src, %al|%al, $src}", []>;
3035 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3036 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3037 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3038 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3041 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3042 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3043 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3044 (ins GR16:$src1, GR16:$src2),
3045 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3046 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3047 (ins GR32:$src1, GR32:$src2),
3048 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3050 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3051 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3052 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3053 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3054 (ins GR16:$src1, i16mem:$src2),
3055 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3056 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3058 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3059 (ins GR32:$src1, i32mem:$src2),
3060 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3061 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3062 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3063 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3064 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3065 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3066 (ins GR16:$src1, i16imm:$src2),
3067 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3068 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3069 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3070 (ins GR16:$src1, i16i8imm:$src2),
3071 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3072 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3074 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3075 (ins GR32:$src1, i32imm:$src2),
3076 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3077 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3078 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3079 (ins GR32:$src1, i32i8imm:$src2),
3080 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3081 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3082 } // Uses = [EFLAGS]
3083 } // Defs = [EFLAGS]
3085 let Defs = [EFLAGS] in {
3086 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3087 // Register-Register Signed Integer Multiply
3088 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3089 "imul{w}\t{$src2, $dst|$dst, $src2}",
3090 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
3091 (implicit EFLAGS)]>, TB, OpSize;
3092 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3093 "imul{l}\t{$src2, $dst|$dst, $src2}",
3094 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
3095 (implicit EFLAGS)]>, TB;
3098 // Register-Memory Signed Integer Multiply
3099 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3100 (ins GR16:$src1, i16mem:$src2),
3101 "imul{w}\t{$src2, $dst|$dst, $src2}",
3102 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
3103 (implicit EFLAGS)]>, TB, OpSize;
3104 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3105 (ins GR32:$src1, i32mem:$src2),
3106 "imul{l}\t{$src2, $dst|$dst, $src2}",
3107 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
3108 (implicit EFLAGS)]>, TB;
3109 } // Defs = [EFLAGS]
3110 } // end Two Address instructions
3112 // Suprisingly enough, these are not two address instructions!
3113 let Defs = [EFLAGS] in {
3114 // Register-Integer Signed Integer Multiply
3115 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3116 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3117 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3118 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
3119 (implicit EFLAGS)]>, OpSize;
3120 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3121 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3122 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3123 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
3124 (implicit EFLAGS)]>;
3125 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3126 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3127 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3128 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
3129 (implicit EFLAGS)]>, OpSize;
3130 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3131 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3132 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3133 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
3134 (implicit EFLAGS)]>;
3136 // Memory-Integer Signed Integer Multiply
3137 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3138 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3139 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3140 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
3141 (implicit EFLAGS)]>, OpSize;
3142 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3143 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3144 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3145 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
3146 (implicit EFLAGS)]>;
3147 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3148 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3149 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3150 [(set GR16:$dst, (mul (load addr:$src1),
3151 i16immSExt8:$src2)),
3152 (implicit EFLAGS)]>, OpSize;
3153 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3154 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3155 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3156 [(set GR32:$dst, (mul (load addr:$src1),
3157 i32immSExt8:$src2)),
3158 (implicit EFLAGS)]>;
3159 } // Defs = [EFLAGS]
3161 //===----------------------------------------------------------------------===//
3162 // Test instructions are just like AND, except they don't generate a result.
3164 let Defs = [EFLAGS] in {
3165 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3166 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
3167 "test{b}\t{$src2, $src1|$src1, $src2}",
3168 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
3169 (implicit EFLAGS)]>;
3170 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3171 "test{w}\t{$src2, $src1|$src1, $src2}",
3172 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
3173 (implicit EFLAGS)]>,
3175 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3176 "test{l}\t{$src2, $src1|$src1, $src2}",
3177 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
3178 (implicit EFLAGS)]>;
3181 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3182 "test{b}\t{$src, %al|%al, $src}", []>;
3183 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3184 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3185 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3186 "test{l}\t{$src, %eax|%eax, $src}", []>;
3188 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3189 "test{b}\t{$src2, $src1|$src1, $src2}",
3190 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
3191 (implicit EFLAGS)]>;
3192 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3193 "test{w}\t{$src2, $src1|$src1, $src2}",
3194 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
3195 (implicit EFLAGS)]>, OpSize;
3196 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3197 "test{l}\t{$src2, $src1|$src1, $src2}",
3198 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
3199 (implicit EFLAGS)]>;
3201 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3202 (outs), (ins GR8:$src1, i8imm:$src2),
3203 "test{b}\t{$src2, $src1|$src1, $src2}",
3204 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
3205 (implicit EFLAGS)]>;
3206 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3207 (outs), (ins GR16:$src1, i16imm:$src2),
3208 "test{w}\t{$src2, $src1|$src1, $src2}",
3209 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
3210 (implicit EFLAGS)]>, OpSize;
3211 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3212 (outs), (ins GR32:$src1, i32imm:$src2),
3213 "test{l}\t{$src2, $src1|$src1, $src2}",
3214 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
3215 (implicit EFLAGS)]>;
3217 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3218 (outs), (ins i8mem:$src1, i8imm:$src2),
3219 "test{b}\t{$src2, $src1|$src1, $src2}",
3220 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
3221 (implicit EFLAGS)]>;
3222 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3223 (outs), (ins i16mem:$src1, i16imm:$src2),
3224 "test{w}\t{$src2, $src1|$src1, $src2}",
3225 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
3226 (implicit EFLAGS)]>, OpSize;
3227 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3228 (outs), (ins i32mem:$src1, i32imm:$src2),
3229 "test{l}\t{$src2, $src1|$src1, $src2}",
3230 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
3231 (implicit EFLAGS)]>;
3232 } // Defs = [EFLAGS]
3235 // Condition code ops, incl. set if equal/not equal/...
3236 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3237 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3238 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3239 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3241 let Uses = [EFLAGS] in {
3242 // Use sbb to materialize carry bit.
3244 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3245 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins),
3246 "sbb{b}\t$dst, $dst",
3247 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3248 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins),
3249 "sbb{w}\t$dst, $dst",
3250 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3252 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins),
3253 "sbb{l}\t$dst, $dst",
3254 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3257 def SETEr : I<0x94, MRM0r,
3258 (outs GR8 :$dst), (ins),
3260 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3262 def SETEm : I<0x94, MRM0m,
3263 (outs), (ins i8mem:$dst),
3265 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3268 def SETNEr : I<0x95, MRM0r,
3269 (outs GR8 :$dst), (ins),
3271 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3273 def SETNEm : I<0x95, MRM0m,
3274 (outs), (ins i8mem:$dst),
3276 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3279 def SETLr : I<0x9C, MRM0r,
3280 (outs GR8 :$dst), (ins),
3282 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3283 TB; // GR8 = < signed
3284 def SETLm : I<0x9C, MRM0m,
3285 (outs), (ins i8mem:$dst),
3287 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3288 TB; // [mem8] = < signed
3290 def SETGEr : I<0x9D, MRM0r,
3291 (outs GR8 :$dst), (ins),
3293 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3294 TB; // GR8 = >= signed
3295 def SETGEm : I<0x9D, MRM0m,
3296 (outs), (ins i8mem:$dst),
3298 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3299 TB; // [mem8] = >= signed
3301 def SETLEr : I<0x9E, MRM0r,
3302 (outs GR8 :$dst), (ins),
3304 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3305 TB; // GR8 = <= signed
3306 def SETLEm : I<0x9E, MRM0m,
3307 (outs), (ins i8mem:$dst),
3309 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3310 TB; // [mem8] = <= signed
3312 def SETGr : I<0x9F, MRM0r,
3313 (outs GR8 :$dst), (ins),
3315 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3316 TB; // GR8 = > signed
3317 def SETGm : I<0x9F, MRM0m,
3318 (outs), (ins i8mem:$dst),
3320 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3321 TB; // [mem8] = > signed
3323 def SETBr : I<0x92, MRM0r,
3324 (outs GR8 :$dst), (ins),
3326 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3327 TB; // GR8 = < unsign
3328 def SETBm : I<0x92, MRM0m,
3329 (outs), (ins i8mem:$dst),
3331 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3332 TB; // [mem8] = < unsign
3334 def SETAEr : I<0x93, MRM0r,
3335 (outs GR8 :$dst), (ins),
3337 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3338 TB; // GR8 = >= unsign
3339 def SETAEm : I<0x93, MRM0m,
3340 (outs), (ins i8mem:$dst),
3342 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3343 TB; // [mem8] = >= unsign
3345 def SETBEr : I<0x96, MRM0r,
3346 (outs GR8 :$dst), (ins),
3348 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3349 TB; // GR8 = <= unsign
3350 def SETBEm : I<0x96, MRM0m,
3351 (outs), (ins i8mem:$dst),
3353 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3354 TB; // [mem8] = <= unsign
3356 def SETAr : I<0x97, MRM0r,
3357 (outs GR8 :$dst), (ins),
3359 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3360 TB; // GR8 = > signed
3361 def SETAm : I<0x97, MRM0m,
3362 (outs), (ins i8mem:$dst),
3364 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3365 TB; // [mem8] = > signed
3367 def SETSr : I<0x98, MRM0r,
3368 (outs GR8 :$dst), (ins),
3370 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3371 TB; // GR8 = <sign bit>
3372 def SETSm : I<0x98, MRM0m,
3373 (outs), (ins i8mem:$dst),
3375 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3376 TB; // [mem8] = <sign bit>
3377 def SETNSr : I<0x99, MRM0r,
3378 (outs GR8 :$dst), (ins),
3380 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3381 TB; // GR8 = !<sign bit>
3382 def SETNSm : I<0x99, MRM0m,
3383 (outs), (ins i8mem:$dst),
3385 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3386 TB; // [mem8] = !<sign bit>
3388 def SETPr : I<0x9A, MRM0r,
3389 (outs GR8 :$dst), (ins),
3391 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3393 def SETPm : I<0x9A, MRM0m,
3394 (outs), (ins i8mem:$dst),
3396 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3397 TB; // [mem8] = parity
3398 def SETNPr : I<0x9B, MRM0r,
3399 (outs GR8 :$dst), (ins),
3401 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3402 TB; // GR8 = not parity
3403 def SETNPm : I<0x9B, MRM0m,
3404 (outs), (ins i8mem:$dst),
3406 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3407 TB; // [mem8] = not parity
3409 def SETOr : I<0x90, MRM0r,
3410 (outs GR8 :$dst), (ins),
3412 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3413 TB; // GR8 = overflow
3414 def SETOm : I<0x90, MRM0m,
3415 (outs), (ins i8mem:$dst),
3417 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3418 TB; // [mem8] = overflow
3419 def SETNOr : I<0x91, MRM0r,
3420 (outs GR8 :$dst), (ins),
3422 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3423 TB; // GR8 = not overflow
3424 def SETNOm : I<0x91, MRM0m,
3425 (outs), (ins i8mem:$dst),
3427 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3428 TB; // [mem8] = not overflow
3429 } // Uses = [EFLAGS]
3432 // Integer comparisons
3433 let Defs = [EFLAGS] in {
3434 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3435 "cmp{b}\t{$src, %al|%al, $src}", []>;
3436 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3437 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3438 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3439 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3441 def CMP8rr : I<0x38, MRMDestReg,
3442 (outs), (ins GR8 :$src1, GR8 :$src2),
3443 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3444 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
3445 def CMP16rr : I<0x39, MRMDestReg,
3446 (outs), (ins GR16:$src1, GR16:$src2),
3447 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3448 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
3449 def CMP32rr : I<0x39, MRMDestReg,
3450 (outs), (ins GR32:$src1, GR32:$src2),
3451 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3452 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
3453 def CMP8mr : I<0x38, MRMDestMem,
3454 (outs), (ins i8mem :$src1, GR8 :$src2),
3455 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3456 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
3457 (implicit EFLAGS)]>;
3458 def CMP16mr : I<0x39, MRMDestMem,
3459 (outs), (ins i16mem:$src1, GR16:$src2),
3460 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3461 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
3462 (implicit EFLAGS)]>, OpSize;
3463 def CMP32mr : I<0x39, MRMDestMem,
3464 (outs), (ins i32mem:$src1, GR32:$src2),
3465 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3466 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
3467 (implicit EFLAGS)]>;
3468 def CMP8rm : I<0x3A, MRMSrcMem,
3469 (outs), (ins GR8 :$src1, i8mem :$src2),
3470 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3471 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
3472 (implicit EFLAGS)]>;
3473 def CMP16rm : I<0x3B, MRMSrcMem,
3474 (outs), (ins GR16:$src1, i16mem:$src2),
3475 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3476 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
3477 (implicit EFLAGS)]>, OpSize;
3478 def CMP32rm : I<0x3B, MRMSrcMem,
3479 (outs), (ins GR32:$src1, i32mem:$src2),
3480 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3481 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
3482 (implicit EFLAGS)]>;
3483 def CMP8mrmrr : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3484 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3485 def CMP16mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3486 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3487 def CMP32mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3488 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3489 def CMP8ri : Ii8<0x80, MRM7r,
3490 (outs), (ins GR8:$src1, i8imm:$src2),
3491 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3492 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
3493 def CMP16ri : Ii16<0x81, MRM7r,
3494 (outs), (ins GR16:$src1, i16imm:$src2),
3495 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3496 [(X86cmp GR16:$src1, imm:$src2),
3497 (implicit EFLAGS)]>, OpSize;
3498 def CMP32ri : Ii32<0x81, MRM7r,
3499 (outs), (ins GR32:$src1, i32imm:$src2),
3500 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3501 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
3502 def CMP8mi : Ii8 <0x80, MRM7m,
3503 (outs), (ins i8mem :$src1, i8imm :$src2),
3504 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3505 [(X86cmp (loadi8 addr:$src1), imm:$src2),
3506 (implicit EFLAGS)]>;
3507 def CMP16mi : Ii16<0x81, MRM7m,
3508 (outs), (ins i16mem:$src1, i16imm:$src2),
3509 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3510 [(X86cmp (loadi16 addr:$src1), imm:$src2),
3511 (implicit EFLAGS)]>, OpSize;
3512 def CMP32mi : Ii32<0x81, MRM7m,
3513 (outs), (ins i32mem:$src1, i32imm:$src2),
3514 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3515 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3516 (implicit EFLAGS)]>;
3517 def CMP16ri8 : Ii8<0x83, MRM7r,
3518 (outs), (ins GR16:$src1, i16i8imm:$src2),
3519 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3520 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3521 (implicit EFLAGS)]>, OpSize;
3522 def CMP16mi8 : Ii8<0x83, MRM7m,
3523 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3524 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3525 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3526 (implicit EFLAGS)]>, OpSize;
3527 def CMP32mi8 : Ii8<0x83, MRM7m,
3528 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3529 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3530 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3531 (implicit EFLAGS)]>;
3532 def CMP32ri8 : Ii8<0x83, MRM7r,
3533 (outs), (ins GR32:$src1, i32i8imm:$src2),
3534 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3535 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3536 (implicit EFLAGS)]>;
3537 } // Defs = [EFLAGS]
3540 // TODO: BTC, BTR, and BTS
3541 let Defs = [EFLAGS] in {
3542 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3543 "bt{w}\t{$src2, $src1|$src1, $src2}",
3544 [(X86bt GR16:$src1, GR16:$src2),
3545 (implicit EFLAGS)]>, OpSize, TB;
3546 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3547 "bt{l}\t{$src2, $src1|$src1, $src2}",
3548 [(X86bt GR32:$src1, GR32:$src2),
3549 (implicit EFLAGS)]>, TB;
3551 // Unlike with the register+register form, the memory+register form of the
3552 // bt instruction does not ignore the high bits of the index. From ISel's
3553 // perspective, this is pretty bizarre. Make these instructions disassembly
3556 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3557 "bt{w}\t{$src2, $src1|$src1, $src2}",
3558 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3559 // (implicit EFLAGS)]
3561 >, OpSize, TB, Requires<[FastBTMem]>;
3562 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3563 "bt{l}\t{$src2, $src1|$src1, $src2}",
3564 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3565 // (implicit EFLAGS)]
3567 >, TB, Requires<[FastBTMem]>;
3569 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3570 "bt{w}\t{$src2, $src1|$src1, $src2}",
3571 [(X86bt GR16:$src1, i16immSExt8:$src2),
3572 (implicit EFLAGS)]>, OpSize, TB;
3573 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3574 "bt{l}\t{$src2, $src1|$src1, $src2}",
3575 [(X86bt GR32:$src1, i32immSExt8:$src2),
3576 (implicit EFLAGS)]>, TB;
3577 // Note that these instructions don't need FastBTMem because that
3578 // only applies when the other operand is in a register. When it's
3579 // an immediate, bt is still fast.
3580 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3581 "bt{w}\t{$src2, $src1|$src1, $src2}",
3582 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3583 (implicit EFLAGS)]>, OpSize, TB;
3584 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3585 "bt{l}\t{$src2, $src1|$src1, $src2}",
3586 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3587 (implicit EFLAGS)]>, TB;
3589 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3590 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3591 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3592 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3593 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3594 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3595 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3596 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3597 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3598 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3599 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3600 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3601 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3602 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3603 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3604 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3606 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3607 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3608 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3609 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3610 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3611 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3612 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3613 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3614 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3615 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3616 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3617 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3618 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3619 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3620 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3621 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3623 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3624 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3625 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3626 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3627 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3628 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3629 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3630 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3631 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3632 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3633 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3634 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3635 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3636 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3637 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3638 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3639 } // Defs = [EFLAGS]
3641 // Sign/Zero extenders
3642 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3643 // of the register here. This has a smaller encoding and avoids a
3644 // partial-register update. Actual movsbw included for the disassembler.
3645 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3646 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3647 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3648 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3649 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3650 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3651 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3652 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3653 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3654 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3655 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3656 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3657 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3658 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3659 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3660 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3661 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3662 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3663 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3664 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3666 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3667 // of the register here. This has a smaller encoding and avoids a
3668 // partial-register update. Actual movzbw included for the disassembler.
3669 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3670 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3671 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3672 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3673 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3674 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3675 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3676 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3677 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3678 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3679 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3680 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3681 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3682 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3683 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3684 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3685 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3686 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3687 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3688 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3690 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3691 // except that they use GR32_NOREX for the output operand register class
3692 // instead of GR32. This allows them to operate on h registers on x86-64.
3693 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3694 (outs GR32_NOREX:$dst), (ins GR8:$src),
3695 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3698 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3699 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3700 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3703 let neverHasSideEffects = 1 in {
3704 let Defs = [AX], Uses = [AL] in
3705 def CBW : I<0x98, RawFrm, (outs), (ins),
3706 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3707 let Defs = [EAX], Uses = [AX] in
3708 def CWDE : I<0x98, RawFrm, (outs), (ins),
3709 "{cwtl|cwde}", []>; // EAX = signext(AX)
3711 let Defs = [AX,DX], Uses = [AX] in
3712 def CWD : I<0x99, RawFrm, (outs), (ins),
3713 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3714 let Defs = [EAX,EDX], Uses = [EAX] in
3715 def CDQ : I<0x99, RawFrm, (outs), (ins),
3716 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3719 //===----------------------------------------------------------------------===//
3720 // Alias Instructions
3721 //===----------------------------------------------------------------------===//
3723 // Alias instructions that map movr0 to xor.
3724 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3725 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3726 isCodeGenOnly = 1 in {
3727 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3728 "xor{b}\t$dst, $dst",
3729 [(set GR8:$dst, 0)]>;
3731 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3732 // encoding and avoids a partial-register update sometimes, but doing so
3733 // at isel time interferes with rematerialization in the current register
3734 // allocator. For now, this is rewritten when the instruction is lowered
3736 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3738 [(set GR16:$dst, 0)]>, OpSize;
3740 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3741 "xor{l}\t$dst, $dst",
3742 [(set GR32:$dst, 0)]>;
3745 //===----------------------------------------------------------------------===//
3746 // Thread Local Storage Instructions
3749 // All calls clobber the non-callee saved registers. ESP is marked as
3750 // a use to prevent stack-pointer assignments that appear immediately
3751 // before calls from potentially appearing dead.
3752 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3753 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3754 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3755 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3757 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3758 "leal\t$sym, %eax; "
3759 "call\t___tls_get_addr@PLT",
3760 [(X86tlsaddr tls32addr:$sym)]>,
3761 Requires<[In32BitMode]>;
3763 let AddedComplexity = 5, isCodeGenOnly = 1 in
3764 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3765 "movl\t%gs:$src, $dst",
3766 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3768 let AddedComplexity = 5, isCodeGenOnly = 1 in
3769 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3770 "movl\t%fs:$src, $dst",
3771 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3773 //===----------------------------------------------------------------------===//
3774 // EH Pseudo Instructions
3776 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3777 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3778 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3779 "ret\t#eh_return, addr: $addr",
3780 [(X86ehret GR32:$addr)]>;
3784 //===----------------------------------------------------------------------===//
3788 // Atomic swap. These are just normal xchg instructions. But since a memory
3789 // operand is referenced, the atomicity is ensured.
3790 let Constraints = "$val = $dst" in {
3791 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3792 (ins GR32:$val, i32mem:$ptr),
3793 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3794 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3795 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3796 (ins GR16:$val, i16mem:$ptr),
3797 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3798 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3800 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3801 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3802 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3804 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3805 "xchg{l}\t{$val, $src|$src, $val}", []>;
3806 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3807 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3808 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3809 "xchg{b}\t{$val, $src|$src, $val}", []>;
3812 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3813 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3814 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3815 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3817 // Atomic compare and swap.
3818 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3819 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3821 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3822 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3824 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3825 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3828 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3831 let Defs = [AX, EFLAGS], Uses = [AX] in {
3832 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3834 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3835 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3837 let Defs = [AL, EFLAGS], Uses = [AL] in {
3838 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3840 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3841 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3844 // Atomic exchange and add
3845 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3846 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3848 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3849 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3851 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3853 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3854 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3856 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3858 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3859 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3863 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3864 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3865 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3866 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3867 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3868 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3870 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3871 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3872 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3873 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3874 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3875 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3877 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3878 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3879 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3880 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3881 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3882 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3884 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3885 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3886 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3887 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3888 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3889 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3891 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3892 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3893 "cmpxchg8b\t$dst", []>, TB;
3895 // Optimized codegen when the non-memory output is not used.
3896 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3897 let Defs = [EFLAGS] in {
3898 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3900 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3901 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3903 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3904 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3906 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3907 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3909 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3910 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3912 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3913 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3915 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3916 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3918 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3919 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3921 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3923 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3925 "inc{b}\t$dst", []>, LOCK;
3926 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3928 "inc{w}\t$dst", []>, OpSize, LOCK;
3929 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3931 "inc{l}\t$dst", []>, LOCK;
3933 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3935 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3936 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3938 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3939 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3941 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3942 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3944 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3945 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3947 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3948 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3950 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3951 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3953 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3954 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3956 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3958 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3960 "dec{b}\t$dst", []>, LOCK;
3961 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3963 "dec{w}\t$dst", []>, OpSize, LOCK;
3964 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3966 "dec{l}\t$dst", []>, LOCK;
3969 // Atomic exchange, and, or, xor
3970 let Constraints = "$val = $dst", Defs = [EFLAGS],
3971 usesCustomInserter = 1 in {
3972 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3973 "#ATOMAND32 PSEUDO!",
3974 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3975 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3976 "#ATOMOR32 PSEUDO!",
3977 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3978 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3979 "#ATOMXOR32 PSEUDO!",
3980 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3981 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3982 "#ATOMNAND32 PSEUDO!",
3983 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3984 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3985 "#ATOMMIN32 PSEUDO!",
3986 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3987 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3988 "#ATOMMAX32 PSEUDO!",
3989 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3990 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3991 "#ATOMUMIN32 PSEUDO!",
3992 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3993 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3994 "#ATOMUMAX32 PSEUDO!",
3995 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3997 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3998 "#ATOMAND16 PSEUDO!",
3999 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4000 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4001 "#ATOMOR16 PSEUDO!",
4002 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4003 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4004 "#ATOMXOR16 PSEUDO!",
4005 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4006 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4007 "#ATOMNAND16 PSEUDO!",
4008 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4009 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4010 "#ATOMMIN16 PSEUDO!",
4011 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4012 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4013 "#ATOMMAX16 PSEUDO!",
4014 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4015 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4016 "#ATOMUMIN16 PSEUDO!",
4017 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4018 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4019 "#ATOMUMAX16 PSEUDO!",
4020 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4022 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4023 "#ATOMAND8 PSEUDO!",
4024 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4025 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4027 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4028 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4029 "#ATOMXOR8 PSEUDO!",
4030 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4031 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4032 "#ATOMNAND8 PSEUDO!",
4033 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4036 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4037 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4038 Uses = [EAX, EBX, ECX, EDX],
4039 mayLoad = 1, mayStore = 1,
4040 usesCustomInserter = 1 in {
4041 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4042 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4043 "#ATOMAND6432 PSEUDO!", []>;
4044 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4045 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4046 "#ATOMOR6432 PSEUDO!", []>;
4047 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4048 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4049 "#ATOMXOR6432 PSEUDO!", []>;
4050 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4051 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4052 "#ATOMNAND6432 PSEUDO!", []>;
4053 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4054 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4055 "#ATOMADD6432 PSEUDO!", []>;
4056 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4057 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4058 "#ATOMSUB6432 PSEUDO!", []>;
4059 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4060 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4061 "#ATOMSWAP6432 PSEUDO!", []>;
4064 // Segmentation support instructions.
4066 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4067 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4068 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4069 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4071 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4072 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4073 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4074 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4075 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4077 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4078 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4079 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4080 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4081 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4082 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4083 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4084 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4086 def INVLPG : I<0x01, RawFrm, (outs), (ins), "invlpg", []>, TB;
4088 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4089 "str{w}\t{$dst}", []>, TB;
4090 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4091 "str{w}\t{$dst}", []>, TB;
4092 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4093 "ltr{w}\t{$src}", []>, TB;
4094 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4095 "ltr{w}\t{$src}", []>, TB;
4097 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4098 "push{w}\t%fs", []>, OpSize, TB;
4099 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4100 "push{l}\t%fs", []>, TB;
4101 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4102 "push{w}\t%gs", []>, OpSize, TB;
4103 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4104 "push{l}\t%gs", []>, TB;
4106 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4107 "pop{w}\t%fs", []>, OpSize, TB;
4108 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4109 "pop{l}\t%fs", []>, TB;
4110 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4111 "pop{w}\t%gs", []>, OpSize, TB;
4112 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4113 "pop{l}\t%gs", []>, TB;
4115 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4116 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4117 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4118 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4119 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4120 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4121 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4122 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4123 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4124 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4125 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4126 "les{l}\t{$src, $dst|$dst, $src}", []>;
4127 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4128 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4129 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4130 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4131 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4132 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4133 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4134 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4136 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4137 "verr\t$seg", []>, TB;
4138 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4139 "verr\t$seg", []>, TB;
4140 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4141 "verw\t$seg", []>, TB;
4142 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4143 "verw\t$seg", []>, TB;
4145 // Descriptor-table support instructions
4147 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4148 "sgdt\t$dst", []>, TB;
4149 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4150 "sidt\t$dst", []>, TB;
4151 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4152 "sldt{w}\t$dst", []>, TB;
4153 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4154 "sldt{w}\t$dst", []>, TB;
4155 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4156 "lgdt\t$src", []>, TB;
4157 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4158 "lidt\t$src", []>, TB;
4159 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4160 "lldt{w}\t$src", []>, TB;
4161 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4162 "lldt{w}\t$src", []>, TB;
4164 // String manipulation instructions
4166 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4167 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4168 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4170 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4171 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4172 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4174 // CPU flow control instructions
4176 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4177 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4179 // FPU control instructions
4181 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4183 // Flag instructions
4185 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4186 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4187 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4188 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4189 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4190 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4191 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4193 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4195 // Table lookup instructions
4197 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4199 // Specialized register support
4201 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4202 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4203 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4205 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4206 "smsw{w}\t$dst", []>, OpSize, TB;
4207 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4208 "smsw{l}\t$dst", []>, TB;
4209 // For memory operands, there is only a 16-bit form
4210 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4211 "smsw{w}\t$dst", []>, TB;
4213 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4214 "lmsw{w}\t$src", []>, TB;
4215 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4216 "lmsw{w}\t$src", []>, TB;
4218 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4220 // Cache instructions
4222 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4223 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4228 def INVEPT : I<0x38, RawFrm, (outs), (ins), "invept", []>, OpSize, TB;
4230 def INVVPID : I<0x38, RawFrm, (outs), (ins), "invvpid", []>, OpSize, TB;
4232 def VMCALL : I<0x01, RawFrm, (outs), (ins), "vmcall", []>, TB;
4233 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4234 "vmclear\t$vmcs", []>, OpSize, TB;
4236 def VMLAUNCH : I<0x01, RawFrm, (outs), (ins), "vmlaunch", []>, TB;
4238 def VMRESUME : I<0x01, RawFrm, (outs), (ins), "vmresume", []>, TB;
4239 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4240 "vmptrld\t$vmcs", []>, TB;
4241 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4242 "vmptrst\t$vmcs", []>, TB;
4243 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4244 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4245 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4246 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4247 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4248 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4249 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4250 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4251 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4252 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4253 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4254 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4255 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4256 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4257 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4258 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4260 def VMXOFF : I<0x01, RawFrm, (outs), (ins), "vmxoff", []>, OpSize;
4261 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4262 "vmxon\t{$vmxon}", []>, XD;
4264 //===----------------------------------------------------------------------===//
4265 // Non-Instruction Patterns
4266 //===----------------------------------------------------------------------===//
4268 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4269 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4270 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4271 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4272 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4273 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4274 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4276 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4277 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4278 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4279 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4280 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4281 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4282 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4283 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4284 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4285 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4287 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4288 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4289 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4290 (MOV32mi addr:$dst, texternalsym:$src)>;
4291 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4292 (MOV32mi addr:$dst, tblockaddress:$src)>;
4296 def : Pat<(X86tcret GR32:$dst, imm:$off),
4297 (TCRETURNri GR32:$dst, imm:$off)>;
4299 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4300 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4302 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4303 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4305 // Normal calls, with various flavors of addresses.
4306 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4307 (CALLpcrel32 tglobaladdr:$dst)>;
4308 def : Pat<(X86call (i32 texternalsym:$dst)),
4309 (CALLpcrel32 texternalsym:$dst)>;
4310 def : Pat<(X86call (i32 imm:$dst)),
4311 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4313 // X86 specific add which produces a flag.
4314 def : Pat<(addc GR32:$src1, GR32:$src2),
4315 (ADD32rr GR32:$src1, GR32:$src2)>;
4316 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4317 (ADD32rm GR32:$src1, addr:$src2)>;
4318 def : Pat<(addc GR32:$src1, imm:$src2),
4319 (ADD32ri GR32:$src1, imm:$src2)>;
4320 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4321 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4323 def : Pat<(subc GR32:$src1, GR32:$src2),
4324 (SUB32rr GR32:$src1, GR32:$src2)>;
4325 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4326 (SUB32rm GR32:$src1, addr:$src2)>;
4327 def : Pat<(subc GR32:$src1, imm:$src2),
4328 (SUB32ri GR32:$src1, imm:$src2)>;
4329 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4330 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4334 // TEST R,R is smaller than CMP R,0
4335 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
4336 (TEST8rr GR8:$src1, GR8:$src1)>;
4337 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
4338 (TEST16rr GR16:$src1, GR16:$src1)>;
4339 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
4340 (TEST32rr GR32:$src1, GR32:$src1)>;
4342 // Conditional moves with folded loads with operands swapped and conditions
4344 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4345 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4346 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4347 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4348 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4349 (CMOVB16rm GR16:$src2, addr:$src1)>;
4350 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4351 (CMOVB32rm GR32:$src2, addr:$src1)>;
4352 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4353 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4354 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4355 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4356 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4357 (CMOVE16rm GR16:$src2, addr:$src1)>;
4358 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4359 (CMOVE32rm GR32:$src2, addr:$src1)>;
4360 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4361 (CMOVA16rm GR16:$src2, addr:$src1)>;
4362 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4363 (CMOVA32rm GR32:$src2, addr:$src1)>;
4364 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4365 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4366 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4367 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4368 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4369 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4370 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4371 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4372 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4373 (CMOVL16rm GR16:$src2, addr:$src1)>;
4374 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4375 (CMOVL32rm GR32:$src2, addr:$src1)>;
4376 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4377 (CMOVG16rm GR16:$src2, addr:$src1)>;
4378 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4379 (CMOVG32rm GR32:$src2, addr:$src1)>;
4380 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4381 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4382 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4383 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4384 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4385 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4386 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4387 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4388 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4389 (CMOVP16rm GR16:$src2, addr:$src1)>;
4390 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4391 (CMOVP32rm GR32:$src2, addr:$src1)>;
4392 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4393 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4394 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4395 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4396 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4397 (CMOVS16rm GR16:$src2, addr:$src1)>;
4398 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4399 (CMOVS32rm GR32:$src2, addr:$src1)>;
4400 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4401 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4402 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4403 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4404 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4405 (CMOVO16rm GR16:$src2, addr:$src1)>;
4406 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4407 (CMOVO32rm GR32:$src2, addr:$src1)>;
4409 // zextload bool -> zextload byte
4410 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4411 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4412 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4414 // extload bool -> extload byte
4415 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4416 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4417 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4418 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4419 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4420 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4422 // anyext. Define these to do an explicit zero-extend to
4423 // avoid partial-register updates.
4424 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4425 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4426 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
4428 // (and (i32 load), 255) -> (zextload i8)
4429 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
4430 (MOVZX32rm8 addr:$src)>;
4431 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
4432 (MOVZX32rm16 addr:$src)>;
4434 //===----------------------------------------------------------------------===//
4436 //===----------------------------------------------------------------------===//
4438 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4439 // +128 doesn't, so in this special case use a sub instead of an add.
4440 def : Pat<(add GR16:$src1, 128),
4441 (SUB16ri8 GR16:$src1, -128)>;
4442 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4443 (SUB16mi8 addr:$dst, -128)>;
4444 def : Pat<(add GR32:$src1, 128),
4445 (SUB32ri8 GR32:$src1, -128)>;
4446 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4447 (SUB32mi8 addr:$dst, -128)>;
4449 // r & (2^16-1) ==> movz
4450 def : Pat<(and GR32:$src1, 0xffff),
4451 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4452 // r & (2^8-1) ==> movz
4453 def : Pat<(and GR32:$src1, 0xff),
4454 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4457 Requires<[In32BitMode]>;
4458 // r & (2^8-1) ==> movz
4459 def : Pat<(and GR16:$src1, 0xff),
4460 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4463 Requires<[In32BitMode]>;
4465 // sext_inreg patterns
4466 def : Pat<(sext_inreg GR32:$src, i16),
4467 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4468 def : Pat<(sext_inreg GR32:$src, i8),
4469 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4472 Requires<[In32BitMode]>;
4473 def : Pat<(sext_inreg GR16:$src, i8),
4474 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4477 Requires<[In32BitMode]>;
4480 def : Pat<(i16 (trunc GR32:$src)),
4481 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4482 def : Pat<(i8 (trunc GR32:$src)),
4483 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4485 Requires<[In32BitMode]>;
4486 def : Pat<(i8 (trunc GR16:$src)),
4487 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4489 Requires<[In32BitMode]>;
4491 // h-register tricks
4492 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4493 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4494 x86_subreg_8bit_hi)>,
4495 Requires<[In32BitMode]>;
4496 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4497 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4498 x86_subreg_8bit_hi)>,
4499 Requires<[In32BitMode]>;
4500 def : Pat<(srl GR16:$src, (i8 8)),
4503 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4504 x86_subreg_8bit_hi)),
4506 Requires<[In32BitMode]>;
4507 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4508 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4510 x86_subreg_8bit_hi))>,
4511 Requires<[In32BitMode]>;
4512 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4513 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4515 x86_subreg_8bit_hi))>,
4516 Requires<[In32BitMode]>;
4517 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4518 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4520 x86_subreg_8bit_hi))>,
4521 Requires<[In32BitMode]>;
4523 // (shl x, 1) ==> (add x, x)
4524 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4525 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4526 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4528 // (shl x (and y, 31)) ==> (shl x, y)
4529 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
4530 (SHL8rCL GR8:$src1)>;
4531 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
4532 (SHL16rCL GR16:$src1)>;
4533 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
4534 (SHL32rCL GR32:$src1)>;
4535 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4536 (SHL8mCL addr:$dst)>;
4537 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4538 (SHL16mCL addr:$dst)>;
4539 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4540 (SHL32mCL addr:$dst)>;
4542 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
4543 (SHR8rCL GR8:$src1)>;
4544 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
4545 (SHR16rCL GR16:$src1)>;
4546 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
4547 (SHR32rCL GR32:$src1)>;
4548 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4549 (SHR8mCL addr:$dst)>;
4550 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4551 (SHR16mCL addr:$dst)>;
4552 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4553 (SHR32mCL addr:$dst)>;
4555 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
4556 (SAR8rCL GR8:$src1)>;
4557 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
4558 (SAR16rCL GR16:$src1)>;
4559 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
4560 (SAR32rCL GR32:$src1)>;
4561 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4562 (SAR8mCL addr:$dst)>;
4563 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4564 (SAR16mCL addr:$dst)>;
4565 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4566 (SAR32mCL addr:$dst)>;
4568 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
4569 def : Pat<(or (srl GR32:$src1, CL:$amt),
4570 (shl GR32:$src2, (sub 32, CL:$amt))),
4571 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4573 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
4574 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4575 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4577 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
4578 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4579 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4581 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4582 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4584 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4586 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
4587 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4589 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
4590 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
4591 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4593 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
4594 def : Pat<(or (shl GR32:$src1, CL:$amt),
4595 (srl GR32:$src2, (sub 32, CL:$amt))),
4596 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4598 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
4599 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4600 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4602 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
4603 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4604 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4606 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4607 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4609 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4611 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
4612 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4614 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
4615 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
4616 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4618 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
4619 def : Pat<(or (srl GR16:$src1, CL:$amt),
4620 (shl GR16:$src2, (sub 16, CL:$amt))),
4621 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4623 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
4624 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4625 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4627 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
4628 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4629 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4631 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4632 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4634 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4636 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
4637 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4639 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
4640 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
4641 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4643 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
4644 def : Pat<(or (shl GR16:$src1, CL:$amt),
4645 (srl GR16:$src2, (sub 16, CL:$amt))),
4646 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4648 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
4649 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4650 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4652 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
4653 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4654 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4656 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4657 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4659 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4661 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
4662 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4664 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
4665 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
4666 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4668 // (anyext (setcc_carry)) -> (setcc_carry)
4669 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4671 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4674 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4675 let AddedComplexity = 5 in { // Try this before the selecting to OR
4676 def : Pat<(parallel (or_is_add GR16:$src1, imm:$src2),
4678 (ADD16ri GR16:$src1, imm:$src2)>;
4679 def : Pat<(parallel (or_is_add GR32:$src1, imm:$src2),
4681 (ADD32ri GR32:$src1, imm:$src2)>;
4682 def : Pat<(parallel (or_is_add GR16:$src1, i16immSExt8:$src2),
4684 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4685 def : Pat<(parallel (or_is_add GR32:$src1, i32immSExt8:$src2),
4687 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4688 def : Pat<(parallel (or_is_add GR16:$src1, GR16:$src2),
4690 (ADD16rr GR16:$src1, GR16:$src2)>;
4691 def : Pat<(parallel (or_is_add GR32:$src1, GR32:$src2),
4693 (ADD32rr GR32:$src1, GR32:$src2)>;
4694 } // AddedComplexity
4696 //===----------------------------------------------------------------------===//
4697 // EFLAGS-defining Patterns
4698 //===----------------------------------------------------------------------===//
4700 // Register-Register Addition with EFLAGS result
4701 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
4703 (ADD8rr GR8:$src1, GR8:$src2)>;
4704 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
4706 (ADD16rr GR16:$src1, GR16:$src2)>;
4707 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
4709 (ADD32rr GR32:$src1, GR32:$src2)>;
4711 // Register-Memory Addition with EFLAGS result
4712 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
4714 (ADD8rm GR8:$src1, addr:$src2)>;
4715 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
4717 (ADD16rm GR16:$src1, addr:$src2)>;
4718 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
4720 (ADD32rm GR32:$src1, addr:$src2)>;
4722 // Register-Integer Addition with EFLAGS result
4723 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
4725 (ADD8ri GR8:$src1, imm:$src2)>;
4726 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
4728 (ADD16ri GR16:$src1, imm:$src2)>;
4729 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
4731 (ADD32ri GR32:$src1, imm:$src2)>;
4732 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
4734 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4735 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
4737 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4739 // Memory-Register Addition with EFLAGS result
4740 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
4743 (ADD8mr addr:$dst, GR8:$src2)>;
4744 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
4747 (ADD16mr addr:$dst, GR16:$src2)>;
4748 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
4751 (ADD32mr addr:$dst, GR32:$src2)>;
4753 // Memory-Integer Addition with EFLAGS result
4754 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
4757 (ADD8mi addr:$dst, imm:$src2)>;
4758 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
4761 (ADD16mi addr:$dst, imm:$src2)>;
4762 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
4765 (ADD32mi addr:$dst, imm:$src2)>;
4766 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4769 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
4770 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4773 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
4775 // Register-Register Subtraction with EFLAGS result
4776 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
4778 (SUB8rr GR8:$src1, GR8:$src2)>;
4779 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
4781 (SUB16rr GR16:$src1, GR16:$src2)>;
4782 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
4784 (SUB32rr GR32:$src1, GR32:$src2)>;
4786 // Register-Memory Subtraction with EFLAGS result
4787 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
4789 (SUB8rm GR8:$src1, addr:$src2)>;
4790 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
4792 (SUB16rm GR16:$src1, addr:$src2)>;
4793 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
4795 (SUB32rm GR32:$src1, addr:$src2)>;
4797 // Register-Integer Subtraction with EFLAGS result
4798 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
4800 (SUB8ri GR8:$src1, imm:$src2)>;
4801 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
4803 (SUB16ri GR16:$src1, imm:$src2)>;
4804 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
4806 (SUB32ri GR32:$src1, imm:$src2)>;
4807 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
4809 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4810 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
4812 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4814 // Memory-Register Subtraction with EFLAGS result
4815 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
4818 (SUB8mr addr:$dst, GR8:$src2)>;
4819 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
4822 (SUB16mr addr:$dst, GR16:$src2)>;
4823 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
4826 (SUB32mr addr:$dst, GR32:$src2)>;
4828 // Memory-Integer Subtraction with EFLAGS result
4829 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
4832 (SUB8mi addr:$dst, imm:$src2)>;
4833 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
4836 (SUB16mi addr:$dst, imm:$src2)>;
4837 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4840 (SUB32mi addr:$dst, imm:$src2)>;
4841 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4844 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4845 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4848 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4851 // Register-Register Signed Integer Multiply with EFLAGS result
4852 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4854 (IMUL16rr GR16:$src1, GR16:$src2)>;
4855 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4857 (IMUL32rr GR32:$src1, GR32:$src2)>;
4859 // Register-Memory Signed Integer Multiply with EFLAGS result
4860 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4862 (IMUL16rm GR16:$src1, addr:$src2)>;
4863 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4865 (IMUL32rm GR32:$src1, addr:$src2)>;
4867 // Register-Integer Signed Integer Multiply with EFLAGS result
4868 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4870 (IMUL16rri GR16:$src1, imm:$src2)>;
4871 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4873 (IMUL32rri GR32:$src1, imm:$src2)>;
4874 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4876 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4877 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4879 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4881 // Memory-Integer Signed Integer Multiply with EFLAGS result
4882 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4884 (IMUL16rmi addr:$src1, imm:$src2)>;
4885 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4887 (IMUL32rmi addr:$src1, imm:$src2)>;
4888 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4890 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4891 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4893 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4895 // Optimize multiply by 2 with EFLAGS result.
4896 let AddedComplexity = 2 in {
4897 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4899 (ADD16rr GR16:$src1, GR16:$src1)>;
4901 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4903 (ADD32rr GR32:$src1, GR32:$src1)>;
4906 // INC and DEC with EFLAGS result. Note that these do not set CF.
4907 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4909 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4912 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4914 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4918 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4919 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4920 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4922 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4923 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4924 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4925 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4927 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4929 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4930 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4931 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4933 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4934 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4935 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4936 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4938 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4940 // Register-Register Or with EFLAGS result
4941 def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
4943 (OR8rr GR8:$src1, GR8:$src2)>;
4944 def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2),
4946 (OR16rr GR16:$src1, GR16:$src2)>;
4947 def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2),
4949 (OR32rr GR32:$src1, GR32:$src2)>;
4951 // Register-Memory Or with EFLAGS result
4952 def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)),
4954 (OR8rm GR8:$src1, addr:$src2)>;
4955 def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)),
4957 (OR16rm GR16:$src1, addr:$src2)>;
4958 def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)),
4960 (OR32rm GR32:$src1, addr:$src2)>;
4962 // Register-Integer Or with EFLAGS result
4963 def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2),
4965 (OR8ri GR8:$src1, imm:$src2)>;
4966 def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2),
4968 (OR16ri GR16:$src1, imm:$src2)>;
4969 def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2),
4971 (OR32ri GR32:$src1, imm:$src2)>;
4972 def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
4974 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4975 def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
4977 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4979 // Memory-Register Or with EFLAGS result
4980 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
4983 (OR8mr addr:$dst, GR8:$src2)>;
4984 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2),
4987 (OR16mr addr:$dst, GR16:$src2)>;
4988 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2),
4991 (OR32mr addr:$dst, GR32:$src2)>;
4993 // Memory-Integer Or with EFLAGS result
4994 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2),
4997 (OR8mi addr:$dst, imm:$src2)>;
4998 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2),
5001 (OR16mi addr:$dst, imm:$src2)>;
5002 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2),
5005 (OR32mi addr:$dst, imm:$src2)>;
5006 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5009 (OR16mi8 addr:$dst, i16immSExt8:$src2)>;
5010 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5013 (OR32mi8 addr:$dst, i32immSExt8:$src2)>;
5015 // Register-Register XOr with EFLAGS result
5016 def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
5018 (XOR8rr GR8:$src1, GR8:$src2)>;
5019 def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2),
5021 (XOR16rr GR16:$src1, GR16:$src2)>;
5022 def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2),
5024 (XOR32rr GR32:$src1, GR32:$src2)>;
5026 // Register-Memory XOr with EFLAGS result
5027 def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)),
5029 (XOR8rm GR8:$src1, addr:$src2)>;
5030 def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)),
5032 (XOR16rm GR16:$src1, addr:$src2)>;
5033 def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)),
5035 (XOR32rm GR32:$src1, addr:$src2)>;
5037 // Register-Integer XOr with EFLAGS result
5038 def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2),
5040 (XOR8ri GR8:$src1, imm:$src2)>;
5041 def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2),
5043 (XOR16ri GR16:$src1, imm:$src2)>;
5044 def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2),
5046 (XOR32ri GR32:$src1, imm:$src2)>;
5047 def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2),
5049 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
5050 def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
5052 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
5054 // Memory-Register XOr with EFLAGS result
5055 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
5058 (XOR8mr addr:$dst, GR8:$src2)>;
5059 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2),
5062 (XOR16mr addr:$dst, GR16:$src2)>;
5063 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2),
5066 (XOR32mr addr:$dst, GR32:$src2)>;
5068 // Memory-Integer XOr with EFLAGS result
5069 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2),
5072 (XOR8mi addr:$dst, imm:$src2)>;
5073 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2),
5076 (XOR16mi addr:$dst, imm:$src2)>;
5077 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2),
5080 (XOR32mi addr:$dst, imm:$src2)>;
5081 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5084 (XOR16mi8 addr:$dst, i16immSExt8:$src2)>;
5085 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5088 (XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
5090 // Register-Register And with EFLAGS result
5091 def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
5093 (AND8rr GR8:$src1, GR8:$src2)>;
5094 def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2),
5096 (AND16rr GR16:$src1, GR16:$src2)>;
5097 def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2),
5099 (AND32rr GR32:$src1, GR32:$src2)>;
5101 // Register-Memory And with EFLAGS result
5102 def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)),
5104 (AND8rm GR8:$src1, addr:$src2)>;
5105 def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)),
5107 (AND16rm GR16:$src1, addr:$src2)>;
5108 def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)),
5110 (AND32rm GR32:$src1, addr:$src2)>;
5112 // Register-Integer And with EFLAGS result
5113 def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2),
5115 (AND8ri GR8:$src1, imm:$src2)>;
5116 def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2),
5118 (AND16ri GR16:$src1, imm:$src2)>;
5119 def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2),
5121 (AND32ri GR32:$src1, imm:$src2)>;
5122 def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2),
5124 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
5125 def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
5127 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
5129 // Memory-Register And with EFLAGS result
5130 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
5133 (AND8mr addr:$dst, GR8:$src2)>;
5134 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2),
5137 (AND16mr addr:$dst, GR16:$src2)>;
5138 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2),
5141 (AND32mr addr:$dst, GR32:$src2)>;
5143 // Memory-Integer And with EFLAGS result
5144 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2),
5147 (AND8mi addr:$dst, imm:$src2)>;
5148 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2),
5151 (AND16mi addr:$dst, imm:$src2)>;
5152 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2),
5155 (AND32mi addr:$dst, imm:$src2)>;
5156 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5159 (AND16mi8 addr:$dst, i16immSExt8:$src2)>;
5160 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5163 (AND32mi8 addr:$dst, i32immSExt8:$src2)>;
5165 // -disable-16bit support.
5166 def : Pat<(truncstorei16 (i32 imm:$src), addr:$dst),
5167 (MOV16mi addr:$dst, imm:$src)>;
5168 def : Pat<(truncstorei16 GR32:$src, addr:$dst),
5169 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
5170 def : Pat<(i32 (sextloadi16 addr:$dst)),
5171 (MOVSX32rm16 addr:$dst)>;
5172 def : Pat<(i32 (zextloadi16 addr:$dst)),
5173 (MOVZX32rm16 addr:$dst)>;
5174 def : Pat<(i32 (extloadi16 addr:$dst)),
5175 (MOVZX32rm16 addr:$dst)>;
5177 //===----------------------------------------------------------------------===//
5178 // Floating Point Stack Support
5179 //===----------------------------------------------------------------------===//
5181 include "X86InstrFPStack.td"
5183 //===----------------------------------------------------------------------===//
5185 //===----------------------------------------------------------------------===//
5187 include "X86Instr64bit.td"
5189 //===----------------------------------------------------------------------===//
5190 // XMM Floating point support (requires SSE / SSE2)
5191 //===----------------------------------------------------------------------===//
5193 include "X86InstrSSE.td"
5195 //===----------------------------------------------------------------------===//
5196 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
5197 //===----------------------------------------------------------------------===//
5199 include "X86InstrMMX.td"