1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
117 [SDNPHasChain,SDNPSideEffect]>;
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
146 [SDNPHasChain, SDNPSideEffect]>;
148 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
155 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
158 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
159 [SDNPHasChain, SDNPMayStore,
160 SDNPMayLoad, SDNPMemOperand]>;
161 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
162 [SDNPHasChain, SDNPMayStore,
163 SDNPMayLoad, SDNPMemOperand]>;
164 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
165 [SDNPHasChain, SDNPMayStore,
166 SDNPMayLoad, SDNPMemOperand]>;
167 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
177 [SDNPHasChain, SDNPMayStore,
178 SDNPMayLoad, SDNPMemOperand]>;
179 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
182 def X86vastart_save_xmm_regs :
183 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
184 SDT_X86VASTART_SAVE_XMM_REGS,
185 [SDNPHasChain, SDNPVariadic]>;
187 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
190 def X86callseq_start :
191 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
192 [SDNPHasChain, SDNPOutGlue]>;
194 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
197 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
198 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
201 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
202 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
203 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
204 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
207 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
208 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
210 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
211 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
213 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
214 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
216 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
217 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
219 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
222 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
223 SDTypeProfile<1, 1, [SDTCisInt<0>,
225 [SDNPHasChain, SDNPSideEffect]>;
226 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
227 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
228 [SDNPHasChain, SDNPSideEffect]>;
230 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
231 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
233 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
235 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
236 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
238 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
240 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
241 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
243 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
244 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
245 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
247 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
249 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
252 def X86blsi : SDNode<"X86ISD::BLSI", SDTIntUnaryOp>;
253 def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>;
254 def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>;
255 def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntShiftOp>;
256 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
258 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
260 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
261 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
263 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
266 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
267 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
269 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
270 [SDNPHasChain, SDNPOutGlue]>;
272 //===----------------------------------------------------------------------===//
273 // X86 Operand Definitions.
276 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
277 // the index operand of an address, to conform to x86 encoding restrictions.
278 def ptr_rc_nosp : PointerLikeRegClass<1>;
280 // *mem - Operand definitions for the funky X86 addressing mode operands.
282 def X86MemAsmOperand : AsmOperandClass {
285 def X86Mem8AsmOperand : AsmOperandClass {
286 let Name = "Mem8"; let RenderMethod = "addMemOperands";
288 def X86Mem16AsmOperand : AsmOperandClass {
289 let Name = "Mem16"; let RenderMethod = "addMemOperands";
291 def X86Mem32AsmOperand : AsmOperandClass {
292 let Name = "Mem32"; let RenderMethod = "addMemOperands";
294 def X86Mem64AsmOperand : AsmOperandClass {
295 let Name = "Mem64"; let RenderMethod = "addMemOperands";
297 def X86Mem80AsmOperand : AsmOperandClass {
298 let Name = "Mem80"; let RenderMethod = "addMemOperands";
300 def X86Mem128AsmOperand : AsmOperandClass {
301 let Name = "Mem128"; let RenderMethod = "addMemOperands";
303 def X86Mem256AsmOperand : AsmOperandClass {
304 let Name = "Mem256"; let RenderMethod = "addMemOperands";
306 def X86Mem512AsmOperand : AsmOperandClass {
307 let Name = "Mem512"; let RenderMethod = "addMemOperands";
310 // Gather mem operands
311 def X86MemVX32Operand : AsmOperandClass {
312 let Name = "MemVX32"; let RenderMethod = "addMemOperands";
314 def X86MemVY32Operand : AsmOperandClass {
315 let Name = "MemVY32"; let RenderMethod = "addMemOperands";
317 def X86MemVZ32Operand : AsmOperandClass {
318 let Name = "MemVZ32"; let RenderMethod = "addMemOperands";
320 def X86MemVX64Operand : AsmOperandClass {
321 let Name = "MemVX64"; let RenderMethod = "addMemOperands";
323 def X86MemVY64Operand : AsmOperandClass {
324 let Name = "MemVY64"; let RenderMethod = "addMemOperands";
326 def X86MemVZ64Operand : AsmOperandClass {
327 let Name = "MemVZ64"; let RenderMethod = "addMemOperands";
330 def X86AbsMemAsmOperand : AsmOperandClass {
332 let SuperClasses = [X86MemAsmOperand];
334 class X86MemOperand<string printMethod> : Operand<iPTR> {
335 let PrintMethod = printMethod;
336 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
337 let ParserMatchClass = X86MemAsmOperand;
340 let OperandType = "OPERAND_MEMORY" in {
341 def opaque32mem : X86MemOperand<"printopaquemem">;
342 def opaque48mem : X86MemOperand<"printopaquemem">;
343 def opaque80mem : X86MemOperand<"printopaquemem">;
344 def opaque512mem : X86MemOperand<"printopaquemem">;
346 def i8mem : X86MemOperand<"printi8mem"> {
347 let ParserMatchClass = X86Mem8AsmOperand; }
348 def i16mem : X86MemOperand<"printi16mem"> {
349 let ParserMatchClass = X86Mem16AsmOperand; }
350 def i32mem : X86MemOperand<"printi32mem"> {
351 let ParserMatchClass = X86Mem32AsmOperand; }
352 def i64mem : X86MemOperand<"printi64mem"> {
353 let ParserMatchClass = X86Mem64AsmOperand; }
354 def i128mem : X86MemOperand<"printi128mem"> {
355 let ParserMatchClass = X86Mem128AsmOperand; }
356 def i256mem : X86MemOperand<"printi256mem"> {
357 let ParserMatchClass = X86Mem256AsmOperand; }
358 def i512mem : X86MemOperand<"printi512mem"> {
359 let ParserMatchClass = X86Mem512AsmOperand; }
360 def f32mem : X86MemOperand<"printf32mem"> {
361 let ParserMatchClass = X86Mem32AsmOperand; }
362 def f64mem : X86MemOperand<"printf64mem"> {
363 let ParserMatchClass = X86Mem64AsmOperand; }
364 def f80mem : X86MemOperand<"printf80mem"> {
365 let ParserMatchClass = X86Mem80AsmOperand; }
366 def f128mem : X86MemOperand<"printf128mem"> {
367 let ParserMatchClass = X86Mem128AsmOperand; }
368 def f256mem : X86MemOperand<"printf256mem">{
369 let ParserMatchClass = X86Mem256AsmOperand; }
370 def f512mem : X86MemOperand<"printf512mem">{
371 let ParserMatchClass = X86Mem512AsmOperand; }
372 def v512mem : Operand<iPTR> {
373 let PrintMethod = "printf512mem";
374 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
375 let ParserMatchClass = X86Mem512AsmOperand; }
377 // Gather mem operands
378 def vx32mem : X86MemOperand<"printi32mem">{
379 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
380 let ParserMatchClass = X86MemVX32Operand; }
381 def vy32mem : X86MemOperand<"printi32mem">{
382 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
383 let ParserMatchClass = X86MemVY32Operand; }
384 def vx64mem : X86MemOperand<"printi64mem">{
385 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
386 let ParserMatchClass = X86MemVX64Operand; }
387 def vy64mem : X86MemOperand<"printi64mem">{
388 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
389 let ParserMatchClass = X86MemVY64Operand; }
390 def vy64xmem : X86MemOperand<"printi64mem">{
391 let MIOperandInfo = (ops ptr_rc, i8imm, VR256X, i32imm, i8imm);
392 let ParserMatchClass = X86MemVY64Operand; }
393 def vz32mem : X86MemOperand<"printi32mem">{
394 let MIOperandInfo = (ops ptr_rc, i16imm, VR512, i32imm, i8imm);
395 let ParserMatchClass = X86MemVZ32Operand; }
396 def vz64mem : X86MemOperand<"printi64mem">{
397 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
398 let ParserMatchClass = X86MemVZ64Operand; }
401 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
402 // plain GR64, so that it doesn't potentially require a REX prefix.
403 def i8mem_NOREX : Operand<i64> {
404 let PrintMethod = "printi8mem";
405 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
406 let ParserMatchClass = X86Mem8AsmOperand;
407 let OperandType = "OPERAND_MEMORY";
410 // GPRs available for tailcall.
411 // It represents GR32_TC, GR64_TC or GR64_TCW64.
412 def ptr_rc_tailcall : PointerLikeRegClass<2>;
414 // Special i32mem for addresses of load folding tail calls. These are not
415 // allowed to use callee-saved registers since they must be scheduled
416 // after callee-saved register are popped.
417 def i32mem_TC : Operand<i32> {
418 let PrintMethod = "printi32mem";
419 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
421 let ParserMatchClass = X86Mem32AsmOperand;
422 let OperandType = "OPERAND_MEMORY";
425 // Special i64mem for addresses of load folding tail calls. These are not
426 // allowed to use callee-saved registers since they must be scheduled
427 // after callee-saved register are popped.
428 def i64mem_TC : Operand<i64> {
429 let PrintMethod = "printi64mem";
430 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
431 ptr_rc_tailcall, i32imm, i8imm);
432 let ParserMatchClass = X86Mem64AsmOperand;
433 let OperandType = "OPERAND_MEMORY";
436 let OperandType = "OPERAND_PCREL",
437 ParserMatchClass = X86AbsMemAsmOperand,
438 PrintMethod = "printPCRelImm" in {
439 def i32imm_pcrel : Operand<i32>;
440 def i16imm_pcrel : Operand<i16>;
442 // Branch targets have OtherVT type and print as pc-relative values.
443 def brtarget : Operand<OtherVT>;
444 def brtarget8 : Operand<OtherVT>;
448 def X86SrcIdx8Operand : AsmOperandClass {
449 let Name = "SrcIdx8";
450 let RenderMethod = "addSrcIdxOperands";
451 let SuperClasses = [X86Mem8AsmOperand];
453 def X86SrcIdx16Operand : AsmOperandClass {
454 let Name = "SrcIdx16";
455 let RenderMethod = "addSrcIdxOperands";
456 let SuperClasses = [X86Mem16AsmOperand];
458 def X86SrcIdx32Operand : AsmOperandClass {
459 let Name = "SrcIdx32";
460 let RenderMethod = "addSrcIdxOperands";
461 let SuperClasses = [X86Mem32AsmOperand];
463 def X86SrcIdx64Operand : AsmOperandClass {
464 let Name = "SrcIdx64";
465 let RenderMethod = "addSrcIdxOperands";
466 let SuperClasses = [X86Mem64AsmOperand];
468 def X86MemOffs8AsmOperand : AsmOperandClass {
469 let Name = "MemOffs8";
470 let RenderMethod = "addMemOffsOperands";
471 let SuperClasses = [X86Mem8AsmOperand];
473 def X86MemOffs16AsmOperand : AsmOperandClass {
474 let Name = "MemOffs16";
475 let RenderMethod = "addMemOffsOperands";
476 let SuperClasses = [X86Mem16AsmOperand];
478 def X86MemOffs32AsmOperand : AsmOperandClass {
479 let Name = "MemOffs32";
480 let RenderMethod = "addMemOffsOperands";
481 let SuperClasses = [X86Mem32AsmOperand];
483 def X86MemOffs64AsmOperand : AsmOperandClass {
484 let Name = "MemOffs64";
485 let RenderMethod = "addMemOffsOperands";
486 let SuperClasses = [X86Mem64AsmOperand];
488 let OperandType = "OPERAND_MEMORY" in {
489 def srcidx8 : Operand<iPTR> {
490 let ParserMatchClass = X86SrcIdx8Operand;
491 let MIOperandInfo = (ops ptr_rc, i8imm);
492 let PrintMethod = "printSrcIdx8"; }
493 def srcidx16 : Operand<iPTR> {
494 let ParserMatchClass = X86SrcIdx16Operand;
495 let MIOperandInfo = (ops ptr_rc, i8imm);
496 let PrintMethod = "printSrcIdx16"; }
497 def srcidx32 : Operand<iPTR> {
498 let ParserMatchClass = X86SrcIdx32Operand;
499 let MIOperandInfo = (ops ptr_rc, i8imm);
500 let PrintMethod = "printSrcIdx32"; }
501 def srcidx64 : Operand<iPTR> {
502 let ParserMatchClass = X86SrcIdx64Operand;
503 let MIOperandInfo = (ops ptr_rc, i8imm);
504 let PrintMethod = "printSrcIdx64"; }
505 def offset8 : Operand<iPTR> {
506 let ParserMatchClass = X86MemOffs8AsmOperand;
507 let MIOperandInfo = (ops i64imm, i8imm);
508 let PrintMethod = "printMemOffs8"; }
509 def offset16 : Operand<iPTR> {
510 let ParserMatchClass = X86MemOffs16AsmOperand;
511 let MIOperandInfo = (ops i64imm, i8imm);
512 let PrintMethod = "printMemOffs16"; }
513 def offset32 : Operand<iPTR> {
514 let ParserMatchClass = X86MemOffs32AsmOperand;
515 let MIOperandInfo = (ops i64imm, i8imm);
516 let PrintMethod = "printMemOffs32"; }
517 def offset64 : Operand<iPTR> {
518 let ParserMatchClass = X86MemOffs64AsmOperand;
519 let MIOperandInfo = (ops i64imm, i8imm);
520 let PrintMethod = "printMemOffs64"; }
524 def SSECC : Operand<i8> {
525 let PrintMethod = "printSSECC";
526 let OperandType = "OPERAND_IMMEDIATE";
529 def AVXCC : Operand<i8> {
530 let PrintMethod = "printAVXCC";
531 let OperandType = "OPERAND_IMMEDIATE";
534 class ImmSExtAsmOperandClass : AsmOperandClass {
535 let SuperClasses = [ImmAsmOperand];
536 let RenderMethod = "addImmOperands";
539 class ImmZExtAsmOperandClass : AsmOperandClass {
540 let SuperClasses = [ImmAsmOperand];
541 let RenderMethod = "addImmOperands";
544 def X86GR32orGR64AsmOperand : AsmOperandClass {
545 let Name = "GR32orGR64";
548 def GR32orGR64 : RegisterOperand<GR32> {
549 let ParserMatchClass = X86GR32orGR64AsmOperand;
552 def AVX512RC : Operand<i32> {
553 let PrintMethod = "printRoundingControl";
554 let OperandType = "OPERAND_IMMEDIATE";
556 // Sign-extended immediate classes. We don't need to define the full lattice
557 // here because there is no instruction with an ambiguity between ImmSExti64i32
560 // The strange ranges come from the fact that the assembler always works with
561 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
562 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
565 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
566 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
567 let Name = "ImmSExti64i32";
570 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
571 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
572 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
573 let Name = "ImmSExti16i8";
574 let SuperClasses = [ImmSExti64i32AsmOperand];
577 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
578 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
579 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
580 let Name = "ImmSExti32i8";
584 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
585 let Name = "ImmZExtu32u8";
590 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
591 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
592 let Name = "ImmSExti64i8";
593 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
594 ImmSExti64i32AsmOperand];
597 // A couple of more descriptive operand definitions.
598 // 16-bits but only 8 bits are significant.
599 def i16i8imm : Operand<i16> {
600 let ParserMatchClass = ImmSExti16i8AsmOperand;
601 let OperandType = "OPERAND_IMMEDIATE";
603 // 32-bits but only 8 bits are significant.
604 def i32i8imm : Operand<i32> {
605 let ParserMatchClass = ImmSExti32i8AsmOperand;
606 let OperandType = "OPERAND_IMMEDIATE";
608 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
609 def u32u8imm : Operand<i32> {
610 let ParserMatchClass = ImmZExtu32u8AsmOperand;
611 let OperandType = "OPERAND_IMMEDIATE";
614 // 64-bits but only 32 bits are significant.
615 def i64i32imm : Operand<i64> {
616 let ParserMatchClass = ImmSExti64i32AsmOperand;
617 let OperandType = "OPERAND_IMMEDIATE";
620 // 64-bits but only 32 bits are significant, and those bits are treated as being
622 def i64i32imm_pcrel : Operand<i64> {
623 let PrintMethod = "printPCRelImm";
624 let ParserMatchClass = X86AbsMemAsmOperand;
625 let OperandType = "OPERAND_PCREL";
628 // 64-bits but only 8 bits are significant.
629 def i64i8imm : Operand<i64> {
630 let ParserMatchClass = ImmSExti64i8AsmOperand;
631 let OperandType = "OPERAND_IMMEDIATE";
634 def lea64_32mem : Operand<i32> {
635 let PrintMethod = "printi32mem";
636 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
637 let ParserMatchClass = X86MemAsmOperand;
640 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
641 def lea64mem : Operand<i64> {
642 let PrintMethod = "printi64mem";
643 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
644 let ParserMatchClass = X86MemAsmOperand;
648 //===----------------------------------------------------------------------===//
649 // X86 Complex Pattern Definitions.
652 // Define X86 specific addressing mode.
653 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
654 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
655 [add, sub, mul, X86mul_imm, shl, or, frameindex],
657 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
658 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
659 [add, sub, mul, X86mul_imm, shl, or,
660 frameindex, X86WrapperRIP],
663 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
664 [tglobaltlsaddr], []>;
666 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
667 [tglobaltlsaddr], []>;
669 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
670 [add, sub, mul, X86mul_imm, shl, or, frameindex,
673 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
674 [tglobaltlsaddr], []>;
676 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
677 [tglobaltlsaddr], []>;
679 //===----------------------------------------------------------------------===//
680 // X86 Instruction Predicate Definitions.
681 def HasCMov : Predicate<"Subtarget->hasCMov()">;
682 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
684 def HasMMX : Predicate<"Subtarget->hasMMX()">;
685 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
686 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
687 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
688 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
689 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
690 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
691 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
692 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
693 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
694 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
695 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
696 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
697 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
698 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
699 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
700 def HasAVX : Predicate<"Subtarget->hasAVX()">;
701 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
702 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
703 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
704 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
705 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
706 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
707 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
708 def HasCDI : Predicate<"Subtarget->hasCDI()">;
709 def HasPFI : Predicate<"Subtarget->hasPFI()">;
710 def HasERI : Predicate<"Subtarget->hasERI()">;
712 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
713 def HasAES : Predicate<"Subtarget->hasAES()">;
714 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
715 def HasFMA : Predicate<"Subtarget->hasFMA()">;
716 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
717 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
718 def HasXOP : Predicate<"Subtarget->hasXOP()">;
719 def HasTBM : Predicate<"Subtarget->hasTBM()">;
720 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
721 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
722 def HasF16C : Predicate<"Subtarget->hasF16C()">;
723 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
724 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
725 def HasBMI : Predicate<"Subtarget->hasBMI()">;
726 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
727 def HasRTM : Predicate<"Subtarget->hasRTM()">;
728 def HasHLE : Predicate<"Subtarget->hasHLE()">;
729 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
730 def HasADX : Predicate<"Subtarget->hasADX()">;
731 def HasSHA : Predicate<"Subtarget->hasSHA()">;
732 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
733 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
734 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
735 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
736 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
737 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
738 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
739 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
740 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
741 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
742 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
743 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
744 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
745 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
746 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
747 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
748 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
749 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
750 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
751 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
752 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
753 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
754 "TM.getCodeModel() != CodeModel::Kernel">;
755 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
756 "TM.getCodeModel() == CodeModel::Kernel">;
757 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
758 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
759 def OptForSize : Predicate<"OptForSize">;
760 def OptForSpeed : Predicate<"!OptForSize">;
761 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
762 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
763 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
765 //===----------------------------------------------------------------------===//
766 // X86 Instruction Format Definitions.
769 include "X86InstrFormats.td"
771 //===----------------------------------------------------------------------===//
772 // Pattern fragments.
775 // X86 specific condition code. These correspond to CondCode in
776 // X86InstrInfo.h. They must be kept in synch.
777 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
778 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
779 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
780 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
781 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
782 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
783 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
784 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
785 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
786 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
787 def X86_COND_NO : PatLeaf<(i8 10)>;
788 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
789 def X86_COND_NS : PatLeaf<(i8 12)>;
790 def X86_COND_O : PatLeaf<(i8 13)>;
791 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
792 def X86_COND_S : PatLeaf<(i8 15)>;
794 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
795 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
796 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
797 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
800 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
803 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
805 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
807 def i64immZExt32SExt8 : ImmLeaf<i64, [{
808 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
811 // Helper fragments for loads.
812 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
813 // known to be 32-bit aligned or better. Ditto for i8 to i16.
814 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
815 LoadSDNode *LD = cast<LoadSDNode>(N);
816 ISD::LoadExtType ExtType = LD->getExtensionType();
817 if (ExtType == ISD::NON_EXTLOAD)
819 if (ExtType == ISD::EXTLOAD)
820 return LD->getAlignment() >= 2 && !LD->isVolatile();
824 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
825 LoadSDNode *LD = cast<LoadSDNode>(N);
826 ISD::LoadExtType ExtType = LD->getExtensionType();
827 if (ExtType == ISD::EXTLOAD)
828 return LD->getAlignment() >= 2 && !LD->isVolatile();
832 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
833 LoadSDNode *LD = cast<LoadSDNode>(N);
834 ISD::LoadExtType ExtType = LD->getExtensionType();
835 if (ExtType == ISD::NON_EXTLOAD)
837 if (ExtType == ISD::EXTLOAD)
838 return LD->getAlignment() >= 4 && !LD->isVolatile();
842 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
843 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
844 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
845 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
846 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
848 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
849 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
850 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
851 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
852 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
853 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
855 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
856 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
857 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
858 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
859 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
860 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
861 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
862 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
863 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
864 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
866 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
867 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
868 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
869 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
870 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
871 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
872 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
873 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
874 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
875 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
878 // An 'and' node with a single use.
879 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
880 return N->hasOneUse();
882 // An 'srl' node with a single use.
883 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
884 return N->hasOneUse();
886 // An 'trunc' node with a single use.
887 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
888 return N->hasOneUse();
891 //===----------------------------------------------------------------------===//
896 let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
897 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
898 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
899 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
900 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
901 "nop{l}\t$zero", [], IIC_NOP>, TB;
905 // Constructing a stack frame.
906 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
907 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
909 let SchedRW = [WriteALU] in {
910 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
911 def LEAVE : I<0xC9, RawFrm,
912 (outs), (ins), "leave", [], IIC_LEAVE>,
913 Requires<[Not64BitMode]>;
915 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
916 def LEAVE64 : I<0xC9, RawFrm,
917 (outs), (ins), "leave", [], IIC_LEAVE>,
918 Requires<[In64BitMode]>;
921 //===----------------------------------------------------------------------===//
922 // Miscellaneous Instructions.
925 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
926 let mayLoad = 1, SchedRW = [WriteLoad] in {
927 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
928 IIC_POP_REG16>, OpSize;
929 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
930 IIC_POP_REG>, OpSize16, Requires<[Not64BitMode]>;
931 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
932 IIC_POP_REG>, OpSize;
933 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
934 IIC_POP_MEM>, OpSize;
935 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
936 IIC_POP_REG>, OpSize16, Requires<[Not64BitMode]>;
937 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
938 IIC_POP_MEM>, Requires<[Not64BitMode]>;
940 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
941 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
942 OpSize16, Requires<[Not64BitMode]>;
943 } // mayLoad, SchedRW
945 let mayStore = 1, SchedRW = [WriteStore] in {
946 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
947 IIC_PUSH_REG>, OpSize;
948 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
949 IIC_PUSH_REG>, OpSize16, Requires<[Not64BitMode]>;
950 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
951 IIC_PUSH_REG>, OpSize;
952 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
953 IIC_PUSH_MEM>, OpSize;
954 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
955 IIC_PUSH_REG>, OpSize16, Requires<[Not64BitMode]>;
956 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
957 IIC_PUSH_MEM>, OpSize16, Requires<[Not64BitMode]>;
959 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
960 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
961 Requires<[Not64BitMode]>;
962 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
963 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
964 Requires<[Not64BitMode]>;
965 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
966 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
967 Requires<[Not64BitMode]>;
968 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
969 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
970 Requires<[Not64BitMode]>;
972 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
974 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
975 OpSize16, Requires<[Not64BitMode]>;
977 } // mayStore, SchedRW
980 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
981 let mayLoad = 1, SchedRW = [WriteLoad] in {
982 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
983 IIC_POP_REG>, Requires<[In64BitMode]>;
984 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
985 IIC_POP_REG>, Requires<[In64BitMode]>;
986 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
987 IIC_POP_MEM>, Requires<[In64BitMode]>;
988 } // mayLoad, SchedRW
989 let mayStore = 1, SchedRW = [WriteStore] in {
990 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
991 IIC_PUSH_REG>, Requires<[In64BitMode]>;
992 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
993 IIC_PUSH_REG>, Requires<[In64BitMode]>;
994 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
995 IIC_PUSH_MEM>, Requires<[In64BitMode]>;
996 } // mayStore, SchedRW
999 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1,
1000 SchedRW = [WriteStore] in {
1001 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1002 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1003 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1004 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
1005 Requires<[In64BitMode]>;
1006 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1007 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1010 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
1011 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1012 Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1013 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
1014 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1015 Requires<[In64BitMode]>, Sched<[WriteStore]>;
1017 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1018 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
1019 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1020 OpSize16, Requires<[Not64BitMode]>;
1021 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1022 OpSize, Requires<[Not64BitMode]>;
1024 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1025 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
1026 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1027 OpSize16, Requires<[Not64BitMode]>;
1028 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1029 OpSize, Requires<[Not64BitMode]>;
1032 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1033 // GR32 = bswap GR32
1034 def BSWAP32r : I<0xC8, AddRegFrm,
1035 (outs GR32:$dst), (ins GR32:$src),
1037 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize16, TB;
1039 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1041 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1042 } // Constraints = "$src = $dst", SchedRW
1044 // Bit scan instructions.
1045 let Defs = [EFLAGS] in {
1046 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1047 "bsf{w}\t{$src, $dst|$dst, $src}",
1048 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1049 IIC_BIT_SCAN_REG>, TB, OpSize, Sched<[WriteShift]>;
1050 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1051 "bsf{w}\t{$src, $dst|$dst, $src}",
1052 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1053 IIC_BIT_SCAN_MEM>, TB, OpSize, Sched<[WriteShiftLd]>;
1054 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1055 "bsf{l}\t{$src, $dst|$dst, $src}",
1056 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1057 IIC_BIT_SCAN_REG>, TB, OpSize16,
1058 Sched<[WriteShift]>;
1059 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1060 "bsf{l}\t{$src, $dst|$dst, $src}",
1061 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1062 IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
1063 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1064 "bsf{q}\t{$src, $dst|$dst, $src}",
1065 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1066 IIC_BIT_SCAN_REG>, TB, Sched<[WriteShift]>;
1067 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1068 "bsf{q}\t{$src, $dst|$dst, $src}",
1069 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1070 IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;
1072 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1073 "bsr{w}\t{$src, $dst|$dst, $src}",
1074 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1076 TB, OpSize, Sched<[WriteShift]>;
1077 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1078 "bsr{w}\t{$src, $dst|$dst, $src}",
1079 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1080 IIC_BIT_SCAN_MEM>, TB,
1081 OpSize, Sched<[WriteShiftLd]>;
1082 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1083 "bsr{l}\t{$src, $dst|$dst, $src}",
1084 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1085 IIC_BIT_SCAN_REG>, TB, OpSize16,
1086 Sched<[WriteShift]>;
1087 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1088 "bsr{l}\t{$src, $dst|$dst, $src}",
1089 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1090 IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
1091 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1092 "bsr{q}\t{$src, $dst|$dst, $src}",
1093 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BIT_SCAN_REG>, TB,
1094 Sched<[WriteShift]>;
1095 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1096 "bsr{q}\t{$src, $dst|$dst, $src}",
1097 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1098 IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;
1099 } // Defs = [EFLAGS]
1101 let SchedRW = [WriteMicrocoded] in {
1102 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1103 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1104 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
1105 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
1106 def MOVSL : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>, OpSize16;
1107 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
1110 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1111 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1112 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>;
1113 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1114 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
1115 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1116 def STOSL : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>, OpSize16;
1117 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1118 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
1120 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
1121 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
1122 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>,
1124 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
1126 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
1127 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
1128 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>,
1130 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
1133 //===----------------------------------------------------------------------===//
1134 // Move Instructions.
1136 let SchedRW = [WriteMove] in {
1137 let neverHasSideEffects = 1 in {
1138 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1139 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1140 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1141 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1142 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1143 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1144 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1145 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1148 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1149 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1150 "mov{b}\t{$src, $dst|$dst, $src}",
1151 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1152 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1153 "mov{w}\t{$src, $dst|$dst, $src}",
1154 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
1155 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1156 "mov{l}\t{$src, $dst|$dst, $src}",
1157 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize16;
1158 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1159 "movabs{q}\t{$src, $dst|$dst, $src}",
1160 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1161 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1162 "mov{q}\t{$src, $dst|$dst, $src}",
1163 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1167 let SchedRW = [WriteStore] in {
1168 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1169 "mov{b}\t{$src, $dst|$dst, $src}",
1170 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1171 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1172 "mov{w}\t{$src, $dst|$dst, $src}",
1173 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
1174 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1175 "mov{l}\t{$src, $dst|$dst, $src}",
1176 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1177 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1178 "mov{q}\t{$src, $dst|$dst, $src}",
1179 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1182 let hasSideEffects = 0 in {
1184 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1185 /// 32-bit offset from the segment base. These are only valid in x86-32 mode.
1186 let SchedRW = [WriteALU] in {
1187 let mayLoad = 1 in {
1188 def MOV8o8a : Ii32 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
1189 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1190 Requires<[In32BitMode]>;
1191 def MOV16o16a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1192 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize,
1193 Requires<[In32BitMode]>;
1194 def MOV32o32a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
1195 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1196 OpSize16, Requires<[In32BitMode]>;
1198 def MOV8o8a_16 : Ii16 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
1199 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1200 AdSize, Requires<[In16BitMode]>;
1201 def MOV16o16a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1202 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize,
1203 AdSize, Requires<[In16BitMode]>;
1204 def MOV32o32a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
1205 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1206 AdSize, OpSize16, Requires<[In16BitMode]>;
1208 let mayStore = 1 in {
1209 def MOV8ao8 : Ii32 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
1210 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
1211 Requires<[In32BitMode]>;
1212 def MOV16ao16 : Ii32 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1213 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize,
1214 Requires<[In32BitMode]>;
1215 def MOV32ao32 : Ii32 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
1216 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1217 OpSize16, Requires<[In32BitMode]>;
1219 def MOV8ao8_16 : Ii16 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
1220 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
1221 AdSize, Requires<[In16BitMode]>;
1222 def MOV16ao16_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1223 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize,
1224 AdSize, Requires<[In16BitMode]>;
1225 def MOV32ao32_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
1226 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1227 OpSize16, AdSize, Requires<[In16BitMode]>;
1231 // These forms all have full 64-bit absolute addresses in their instructions
1232 // and use the movabs mnemonic to indicate this specific form.
1233 let mayLoad = 1 in {
1234 def MOV64o8a : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
1235 "movabs{b}\t{$src, %al|al, $src}", []>,
1236 Requires<[In64BitMode]>;
1237 def MOV64o16a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1238 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize,
1239 Requires<[In64BitMode]>;
1240 def MOV64o32a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
1241 "movabs{l}\t{$src, %eax|eax, $src}", []>,
1242 Requires<[In64BitMode]>;
1243 def MOV64o64a : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64:$src),
1244 "movabs{q}\t{$src, %rax|rax, $src}", []>,
1245 Requires<[In64BitMode]>;
1248 let mayStore = 1 in {
1249 def MOV64ao8 : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
1250 "movabs{b}\t{%al, $dst|$dst, al}", []>,
1251 Requires<[In64BitMode]>;
1252 def MOV64ao16 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1253 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize,
1254 Requires<[In64BitMode]>;
1255 def MOV64ao32 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
1256 "movabs{l}\t{%eax, $dst|$dst, eax}", []>,
1257 Requires<[In64BitMode]>;
1258 def MOV64ao64 : RIi64<0xA3, RawFrmMemOffs, (outs offset64:$dst), (ins),
1259 "movabs{q}\t{%rax, $dst|$dst, rax}", []>,
1260 Requires<[In64BitMode]>;
1262 } // hasSideEffects = 0
1264 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1265 SchedRW = [WriteMove] in {
1266 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1267 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1268 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1269 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1270 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1271 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1272 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1273 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1276 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1277 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1278 "mov{b}\t{$src, $dst|$dst, $src}",
1279 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1280 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1281 "mov{w}\t{$src, $dst|$dst, $src}",
1282 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
1283 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1284 "mov{l}\t{$src, $dst|$dst, $src}",
1285 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize16;
1286 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1287 "mov{q}\t{$src, $dst|$dst, $src}",
1288 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1291 let SchedRW = [WriteStore] in {
1292 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1293 "mov{b}\t{$src, $dst|$dst, $src}",
1294 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1295 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1296 "mov{w}\t{$src, $dst|$dst, $src}",
1297 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
1298 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1299 "mov{l}\t{$src, $dst|$dst, $src}",
1300 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1301 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1302 "mov{q}\t{$src, $dst|$dst, $src}",
1303 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1306 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1307 // that they can be used for copying and storing h registers, which can't be
1308 // encoded when a REX prefix is present.
1309 let isCodeGenOnly = 1 in {
1310 let neverHasSideEffects = 1 in
1311 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1312 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1313 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1315 let mayStore = 1, neverHasSideEffects = 1 in
1316 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1317 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1318 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1319 IIC_MOV_MEM>, Sched<[WriteStore]>;
1320 let mayLoad = 1, neverHasSideEffects = 1,
1321 canFoldAsLoad = 1, isReMaterializable = 1 in
1322 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1323 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1324 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1325 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1329 // Condition code ops, incl. set if equal/not equal/...
1330 let SchedRW = [WriteALU] in {
1331 let Defs = [EFLAGS], Uses = [AH] in
1332 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1333 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1334 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1335 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1336 IIC_AHF>; // AH = flags
1339 //===----------------------------------------------------------------------===//
1340 // Bit tests instructions: BT, BTS, BTR, BTC.
1342 let Defs = [EFLAGS] in {
1343 let SchedRW = [WriteALU] in {
1344 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1345 "bt{w}\t{$src2, $src1|$src1, $src2}",
1346 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1348 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1349 "bt{l}\t{$src2, $src1|$src1, $src2}",
1350 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1352 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1353 "bt{q}\t{$src2, $src1|$src1, $src2}",
1354 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1357 // Unlike with the register+register form, the memory+register form of the
1358 // bt instruction does not ignore the high bits of the index. From ISel's
1359 // perspective, this is pretty bizarre. Make these instructions disassembly
1362 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1363 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1364 "bt{w}\t{$src2, $src1|$src1, $src2}",
1365 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1366 // (implicit EFLAGS)]
1368 >, OpSize, TB, Requires<[FastBTMem]>;
1369 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1370 "bt{l}\t{$src2, $src1|$src1, $src2}",
1371 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1372 // (implicit EFLAGS)]
1374 >, OpSize16, TB, Requires<[FastBTMem]>;
1375 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1376 "bt{q}\t{$src2, $src1|$src1, $src2}",
1377 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1378 // (implicit EFLAGS)]
1383 let SchedRW = [WriteALU] in {
1384 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1385 "bt{w}\t{$src2, $src1|$src1, $src2}",
1386 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1387 IIC_BT_RI>, OpSize, TB;
1388 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1389 "bt{l}\t{$src2, $src1|$src1, $src2}",
1390 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1391 IIC_BT_RI>, OpSize16, TB;
1392 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1393 "bt{q}\t{$src2, $src1|$src1, $src2}",
1394 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1398 // Note that these instructions don't need FastBTMem because that
1399 // only applies when the other operand is in a register. When it's
1400 // an immediate, bt is still fast.
1401 let SchedRW = [WriteALU] in {
1402 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1403 "bt{w}\t{$src2, $src1|$src1, $src2}",
1404 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1405 ], IIC_BT_MI>, OpSize, TB;
1406 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1407 "bt{l}\t{$src2, $src1|$src1, $src2}",
1408 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1409 ], IIC_BT_MI>, OpSize16, TB;
1410 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1411 "bt{q}\t{$src2, $src1|$src1, $src2}",
1412 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1413 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1416 let hasSideEffects = 0 in {
1417 let SchedRW = [WriteALU] in {
1418 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1419 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1421 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1422 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1424 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1425 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1428 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1429 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1430 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1432 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1433 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1435 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1436 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1439 let SchedRW = [WriteALU] in {
1440 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1441 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1443 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1444 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1446 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1447 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1450 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1451 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1452 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1454 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1455 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1457 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1458 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1461 let SchedRW = [WriteALU] in {
1462 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1463 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1465 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1466 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1468 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1469 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1472 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1473 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1474 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1476 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1477 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1479 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1480 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1483 let SchedRW = [WriteALU] in {
1484 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1485 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1487 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1488 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1490 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1491 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1494 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1495 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1496 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1498 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1499 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1501 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1502 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1505 let SchedRW = [WriteALU] in {
1506 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1507 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1509 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1510 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1512 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1513 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1516 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1517 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1518 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1520 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1521 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1523 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1524 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1527 let SchedRW = [WriteALU] in {
1528 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1529 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1531 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1532 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1534 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1535 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1538 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1539 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1540 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1542 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1543 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1545 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1546 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1548 } // hasSideEffects = 0
1549 } // Defs = [EFLAGS]
1552 //===----------------------------------------------------------------------===//
1556 // Atomic swap. These are just normal xchg instructions. But since a memory
1557 // operand is referenced, the atomicity is ensured.
1558 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1559 InstrItinClass itin> {
1560 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1561 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1562 (ins GR8:$val, i8mem:$ptr),
1563 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1566 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1568 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1569 (ins GR16:$val, i16mem:$ptr),
1570 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1573 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1575 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1576 (ins GR32:$val, i32mem:$ptr),
1577 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1580 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1582 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1583 (ins GR64:$val, i64mem:$ptr),
1584 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1587 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1592 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1594 // Swap between registers.
1595 let SchedRW = [WriteALU] in {
1596 let Constraints = "$val = $dst" in {
1597 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1598 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1599 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1600 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
1601 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1602 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1604 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1605 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1608 // Swap between EAX and other registers.
1609 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1610 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize;
1611 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1612 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1613 OpSize16, Requires<[Not64BitMode]>;
1614 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1615 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1616 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1617 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1618 Requires<[In64BitMode]>;
1619 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1620 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1623 let SchedRW = [WriteALU] in {
1624 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1625 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1626 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1627 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1629 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1630 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1632 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1633 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1636 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1637 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1638 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1639 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1640 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1642 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1643 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1645 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1646 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1650 let SchedRW = [WriteALU] in {
1651 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1652 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1653 IIC_CMPXCHG_REG8>, TB;
1654 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1655 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1656 IIC_CMPXCHG_REG>, TB, OpSize;
1657 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1658 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1659 IIC_CMPXCHG_REG>, TB, OpSize16;
1660 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1661 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1662 IIC_CMPXCHG_REG>, TB;
1665 let SchedRW = [WriteALULd, WriteRMW] in {
1666 let mayLoad = 1, mayStore = 1 in {
1667 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1668 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1669 IIC_CMPXCHG_MEM8>, TB;
1670 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1671 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1672 IIC_CMPXCHG_MEM>, TB, OpSize;
1673 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1674 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1675 IIC_CMPXCHG_MEM>, TB, OpSize16;
1676 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1677 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1678 IIC_CMPXCHG_MEM>, TB;
1681 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1682 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1683 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1685 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1686 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1687 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1688 TB, Requires<[HasCmpxchg16b]>;
1692 // Lock instruction prefix
1693 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1695 // Rex64 instruction prefix
1696 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1697 Requires<[In64BitMode]>;
1699 // Data16 instruction prefix
1700 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1702 // Repeat string operation instruction prefixes
1703 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1704 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1705 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1706 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1707 // Repeat while not equal (used with CMPS and SCAS)
1708 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1712 // String manipulation instructions
1713 let SchedRW = [WriteMicrocoded] in {
1714 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1715 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1716 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1717 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize;
1718 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1719 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize16;
1720 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1721 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1724 let SchedRW = [WriteSystem] in {
1725 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
1726 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
1727 def OUTSL : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>, OpSize16;
1730 // Flag instructions
1731 let SchedRW = [WriteALU] in {
1732 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1733 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1734 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1735 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1736 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1737 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1738 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1740 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1743 // Table lookup instructions
1744 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1747 let SchedRW = [WriteMicrocoded] in {
1748 // ASCII Adjust After Addition
1749 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1750 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1751 Requires<[Not64BitMode]>;
1753 // ASCII Adjust AX Before Division
1754 // sets AL, AH and EFLAGS and uses AL and AH
1755 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1756 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1758 // ASCII Adjust AX After Multiply
1759 // sets AL, AH and EFLAGS and uses AL
1760 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1761 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1763 // ASCII Adjust AL After Subtraction - sets
1764 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1765 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1766 Requires<[Not64BitMode]>;
1768 // Decimal Adjust AL after Addition
1769 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1770 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1771 Requires<[Not64BitMode]>;
1773 // Decimal Adjust AL after Subtraction
1774 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1775 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1776 Requires<[Not64BitMode]>;
1779 let SchedRW = [WriteSystem] in {
1780 // Check Array Index Against Bounds
1781 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1782 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
1783 Requires<[Not64BitMode]>;
1784 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1785 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1786 Requires<[Not64BitMode]>;
1788 // Adjust RPL Field of Segment Selector
1789 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1790 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1791 Requires<[Not64BitMode]>;
1792 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1793 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1794 Requires<[Not64BitMode]>;
1797 //===----------------------------------------------------------------------===//
1798 // MOVBE Instructions
1800 let Predicates = [HasMOVBE] in {
1801 let SchedRW = [WriteALULd] in {
1802 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1803 "movbe{w}\t{$src, $dst|$dst, $src}",
1804 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1806 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1807 "movbe{l}\t{$src, $dst|$dst, $src}",
1808 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1810 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1811 "movbe{q}\t{$src, $dst|$dst, $src}",
1812 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1815 let SchedRW = [WriteStore] in {
1816 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1817 "movbe{w}\t{$src, $dst|$dst, $src}",
1818 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1820 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1821 "movbe{l}\t{$src, $dst|$dst, $src}",
1822 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1824 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1825 "movbe{q}\t{$src, $dst|$dst, $src}",
1826 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1831 //===----------------------------------------------------------------------===//
1832 // RDRAND Instruction
1834 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1835 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1837 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
1838 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1840 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1841 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1843 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1846 //===----------------------------------------------------------------------===//
1847 // RDSEED Instruction
1849 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1850 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1852 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize, TB;
1853 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1855 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
1856 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
1858 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
1861 //===----------------------------------------------------------------------===//
1862 // LZCNT Instruction
1864 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1865 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1866 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1867 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1869 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1870 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1871 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1872 (implicit EFLAGS)]>, XS, OpSize;
1874 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1875 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1876 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
1878 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1879 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1880 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1881 (implicit EFLAGS)]>, XS, OpSize16;
1883 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1884 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1885 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1887 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1888 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1889 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1890 (implicit EFLAGS)]>, XS;
1893 //===----------------------------------------------------------------------===//
1896 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1897 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1898 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1899 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1901 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1902 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1903 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1904 (implicit EFLAGS)]>, XS, OpSize;
1906 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1907 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1908 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
1910 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1911 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1912 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1913 (implicit EFLAGS)]>, XS, OpSize16;
1915 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1916 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1917 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1919 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1920 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1921 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1922 (implicit EFLAGS)]>, XS;
1925 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1926 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1928 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1929 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1930 [(set RC:$dst, (OpNode RC:$src)), (implicit EFLAGS)]>, T8, VEX_4V;
1931 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1932 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1933 [(set RC:$dst, (OpNode (ld_frag addr:$src))), (implicit EFLAGS)]>,
1937 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1938 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1940 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1941 X86blsr, loadi64>, VEX_W;
1942 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1943 X86blsmsk, loadi32>;
1944 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1945 X86blsmsk, loadi64>, VEX_W;
1946 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1948 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1949 X86blsi, loadi64>, VEX_W;
1952 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1953 X86MemOperand x86memop, Intrinsic Int,
1955 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1956 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1957 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1959 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1960 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1961 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1962 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1965 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1966 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1967 int_x86_bmi_bextr_32, loadi32>;
1968 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1969 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1972 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1973 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1974 int_x86_bmi_bzhi_32, loadi32>;
1975 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1976 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1979 def : Pat<(X86bzhi GR32:$src1, GR8:$src2),
1980 (BZHI32rr GR32:$src1,
1981 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1982 def : Pat<(X86bzhi (loadi32 addr:$src1), GR8:$src2),
1983 (BZHI32rm addr:$src1,
1984 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1985 def : Pat<(X86bzhi GR64:$src1, GR8:$src2),
1986 (BZHI64rr GR64:$src1,
1987 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1988 def : Pat<(X86bzhi (loadi64 addr:$src1), GR8:$src2),
1989 (BZHI64rm addr:$src1,
1990 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1992 let Predicates = [HasBMI] in {
1993 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
1994 (BEXTR32rr GR32:$src1, GR32:$src2)>;
1995 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
1996 (BEXTR32rm addr:$src1, GR32:$src2)>;
1997 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
1998 (BEXTR64rr GR64:$src1, GR64:$src2)>;
1999 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2000 (BEXTR64rm addr:$src1, GR64:$src2)>;
2003 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2004 X86MemOperand x86memop, Intrinsic Int,
2006 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2007 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2008 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2010 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2011 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2012 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2015 let Predicates = [HasBMI2] in {
2016 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2017 int_x86_bmi_pdep_32, loadi32>, T8XD;
2018 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2019 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2020 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2021 int_x86_bmi_pext_32, loadi32>, T8XS;
2022 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2023 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2026 //===----------------------------------------------------------------------===//
2029 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2031 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2032 X86MemOperand x86memop, PatFrag ld_frag,
2033 Intrinsic Int, Operand immtype,
2034 SDPatternOperator immoperator> {
2035 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2036 !strconcat(OpcodeStr,
2037 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2038 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2040 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2041 (ins x86memop:$src1, immtype:$cntl),
2042 !strconcat(OpcodeStr,
2043 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2044 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2048 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2049 int_x86_tbm_bextri_u32, i32imm, imm>;
2050 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2051 int_x86_tbm_bextri_u64, i64i32imm,
2052 i64immSExt32>, VEX_W;
2054 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2055 RegisterClass RC, string OpcodeStr,
2056 X86MemOperand x86memop, PatFrag ld_frag> {
2057 let hasSideEffects = 0 in {
2058 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2059 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2060 []>, XOP, XOP9, VEX_4V;
2062 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2063 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2064 []>, XOP, XOP9, VEX_4V;
2068 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2069 Format FormReg, Format FormMem> {
2070 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2072 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2076 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2077 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2078 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2079 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2080 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2081 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2082 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2083 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2084 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2087 //===----------------------------------------------------------------------===//
2088 // Pattern fragments to auto generate TBM instructions.
2089 //===----------------------------------------------------------------------===//
2091 let Predicates = [HasTBM] in {
2092 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2093 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2094 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2095 (BEXTRI32mi addr:$src1, imm:$src2)>;
2096 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2097 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2098 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2099 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2101 // FIXME: patterns for the load versions are not implemented
2102 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2103 (BLCFILL32rr GR32:$src)>;
2104 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2105 (BLCFILL64rr GR64:$src)>;
2107 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2108 (BLCI32rr GR32:$src)>;
2109 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2110 (BLCI64rr GR64:$src)>;
2112 // Extra patterns because opt can optimize the above patterns to this.
2113 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2114 (BLCI32rr GR32:$src)>;
2115 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2116 (BLCI64rr GR64:$src)>;
2118 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2119 (BLCIC32rr GR32:$src)>;
2120 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2121 (BLCIC64rr GR64:$src)>;
2123 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2124 (BLCMSK32rr GR32:$src)>;
2125 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2126 (BLCMSK64rr GR64:$src)>;
2128 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2129 (BLCS32rr GR32:$src)>;
2130 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2131 (BLCS64rr GR64:$src)>;
2133 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2134 (BLSFILL32rr GR32:$src)>;
2135 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2136 (BLSFILL64rr GR64:$src)>;
2138 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2139 (BLSIC32rr GR32:$src)>;
2140 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2141 (BLSIC64rr GR64:$src)>;
2143 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2144 (T1MSKC32rr GR32:$src)>;
2145 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2146 (T1MSKC64rr GR64:$src)>;
2148 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2149 (TZMSK32rr GR32:$src)>;
2150 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2151 (TZMSK64rr GR64:$src)>;
2154 //===----------------------------------------------------------------------===//
2156 //===----------------------------------------------------------------------===//
2158 include "X86InstrArithmetic.td"
2159 include "X86InstrCMovSetCC.td"
2160 include "X86InstrExtension.td"
2161 include "X86InstrControl.td"
2162 include "X86InstrShiftRotate.td"
2164 // X87 Floating Point Stack.
2165 include "X86InstrFPStack.td"
2167 // SIMD support (SSE, MMX and AVX)
2168 include "X86InstrFragmentsSIMD.td"
2170 // FMA - Fused Multiply-Add support (requires FMA)
2171 include "X86InstrFMA.td"
2174 include "X86InstrXOP.td"
2176 // SSE, MMX and 3DNow! vector support.
2177 include "X86InstrSSE.td"
2178 include "X86InstrAVX512.td"
2179 include "X86InstrMMX.td"
2180 include "X86Instr3DNow.td"
2182 include "X86InstrVMX.td"
2183 include "X86InstrSVM.td"
2185 include "X86InstrTSX.td"
2187 // System instructions.
2188 include "X86InstrSystem.td"
2190 // Compiler Pseudo Instructions and Pat Patterns
2191 include "X86InstrCompiler.td"
2193 //===----------------------------------------------------------------------===//
2194 // Assembler Mnemonic Aliases
2195 //===----------------------------------------------------------------------===//
2197 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2198 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2199 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2201 def : MnemonicAlias<"cbw", "cbtw", "att">;
2202 def : MnemonicAlias<"cwde", "cwtl", "att">;
2203 def : MnemonicAlias<"cwd", "cwtd", "att">;
2204 def : MnemonicAlias<"cdq", "cltd", "att">;
2205 def : MnemonicAlias<"cdqe", "cltq", "att">;
2206 def : MnemonicAlias<"cqo", "cqto", "att">;
2208 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2209 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2210 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2212 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2213 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2215 def : MnemonicAlias<"loopz", "loope", "att">;
2216 def : MnemonicAlias<"loopnz", "loopne", "att">;
2218 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2219 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2220 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2221 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2222 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2223 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2224 def : MnemonicAlias<"popfd", "popfl", "att">;
2226 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2227 // all modes. However: "push (addr)" and "push $42" should default to
2228 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2229 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2230 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2231 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2232 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2233 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2234 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2235 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2237 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2238 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2239 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2240 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2241 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2242 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2244 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2245 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2246 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2247 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2249 def : MnemonicAlias<"repe", "rep", "att">;
2250 def : MnemonicAlias<"repz", "rep", "att">;
2251 def : MnemonicAlias<"repnz", "repne", "att">;
2253 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2254 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2255 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2257 def : MnemonicAlias<"salb", "shlb", "att">;
2258 def : MnemonicAlias<"salw", "shlw", "att">;
2259 def : MnemonicAlias<"sall", "shll", "att">;
2260 def : MnemonicAlias<"salq", "shlq", "att">;
2262 def : MnemonicAlias<"smovb", "movsb", "att">;
2263 def : MnemonicAlias<"smovw", "movsw", "att">;
2264 def : MnemonicAlias<"smovl", "movsl", "att">;
2265 def : MnemonicAlias<"smovq", "movsq", "att">;
2267 def : MnemonicAlias<"ud2a", "ud2", "att">;
2268 def : MnemonicAlias<"verrw", "verr", "att">;
2270 // System instruction aliases.
2271 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2272 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2273 def : MnemonicAlias<"sysret", "sysretl", "att">;
2274 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2276 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2277 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2278 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2279 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2280 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2281 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2282 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2283 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2284 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2285 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2286 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2287 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2290 // Floating point stack aliases.
2291 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2292 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2293 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2294 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2295 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2296 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2297 def : MnemonicAlias<"fildq", "fildll", "att">;
2298 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2299 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2300 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2301 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2302 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2303 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2304 def : MnemonicAlias<"fwait", "wait", "att">;
2307 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2309 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2310 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2312 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2313 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2314 /// example "setz" -> "sete".
2315 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2317 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2318 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2319 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2320 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2321 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2322 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2323 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2324 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2325 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2326 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2328 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2329 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2330 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2331 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2334 // Aliases for set<CC>
2335 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2336 // Aliases for j<CC>
2337 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2338 // Aliases for cmov<CC>{w,l,q}
2339 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2340 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2341 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2342 // No size suffix for intel-style asm.
2343 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2346 //===----------------------------------------------------------------------===//
2347 // Assembler Instruction Aliases
2348 //===----------------------------------------------------------------------===//
2350 // aad/aam default to base 10 if no operand is specified.
2351 def : InstAlias<"aad", (AAD8i8 10)>;
2352 def : InstAlias<"aam", (AAM8i8 10)>;
2354 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2355 // Likewise for btc/btr/bts.
2356 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2357 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2358 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2359 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2360 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2361 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2362 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2363 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2366 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2367 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2368 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2369 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2371 // lods aliases. Accept the destination being omitted because it's implicit
2372 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2373 // in the destination.
2374 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2375 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2376 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2377 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2378 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2379 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2380 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2381 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2383 // div and idiv aliases for explicit A register.
2384 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2385 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2386 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2387 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2388 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2389 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2390 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2391 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2392 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2393 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2394 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2395 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2396 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2397 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2398 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2399 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2403 // Various unary fpstack operations default to operating on on ST1.
2404 // For example, "fxch" -> "fxch %st(1)"
2405 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2406 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2407 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2408 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2409 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2410 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2411 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2412 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2413 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2414 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2415 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2416 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2417 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2418 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2419 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2421 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2422 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2423 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2425 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2426 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2427 (Inst RST:$op), EmitAlias>;
2428 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2429 (Inst ST0), EmitAlias>;
2432 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2433 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2434 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2435 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2436 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2437 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2438 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2439 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2440 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2441 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2442 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2443 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2444 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2445 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2446 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2447 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2450 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2451 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2452 // solely because gas supports it.
2453 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2454 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2455 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2456 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2457 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2458 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2460 // We accept "fnstsw %eax" even though it only writes %ax.
2461 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2462 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2463 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2465 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2466 // this is compatible with what GAS does.
2467 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2468 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2469 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>, Requires<[Not16BitMode]>;
2470 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>, Requires<[Not16BitMode]>;
2471 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2472 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2473 def : InstAlias<"lcall *$dst", (FARCALL16m opaque32mem:$dst)>, Requires<[In16BitMode]>;
2474 def : InstAlias<"ljmp *$dst", (FARJMP16m opaque32mem:$dst)>, Requires<[In16BitMode]>;
2476 def : InstAlias<"call *$dst", (CALL64m i16mem:$dst)>, Requires<[In64BitMode]>;
2477 def : InstAlias<"jmp *$dst", (JMP64m i16mem:$dst)>, Requires<[In64BitMode]>;
2478 def : InstAlias<"call *$dst", (CALL32m i16mem:$dst)>, Requires<[In32BitMode]>;
2479 def : InstAlias<"jmp *$dst", (JMP32m i16mem:$dst)>, Requires<[In32BitMode]>;
2480 def : InstAlias<"call *$dst", (CALL16m i16mem:$dst)>, Requires<[In16BitMode]>;
2481 def : InstAlias<"jmp *$dst", (JMP16m i16mem:$dst)>, Requires<[In16BitMode]>;
2484 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2485 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
2486 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
2487 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
2488 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
2489 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
2490 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
2492 // inb %dx -> inb %al, %dx
2493 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2494 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2495 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2496 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2497 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2498 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2501 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2502 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2503 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2504 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2505 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2506 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2507 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2508 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2509 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2511 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2512 // the move. All segment/mem forms are equivalent, this has the shortest
2514 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
2515 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
2517 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2518 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
2520 // Match 'movq GR64, MMX' as an alias for movd.
2521 def : InstAlias<"movq $src, $dst",
2522 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2523 def : InstAlias<"movq $src, $dst",
2524 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2526 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
2527 // alias for movsl. (as in rep; movsd)
2528 def : InstAlias<"movsd", (MOVSL), 0>;
2531 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2532 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2533 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2534 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2535 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2536 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2537 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2540 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2541 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2542 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2543 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2544 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2545 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2546 // Note: No GR32->GR64 movzx form.
2548 // outb %dx -> outb %al, %dx
2549 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2550 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2551 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2552 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2553 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2554 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2556 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2557 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2558 // errors, since its encoding is the most compact.
2559 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
2561 // shld/shrd op,op -> shld op, op, CL
2562 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2563 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2564 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2565 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2566 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2567 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2569 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2570 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2571 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2572 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2573 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2574 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2576 /* FIXME: This is disabled because the asm matcher is currently incapable of
2577 * matching a fixed immediate like $1.
2578 // "shl X, $1" is an alias for "shl X".
2579 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2580 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2581 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2582 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2583 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2584 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2585 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2586 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2587 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2588 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2589 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2590 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2591 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2592 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2593 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2594 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2595 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2598 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2599 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2600 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2601 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2604 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2605 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", (TEST8rm GR8 :$val, i8mem :$mem)>;
2606 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", (TEST16rm GR16:$val, i16mem:$mem)>;
2607 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", (TEST32rm GR32:$val, i32mem:$mem)>;
2608 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", (TEST64rm GR64:$val, i64mem:$mem)>;
2610 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2611 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", (XCHG8rm GR8 :$val, i8mem :$mem)>;
2612 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", (XCHG16rm GR16:$val, i16mem:$mem)>;
2613 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", (XCHG32rm GR32:$val, i32mem:$mem)>;
2614 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", (XCHG64rm GR64:$val, i64mem:$mem)>;
2616 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2617 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src)>;
2618 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src)>, Requires<[Not64BitMode]>;
2619 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2620 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src)>;