1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 // *mem - Operand definitions for the funky X86 addressing mode operands.
18 def i8mem : Operand<i8> {
19 let NumMIOperands = 4;
20 let PrintMethod = "printMemoryOperand";
23 def i16mem : Operand<i16> {
24 let NumMIOperands = 4;
25 let PrintMethod = "printMemoryOperand";
28 def i32mem : Operand<i32> {
29 let NumMIOperands = 4;
30 let PrintMethod = "printMemoryOperand";
34 // Format specifies the encoding used by the instruction. This is part of the
35 // ad-hoc solution used to emit machine instruction encodings by our machine
37 class Format<bits<5> val> {
41 def Pseudo : Format<0>; def RawFrm : Format<1>;
42 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
43 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
44 def MRMSrcMem : Format<6>;
45 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
46 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
47 def MRM6r : Format<22>; def MRM7r : Format<23>;
48 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
49 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
50 def MRM6m : Format<30>; def MRM7m : Format<31>;
52 // ImmType - This specifies the immediate type used by an instruction. This is
53 // part of the ad-hoc solution used to emit machine instruction encodings by our
54 // machine code emitter.
55 class ImmType<bits<2> val> {
58 def NoImm : ImmType<0>;
59 def Imm8 : ImmType<1>;
60 def Imm16 : ImmType<2>;
61 def Imm32 : ImmType<3>;
63 // MemType - This specifies the immediate type used by an instruction. This is
64 // part of the ad-hoc solution used to emit machine instruction encodings by our
65 // machine code emitter.
66 class MemType<bits<3> val> {
69 def NoMem : MemType<0>;
70 def Mem8 : MemType<1>;
71 def Mem16 : MemType<2>;
72 def Mem32 : MemType<3>;
73 def Mem64 : MemType<4>;
74 def Mem80 : MemType<5>;
75 def Mem128 : MemType<6>;
77 // FPFormat - This specifies what form this FP instruction has. This is used by
78 // the Floating-Point stackifier pass.
79 class FPFormat<bits<3> val> {
82 def NotFP : FPFormat<0>;
83 def ZeroArgFP : FPFormat<1>;
84 def OneArgFP : FPFormat<2>;
85 def OneArgFPRW : FPFormat<3>;
86 def TwoArgFP : FPFormat<4>;
87 def CompareFP : FPFormat<5>;
88 def CondMovFP : FPFormat<6>;
89 def SpecialFP : FPFormat<7>;
92 class X86Inst<string nam, bits<8> opcod, Format f, MemType m, ImmType i> : Instruction {
93 let Namespace = "X86";
96 bits<8> Opcode = opcod;
98 bits<5> FormBits = Form.Value;
100 bits<3> MemTypeBits = MemT.Value;
102 bits<2> ImmTypeBits = ImmT.Value;
105 // Attributes specific to X86 instructions...
107 bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
109 // Flag whether implicit register usage is printed after the instruction.
110 bit printImplicitUsesAfter = 0;
112 bits<4> Prefix = 0; // Which prefix byte does this inst have?
113 FPFormat FPForm; // What flavor of FP instruction is this?
114 bits<3> FPFormBits = 0;
117 class Imp<list<Register> uses, list<Register> defs> {
118 list<Register> Uses = uses;
119 list<Register> Defs = defs;
122 // II - InstructionInfo - this will eventually replace the I class.
123 class II<dag ops, string AsmStr> {
124 dag OperandList = ops;
125 string AsmString = AsmStr;
129 // Prefix byte classes which are used to indicate to the ad-hoc machine code
130 // emitter that various prefix bytes are required.
131 class OpSize { bit hasOpSizePrefix = 1; }
132 class TB { bits<4> Prefix = 1; }
133 class REP { bits<4> Prefix = 2; }
134 class D8 { bits<4> Prefix = 3; }
135 class D9 { bits<4> Prefix = 4; }
136 class DA { bits<4> Prefix = 5; }
137 class DB { bits<4> Prefix = 6; }
138 class DC { bits<4> Prefix = 7; }
139 class DD { bits<4> Prefix = 8; }
140 class DE { bits<4> Prefix = 9; }
141 class DF { bits<4> Prefix = 10; }
144 //===----------------------------------------------------------------------===//
145 // Instruction templates...
147 class I<bits<8> o, Format f, dag ops, string asm> : X86Inst<"", o, f, NoMem, NoImm>, II<ops, asm>;
149 class Im<string n, bits<8> o, Format f, MemType m> : X86Inst<n, o, f, m, NoImm>;
150 class Im8 <string n, bits<8> o, Format f> : Im<n, o, f, Mem8 >;
151 class Im16<string n, bits<8> o, Format f> : Im<n, o, f, Mem16>;
152 class Im32<string n, bits<8> o, Format f> : Im<n, o, f, Mem32>;
154 class Ii<bits<8> o, Format f, ImmType i> : X86Inst<"", o, f, NoMem, i>;
155 class Ii8 <bits<8> o, Format f, dag ops, string asm> : Ii<o, f, Imm8 >, II<ops, asm>;
156 class Ii16<bits<8> o, Format f, dag ops, string asm> : Ii<o, f, Imm16>, II<ops, asm>;
157 class Ii32<bits<8> o, Format f, dag ops, string asm> : Ii<o, f, Imm32>, II<ops, asm>;
159 class Im8i8 <string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem8 , Imm8 >;
160 class Im16i16<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem16, Imm16>;
161 class Im32i32<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm32>;
163 class Im16i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem16, Imm8>;
164 class Im32i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm8>;
166 //===----------------------------------------------------------------------===//
167 // Instruction list...
170 def PHI : I<0, Pseudo, (ops), "PHINODE">; // PHI node.
171 def NOOP : I<0x90, RawFrm, (ops), "nop">; // nop
173 def ADJCALLSTACKDOWN : I<0, Pseudo, (ops), "#ADJCALLSTACKDOWN">;
174 def ADJCALLSTACKUP : I<0, Pseudo, (ops), "#ADJCALLSTACKUP">;
175 def IMPLICIT_USE : I<0, Pseudo, (ops), "#IMPLICIT_USE">;
176 def IMPLICIT_DEF : I<0, Pseudo, (ops), "#IMPLICIT_DEF">;
177 let isTerminator = 1 in
178 let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
179 def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL">;
181 //===----------------------------------------------------------------------===//
182 // Control Flow Instructions...
185 // Return instruction...
186 let isTerminator = 1, isReturn = 1, isBarrier = 1 in
187 def RET : I<0xC3, RawFrm, (ops), "ret">;
189 // All branches are RawFrm, Void, Branch, and Terminators
190 let isBranch = 1, isTerminator = 1 in
191 class IBr<bits<8> opcode, dag ops, string asm> : I<opcode, RawFrm, ops, asm>;
194 def JMP : IBr<0xE9, (ops i32imm:$dst), "jmp $dst">;
195 def JB : IBr<0x82, (ops i32imm:$dst), "jb $dst">, TB;
196 def JAE : IBr<0x83, (ops i32imm:$dst), "jae $dst">, TB;
197 def JE : IBr<0x84, (ops i32imm:$dst), "je $dst">, TB;
198 def JNE : IBr<0x85, (ops i32imm:$dst), "jne $dst">, TB;
199 def JBE : IBr<0x86, (ops i32imm:$dst), "jbe $dst">, TB;
200 def JA : IBr<0x87, (ops i32imm:$dst), "ja $dst">, TB;
201 def JS : IBr<0x88, (ops i32imm:$dst), "js $dst">, TB;
202 def JNS : IBr<0x89, (ops i32imm:$dst), "jns $dst">, TB;
203 def JL : IBr<0x8C, (ops i32imm:$dst), "jl $dst">, TB;
204 def JGE : IBr<0x8D, (ops i32imm:$dst), "jge $dst">, TB;
205 def JLE : IBr<0x8E, (ops i32imm:$dst), "jle $dst">, TB;
206 def JG : IBr<0x8F, (ops i32imm:$dst), "jg $dst">, TB;
209 //===----------------------------------------------------------------------===//
210 // Call Instructions...
213 // All calls clobber the non-callee saved registers...
214 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
215 def CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoMem, NoImm>; // FIXME: 'call' doesn't allow 'OFFSET'
216 def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call $dst">;
217 def CALL32m : Im32<"call", 0xFF, MRM2m>;
221 //===----------------------------------------------------------------------===//
222 // Miscellaneous Instructions...
224 def LEAVE : I<0xC9, RawFrm,
225 (ops), "leave">, Imp<[EBP,ESP],[EBP,ESP]>;
226 def POP32r : I<0x58, AddRegFrm,
227 (ops R32:$reg), "pop $reg">, Imp<[ESP],[ESP]>;
229 let isTwoAddress = 1 in // R32 = bswap R32
230 def BSWAP32r : I<0xC8, AddRegFrm,
231 (ops R32:$dst, R32:$src), "bswap $dst">, TB;
233 def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8
234 (ops R8:$src1, R8:$src2), "xchg $src1, $src2">;
235 def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16
236 (ops R16:$src1, R16:$src2), "xchg $src1, $src2">, OpSize;
237 def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32
238 (ops R32:$src1, R32:$src2), "xchg $src1, $src2">;
240 def XCHG8mr : Im8 <"", 0x86, MRMDestMem>, // xchg [mem8], R8
241 II<(ops i8mem:$src1, R8:$src2), "xchg $src1, $src2">;
242 def XCHG16mr : Im16<"xchg", 0x87, MRMDestMem>, OpSize; // xchg [mem16], R16
243 def XCHG32mr : Im32<"xchg", 0x87, MRMDestMem>; // xchg [mem32], R32
244 def XCHG8rm : Im8 <"xchg", 0x86, MRMSrcMem >; // xchg R8, [mem8]
245 def XCHG16rm : Im16<"xchg", 0x87, MRMSrcMem >, OpSize; // xchg R16, [mem16]
246 def XCHG32rm : Im32<"xchg", 0x87, MRMSrcMem >; // xchg R32, [mem32]
248 def LEA16r : Im32<"lea", 0x8D, MRMSrcMem>, OpSize; // R16 = lea [mem]
249 def LEA32r : Im32<"lea", 0x8D, MRMSrcMem>; // R32 = lea [mem]
252 def REP_MOVSB : I<0xA4, RawFrm, (ops), "rep movsb">,
253 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
254 def REP_MOVSW : I<0xA5, RawFrm, (ops), "rep movsw">,
255 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
256 def REP_MOVSD : I<0xA5, RawFrm, (ops), "rep movsd">,
257 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
259 def REP_STOSB : I<0xAA, RawFrm, (ops), "rep stosb">,
260 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
261 def REP_STOSW : I<0xAB, RawFrm, (ops), "rep stosw">,
262 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
263 def REP_STOSD : I<0xAB, RawFrm, (ops), "rep stosd">,
264 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
267 //===----------------------------------------------------------------------===//
268 // Input/Output Instructions...
270 def IN8rr : I<0xEC, RawFrm, (ops),
271 "in %AL, %DX">, Imp<[DX], [AL]>;
272 def IN16rr : I<0xED, RawFrm, (ops),
273 "in %AX, %DX">, Imp<[DX], [AX]>, OpSize;
274 def IN32rr : I<0xED, RawFrm, (ops),
275 "in %EAX, %DX">, Imp<[DX],[EAX]>;
277 def IN8ri : Ii16<0xE4, RawFrm, (ops i16imm:$port),
278 "in %AL, $port">, Imp<[], [AL]>;
279 def IN16ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
280 "in %AX, $port">, Imp<[], [AX]>, OpSize;
281 def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port),
282 "in %EAX, $port">, Imp<[],[EAX]>;
284 def OUT8rr : I<0xEE, RawFrm, (ops),
285 "out %DX, %AL">, Imp<[DX, AL], []>;
286 def OUT16rr : I<0xEF, RawFrm, (ops),
287 "out %DX, %AX">, Imp<[DX, AX], []>, OpSize;
288 def OUT32rr : I<0xEF, RawFrm, (ops),
289 "out %DX, %EAX">, Imp<[DX, EAX], []>;
291 def OUT8ir : Ii16<0xE6, RawFrm, (ops i16imm:$port),
292 "out $port, %AL">, Imp<[AL], []>;
293 def OUT16ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
294 "out $port, %AX">, Imp<[AX], []>, OpSize;
295 def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port),
296 "out $port, %EAX">, Imp<[EAX], []>;
298 //===----------------------------------------------------------------------===//
299 // Move Instructions...
301 def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src), "mov $dst, $src">;
302 def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src), "mov $dst, $src">, OpSize;
303 def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src), "mov $dst, $src">;
304 def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src), "mov $dst, $src">;
305 def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src), "mov $dst, $src">, OpSize;
306 def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src), "mov $dst, $src">;
307 def MOV8mi : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8
308 def MOV16mi : Im16i16<"mov", 0xC7, MRM0m >, OpSize; // [mem16] = imm16
309 def MOV32mi : Im32i32<"mov", 0xC7, MRM0m >; // [mem32] = imm32
311 def MOV8rm : Im8 <"", 0x8A, MRMSrcMem>, // R8 = [mem8]
312 II<(ops R8 :$dst, i8mem :$src), "mov $dst, $src">;
313 def MOV16rm : Im16<"", 0x8B, MRMSrcMem>, OpSize, // R16 = [mem16]
314 II<(ops R16:$dst, i16mem:$src), "mov $dst, $src">;
315 def MOV32rm : Im32<"", 0x8B, MRMSrcMem>, // R32 = [mem32]
316 II<(ops R32:$dst, i32mem:$src), "mov $dst, $src">;
318 def MOV8mr : Im8 <"", 0x88, MRMDestMem>, // [mem8] = R8
319 II<(ops i8mem :$dst, R8 :$src), "mov $dst, $src">;
320 def MOV16mr : Im16<"", 0x89, MRMDestMem>, OpSize, // [mem16] = R16
321 II<(ops i16mem:$dst, R16:$src), "mov $dst, $src">;
322 def MOV32mr : Im32<"", 0x89, MRMDestMem>, // [mem32] = R32
323 II<(ops i32mem:$dst, R32:$src), "mov $dst, $src">;
325 //===----------------------------------------------------------------------===//
326 // Fixed-Register Multiplication and Division Instructions...
329 // Extra precision multiplication
330 def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul $src">,
331 Imp<[AL],[AX]>; // AL,AH = AL*R8
332 def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul $src">,
333 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
334 def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul $src">,
335 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
336 def MUL8m : Im8 <"mul", 0xF6, MRM4m>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
337 def MUL16m : Im16<"mul", 0xF7, MRM4m>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16]
338 def MUL32m : Im32<"mul", 0xF7, MRM4m>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
340 // unsigned division/remainder
341 def DIV8r : I<0xF6, MRM6r, (ops R8:$src), "div $src">,
342 Imp<[AX],[AX]>; // AX/r8 = AL,AH
343 def DIV16r : I<0xF7, MRM6r, (ops R16:$src), "div $src">,
344 Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
345 def DIV32r : I<0xF7, MRM6r, (ops R32:$src), "div $src">,
346 Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
347 def DIV8m : Im8 <"div", 0xF6, MRM6m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
348 def DIV16m : Im16<"div", 0xF7, MRM6m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
349 def DIV32m : Im32<"div", 0xF7, MRM6m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
351 // Signed division/remainder.
352 def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), "idiv $src">,
353 Imp<[AX],[AX]>; // AX/r8 = AL,AH
354 def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), "idiv $src">,
355 Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
356 def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), "idiv $src">,
357 Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
358 def IDIV8m : Im8 <"idiv",0xF6, MRM7m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
359 def IDIV16m: Im16<"idiv",0xF7, MRM7m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
360 def IDIV32m: Im32<"idiv",0xF7, MRM7m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
362 // Sign-extenders for division.
363 def CBW : I<0x98, RawFrm, (ops), "cbw">, Imp<[AL],[AH]>; // AX = signext(AL)
364 def CWD : I<0x99, RawFrm, (ops), "cwd">, Imp<[AX],[DX]>; // DX:AX = signext(AX)
365 def CDQ : I<0x99, RawFrm, (ops), "cdq">, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX)
368 //===----------------------------------------------------------------------===//
369 // Two address Instructions...
371 let isTwoAddress = 1 in {
374 def CMOVB16rr : I<0x42, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
375 "cmovb $dst, $src2">, TB, OpSize; // if <u, R16 = R16
376 def CMOVB16rm : Im16<"cmovb", 0x42, MRMSrcMem>, TB, OpSize; // if <u, R16 = [mem16]
377 def CMOVB32rr : I<0x42, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
378 "cmovb $dst, $src2">, TB; // if <u, R32 = R32
379 def CMOVB32rm : Im32<"cmovb", 0x42, MRMSrcMem>, TB; // if <u, R32 = [mem32]
381 def CMOVAE16rr: I<0x43, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
382 "cmovae $dst, $src2">, TB, OpSize; // if >=u, R16 = R16
383 def CMOVAE16rm: Im16<"cmovae", 0x43, MRMSrcMem>, TB, OpSize; // if >=u, R16 = [mem16]
384 def CMOVAE32rr: I<0x43, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
385 "cmovae $dst, $src2">, TB; // if >=u, R32 = R32
386 def CMOVAE32rm: Im32<"cmovae", 0x43, MRMSrcMem>, TB; // if >=u, R32 = [mem32]
388 def CMOVE16rr : I<0x44, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
389 "cmove $dst, $src2">, TB, OpSize; // if ==, R16 = R16
390 def CMOVE16rm : Im16<"cmove", 0x44, MRMSrcMem>, TB, OpSize; // if ==, R16 = [mem16]
391 def CMOVE32rr : I<0x44, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
392 "cmove $dst, $src2">, TB; // if ==, R32 = R32
393 def CMOVE32rm : Im32<"cmove", 0x44, MRMSrcMem>, TB; // if ==, R32 = [mem32]
395 def CMOVNE16rr: I<0x45, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
396 "cmovne $dst, $src2">, TB, OpSize; // if !=, R16 = R16
397 def CMOVNE16rm: Im16<"cmovne",0x45, MRMSrcMem>, TB, OpSize; // if !=, R16 = [mem16]
398 def CMOVNE32rr: I<0x45, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
399 "cmovne $dst, $src2">, TB; // if !=, R32 = R32
400 def CMOVNE32rm: Im32<"cmovne",0x45, MRMSrcMem>, TB; // if !=, R32 = [mem32]
402 def CMOVBE16rr: I<0x46, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
403 "cmovbe $dst, $src2">, TB, OpSize; // if <=u, R16 = R16
404 def CMOVBE16rm: Im16<"cmovbe",0x46, MRMSrcMem>, TB, OpSize; // if <=u, R16 = [mem16]
405 def CMOVBE32rr: I<0x46, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
406 "cmovbe $dst, $src2">, TB; // if <=u, R32 = R32
407 def CMOVBE32rm: Im32<"cmovbe",0x46, MRMSrcMem>, TB; // if <=u, R32 = [mem32]
409 def CMOVA16rr : I<0x47, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
410 "cmova $dst, $src2">, TB, OpSize; // if >u, R16 = R16
411 def CMOVA16rm : Im16<"cmova", 0x47, MRMSrcMem>, TB, OpSize; // if >u, R16 = [mem16]
412 def CMOVA32rr : I<0x47, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
413 "cmova $dst, $src2">, TB; // if >u, R32 = R32
414 def CMOVA32rm : Im32<"cmova", 0x47, MRMSrcMem>, TB; // if >u, R32 = [mem32]
416 def CMOVS16rr : I<0x48, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
417 "cmovs $dst, $src2">, TB, OpSize; // if signed, R16 = R16
418 def CMOVS16rm : Im16<"cmovs", 0x48, MRMSrcMem>, TB, OpSize; // if signed, R16 = [mem16]
419 def CMOVS32rr : I<0x48, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
420 "cmovs $dst, $src2">, TB; // if signed, R32 = R32
421 def CMOVS32rm : Im32<"cmovs", 0x48, MRMSrcMem>, TB; // if signed, R32 = [mem32]
423 def CMOVNS16rr: I<0x49, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
424 "cmovns $dst, $src2">, TB, OpSize; // if !signed, R16 = R16
425 def CMOVNS16rm: Im16<"cmovns",0x49, MRMSrcMem>, TB, OpSize; // if !signed, R16 = [mem16]
426 def CMOVNS32rr: I<0x49, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
427 "cmovns $dst, $src2">, TB; // if !signed, R32 = R32
428 def CMOVNS32rm: Im32<"cmovns",0x49, MRMSrcMem>, TB; // if !signed, R32 = [mem32]
430 def CMOVL16rr : I<0x4C, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
431 "cmovl $dst, $src2">, TB, OpSize; // if <s, R16 = R16
432 def CMOVL16rm : Im16<"cmovl", 0x4C, MRMSrcMem>, TB, OpSize; // if <s, R16 = [mem16]
433 def CMOVL32rr : I<0x4C, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
434 "cmovl $dst, $src2">, TB; // if <s, R32 = R32
435 def CMOVL32rm : Im32<"cmovl", 0x4C, MRMSrcMem>, TB; // if <s, R32 = [mem32]
437 def CMOVGE16rr: I<0x4D, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
438 "cmovge $dst, $src2">, TB, OpSize; // if >=s, R16 = R16
439 def CMOVGE16rm: Im16<"cmovge",0x4D, MRMSrcMem>, TB, OpSize; // if >=s, R16 = [mem16]
440 def CMOVGE32rr: I<0x4D, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
441 "cmovge $dst, $src2">, TB; // if >=s, R32 = R32
442 def CMOVGE32rm: Im32<"cmovge",0x4D, MRMSrcMem>, TB; // if >=s, R32 = [mem32]
444 def CMOVLE16rr: I<0x4E, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
445 "cmovle $dst, $src2">, TB, OpSize; // if <=s, R16 = R16
446 def CMOVLE16rm: Im16<"cmovle",0x4E, MRMSrcMem>, TB, OpSize; // if <=s, R16 = [mem16]
447 def CMOVLE32rr: I<0x4E, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
448 "cmovle $dst, $src2">, TB; // if <=s, R32 = R32
449 def CMOVLE32rm: Im32<"cmovle",0x4E, MRMSrcMem>, TB; // if <=s, R32 = [mem32]
451 def CMOVG16rr : I<0x4F, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2),
452 "cmovg $dst, $src2">, TB, OpSize; // if >s, R16 = R16
453 def CMOVG16rm : Im16<"cmovg", 0x4F, MRMSrcMem>, TB, OpSize; // if >s, R16 = [mem16]
454 def CMOVG32rr : I<0x4F, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
455 "cmovg $dst, $src2">, TB; // if >s, R32 = R32
456 def CMOVG32rm : Im32<"cmovg", 0x4F, MRMSrcMem>, TB; // if >s, R32 = [mem32]
458 // unary instructions
459 def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg $dst">;
460 def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg $dst">, OpSize;
461 def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg $dst">;
462 def NEG8m : Im8 <"neg", 0xF6, MRM3m>; // [mem8] = -[mem8] = 0-[mem8]
463 def NEG16m : Im16<"neg", 0xF7, MRM3m>, OpSize; // [mem16] = -[mem16] = 0-[mem16]
464 def NEG32m : Im32<"neg", 0xF7, MRM3m>; // [mem32] = -[mem32] = 0-[mem32]
466 def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not $dst">;
467 def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not $dst">, OpSize;
468 def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not $dst">;
469 def NOT8m : Im8 <"not", 0xF6, MRM2m>; // [mem8] = ~[mem8] = [mem8^-1]
470 def NOT16m : Im16<"not", 0xF7, MRM2m>, OpSize; // [mem16] = ~[mem16] = [mem16^-1]
471 def NOT32m : Im32<"not", 0xF7, MRM2m>; // [mem32] = ~[mem32] = [mem32^-1]
473 def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc $dst">;
474 def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc $dst">, OpSize;
475 def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc $dst">;
476 def INC8m : Im8 <"inc", 0xFE, MRM0m>; // ++R8
477 def INC16m : Im16<"inc", 0xFF, MRM0m>, OpSize; // ++R16
478 def INC32m : Im32<"inc", 0xFF, MRM0m>; // ++R32
480 def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec $dst">;
481 def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec $dst">, OpSize;
482 def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec $dst">;
483 def DEC8m : Im8 <"dec", 0xFE, MRM1m>; // --[mem8]
484 def DEC16m : Im16<"dec", 0xFF, MRM1m>, OpSize; // --[mem16]
485 def DEC32m : Im32<"dec", 0xFF, MRM1m>; // --[mem32]
487 // Logical operators...
488 def AND8rr : I<0x20, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), "and $dst, $src2">;
489 def AND16rr : I<0x21, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), "and $dst, $src2">, OpSize;
490 def AND32rr : I<0x21, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "and $dst, $src2">;
491 def AND8mr : Im8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8
492 def AND16mr : Im16 <"and", 0x21, MRMDestMem>, OpSize; // [mem16] &= R16
493 def AND32mr : Im32 <"and", 0x21, MRMDestMem>; // [mem32] &= R32
494 def AND8rm : Im8 <"and", 0x22, MRMSrcMem >; // R8 &= [mem8]
495 def AND16rm : Im16 <"and", 0x23, MRMSrcMem >, OpSize; // R16 &= [mem16]
496 def AND32rm : Im32 <"and", 0x23, MRMSrcMem >; // R32 &= [mem32]
498 def AND8ri : Ii8 <0x80, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm :$src2),
500 def AND16ri : Ii16<0x81, MRM4r, (ops R16:$dst, R16:$src1, i16imm:$src2),
501 "and $dst, $src2">, OpSize;
502 def AND32ri : Ii32<0x81, MRM4r, (ops R32:$dst, R32:$src1, i32imm:$src2),
504 def AND8mi : Im8i8 <"and", 0x80, MRM4m >; // [mem8] &= imm8
505 def AND16mi : Im16i16<"and", 0x81, MRM4m >, OpSize; // [mem16] &= imm16
506 def AND32mi : Im32i32<"and", 0x81, MRM4m >; // [mem32] &= imm32
508 def AND16ri8 : Ii8<0x83, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2),
509 "and $dst, $src2" >, OpSize;
510 def AND32ri8 : Ii8<0x83, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2),
512 def AND16mi8 : Im16i8<"and", 0x83, MRM4m >, OpSize; // [mem16] &= imm8
513 def AND32mi8 : Im32i8<"and", 0x83, MRM4m >; // [mem32] &= imm8
516 def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2),
518 def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2),
519 "or $dst, $src2">, OpSize;
520 def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
522 def OR8mr : Im8 <"or" , 0x08, MRMDestMem>; // [mem8] |= R8
523 def OR16mr : Im16 <"or" , 0x09, MRMDestMem>, OpSize; // [mem16] |= R16
524 def OR32mr : Im32 <"or" , 0x09, MRMDestMem>; // [mem32] |= R32
525 def OR8rm : Im8 <"or" , 0x0A, MRMSrcMem >; // R8 |= [mem8]
526 def OR16rm : Im16 <"or" , 0x0B, MRMSrcMem >, OpSize; // R16 |= [mem16]
527 def OR32rm : Im32 <"or" , 0x0B, MRMSrcMem >; // R32 |= [mem32]
529 def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
531 def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2),
532 "or $dst, $src2">, OpSize;
533 def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2),
535 def OR8mi : Im8i8 <"or" , 0x80, MRM1m>; // [mem8] |= imm8
536 def OR16mi : Im16i16<"or" , 0x81, MRM1m>, OpSize; // [mem16] |= imm16
537 def OR32mi : Im32i32<"or" , 0x81, MRM1m>; // [mem32] |= imm32
539 def OR16ri8 : Ii8<0x83, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
540 "or $dst, $src2">, OpSize;
541 def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2),
543 def OR16mi8 : Im16i8<"or" , 0x83, MRM1m>, OpSize; // [mem16] |= imm8
544 def OR32mi8 : Im32i8<"or" , 0x83, MRM1m>; // [mem32] |= imm8
547 def XOR8rr : I<0x30, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), "xor $dst, $src2">;
548 def XOR16rr : I<0x31, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), "xor $dst, $src2">, OpSize;
549 def XOR32rr : I<0x31, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "xor $dst, $src2">;
550 def XOR8mr : Im8 <"xor", 0x30, MRMDestMem>; // [mem8] ^= R8
551 def XOR16mr : Im16 <"xor", 0x31, MRMDestMem>, OpSize; // [mem16] ^= R16
552 def XOR32mr : Im32 <"xor", 0x31, MRMDestMem>; // [mem32] ^= R32
553 def XOR8rm : Im8 <"xor", 0x32, MRMSrcMem >; // R8 ^= [mem8]
554 def XOR16rm : Im16 <"xor", 0x33, MRMSrcMem >, OpSize; // R16 ^= [mem16]
555 def XOR32rm : Im32 <"xor", 0x33, MRMSrcMem >; // R32 ^= [mem32]
557 def XOR8ri : Ii8 <0x80, MRM6r, (ops R8:$dst, R8:$src1, i8imm:$src2), "xor $dst, $src2">;
558 def XOR16ri : Ii16 <0x81, MRM6r, (ops R16:$dst, R16:$src1, i16imm:$src2), "xor $dst, $src2">, OpSize;
559 def XOR32ri : Ii32 <0x81, MRM6r, (ops R32:$dst, R32:$src1, i32imm:$src2), "xor $dst, $src2">;
560 def XOR8mi : Im8i8 <"xor", 0x80, MRM6m >; // [mem8] ^= R8
561 def XOR16mi : Im16i16<"xor", 0x81, MRM6m >, OpSize; // [mem16] ^= R16
562 def XOR32mi : Im32i32<"xor", 0x81, MRM6m >; // [mem32] ^= R32
564 def XOR16ri8 : Ii8<0x83, MRM6r, (ops R16:$dst, R16:$src1, i8imm:$src2),
565 "xor $dst, $src2">, OpSize;
566 def XOR32ri8 : Ii8<0x83, MRM6r, (ops R32:$dst, R32:$src1, i8imm:$src2),
568 def XOR16mi8 : Im16i8<"xor", 0x83, MRM6m >, OpSize; // [mem16] ^= imm8
569 def XOR32mi8 : Im32i8<"xor", 0x83, MRM6m >; // [mem32] ^= imm8
571 // Shift instructions
572 // FIXME: provide shorter instructions when imm8 == 1
573 let Uses = [CL], printImplicitUsesAfter = 1 in {
574 def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src), "shl $dst, %CL">;
575 def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src), "shl $dst, %CL">, OpSize;
576 def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src), "shl $dst, %CL">;
577 def SHL8mCL : Im8 <"shl", 0xD2, MRM4m > ; // [mem8] <<= cl
578 def SHL16mCL : Im16 <"shl", 0xD3, MRM4m >, OpSize; // [mem16] <<= cl
579 def SHL32mCL : Im32 <"shl", 0xD3, MRM4m > ; // [mem32] <<= cl
582 def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
584 def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2),
585 "shl $dst, $src2">, OpSize;
586 def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2),
588 def SHL8mi : Im8i8 <"shl", 0xC0, MRM4m >; // [mem8] <<= imm8
589 def SHL16mi : Im16i8<"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm8
590 def SHL32mi : Im32i8<"shl", 0xC1, MRM4m >; // [mem32] <<= imm8
592 let Uses = [CL], printImplicitUsesAfter = 1 in {
593 def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src), "shr $dst, %CL">;
594 def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src), "shr $dst, %CL">, OpSize;
595 def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src), "shr $dst, %CL">;
596 def SHR8mCL : Im8 <"shr", 0xD2, MRM5m > ; // [mem8] >>= cl
597 def SHR16mCL : Im16 <"shr", 0xD3, MRM5m >, OpSize; // [mem16] >>= cl
598 def SHR32mCL : Im32 <"shr", 0xD3, MRM5m > ; // [mem32] >>= cl
601 def SHR8ri : Ii8 <0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), "shr $dst, $src2">;
602 def SHR16ri : Ii8 <0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2), "shr $dst, $src2">, OpSize;
603 def SHR32ri : Ii8 <0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2), "shr $dst, $src2">;
604 def SHR8mi : Im8i8 <"shr", 0xC0, MRM5m >; // [mem8] >>= imm8
605 def SHR16mi : Im16i8<"shr", 0xC1, MRM5m >, OpSize; // [mem16] >>= imm8
606 def SHR32mi : Im32i8<"shr", 0xC1, MRM5m >; // [mem32] >>= imm8
608 let Uses = [CL], printImplicitUsesAfter = 1 in {
609 def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src), "sar $dst, %CL">;
610 def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src), "sar $dst, %CL">, OpSize;
611 def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src), "sar $dst, %CL">;
612 def SAR8mCL : Im8 <"sar", 0xD2, MRM7m > ; // [mem8] >>>= cl
613 def SAR16mCL : Im16 <"sar", 0xD3, MRM7m >, OpSize; // [mem16] >>>= cl
614 def SAR32mCL : Im32 <"sar", 0xD3, MRM7m > ; // [mem32] >>>= cl
617 def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2),
619 def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2),
620 "sar $dst, $src2">, OpSize;
621 def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2),
623 def SAR8mi : Im8i8 <"sar", 0xC0, MRM7m >; // [mem8] >>>= imm8
624 def SAR16mi : Im16i8<"sar", 0xC1, MRM7m >, OpSize; // [mem16] >>>= imm8
625 def SAR32mi : Im32i8<"sar", 0xC1, MRM7m >; // [mem32] >>>= imm8
627 let Uses = [CL], printImplicitUsesAfter = 1 in {
628 def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
629 "shld $dst, $src2, %CL">, TB;
630 def SHLD32mrCL : Im32 <"shld", 0xA5, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 cl
631 def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
632 "shrd $dst, $src2, %CL">, TB;
633 def SHRD32mrCL : Im32 <"shrd", 0xAD, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 cl
636 def SHLD32rri8 : Ii8 <0xA4, MRMDestReg, (ops R8:$dst, R8:$src1, i8imm:$src2),
637 "shld $dst, $src2">, TB;
638 def SHLD32mri8 : Im32i8<"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8
639 def SHRD32rri8 : Ii8 <0xAC, MRMDestReg, (ops R16:$dst, R16:$src1, i8imm:$src2),
640 "shrd $dst, $src2">, TB;
641 def SHRD32mri8 : Im32i8<"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 imm8
645 def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), "add $dst, $src2">;
646 def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), "add $dst, $src2">, OpSize;
647 def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "add $dst, $src2">;
648 def ADD8mr : Im8 <"add", 0x00, MRMDestMem>; // [mem8] += R8
649 def ADD16mr : Im16 <"add", 0x01, MRMDestMem>, OpSize; // [mem16] += R16
650 def ADD32mr : Im32 <"add", 0x01, MRMDestMem>; // [mem32] += R32
651 def ADD8rm : Im8 <"add", 0x02, MRMSrcMem >; // R8 += [mem8]
652 def ADD16rm : Im16 <"add", 0x03, MRMSrcMem >, OpSize; // R16 += [mem16]
653 def ADD32rm : Im32 <"add", 0x03, MRMSrcMem >; // R32 += [mem32]
655 def ADD8ri : Ii8 <0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2), "add $dst, $src2">;
656 def ADD16ri : Ii16 <0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2), "add $dst, $src2">, OpSize;
657 def ADD32ri : Ii32 <0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), "add $dst, $src2">;
658 def ADD8mi : Im8i8 <"add", 0x80, MRM0m >; // [mem8] += I8
659 def ADD16mi : Im16i16<"add", 0x81, MRM0m >, OpSize; // [mem16] += I16
660 def ADD32mi : Im32i32<"add", 0x81, MRM0m >; // [mem32] += I32
662 def ADD16ri8 : Ii8 <0x83, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2), "add $dst, $src2">, OpSize;
663 def ADD32ri8 : Ii8 <0x83, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2), "add $dst, $src2">;
664 def ADD16mi8 : Im16i8<"add", 0x83, MRM0m >, OpSize; // [mem16] += I8
665 def ADD32mi8 : Im32i8<"add", 0x83, MRM0m >; // [mem32] += I8
667 def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "adc $dst, $src2">;
668 def ADC32mr : Im32 <"adc", 0x11, MRMDestMem>; // [mem32] += R32+Carry
669 def ADC32rm : Im32 <"adc", 0x13, MRMSrcMem >; // R32 += [mem32]+Carry
670 def ADC32ri : Ii32 <0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2), "adc $dst, $src2">;
671 def ADC32ri8 : Ii8 <0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2), "adc $dst, $src2">;
672 def ADC32mi : Im32i32<"adc", 0x81, MRM2m >; // [mem32] += I32+Carry
673 def ADC32mi8 : Im32i8 <"adc", 0x83, MRM2m >; // [mem32] += I8+Carry
675 def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), "sub $dst, $src2">;
676 def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), "sub $dst, $src2">, OpSize;
677 def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "sub $dst, $src2">;
678 def SUB8mr : Im8 <"sub", 0x28, MRMDestMem>; // [mem8] -= R8
679 def SUB16mr : Im16 <"sub", 0x29, MRMDestMem>, OpSize; // [mem16] -= R16
680 def SUB32mr : Im32 <"sub", 0x29, MRMDestMem>; // [mem32] -= R32
681 def SUB8rm : Im8 <"sub", 0x2A, MRMSrcMem >; // R8 -= [mem8]
682 def SUB16rm : Im16 <"sub", 0x2B, MRMSrcMem >, OpSize; // R16 -= [mem16]
683 def SUB32rm : Im32 <"sub", 0x2B, MRMSrcMem >; // R32 -= [mem32]
685 def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2),
687 def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2),
688 "sub $dst, $src2">, OpSize;
689 def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2),
691 def SUB8mi : Im8i8 <"sub", 0x80, MRM5m >; // [mem8] -= I8
692 def SUB16mi : Im16i16<"sub", 0x81, MRM5m >, OpSize; // [mem16] -= I16
693 def SUB32mi : Im32i32<"sub", 0x81, MRM5m >; // [mem32] -= I32
695 def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2),
696 "sub $dst, $src2">, OpSize;
697 def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2),
699 def SUB16mi8 : Im16i8<"sub", 0x83, MRM5m >, OpSize; // [mem16] -= I8
700 def SUB32mi8 : Im32i8<"sub", 0x83, MRM5m >; // [mem32] -= I8
702 def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
704 def SBB32mr : Im32<"sbb", 0x19, MRMDestMem>; // [mem32] -= R32+Carry
705 def SBB32rm : Im32<"sbb", 0x1B, MRMSrcMem >; // R32 -= [mem32]+Carry
706 def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2),
708 def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2),
710 def SBB32mi : Im32i32<"sbb", 0x81, MRM3m>; // [mem32] -= I32+Carry
711 def SBB32mi8 : Im32i8 <"sbb", 0x83, MRM3m>; // [mem32] -= I8+Carry
713 def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), "imul $dst, $src2">, TB, OpSize;
714 def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), "imul $dst, $src2">, TB;
715 def IMUL16rm : Im16 <"imul", 0xAF, MRMSrcMem>, TB, OpSize;
716 def IMUL32rm : Im32 <"imul", 0xAF, MRMSrcMem>, TB ;
718 } // end Two Address instructions
720 // These are suprisingly enough not two address instructions!
721 def IMUL16rri : Ii16<0x69, MRMSrcReg, (ops R16:$dst, R16:$src1, i16imm:$src2),
722 "imul $dst, $src1, $src2">, OpSize; // R16 = R16*I16
723 def IMUL32rri : Ii32<0x69, MRMSrcReg, (ops R32:$dst, R32:$src1, i32imm:$src2),
724 "imul $dst, $src1, $src2">; // R32 = R32*I32
725 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, (ops R16:$dst, R16:$src1, i8imm:$src2),
726 "imul $dst, $src1, $src2">, OpSize; // R16 = R16*I8
727 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, (ops R32:$dst, R32:$src1, i8imm:$src2),
728 "imul $dst, $src1, $src2">; // R32 = R32*I8
729 def IMUL16rmi : Im16i16<"imul",0x69, MRMSrcMem>, OpSize; // R16 = [mem16]*I16
730 def IMUL32rmi : Im32i32<"imul",0x69, MRMSrcMem>; // R32 = [mem32]*I32
731 def IMUL16rmi8 : Im16i8<"imul", 0x6B, MRMSrcMem>, OpSize; // R16 = [mem16]*I8
732 def IMUL32rmi8 : Im32i8<"imul", 0x6B, MRMSrcMem>; // R32 = [mem32]*I8
734 //===----------------------------------------------------------------------===//
735 // Test instructions are just like AND, except they don't generate a result.
736 def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2),
737 "test $src1, $src2">;
738 def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2),
739 "test $src1, $src2">, OpSize;
740 def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2),
741 "test $src1, $src2">;
742 def TEST8mr : Im8 <"test", 0x84, MRMDestMem>; // flags = [mem8] & R8
743 def TEST16mr : Im16 <"test", 0x85, MRMDestMem>, OpSize; // flags = [mem16] & R16
744 def TEST32mr : Im32 <"test", 0x85, MRMDestMem>; // flags = [mem32] & R32
745 def TEST8rm : Im8 <"test", 0x84, MRMSrcMem >; // flags = R8 & [mem8]
746 def TEST16rm : Im16 <"test", 0x85, MRMSrcMem >, OpSize; // flags = R16 & [mem16]
747 def TEST32rm : Im32 <"test", 0x85, MRMSrcMem >; // flags = R32 & [mem32]
749 def TEST8ri : Ii8 <0xF6, MRM0r, (ops R8:$dst, i8imm:$src),
750 "test $dst, $src">; // flags = R8 & imm8
751 def TEST16ri : Ii16 <0xF7, MRM0r, (ops R16:$dst, i16imm:$src),
752 "test $dst, $src">, OpSize; // flags = R16 & imm16
753 def TEST32ri : Ii32 <0xF7, MRM0r, (ops R32:$dst, i32imm:$src),
754 "test $dst, $src">; // flags = R32 & imm32
755 def TEST8mi : Im8i8 <"test", 0xF6, MRM0m >; // flags = [mem8] & imm8
756 def TEST16mi : Im16i16<"test", 0xF7, MRM0m >, OpSize; // flags = [mem16] & imm16
757 def TEST32mi : Im32i32<"test", 0xF7, MRM0m >; // flags = [mem32] & imm32
761 // Condition code ops, incl. set if equal/not equal/...
762 def SAHF : I<0x9E, RawFrm, (ops), "sahf">, Imp<[AH],[]>; // flags = AH
763 def LAHF : I<0x9F, RawFrm, (ops), "lahf">, Imp<[],[AH]>; // AH = flags
765 def SETBr : I<0x92, MRM0r, (ops R8:$dst), "setb $dst">, TB; // R8 = < unsign
766 def SETBm : Im8<"setb" , 0x92, MRM0m>, TB; // [mem8] = < unsign
767 def SETAEr : I<0x93, MRM0r, (ops R8:$dst), "setae $dst">, TB; // R8 = >= unsign
768 def SETAEm : Im8<"setae", 0x93, MRM0m>, TB; // [mem8] = >= unsign
769 def SETEr : I<0x94, MRM0r, (ops R8:$dst), "sete $dst">, TB; // R8 = ==
770 def SETEm : Im8<"sete" , 0x94, MRM0m>, TB; // [mem8] = ==
771 def SETNEr : I<0x95, MRM0r, (ops R8:$dst), "setne $dst">, TB; // R8 = !=
772 def SETNEm : Im8<"setne", 0x95, MRM0m>, TB; // [mem8] = !=
773 def SETBEr : I<0x96, MRM0r, (ops R8:$dst), "setbe $dst">, TB; // R8 = <= unsign
774 def SETBEm : Im8<"setbe", 0x96, MRM0m>, TB; // [mem8] = <= unsign
775 def SETAr : I<0x97, MRM0r, (ops R8:$dst), "seta $dst">, TB; // R8 = > signed
776 def SETAm : Im8<"seta" , 0x97, MRM0m>, TB; // [mem8] = > signed
777 def SETSr : I<0x98, MRM0r, (ops R8:$dst), "sets $dst">, TB; // R8 = <sign bit>
778 def SETSm : Im8<"sets" , 0x98, MRM0m>, TB; // [mem8] = <sign bit>
779 def SETNSr : I<0x99, MRM0r, (ops R8:$dst), "setns $dst">, TB; // R8 = !<sign bit>
780 def SETNSm : Im8<"setns", 0x99, MRM0m>, TB; // [mem8] = !<sign bit>
781 def SETPr : I<0x9A, MRM0r, (ops R8:$dst), "setp $dst">, TB; // R8 = parity
782 def SETPm : Im8<"setp" , 0x9A, MRM0m>, TB; // [mem8] = parity
783 def SETLr : I<0x9C, MRM0r, (ops R8:$dst), "setl $dst">, TB; // R8 = < signed
784 def SETLm : Im8<"setl" , 0x9C, MRM0m>, TB; // [mem8] = < signed
785 def SETGEr : I<0x9D, MRM0r, (ops R8:$dst), "setge $dst">, TB; // R8 = >= signed
786 def SETGEm : Im8<"setge", 0x9D, MRM0m>, TB; // [mem8] = >= signed
787 def SETLEr : I<0x9E, MRM0r, (ops R8:$dst), "setle $dst">, TB; // R8 = <= signed
788 def SETLEm : Im8<"setle", 0x9E, MRM0m>, TB; // [mem8] = <= signed
789 def SETGr : I<0x9F, MRM0r, (ops R8:$dst), "setg $dst">, TB; // R8 = < signed
790 def SETGm : Im8<"setg" , 0x9F, MRM0m>, TB; // [mem8] = < signed
792 // Integer comparisons
793 def CMP8rr : I<0x38, MRMDestReg, (ops R8 :$src1, R8 :$src2), "cmp $src1, $src2">;
794 def CMP16rr : I<0x39, MRMDestReg, (ops R16:$src1, R16:$src2), "cmp $src1, $src2">, OpSize;
795 def CMP32rr : I<0x39, MRMDestReg, (ops R32:$src1, R32:$src2), "cmp $src1, $src2">;
796 def CMP8mr : Im8 <"cmp", 0x38, MRMDestMem>; // compare [mem8], R8
797 def CMP16mr : Im16 <"cmp", 0x39, MRMDestMem>, OpSize; // compare [mem16], R16
798 def CMP32mr : Im32 <"cmp", 0x39, MRMDestMem>; // compare [mem32], R32
799 def CMP8rm : Im8 <"cmp", 0x3A, MRMSrcMem >; // compare R8, [mem8]
800 def CMP16rm : Im16 <"cmp", 0x3B, MRMSrcMem >, OpSize; // compare R16, [mem16]
801 def CMP32rm : Im32 <"cmp", 0x3B, MRMSrcMem >; // compare R32, [mem32]
802 def CMP8ri : Ii8 <0x80, MRM7r, (ops R16:$dst, i8imm:$src), "cmp $dst, $src">;
803 def CMP16ri : Ii16 <0x81, MRM7r, (ops R16:$dst, i16imm:$src), "cmp $dst, $src">, OpSize;
804 def CMP32ri : Ii32 <0x81, MRM7r, (ops R32:$dst, i32imm:$src), "cmp $dst, $src">;
805 def CMP8mi : Im8i8 <"cmp", 0x80, MRM7m >; // compare [mem8], imm8
806 def CMP16mi : Im16i16<"cmp", 0x81, MRM7m >, OpSize; // compare [mem16], imm16
807 def CMP32mi : Im32i32<"cmp", 0x81, MRM7m >; // compare [mem32], imm32
809 // Sign/Zero extenders
810 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src), "movsx $dst, $src">, TB, OpSize;
811 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src), "movsx $dst, $src">, TB;
812 def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src), "movsx $dst, $src">, TB;
813 def MOVSX16rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB, OpSize; // R16 = signext([mem8])
814 def MOVSX32rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB; // R32 = signext([mem8])
815 def MOVSX32rm16: Im16<"movsx", 0xBF, MRMSrcMem>, TB; // R32 = signext([mem16])
817 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src), "movzx $dst, $src">, TB, OpSize;
818 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src), "movzx $dst, $src">, TB;
819 def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src), "movzx $dst, $src">, TB;
820 def MOVZX16rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB, OpSize; // R16 = zeroext([mem8])
821 def MOVZX32rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB; // R32 = zeroext([mem8])
822 def MOVZX32rm16: Im16<"movzx", 0xB7, MRMSrcMem>, TB; // R32 = zeroext([mem16])
825 //===----------------------------------------------------------------------===//
826 // Floating point support
827 //===----------------------------------------------------------------------===//
829 // FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP'
831 // Floating point instruction templates
832 class FPInst<string n, bits<8> o, Format F, FPFormat fp, MemType m, ImmType i>
833 : X86Inst<n, o, F, m, i> { let FPForm = fp; let FPFormBits = FPForm.Value; }
835 class FPI<bits<8> o, Format F, FPFormat fp> : FPInst<"", o, F, fp, NoMem, NoImm>;
837 class FPIM<string n, bits<8> o, Format F, FPFormat fp, MemType m> : FPInst<n, o, F, fp, m, NoImm>;
839 class FPI16m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem16>;
840 class FPI32m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem32>;
841 class FPI64m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem64>;
842 class FPI80m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem80>;
844 // Pseudo instructions for floating point. We use these pseudo instructions
845 // because they can be expanded by the fp spackifier into one of many different
846 // forms of instructions for doing these operations. Until the stackifier runs,
847 // we prefer to be abstract.
848 def FpMOV : FPI<0, Pseudo, SpecialFP>; // f1 = fmov f2
849 def FpADD : FPI<0, Pseudo, TwoArgFP>; // f1 = fadd f2, f3
850 def FpSUB : FPI<0, Pseudo, TwoArgFP>; // f1 = fsub f2, f3
851 def FpMUL : FPI<0, Pseudo, TwoArgFP>; // f1 = fmul f2, f3
852 def FpDIV : FPI<0, Pseudo, TwoArgFP>; // f1 = fdiv f2, f3
854 def FpGETRESULT : FPI<0, Pseudo, SpecialFP>; // FPR = ST(0)
855 def FpSETRESULT : FPI<0, Pseudo, SpecialFP>; // ST(0) = FPR
857 // FADD reg, mem: Before stackification, these are represented by: R1 = FADD* R2, [mem]
858 def FADD32m : FPI32m<"fadd", 0xD8, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32real]
859 def FADD64m : FPI64m<"fadd", 0xDC, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem64real]
860 def FIADD16m : FPI16m<"fiadd", 0xDE, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem16int]
861 def FIADD32m : FPI32m<"fiadd", 0xDA, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32int]
863 // FMUL reg, mem: Before stackification, these are represented by: R1 = FMUL* R2, [mem]
864 def FMUL32m : FPI32m<"fmul", 0xD8, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem32real]
865 def FMUL64m : FPI64m<"fmul", 0xDC, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem64real]
866 def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem16int]
867 def FIMUL32m : FPI32m<"fimul", 0xDA, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem32int]
869 // FSUB reg, mem: Before stackification, these are represented by: R1 = FSUB* R2, [mem]
870 def FSUB32m : FPI32m<"fsub", 0xD8, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem32real]
871 def FSUB64m : FPI64m<"fsub", 0xDC, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem64real]
872 def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem16int]
873 def FISUB32m : FPI32m<"fisub", 0xDA, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem32int]
875 // FSUBR reg, mem: Before stackification, these are represented by: R1 = FSUBR* R2, [mem]
876 // Note that the order of operands does not reflect the operation being performed.
877 def FSUBR32m : FPI32m<"fsubr", 0xD8, MRM5m, OneArgFPRW>; // ST(0) = [mem32real] - ST(0)
878 def FSUBR64m : FPI64m<"fsubr", 0xDC, MRM5m, OneArgFPRW>; // ST(0) = [mem64real] - ST(0)
879 def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>; // ST(0) = [mem16int] - ST(0)
880 def FISUBR32m : FPI32m<"fisubr", 0xDA, MRM5m, OneArgFPRW>; // ST(0) = [mem32int] - ST(0)
882 // FDIV reg, mem: Before stackification, these are represented by: R1 = FDIV* R2, [mem]
883 def FDIV32m : FPI32m<"fdiv", 0xD8, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem32real]
884 def FDIV64m : FPI64m<"fdiv", 0xDC, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem64real]
885 def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem16int]
886 def FIDIV32m : FPI32m<"fidiv", 0xDA, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem32int]
888 // FDIVR reg, mem: Before stackification, these are represented by: R1 = FDIVR* R2, [mem]
889 // Note that the order of operands does not reflect the operation being performed.
890 def FDIVR32m : FPI32m<"fdivr", 0xD8, MRM7m, OneArgFPRW>; // ST(0) = [mem32real] / ST(0)
891 def FDIVR64m : FPI64m<"fdivr", 0xDC, MRM7m, OneArgFPRW>; // ST(0) = [mem64real] / ST(0)
892 def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>; // ST(0) = [mem16int] / ST(0)
893 def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>; // ST(0) = [mem32int] / ST(0)
896 // Floating point cmovs...
897 let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in {
898 def FCMOVB : FPI<0xC0, AddRegFrm, CondMovFP>, DA, // fcmovb ST(i) -> ST(0)
899 II<(ops RST:$op), "fcmovb %ST(0), $op">;
900 def FCMOVBE : FPI<0xD0, AddRegFrm, CondMovFP>, DA, // fcmovbe ST(i) -> ST(0)
901 II<(ops RST:$op), "fcmovbe %ST(0), $op">;
902 def FCMOVE : FPI<0xC8, AddRegFrm, CondMovFP>, DA, // fcmove ST(i) -> ST(0)
903 II<(ops RST:$op), "fcmove %ST(0), $op">;
904 def FCMOVAE : FPI<0xC0, AddRegFrm, CondMovFP>, DB, // fcmovae ST(i) -> ST(0)
905 II<(ops RST:$op), "fcmovae %ST(0), $op">;
906 def FCMOVA : FPI<0xD0, AddRegFrm, CondMovFP>, DB, // fcmova ST(i) -> ST(0)
907 II<(ops RST:$op), "fcmova %ST(0), $op">;
908 def FCMOVNE : FPI<0xC8, AddRegFrm, CondMovFP>, DB, // fcmovne ST(i) -> ST(0)
909 II<(ops RST:$op), "fcmovne %ST(0), $op">;
912 // Floating point loads & stores...
914 def FLDrr : FPI<0xC0, AddRegFrm, NotFP>, D9; // push(ST(i))
915 def FLD32m : FPI32m <"fld" , 0xD9, MRM0m , ZeroArgFP>; // load float
916 def FLD64m : FPI64m <"fld" , 0xDD, MRM0m , ZeroArgFP>; // load double
917 def FLD80m : FPI80m <"fld" , 0xDB, MRM5m , ZeroArgFP>; // load extended
918 def FILD16m : FPI16m <"fild" , 0xDF, MRM0m , ZeroArgFP>; // load signed short
919 def FILD32m : FPI32m <"fild" , 0xDB, MRM0m , ZeroArgFP>; // load signed int
920 def FILD64m : FPI64m <"fild" , 0xDF, MRM5m , ZeroArgFP>; // load signed long
923 def FSTrr : FPI<0xD0, AddRegFrm, NotFP >, DD; // ST(i) = ST(0)
925 def FSTPrr : FPI<0xD8, AddRegFrm, NotFP >, DD; // ST(i) = ST(0), pop
926 def FST32m : FPI32m <"fst" , 0xD9, MRM2m , OneArgFP>; // store float
927 def FST64m : FPI64m <"fst" , 0xDD, MRM2m , OneArgFP>; // store double
928 def FSTP32m : FPI32m <"fstp", 0xD9, MRM3m , OneArgFP>; // store float, pop
929 def FSTP64m : FPI64m <"fstp", 0xDD, MRM3m , OneArgFP>; // store double, pop
930 def FSTP80m : FPI80m <"fstp", 0xDB, MRM7m , OneArgFP>; // store extended, pop
932 def FIST16m : FPI16m <"fist", 0xDF, MRM2m , OneArgFP>; // store signed short
933 def FIST32m : FPI32m <"fist", 0xDB, MRM2m , OneArgFP>; // store signed int
934 def FISTP16m : FPI16m <"fistp", 0xDF, MRM3m , NotFP >; // store signed short, pop
935 def FISTP32m : FPI32m <"fistp", 0xDB, MRM3m , NotFP >; // store signed int, pop
936 def FISTP64m : FPI64m <"fistpll", 0xDF, MRM7m , OneArgFP>; // store signed long, pop
938 def FXCH : FPI<0xC8, AddRegFrm, NotFP>,
939 II<(ops RST:$op), "fxch $op">, D9; // fxch ST(i), ST(0)
941 // Floating point constant loads...
942 def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP>, D9,
944 def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP>, D9,
948 // Unary operations...
949 def FCHS : FPI<0xE0, RawFrm, OneArgFPRW>, // f1 = fchs f2
950 II<(ops), "fchs">, D9;
951 def FTST : FPI<0xE4, RawFrm, OneArgFP>, // ftst ST(0)
952 II<(ops), "ftst">, D9;
954 // Binary arithmetic operations...
955 class FPST0rInst<bits<8> o, dag ops, string asm> : I<o, AddRegFrm, ops, asm>, D8 {
956 list<Register> Uses = [ST0];
957 list<Register> Defs = [ST0];
959 class FPrST0Inst<bits<8> o, dag ops, string asm> : I<o, AddRegFrm, ops, asm>, DC {
960 list<Register> Uses = [ST0];
962 class FPrST0PInst<bits<8> o, dag ops, string asm> : I<o, AddRegFrm, ops, asm>, DE {
963 list<Register> Uses = [ST0];
966 def FADDST0r : FPST0rInst <0xC0, (ops RST:$op), "fadd $op">;
967 def FADDrST0 : FPrST0Inst <0xC0, (ops RST:$op), "fadd $op, %ST(0)">;
968 def FADDPrST0 : FPrST0PInst<0xC0, (ops RST:$op), "faddp $op">;
970 def FSUBRST0r : FPST0rInst <0xE8, (ops RST:$op), "fsubr $op">;
971 def FSUBrST0 : FPrST0Inst <0xE8, (ops RST:$op), "fsub $op, %ST(0)">;
972 def FSUBPrST0 : FPrST0PInst<0xE8, (ops RST:$op), "fsubp $op">;
974 def FSUBST0r : FPST0rInst <0xE0, (ops RST:$op), "fsub $op">;
975 def FSUBRrST0 : FPrST0Inst <0xE0, (ops RST:$op), "fsubr $op, %ST(0)">;
976 def FSUBRPrST0 : FPrST0PInst<0xE0, (ops RST:$op), "fsubrp $op">;
978 def FMULST0r : FPST0rInst <0xC8, (ops RST:$op), "fmul $op">;
979 def FMULrST0 : FPrST0Inst <0xC8, (ops RST:$op), "fmul $op, %ST(0)">;
980 def FMULPrST0 : FPrST0PInst<0xC8, (ops RST:$op), "fmulp $op">;
982 def FDIVRST0r : FPST0rInst <0xF8, (ops RST:$op), "fdivr $op">;
983 def FDIVrST0 : FPrST0Inst <0xF8, (ops RST:$op), "fdiv $op, %ST(0)">;
984 def FDIVPrST0 : FPrST0PInst<0xF8, (ops RST:$op), "fdivp $op">;
986 def FDIVST0r : FPST0rInst <0xF0, (ops RST:$op), "fdiv $op">; // ST(0) = ST(0) / ST(i)
987 def FDIVRrST0 : FPrST0Inst <0xF0, (ops RST:$op), "fdivr $op, %ST(0)">; // ST(i) = ST(0) / ST(i)
988 def FDIVRPrST0 : FPrST0PInst<0xF0, (ops RST:$op), "fdivrp $op">; // ST(i) = ST(0) / ST(i), pop
990 // Floating point compares
991 def FUCOMr : FPI<0xE0, AddRegFrm, CompareFP>, // FPSW = compare ST(0) with ST(i)
992 II<(ops RST:$reg), "fucom $reg">, DD, Imp<[ST0],[]>;
993 def FUCOMPr : I<0xE8, AddRegFrm, (ops RST:$reg),
994 "fucomp $reg">, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
995 def FUCOMPPr : I<0xE9, RawFrm, (ops),
996 "fucompp">, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop
998 def FUCOMIr : FPI<0xE8, AddRegFrm, CompareFP>, // CC = compare ST(0) with ST(i)
999 II<(ops RST:$reg), "fucomi %ST(0), $reg">, DB, Imp<[ST0],[]>;
1000 def FUCOMIPr : I<0xE8, AddRegFrm, (ops RST:$reg),
1001 "fucomip %ST(0), $reg">, DF, Imp<[ST0],[]>; // CC = compare ST(0) with ST(i), pop
1004 // Floating point flag ops
1005 def FNSTSW8r : I<0xE0, RawFrm, (ops), "fnstsw">, DF, Imp<[],[AX]>; // AX = fp flags
1007 def FNSTCW16m : Im16<"fnstcw", 0xD9, MRM7m>; // [mem16] = X87 control world
1008 def FLDCW16m : Im16<"fldcw" , 0xD9, MRM5m>; // X87 control world = [mem16]