1 //===----------------------------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
79 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
81 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
82 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
83 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
84 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
86 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
128 [SDNPHasChain, SDNPVariadic]>;
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
141 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
142 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
143 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
144 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
147 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
148 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
150 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
151 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
153 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
154 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
155 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
156 SDT_X86SegmentBaseAddress, []>;
158 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
161 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
162 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
164 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
166 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
167 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
169 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
172 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
173 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
174 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
176 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
178 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
181 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
183 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
184 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
186 //===----------------------------------------------------------------------===//
187 // X86 Operand Definitions.
190 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
191 // the index operand of an address, to conform to x86 encoding restrictions.
192 def ptr_rc_nosp : PointerLikeRegClass<1>;
194 // *mem - Operand definitions for the funky X86 addressing mode operands.
196 def X86MemAsmOperand : AsmOperandClass {
200 def X86AbsMemAsmOperand : AsmOperandClass {
202 let SuperClass = X86MemAsmOperand;
204 def X86NoSegMemAsmOperand : AsmOperandClass {
205 let Name = "NoSegMem";
206 let SuperClass = X86MemAsmOperand;
208 class X86MemOperand<string printMethod> : Operand<iPTR> {
209 let PrintMethod = printMethod;
210 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
211 let ParserMatchClass = X86MemAsmOperand;
214 def opaque32mem : X86MemOperand<"printopaquemem">;
215 def opaque48mem : X86MemOperand<"printopaquemem">;
216 def opaque80mem : X86MemOperand<"printopaquemem">;
217 def opaque512mem : X86MemOperand<"printopaquemem">;
219 def i8mem : X86MemOperand<"printi8mem">;
220 def i16mem : X86MemOperand<"printi16mem">;
221 def i32mem : X86MemOperand<"printi32mem">;
222 def i64mem : X86MemOperand<"printi64mem">;
223 def i128mem : X86MemOperand<"printi128mem">;
224 //def i256mem : X86MemOperand<"printi256mem">;
225 def f32mem : X86MemOperand<"printf32mem">;
226 def f64mem : X86MemOperand<"printf64mem">;
227 def f80mem : X86MemOperand<"printf80mem">;
228 def f128mem : X86MemOperand<"printf128mem">;
229 //def f256mem : X86MemOperand<"printf256mem">;
231 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
232 // plain GR64, so that it doesn't potentially require a REX prefix.
233 def i8mem_NOREX : Operand<i64> {
234 let PrintMethod = "printi8mem";
235 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
236 let ParserMatchClass = X86MemAsmOperand;
239 // Special i32mem for addresses of load folding tail calls. These are not
240 // allowed to use callee-saved registers since they must be scheduled
241 // after callee-saved register are popped.
242 def i32mem_TC : Operand<i32> {
243 let PrintMethod = "printi32mem";
244 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
245 let ParserMatchClass = X86MemAsmOperand;
248 def lea32mem : Operand<i32> {
249 let PrintMethod = "printlea32mem";
250 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
251 let ParserMatchClass = X86NoSegMemAsmOperand;
254 let ParserMatchClass = X86AbsMemAsmOperand,
255 PrintMethod = "print_pcrel_imm" in {
256 def i32imm_pcrel : Operand<i32>;
258 def offset8 : Operand<i64>;
259 def offset16 : Operand<i64>;
260 def offset32 : Operand<i64>;
261 def offset64 : Operand<i64>;
263 // Branch targets have OtherVT type and print as pc-relative values.
264 def brtarget : Operand<OtherVT>;
265 def brtarget8 : Operand<OtherVT>;
269 def SSECC : Operand<i8> {
270 let PrintMethod = "printSSECC";
273 def ImmSExt8AsmOperand : AsmOperandClass {
274 let Name = "ImmSExt8";
275 let SuperClass = ImmAsmOperand;
278 // A couple of more descriptive operand definitions.
279 // 16-bits but only 8 bits are significant.
280 def i16i8imm : Operand<i16> {
281 let ParserMatchClass = ImmSExt8AsmOperand;
283 // 32-bits but only 8 bits are significant.
284 def i32i8imm : Operand<i32> {
285 let ParserMatchClass = ImmSExt8AsmOperand;
288 //===----------------------------------------------------------------------===//
289 // X86 Complex Pattern Definitions.
292 // Define X86 specific addressing mode.
293 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
294 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
295 [add, sub, mul, X86mul_imm, shl, or, frameindex],
297 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
298 [tglobaltlsaddr], []>;
300 //===----------------------------------------------------------------------===//
301 // X86 Instruction Predicate Definitions.
302 def HasCMov : Predicate<"Subtarget->hasCMov()">;
303 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
304 def HasMMX : Predicate<"Subtarget->hasMMX()">;
305 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
306 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
307 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
308 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
309 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
310 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
311 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
312 def HasAVX : Predicate<"Subtarget->hasAVX()">;
313 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
314 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
315 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
316 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
317 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
318 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
319 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
320 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
321 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
322 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
323 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
324 "TM.getCodeModel() != CodeModel::Kernel">;
325 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
326 "TM.getCodeModel() == CodeModel::Kernel">;
327 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
328 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
329 def OptForSize : Predicate<"OptForSize">;
330 def OptForSpeed : Predicate<"!OptForSize">;
331 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
332 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
333 def HasAES : Predicate<"Subtarget->hasAES()">;
335 //===----------------------------------------------------------------------===//
336 // X86 Instruction Format Definitions.
339 include "X86InstrFormats.td"
341 //===----------------------------------------------------------------------===//
342 // Pattern fragments...
345 // X86 specific condition code. These correspond to CondCode in
346 // X86InstrInfo.h. They must be kept in synch.
347 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
348 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
349 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
350 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
351 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
352 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
353 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
354 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
355 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
356 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
357 def X86_COND_NO : PatLeaf<(i8 10)>;
358 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
359 def X86_COND_NS : PatLeaf<(i8 12)>;
360 def X86_COND_O : PatLeaf<(i8 13)>;
361 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
362 def X86_COND_S : PatLeaf<(i8 15)>;
364 def immSext8 : PatLeaf<(imm), [{
365 return N->getSExtValue() == (int8_t)N->getSExtValue();
368 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
369 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
371 /// Load patterns: these constraint the match to the right address space.
372 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
373 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
374 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
375 if (PT->getAddressSpace() > 255)
380 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
381 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
382 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
383 return PT->getAddressSpace() == 256;
387 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
388 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
389 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
390 return PT->getAddressSpace() == 257;
395 // Helper fragments for loads.
396 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
397 // known to be 32-bit aligned or better. Ditto for i8 to i16.
398 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
399 LoadSDNode *LD = cast<LoadSDNode>(N);
400 if (const Value *Src = LD->getSrcValue())
401 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
402 if (PT->getAddressSpace() > 255)
404 ISD::LoadExtType ExtType = LD->getExtensionType();
405 if (ExtType == ISD::NON_EXTLOAD)
407 if (ExtType == ISD::EXTLOAD)
408 return LD->getAlignment() >= 2 && !LD->isVolatile();
412 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
413 LoadSDNode *LD = cast<LoadSDNode>(N);
414 if (const Value *Src = LD->getSrcValue())
415 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
416 if (PT->getAddressSpace() > 255)
418 ISD::LoadExtType ExtType = LD->getExtensionType();
419 if (ExtType == ISD::EXTLOAD)
420 return LD->getAlignment() >= 2 && !LD->isVolatile();
424 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
425 LoadSDNode *LD = cast<LoadSDNode>(N);
426 if (const Value *Src = LD->getSrcValue())
427 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
428 if (PT->getAddressSpace() > 255)
430 ISD::LoadExtType ExtType = LD->getExtensionType();
431 if (ExtType == ISD::NON_EXTLOAD)
433 if (ExtType == ISD::EXTLOAD)
434 return LD->getAlignment() >= 4 && !LD->isVolatile();
438 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
439 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
440 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
441 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
442 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
444 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
445 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
446 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
448 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
449 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
450 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
451 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
452 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
453 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
455 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
456 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
457 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
458 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
459 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
460 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
463 // An 'and' node with a single use.
464 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
465 return N->hasOneUse();
467 // An 'srl' node with a single use.
468 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
469 return N->hasOneUse();
471 // An 'trunc' node with a single use.
472 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
473 return N->hasOneUse();
476 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
477 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
478 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
479 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
481 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
482 APInt Mask = APInt::getAllOnesValue(BitWidth);
483 APInt KnownZero0, KnownOne0;
484 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
485 APInt KnownZero1, KnownOne1;
486 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
487 return (~KnownZero0 & ~KnownZero1) == 0;
490 // 'shld' and 'shrd' instruction patterns. Note that even though these have
491 // the srl and shl in their patterns, the C++ code must still check for them,
492 // because predicates are tested before children nodes are explored.
494 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
495 (or (srl node:$src1, node:$amt1),
496 (shl node:$src2, node:$amt2)), [{
497 assert(N->getOpcode() == ISD::OR);
498 return N->getOperand(0).getOpcode() == ISD::SRL &&
499 N->getOperand(1).getOpcode() == ISD::SHL &&
500 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
501 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
502 N->getOperand(0).getConstantOperandVal(1) ==
503 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
506 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
507 (or (shl node:$src1, node:$amt1),
508 (srl node:$src2, node:$amt2)), [{
509 assert(N->getOpcode() == ISD::OR);
510 return N->getOperand(0).getOpcode() == ISD::SHL &&
511 N->getOperand(1).getOpcode() == ISD::SRL &&
512 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
513 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
514 N->getOperand(0).getConstantOperandVal(1) ==
515 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
518 //===----------------------------------------------------------------------===//
519 // Instruction list...
522 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
523 // a stack adjustment and the codegen must know that they may modify the stack
524 // pointer before prolog-epilog rewriting occurs.
525 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
526 // sub / add which can clobber EFLAGS.
527 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
528 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
530 [(X86callseq_start timm:$amt)]>,
531 Requires<[In32BitMode]>;
532 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
534 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
535 Requires<[In32BitMode]>;
538 // x86-64 va_start lowering magic.
539 let usesCustomInserter = 1 in {
540 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
543 i64imm:$regsavefi, i64imm:$offset,
545 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
546 [(X86vastart_save_xmm_regs GR8:$al,
550 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
551 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
552 // one go. Touching the stack at 4K increments is necessary to ensure that the
553 // guard pages used by the OS virtual memory manager are allocated in correct
555 // The main point of having separate instruction are extra unmodelled effects
556 // (compared to ordinary calls) like stack pointer change.
558 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
559 "# dynamic stack allocation",
564 let neverHasSideEffects = 1 in {
565 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
566 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
567 "nop{w}\t$zero", []>, TB, OpSize;
568 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
569 "nop{l}\t$zero", []>, TB;
573 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
574 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
575 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
576 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
578 // PIC base construction. This expands to code that looks like this:
581 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
582 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
585 //===----------------------------------------------------------------------===//
586 // Control Flow Instructions.
589 // Return instructions.
590 let isTerminator = 1, isReturn = 1, isBarrier = 1,
591 hasCtrlDep = 1, FPForm = SpecialFP in {
592 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
595 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
597 [(X86retflag timm:$amt)]>;
598 def LRET : I <0xCB, RawFrm, (outs), (ins),
600 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
604 // Unconditional branches.
605 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
606 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
607 "jmp\t$dst", [(br bb:$dst)]>;
608 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
612 // Conditional Branches.
613 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
614 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
615 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
616 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
617 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
621 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
622 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
623 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
624 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
625 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
626 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
627 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
628 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
629 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
630 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
631 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
632 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
633 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
634 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
635 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
636 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
638 // FIXME: What about the CX/RCX versions of this instruction?
639 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
640 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
645 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
646 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
647 [(brind GR32:$dst)]>;
648 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
649 [(brind (loadi32 addr:$dst))]>;
651 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
652 (ins i16imm:$seg, i16imm:$off),
653 "ljmp{w}\t$seg, $off", []>, OpSize;
654 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
655 (ins i16imm:$seg, i32imm:$off),
656 "ljmp{l}\t$seg, $off", []>;
658 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
659 "ljmp{w}\t{*}$dst", []>, OpSize;
660 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
661 "ljmp{l}\t{*}$dst", []>;
667 def LOOP : I<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
668 def LOOPE : I<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
669 def LOOPNE : I<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
671 //===----------------------------------------------------------------------===//
672 // Call Instructions...
675 // All calls clobber the non-callee saved registers. ESP is marked as
676 // a use to prevent stack-pointer assignments that appear immediately
677 // before calls from potentially appearing dead. Uses for argument
678 // registers are added manually.
679 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
680 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
681 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
682 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
684 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
685 (outs), (ins i32imm_pcrel:$dst,variable_ops),
687 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
688 "call\t{*}$dst", [(X86call GR32:$dst)]>;
689 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
690 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
692 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
693 (ins i16imm:$seg, i16imm:$off),
694 "lcall{w}\t$seg, $off", []>, OpSize;
695 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
696 (ins i16imm:$seg, i32imm:$off),
697 "lcall{l}\t$seg, $off", []>;
699 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
700 "lcall{w}\t{*}$dst", []>, OpSize;
701 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
702 "lcall{l}\t{*}$dst", []>;
705 // Constructing a stack frame.
707 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
708 "enter\t$len, $lvl", []>;
712 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
713 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
714 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
715 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
716 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
718 def TCRETURNdi : I<0, Pseudo, (outs),
719 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
720 "#TC_RETURN $dst $offset", []>;
721 def TCRETURNri : I<0, Pseudo, (outs),
722 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
723 "#TC_RETURN $dst $offset", []>;
724 def TCRETURNmi : I<0, Pseudo, (outs),
725 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
726 "#TC_RETURN $dst $offset", []>;
728 // FIXME: The should be pseudo instructions that are lowered when going to
730 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
731 (ins i32imm_pcrel:$dst, variable_ops),
732 "jmp\t$dst # TAILCALL",
734 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
735 "jmp{l}\t{*}$dst # TAILCALL",
737 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
738 "jmp{l}\t{*}$dst # TAILCALL", []>;
741 //===----------------------------------------------------------------------===//
742 // Miscellaneous Instructions...
744 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
745 def LEAVE : I<0xC9, RawFrm,
746 (outs), (ins), "leave", []>;
748 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
749 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
750 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
751 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
752 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
753 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
754 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
755 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
757 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
759 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
761 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
762 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
764 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
766 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
767 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
770 let mayStore = 1 in {
771 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
773 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
774 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
776 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
778 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
779 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
783 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
784 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
785 "push{l}\t$imm", []>;
786 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
787 "push{l}\t$imm", []>;
788 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
789 "push{l}\t$imm", []>;
792 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
793 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
794 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
796 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
797 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
798 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
801 let isTwoAddress = 1 in // GR32 = bswap GR32
802 def BSWAP32r : I<0xC8, AddRegFrm,
803 (outs GR32:$dst), (ins GR32:$src),
805 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
808 // Bit scan instructions.
809 let Defs = [EFLAGS] in {
810 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
811 "bsf{w}\t{$src, $dst|$dst, $src}",
812 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB;
813 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
814 "bsf{w}\t{$src, $dst|$dst, $src}",
815 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB;
816 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
817 "bsf{l}\t{$src, $dst|$dst, $src}",
818 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
819 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
820 "bsf{l}\t{$src, $dst|$dst, $src}",
821 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
823 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
824 "bsr{w}\t{$src, $dst|$dst, $src}",
825 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB;
826 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
827 "bsr{w}\t{$src, $dst|$dst, $src}",
828 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB;
829 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
830 "bsr{l}\t{$src, $dst|$dst, $src}",
831 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
832 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
833 "bsr{l}\t{$src, $dst|$dst, $src}",
834 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
837 let neverHasSideEffects = 1 in
838 def LEA16r : I<0x8D, MRMSrcMem,
839 (outs GR16:$dst), (ins lea32mem:$src),
840 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
841 let isReMaterializable = 1 in
842 def LEA32r : I<0x8D, MRMSrcMem,
843 (outs GR32:$dst), (ins lea32mem:$src),
844 "lea{l}\t{$src|$dst}, {$dst|$src}",
845 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
847 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
848 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
849 [(X86rep_movs i8)]>, REP;
850 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
851 [(X86rep_movs i16)]>, REP, OpSize;
852 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
853 [(X86rep_movs i32)]>, REP;
856 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
857 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
858 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
859 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
860 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
863 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
864 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
865 [(X86rep_stos i8)]>, REP;
866 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
867 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
868 [(X86rep_stos i16)]>, REP, OpSize;
869 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
870 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
871 [(X86rep_stos i32)]>, REP;
873 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
874 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
875 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
876 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
877 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
878 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
879 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
881 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
882 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
883 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
885 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
886 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
887 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
889 let Defs = [RAX, RDX] in
890 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
893 let Defs = [RAX, RCX, RDX] in
894 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
896 let isBarrier = 1, hasCtrlDep = 1 in {
897 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
900 def SYSCALL : I<0x05, RawFrm,
901 (outs), (ins), "syscall", []>, TB;
902 def SYSRET : I<0x07, RawFrm,
903 (outs), (ins), "sysret", []>, TB;
904 def SYSENTER : I<0x34, RawFrm,
905 (outs), (ins), "sysenter", []>, TB;
906 def SYSEXIT : I<0x35, RawFrm,
907 (outs), (ins), "sysexit", []>, TB;
909 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
912 //===----------------------------------------------------------------------===//
913 // Input/Output Instructions...
915 let Defs = [AL], Uses = [DX] in
916 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
917 "in{b}\t{%dx, %al|%AL, %DX}", []>;
918 let Defs = [AX], Uses = [DX] in
919 def IN16rr : I<0xED, RawFrm, (outs), (ins),
920 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
921 let Defs = [EAX], Uses = [DX] in
922 def IN32rr : I<0xED, RawFrm, (outs), (ins),
923 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
926 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
927 "in{b}\t{$port, %al|%AL, $port}", []>;
929 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
930 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
932 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
933 "in{l}\t{$port, %eax|%EAX, $port}", []>;
935 let Uses = [DX, AL] in
936 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
937 "out{b}\t{%al, %dx|%DX, %AL}", []>;
938 let Uses = [DX, AX] in
939 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
940 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
941 let Uses = [DX, EAX] in
942 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
943 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
946 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
947 "out{b}\t{%al, $port|$port, %AL}", []>;
949 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
950 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
952 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
953 "out{l}\t{%eax, $port|$port, %EAX}", []>;
955 def IN8 : I<0x6C, RawFrm, (outs), (ins),
957 def IN16 : I<0x6D, RawFrm, (outs), (ins),
958 "ins{w}", []>, OpSize;
959 def IN32 : I<0x6D, RawFrm, (outs), (ins),
962 //===----------------------------------------------------------------------===//
963 // Move Instructions...
965 let neverHasSideEffects = 1 in {
966 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
967 "mov{b}\t{$src, $dst|$dst, $src}", []>;
968 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
969 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
970 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
971 "mov{l}\t{$src, $dst|$dst, $src}", []>;
973 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
974 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
975 "mov{b}\t{$src, $dst|$dst, $src}",
976 [(set GR8:$dst, imm:$src)]>;
977 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
978 "mov{w}\t{$src, $dst|$dst, $src}",
979 [(set GR16:$dst, imm:$src)]>, OpSize;
980 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
981 "mov{l}\t{$src, $dst|$dst, $src}",
982 [(set GR32:$dst, imm:$src)]>;
985 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
986 "mov{b}\t{$src, $dst|$dst, $src}",
987 [(store (i8 imm:$src), addr:$dst)]>;
988 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
989 "mov{w}\t{$src, $dst|$dst, $src}",
990 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
991 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
992 "mov{l}\t{$src, $dst|$dst, $src}",
993 [(store (i32 imm:$src), addr:$dst)]>;
995 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src),
996 "mov{b}\t{$src, %al|%al, $src}", []>;
997 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
998 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
999 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1000 "mov{l}\t{$src, %eax|%eax, $src}", []>;
1002 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1003 "mov{b}\t{%al, $dst|$dst, %al}", []>;
1004 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1005 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
1006 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1007 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
1009 // Moves to and from segment registers
1010 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1011 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1012 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1013 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1014 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1015 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1016 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1017 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1019 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1020 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1021 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1022 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1023 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1024 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1026 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1027 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1028 "mov{b}\t{$src, $dst|$dst, $src}",
1029 [(set GR8:$dst, (loadi8 addr:$src))]>;
1030 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1031 "mov{w}\t{$src, $dst|$dst, $src}",
1032 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1033 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1034 "mov{l}\t{$src, $dst|$dst, $src}",
1035 [(set GR32:$dst, (loadi32 addr:$src))]>;
1038 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1039 "mov{b}\t{$src, $dst|$dst, $src}",
1040 [(store GR8:$src, addr:$dst)]>;
1041 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1042 "mov{w}\t{$src, $dst|$dst, $src}",
1043 [(store GR16:$src, addr:$dst)]>, OpSize;
1044 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1045 "mov{l}\t{$src, $dst|$dst, $src}",
1046 [(store GR32:$src, addr:$dst)]>;
1048 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1049 let neverHasSideEffects = 1 in
1050 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1051 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1054 canFoldAsLoad = 1, isReMaterializable = 1 in
1055 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1056 "mov{l}\t{$src, $dst|$dst, $src}",
1060 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1061 "mov{l}\t{$src, $dst|$dst, $src}",
1064 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1065 // that they can be used for copying and storing h registers, which can't be
1066 // encoded when a REX prefix is present.
1067 let neverHasSideEffects = 1 in
1068 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1069 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1070 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1072 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1073 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1074 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1076 canFoldAsLoad = 1, isReMaterializable = 1 in
1077 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1078 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1079 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1081 // Moves to and from debug registers
1082 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1083 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1084 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1085 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1087 // Moves to and from control registers
1088 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
1089 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1090 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
1091 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1093 //===----------------------------------------------------------------------===//
1094 // Fixed-Register Multiplication and Division Instructions...
1097 // Extra precision multiplication
1099 // AL is really implied by AX, by the registers in Defs must match the
1100 // SDNode results (i8, i32).
1101 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1102 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1103 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1104 // This probably ought to be moved to a def : Pat<> if the
1105 // syntax can be accepted.
1106 [(set AL, (mul AL, GR8:$src)),
1107 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1109 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1110 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1112 []>, OpSize; // AX,DX = AX*GR16
1114 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1115 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1117 []>; // EAX,EDX = EAX*GR32
1119 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1120 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1122 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1123 // This probably ought to be moved to a def : Pat<> if the
1124 // syntax can be accepted.
1125 [(set AL, (mul AL, (loadi8 addr:$src))),
1126 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1128 let mayLoad = 1, neverHasSideEffects = 1 in {
1129 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1130 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1132 []>, OpSize; // AX,DX = AX*[mem16]
1134 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1135 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1137 []>; // EAX,EDX = EAX*[mem32]
1140 let neverHasSideEffects = 1 in {
1141 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1142 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1144 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1145 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1146 OpSize; // AX,DX = AX*GR16
1147 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1148 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1149 // EAX,EDX = EAX*GR32
1150 let mayLoad = 1 in {
1151 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1152 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1153 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1154 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1155 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1156 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1157 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1158 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1159 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1161 } // neverHasSideEffects
1163 // unsigned division/remainder
1164 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1165 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1166 "div{b}\t$src", []>;
1167 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1168 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1169 "div{w}\t$src", []>, OpSize;
1170 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1171 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1172 "div{l}\t$src", []>;
1173 let mayLoad = 1 in {
1174 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1175 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1176 "div{b}\t$src", []>;
1177 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1178 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1179 "div{w}\t$src", []>, OpSize;
1180 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1181 // EDX:EAX/[mem32] = EAX,EDX
1182 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1183 "div{l}\t$src", []>;
1186 // Signed division/remainder.
1187 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1188 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1189 "idiv{b}\t$src", []>;
1190 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1191 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1192 "idiv{w}\t$src", []>, OpSize;
1193 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1194 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1195 "idiv{l}\t$src", []>;
1196 let mayLoad = 1, mayLoad = 1 in {
1197 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1198 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1199 "idiv{b}\t$src", []>;
1200 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1201 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1202 "idiv{w}\t$src", []>, OpSize;
1203 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1204 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1205 // EDX:EAX/[mem32] = EAX,EDX
1206 "idiv{l}\t$src", []>;
1209 //===----------------------------------------------------------------------===//
1210 // Two address Instructions.
1212 let isTwoAddress = 1 in {
1214 // Conditional moves
1215 let Uses = [EFLAGS] in {
1217 let Predicates = [HasCMov] in {
1218 let isCommutable = 1 in {
1219 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1220 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1221 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1222 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1223 X86_COND_B, EFLAGS))]>,
1225 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1226 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1227 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1228 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1229 X86_COND_B, EFLAGS))]>,
1231 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1232 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1233 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1234 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1235 X86_COND_AE, EFLAGS))]>,
1237 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1238 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1239 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1240 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1241 X86_COND_AE, EFLAGS))]>,
1243 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1244 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1245 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1246 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1247 X86_COND_E, EFLAGS))]>,
1249 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1250 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1251 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1252 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1253 X86_COND_E, EFLAGS))]>,
1255 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1256 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1257 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1258 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1259 X86_COND_NE, EFLAGS))]>,
1261 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1262 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1263 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1264 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1265 X86_COND_NE, EFLAGS))]>,
1267 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1268 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1269 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1270 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1271 X86_COND_BE, EFLAGS))]>,
1273 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1274 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1275 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1276 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1277 X86_COND_BE, EFLAGS))]>,
1279 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1280 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1281 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1282 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1283 X86_COND_A, EFLAGS))]>,
1285 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1286 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1287 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1288 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1289 X86_COND_A, EFLAGS))]>,
1291 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1292 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1293 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1294 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1295 X86_COND_L, EFLAGS))]>,
1297 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1298 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1299 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1300 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1301 X86_COND_L, EFLAGS))]>,
1303 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1304 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1305 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1306 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1307 X86_COND_GE, EFLAGS))]>,
1309 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1310 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1311 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1312 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1313 X86_COND_GE, EFLAGS))]>,
1315 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1316 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1317 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1318 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1319 X86_COND_LE, EFLAGS))]>,
1321 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1322 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1323 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1324 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1325 X86_COND_LE, EFLAGS))]>,
1327 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1328 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1329 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1330 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1331 X86_COND_G, EFLAGS))]>,
1333 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1334 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1335 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1336 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1337 X86_COND_G, EFLAGS))]>,
1339 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1340 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1341 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1342 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1343 X86_COND_S, EFLAGS))]>,
1345 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1346 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1347 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1348 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1349 X86_COND_S, EFLAGS))]>,
1351 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1352 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1353 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1354 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1355 X86_COND_NS, EFLAGS))]>,
1357 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1358 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1359 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1360 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1361 X86_COND_NS, EFLAGS))]>,
1363 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1364 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1365 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1366 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1367 X86_COND_P, EFLAGS))]>,
1369 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1370 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1371 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1372 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1373 X86_COND_P, EFLAGS))]>,
1375 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1376 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1377 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1378 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1379 X86_COND_NP, EFLAGS))]>,
1381 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1382 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1383 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1384 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1385 X86_COND_NP, EFLAGS))]>,
1387 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1388 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1389 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1390 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1391 X86_COND_O, EFLAGS))]>,
1393 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1394 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1395 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1396 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1397 X86_COND_O, EFLAGS))]>,
1399 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1400 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1401 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1402 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1403 X86_COND_NO, EFLAGS))]>,
1405 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1406 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1407 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1408 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1409 X86_COND_NO, EFLAGS))]>,
1411 } // isCommutable = 1
1413 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1414 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1415 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1416 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1417 X86_COND_B, EFLAGS))]>,
1419 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1420 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1421 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1422 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1423 X86_COND_B, EFLAGS))]>,
1425 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1426 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1427 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1428 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1429 X86_COND_AE, EFLAGS))]>,
1431 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1432 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1433 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1434 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1435 X86_COND_AE, EFLAGS))]>,
1437 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1438 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1439 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1440 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1441 X86_COND_E, EFLAGS))]>,
1443 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1444 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1445 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1446 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1447 X86_COND_E, EFLAGS))]>,
1449 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1450 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1451 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1452 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1453 X86_COND_NE, EFLAGS))]>,
1455 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1456 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1457 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1458 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1459 X86_COND_NE, EFLAGS))]>,
1461 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1462 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1463 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1464 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1465 X86_COND_BE, EFLAGS))]>,
1467 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1468 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1469 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1470 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1471 X86_COND_BE, EFLAGS))]>,
1473 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1474 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1475 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1476 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1477 X86_COND_A, EFLAGS))]>,
1479 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1480 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1481 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1482 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1483 X86_COND_A, EFLAGS))]>,
1485 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1486 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1487 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1488 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1489 X86_COND_L, EFLAGS))]>,
1491 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1492 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1493 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1494 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1495 X86_COND_L, EFLAGS))]>,
1497 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1498 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1499 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1500 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1501 X86_COND_GE, EFLAGS))]>,
1503 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1504 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1505 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1506 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1507 X86_COND_GE, EFLAGS))]>,
1509 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1510 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1511 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1512 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1513 X86_COND_LE, EFLAGS))]>,
1515 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1516 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1517 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1518 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1519 X86_COND_LE, EFLAGS))]>,
1521 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1522 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1523 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1524 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1525 X86_COND_G, EFLAGS))]>,
1527 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1528 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1529 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1530 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1531 X86_COND_G, EFLAGS))]>,
1533 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1534 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1535 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1536 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1537 X86_COND_S, EFLAGS))]>,
1539 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1540 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1541 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1542 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1543 X86_COND_S, EFLAGS))]>,
1545 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1546 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1547 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1548 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1549 X86_COND_NS, EFLAGS))]>,
1551 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1552 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1553 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1554 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1555 X86_COND_NS, EFLAGS))]>,
1557 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1558 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1559 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1560 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1561 X86_COND_P, EFLAGS))]>,
1563 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1564 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1565 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1566 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1567 X86_COND_P, EFLAGS))]>,
1569 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1570 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1571 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1572 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1573 X86_COND_NP, EFLAGS))]>,
1575 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1576 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1577 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1578 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1579 X86_COND_NP, EFLAGS))]>,
1581 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1582 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1583 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1584 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1585 X86_COND_O, EFLAGS))]>,
1587 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1588 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1589 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1590 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1591 X86_COND_O, EFLAGS))]>,
1593 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1594 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1595 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1596 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1597 X86_COND_NO, EFLAGS))]>,
1599 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1600 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1601 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1602 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1603 X86_COND_NO, EFLAGS))]>,
1605 } // Predicates = [HasCMov]
1607 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1608 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1609 // however that requires promoting the operands, and can induce additional
1610 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1611 // clobber EFLAGS, because if one of the operands is zero, the expansion
1612 // could involve an xor.
1613 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in {
1614 def CMOV_GR8 : I<0, Pseudo,
1615 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1616 "#CMOV_GR8 PSEUDO!",
1617 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1618 imm:$cond, EFLAGS))]>;
1620 let Predicates = [NoCMov] in {
1621 def CMOV_GR32 : I<0, Pseudo,
1622 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1623 "#CMOV_GR32* PSEUDO!",
1625 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1626 def CMOV_GR16 : I<0, Pseudo,
1627 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1628 "#CMOV_GR16* PSEUDO!",
1630 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1631 def CMOV_RFP32 : I<0, Pseudo,
1632 (outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1633 "#CMOV_RFP32 PSEUDO!",
1634 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1636 def CMOV_RFP64 : I<0, Pseudo,
1637 (outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1638 "#CMOV_RFP64 PSEUDO!",
1639 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1641 def CMOV_RFP80 : I<0, Pseudo,
1642 (outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1643 "#CMOV_RFP80 PSEUDO!",
1644 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1646 } // Predicates = [NoCMov]
1647 } // UsesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS]
1648 } // Uses = [EFLAGS]
1651 // unary instructions
1652 let CodeSize = 2 in {
1653 let Defs = [EFLAGS] in {
1654 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1655 [(set GR8:$dst, (ineg GR8:$src)),
1656 (implicit EFLAGS)]>;
1657 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1658 [(set GR16:$dst, (ineg GR16:$src)),
1659 (implicit EFLAGS)]>, OpSize;
1660 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1661 [(set GR32:$dst, (ineg GR32:$src)),
1662 (implicit EFLAGS)]>;
1663 let isTwoAddress = 0 in {
1664 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1665 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1666 (implicit EFLAGS)]>;
1667 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1668 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1669 (implicit EFLAGS)]>, OpSize;
1670 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1671 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1672 (implicit EFLAGS)]>;
1674 } // Defs = [EFLAGS]
1676 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1677 let AddedComplexity = 15 in {
1678 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1679 [(set GR8:$dst, (not GR8:$src))]>;
1680 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1681 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1682 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1683 [(set GR32:$dst, (not GR32:$src))]>;
1685 let isTwoAddress = 0 in {
1686 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1687 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1688 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1689 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1690 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1691 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1695 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1696 let Defs = [EFLAGS] in {
1698 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1699 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src))]>;
1701 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1702 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1704 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src))]>,
1705 OpSize, Requires<[In32BitMode]>;
1706 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1708 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src))]>,
1709 Requires<[In32BitMode]>;
1711 let isTwoAddress = 0, CodeSize = 2 in {
1712 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1713 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1714 (implicit EFLAGS)]>;
1715 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1716 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1717 (implicit EFLAGS)]>,
1718 OpSize, Requires<[In32BitMode]>;
1719 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1720 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1721 (implicit EFLAGS)]>,
1722 Requires<[In32BitMode]>;
1726 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1727 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src))]>;
1728 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1729 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1731 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src))]>,
1732 OpSize, Requires<[In32BitMode]>;
1733 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1735 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src))]>,
1736 Requires<[In32BitMode]>;
1739 let isTwoAddress = 0, CodeSize = 2 in {
1740 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1741 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1742 (implicit EFLAGS)]>;
1743 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1744 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1745 (implicit EFLAGS)]>,
1746 OpSize, Requires<[In32BitMode]>;
1747 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1748 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1749 (implicit EFLAGS)]>,
1750 Requires<[In32BitMode]>;
1752 } // Defs = [EFLAGS]
1754 // Logical operators...
1755 let Defs = [EFLAGS] in {
1756 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1757 def AND8rr : I<0x20, MRMDestReg,
1758 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1759 "and{b}\t{$src2, $dst|$dst, $src2}",
1760 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1761 def AND16rr : I<0x21, MRMDestReg,
1762 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1763 "and{w}\t{$src2, $dst|$dst, $src2}",
1764 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1765 GR16:$src2))]>, OpSize;
1766 def AND32rr : I<0x21, MRMDestReg,
1767 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1768 "and{l}\t{$src2, $dst|$dst, $src2}",
1769 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1773 // AND instructions with the destination register in REG and the source register
1774 // in R/M. Included for the disassembler.
1775 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1776 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1777 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1778 (ins GR16:$src1, GR16:$src2),
1779 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1780 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1781 (ins GR32:$src1, GR32:$src2),
1782 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1784 def AND8rm : I<0x22, MRMSrcMem,
1785 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1786 "and{b}\t{$src2, $dst|$dst, $src2}",
1787 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1788 (loadi8 addr:$src2)))]>;
1789 def AND16rm : I<0x23, MRMSrcMem,
1790 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1791 "and{w}\t{$src2, $dst|$dst, $src2}",
1792 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1793 (loadi16 addr:$src2)))]>,
1795 def AND32rm : I<0x23, MRMSrcMem,
1796 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1797 "and{l}\t{$src2, $dst|$dst, $src2}",
1798 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1799 (loadi32 addr:$src2)))]>;
1801 def AND8ri : Ii8<0x80, MRM4r,
1802 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1803 "and{b}\t{$src2, $dst|$dst, $src2}",
1804 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1806 def AND16ri : Ii16<0x81, MRM4r,
1807 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1808 "and{w}\t{$src2, $dst|$dst, $src2}",
1809 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1810 imm:$src2))]>, OpSize;
1811 def AND32ri : Ii32<0x81, MRM4r,
1812 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1813 "and{l}\t{$src2, $dst|$dst, $src2}",
1814 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1816 def AND16ri8 : Ii8<0x83, MRM4r,
1817 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1818 "and{w}\t{$src2, $dst|$dst, $src2}",
1819 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1820 i16immSExt8:$src2))]>,
1822 def AND32ri8 : Ii8<0x83, MRM4r,
1823 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1824 "and{l}\t{$src2, $dst|$dst, $src2}",
1825 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1826 i32immSExt8:$src2))]>;
1828 let isTwoAddress = 0 in {
1829 def AND8mr : I<0x20, MRMDestMem,
1830 (outs), (ins i8mem :$dst, GR8 :$src),
1831 "and{b}\t{$src, $dst|$dst, $src}",
1832 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1833 (implicit EFLAGS)]>;
1834 def AND16mr : I<0x21, MRMDestMem,
1835 (outs), (ins i16mem:$dst, GR16:$src),
1836 "and{w}\t{$src, $dst|$dst, $src}",
1837 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1838 (implicit EFLAGS)]>,
1840 def AND32mr : I<0x21, MRMDestMem,
1841 (outs), (ins i32mem:$dst, GR32:$src),
1842 "and{l}\t{$src, $dst|$dst, $src}",
1843 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1844 (implicit EFLAGS)]>;
1845 def AND8mi : Ii8<0x80, MRM4m,
1846 (outs), (ins i8mem :$dst, i8imm :$src),
1847 "and{b}\t{$src, $dst|$dst, $src}",
1848 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1849 (implicit EFLAGS)]>;
1850 def AND16mi : Ii16<0x81, MRM4m,
1851 (outs), (ins i16mem:$dst, i16imm:$src),
1852 "and{w}\t{$src, $dst|$dst, $src}",
1853 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1854 (implicit EFLAGS)]>,
1856 def AND32mi : Ii32<0x81, MRM4m,
1857 (outs), (ins i32mem:$dst, i32imm:$src),
1858 "and{l}\t{$src, $dst|$dst, $src}",
1859 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1860 (implicit EFLAGS)]>;
1861 def AND16mi8 : Ii8<0x83, MRM4m,
1862 (outs), (ins i16mem:$dst, i16i8imm :$src),
1863 "and{w}\t{$src, $dst|$dst, $src}",
1864 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1865 (implicit EFLAGS)]>,
1867 def AND32mi8 : Ii8<0x83, MRM4m,
1868 (outs), (ins i32mem:$dst, i32i8imm :$src),
1869 "and{l}\t{$src, $dst|$dst, $src}",
1870 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1871 (implicit EFLAGS)]>;
1873 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1874 "and{b}\t{$src, %al|%al, $src}", []>;
1875 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1876 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1877 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1878 "and{l}\t{$src, %eax|%eax, $src}", []>;
1883 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1884 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1885 (ins GR8 :$src1, GR8 :$src2),
1886 "or{b}\t{$src2, $dst|$dst, $src2}",
1887 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1888 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1889 (ins GR16:$src1, GR16:$src2),
1890 "or{w}\t{$src2, $dst|$dst, $src2}",
1891 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1893 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1894 (ins GR32:$src1, GR32:$src2),
1895 "or{l}\t{$src2, $dst|$dst, $src2}",
1896 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1899 // OR instructions with the destination register in REG and the source register
1900 // in R/M. Included for the disassembler.
1901 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1902 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1903 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1904 (ins GR16:$src1, GR16:$src2),
1905 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1906 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1907 (ins GR32:$src1, GR32:$src2),
1908 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1910 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
1911 (ins GR8 :$src1, i8mem :$src2),
1912 "or{b}\t{$src2, $dst|$dst, $src2}",
1913 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
1914 (load addr:$src2)))]>;
1915 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
1916 (ins GR16:$src1, i16mem:$src2),
1917 "or{w}\t{$src2, $dst|$dst, $src2}",
1918 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1919 (load addr:$src2)))]>,
1921 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
1922 (ins GR32:$src1, i32mem:$src2),
1923 "or{l}\t{$src2, $dst|$dst, $src2}",
1924 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1925 (load addr:$src2)))]>;
1927 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1928 (ins GR8 :$src1, i8imm:$src2),
1929 "or{b}\t{$src2, $dst|$dst, $src2}",
1930 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
1931 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1932 (ins GR16:$src1, i16imm:$src2),
1933 "or{w}\t{$src2, $dst|$dst, $src2}",
1934 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1935 imm:$src2))]>, OpSize;
1936 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1937 (ins GR32:$src1, i32imm:$src2),
1938 "or{l}\t{$src2, $dst|$dst, $src2}",
1939 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1942 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1943 (ins GR16:$src1, i16i8imm:$src2),
1944 "or{w}\t{$src2, $dst|$dst, $src2}",
1945 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1946 i16immSExt8:$src2))]>, OpSize;
1947 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1948 (ins GR32:$src1, i32i8imm:$src2),
1949 "or{l}\t{$src2, $dst|$dst, $src2}",
1950 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1951 i32immSExt8:$src2))]>;
1952 let isTwoAddress = 0 in {
1953 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1954 "or{b}\t{$src, $dst|$dst, $src}",
1955 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1956 (implicit EFLAGS)]>;
1957 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1958 "or{w}\t{$src, $dst|$dst, $src}",
1959 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1960 (implicit EFLAGS)]>, OpSize;
1961 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1962 "or{l}\t{$src, $dst|$dst, $src}",
1963 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1964 (implicit EFLAGS)]>;
1965 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1966 "or{b}\t{$src, $dst|$dst, $src}",
1967 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1968 (implicit EFLAGS)]>;
1969 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1970 "or{w}\t{$src, $dst|$dst, $src}",
1971 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1972 (implicit EFLAGS)]>,
1974 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1975 "or{l}\t{$src, $dst|$dst, $src}",
1976 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1977 (implicit EFLAGS)]>;
1978 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1979 "or{w}\t{$src, $dst|$dst, $src}",
1980 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1981 (implicit EFLAGS)]>,
1983 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1984 "or{l}\t{$src, $dst|$dst, $src}",
1985 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1986 (implicit EFLAGS)]>;
1988 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1989 "or{b}\t{$src, %al|%al, $src}", []>;
1990 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1991 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1992 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1993 "or{l}\t{$src, %eax|%eax, $src}", []>;
1994 } // isTwoAddress = 0
1997 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1998 def XOR8rr : I<0x30, MRMDestReg,
1999 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2000 "xor{b}\t{$src2, $dst|$dst, $src2}",
2001 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2003 def XOR16rr : I<0x31, MRMDestReg,
2004 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2005 "xor{w}\t{$src2, $dst|$dst, $src2}",
2006 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2007 GR16:$src2))]>, OpSize;
2008 def XOR32rr : I<0x31, MRMDestReg,
2009 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2010 "xor{l}\t{$src2, $dst|$dst, $src2}",
2011 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2013 } // isCommutable = 1
2015 // XOR instructions with the destination register in REG and the source register
2016 // in R/M. Included for the disassembler.
2017 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2018 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
2019 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
2020 (ins GR16:$src1, GR16:$src2),
2021 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2022 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
2023 (ins GR32:$src1, GR32:$src2),
2024 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2026 def XOR8rm : I<0x32, MRMSrcMem,
2027 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2028 "xor{b}\t{$src2, $dst|$dst, $src2}",
2029 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2030 (load addr:$src2)))]>;
2031 def XOR16rm : I<0x33, MRMSrcMem,
2032 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2033 "xor{w}\t{$src2, $dst|$dst, $src2}",
2034 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2035 (load addr:$src2)))]>,
2037 def XOR32rm : I<0x33, MRMSrcMem,
2038 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2039 "xor{l}\t{$src2, $dst|$dst, $src2}",
2040 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2041 (load addr:$src2)))]>;
2043 def XOR8ri : Ii8<0x80, MRM6r,
2044 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2045 "xor{b}\t{$src2, $dst|$dst, $src2}",
2046 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
2047 def XOR16ri : Ii16<0x81, MRM6r,
2048 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2049 "xor{w}\t{$src2, $dst|$dst, $src2}",
2050 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2051 imm:$src2))]>, OpSize;
2052 def XOR32ri : Ii32<0x81, MRM6r,
2053 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2054 "xor{l}\t{$src2, $dst|$dst, $src2}",
2055 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2057 def XOR16ri8 : Ii8<0x83, MRM6r,
2058 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2059 "xor{w}\t{$src2, $dst|$dst, $src2}",
2060 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2061 i16immSExt8:$src2))]>,
2063 def XOR32ri8 : Ii8<0x83, MRM6r,
2064 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2065 "xor{l}\t{$src2, $dst|$dst, $src2}",
2066 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2067 i32immSExt8:$src2))]>;
2069 let isTwoAddress = 0 in {
2070 def XOR8mr : I<0x30, MRMDestMem,
2071 (outs), (ins i8mem :$dst, GR8 :$src),
2072 "xor{b}\t{$src, $dst|$dst, $src}",
2073 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2074 (implicit EFLAGS)]>;
2075 def XOR16mr : I<0x31, MRMDestMem,
2076 (outs), (ins i16mem:$dst, GR16:$src),
2077 "xor{w}\t{$src, $dst|$dst, $src}",
2078 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2079 (implicit EFLAGS)]>,
2081 def XOR32mr : I<0x31, MRMDestMem,
2082 (outs), (ins i32mem:$dst, GR32:$src),
2083 "xor{l}\t{$src, $dst|$dst, $src}",
2084 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2085 (implicit EFLAGS)]>;
2086 def XOR8mi : Ii8<0x80, MRM6m,
2087 (outs), (ins i8mem :$dst, i8imm :$src),
2088 "xor{b}\t{$src, $dst|$dst, $src}",
2089 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2090 (implicit EFLAGS)]>;
2091 def XOR16mi : Ii16<0x81, MRM6m,
2092 (outs), (ins i16mem:$dst, i16imm:$src),
2093 "xor{w}\t{$src, $dst|$dst, $src}",
2094 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2095 (implicit EFLAGS)]>,
2097 def XOR32mi : Ii32<0x81, MRM6m,
2098 (outs), (ins i32mem:$dst, i32imm:$src),
2099 "xor{l}\t{$src, $dst|$dst, $src}",
2100 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2101 (implicit EFLAGS)]>;
2102 def XOR16mi8 : Ii8<0x83, MRM6m,
2103 (outs), (ins i16mem:$dst, i16i8imm :$src),
2104 "xor{w}\t{$src, $dst|$dst, $src}",
2105 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2106 (implicit EFLAGS)]>,
2108 def XOR32mi8 : Ii8<0x83, MRM6m,
2109 (outs), (ins i32mem:$dst, i32i8imm :$src),
2110 "xor{l}\t{$src, $dst|$dst, $src}",
2111 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2112 (implicit EFLAGS)]>;
2114 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2115 "xor{b}\t{$src, %al|%al, $src}", []>;
2116 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
2117 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2118 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
2119 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2120 } // isTwoAddress = 0
2121 } // Defs = [EFLAGS]
2123 // Shift instructions
2124 let Defs = [EFLAGS] in {
2125 let Uses = [CL] in {
2126 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2127 "shl{b}\t{%cl, $dst|$dst, CL}",
2128 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2129 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2130 "shl{w}\t{%cl, $dst|$dst, CL}",
2131 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2132 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2133 "shl{l}\t{%cl, $dst|$dst, CL}",
2134 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2137 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2138 "shl{b}\t{$src2, $dst|$dst, $src2}",
2139 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2140 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2141 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2142 "shl{w}\t{$src2, $dst|$dst, $src2}",
2143 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2144 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2145 "shl{l}\t{$src2, $dst|$dst, $src2}",
2146 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2148 // NOTE: We don't include patterns for shifts of a register by one, because
2149 // 'add reg,reg' is cheaper.
2151 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2152 "shl{b}\t$dst", []>;
2153 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2154 "shl{w}\t$dst", []>, OpSize;
2155 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2156 "shl{l}\t$dst", []>;
2158 } // isConvertibleToThreeAddress = 1
2160 let isTwoAddress = 0 in {
2161 let Uses = [CL] in {
2162 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2163 "shl{b}\t{%cl, $dst|$dst, CL}",
2164 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2165 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2166 "shl{w}\t{%cl, $dst|$dst, CL}",
2167 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2168 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2169 "shl{l}\t{%cl, $dst|$dst, CL}",
2170 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2172 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2173 "shl{b}\t{$src, $dst|$dst, $src}",
2174 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2175 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2176 "shl{w}\t{$src, $dst|$dst, $src}",
2177 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2179 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2180 "shl{l}\t{$src, $dst|$dst, $src}",
2181 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2184 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2186 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2187 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2189 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2191 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2193 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2196 let Uses = [CL] in {
2197 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2198 "shr{b}\t{%cl, $dst|$dst, CL}",
2199 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2200 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2201 "shr{w}\t{%cl, $dst|$dst, CL}",
2202 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2203 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2204 "shr{l}\t{%cl, $dst|$dst, CL}",
2205 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2208 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2209 "shr{b}\t{$src2, $dst|$dst, $src2}",
2210 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2211 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2212 "shr{w}\t{$src2, $dst|$dst, $src2}",
2213 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2214 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2215 "shr{l}\t{$src2, $dst|$dst, $src2}",
2216 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2219 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2221 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2222 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2224 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2225 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2227 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2229 let isTwoAddress = 0 in {
2230 let Uses = [CL] in {
2231 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2232 "shr{b}\t{%cl, $dst|$dst, CL}",
2233 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2234 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2235 "shr{w}\t{%cl, $dst|$dst, CL}",
2236 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2238 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2239 "shr{l}\t{%cl, $dst|$dst, CL}",
2240 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2242 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2243 "shr{b}\t{$src, $dst|$dst, $src}",
2244 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2245 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2246 "shr{w}\t{$src, $dst|$dst, $src}",
2247 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2249 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2250 "shr{l}\t{$src, $dst|$dst, $src}",
2251 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2254 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2256 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2257 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2259 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2260 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2262 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2265 let Uses = [CL] in {
2266 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2267 "sar{b}\t{%cl, $dst|$dst, CL}",
2268 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2269 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2270 "sar{w}\t{%cl, $dst|$dst, CL}",
2271 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2272 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2273 "sar{l}\t{%cl, $dst|$dst, CL}",
2274 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2277 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2278 "sar{b}\t{$src2, $dst|$dst, $src2}",
2279 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2280 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2281 "sar{w}\t{$src2, $dst|$dst, $src2}",
2282 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2284 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2285 "sar{l}\t{$src2, $dst|$dst, $src2}",
2286 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2289 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2291 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2292 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2294 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2295 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2297 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2299 let isTwoAddress = 0 in {
2300 let Uses = [CL] in {
2301 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2302 "sar{b}\t{%cl, $dst|$dst, CL}",
2303 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2304 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2305 "sar{w}\t{%cl, $dst|$dst, CL}",
2306 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2307 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2308 "sar{l}\t{%cl, $dst|$dst, CL}",
2309 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2311 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2312 "sar{b}\t{$src, $dst|$dst, $src}",
2313 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2314 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2315 "sar{w}\t{$src, $dst|$dst, $src}",
2316 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2318 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2319 "sar{l}\t{$src, $dst|$dst, $src}",
2320 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2323 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2325 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2326 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2328 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2330 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2332 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2335 // Rotate instructions
2337 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2338 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2339 let Uses = [CL] in {
2340 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2341 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2343 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2344 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2346 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2347 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2348 let Uses = [CL] in {
2349 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2350 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2352 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2353 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2355 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2356 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2357 let Uses = [CL] in {
2358 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2359 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2361 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2362 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2364 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2365 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2366 let Uses = [CL] in {
2367 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2368 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2370 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2371 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2373 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2374 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2375 let Uses = [CL] in {
2376 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2377 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2379 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2380 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2382 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2383 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2384 let Uses = [CL] in {
2385 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2386 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2388 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2389 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2391 let isTwoAddress = 0 in {
2392 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2393 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2394 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2395 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2396 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2397 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2398 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2399 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2400 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2401 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2402 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2403 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2404 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2405 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2406 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2407 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2408 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2409 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2410 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2411 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2412 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2413 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2414 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2415 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2417 let Uses = [CL] in {
2418 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2419 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2420 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2421 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2422 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2423 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2424 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2425 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2426 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2427 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2428 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2429 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2433 // FIXME: provide shorter instructions when imm8 == 1
2434 let Uses = [CL] in {
2435 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2436 "rol{b}\t{%cl, $dst|$dst, CL}",
2437 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2438 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2439 "rol{w}\t{%cl, $dst|$dst, CL}",
2440 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2441 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2442 "rol{l}\t{%cl, $dst|$dst, CL}",
2443 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2446 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2447 "rol{b}\t{$src2, $dst|$dst, $src2}",
2448 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2449 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2450 "rol{w}\t{$src2, $dst|$dst, $src2}",
2451 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2453 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2454 "rol{l}\t{$src2, $dst|$dst, $src2}",
2455 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2458 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2460 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2461 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2463 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2464 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2466 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2468 let isTwoAddress = 0 in {
2469 let Uses = [CL] in {
2470 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2471 "rol{b}\t{%cl, $dst|$dst, CL}",
2472 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2473 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2474 "rol{w}\t{%cl, $dst|$dst, CL}",
2475 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2476 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2477 "rol{l}\t{%cl, $dst|$dst, CL}",
2478 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2480 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2481 "rol{b}\t{$src, $dst|$dst, $src}",
2482 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2483 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2484 "rol{w}\t{$src, $dst|$dst, $src}",
2485 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2487 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2488 "rol{l}\t{$src, $dst|$dst, $src}",
2489 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2492 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2494 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2495 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2497 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2499 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2501 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2504 let Uses = [CL] in {
2505 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2506 "ror{b}\t{%cl, $dst|$dst, CL}",
2507 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2508 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2509 "ror{w}\t{%cl, $dst|$dst, CL}",
2510 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2511 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2512 "ror{l}\t{%cl, $dst|$dst, CL}",
2513 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2516 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2517 "ror{b}\t{$src2, $dst|$dst, $src2}",
2518 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2519 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2520 "ror{w}\t{$src2, $dst|$dst, $src2}",
2521 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2523 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2524 "ror{l}\t{$src2, $dst|$dst, $src2}",
2525 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2528 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2530 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2531 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2533 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2534 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2536 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2538 let isTwoAddress = 0 in {
2539 let Uses = [CL] in {
2540 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2541 "ror{b}\t{%cl, $dst|$dst, CL}",
2542 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2543 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2544 "ror{w}\t{%cl, $dst|$dst, CL}",
2545 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2546 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2547 "ror{l}\t{%cl, $dst|$dst, CL}",
2548 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2550 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2551 "ror{b}\t{$src, $dst|$dst, $src}",
2552 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2553 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2554 "ror{w}\t{$src, $dst|$dst, $src}",
2555 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2557 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2558 "ror{l}\t{$src, $dst|$dst, $src}",
2559 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2562 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2564 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2565 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2567 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2569 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2571 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2576 // Double shift instructions (generalizations of rotate)
2577 let Uses = [CL] in {
2578 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2579 (ins GR32:$src1, GR32:$src2),
2580 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2581 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2582 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2583 (ins GR32:$src1, GR32:$src2),
2584 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2585 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2586 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2587 (ins GR16:$src1, GR16:$src2),
2588 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2589 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2591 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2592 (ins GR16:$src1, GR16:$src2),
2593 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2594 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2598 let isCommutable = 1 in { // These instructions commute to each other.
2599 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2601 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2602 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2603 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2606 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2608 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2609 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2610 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2613 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2615 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2616 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2617 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2620 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2622 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2623 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2624 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2629 let isTwoAddress = 0 in {
2630 let Uses = [CL] in {
2631 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2632 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2633 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2635 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2636 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2637 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2640 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2641 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2642 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2643 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2644 (i8 imm:$src3)), addr:$dst)]>,
2646 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2647 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2648 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2649 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2650 (i8 imm:$src3)), addr:$dst)]>,
2653 let Uses = [CL] in {
2654 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2655 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2656 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2657 addr:$dst)]>, TB, OpSize;
2658 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2659 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2660 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2661 addr:$dst)]>, TB, OpSize;
2663 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2664 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2665 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2666 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2667 (i8 imm:$src3)), addr:$dst)]>,
2669 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2670 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2671 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2672 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2673 (i8 imm:$src3)), addr:$dst)]>,
2676 } // Defs = [EFLAGS]
2680 let Defs = [EFLAGS] in {
2681 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2682 // Register-Register Addition
2683 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2684 (ins GR8 :$src1, GR8 :$src2),
2685 "add{b}\t{$src2, $dst|$dst, $src2}",
2686 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2688 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2689 // Register-Register Addition
2690 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2691 (ins GR16:$src1, GR16:$src2),
2692 "add{w}\t{$src2, $dst|$dst, $src2}",
2693 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2694 GR16:$src2))]>, OpSize;
2695 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2696 (ins GR32:$src1, GR32:$src2),
2697 "add{l}\t{$src2, $dst|$dst, $src2}",
2698 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2700 } // end isConvertibleToThreeAddress
2701 } // end isCommutable
2703 // These are alternate spellings for use by the disassembler, we mark them as
2704 // code gen only to ensure they aren't matched by the assembler.
2705 let isCodeGenOnly = 1 in {
2706 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2707 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2708 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2709 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2710 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2711 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2714 // Register-Memory Addition
2715 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2716 (ins GR8 :$src1, i8mem :$src2),
2717 "add{b}\t{$src2, $dst|$dst, $src2}",
2718 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2719 (load addr:$src2)))]>;
2720 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2721 (ins GR16:$src1, i16mem:$src2),
2722 "add{w}\t{$src2, $dst|$dst, $src2}",
2723 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2724 (load addr:$src2)))]>, OpSize;
2725 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2726 (ins GR32:$src1, i32mem:$src2),
2727 "add{l}\t{$src2, $dst|$dst, $src2}",
2728 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2729 (load addr:$src2)))]>;
2731 // Register-Integer Addition
2732 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2733 "add{b}\t{$src2, $dst|$dst, $src2}",
2734 [(set GR8:$dst, EFLAGS,
2735 (X86add_flag GR8:$src1, imm:$src2))]>;
2737 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2738 // Register-Integer Addition
2739 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2740 (ins GR16:$src1, i16imm:$src2),
2741 "add{w}\t{$src2, $dst|$dst, $src2}",
2742 [(set GR16:$dst, EFLAGS,
2743 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2744 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2745 (ins GR32:$src1, i32imm:$src2),
2746 "add{l}\t{$src2, $dst|$dst, $src2}",
2747 [(set GR32:$dst, EFLAGS,
2748 (X86add_flag GR32:$src1, imm:$src2))]>;
2749 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2750 (ins GR16:$src1, i16i8imm:$src2),
2751 "add{w}\t{$src2, $dst|$dst, $src2}",
2752 [(set GR16:$dst, EFLAGS,
2753 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2754 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2755 (ins GR32:$src1, i32i8imm:$src2),
2756 "add{l}\t{$src2, $dst|$dst, $src2}",
2757 [(set GR32:$dst, EFLAGS,
2758 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2761 let isTwoAddress = 0 in {
2762 // Memory-Register Addition
2763 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2764 "add{b}\t{$src2, $dst|$dst, $src2}",
2765 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2766 (implicit EFLAGS)]>;
2767 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2768 "add{w}\t{$src2, $dst|$dst, $src2}",
2769 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2770 (implicit EFLAGS)]>, OpSize;
2771 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2772 "add{l}\t{$src2, $dst|$dst, $src2}",
2773 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2774 (implicit EFLAGS)]>;
2775 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2776 "add{b}\t{$src2, $dst|$dst, $src2}",
2777 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2778 (implicit EFLAGS)]>;
2779 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2780 "add{w}\t{$src2, $dst|$dst, $src2}",
2781 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2782 (implicit EFLAGS)]>, OpSize;
2783 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2784 "add{l}\t{$src2, $dst|$dst, $src2}",
2785 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2786 (implicit EFLAGS)]>;
2787 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2788 "add{w}\t{$src2, $dst|$dst, $src2}",
2789 [(store (add (load addr:$dst), i16immSExt8:$src2),
2791 (implicit EFLAGS)]>, OpSize;
2792 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2793 "add{l}\t{$src2, $dst|$dst, $src2}",
2794 [(store (add (load addr:$dst), i32immSExt8:$src2),
2796 (implicit EFLAGS)]>;
2799 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2800 "add{b}\t{$src, %al|%al, $src}", []>;
2801 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2802 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2803 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2804 "add{l}\t{$src, %eax|%eax, $src}", []>;
2807 let Uses = [EFLAGS] in {
2808 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2809 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2810 "adc{b}\t{$src2, $dst|$dst, $src2}",
2811 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2812 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2813 (ins GR16:$src1, GR16:$src2),
2814 "adc{w}\t{$src2, $dst|$dst, $src2}",
2815 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2816 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2817 (ins GR32:$src1, GR32:$src2),
2818 "adc{l}\t{$src2, $dst|$dst, $src2}",
2819 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2822 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2823 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2824 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2825 (ins GR16:$src1, GR16:$src2),
2826 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2827 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2828 (ins GR32:$src1, GR32:$src2),
2829 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2831 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2832 (ins GR8:$src1, i8mem:$src2),
2833 "adc{b}\t{$src2, $dst|$dst, $src2}",
2834 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2835 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2836 (ins GR16:$src1, i16mem:$src2),
2837 "adc{w}\t{$src2, $dst|$dst, $src2}",
2838 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2840 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2841 (ins GR32:$src1, i32mem:$src2),
2842 "adc{l}\t{$src2, $dst|$dst, $src2}",
2843 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2844 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2845 "adc{b}\t{$src2, $dst|$dst, $src2}",
2846 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2847 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2848 (ins GR16:$src1, i16imm:$src2),
2849 "adc{w}\t{$src2, $dst|$dst, $src2}",
2850 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2851 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2852 (ins GR16:$src1, i16i8imm:$src2),
2853 "adc{w}\t{$src2, $dst|$dst, $src2}",
2854 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2856 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2857 (ins GR32:$src1, i32imm:$src2),
2858 "adc{l}\t{$src2, $dst|$dst, $src2}",
2859 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2860 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2861 (ins GR32:$src1, i32i8imm:$src2),
2862 "adc{l}\t{$src2, $dst|$dst, $src2}",
2863 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2865 let isTwoAddress = 0 in {
2866 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2867 "adc{b}\t{$src2, $dst|$dst, $src2}",
2868 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2869 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2870 "adc{w}\t{$src2, $dst|$dst, $src2}",
2871 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2873 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2874 "adc{l}\t{$src2, $dst|$dst, $src2}",
2875 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2876 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2877 "adc{b}\t{$src2, $dst|$dst, $src2}",
2878 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2879 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2880 "adc{w}\t{$src2, $dst|$dst, $src2}",
2881 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2883 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2884 "adc{w}\t{$src2, $dst|$dst, $src2}",
2885 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2887 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2888 "adc{l}\t{$src2, $dst|$dst, $src2}",
2889 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2890 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2891 "adc{l}\t{$src2, $dst|$dst, $src2}",
2892 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2894 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2895 "adc{b}\t{$src, %al|%al, $src}", []>;
2896 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2897 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2898 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2899 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2901 } // Uses = [EFLAGS]
2903 // Register-Register Subtraction
2904 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2905 "sub{b}\t{$src2, $dst|$dst, $src2}",
2906 [(set GR8:$dst, EFLAGS,
2907 (X86sub_flag GR8:$src1, GR8:$src2))]>;
2908 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2909 "sub{w}\t{$src2, $dst|$dst, $src2}",
2910 [(set GR16:$dst, EFLAGS,
2911 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
2912 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2913 "sub{l}\t{$src2, $dst|$dst, $src2}",
2914 [(set GR32:$dst, EFLAGS,
2915 (X86sub_flag GR32:$src1, GR32:$src2))]>;
2917 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2918 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2919 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2920 (ins GR16:$src1, GR16:$src2),
2921 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2922 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2923 (ins GR32:$src1, GR32:$src2),
2924 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2926 // Register-Memory Subtraction
2927 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2928 (ins GR8 :$src1, i8mem :$src2),
2929 "sub{b}\t{$src2, $dst|$dst, $src2}",
2930 [(set GR8:$dst, EFLAGS,
2931 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
2932 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2933 (ins GR16:$src1, i16mem:$src2),
2934 "sub{w}\t{$src2, $dst|$dst, $src2}",
2935 [(set GR16:$dst, EFLAGS,
2936 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
2937 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2938 (ins GR32:$src1, i32mem:$src2),
2939 "sub{l}\t{$src2, $dst|$dst, $src2}",
2940 [(set GR32:$dst, EFLAGS,
2941 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
2943 // Register-Integer Subtraction
2944 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2945 (ins GR8:$src1, i8imm:$src2),
2946 "sub{b}\t{$src2, $dst|$dst, $src2}",
2947 [(set GR8:$dst, EFLAGS,
2948 (X86sub_flag GR8:$src1, imm:$src2))]>;
2949 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2950 (ins GR16:$src1, i16imm:$src2),
2951 "sub{w}\t{$src2, $dst|$dst, $src2}",
2952 [(set GR16:$dst, EFLAGS,
2953 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
2954 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2955 (ins GR32:$src1, i32imm:$src2),
2956 "sub{l}\t{$src2, $dst|$dst, $src2}",
2957 [(set GR32:$dst, EFLAGS,
2958 (X86sub_flag GR32:$src1, imm:$src2))]>;
2959 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2960 (ins GR16:$src1, i16i8imm:$src2),
2961 "sub{w}\t{$src2, $dst|$dst, $src2}",
2962 [(set GR16:$dst, EFLAGS,
2963 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2964 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2965 (ins GR32:$src1, i32i8imm:$src2),
2966 "sub{l}\t{$src2, $dst|$dst, $src2}",
2967 [(set GR32:$dst, EFLAGS,
2968 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
2970 let isTwoAddress = 0 in {
2971 // Memory-Register Subtraction
2972 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2973 "sub{b}\t{$src2, $dst|$dst, $src2}",
2974 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2975 (implicit EFLAGS)]>;
2976 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2977 "sub{w}\t{$src2, $dst|$dst, $src2}",
2978 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2979 (implicit EFLAGS)]>, OpSize;
2980 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2981 "sub{l}\t{$src2, $dst|$dst, $src2}",
2982 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2983 (implicit EFLAGS)]>;
2985 // Memory-Integer Subtraction
2986 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2987 "sub{b}\t{$src2, $dst|$dst, $src2}",
2988 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2989 (implicit EFLAGS)]>;
2990 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2991 "sub{w}\t{$src2, $dst|$dst, $src2}",
2992 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2993 (implicit EFLAGS)]>, OpSize;
2994 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2995 "sub{l}\t{$src2, $dst|$dst, $src2}",
2996 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2997 (implicit EFLAGS)]>;
2998 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2999 "sub{w}\t{$src2, $dst|$dst, $src2}",
3000 [(store (sub (load addr:$dst), i16immSExt8:$src2),
3002 (implicit EFLAGS)]>, OpSize;
3003 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3004 "sub{l}\t{$src2, $dst|$dst, $src2}",
3005 [(store (sub (load addr:$dst), i32immSExt8:$src2),
3007 (implicit EFLAGS)]>;
3009 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
3010 "sub{b}\t{$src, %al|%al, $src}", []>;
3011 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
3012 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3013 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
3014 "sub{l}\t{$src, %eax|%eax, $src}", []>;
3017 let Uses = [EFLAGS] in {
3018 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
3019 (ins GR8:$src1, GR8:$src2),
3020 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3021 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
3022 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
3023 (ins GR16:$src1, GR16:$src2),
3024 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3025 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3026 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3027 (ins GR32:$src1, GR32:$src2),
3028 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3029 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3031 let isTwoAddress = 0 in {
3032 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3033 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3034 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3035 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3036 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3037 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3039 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3040 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3041 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3042 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3043 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3044 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3045 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3046 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3047 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3049 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3050 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3051 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3053 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3054 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3055 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3056 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3057 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3058 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3060 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3061 "sbb{b}\t{$src, %al|%al, $src}", []>;
3062 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3063 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3064 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3065 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3068 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3069 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3070 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3071 (ins GR16:$src1, GR16:$src2),
3072 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3073 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3074 (ins GR32:$src1, GR32:$src2),
3075 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3077 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3078 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3079 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3080 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3081 (ins GR16:$src1, i16mem:$src2),
3082 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3083 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3085 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3086 (ins GR32:$src1, i32mem:$src2),
3087 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3088 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3089 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3090 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3091 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3092 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3093 (ins GR16:$src1, i16imm:$src2),
3094 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3095 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3096 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3097 (ins GR16:$src1, i16i8imm:$src2),
3098 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3099 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3101 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3102 (ins GR32:$src1, i32imm:$src2),
3103 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3104 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3105 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3106 (ins GR32:$src1, i32i8imm:$src2),
3107 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3108 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3109 } // Uses = [EFLAGS]
3110 } // Defs = [EFLAGS]
3112 let Defs = [EFLAGS] in {
3113 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3114 // Register-Register Signed Integer Multiply
3115 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3116 "imul{w}\t{$src2, $dst|$dst, $src2}",
3117 [(set GR16:$dst, EFLAGS,
3118 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
3119 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3120 "imul{l}\t{$src2, $dst|$dst, $src2}",
3121 [(set GR32:$dst, EFLAGS,
3122 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
3125 // Register-Memory Signed Integer Multiply
3126 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3127 (ins GR16:$src1, i16mem:$src2),
3128 "imul{w}\t{$src2, $dst|$dst, $src2}",
3129 [(set GR16:$dst, EFLAGS,
3130 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
3132 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3133 (ins GR32:$src1, i32mem:$src2),
3134 "imul{l}\t{$src2, $dst|$dst, $src2}",
3135 [(set GR32:$dst, EFLAGS,
3136 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
3137 } // Defs = [EFLAGS]
3138 } // end Two Address instructions
3140 // Suprisingly enough, these are not two address instructions!
3141 let Defs = [EFLAGS] in {
3142 // Register-Integer Signed Integer Multiply
3143 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3144 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3145 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3146 [(set GR16:$dst, EFLAGS,
3147 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
3148 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3149 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3150 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3151 [(set GR32:$dst, EFLAGS,
3152 (X86smul_flag GR32:$src1, imm:$src2))]>;
3153 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3154 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3155 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3156 [(set GR16:$dst, EFLAGS,
3157 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
3159 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3160 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3161 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3162 [(set GR32:$dst, EFLAGS,
3163 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
3165 // Memory-Integer Signed Integer Multiply
3166 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3167 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3168 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3169 [(set GR16:$dst, EFLAGS,
3170 (X86smul_flag (load addr:$src1), imm:$src2))]>,
3172 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3173 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3174 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3175 [(set GR32:$dst, EFLAGS,
3176 (X86smul_flag (load addr:$src1), imm:$src2))]>;
3177 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3178 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3179 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3180 [(set GR16:$dst, EFLAGS,
3181 (X86smul_flag (load addr:$src1),
3182 i16immSExt8:$src2))]>, OpSize;
3183 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3184 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3185 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3186 [(set GR32:$dst, EFLAGS,
3187 (X86smul_flag (load addr:$src1),
3188 i32immSExt8:$src2))]>;
3189 } // Defs = [EFLAGS]
3191 //===----------------------------------------------------------------------===//
3192 // Test instructions are just like AND, except they don't generate a result.
3194 let Defs = [EFLAGS] in {
3195 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3196 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3197 "test{b}\t{$src2, $src1|$src1, $src2}",
3198 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3199 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3200 "test{w}\t{$src2, $src1|$src1, $src2}",
3201 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3204 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3205 "test{l}\t{$src2, $src1|$src1, $src2}",
3206 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3210 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3211 "test{b}\t{$src, %al|%al, $src}", []>;
3212 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3213 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3214 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3215 "test{l}\t{$src, %eax|%eax, $src}", []>;
3217 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3218 "test{b}\t{$src2, $src1|$src1, $src2}",
3219 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3221 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3222 "test{w}\t{$src2, $src1|$src1, $src2}",
3223 [(set EFLAGS, (X86cmp (and GR16:$src1,
3224 (loadi16 addr:$src2)), 0))]>, OpSize;
3225 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3226 "test{l}\t{$src2, $src1|$src1, $src2}",
3227 [(set EFLAGS, (X86cmp (and GR32:$src1,
3228 (loadi32 addr:$src2)), 0))]>;
3230 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3231 (outs), (ins GR8:$src1, i8imm:$src2),
3232 "test{b}\t{$src2, $src1|$src1, $src2}",
3233 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3234 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3235 (outs), (ins GR16:$src1, i16imm:$src2),
3236 "test{w}\t{$src2, $src1|$src1, $src2}",
3237 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3239 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3240 (outs), (ins GR32:$src1, i32imm:$src2),
3241 "test{l}\t{$src2, $src1|$src1, $src2}",
3242 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3244 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3245 (outs), (ins i8mem:$src1, i8imm:$src2),
3246 "test{b}\t{$src2, $src1|$src1, $src2}",
3247 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3249 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3250 (outs), (ins i16mem:$src1, i16imm:$src2),
3251 "test{w}\t{$src2, $src1|$src1, $src2}",
3252 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3254 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3255 (outs), (ins i32mem:$src1, i32imm:$src2),
3256 "test{l}\t{$src2, $src1|$src1, $src2}",
3257 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3259 } // Defs = [EFLAGS]
3262 // Condition code ops, incl. set if equal/not equal/...
3263 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3264 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3265 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3266 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3268 let Uses = [EFLAGS] in {
3269 // Use sbb to materialize carry bit.
3270 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3271 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3272 // However, Pat<> can't replicate the destination reg into the inputs of the
3274 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3276 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3277 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3278 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3279 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3281 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3282 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3285 def SETEr : I<0x94, MRM0r,
3286 (outs GR8 :$dst), (ins),
3288 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3290 def SETEm : I<0x94, MRM0m,
3291 (outs), (ins i8mem:$dst),
3293 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3296 def SETNEr : I<0x95, MRM0r,
3297 (outs GR8 :$dst), (ins),
3299 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3301 def SETNEm : I<0x95, MRM0m,
3302 (outs), (ins i8mem:$dst),
3304 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3307 def SETLr : I<0x9C, MRM0r,
3308 (outs GR8 :$dst), (ins),
3310 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3311 TB; // GR8 = < signed
3312 def SETLm : I<0x9C, MRM0m,
3313 (outs), (ins i8mem:$dst),
3315 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3316 TB; // [mem8] = < signed
3318 def SETGEr : I<0x9D, MRM0r,
3319 (outs GR8 :$dst), (ins),
3321 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3322 TB; // GR8 = >= signed
3323 def SETGEm : I<0x9D, MRM0m,
3324 (outs), (ins i8mem:$dst),
3326 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3327 TB; // [mem8] = >= signed
3329 def SETLEr : I<0x9E, MRM0r,
3330 (outs GR8 :$dst), (ins),
3332 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3333 TB; // GR8 = <= signed
3334 def SETLEm : I<0x9E, MRM0m,
3335 (outs), (ins i8mem:$dst),
3337 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3338 TB; // [mem8] = <= signed
3340 def SETGr : I<0x9F, MRM0r,
3341 (outs GR8 :$dst), (ins),
3343 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3344 TB; // GR8 = > signed
3345 def SETGm : I<0x9F, MRM0m,
3346 (outs), (ins i8mem:$dst),
3348 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3349 TB; // [mem8] = > signed
3351 def SETBr : I<0x92, MRM0r,
3352 (outs GR8 :$dst), (ins),
3354 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3355 TB; // GR8 = < unsign
3356 def SETBm : I<0x92, MRM0m,
3357 (outs), (ins i8mem:$dst),
3359 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3360 TB; // [mem8] = < unsign
3362 def SETAEr : I<0x93, MRM0r,
3363 (outs GR8 :$dst), (ins),
3365 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3366 TB; // GR8 = >= unsign
3367 def SETAEm : I<0x93, MRM0m,
3368 (outs), (ins i8mem:$dst),
3370 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3371 TB; // [mem8] = >= unsign
3373 def SETBEr : I<0x96, MRM0r,
3374 (outs GR8 :$dst), (ins),
3376 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3377 TB; // GR8 = <= unsign
3378 def SETBEm : I<0x96, MRM0m,
3379 (outs), (ins i8mem:$dst),
3381 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3382 TB; // [mem8] = <= unsign
3384 def SETAr : I<0x97, MRM0r,
3385 (outs GR8 :$dst), (ins),
3387 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3388 TB; // GR8 = > signed
3389 def SETAm : I<0x97, MRM0m,
3390 (outs), (ins i8mem:$dst),
3392 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3393 TB; // [mem8] = > signed
3395 def SETSr : I<0x98, MRM0r,
3396 (outs GR8 :$dst), (ins),
3398 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3399 TB; // GR8 = <sign bit>
3400 def SETSm : I<0x98, MRM0m,
3401 (outs), (ins i8mem:$dst),
3403 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3404 TB; // [mem8] = <sign bit>
3405 def SETNSr : I<0x99, MRM0r,
3406 (outs GR8 :$dst), (ins),
3408 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3409 TB; // GR8 = !<sign bit>
3410 def SETNSm : I<0x99, MRM0m,
3411 (outs), (ins i8mem:$dst),
3413 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3414 TB; // [mem8] = !<sign bit>
3416 def SETPr : I<0x9A, MRM0r,
3417 (outs GR8 :$dst), (ins),
3419 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3421 def SETPm : I<0x9A, MRM0m,
3422 (outs), (ins i8mem:$dst),
3424 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3425 TB; // [mem8] = parity
3426 def SETNPr : I<0x9B, MRM0r,
3427 (outs GR8 :$dst), (ins),
3429 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3430 TB; // GR8 = not parity
3431 def SETNPm : I<0x9B, MRM0m,
3432 (outs), (ins i8mem:$dst),
3434 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3435 TB; // [mem8] = not parity
3437 def SETOr : I<0x90, MRM0r,
3438 (outs GR8 :$dst), (ins),
3440 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3441 TB; // GR8 = overflow
3442 def SETOm : I<0x90, MRM0m,
3443 (outs), (ins i8mem:$dst),
3445 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3446 TB; // [mem8] = overflow
3447 def SETNOr : I<0x91, MRM0r,
3448 (outs GR8 :$dst), (ins),
3450 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3451 TB; // GR8 = not overflow
3452 def SETNOm : I<0x91, MRM0m,
3453 (outs), (ins i8mem:$dst),
3455 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3456 TB; // [mem8] = not overflow
3457 } // Uses = [EFLAGS]
3460 // Integer comparisons
3461 let Defs = [EFLAGS] in {
3462 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3463 "cmp{b}\t{$src, %al|%al, $src}", []>;
3464 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3465 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3466 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3467 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3469 def CMP8rr : I<0x38, MRMDestReg,
3470 (outs), (ins GR8 :$src1, GR8 :$src2),
3471 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3472 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3473 def CMP16rr : I<0x39, MRMDestReg,
3474 (outs), (ins GR16:$src1, GR16:$src2),
3475 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3476 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3477 def CMP32rr : I<0x39, MRMDestReg,
3478 (outs), (ins GR32:$src1, GR32:$src2),
3479 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3480 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3481 def CMP8mr : I<0x38, MRMDestMem,
3482 (outs), (ins i8mem :$src1, GR8 :$src2),
3483 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3484 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3485 def CMP16mr : I<0x39, MRMDestMem,
3486 (outs), (ins i16mem:$src1, GR16:$src2),
3487 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3488 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3490 def CMP32mr : I<0x39, MRMDestMem,
3491 (outs), (ins i32mem:$src1, GR32:$src2),
3492 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3493 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3494 def CMP8rm : I<0x3A, MRMSrcMem,
3495 (outs), (ins GR8 :$src1, i8mem :$src2),
3496 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3497 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3498 def CMP16rm : I<0x3B, MRMSrcMem,
3499 (outs), (ins GR16:$src1, i16mem:$src2),
3500 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3501 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3503 def CMP32rm : I<0x3B, MRMSrcMem,
3504 (outs), (ins GR32:$src1, i32mem:$src2),
3505 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3506 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3508 // These are alternate spellings for use by the disassembler, we mark them as
3509 // code gen only to ensure they aren't matched by the assembler.
3510 let isCodeGenOnly = 1 in {
3511 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3512 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3513 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3514 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3515 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3516 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3519 def CMP8ri : Ii8<0x80, MRM7r,
3520 (outs), (ins GR8:$src1, i8imm:$src2),
3521 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3522 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3523 def CMP16ri : Ii16<0x81, MRM7r,
3524 (outs), (ins GR16:$src1, i16imm:$src2),
3525 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3526 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3527 def CMP32ri : Ii32<0x81, MRM7r,
3528 (outs), (ins GR32:$src1, i32imm:$src2),
3529 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3530 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3531 def CMP8mi : Ii8 <0x80, MRM7m,
3532 (outs), (ins i8mem :$src1, i8imm :$src2),
3533 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3534 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3535 def CMP16mi : Ii16<0x81, MRM7m,
3536 (outs), (ins i16mem:$src1, i16imm:$src2),
3537 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3538 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3540 def CMP32mi : Ii32<0x81, MRM7m,
3541 (outs), (ins i32mem:$src1, i32imm:$src2),
3542 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3543 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3544 def CMP16ri8 : Ii8<0x83, MRM7r,
3545 (outs), (ins GR16:$src1, i16i8imm:$src2),
3546 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3547 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3549 def CMP16mi8 : Ii8<0x83, MRM7m,
3550 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3551 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3552 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3553 i16immSExt8:$src2))]>, OpSize;
3554 def CMP32mi8 : Ii8<0x83, MRM7m,
3555 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3556 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3557 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3558 i32immSExt8:$src2))]>;
3559 def CMP32ri8 : Ii8<0x83, MRM7r,
3560 (outs), (ins GR32:$src1, i32i8imm:$src2),
3561 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3562 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3563 } // Defs = [EFLAGS]
3566 // TODO: BTC, BTR, and BTS
3567 let Defs = [EFLAGS] in {
3568 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3569 "bt{w}\t{$src2, $src1|$src1, $src2}",
3570 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3571 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3572 "bt{l}\t{$src2, $src1|$src1, $src2}",
3573 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3575 // Unlike with the register+register form, the memory+register form of the
3576 // bt instruction does not ignore the high bits of the index. From ISel's
3577 // perspective, this is pretty bizarre. Make these instructions disassembly
3580 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3581 "bt{w}\t{$src2, $src1|$src1, $src2}",
3582 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3583 // (implicit EFLAGS)]
3585 >, OpSize, TB, Requires<[FastBTMem]>;
3586 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3587 "bt{l}\t{$src2, $src1|$src1, $src2}",
3588 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3589 // (implicit EFLAGS)]
3591 >, TB, Requires<[FastBTMem]>;
3593 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3594 "bt{w}\t{$src2, $src1|$src1, $src2}",
3595 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3597 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3598 "bt{l}\t{$src2, $src1|$src1, $src2}",
3599 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3600 // Note that these instructions don't need FastBTMem because that
3601 // only applies when the other operand is in a register. When it's
3602 // an immediate, bt is still fast.
3603 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3604 "bt{w}\t{$src2, $src1|$src1, $src2}",
3605 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3607 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3608 "bt{l}\t{$src2, $src1|$src1, $src2}",
3609 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3612 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3613 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3614 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3615 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3616 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3617 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3618 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3619 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3620 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3621 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3622 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3623 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3624 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3625 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3626 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3627 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3629 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3630 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3631 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3632 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3633 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3634 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3635 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3636 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3637 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3638 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3639 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3640 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3641 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3642 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3643 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3644 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3646 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3647 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3648 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3649 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3650 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3651 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3652 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3653 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3654 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3655 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3656 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3657 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3658 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3659 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3660 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3661 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3662 } // Defs = [EFLAGS]
3664 // Sign/Zero extenders
3665 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3666 // of the register here. This has a smaller encoding and avoids a
3667 // partial-register update. Actual movsbw included for the disassembler.
3668 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3669 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3670 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3671 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3672 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3673 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3674 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3675 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3676 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3677 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3678 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3679 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3680 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3681 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3682 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3683 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3684 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3685 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3686 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3687 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3689 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3690 // of the register here. This has a smaller encoding and avoids a
3691 // partial-register update. Actual movzbw included for the disassembler.
3692 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3693 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3694 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3695 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3696 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3697 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3698 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3699 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3700 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3701 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3702 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3703 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3704 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3705 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3706 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3707 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3708 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3709 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3710 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3711 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3713 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3714 // except that they use GR32_NOREX for the output operand register class
3715 // instead of GR32. This allows them to operate on h registers on x86-64.
3716 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3717 (outs GR32_NOREX:$dst), (ins GR8:$src),
3718 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3721 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3722 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3723 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3726 let neverHasSideEffects = 1 in {
3727 let Defs = [AX], Uses = [AL] in
3728 def CBW : I<0x98, RawFrm, (outs), (ins),
3729 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3730 let Defs = [EAX], Uses = [AX] in
3731 def CWDE : I<0x98, RawFrm, (outs), (ins),
3732 "{cwtl|cwde}", []>; // EAX = signext(AX)
3734 let Defs = [AX,DX], Uses = [AX] in
3735 def CWD : I<0x99, RawFrm, (outs), (ins),
3736 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3737 let Defs = [EAX,EDX], Uses = [EAX] in
3738 def CDQ : I<0x99, RawFrm, (outs), (ins),
3739 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3742 //===----------------------------------------------------------------------===//
3743 // Alias Instructions
3744 //===----------------------------------------------------------------------===//
3746 // Alias instructions that map movr0 to xor.
3747 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3748 // FIXME: Set encoding to pseudo.
3749 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3750 isCodeGenOnly = 1 in {
3751 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3752 [(set GR8:$dst, 0)]>;
3754 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3755 // encoding and avoids a partial-register update sometimes, but doing so
3756 // at isel time interferes with rematerialization in the current register
3757 // allocator. For now, this is rewritten when the instruction is lowered
3759 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3761 [(set GR16:$dst, 0)]>, OpSize;
3763 // FIXME: Set encoding to pseudo.
3764 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3765 [(set GR32:$dst, 0)]>;
3768 //===----------------------------------------------------------------------===//
3769 // Thread Local Storage Instructions
3772 // All calls clobber the non-callee saved registers. ESP is marked as
3773 // a use to prevent stack-pointer assignments that appear immediately
3774 // before calls from potentially appearing dead.
3775 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3776 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3777 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3778 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3780 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3781 "leal\t$sym, %eax; "
3782 "call\t___tls_get_addr@PLT",
3783 [(X86tlsaddr tls32addr:$sym)]>,
3784 Requires<[In32BitMode]>;
3786 let AddedComplexity = 5, isCodeGenOnly = 1 in
3787 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3788 "movl\t%gs:$src, $dst",
3789 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3791 let AddedComplexity = 5, isCodeGenOnly = 1 in
3792 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3793 "movl\t%fs:$src, $dst",
3794 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3796 //===----------------------------------------------------------------------===//
3797 // EH Pseudo Instructions
3799 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3800 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3801 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3802 "ret\t#eh_return, addr: $addr",
3803 [(X86ehret GR32:$addr)]>;
3807 //===----------------------------------------------------------------------===//
3811 // Atomic swap. These are just normal xchg instructions. But since a memory
3812 // operand is referenced, the atomicity is ensured.
3813 let Constraints = "$val = $dst" in {
3814 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3815 (ins GR32:$val, i32mem:$ptr),
3816 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3817 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3818 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3819 (ins GR16:$val, i16mem:$ptr),
3820 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3821 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3823 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3824 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3825 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3827 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3828 "xchg{l}\t{$val, $src|$src, $val}", []>;
3829 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3830 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3831 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3832 "xchg{b}\t{$val, $src|$src, $val}", []>;
3835 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3836 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3837 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3838 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3840 // Atomic compare and swap.
3841 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3842 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3844 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3845 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3847 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3848 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3851 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3854 let Defs = [AX, EFLAGS], Uses = [AX] in {
3855 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3857 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3858 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3860 let Defs = [AL, EFLAGS], Uses = [AL] in {
3861 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3863 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3864 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3867 // Atomic exchange and add
3868 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3869 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3871 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3872 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3874 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3876 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3877 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3879 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3881 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3882 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3886 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3887 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3888 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3889 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3890 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3891 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3893 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3894 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3895 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3896 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3897 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3898 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3900 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3901 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3902 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3903 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3904 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3905 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3907 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3908 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3909 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3910 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3911 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3912 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3914 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3915 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3916 "cmpxchg8b\t$dst", []>, TB;
3918 // Optimized codegen when the non-memory output is not used.
3919 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3920 let Defs = [EFLAGS] in {
3921 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3923 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3924 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3926 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3927 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3929 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3930 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3932 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3933 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3935 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3936 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3938 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3939 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3941 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3942 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3944 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3946 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3948 "inc{b}\t$dst", []>, LOCK;
3949 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3951 "inc{w}\t$dst", []>, OpSize, LOCK;
3952 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3954 "inc{l}\t$dst", []>, LOCK;
3956 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3958 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3959 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3961 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3962 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3964 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3965 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3967 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3968 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3970 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3971 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3973 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3974 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3976 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3977 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3979 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3981 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3983 "dec{b}\t$dst", []>, LOCK;
3984 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3986 "dec{w}\t$dst", []>, OpSize, LOCK;
3987 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3989 "dec{l}\t$dst", []>, LOCK;
3992 // Atomic exchange, and, or, xor
3993 let Constraints = "$val = $dst", Defs = [EFLAGS],
3994 usesCustomInserter = 1 in {
3995 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3996 "#ATOMAND32 PSEUDO!",
3997 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3998 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3999 "#ATOMOR32 PSEUDO!",
4000 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
4001 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4002 "#ATOMXOR32 PSEUDO!",
4003 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
4004 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4005 "#ATOMNAND32 PSEUDO!",
4006 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
4007 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
4008 "#ATOMMIN32 PSEUDO!",
4009 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
4010 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4011 "#ATOMMAX32 PSEUDO!",
4012 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
4013 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4014 "#ATOMUMIN32 PSEUDO!",
4015 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
4016 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4017 "#ATOMUMAX32 PSEUDO!",
4018 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
4020 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4021 "#ATOMAND16 PSEUDO!",
4022 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4023 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4024 "#ATOMOR16 PSEUDO!",
4025 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4026 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4027 "#ATOMXOR16 PSEUDO!",
4028 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4029 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4030 "#ATOMNAND16 PSEUDO!",
4031 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4032 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4033 "#ATOMMIN16 PSEUDO!",
4034 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4035 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4036 "#ATOMMAX16 PSEUDO!",
4037 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4038 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4039 "#ATOMUMIN16 PSEUDO!",
4040 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4041 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4042 "#ATOMUMAX16 PSEUDO!",
4043 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4045 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4046 "#ATOMAND8 PSEUDO!",
4047 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4048 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4050 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4051 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4052 "#ATOMXOR8 PSEUDO!",
4053 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4054 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4055 "#ATOMNAND8 PSEUDO!",
4056 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4059 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4060 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4061 Uses = [EAX, EBX, ECX, EDX],
4062 mayLoad = 1, mayStore = 1,
4063 usesCustomInserter = 1 in {
4064 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4065 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4066 "#ATOMAND6432 PSEUDO!", []>;
4067 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4068 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4069 "#ATOMOR6432 PSEUDO!", []>;
4070 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4071 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4072 "#ATOMXOR6432 PSEUDO!", []>;
4073 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4074 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4075 "#ATOMNAND6432 PSEUDO!", []>;
4076 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4077 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4078 "#ATOMADD6432 PSEUDO!", []>;
4079 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4080 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4081 "#ATOMSUB6432 PSEUDO!", []>;
4082 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4083 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4084 "#ATOMSWAP6432 PSEUDO!", []>;
4087 // Segmentation support instructions.
4089 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4090 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4091 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4092 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4094 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4095 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4096 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4097 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4098 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4100 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4101 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4102 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4103 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4104 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4105 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4106 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4107 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4109 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4111 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4112 "str{w}\t{$dst}", []>, TB;
4113 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4114 "str{w}\t{$dst}", []>, TB;
4115 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4116 "ltr{w}\t{$src}", []>, TB;
4117 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4118 "ltr{w}\t{$src}", []>, TB;
4120 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4121 "push{w}\t%fs", []>, OpSize, TB;
4122 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4123 "push{l}\t%fs", []>, TB;
4124 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4125 "push{w}\t%gs", []>, OpSize, TB;
4126 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4127 "push{l}\t%gs", []>, TB;
4129 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4130 "pop{w}\t%fs", []>, OpSize, TB;
4131 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4132 "pop{l}\t%fs", []>, TB;
4133 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4134 "pop{w}\t%gs", []>, OpSize, TB;
4135 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4136 "pop{l}\t%gs", []>, TB;
4138 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4139 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4140 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4141 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4142 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4143 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4144 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4145 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4146 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4147 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4148 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4149 "les{l}\t{$src, $dst|$dst, $src}", []>;
4150 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4151 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4152 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4153 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4154 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4155 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4156 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4157 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4159 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4160 "verr\t$seg", []>, TB;
4161 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4162 "verr\t$seg", []>, TB;
4163 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4164 "verw\t$seg", []>, TB;
4165 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4166 "verw\t$seg", []>, TB;
4168 // Descriptor-table support instructions
4170 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4171 "sgdt\t$dst", []>, TB;
4172 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4173 "sidt\t$dst", []>, TB;
4174 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4175 "sldt{w}\t$dst", []>, TB;
4176 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4177 "sldt{w}\t$dst", []>, TB;
4178 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4179 "lgdt\t$src", []>, TB;
4180 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4181 "lidt\t$src", []>, TB;
4182 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4183 "lldt{w}\t$src", []>, TB;
4184 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4185 "lldt{w}\t$src", []>, TB;
4187 // Lock instruction prefix
4188 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4190 // Repeat string operation instruction prefixes
4191 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4192 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4193 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4194 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4195 // Repeat while not equal (used with CMPS and SCAS)
4196 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4199 // Segment override instruction prefixes
4200 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4201 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4202 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4203 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4204 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4205 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4207 // String manipulation instructions
4209 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4210 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4211 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4213 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4214 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4215 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4217 // CPU flow control instructions
4219 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4220 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4222 // FPU control instructions
4224 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4226 // Flag instructions
4228 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4229 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4230 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4231 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4232 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4233 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4234 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4236 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4238 // Table lookup instructions
4240 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4242 // Specialized register support
4244 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4245 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4246 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4248 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4249 "smsw{w}\t$dst", []>, OpSize, TB;
4250 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4251 "smsw{l}\t$dst", []>, TB;
4252 // For memory operands, there is only a 16-bit form
4253 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4254 "smsw{w}\t$dst", []>, TB;
4256 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4257 "lmsw{w}\t$src", []>, TB;
4258 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4259 "lmsw{w}\t$src", []>, TB;
4261 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4263 // Cache instructions
4265 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4266 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4271 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4273 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4275 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4276 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4277 "vmclear\t$vmcs", []>, OpSize, TB;
4279 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4281 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4282 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4283 "vmptrld\t$vmcs", []>, TB;
4284 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4285 "vmptrst\t$vmcs", []>, TB;
4286 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4287 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4288 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4289 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4290 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4291 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4292 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4293 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4294 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4295 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4296 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4297 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4298 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4299 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4300 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4301 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4303 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4304 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4305 "vmxon\t{$vmxon}", []>, XS;
4307 //===----------------------------------------------------------------------===//
4308 // Non-Instruction Patterns
4309 //===----------------------------------------------------------------------===//
4311 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4312 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4313 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4314 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4315 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4316 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4317 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4319 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4320 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4321 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4322 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4323 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4324 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4325 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4326 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4327 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4328 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4330 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4331 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4332 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4333 (MOV32mi addr:$dst, texternalsym:$src)>;
4334 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4335 (MOV32mi addr:$dst, tblockaddress:$src)>;
4339 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4340 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4341 Requires<[In32BitMode]>;
4343 // FIXME: This is disabled for 32-bit PIC mode because the global base
4344 // register which is part of the address mode may be assigned a
4345 // callee-saved register.
4346 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4347 (TCRETURNmi addr:$dst, imm:$off)>,
4348 Requires<[In32BitMode, IsNotPIC]>;
4350 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4351 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4352 Requires<[In32BitMode]>;
4354 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4355 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4356 Requires<[In32BitMode]>;
4358 // Normal calls, with various flavors of addresses.
4359 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4360 (CALLpcrel32 tglobaladdr:$dst)>;
4361 def : Pat<(X86call (i32 texternalsym:$dst)),
4362 (CALLpcrel32 texternalsym:$dst)>;
4363 def : Pat<(X86call (i32 imm:$dst)),
4364 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4366 // X86 specific add which produces a flag.
4367 def : Pat<(addc GR32:$src1, GR32:$src2),
4368 (ADD32rr GR32:$src1, GR32:$src2)>;
4369 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4370 (ADD32rm GR32:$src1, addr:$src2)>;
4371 def : Pat<(addc GR32:$src1, imm:$src2),
4372 (ADD32ri GR32:$src1, imm:$src2)>;
4373 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4374 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4376 def : Pat<(subc GR32:$src1, GR32:$src2),
4377 (SUB32rr GR32:$src1, GR32:$src2)>;
4378 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4379 (SUB32rm GR32:$src1, addr:$src2)>;
4380 def : Pat<(subc GR32:$src1, imm:$src2),
4381 (SUB32ri GR32:$src1, imm:$src2)>;
4382 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4383 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4387 // TEST R,R is smaller than CMP R,0
4388 def : Pat<(X86cmp GR8:$src1, 0),
4389 (TEST8rr GR8:$src1, GR8:$src1)>;
4390 def : Pat<(X86cmp GR16:$src1, 0),
4391 (TEST16rr GR16:$src1, GR16:$src1)>;
4392 def : Pat<(X86cmp GR32:$src1, 0),
4393 (TEST32rr GR32:$src1, GR32:$src1)>;
4395 // Conditional moves with folded loads with operands swapped and conditions
4397 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4398 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4399 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4400 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4401 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4402 (CMOVB16rm GR16:$src2, addr:$src1)>;
4403 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4404 (CMOVB32rm GR32:$src2, addr:$src1)>;
4405 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4406 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4407 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4408 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4409 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4410 (CMOVE16rm GR16:$src2, addr:$src1)>;
4411 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4412 (CMOVE32rm GR32:$src2, addr:$src1)>;
4413 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4414 (CMOVA16rm GR16:$src2, addr:$src1)>;
4415 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4416 (CMOVA32rm GR32:$src2, addr:$src1)>;
4417 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4418 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4419 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4420 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4421 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4422 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4423 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4424 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4425 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4426 (CMOVL16rm GR16:$src2, addr:$src1)>;
4427 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4428 (CMOVL32rm GR32:$src2, addr:$src1)>;
4429 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4430 (CMOVG16rm GR16:$src2, addr:$src1)>;
4431 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4432 (CMOVG32rm GR32:$src2, addr:$src1)>;
4433 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4434 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4435 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4436 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4437 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4438 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4439 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4440 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4441 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4442 (CMOVP16rm GR16:$src2, addr:$src1)>;
4443 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4444 (CMOVP32rm GR32:$src2, addr:$src1)>;
4445 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4446 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4447 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4448 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4449 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4450 (CMOVS16rm GR16:$src2, addr:$src1)>;
4451 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4452 (CMOVS32rm GR32:$src2, addr:$src1)>;
4453 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4454 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4455 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4456 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4457 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4458 (CMOVO16rm GR16:$src2, addr:$src1)>;
4459 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4460 (CMOVO32rm GR32:$src2, addr:$src1)>;
4462 // zextload bool -> zextload byte
4463 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4464 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4465 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4467 // extload bool -> extload byte
4468 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4469 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4470 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4471 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4472 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4473 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4475 // anyext. Define these to do an explicit zero-extend to
4476 // avoid partial-register updates.
4477 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4478 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4479 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
4481 //===----------------------------------------------------------------------===//
4483 //===----------------------------------------------------------------------===//
4485 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4486 // +128 doesn't, so in this special case use a sub instead of an add.
4487 def : Pat<(add GR16:$src1, 128),
4488 (SUB16ri8 GR16:$src1, -128)>;
4489 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4490 (SUB16mi8 addr:$dst, -128)>;
4491 def : Pat<(add GR32:$src1, 128),
4492 (SUB32ri8 GR32:$src1, -128)>;
4493 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4494 (SUB32mi8 addr:$dst, -128)>;
4496 // r & (2^16-1) ==> movz
4497 def : Pat<(and GR32:$src1, 0xffff),
4498 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4499 // r & (2^8-1) ==> movz
4500 def : Pat<(and GR32:$src1, 0xff),
4501 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4504 Requires<[In32BitMode]>;
4505 // r & (2^8-1) ==> movz
4506 def : Pat<(and GR16:$src1, 0xff),
4507 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4510 Requires<[In32BitMode]>;
4512 // sext_inreg patterns
4513 def : Pat<(sext_inreg GR32:$src, i16),
4514 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4515 def : Pat<(sext_inreg GR32:$src, i8),
4516 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4519 Requires<[In32BitMode]>;
4520 def : Pat<(sext_inreg GR16:$src, i8),
4521 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4524 Requires<[In32BitMode]>;
4527 def : Pat<(i16 (trunc GR32:$src)),
4528 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4529 def : Pat<(i8 (trunc GR32:$src)),
4530 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4532 Requires<[In32BitMode]>;
4533 def : Pat<(i8 (trunc GR16:$src)),
4534 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4536 Requires<[In32BitMode]>;
4538 // h-register tricks
4539 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4540 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4541 x86_subreg_8bit_hi)>,
4542 Requires<[In32BitMode]>;
4543 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4544 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4545 x86_subreg_8bit_hi)>,
4546 Requires<[In32BitMode]>;
4547 def : Pat<(srl GR16:$src, (i8 8)),
4550 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4551 x86_subreg_8bit_hi)),
4553 Requires<[In32BitMode]>;
4554 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4555 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4557 x86_subreg_8bit_hi))>,
4558 Requires<[In32BitMode]>;
4559 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4560 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4562 x86_subreg_8bit_hi))>,
4563 Requires<[In32BitMode]>;
4564 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4565 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4567 x86_subreg_8bit_hi))>,
4568 Requires<[In32BitMode]>;
4570 // (shl x, 1) ==> (add x, x)
4571 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4572 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4573 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4575 // (shl x (and y, 31)) ==> (shl x, y)
4576 def : Pat<(shl GR8:$src1, (and CL, 31)),
4577 (SHL8rCL GR8:$src1)>;
4578 def : Pat<(shl GR16:$src1, (and CL, 31)),
4579 (SHL16rCL GR16:$src1)>;
4580 def : Pat<(shl GR32:$src1, (and CL, 31)),
4581 (SHL32rCL GR32:$src1)>;
4582 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4583 (SHL8mCL addr:$dst)>;
4584 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4585 (SHL16mCL addr:$dst)>;
4586 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4587 (SHL32mCL addr:$dst)>;
4589 def : Pat<(srl GR8:$src1, (and CL, 31)),
4590 (SHR8rCL GR8:$src1)>;
4591 def : Pat<(srl GR16:$src1, (and CL, 31)),
4592 (SHR16rCL GR16:$src1)>;
4593 def : Pat<(srl GR32:$src1, (and CL, 31)),
4594 (SHR32rCL GR32:$src1)>;
4595 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4596 (SHR8mCL addr:$dst)>;
4597 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4598 (SHR16mCL addr:$dst)>;
4599 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4600 (SHR32mCL addr:$dst)>;
4602 def : Pat<(sra GR8:$src1, (and CL, 31)),
4603 (SAR8rCL GR8:$src1)>;
4604 def : Pat<(sra GR16:$src1, (and CL, 31)),
4605 (SAR16rCL GR16:$src1)>;
4606 def : Pat<(sra GR32:$src1, (and CL, 31)),
4607 (SAR32rCL GR32:$src1)>;
4608 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4609 (SAR8mCL addr:$dst)>;
4610 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4611 (SAR16mCL addr:$dst)>;
4612 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4613 (SAR32mCL addr:$dst)>;
4615 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
4616 def : Pat<(or (srl GR32:$src1, CL:$amt),
4617 (shl GR32:$src2, (sub 32, CL:$amt))),
4618 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4620 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
4621 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4622 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4624 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
4625 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4626 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4628 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4629 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4631 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4633 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm/*:$amt2*/)),
4634 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4636 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
4637 GR32:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4638 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4640 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
4641 def : Pat<(or (shl GR32:$src1, CL:$amt),
4642 (srl GR32:$src2, (sub 32, CL:$amt))),
4643 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4645 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
4646 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4647 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4649 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
4650 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4651 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4653 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4654 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4656 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4658 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm/*:$amt2*/)),
4659 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4661 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
4662 GR32:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4663 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4665 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
4666 def : Pat<(or (srl GR16:$src1, CL:$amt),
4667 (shl GR16:$src2, (sub 16, CL:$amt))),
4668 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4670 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
4671 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4672 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4674 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
4675 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4676 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4678 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4679 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4681 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4683 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm/*:$amt2*/)),
4684 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4686 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
4687 GR16:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4688 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4690 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
4691 def : Pat<(or (shl GR16:$src1, CL:$amt),
4692 (srl GR16:$src2, (sub 16, CL:$amt))),
4693 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4695 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
4696 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4697 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4699 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
4700 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4701 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4703 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4704 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4706 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4708 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm/*:$amt2*/)),
4709 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4711 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
4712 GR16:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4713 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4715 // (anyext (setcc_carry)) -> (setcc_carry)
4716 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4718 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4721 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4722 let AddedComplexity = 5 in { // Try this before the selecting to OR
4723 def : Pat<(or_is_add GR16:$src1, imm:$src2),
4724 (ADD16ri GR16:$src1, imm:$src2)>;
4725 def : Pat<(or_is_add GR32:$src1, imm:$src2),
4726 (ADD32ri GR32:$src1, imm:$src2)>;
4727 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
4728 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4729 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
4730 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4731 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
4732 (ADD16rr GR16:$src1, GR16:$src2)>;
4733 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
4734 (ADD32rr GR32:$src1, GR32:$src2)>;
4735 } // AddedComplexity
4737 //===----------------------------------------------------------------------===//
4738 // EFLAGS-defining Patterns
4739 //===----------------------------------------------------------------------===//
4742 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
4743 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
4744 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
4747 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
4748 (ADD8rm GR8:$src1, addr:$src2)>;
4749 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
4750 (ADD16rm GR16:$src1, addr:$src2)>;
4751 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
4752 (ADD32rm GR32:$src1, addr:$src2)>;
4755 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
4756 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
4757 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
4758 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
4759 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4760 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
4761 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4764 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
4765 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
4766 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
4769 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
4770 (SUB8rm GR8:$src1, addr:$src2)>;
4771 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
4772 (SUB16rm GR16:$src1, addr:$src2)>;
4773 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
4774 (SUB32rm GR32:$src1, addr:$src2)>;
4777 def : Pat<(sub GR8:$src1, imm:$src2),
4778 (SUB8ri GR8:$src1, imm:$src2)>;
4779 def : Pat<(sub GR16:$src1, imm:$src2),
4780 (SUB16ri GR16:$src1, imm:$src2)>;
4781 def : Pat<(sub GR32:$src1, imm:$src2),
4782 (SUB32ri GR32:$src1, imm:$src2)>;
4783 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
4784 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4785 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
4786 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4789 def : Pat<(mul GR16:$src1, GR16:$src2),
4790 (IMUL16rr GR16:$src1, GR16:$src2)>;
4791 def : Pat<(mul GR32:$src1, GR32:$src2),
4792 (IMUL32rr GR32:$src1, GR32:$src2)>;
4795 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
4796 (IMUL16rm GR16:$src1, addr:$src2)>;
4797 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
4798 (IMUL32rm GR32:$src1, addr:$src2)>;
4801 def : Pat<(mul GR16:$src1, imm:$src2),
4802 (IMUL16rri GR16:$src1, imm:$src2)>;
4803 def : Pat<(mul GR32:$src1, imm:$src2),
4804 (IMUL32rri GR32:$src1, imm:$src2)>;
4805 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
4806 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4807 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
4808 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4810 // reg = mul mem, imm
4811 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
4812 (IMUL16rmi addr:$src1, imm:$src2)>;
4813 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
4814 (IMUL32rmi addr:$src1, imm:$src2)>;
4815 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
4816 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4817 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
4818 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4820 // Optimize multiply by 2 with EFLAGS result.
4821 let AddedComplexity = 2 in {
4822 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
4823 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
4826 // Patterns for nodes that do not produce flags, for instructions that do.
4829 def : Pat<(add GR8:$src , 1), (INC8r GR8:$src)>;
4830 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4831 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4834 def : Pat<(add GR8:$src , -1), (DEC8r GR8:$src)>;
4835 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4836 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4839 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
4840 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
4841 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
4844 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
4845 (OR8rm GR8:$src1, addr:$src2)>;
4846 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
4847 (OR16rm GR16:$src1, addr:$src2)>;
4848 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
4849 (OR32rm GR32:$src1, addr:$src2)>;
4852 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
4853 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
4854 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
4855 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
4856 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4857 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
4858 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4861 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
4862 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
4863 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
4866 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
4867 (XOR8rm GR8:$src1, addr:$src2)>;
4868 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
4869 (XOR16rm GR16:$src1, addr:$src2)>;
4870 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
4871 (XOR32rm GR32:$src1, addr:$src2)>;
4874 def : Pat<(xor GR8:$src1, imm:$src2),
4875 (XOR8ri GR8:$src1, imm:$src2)>;
4876 def : Pat<(xor GR16:$src1, imm:$src2),
4877 (XOR16ri GR16:$src1, imm:$src2)>;
4878 def : Pat<(xor GR32:$src1, imm:$src2),
4879 (XOR32ri GR32:$src1, imm:$src2)>;
4880 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
4881 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4882 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
4883 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4886 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
4887 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
4888 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
4891 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
4892 (AND8rm GR8:$src1, addr:$src2)>;
4893 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
4894 (AND16rm GR16:$src1, addr:$src2)>;
4895 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
4896 (AND32rm GR32:$src1, addr:$src2)>;
4899 def : Pat<(and GR8:$src1, imm:$src2),
4900 (AND8ri GR8:$src1, imm:$src2)>;
4901 def : Pat<(and GR16:$src1, imm:$src2),
4902 (AND16ri GR16:$src1, imm:$src2)>;
4903 def : Pat<(and GR32:$src1, imm:$src2),
4904 (AND32ri GR32:$src1, imm:$src2)>;
4905 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
4906 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4907 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
4908 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4910 // -disable-16bit support.
4911 def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
4912 (MOV16mi addr:$dst, imm:$src)>;
4913 def : Pat<(truncstorei16 GR32:$src, addr:$dst),
4914 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4915 def : Pat<(i32 (sextloadi16 addr:$dst)),
4916 (MOVSX32rm16 addr:$dst)>;
4917 def : Pat<(i32 (zextloadi16 addr:$dst)),
4918 (MOVZX32rm16 addr:$dst)>;
4919 def : Pat<(i32 (extloadi16 addr:$dst)),
4920 (MOVZX32rm16 addr:$dst)>;
4922 //===----------------------------------------------------------------------===//
4923 // Floating Point Stack Support
4924 //===----------------------------------------------------------------------===//
4926 include "X86InstrFPStack.td"
4928 //===----------------------------------------------------------------------===//
4930 //===----------------------------------------------------------------------===//
4932 include "X86Instr64bit.td"
4934 //===----------------------------------------------------------------------===//
4935 // SIMD support (SSE, MMX and AVX)
4936 //===----------------------------------------------------------------------===//
4938 include "X86InstrFragmentsSIMD.td"
4940 //===----------------------------------------------------------------------===//
4941 // XMM Floating point support (requires SSE / SSE2)
4942 //===----------------------------------------------------------------------===//
4944 include "X86InstrSSE.td"
4946 //===----------------------------------------------------------------------===//
4947 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4948 //===----------------------------------------------------------------------===//
4950 include "X86InstrMMX.td"