1 //===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
79 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
81 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
82 def SDT_X86MEMBARRIERNoSSE : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
84 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
86 def X86MemBarrierNoSSE : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIERNoSSE,
88 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
90 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
92 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
96 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
97 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
98 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
99 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
101 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
102 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
104 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
105 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
107 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
108 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
110 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
111 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
114 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
123 [SDNPHasChain, SDNPMayStore,
124 SDNPMayLoad, SDNPMemOperand]>;
125 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
126 [SDNPHasChain, SDNPMayStore,
127 SDNPMayLoad, SDNPMemOperand]>;
128 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
129 [SDNPHasChain, SDNPMayStore,
130 SDNPMayLoad, SDNPMemOperand]>;
131 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
132 [SDNPHasChain, SDNPMayStore,
133 SDNPMayLoad, SDNPMemOperand]>;
134 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
135 [SDNPHasChain, SDNPMayStore,
136 SDNPMayLoad, SDNPMemOperand]>;
137 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
138 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
140 def X86vastart_save_xmm_regs :
141 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
142 SDT_X86VASTART_SAVE_XMM_REGS,
143 [SDNPHasChain, SDNPVariadic]>;
145 def X86callseq_start :
146 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
147 [SDNPHasChain, SDNPOutFlag]>;
149 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
150 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
152 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
153 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
156 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
157 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
158 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
159 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
162 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
163 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
165 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
166 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
168 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
169 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
171 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
174 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
175 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
177 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
179 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
180 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
182 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
185 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
186 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
187 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
189 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
191 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
194 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
196 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
197 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
199 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
202 //===----------------------------------------------------------------------===//
203 // X86 Operand Definitions.
206 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
207 // the index operand of an address, to conform to x86 encoding restrictions.
208 def ptr_rc_nosp : PointerLikeRegClass<1>;
210 // *mem - Operand definitions for the funky X86 addressing mode operands.
212 def X86MemAsmOperand : AsmOperandClass {
214 let SuperClasses = [];
216 def X86AbsMemAsmOperand : AsmOperandClass {
218 let SuperClasses = [X86MemAsmOperand];
220 class X86MemOperand<string printMethod> : Operand<iPTR> {
221 let PrintMethod = printMethod;
222 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
223 let ParserMatchClass = X86MemAsmOperand;
226 def opaque32mem : X86MemOperand<"printopaquemem">;
227 def opaque48mem : X86MemOperand<"printopaquemem">;
228 def opaque80mem : X86MemOperand<"printopaquemem">;
229 def opaque512mem : X86MemOperand<"printopaquemem">;
231 def i8mem : X86MemOperand<"printi8mem">;
232 def i16mem : X86MemOperand<"printi16mem">;
233 def i32mem : X86MemOperand<"printi32mem">;
234 def i64mem : X86MemOperand<"printi64mem">;
235 def i128mem : X86MemOperand<"printi128mem">;
236 def i256mem : X86MemOperand<"printi256mem">;
237 def f32mem : X86MemOperand<"printf32mem">;
238 def f64mem : X86MemOperand<"printf64mem">;
239 def f80mem : X86MemOperand<"printf80mem">;
240 def f128mem : X86MemOperand<"printf128mem">;
241 def f256mem : X86MemOperand<"printf256mem">;
243 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
244 // plain GR64, so that it doesn't potentially require a REX prefix.
245 def i8mem_NOREX : Operand<i64> {
246 let PrintMethod = "printi8mem";
247 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
248 let ParserMatchClass = X86MemAsmOperand;
251 // Special i32mem for addresses of load folding tail calls. These are not
252 // allowed to use callee-saved registers since they must be scheduled
253 // after callee-saved register are popped.
254 def i32mem_TC : Operand<i32> {
255 let PrintMethod = "printi32mem";
256 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
257 let ParserMatchClass = X86MemAsmOperand;
261 let ParserMatchClass = X86AbsMemAsmOperand,
262 PrintMethod = "print_pcrel_imm" in {
263 def i32imm_pcrel : Operand<i32>;
264 def i16imm_pcrel : Operand<i16>;
266 def offset8 : Operand<i64>;
267 def offset16 : Operand<i64>;
268 def offset32 : Operand<i64>;
269 def offset64 : Operand<i64>;
271 // Branch targets have OtherVT type and print as pc-relative values.
272 def brtarget : Operand<OtherVT>;
273 def brtarget8 : Operand<OtherVT>;
277 def SSECC : Operand<i8> {
278 let PrintMethod = "printSSECC";
281 class ImmSExtAsmOperandClass : AsmOperandClass {
282 let SuperClasses = [ImmAsmOperand];
283 let RenderMethod = "addImmOperands";
286 // Sign-extended immediate classes. We don't need to define the full lattice
287 // here because there is no instruction with an ambiguity between ImmSExti64i32
290 // The strange ranges come from the fact that the assembler always works with
291 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
292 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
295 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
296 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
297 let Name = "ImmSExti64i32";
300 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
301 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
302 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
303 let Name = "ImmSExti16i8";
304 let SuperClasses = [ImmSExti64i32AsmOperand];
307 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
308 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
309 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
310 let Name = "ImmSExti32i8";
314 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
315 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
316 let Name = "ImmSExti64i8";
317 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
318 ImmSExti64i32AsmOperand];
321 // A couple of more descriptive operand definitions.
322 // 16-bits but only 8 bits are significant.
323 def i16i8imm : Operand<i16> {
324 let ParserMatchClass = ImmSExti16i8AsmOperand;
326 // 32-bits but only 8 bits are significant.
327 def i32i8imm : Operand<i32> {
328 let ParserMatchClass = ImmSExti32i8AsmOperand;
331 //===----------------------------------------------------------------------===//
332 // X86 Complex Pattern Definitions.
335 // Define X86 specific addressing mode.
336 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
337 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
338 [add, sub, mul, X86mul_imm, shl, or, frameindex],
340 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
341 [tglobaltlsaddr], []>;
343 //===----------------------------------------------------------------------===//
344 // X86 Instruction Predicate Definitions.
345 def HasCMov : Predicate<"Subtarget->hasCMov()">;
346 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
348 // FIXME: temporary hack to let codegen assert or generate poor code in case
349 // no AVX version of the desired intructions is present, this is better for
350 // incremental dev (without fallbacks it's easier to spot what's missing)
351 def HasMMX : Predicate<"Subtarget->hasMMX() && !Subtarget->hasAVX()">;
352 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
353 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
354 def HasSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
355 def HasSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
356 def HasSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
357 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
358 def HasSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
359 def HasSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
360 def HasSSE4A : Predicate<"Subtarget->hasSSE4A() && !Subtarget->hasAVX()">;
362 def HasAVX : Predicate<"Subtarget->hasAVX()">;
363 def HasCLMUL : Predicate<"Subtarget->hasCLMUL()">;
364 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
365 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
366 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
367 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
368 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
369 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
370 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
371 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
372 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
373 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
374 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
375 "TM.getCodeModel() != CodeModel::Kernel">;
376 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
377 "TM.getCodeModel() == CodeModel::Kernel">;
378 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
379 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
380 def OptForSize : Predicate<"OptForSize">;
381 def OptForSpeed : Predicate<"!OptForSize">;
382 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
383 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
384 def HasAES : Predicate<"Subtarget->hasAES()">;
386 //===----------------------------------------------------------------------===//
387 // X86 Instruction Format Definitions.
390 include "X86InstrFormats.td"
392 //===----------------------------------------------------------------------===//
393 // Pattern fragments...
396 // X86 specific condition code. These correspond to CondCode in
397 // X86InstrInfo.h. They must be kept in synch.
398 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
399 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
400 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
401 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
402 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
403 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
404 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
405 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
406 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
407 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
408 def X86_COND_NO : PatLeaf<(i8 10)>;
409 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
410 def X86_COND_NS : PatLeaf<(i8 12)>;
411 def X86_COND_O : PatLeaf<(i8 13)>;
412 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
413 def X86_COND_S : PatLeaf<(i8 15)>;
415 def immSext8 : PatLeaf<(imm), [{ return immSext8(N); }]>;
417 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
418 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
420 // Helper fragments for loads.
421 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
422 // known to be 32-bit aligned or better. Ditto for i8 to i16.
423 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
424 LoadSDNode *LD = cast<LoadSDNode>(N);
425 ISD::LoadExtType ExtType = LD->getExtensionType();
426 if (ExtType == ISD::NON_EXTLOAD)
428 if (ExtType == ISD::EXTLOAD)
429 return LD->getAlignment() >= 2 && !LD->isVolatile();
433 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
434 LoadSDNode *LD = cast<LoadSDNode>(N);
435 ISD::LoadExtType ExtType = LD->getExtensionType();
436 if (ExtType == ISD::EXTLOAD)
437 return LD->getAlignment() >= 2 && !LD->isVolatile();
441 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
442 LoadSDNode *LD = cast<LoadSDNode>(N);
443 ISD::LoadExtType ExtType = LD->getExtensionType();
444 if (ExtType == ISD::NON_EXTLOAD)
446 if (ExtType == ISD::EXTLOAD)
447 return LD->getAlignment() >= 4 && !LD->isVolatile();
451 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
452 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
453 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
454 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
455 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
457 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
458 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
459 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
461 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
462 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
463 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
464 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
465 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
466 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
468 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
469 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
470 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
471 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
472 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
473 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
476 // An 'and' node with a single use.
477 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
478 return N->hasOneUse();
480 // An 'srl' node with a single use.
481 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
482 return N->hasOneUse();
484 // An 'trunc' node with a single use.
485 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
486 return N->hasOneUse();
489 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
490 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
491 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
492 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
494 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
495 APInt Mask = APInt::getAllOnesValue(BitWidth);
496 APInt KnownZero0, KnownOne0;
497 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
498 APInt KnownZero1, KnownOne1;
499 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
500 return (~KnownZero0 & ~KnownZero1) == 0;
503 //===----------------------------------------------------------------------===//
508 let neverHasSideEffects = 1 in {
509 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
510 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
511 "nop{w}\t$zero", []>, TB, OpSize;
512 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
513 "nop{l}\t$zero", []>, TB;
517 // Constructing a stack frame.
518 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
519 "enter\t$len, $lvl", []>;
521 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
522 def LEAVE : I<0xC9, RawFrm,
523 (outs), (ins), "leave", []>, Requires<[In32BitMode]>;
525 //===----------------------------------------------------------------------===//
526 // Miscellaneous Instructions...
528 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
529 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
531 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
532 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
533 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
534 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
536 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
537 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
539 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
541 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
543 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
544 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
546 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
548 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
549 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
552 let mayStore = 1 in {
553 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
555 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
556 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
558 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
560 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
561 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
565 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
566 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
567 "push{l}\t$imm", []>;
568 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
569 "push{w}\t$imm", []>, OpSize;
570 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
571 "push{l}\t$imm", []>;
574 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
575 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
576 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
577 Requires<[In32BitMode]>;
579 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
580 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
581 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
582 Requires<[In32BitMode]>;
585 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
586 mayLoad=1, neverHasSideEffects=1 in {
587 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
588 Requires<[In32BitMode]>;
590 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
591 mayStore=1, neverHasSideEffects=1 in {
592 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
593 Requires<[In32BitMode]>;
596 let Uses = [EFLAGS], Constraints = "$src = $dst" in // GR32 = bswap GR32
597 def BSWAP32r : I<0xC8, AddRegFrm,
598 (outs GR32:$dst), (ins GR32:$src),
600 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
603 // Bit scan instructions.
604 let Defs = [EFLAGS] in {
605 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
606 "bsf{w}\t{$src, $dst|$dst, $src}",
607 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
608 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
609 "bsf{w}\t{$src, $dst|$dst, $src}",
610 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
612 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
613 "bsf{l}\t{$src, $dst|$dst, $src}",
614 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
615 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
616 "bsf{l}\t{$src, $dst|$dst, $src}",
617 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
619 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
620 "bsr{w}\t{$src, $dst|$dst, $src}",
621 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
622 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
623 "bsr{w}\t{$src, $dst|$dst, $src}",
624 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
626 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
627 "bsr{l}\t{$src, $dst|$dst, $src}",
628 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
629 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
630 "bsr{l}\t{$src, $dst|$dst, $src}",
631 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
634 let neverHasSideEffects = 1 in
635 def LEA16r : I<0x8D, MRMSrcMem,
636 (outs GR16:$dst), (ins i32mem:$src),
637 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
638 let isReMaterializable = 1 in
639 def LEA32r : I<0x8D, MRMSrcMem,
640 (outs GR32:$dst), (ins i32mem:$src),
641 "lea{l}\t{$src|$dst}, {$dst|$src}",
642 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
644 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
645 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
646 [(X86rep_movs i8)]>, REP;
647 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
648 [(X86rep_movs i16)]>, REP, OpSize;
649 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
650 [(X86rep_movs i32)]>, REP;
653 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
654 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
655 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
656 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
657 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
660 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
661 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
662 [(X86rep_stos i8)]>, REP;
663 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
664 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
665 [(X86rep_stos i16)]>, REP, OpSize;
666 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
667 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
668 [(X86rep_stos i32)]>, REP;
670 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
671 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
672 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
673 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
674 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
675 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
676 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
678 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
679 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
680 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
682 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
683 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
684 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
687 //===----------------------------------------------------------------------===//
688 // Move Instructions.
690 let neverHasSideEffects = 1 in {
691 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
692 "mov{b}\t{$src, $dst|$dst, $src}", []>;
693 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
694 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
695 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
696 "mov{l}\t{$src, $dst|$dst, $src}", []>;
698 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
699 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
700 "mov{b}\t{$src, $dst|$dst, $src}",
701 [(set GR8:$dst, imm:$src)]>;
702 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
703 "mov{w}\t{$src, $dst|$dst, $src}",
704 [(set GR16:$dst, imm:$src)]>, OpSize;
705 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
706 "mov{l}\t{$src, $dst|$dst, $src}",
707 [(set GR32:$dst, imm:$src)]>;
710 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
711 "mov{b}\t{$src, $dst|$dst, $src}",
712 [(store (i8 imm:$src), addr:$dst)]>;
713 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
714 "mov{w}\t{$src, $dst|$dst, $src}",
715 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
716 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
717 "mov{l}\t{$src, $dst|$dst, $src}",
718 [(store (i32 imm:$src), addr:$dst)]>;
720 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
721 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
722 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
723 "mov{b}\t{$src, %al|%al, $src}", []>,
724 Requires<[In32BitMode]>;
725 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
726 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
727 Requires<[In32BitMode]>;
728 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
729 "mov{l}\t{$src, %eax|%eax, $src}", []>,
730 Requires<[In32BitMode]>;
731 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
732 "mov{b}\t{%al, $dst|$dst, %al}", []>,
733 Requires<[In32BitMode]>;
734 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
735 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
736 Requires<[In32BitMode]>;
737 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
738 "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
739 Requires<[In32BitMode]>;
742 let isCodeGenOnly = 1 in {
743 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
744 "mov{b}\t{$src, $dst|$dst, $src}", []>;
745 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
746 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
747 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
748 "mov{l}\t{$src, $dst|$dst, $src}", []>;
751 let canFoldAsLoad = 1, isReMaterializable = 1 in {
752 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
753 "mov{b}\t{$src, $dst|$dst, $src}",
754 [(set GR8:$dst, (loadi8 addr:$src))]>;
755 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
756 "mov{w}\t{$src, $dst|$dst, $src}",
757 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
758 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
759 "mov{l}\t{$src, $dst|$dst, $src}",
760 [(set GR32:$dst, (loadi32 addr:$src))]>;
763 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
764 "mov{b}\t{$src, $dst|$dst, $src}",
765 [(store GR8:$src, addr:$dst)]>;
766 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
767 "mov{w}\t{$src, $dst|$dst, $src}",
768 [(store GR16:$src, addr:$dst)]>, OpSize;
769 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
770 "mov{l}\t{$src, $dst|$dst, $src}",
771 [(store GR32:$src, addr:$dst)]>;
773 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
774 let isCodeGenOnly = 1 in {
775 let neverHasSideEffects = 1 in
776 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
777 "mov{l}\t{$src, $dst|$dst, $src}", []>;
780 canFoldAsLoad = 1, isReMaterializable = 1 in
781 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
782 "mov{l}\t{$src, $dst|$dst, $src}",
786 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
787 "mov{l}\t{$src, $dst|$dst, $src}",
791 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
792 // that they can be used for copying and storing h registers, which can't be
793 // encoded when a REX prefix is present.
794 let isCodeGenOnly = 1 in {
795 let neverHasSideEffects = 1 in
796 def MOV8rr_NOREX : I<0x88, MRMDestReg,
797 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
798 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
800 def MOV8mr_NOREX : I<0x88, MRMDestMem,
801 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
802 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
804 canFoldAsLoad = 1, isReMaterializable = 1 in
805 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
806 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
807 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
810 //===----------------------------------------------------------------------===//
811 // Fixed-Register Multiplication and Division Instructions...
814 // Extra precision multiplication
816 // AL is really implied by AX, but the registers in Defs must match the
817 // SDNode results (i8, i32).
818 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
819 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
820 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
821 // This probably ought to be moved to a def : Pat<> if the
822 // syntax can be accepted.
823 [(set AL, (mul AL, GR8:$src)),
824 (implicit EFLAGS)]>; // AL,AH = AL*GR8
826 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
827 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
829 []>, OpSize; // AX,DX = AX*GR16
831 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
832 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
834 []>; // EAX,EDX = EAX*GR32
836 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
837 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
839 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
840 // This probably ought to be moved to a def : Pat<> if the
841 // syntax can be accepted.
842 [(set AL, (mul AL, (loadi8 addr:$src))),
843 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
845 let mayLoad = 1, neverHasSideEffects = 1 in {
846 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
847 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
849 []>, OpSize; // AX,DX = AX*[mem16]
851 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
852 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
854 []>; // EAX,EDX = EAX*[mem32]
857 let neverHasSideEffects = 1 in {
858 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
859 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
861 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
862 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
863 OpSize; // AX,DX = AX*GR16
864 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
865 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
866 // EAX,EDX = EAX*GR32
868 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
869 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
870 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
871 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
872 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
873 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
874 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
875 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
876 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
878 } // neverHasSideEffects
880 // unsigned division/remainder
881 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
882 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
884 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
885 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
886 "div{w}\t$src", []>, OpSize;
887 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
888 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
891 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
892 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
894 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
895 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
896 "div{w}\t$src", []>, OpSize;
897 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
898 // EDX:EAX/[mem32] = EAX,EDX
899 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
903 // Signed division/remainder.
904 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
905 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
906 "idiv{b}\t$src", []>;
907 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
908 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
909 "idiv{w}\t$src", []>, OpSize;
910 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
911 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
912 "idiv{l}\t$src", []>;
913 let mayLoad = 1, mayLoad = 1 in {
914 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
915 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
916 "idiv{b}\t$src", []>;
917 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
918 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
919 "idiv{w}\t$src", []>, OpSize;
920 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
921 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
922 // EDX:EAX/[mem32] = EAX,EDX
923 "idiv{l}\t$src", []>;
926 //===----------------------------------------------------------------------===//
927 // Two address Instructions.
929 let Constraints = "$src1 = $dst" in {
932 let Uses = [EFLAGS] in {
934 let Predicates = [HasCMov] in {
935 let isCommutable = 1 in {
936 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
937 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
938 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
939 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
940 X86_COND_B, EFLAGS))]>,
942 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
943 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
944 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
945 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
946 X86_COND_B, EFLAGS))]>,
948 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
949 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
950 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
951 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
952 X86_COND_AE, EFLAGS))]>,
954 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
955 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
956 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
957 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
958 X86_COND_AE, EFLAGS))]>,
960 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
961 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
962 "cmove{w}\t{$src2, $dst|$dst, $src2}",
963 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
964 X86_COND_E, EFLAGS))]>,
966 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
967 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
968 "cmove{l}\t{$src2, $dst|$dst, $src2}",
969 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
970 X86_COND_E, EFLAGS))]>,
972 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
973 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
974 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
975 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
976 X86_COND_NE, EFLAGS))]>,
978 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
979 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
980 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
981 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
982 X86_COND_NE, EFLAGS))]>,
984 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
985 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
986 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
987 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
988 X86_COND_BE, EFLAGS))]>,
990 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
991 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
992 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
993 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
994 X86_COND_BE, EFLAGS))]>,
996 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
997 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
998 "cmova{w}\t{$src2, $dst|$dst, $src2}",
999 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1000 X86_COND_A, EFLAGS))]>,
1002 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1003 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1004 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1005 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1006 X86_COND_A, EFLAGS))]>,
1008 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1009 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1010 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1011 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1012 X86_COND_L, EFLAGS))]>,
1014 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1015 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1016 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1017 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1018 X86_COND_L, EFLAGS))]>,
1020 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1021 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1022 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1023 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1024 X86_COND_GE, EFLAGS))]>,
1026 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1027 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1028 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1029 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1030 X86_COND_GE, EFLAGS))]>,
1032 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1033 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1034 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1035 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1036 X86_COND_LE, EFLAGS))]>,
1038 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1039 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1040 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1041 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1042 X86_COND_LE, EFLAGS))]>,
1044 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1045 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1046 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1047 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1048 X86_COND_G, EFLAGS))]>,
1050 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1051 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1052 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1053 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1054 X86_COND_G, EFLAGS))]>,
1056 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1057 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1058 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1059 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1060 X86_COND_S, EFLAGS))]>,
1062 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1063 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1064 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1065 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1066 X86_COND_S, EFLAGS))]>,
1068 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1069 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1070 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1071 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1072 X86_COND_NS, EFLAGS))]>,
1074 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1075 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1076 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1077 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1078 X86_COND_NS, EFLAGS))]>,
1080 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1081 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1082 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1083 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1084 X86_COND_P, EFLAGS))]>,
1086 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1087 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1088 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1089 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1090 X86_COND_P, EFLAGS))]>,
1092 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1093 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1094 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1095 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1096 X86_COND_NP, EFLAGS))]>,
1098 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1099 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1100 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1101 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1102 X86_COND_NP, EFLAGS))]>,
1104 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1105 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1106 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1107 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1108 X86_COND_O, EFLAGS))]>,
1110 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1111 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1112 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1113 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1114 X86_COND_O, EFLAGS))]>,
1116 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1117 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1118 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1119 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1120 X86_COND_NO, EFLAGS))]>,
1122 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1123 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1124 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1125 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1126 X86_COND_NO, EFLAGS))]>,
1128 } // isCommutable = 1
1130 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1131 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1132 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1133 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1134 X86_COND_B, EFLAGS))]>,
1136 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1137 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1138 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1139 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1140 X86_COND_B, EFLAGS))]>,
1142 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1143 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1144 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1145 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1146 X86_COND_AE, EFLAGS))]>,
1148 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1149 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1150 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1151 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1152 X86_COND_AE, EFLAGS))]>,
1154 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1155 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1156 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1157 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1158 X86_COND_E, EFLAGS))]>,
1160 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1161 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1162 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1163 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1164 X86_COND_E, EFLAGS))]>,
1166 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1167 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1168 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1169 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1170 X86_COND_NE, EFLAGS))]>,
1172 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1173 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1174 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1175 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1176 X86_COND_NE, EFLAGS))]>,
1178 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1179 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1180 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1181 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1182 X86_COND_BE, EFLAGS))]>,
1184 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1185 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1186 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1187 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1188 X86_COND_BE, EFLAGS))]>,
1190 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1191 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1192 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1193 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1194 X86_COND_A, EFLAGS))]>,
1196 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1197 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1198 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1199 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1200 X86_COND_A, EFLAGS))]>,
1202 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1203 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1204 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1205 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1206 X86_COND_L, EFLAGS))]>,
1208 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1209 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1210 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1211 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1212 X86_COND_L, EFLAGS))]>,
1214 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1215 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1216 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1217 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1218 X86_COND_GE, EFLAGS))]>,
1220 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1221 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1222 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1223 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1224 X86_COND_GE, EFLAGS))]>,
1226 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1227 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1228 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1229 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1230 X86_COND_LE, EFLAGS))]>,
1232 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1233 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1234 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1235 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1236 X86_COND_LE, EFLAGS))]>,
1238 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1239 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1240 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1241 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1242 X86_COND_G, EFLAGS))]>,
1244 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1245 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1246 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1247 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1248 X86_COND_G, EFLAGS))]>,
1250 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1251 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1252 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1253 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1254 X86_COND_S, EFLAGS))]>,
1256 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1257 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1258 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1259 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1260 X86_COND_S, EFLAGS))]>,
1262 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1263 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1264 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1265 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1266 X86_COND_NS, EFLAGS))]>,
1268 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1269 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1270 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1271 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1272 X86_COND_NS, EFLAGS))]>,
1274 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1275 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1276 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1277 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1278 X86_COND_P, EFLAGS))]>,
1280 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1281 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1282 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1283 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1284 X86_COND_P, EFLAGS))]>,
1286 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1287 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1288 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1289 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1290 X86_COND_NP, EFLAGS))]>,
1292 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1293 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1294 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1295 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1296 X86_COND_NP, EFLAGS))]>,
1298 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1299 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1300 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1301 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1302 X86_COND_O, EFLAGS))]>,
1304 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1305 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1306 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1307 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1308 X86_COND_O, EFLAGS))]>,
1310 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1311 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1312 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1314 X86_COND_NO, EFLAGS))]>,
1316 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1317 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1318 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1319 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1320 X86_COND_NO, EFLAGS))]>,
1322 } // Predicates = [HasCMov]
1324 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1325 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1326 // however that requires promoting the operands, and can induce additional
1327 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1328 // clobber EFLAGS, because if one of the operands is zero, the expansion
1329 // could involve an xor.
1330 let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
1331 def CMOV_GR8 : I<0, Pseudo,
1332 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1333 "#CMOV_GR8 PSEUDO!",
1334 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1335 imm:$cond, EFLAGS))]>;
1337 let Predicates = [NoCMov] in {
1338 def CMOV_GR32 : I<0, Pseudo,
1339 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1340 "#CMOV_GR32* PSEUDO!",
1342 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1343 def CMOV_GR16 : I<0, Pseudo,
1344 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1345 "#CMOV_GR16* PSEUDO!",
1347 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1348 def CMOV_RFP32 : I<0, Pseudo,
1350 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1351 "#CMOV_RFP32 PSEUDO!",
1353 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1355 def CMOV_RFP64 : I<0, Pseudo,
1357 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1358 "#CMOV_RFP64 PSEUDO!",
1360 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1362 def CMOV_RFP80 : I<0, Pseudo,
1364 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1365 "#CMOV_RFP80 PSEUDO!",
1367 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1369 } // Predicates = [NoCMov]
1370 } // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
1371 } // Uses = [EFLAGS]
1374 // unary instructions
1375 let CodeSize = 2 in {
1376 let Defs = [EFLAGS] in {
1377 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
1379 [(set GR8:$dst, (ineg GR8:$src1)),
1380 (implicit EFLAGS)]>;
1381 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
1383 [(set GR16:$dst, (ineg GR16:$src1)),
1384 (implicit EFLAGS)]>, OpSize;
1385 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
1387 [(set GR32:$dst, (ineg GR32:$src1)),
1388 (implicit EFLAGS)]>;
1390 let Constraints = "" in {
1391 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
1393 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1394 (implicit EFLAGS)]>;
1395 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
1397 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1398 (implicit EFLAGS)]>, OpSize;
1399 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
1401 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1402 (implicit EFLAGS)]>;
1403 } // Constraints = ""
1404 } // Defs = [EFLAGS]
1406 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1407 let AddedComplexity = 15 in {
1408 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
1410 [(set GR8:$dst, (not GR8:$src1))]>;
1411 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
1413 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
1414 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
1416 [(set GR32:$dst, (not GR32:$src1))]>;
1418 let Constraints = "" in {
1419 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
1421 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1422 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
1424 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1425 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
1427 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1428 } // Constraints = ""
1431 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1432 let Defs = [EFLAGS] in {
1434 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1436 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
1438 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1439 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1441 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
1442 OpSize, Requires<[In32BitMode]>;
1443 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1445 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
1446 Requires<[In32BitMode]>;
1448 let Constraints = "", CodeSize = 2 in {
1449 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1450 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1451 (implicit EFLAGS)]>;
1452 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1453 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1454 (implicit EFLAGS)]>,
1455 OpSize, Requires<[In32BitMode]>;
1456 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1457 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1458 (implicit EFLAGS)]>,
1459 Requires<[In32BitMode]>;
1460 } // Constraints = "", CodeSize = 2
1463 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1465 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
1466 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1467 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1469 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
1470 OpSize, Requires<[In32BitMode]>;
1471 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1473 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
1474 Requires<[In32BitMode]>;
1477 let Constraints = "", CodeSize = 2 in {
1478 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1479 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1480 (implicit EFLAGS)]>;
1481 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1482 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1483 (implicit EFLAGS)]>,
1484 OpSize, Requires<[In32BitMode]>;
1485 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1486 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1487 (implicit EFLAGS)]>,
1488 Requires<[In32BitMode]>;
1489 } // Constraints = "", CodeSize = 2
1490 } // Defs = [EFLAGS]
1492 // Logical operators...
1493 let Defs = [EFLAGS] in {
1494 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1495 def AND8rr : I<0x20, MRMDestReg,
1496 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1497 "and{b}\t{$src2, $dst|$dst, $src2}",
1498 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1499 def AND16rr : I<0x21, MRMDestReg,
1500 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1501 "and{w}\t{$src2, $dst|$dst, $src2}",
1502 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1503 GR16:$src2))]>, OpSize;
1504 def AND32rr : I<0x21, MRMDestReg,
1505 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1506 "and{l}\t{$src2, $dst|$dst, $src2}",
1507 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1511 // AND instructions with the destination register in REG and the source register
1512 // in R/M. Included for the disassembler.
1513 let isCodeGenOnly = 1 in {
1514 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1515 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1516 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1517 (ins GR16:$src1, GR16:$src2),
1518 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1519 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1520 (ins GR32:$src1, GR32:$src2),
1521 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1524 def AND8rm : I<0x22, MRMSrcMem,
1525 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1526 "and{b}\t{$src2, $dst|$dst, $src2}",
1527 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1528 (loadi8 addr:$src2)))]>;
1529 def AND16rm : I<0x23, MRMSrcMem,
1530 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1531 "and{w}\t{$src2, $dst|$dst, $src2}",
1532 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1533 (loadi16 addr:$src2)))]>,
1535 def AND32rm : I<0x23, MRMSrcMem,
1536 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1537 "and{l}\t{$src2, $dst|$dst, $src2}",
1538 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1539 (loadi32 addr:$src2)))]>;
1541 def AND8ri : Ii8<0x80, MRM4r,
1542 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1543 "and{b}\t{$src2, $dst|$dst, $src2}",
1544 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1546 def AND16ri : Ii16<0x81, MRM4r,
1547 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1548 "and{w}\t{$src2, $dst|$dst, $src2}",
1549 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1550 imm:$src2))]>, OpSize;
1551 def AND32ri : Ii32<0x81, MRM4r,
1552 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1553 "and{l}\t{$src2, $dst|$dst, $src2}",
1554 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1556 def AND16ri8 : Ii8<0x83, MRM4r,
1557 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1558 "and{w}\t{$src2, $dst|$dst, $src2}",
1559 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1560 i16immSExt8:$src2))]>,
1562 def AND32ri8 : Ii8<0x83, MRM4r,
1563 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1564 "and{l}\t{$src2, $dst|$dst, $src2}",
1565 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1566 i32immSExt8:$src2))]>;
1568 let Constraints = "" in {
1569 def AND8mr : I<0x20, MRMDestMem,
1570 (outs), (ins i8mem :$dst, GR8 :$src),
1571 "and{b}\t{$src, $dst|$dst, $src}",
1572 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1573 (implicit EFLAGS)]>;
1574 def AND16mr : I<0x21, MRMDestMem,
1575 (outs), (ins i16mem:$dst, GR16:$src),
1576 "and{w}\t{$src, $dst|$dst, $src}",
1577 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1578 (implicit EFLAGS)]>,
1580 def AND32mr : I<0x21, MRMDestMem,
1581 (outs), (ins i32mem:$dst, GR32:$src),
1582 "and{l}\t{$src, $dst|$dst, $src}",
1583 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1584 (implicit EFLAGS)]>;
1585 def AND8mi : Ii8<0x80, MRM4m,
1586 (outs), (ins i8mem :$dst, i8imm :$src),
1587 "and{b}\t{$src, $dst|$dst, $src}",
1588 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1589 (implicit EFLAGS)]>;
1590 def AND16mi : Ii16<0x81, MRM4m,
1591 (outs), (ins i16mem:$dst, i16imm:$src),
1592 "and{w}\t{$src, $dst|$dst, $src}",
1593 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1594 (implicit EFLAGS)]>,
1596 def AND32mi : Ii32<0x81, MRM4m,
1597 (outs), (ins i32mem:$dst, i32imm:$src),
1598 "and{l}\t{$src, $dst|$dst, $src}",
1599 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1600 (implicit EFLAGS)]>;
1601 def AND16mi8 : Ii8<0x83, MRM4m,
1602 (outs), (ins i16mem:$dst, i16i8imm :$src),
1603 "and{w}\t{$src, $dst|$dst, $src}",
1604 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1605 (implicit EFLAGS)]>,
1607 def AND32mi8 : Ii8<0x83, MRM4m,
1608 (outs), (ins i32mem:$dst, i32i8imm :$src),
1609 "and{l}\t{$src, $dst|$dst, $src}",
1610 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1611 (implicit EFLAGS)]>;
1613 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1614 "and{b}\t{$src, %al|%al, $src}", []>;
1615 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1616 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1617 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1618 "and{l}\t{$src, %eax|%eax, $src}", []>;
1620 } // Constraints = ""
1623 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1624 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1625 (ins GR8 :$src1, GR8 :$src2),
1626 "or{b}\t{$src2, $dst|$dst, $src2}",
1627 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1628 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1629 (ins GR16:$src1, GR16:$src2),
1630 "or{w}\t{$src2, $dst|$dst, $src2}",
1631 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1633 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1634 (ins GR32:$src1, GR32:$src2),
1635 "or{l}\t{$src2, $dst|$dst, $src2}",
1636 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1639 // OR instructions with the destination register in REG and the source register
1640 // in R/M. Included for the disassembler.
1641 let isCodeGenOnly = 1 in {
1642 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1643 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1644 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1645 (ins GR16:$src1, GR16:$src2),
1646 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1647 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1648 (ins GR32:$src1, GR32:$src2),
1649 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1652 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
1653 (ins GR8 :$src1, i8mem :$src2),
1654 "or{b}\t{$src2, $dst|$dst, $src2}",
1655 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
1656 (load addr:$src2)))]>;
1657 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
1658 (ins GR16:$src1, i16mem:$src2),
1659 "or{w}\t{$src2, $dst|$dst, $src2}",
1660 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1661 (load addr:$src2)))]>,
1663 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
1664 (ins GR32:$src1, i32mem:$src2),
1665 "or{l}\t{$src2, $dst|$dst, $src2}",
1666 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1667 (load addr:$src2)))]>;
1669 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1670 (ins GR8 :$src1, i8imm:$src2),
1671 "or{b}\t{$src2, $dst|$dst, $src2}",
1672 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
1673 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1674 (ins GR16:$src1, i16imm:$src2),
1675 "or{w}\t{$src2, $dst|$dst, $src2}",
1676 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1677 imm:$src2))]>, OpSize;
1678 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1679 (ins GR32:$src1, i32imm:$src2),
1680 "or{l}\t{$src2, $dst|$dst, $src2}",
1681 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1684 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1685 (ins GR16:$src1, i16i8imm:$src2),
1686 "or{w}\t{$src2, $dst|$dst, $src2}",
1687 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1688 i16immSExt8:$src2))]>, OpSize;
1689 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1690 (ins GR32:$src1, i32i8imm:$src2),
1691 "or{l}\t{$src2, $dst|$dst, $src2}",
1692 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1693 i32immSExt8:$src2))]>;
1694 let Constraints = "" in {
1695 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1696 "or{b}\t{$src, $dst|$dst, $src}",
1697 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1698 (implicit EFLAGS)]>;
1699 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1700 "or{w}\t{$src, $dst|$dst, $src}",
1701 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1702 (implicit EFLAGS)]>, OpSize;
1703 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1704 "or{l}\t{$src, $dst|$dst, $src}",
1705 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1706 (implicit EFLAGS)]>;
1707 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1708 "or{b}\t{$src, $dst|$dst, $src}",
1709 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1710 (implicit EFLAGS)]>;
1711 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1712 "or{w}\t{$src, $dst|$dst, $src}",
1713 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1714 (implicit EFLAGS)]>,
1716 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1717 "or{l}\t{$src, $dst|$dst, $src}",
1718 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1719 (implicit EFLAGS)]>;
1720 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1721 "or{w}\t{$src, $dst|$dst, $src}",
1722 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1723 (implicit EFLAGS)]>,
1725 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1726 "or{l}\t{$src, $dst|$dst, $src}",
1727 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1728 (implicit EFLAGS)]>;
1730 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1731 "or{b}\t{$src, %al|%al, $src}", []>;
1732 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1733 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1734 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1735 "or{l}\t{$src, %eax|%eax, $src}", []>;
1736 } // Constraints = ""
1739 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1740 def XOR8rr : I<0x30, MRMDestReg,
1741 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1742 "xor{b}\t{$src2, $dst|$dst, $src2}",
1743 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
1745 def XOR16rr : I<0x31, MRMDestReg,
1746 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1747 "xor{w}\t{$src2, $dst|$dst, $src2}",
1748 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
1749 GR16:$src2))]>, OpSize;
1750 def XOR32rr : I<0x31, MRMDestReg,
1751 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1752 "xor{l}\t{$src2, $dst|$dst, $src2}",
1753 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
1755 } // isCommutable = 1
1757 // XOR instructions with the destination register in REG and the source register
1758 // in R/M. Included for the disassembler.
1759 let isCodeGenOnly = 1 in {
1760 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1761 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
1762 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
1763 (ins GR16:$src1, GR16:$src2),
1764 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1765 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
1766 (ins GR32:$src1, GR32:$src2),
1767 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
1770 def XOR8rm : I<0x32, MRMSrcMem,
1771 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1772 "xor{b}\t{$src2, $dst|$dst, $src2}",
1773 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
1774 (load addr:$src2)))]>;
1775 def XOR16rm : I<0x33, MRMSrcMem,
1776 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1777 "xor{w}\t{$src2, $dst|$dst, $src2}",
1778 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
1779 (load addr:$src2)))]>,
1781 def XOR32rm : I<0x33, MRMSrcMem,
1782 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1783 "xor{l}\t{$src2, $dst|$dst, $src2}",
1784 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
1785 (load addr:$src2)))]>;
1787 def XOR8ri : Ii8<0x80, MRM6r,
1788 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1789 "xor{b}\t{$src2, $dst|$dst, $src2}",
1790 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
1791 def XOR16ri : Ii16<0x81, MRM6r,
1792 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1793 "xor{w}\t{$src2, $dst|$dst, $src2}",
1794 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
1795 imm:$src2))]>, OpSize;
1796 def XOR32ri : Ii32<0x81, MRM6r,
1797 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1798 "xor{l}\t{$src2, $dst|$dst, $src2}",
1799 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
1801 def XOR16ri8 : Ii8<0x83, MRM6r,
1802 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1803 "xor{w}\t{$src2, $dst|$dst, $src2}",
1804 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
1805 i16immSExt8:$src2))]>,
1807 def XOR32ri8 : Ii8<0x83, MRM6r,
1808 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1809 "xor{l}\t{$src2, $dst|$dst, $src2}",
1810 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
1811 i32immSExt8:$src2))]>;
1813 let Constraints = "" in {
1814 def XOR8mr : I<0x30, MRMDestMem,
1815 (outs), (ins i8mem :$dst, GR8 :$src),
1816 "xor{b}\t{$src, $dst|$dst, $src}",
1817 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1818 (implicit EFLAGS)]>;
1819 def XOR16mr : I<0x31, MRMDestMem,
1820 (outs), (ins i16mem:$dst, GR16:$src),
1821 "xor{w}\t{$src, $dst|$dst, $src}",
1822 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1823 (implicit EFLAGS)]>,
1825 def XOR32mr : I<0x31, MRMDestMem,
1826 (outs), (ins i32mem:$dst, GR32:$src),
1827 "xor{l}\t{$src, $dst|$dst, $src}",
1828 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1829 (implicit EFLAGS)]>;
1830 def XOR8mi : Ii8<0x80, MRM6m,
1831 (outs), (ins i8mem :$dst, i8imm :$src),
1832 "xor{b}\t{$src, $dst|$dst, $src}",
1833 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1834 (implicit EFLAGS)]>;
1835 def XOR16mi : Ii16<0x81, MRM6m,
1836 (outs), (ins i16mem:$dst, i16imm:$src),
1837 "xor{w}\t{$src, $dst|$dst, $src}",
1838 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1839 (implicit EFLAGS)]>,
1841 def XOR32mi : Ii32<0x81, MRM6m,
1842 (outs), (ins i32mem:$dst, i32imm:$src),
1843 "xor{l}\t{$src, $dst|$dst, $src}",
1844 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1845 (implicit EFLAGS)]>;
1846 def XOR16mi8 : Ii8<0x83, MRM6m,
1847 (outs), (ins i16mem:$dst, i16i8imm :$src),
1848 "xor{w}\t{$src, $dst|$dst, $src}",
1849 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1850 (implicit EFLAGS)]>,
1852 def XOR32mi8 : Ii8<0x83, MRM6m,
1853 (outs), (ins i32mem:$dst, i32i8imm :$src),
1854 "xor{l}\t{$src, $dst|$dst, $src}",
1855 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1856 (implicit EFLAGS)]>;
1858 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
1859 "xor{b}\t{$src, %al|%al, $src}", []>;
1860 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
1861 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1862 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
1863 "xor{l}\t{$src, %eax|%eax, $src}", []>;
1864 } // Constraints = ""
1865 } // Defs = [EFLAGS]
1867 // Shift instructions
1868 let Defs = [EFLAGS] in {
1869 let Uses = [CL] in {
1870 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
1871 "shl{b}\t{%cl, $dst|$dst, CL}",
1872 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
1873 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
1874 "shl{w}\t{%cl, $dst|$dst, CL}",
1875 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
1876 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
1877 "shl{l}\t{%cl, $dst|$dst, CL}",
1878 [(set GR32:$dst, (shl GR32:$src1, CL))]>;
1881 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1882 "shl{b}\t{$src2, $dst|$dst, $src2}",
1883 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1885 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1886 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1887 "shl{w}\t{$src2, $dst|$dst, $src2}",
1888 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1889 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1890 "shl{l}\t{$src2, $dst|$dst, $src2}",
1891 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1893 // NOTE: We don't include patterns for shifts of a register by one, because
1894 // 'add reg,reg' is cheaper.
1896 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
1897 "shl{b}\t$dst", []>;
1898 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
1899 "shl{w}\t$dst", []>, OpSize;
1900 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
1901 "shl{l}\t$dst", []>;
1903 } // isConvertibleToThreeAddress = 1
1905 let Constraints = "" in {
1906 let Uses = [CL] in {
1907 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1908 "shl{b}\t{%cl, $dst|$dst, CL}",
1909 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1910 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1911 "shl{w}\t{%cl, $dst|$dst, CL}",
1912 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1913 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1914 "shl{l}\t{%cl, $dst|$dst, CL}",
1915 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1917 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1918 "shl{b}\t{$src, $dst|$dst, $src}",
1919 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1920 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1921 "shl{w}\t{$src, $dst|$dst, $src}",
1922 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1924 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1925 "shl{l}\t{$src, $dst|$dst, $src}",
1926 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1929 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1931 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1932 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1934 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1936 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1938 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1939 } // Constraints = ""
1941 let Uses = [CL] in {
1942 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
1943 "shr{b}\t{%cl, $dst|$dst, CL}",
1944 [(set GR8:$dst, (srl GR8:$src1, CL))]>;
1945 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1946 "shr{w}\t{%cl, $dst|$dst, CL}",
1947 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
1948 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1949 "shr{l}\t{%cl, $dst|$dst, CL}",
1950 [(set GR32:$dst, (srl GR32:$src1, CL))]>;
1953 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1954 "shr{b}\t{$src2, $dst|$dst, $src2}",
1955 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1956 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1957 "shr{w}\t{$src2, $dst|$dst, $src2}",
1958 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1959 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1960 "shr{l}\t{$src2, $dst|$dst, $src2}",
1961 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1964 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1966 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1967 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1969 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1970 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1972 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1974 let Constraints = "" in {
1975 let Uses = [CL] in {
1976 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1977 "shr{b}\t{%cl, $dst|$dst, CL}",
1978 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1979 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1980 "shr{w}\t{%cl, $dst|$dst, CL}",
1981 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1983 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1984 "shr{l}\t{%cl, $dst|$dst, CL}",
1985 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1987 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1988 "shr{b}\t{$src, $dst|$dst, $src}",
1989 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1990 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1991 "shr{w}\t{$src, $dst|$dst, $src}",
1992 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1994 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1995 "shr{l}\t{$src, $dst|$dst, $src}",
1996 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1999 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2001 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2002 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2004 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2005 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2007 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2008 } // Constraints = ""
2010 let Uses = [CL] in {
2011 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2012 "sar{b}\t{%cl, $dst|$dst, CL}",
2013 [(set GR8:$dst, (sra GR8:$src1, CL))]>;
2014 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2015 "sar{w}\t{%cl, $dst|$dst, CL}",
2016 [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize;
2017 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2018 "sar{l}\t{%cl, $dst|$dst, CL}",
2019 [(set GR32:$dst, (sra GR32:$src1, CL))]>;
2022 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2023 "sar{b}\t{$src2, $dst|$dst, $src2}",
2024 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2025 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2026 "sar{w}\t{$src2, $dst|$dst, $src2}",
2027 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2029 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2030 "sar{l}\t{$src2, $dst|$dst, $src2}",
2031 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2034 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2036 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2037 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2039 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2040 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2042 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2044 let Constraints = "" in {
2045 let Uses = [CL] in {
2046 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2047 "sar{b}\t{%cl, $dst|$dst, CL}",
2048 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2049 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2050 "sar{w}\t{%cl, $dst|$dst, CL}",
2051 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2052 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2053 "sar{l}\t{%cl, $dst|$dst, CL}",
2054 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2056 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2057 "sar{b}\t{$src, $dst|$dst, $src}",
2058 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2059 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2060 "sar{w}\t{$src, $dst|$dst, $src}",
2061 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2063 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2064 "sar{l}\t{$src, $dst|$dst, $src}",
2065 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2068 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2070 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2071 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2073 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2075 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2077 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2078 } // Constraints = ""
2080 // Rotate instructions
2082 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2083 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2084 let Uses = [CL] in {
2085 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2086 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2088 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2089 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2091 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2092 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2093 let Uses = [CL] in {
2094 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2095 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2097 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2098 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2100 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2101 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2102 let Uses = [CL] in {
2103 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2104 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2106 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2107 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2109 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2110 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2111 let Uses = [CL] in {
2112 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2113 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2115 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2116 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2118 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2119 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2120 let Uses = [CL] in {
2121 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2122 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2124 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2125 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2127 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2128 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2129 let Uses = [CL] in {
2130 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2131 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2133 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2134 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2136 let Constraints = "" in {
2137 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2138 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2139 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2140 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2141 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2142 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2143 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2144 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2145 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2146 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2147 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2148 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2149 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2150 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2151 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2152 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2153 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2154 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2155 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2156 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2157 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2158 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2159 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2160 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2162 let Uses = [CL] in {
2163 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2164 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2165 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2166 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2167 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2168 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2169 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2170 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2171 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2172 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2173 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2174 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2176 } // Constraints = ""
2178 // FIXME: provide shorter instructions when imm8 == 1
2179 let Uses = [CL] in {
2180 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2181 "rol{b}\t{%cl, $dst|$dst, CL}",
2182 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
2183 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2184 "rol{w}\t{%cl, $dst|$dst, CL}",
2185 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize;
2186 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2187 "rol{l}\t{%cl, $dst|$dst, CL}",
2188 [(set GR32:$dst, (rotl GR32:$src1, CL))]>;
2191 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2192 "rol{b}\t{$src2, $dst|$dst, $src2}",
2193 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2194 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2195 "rol{w}\t{$src2, $dst|$dst, $src2}",
2196 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2198 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2199 "rol{l}\t{$src2, $dst|$dst, $src2}",
2200 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2203 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2205 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2206 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2208 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2209 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2211 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2213 let Constraints = "" in {
2214 let Uses = [CL] in {
2215 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2216 "rol{b}\t{%cl, $dst|$dst, CL}",
2217 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2218 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2219 "rol{w}\t{%cl, $dst|$dst, CL}",
2220 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2221 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2222 "rol{l}\t{%cl, $dst|$dst, CL}",
2223 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2225 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2226 "rol{b}\t{$src, $dst|$dst, $src}",
2227 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2228 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2229 "rol{w}\t{$src, $dst|$dst, $src}",
2230 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2232 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2233 "rol{l}\t{$src, $dst|$dst, $src}",
2234 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2237 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2239 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2240 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2242 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2244 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2246 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2247 } // Constraints = ""
2249 let Uses = [CL] in {
2250 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2251 "ror{b}\t{%cl, $dst|$dst, CL}",
2252 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
2253 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2254 "ror{w}\t{%cl, $dst|$dst, CL}",
2255 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize;
2256 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2257 "ror{l}\t{%cl, $dst|$dst, CL}",
2258 [(set GR32:$dst, (rotr GR32:$src1, CL))]>;
2261 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2262 "ror{b}\t{$src2, $dst|$dst, $src2}",
2263 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2264 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2265 "ror{w}\t{$src2, $dst|$dst, $src2}",
2266 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2268 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2269 "ror{l}\t{$src2, $dst|$dst, $src2}",
2270 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2273 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2275 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2276 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2278 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2279 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2281 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2283 let Constraints = "" in {
2284 let Uses = [CL] in {
2285 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2286 "ror{b}\t{%cl, $dst|$dst, CL}",
2287 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2288 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2289 "ror{w}\t{%cl, $dst|$dst, CL}",
2290 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2291 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2292 "ror{l}\t{%cl, $dst|$dst, CL}",
2293 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2295 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2296 "ror{b}\t{$src, $dst|$dst, $src}",
2297 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2298 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2299 "ror{w}\t{$src, $dst|$dst, $src}",
2300 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2302 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2303 "ror{l}\t{$src, $dst|$dst, $src}",
2304 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2307 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2309 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2310 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2312 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2314 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2316 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2317 } // Constraints = ""
2320 // Double shift instructions (generalizations of rotate)
2321 let Uses = [CL] in {
2322 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2323 (ins GR32:$src1, GR32:$src2),
2324 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2325 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2326 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2327 (ins GR32:$src1, GR32:$src2),
2328 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2329 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2330 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2331 (ins GR16:$src1, GR16:$src2),
2332 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2333 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2335 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2336 (ins GR16:$src1, GR16:$src2),
2337 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2338 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2342 let isCommutable = 1 in { // These instructions commute to each other.
2343 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2345 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2346 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2347 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2350 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2352 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2353 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2354 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2357 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2359 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2360 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2361 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2364 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2366 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2367 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2368 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2373 let Constraints = "" in {
2374 let Uses = [CL] in {
2375 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2376 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2377 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2379 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2380 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2381 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2384 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2385 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2386 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2387 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2388 (i8 imm:$src3)), addr:$dst)]>,
2390 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2391 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2392 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2393 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2394 (i8 imm:$src3)), addr:$dst)]>,
2397 let Uses = [CL] in {
2398 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2399 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2400 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2401 addr:$dst)]>, TB, OpSize;
2402 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2403 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2404 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2405 addr:$dst)]>, TB, OpSize;
2407 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2408 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2409 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2410 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2411 (i8 imm:$src3)), addr:$dst)]>,
2413 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2414 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2415 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2416 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2417 (i8 imm:$src3)), addr:$dst)]>,
2419 } // Constraints = ""
2420 } // Defs = [EFLAGS]
2424 let Defs = [EFLAGS] in {
2425 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2426 // Register-Register Addition
2427 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2428 (ins GR8 :$src1, GR8 :$src2),
2429 "add{b}\t{$src2, $dst|$dst, $src2}",
2430 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2432 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2433 // Register-Register Addition
2434 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2435 (ins GR16:$src1, GR16:$src2),
2436 "add{w}\t{$src2, $dst|$dst, $src2}",
2437 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2438 GR16:$src2))]>, OpSize;
2439 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2440 (ins GR32:$src1, GR32:$src2),
2441 "add{l}\t{$src2, $dst|$dst, $src2}",
2442 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2444 } // end isConvertibleToThreeAddress
2445 } // end isCommutable
2447 // These are alternate spellings for use by the disassembler, we mark them as
2448 // code gen only to ensure they aren't matched by the assembler.
2449 let isCodeGenOnly = 1 in {
2450 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2451 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2452 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2453 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2454 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2455 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2458 // Register-Memory Addition
2459 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2460 (ins GR8 :$src1, i8mem :$src2),
2461 "add{b}\t{$src2, $dst|$dst, $src2}",
2462 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2463 (load addr:$src2)))]>;
2464 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2465 (ins GR16:$src1, i16mem:$src2),
2466 "add{w}\t{$src2, $dst|$dst, $src2}",
2467 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2468 (load addr:$src2)))]>, OpSize;
2469 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2470 (ins GR32:$src1, i32mem:$src2),
2471 "add{l}\t{$src2, $dst|$dst, $src2}",
2472 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2473 (load addr:$src2)))]>;
2475 // Register-Integer Addition
2476 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2477 "add{b}\t{$src2, $dst|$dst, $src2}",
2478 [(set GR8:$dst, EFLAGS,
2479 (X86add_flag GR8:$src1, imm:$src2))]>;
2481 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2482 // Register-Integer Addition
2483 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2484 (ins GR16:$src1, i16imm:$src2),
2485 "add{w}\t{$src2, $dst|$dst, $src2}",
2486 [(set GR16:$dst, EFLAGS,
2487 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2488 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2489 (ins GR32:$src1, i32imm:$src2),
2490 "add{l}\t{$src2, $dst|$dst, $src2}",
2491 [(set GR32:$dst, EFLAGS,
2492 (X86add_flag GR32:$src1, imm:$src2))]>;
2493 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2494 (ins GR16:$src1, i16i8imm:$src2),
2495 "add{w}\t{$src2, $dst|$dst, $src2}",
2496 [(set GR16:$dst, EFLAGS,
2497 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2498 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2499 (ins GR32:$src1, i32i8imm:$src2),
2500 "add{l}\t{$src2, $dst|$dst, $src2}",
2501 [(set GR32:$dst, EFLAGS,
2502 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2505 let Constraints = "" in {
2506 // Memory-Register Addition
2507 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2508 "add{b}\t{$src2, $dst|$dst, $src2}",
2509 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2510 (implicit EFLAGS)]>;
2511 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2512 "add{w}\t{$src2, $dst|$dst, $src2}",
2513 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2514 (implicit EFLAGS)]>, OpSize;
2515 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2516 "add{l}\t{$src2, $dst|$dst, $src2}",
2517 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2518 (implicit EFLAGS)]>;
2519 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2520 "add{b}\t{$src2, $dst|$dst, $src2}",
2521 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2522 (implicit EFLAGS)]>;
2523 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2524 "add{w}\t{$src2, $dst|$dst, $src2}",
2525 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2526 (implicit EFLAGS)]>, OpSize;
2527 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2528 "add{l}\t{$src2, $dst|$dst, $src2}",
2529 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2530 (implicit EFLAGS)]>;
2531 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2532 "add{w}\t{$src2, $dst|$dst, $src2}",
2533 [(store (add (load addr:$dst), i16immSExt8:$src2),
2535 (implicit EFLAGS)]>, OpSize;
2536 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2537 "add{l}\t{$src2, $dst|$dst, $src2}",
2538 [(store (add (load addr:$dst), i32immSExt8:$src2),
2540 (implicit EFLAGS)]>;
2543 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2544 "add{b}\t{$src, %al|%al, $src}", []>;
2545 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2546 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2547 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2548 "add{l}\t{$src, %eax|%eax, $src}", []>;
2549 } // Constraints = ""
2551 let Uses = [EFLAGS] in {
2552 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2553 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2554 "adc{b}\t{$src2, $dst|$dst, $src2}",
2555 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2556 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2557 (ins GR16:$src1, GR16:$src2),
2558 "adc{w}\t{$src2, $dst|$dst, $src2}",
2559 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2560 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2561 (ins GR32:$src1, GR32:$src2),
2562 "adc{l}\t{$src2, $dst|$dst, $src2}",
2563 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2566 let isCodeGenOnly = 1 in {
2567 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2568 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2569 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2570 (ins GR16:$src1, GR16:$src2),
2571 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2572 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2573 (ins GR32:$src1, GR32:$src2),
2574 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2577 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2578 (ins GR8:$src1, i8mem:$src2),
2579 "adc{b}\t{$src2, $dst|$dst, $src2}",
2580 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2581 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2582 (ins GR16:$src1, i16mem:$src2),
2583 "adc{w}\t{$src2, $dst|$dst, $src2}",
2584 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2586 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2587 (ins GR32:$src1, i32mem:$src2),
2588 "adc{l}\t{$src2, $dst|$dst, $src2}",
2589 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2590 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2591 "adc{b}\t{$src2, $dst|$dst, $src2}",
2592 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2593 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2594 (ins GR16:$src1, i16imm:$src2),
2595 "adc{w}\t{$src2, $dst|$dst, $src2}",
2596 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2597 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2598 (ins GR16:$src1, i16i8imm:$src2),
2599 "adc{w}\t{$src2, $dst|$dst, $src2}",
2600 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2602 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2603 (ins GR32:$src1, i32imm:$src2),
2604 "adc{l}\t{$src2, $dst|$dst, $src2}",
2605 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2606 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2607 (ins GR32:$src1, i32i8imm:$src2),
2608 "adc{l}\t{$src2, $dst|$dst, $src2}",
2609 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2611 let Constraints = "" in {
2612 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2613 "adc{b}\t{$src2, $dst|$dst, $src2}",
2614 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2615 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2616 "adc{w}\t{$src2, $dst|$dst, $src2}",
2617 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2619 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2620 "adc{l}\t{$src2, $dst|$dst, $src2}",
2621 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2622 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2623 "adc{b}\t{$src2, $dst|$dst, $src2}",
2624 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2625 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2626 "adc{w}\t{$src2, $dst|$dst, $src2}",
2627 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2629 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2630 "adc{w}\t{$src2, $dst|$dst, $src2}",
2631 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2633 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2634 "adc{l}\t{$src2, $dst|$dst, $src2}",
2635 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2636 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2637 "adc{l}\t{$src2, $dst|$dst, $src2}",
2638 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2640 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2641 "adc{b}\t{$src, %al|%al, $src}", []>;
2642 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2643 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2644 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2645 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2646 } // Constraints = ""
2647 } // Uses = [EFLAGS]
2649 // Register-Register Subtraction
2650 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2651 "sub{b}\t{$src2, $dst|$dst, $src2}",
2652 [(set GR8:$dst, EFLAGS,
2653 (X86sub_flag GR8:$src1, GR8:$src2))]>;
2654 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2655 "sub{w}\t{$src2, $dst|$dst, $src2}",
2656 [(set GR16:$dst, EFLAGS,
2657 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
2658 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2659 "sub{l}\t{$src2, $dst|$dst, $src2}",
2660 [(set GR32:$dst, EFLAGS,
2661 (X86sub_flag GR32:$src1, GR32:$src2))]>;
2663 let isCodeGenOnly = 1 in {
2664 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2665 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2666 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2667 (ins GR16:$src1, GR16:$src2),
2668 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2669 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2670 (ins GR32:$src1, GR32:$src2),
2671 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2674 // Register-Memory Subtraction
2675 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2676 (ins GR8 :$src1, i8mem :$src2),
2677 "sub{b}\t{$src2, $dst|$dst, $src2}",
2678 [(set GR8:$dst, EFLAGS,
2679 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
2680 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2681 (ins GR16:$src1, i16mem:$src2),
2682 "sub{w}\t{$src2, $dst|$dst, $src2}",
2683 [(set GR16:$dst, EFLAGS,
2684 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
2685 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2686 (ins GR32:$src1, i32mem:$src2),
2687 "sub{l}\t{$src2, $dst|$dst, $src2}",
2688 [(set GR32:$dst, EFLAGS,
2689 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
2691 // Register-Integer Subtraction
2692 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2693 (ins GR8:$src1, i8imm:$src2),
2694 "sub{b}\t{$src2, $dst|$dst, $src2}",
2695 [(set GR8:$dst, EFLAGS,
2696 (X86sub_flag GR8:$src1, imm:$src2))]>;
2697 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2698 (ins GR16:$src1, i16imm:$src2),
2699 "sub{w}\t{$src2, $dst|$dst, $src2}",
2700 [(set GR16:$dst, EFLAGS,
2701 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
2702 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2703 (ins GR32:$src1, i32imm:$src2),
2704 "sub{l}\t{$src2, $dst|$dst, $src2}",
2705 [(set GR32:$dst, EFLAGS,
2706 (X86sub_flag GR32:$src1, imm:$src2))]>;
2707 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2708 (ins GR16:$src1, i16i8imm:$src2),
2709 "sub{w}\t{$src2, $dst|$dst, $src2}",
2710 [(set GR16:$dst, EFLAGS,
2711 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2712 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2713 (ins GR32:$src1, i32i8imm:$src2),
2714 "sub{l}\t{$src2, $dst|$dst, $src2}",
2715 [(set GR32:$dst, EFLAGS,
2716 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
2718 let Constraints = "" in {
2719 // Memory-Register Subtraction
2720 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2721 "sub{b}\t{$src2, $dst|$dst, $src2}",
2722 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2723 (implicit EFLAGS)]>;
2724 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2725 "sub{w}\t{$src2, $dst|$dst, $src2}",
2726 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2727 (implicit EFLAGS)]>, OpSize;
2728 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2729 "sub{l}\t{$src2, $dst|$dst, $src2}",
2730 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2731 (implicit EFLAGS)]>;
2733 // Memory-Integer Subtraction
2734 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2735 "sub{b}\t{$src2, $dst|$dst, $src2}",
2736 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2737 (implicit EFLAGS)]>;
2738 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2739 "sub{w}\t{$src2, $dst|$dst, $src2}",
2740 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2741 (implicit EFLAGS)]>, OpSize;
2742 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2743 "sub{l}\t{$src2, $dst|$dst, $src2}",
2744 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2745 (implicit EFLAGS)]>;
2746 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2747 "sub{w}\t{$src2, $dst|$dst, $src2}",
2748 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2750 (implicit EFLAGS)]>, OpSize;
2751 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2752 "sub{l}\t{$src2, $dst|$dst, $src2}",
2753 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2755 (implicit EFLAGS)]>;
2757 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
2758 "sub{b}\t{$src, %al|%al, $src}", []>;
2759 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
2760 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2761 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
2762 "sub{l}\t{$src, %eax|%eax, $src}", []>;
2763 } // Constraints = ""
2765 let Uses = [EFLAGS] in {
2766 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2767 (ins GR8:$src1, GR8:$src2),
2768 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2769 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2770 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2771 (ins GR16:$src1, GR16:$src2),
2772 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2773 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2774 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2775 (ins GR32:$src1, GR32:$src2),
2776 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2777 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2779 let Constraints = "" in {
2780 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2781 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2782 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2783 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2784 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2785 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2787 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2788 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2789 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2790 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2791 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2792 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2793 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2794 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2795 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2797 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2798 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2799 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2801 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2802 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2803 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2804 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2805 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2806 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2808 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
2809 "sbb{b}\t{$src, %al|%al, $src}", []>;
2810 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
2811 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2812 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
2813 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
2814 } // Constraints = ""
2816 let isCodeGenOnly = 1 in {
2817 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2818 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
2819 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
2820 (ins GR16:$src1, GR16:$src2),
2821 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2822 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
2823 (ins GR32:$src1, GR32:$src2),
2824 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
2827 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2828 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2829 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
2830 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2831 (ins GR16:$src1, i16mem:$src2),
2832 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2833 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
2835 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2836 (ins GR32:$src1, i32mem:$src2),
2837 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2838 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2839 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2840 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2841 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
2842 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2843 (ins GR16:$src1, i16imm:$src2),
2844 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2845 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
2846 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2847 (ins GR16:$src1, i16i8imm:$src2),
2848 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2849 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2851 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2852 (ins GR32:$src1, i32imm:$src2),
2853 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2854 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2855 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2856 (ins GR32:$src1, i32i8imm:$src2),
2857 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2858 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2859 } // Uses = [EFLAGS]
2860 } // Defs = [EFLAGS]
2862 let Defs = [EFLAGS] in {
2863 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2864 // Register-Register Signed Integer Multiply
2865 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2866 "imul{w}\t{$src2, $dst|$dst, $src2}",
2867 [(set GR16:$dst, EFLAGS,
2868 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
2869 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2870 "imul{l}\t{$src2, $dst|$dst, $src2}",
2871 [(set GR32:$dst, EFLAGS,
2872 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
2875 // Register-Memory Signed Integer Multiply
2876 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2877 (ins GR16:$src1, i16mem:$src2),
2878 "imul{w}\t{$src2, $dst|$dst, $src2}",
2879 [(set GR16:$dst, EFLAGS,
2880 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
2882 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
2883 (ins GR32:$src1, i32mem:$src2),
2884 "imul{l}\t{$src2, $dst|$dst, $src2}",
2885 [(set GR32:$dst, EFLAGS,
2886 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
2887 } // Defs = [EFLAGS]
2888 } // end Two Address instructions
2890 // Suprisingly enough, these are not two address instructions!
2891 let Defs = [EFLAGS] in {
2892 // Register-Integer Signed Integer Multiply
2893 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2894 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2895 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2896 [(set GR16:$dst, EFLAGS,
2897 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
2898 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2899 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2900 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2901 [(set GR32:$dst, EFLAGS,
2902 (X86smul_flag GR32:$src1, imm:$src2))]>;
2903 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2904 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2905 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2906 [(set GR16:$dst, EFLAGS,
2907 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
2909 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2910 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2911 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2912 [(set GR32:$dst, EFLAGS,
2913 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
2915 // Memory-Integer Signed Integer Multiply
2916 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2917 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2918 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2919 [(set GR16:$dst, EFLAGS,
2920 (X86smul_flag (load addr:$src1), imm:$src2))]>,
2922 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2923 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2924 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2925 [(set GR32:$dst, EFLAGS,
2926 (X86smul_flag (load addr:$src1), imm:$src2))]>;
2927 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2928 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2929 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2930 [(set GR16:$dst, EFLAGS,
2931 (X86smul_flag (load addr:$src1),
2932 i16immSExt8:$src2))]>, OpSize;
2933 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2934 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2935 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2936 [(set GR32:$dst, EFLAGS,
2937 (X86smul_flag (load addr:$src1),
2938 i32immSExt8:$src2))]>;
2939 } // Defs = [EFLAGS]
2941 //===----------------------------------------------------------------------===//
2942 // Test instructions are just like AND, except they don't generate a result.
2944 let Defs = [EFLAGS] in {
2945 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2946 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
2947 "test{b}\t{$src2, $src1|$src1, $src2}",
2948 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
2949 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
2950 "test{w}\t{$src2, $src1|$src1, $src2}",
2951 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
2954 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
2955 "test{l}\t{$src2, $src1|$src1, $src2}",
2956 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
2960 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
2961 "test{b}\t{$src, %al|%al, $src}", []>;
2962 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
2963 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2964 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
2965 "test{l}\t{$src, %eax|%eax, $src}", []>;
2967 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2968 "test{b}\t{$src2, $src1|$src1, $src2}",
2969 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
2971 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2972 "test{w}\t{$src2, $src1|$src1, $src2}",
2973 [(set EFLAGS, (X86cmp (and GR16:$src1,
2974 (loadi16 addr:$src2)), 0))]>, OpSize;
2975 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2976 "test{l}\t{$src2, $src1|$src1, $src2}",
2977 [(set EFLAGS, (X86cmp (and GR32:$src1,
2978 (loadi32 addr:$src2)), 0))]>;
2980 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2981 (outs), (ins GR8:$src1, i8imm:$src2),
2982 "test{b}\t{$src2, $src1|$src1, $src2}",
2983 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
2984 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2985 (outs), (ins GR16:$src1, i16imm:$src2),
2986 "test{w}\t{$src2, $src1|$src1, $src2}",
2987 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
2989 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2990 (outs), (ins GR32:$src1, i32imm:$src2),
2991 "test{l}\t{$src2, $src1|$src1, $src2}",
2992 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
2994 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2995 (outs), (ins i8mem:$src1, i8imm:$src2),
2996 "test{b}\t{$src2, $src1|$src1, $src2}",
2997 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
2999 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3000 (outs), (ins i16mem:$src1, i16imm:$src2),
3001 "test{w}\t{$src2, $src1|$src1, $src2}",
3002 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3004 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3005 (outs), (ins i32mem:$src1, i32imm:$src2),
3006 "test{l}\t{$src2, $src1|$src1, $src2}",
3007 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3009 } // Defs = [EFLAGS]
3012 // Condition code ops, incl. set if equal/not equal/...
3013 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3014 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3015 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3016 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3018 let Uses = [EFLAGS] in {
3019 // Use sbb to materialize carry bit.
3020 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3021 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3022 // However, Pat<> can't replicate the destination reg into the inputs of the
3024 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3026 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3027 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3028 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3029 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3031 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3032 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3035 def SETEr : I<0x94, MRM0r,
3036 (outs GR8 :$dst), (ins),
3038 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3040 def SETEm : I<0x94, MRM0m,
3041 (outs), (ins i8mem:$dst),
3043 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3046 def SETNEr : I<0x95, MRM0r,
3047 (outs GR8 :$dst), (ins),
3049 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3051 def SETNEm : I<0x95, MRM0m,
3052 (outs), (ins i8mem:$dst),
3054 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3057 def SETLr : I<0x9C, MRM0r,
3058 (outs GR8 :$dst), (ins),
3060 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3061 TB; // GR8 = < signed
3062 def SETLm : I<0x9C, MRM0m,
3063 (outs), (ins i8mem:$dst),
3065 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3066 TB; // [mem8] = < signed
3068 def SETGEr : I<0x9D, MRM0r,
3069 (outs GR8 :$dst), (ins),
3071 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3072 TB; // GR8 = >= signed
3073 def SETGEm : I<0x9D, MRM0m,
3074 (outs), (ins i8mem:$dst),
3076 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3077 TB; // [mem8] = >= signed
3079 def SETLEr : I<0x9E, MRM0r,
3080 (outs GR8 :$dst), (ins),
3082 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3083 TB; // GR8 = <= signed
3084 def SETLEm : I<0x9E, MRM0m,
3085 (outs), (ins i8mem:$dst),
3087 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3088 TB; // [mem8] = <= signed
3090 def SETGr : I<0x9F, MRM0r,
3091 (outs GR8 :$dst), (ins),
3093 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3094 TB; // GR8 = > signed
3095 def SETGm : I<0x9F, MRM0m,
3096 (outs), (ins i8mem:$dst),
3098 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3099 TB; // [mem8] = > signed
3101 def SETBr : I<0x92, MRM0r,
3102 (outs GR8 :$dst), (ins),
3104 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3105 TB; // GR8 = < unsign
3106 def SETBm : I<0x92, MRM0m,
3107 (outs), (ins i8mem:$dst),
3109 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3110 TB; // [mem8] = < unsign
3112 def SETAEr : I<0x93, MRM0r,
3113 (outs GR8 :$dst), (ins),
3115 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3116 TB; // GR8 = >= unsign
3117 def SETAEm : I<0x93, MRM0m,
3118 (outs), (ins i8mem:$dst),
3120 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3121 TB; // [mem8] = >= unsign
3123 def SETBEr : I<0x96, MRM0r,
3124 (outs GR8 :$dst), (ins),
3126 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3127 TB; // GR8 = <= unsign
3128 def SETBEm : I<0x96, MRM0m,
3129 (outs), (ins i8mem:$dst),
3131 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3132 TB; // [mem8] = <= unsign
3134 def SETAr : I<0x97, MRM0r,
3135 (outs GR8 :$dst), (ins),
3137 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3138 TB; // GR8 = > signed
3139 def SETAm : I<0x97, MRM0m,
3140 (outs), (ins i8mem:$dst),
3142 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3143 TB; // [mem8] = > signed
3145 def SETSr : I<0x98, MRM0r,
3146 (outs GR8 :$dst), (ins),
3148 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3149 TB; // GR8 = <sign bit>
3150 def SETSm : I<0x98, MRM0m,
3151 (outs), (ins i8mem:$dst),
3153 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3154 TB; // [mem8] = <sign bit>
3155 def SETNSr : I<0x99, MRM0r,
3156 (outs GR8 :$dst), (ins),
3158 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3159 TB; // GR8 = !<sign bit>
3160 def SETNSm : I<0x99, MRM0m,
3161 (outs), (ins i8mem:$dst),
3163 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3164 TB; // [mem8] = !<sign bit>
3166 def SETPr : I<0x9A, MRM0r,
3167 (outs GR8 :$dst), (ins),
3169 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3171 def SETPm : I<0x9A, MRM0m,
3172 (outs), (ins i8mem:$dst),
3174 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3175 TB; // [mem8] = parity
3176 def SETNPr : I<0x9B, MRM0r,
3177 (outs GR8 :$dst), (ins),
3179 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3180 TB; // GR8 = not parity
3181 def SETNPm : I<0x9B, MRM0m,
3182 (outs), (ins i8mem:$dst),
3184 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3185 TB; // [mem8] = not parity
3187 def SETOr : I<0x90, MRM0r,
3188 (outs GR8 :$dst), (ins),
3190 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3191 TB; // GR8 = overflow
3192 def SETOm : I<0x90, MRM0m,
3193 (outs), (ins i8mem:$dst),
3195 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3196 TB; // [mem8] = overflow
3197 def SETNOr : I<0x91, MRM0r,
3198 (outs GR8 :$dst), (ins),
3200 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3201 TB; // GR8 = not overflow
3202 def SETNOm : I<0x91, MRM0m,
3203 (outs), (ins i8mem:$dst),
3205 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3206 TB; // [mem8] = not overflow
3207 } // Uses = [EFLAGS]
3210 // Integer comparisons
3211 let Defs = [EFLAGS] in {
3212 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3213 "cmp{b}\t{$src, %al|%al, $src}", []>;
3214 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3215 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3216 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3217 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3219 def CMP8rr : I<0x38, MRMDestReg,
3220 (outs), (ins GR8 :$src1, GR8 :$src2),
3221 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3222 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3223 def CMP16rr : I<0x39, MRMDestReg,
3224 (outs), (ins GR16:$src1, GR16:$src2),
3225 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3226 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3227 def CMP32rr : I<0x39, MRMDestReg,
3228 (outs), (ins GR32:$src1, GR32:$src2),
3229 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3230 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3231 def CMP8mr : I<0x38, MRMDestMem,
3232 (outs), (ins i8mem :$src1, GR8 :$src2),
3233 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3234 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3235 def CMP16mr : I<0x39, MRMDestMem,
3236 (outs), (ins i16mem:$src1, GR16:$src2),
3237 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3238 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3240 def CMP32mr : I<0x39, MRMDestMem,
3241 (outs), (ins i32mem:$src1, GR32:$src2),
3242 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3243 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3244 def CMP8rm : I<0x3A, MRMSrcMem,
3245 (outs), (ins GR8 :$src1, i8mem :$src2),
3246 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3247 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3248 def CMP16rm : I<0x3B, MRMSrcMem,
3249 (outs), (ins GR16:$src1, i16mem:$src2),
3250 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3251 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3253 def CMP32rm : I<0x3B, MRMSrcMem,
3254 (outs), (ins GR32:$src1, i32mem:$src2),
3255 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3256 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3258 // These are alternate spellings for use by the disassembler, we mark them as
3259 // code gen only to ensure they aren't matched by the assembler.
3260 let isCodeGenOnly = 1 in {
3261 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3262 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3263 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3264 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3265 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3266 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3269 def CMP8ri : Ii8<0x80, MRM7r,
3270 (outs), (ins GR8:$src1, i8imm:$src2),
3271 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3272 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3273 def CMP16ri : Ii16<0x81, MRM7r,
3274 (outs), (ins GR16:$src1, i16imm:$src2),
3275 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3276 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3277 def CMP32ri : Ii32<0x81, MRM7r,
3278 (outs), (ins GR32:$src1, i32imm:$src2),
3279 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3280 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3281 def CMP8mi : Ii8 <0x80, MRM7m,
3282 (outs), (ins i8mem :$src1, i8imm :$src2),
3283 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3284 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3285 def CMP16mi : Ii16<0x81, MRM7m,
3286 (outs), (ins i16mem:$src1, i16imm:$src2),
3287 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3288 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3290 def CMP32mi : Ii32<0x81, MRM7m,
3291 (outs), (ins i32mem:$src1, i32imm:$src2),
3292 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3293 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3294 def CMP16ri8 : Ii8<0x83, MRM7r,
3295 (outs), (ins GR16:$src1, i16i8imm:$src2),
3296 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3297 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3299 def CMP16mi8 : Ii8<0x83, MRM7m,
3300 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3301 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3302 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3303 i16immSExt8:$src2))]>, OpSize;
3304 def CMP32mi8 : Ii8<0x83, MRM7m,
3305 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3306 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3307 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3308 i32immSExt8:$src2))]>;
3309 def CMP32ri8 : Ii8<0x83, MRM7r,
3310 (outs), (ins GR32:$src1, i32i8imm:$src2),
3311 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3312 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3313 } // Defs = [EFLAGS]
3316 // TODO: BTC, BTR, and BTS
3317 let Defs = [EFLAGS] in {
3318 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3319 "bt{w}\t{$src2, $src1|$src1, $src2}",
3320 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3321 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3322 "bt{l}\t{$src2, $src1|$src1, $src2}",
3323 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3325 // Unlike with the register+register form, the memory+register form of the
3326 // bt instruction does not ignore the high bits of the index. From ISel's
3327 // perspective, this is pretty bizarre. Make these instructions disassembly
3330 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3331 "bt{w}\t{$src2, $src1|$src1, $src2}",
3332 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3333 // (implicit EFLAGS)]
3335 >, OpSize, TB, Requires<[FastBTMem]>;
3336 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3337 "bt{l}\t{$src2, $src1|$src1, $src2}",
3338 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3339 // (implicit EFLAGS)]
3341 >, TB, Requires<[FastBTMem]>;
3343 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3344 "bt{w}\t{$src2, $src1|$src1, $src2}",
3345 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3347 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3348 "bt{l}\t{$src2, $src1|$src1, $src2}",
3349 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3350 // Note that these instructions don't need FastBTMem because that
3351 // only applies when the other operand is in a register. When it's
3352 // an immediate, bt is still fast.
3353 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3354 "bt{w}\t{$src2, $src1|$src1, $src2}",
3355 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3357 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3358 "bt{l}\t{$src2, $src1|$src1, $src2}",
3359 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3362 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3363 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3364 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3365 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3366 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3367 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3368 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3369 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3370 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3371 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3372 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3373 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3374 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3375 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3376 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3377 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3379 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3380 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3381 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3382 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3383 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3384 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3385 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3386 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3387 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3388 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3389 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3390 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3391 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3392 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3393 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3394 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3396 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3397 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3398 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3399 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3400 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3401 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3402 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3403 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3404 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3405 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3406 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3407 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3408 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3409 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3410 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3411 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3412 } // Defs = [EFLAGS]
3414 // Sign/Zero extenders
3415 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3416 // of the register here. This has a smaller encoding and avoids a
3417 // partial-register update. Actual movsbw included for the disassembler.
3418 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3419 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3420 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3421 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3422 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3423 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3424 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3425 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3426 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3427 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3428 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3429 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3430 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3431 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3432 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3433 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3434 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3435 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3436 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3437 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3439 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3440 // of the register here. This has a smaller encoding and avoids a
3441 // partial-register update. Actual movzbw included for the disassembler.
3442 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3443 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3444 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3445 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3446 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3447 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3448 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3449 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3450 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3451 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3452 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3453 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3454 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3455 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3456 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3457 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3458 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3459 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3460 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3461 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3463 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3464 // except that they use GR32_NOREX for the output operand register class
3465 // instead of GR32. This allows them to operate on h registers on x86-64.
3466 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3467 (outs GR32_NOREX:$dst), (ins GR8:$src),
3468 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3471 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3472 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3473 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3476 let neverHasSideEffects = 1 in {
3477 let Defs = [AX], Uses = [AL] in
3478 def CBW : I<0x98, RawFrm, (outs), (ins),
3479 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3480 let Defs = [EAX], Uses = [AX] in
3481 def CWDE : I<0x98, RawFrm, (outs), (ins),
3482 "{cwtl|cwde}", []>; // EAX = signext(AX)
3484 let Defs = [AX,DX], Uses = [AX] in
3485 def CWD : I<0x99, RawFrm, (outs), (ins),
3486 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3487 let Defs = [EAX,EDX], Uses = [EAX] in
3488 def CDQ : I<0x99, RawFrm, (outs), (ins),
3489 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3494 //===----------------------------------------------------------------------===//
3500 // TODO: Get this to fold the constant into the instruction.
3501 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
3503 "or{l}\t{$zero, $dst|$dst, $zero}",
3504 []>, Requires<[In32BitMode]>, LOCK;
3506 let hasSideEffects = 1 in {
3507 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
3509 [(X86MemBarrier)]>, Requires<[HasSSE2]>;
3512 // Atomic swap. These are just normal xchg instructions. But since a memory
3513 // operand is referenced, the atomicity is ensured.
3514 let Constraints = "$val = $dst" in {
3515 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3516 (ins GR32:$val, i32mem:$ptr),
3517 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3518 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3519 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3520 (ins GR16:$val, i16mem:$ptr),
3521 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3522 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3524 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3525 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3526 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3528 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3529 "xchg{l}\t{$val, $src|$src, $val}", []>;
3530 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3531 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3532 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3533 "xchg{b}\t{$val, $src|$src, $val}", []>;
3536 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3537 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3538 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3539 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3541 // Atomic compare and swap.
3542 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3543 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3545 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3546 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3548 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3549 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3552 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3555 let Defs = [AX, EFLAGS], Uses = [AX] in {
3556 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3558 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3559 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3561 let Defs = [AL, EFLAGS], Uses = [AL] in {
3562 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3564 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3565 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3568 // Atomic exchange and add
3569 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3570 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3572 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3573 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3575 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3577 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3578 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3580 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3582 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3583 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3587 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3588 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3589 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3590 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3591 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3592 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3594 let mayLoad = 1, mayStore = 1 in {
3595 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3596 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3597 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3598 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3599 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3600 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3603 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3604 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3605 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3606 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3607 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3608 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3610 let mayLoad = 1, mayStore = 1 in {
3611 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3612 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3613 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3614 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3615 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3616 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3619 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3620 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3621 "cmpxchg8b\t$dst", []>, TB;
3623 // Optimized codegen when the non-memory output is not used.
3624 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3625 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
3626 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3628 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3629 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3631 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3632 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3634 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3635 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3637 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3638 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3640 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3641 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3643 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3644 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3646 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3647 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3649 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3651 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3653 "inc{b}\t$dst", []>, LOCK;
3654 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3656 "inc{w}\t$dst", []>, OpSize, LOCK;
3657 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3659 "inc{l}\t$dst", []>, LOCK;
3661 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3663 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3664 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3666 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3667 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3669 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3670 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3672 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3673 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3675 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3676 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3678 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3679 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3681 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3682 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3684 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3686 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3688 "dec{b}\t$dst", []>, LOCK;
3689 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3691 "dec{w}\t$dst", []>, OpSize, LOCK;
3692 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3694 "dec{l}\t$dst", []>, LOCK;
3697 // Atomic exchange, and, or, xor
3698 let Constraints = "$val = $dst", Defs = [EFLAGS],
3699 usesCustomInserter = 1 in {
3700 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3701 "#ATOMAND32 PSEUDO!",
3702 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3703 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3704 "#ATOMOR32 PSEUDO!",
3705 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3706 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3707 "#ATOMXOR32 PSEUDO!",
3708 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3709 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3710 "#ATOMNAND32 PSEUDO!",
3711 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3712 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3713 "#ATOMMIN32 PSEUDO!",
3714 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3715 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3716 "#ATOMMAX32 PSEUDO!",
3717 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3718 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3719 "#ATOMUMIN32 PSEUDO!",
3720 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3721 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3722 "#ATOMUMAX32 PSEUDO!",
3723 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3725 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3726 "#ATOMAND16 PSEUDO!",
3727 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3728 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3729 "#ATOMOR16 PSEUDO!",
3730 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3731 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3732 "#ATOMXOR16 PSEUDO!",
3733 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3734 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3735 "#ATOMNAND16 PSEUDO!",
3736 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3737 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3738 "#ATOMMIN16 PSEUDO!",
3739 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3740 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3741 "#ATOMMAX16 PSEUDO!",
3742 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3743 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3744 "#ATOMUMIN16 PSEUDO!",
3745 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3746 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3747 "#ATOMUMAX16 PSEUDO!",
3748 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3750 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3751 "#ATOMAND8 PSEUDO!",
3752 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3753 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3755 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3756 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3757 "#ATOMXOR8 PSEUDO!",
3758 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3759 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3760 "#ATOMNAND8 PSEUDO!",
3761 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3764 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3765 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3766 Uses = [EAX, EBX, ECX, EDX],
3767 mayLoad = 1, mayStore = 1,
3768 usesCustomInserter = 1 in {
3769 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3770 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3771 "#ATOMAND6432 PSEUDO!", []>;
3772 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3773 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3774 "#ATOMOR6432 PSEUDO!", []>;
3775 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3776 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3777 "#ATOMXOR6432 PSEUDO!", []>;
3778 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3779 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3780 "#ATOMNAND6432 PSEUDO!", []>;
3781 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3782 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3783 "#ATOMADD6432 PSEUDO!", []>;
3784 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3785 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3786 "#ATOMSUB6432 PSEUDO!", []>;
3787 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3788 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3789 "#ATOMSWAP6432 PSEUDO!", []>;
3792 // Lock instruction prefix
3793 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
3795 // Repeat string operation instruction prefixes
3796 // These uses the DF flag in the EFLAGS register to inc or dec ECX
3797 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
3798 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
3799 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
3800 // Repeat while not equal (used with CMPS and SCAS)
3801 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
3805 // String manipulation instructions
3807 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
3808 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
3809 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
3811 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
3812 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
3813 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
3816 // Flag instructions
3817 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
3818 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
3819 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
3820 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
3821 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
3822 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
3823 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
3825 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
3827 // Table lookup instructions
3828 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
3832 //===----------------------------------------------------------------------===//
3834 //===----------------------------------------------------------------------===//
3836 // Floating Point Stack Support
3837 include "X86InstrFPStack.td"
3840 include "X86Instr64bit.td"
3842 include "X86InstrControl.td"
3844 // SIMD support (SSE, MMX and AVX)
3845 include "X86InstrFragmentsSIMD.td"
3847 // FMA - Fused Multiply-Add support (requires FMA)
3848 include "X86InstrFMA.td"
3850 // SSE, MMX and 3DNow! vector support.
3851 include "X86InstrSSE.td"
3852 include "X86InstrMMX.td"
3853 include "X86Instr3DNow.td"
3855 include "X86InstrVMX.td"
3857 // System instructions.
3858 include "X86InstrSystem.td"
3860 // Compiler Pseudo Instructions and Pat Patterns
3861 include "X86InstrCompiler.td"