1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
117 [SDNPHasChain,SDNPSideEffect]>;
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
146 [SDNPHasChain, SDNPSideEffect]>;
148 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
155 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
158 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
159 [SDNPHasChain, SDNPMayStore,
160 SDNPMayLoad, SDNPMemOperand]>;
161 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
162 [SDNPHasChain, SDNPMayStore,
163 SDNPMayLoad, SDNPMemOperand]>;
164 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
165 [SDNPHasChain, SDNPMayStore,
166 SDNPMayLoad, SDNPMemOperand]>;
167 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
177 [SDNPHasChain, SDNPMayStore,
178 SDNPMayLoad, SDNPMemOperand]>;
179 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
182 def X86vastart_save_xmm_regs :
183 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
184 SDT_X86VASTART_SAVE_XMM_REGS,
185 [SDNPHasChain, SDNPVariadic]>;
187 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
190 def X86callseq_start :
191 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
192 [SDNPHasChain, SDNPOutGlue]>;
194 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
197 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
198 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
201 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
202 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
203 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
204 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
207 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
208 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
210 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
211 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
213 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
214 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
216 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
217 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
219 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
222 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
223 SDTypeProfile<1, 1, [SDTCisInt<0>,
225 [SDNPHasChain, SDNPSideEffect]>;
226 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
227 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
228 [SDNPHasChain, SDNPSideEffect]>;
230 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
231 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
233 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
235 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
236 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
238 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
240 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
241 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
243 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
244 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
245 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
247 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
249 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
252 def X86blsi : SDNode<"X86ISD::BLSI", SDTIntUnaryOp>;
253 def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>;
254 def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>;
255 def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntShiftOp>;
256 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
258 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
260 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
261 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
263 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
266 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
267 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
269 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
270 [SDNPHasChain, SDNPOutGlue]>;
272 //===----------------------------------------------------------------------===//
273 // X86 Operand Definitions.
276 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
277 // the index operand of an address, to conform to x86 encoding restrictions.
278 def ptr_rc_nosp : PointerLikeRegClass<1>;
280 // *mem - Operand definitions for the funky X86 addressing mode operands.
282 def X86MemAsmOperand : AsmOperandClass {
285 def X86Mem8AsmOperand : AsmOperandClass {
286 let Name = "Mem8"; let RenderMethod = "addMemOperands";
288 def X86Mem16AsmOperand : AsmOperandClass {
289 let Name = "Mem16"; let RenderMethod = "addMemOperands";
291 def X86Mem32AsmOperand : AsmOperandClass {
292 let Name = "Mem32"; let RenderMethod = "addMemOperands";
294 def X86Mem64AsmOperand : AsmOperandClass {
295 let Name = "Mem64"; let RenderMethod = "addMemOperands";
297 def X86Mem80AsmOperand : AsmOperandClass {
298 let Name = "Mem80"; let RenderMethod = "addMemOperands";
300 def X86Mem128AsmOperand : AsmOperandClass {
301 let Name = "Mem128"; let RenderMethod = "addMemOperands";
303 def X86Mem256AsmOperand : AsmOperandClass {
304 let Name = "Mem256"; let RenderMethod = "addMemOperands";
306 def X86Mem512AsmOperand : AsmOperandClass {
307 let Name = "Mem512"; let RenderMethod = "addMemOperands";
310 // Gather mem operands
311 def X86MemVX32Operand : AsmOperandClass {
312 let Name = "MemVX32"; let RenderMethod = "addMemOperands";
314 def X86MemVY32Operand : AsmOperandClass {
315 let Name = "MemVY32"; let RenderMethod = "addMemOperands";
317 def X86MemVZ32Operand : AsmOperandClass {
318 let Name = "MemVZ32"; let RenderMethod = "addMemOperands";
320 def X86MemVX64Operand : AsmOperandClass {
321 let Name = "MemVX64"; let RenderMethod = "addMemOperands";
323 def X86MemVY64Operand : AsmOperandClass {
324 let Name = "MemVY64"; let RenderMethod = "addMemOperands";
326 def X86MemVZ64Operand : AsmOperandClass {
327 let Name = "MemVZ64"; let RenderMethod = "addMemOperands";
330 def X86AbsMemAsmOperand : AsmOperandClass {
332 let SuperClasses = [X86MemAsmOperand];
334 class X86MemOperand<string printMethod> : Operand<iPTR> {
335 let PrintMethod = printMethod;
336 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
337 let ParserMatchClass = X86MemAsmOperand;
340 let OperandType = "OPERAND_MEMORY" in {
341 def opaque32mem : X86MemOperand<"printopaquemem">;
342 def opaque48mem : X86MemOperand<"printopaquemem">;
343 def opaque80mem : X86MemOperand<"printopaquemem">;
344 def opaque512mem : X86MemOperand<"printopaquemem">;
346 def i8mem : X86MemOperand<"printi8mem"> {
347 let ParserMatchClass = X86Mem8AsmOperand; }
348 def i16mem : X86MemOperand<"printi16mem"> {
349 let ParserMatchClass = X86Mem16AsmOperand; }
350 def i32mem : X86MemOperand<"printi32mem"> {
351 let ParserMatchClass = X86Mem32AsmOperand; }
352 def i64mem : X86MemOperand<"printi64mem"> {
353 let ParserMatchClass = X86Mem64AsmOperand; }
354 def i128mem : X86MemOperand<"printi128mem"> {
355 let ParserMatchClass = X86Mem128AsmOperand; }
356 def i256mem : X86MemOperand<"printi256mem"> {
357 let ParserMatchClass = X86Mem256AsmOperand; }
358 def i512mem : X86MemOperand<"printi512mem"> {
359 let ParserMatchClass = X86Mem512AsmOperand; }
360 def f32mem : X86MemOperand<"printf32mem"> {
361 let ParserMatchClass = X86Mem32AsmOperand; }
362 def f64mem : X86MemOperand<"printf64mem"> {
363 let ParserMatchClass = X86Mem64AsmOperand; }
364 def f80mem : X86MemOperand<"printf80mem"> {
365 let ParserMatchClass = X86Mem80AsmOperand; }
366 def f128mem : X86MemOperand<"printf128mem"> {
367 let ParserMatchClass = X86Mem128AsmOperand; }
368 def f256mem : X86MemOperand<"printf256mem">{
369 let ParserMatchClass = X86Mem256AsmOperand; }
370 def f512mem : X86MemOperand<"printf512mem">{
371 let ParserMatchClass = X86Mem512AsmOperand; }
372 def v512mem : Operand<iPTR> {
373 let PrintMethod = "printf512mem";
374 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
375 let ParserMatchClass = X86Mem512AsmOperand; }
377 // Gather mem operands
378 def vx32mem : X86MemOperand<"printi32mem">{
379 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
380 let ParserMatchClass = X86MemVX32Operand; }
381 def vy32mem : X86MemOperand<"printi32mem">{
382 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
383 let ParserMatchClass = X86MemVY32Operand; }
384 def vx64mem : X86MemOperand<"printi64mem">{
385 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
386 let ParserMatchClass = X86MemVX64Operand; }
387 def vy64mem : X86MemOperand<"printi64mem">{
388 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
389 let ParserMatchClass = X86MemVY64Operand; }
390 def vy64xmem : X86MemOperand<"printi64mem">{
391 let MIOperandInfo = (ops ptr_rc, i8imm, VR256X, i32imm, i8imm);
392 let ParserMatchClass = X86MemVY64Operand; }
393 def vz32mem : X86MemOperand<"printi32mem">{
394 let MIOperandInfo = (ops ptr_rc, i16imm, VR512, i32imm, i8imm);
395 let ParserMatchClass = X86MemVZ32Operand; }
396 def vz64mem : X86MemOperand<"printi64mem">{
397 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
398 let ParserMatchClass = X86MemVZ64Operand; }
401 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
402 // plain GR64, so that it doesn't potentially require a REX prefix.
403 def i8mem_NOREX : Operand<i64> {
404 let PrintMethod = "printi8mem";
405 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
406 let ParserMatchClass = X86Mem8AsmOperand;
407 let OperandType = "OPERAND_MEMORY";
410 // GPRs available for tailcall.
411 // It represents GR32_TC, GR64_TC or GR64_TCW64.
412 def ptr_rc_tailcall : PointerLikeRegClass<2>;
414 // Special i32mem for addresses of load folding tail calls. These are not
415 // allowed to use callee-saved registers since they must be scheduled
416 // after callee-saved register are popped.
417 def i32mem_TC : Operand<i32> {
418 let PrintMethod = "printi32mem";
419 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
421 let ParserMatchClass = X86Mem32AsmOperand;
422 let OperandType = "OPERAND_MEMORY";
425 // Special i64mem for addresses of load folding tail calls. These are not
426 // allowed to use callee-saved registers since they must be scheduled
427 // after callee-saved register are popped.
428 def i64mem_TC : Operand<i64> {
429 let PrintMethod = "printi64mem";
430 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
431 ptr_rc_tailcall, i32imm, i8imm);
432 let ParserMatchClass = X86Mem64AsmOperand;
433 let OperandType = "OPERAND_MEMORY";
436 let OperandType = "OPERAND_PCREL",
437 ParserMatchClass = X86AbsMemAsmOperand,
438 PrintMethod = "printPCRelImm" in {
439 def i32imm_pcrel : Operand<i32>;
440 def i16imm_pcrel : Operand<i16>;
442 // Branch targets have OtherVT type and print as pc-relative values.
443 def brtarget : Operand<OtherVT>;
444 def brtarget8 : Operand<OtherVT>;
448 def X86MemOffs8AsmOperand : AsmOperandClass {
449 let Name = "MemOffs8";
450 let RenderMethod = "addMemOffsOperands";
451 let SuperClasses = [X86Mem8AsmOperand];
453 def X86MemOffs16AsmOperand : AsmOperandClass {
454 let Name = "MemOffs16";
455 let RenderMethod = "addMemOffsOperands";
456 let SuperClasses = [X86Mem16AsmOperand];
458 def X86MemOffs32AsmOperand : AsmOperandClass {
459 let Name = "MemOffs32";
460 let RenderMethod = "addMemOffsOperands";
461 let SuperClasses = [X86Mem32AsmOperand];
463 def X86MemOffs64AsmOperand : AsmOperandClass {
464 let Name = "MemOffs64";
465 let RenderMethod = "addMemOffsOperands";
466 let SuperClasses = [X86Mem64AsmOperand];
469 let OperandType = "OPERAND_MEMORY" in {
470 def offset8 : Operand<i64> {
471 let ParserMatchClass = X86MemOffs8AsmOperand;
472 let PrintMethod = "printMemOffs8"; }
473 def offset16 : Operand<i64> {
474 let ParserMatchClass = X86MemOffs16AsmOperand;
475 let PrintMethod = "printMemOffs16"; }
476 def offset32 : Operand<i64> {
477 let ParserMatchClass = X86MemOffs32AsmOperand;
478 let PrintMethod = "printMemOffs32"; }
479 def offset64 : Operand<i64> {
480 let ParserMatchClass = X86MemOffs64AsmOperand;
481 let PrintMethod = "printMemOffs64"; }
485 def SSECC : Operand<i8> {
486 let PrintMethod = "printSSECC";
487 let OperandType = "OPERAND_IMMEDIATE";
490 def AVXCC : Operand<i8> {
491 let PrintMethod = "printAVXCC";
492 let OperandType = "OPERAND_IMMEDIATE";
495 class ImmSExtAsmOperandClass : AsmOperandClass {
496 let SuperClasses = [ImmAsmOperand];
497 let RenderMethod = "addImmOperands";
500 class ImmZExtAsmOperandClass : AsmOperandClass {
501 let SuperClasses = [ImmAsmOperand];
502 let RenderMethod = "addImmOperands";
505 def X86GR32orGR64AsmOperand : AsmOperandClass {
506 let Name = "GR32orGR64";
509 def GR32orGR64 : RegisterOperand<GR32> {
510 let ParserMatchClass = X86GR32orGR64AsmOperand;
513 def AVX512RC : Operand<i32> {
514 let PrintMethod = "printRoundingControl";
515 let OperandType = "OPERAND_IMMEDIATE";
517 // Sign-extended immediate classes. We don't need to define the full lattice
518 // here because there is no instruction with an ambiguity between ImmSExti64i32
521 // The strange ranges come from the fact that the assembler always works with
522 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
523 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
526 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
527 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
528 let Name = "ImmSExti64i32";
531 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
532 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
533 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
534 let Name = "ImmSExti16i8";
535 let SuperClasses = [ImmSExti64i32AsmOperand];
538 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
539 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
540 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
541 let Name = "ImmSExti32i8";
545 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
546 let Name = "ImmZExtu32u8";
551 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
552 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
553 let Name = "ImmSExti64i8";
554 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
555 ImmSExti64i32AsmOperand];
558 // A couple of more descriptive operand definitions.
559 // 16-bits but only 8 bits are significant.
560 def i16i8imm : Operand<i16> {
561 let ParserMatchClass = ImmSExti16i8AsmOperand;
562 let OperandType = "OPERAND_IMMEDIATE";
564 // 32-bits but only 8 bits are significant.
565 def i32i8imm : Operand<i32> {
566 let ParserMatchClass = ImmSExti32i8AsmOperand;
567 let OperandType = "OPERAND_IMMEDIATE";
569 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
570 def u32u8imm : Operand<i32> {
571 let ParserMatchClass = ImmZExtu32u8AsmOperand;
572 let OperandType = "OPERAND_IMMEDIATE";
575 // 64-bits but only 32 bits are significant.
576 def i64i32imm : Operand<i64> {
577 let ParserMatchClass = ImmSExti64i32AsmOperand;
578 let OperandType = "OPERAND_IMMEDIATE";
581 // 64-bits but only 32 bits are significant, and those bits are treated as being
583 def i64i32imm_pcrel : Operand<i64> {
584 let PrintMethod = "printPCRelImm";
585 let ParserMatchClass = X86AbsMemAsmOperand;
586 let OperandType = "OPERAND_PCREL";
589 // 64-bits but only 8 bits are significant.
590 def i64i8imm : Operand<i64> {
591 let ParserMatchClass = ImmSExti64i8AsmOperand;
592 let OperandType = "OPERAND_IMMEDIATE";
595 def lea64_32mem : Operand<i32> {
596 let PrintMethod = "printi32mem";
597 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
598 let ParserMatchClass = X86MemAsmOperand;
601 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
602 def lea64mem : Operand<i64> {
603 let PrintMethod = "printi64mem";
604 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
605 let ParserMatchClass = X86MemAsmOperand;
609 //===----------------------------------------------------------------------===//
610 // X86 Complex Pattern Definitions.
613 // Define X86 specific addressing mode.
614 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
615 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
616 [add, sub, mul, X86mul_imm, shl, or, frameindex],
618 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
619 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
620 [add, sub, mul, X86mul_imm, shl, or,
621 frameindex, X86WrapperRIP],
624 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
625 [tglobaltlsaddr], []>;
627 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
628 [tglobaltlsaddr], []>;
630 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
631 [add, sub, mul, X86mul_imm, shl, or, frameindex,
634 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
635 [tglobaltlsaddr], []>;
637 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
638 [tglobaltlsaddr], []>;
640 //===----------------------------------------------------------------------===//
641 // X86 Instruction Predicate Definitions.
642 def HasCMov : Predicate<"Subtarget->hasCMov()">;
643 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
645 def HasMMX : Predicate<"Subtarget->hasMMX()">;
646 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
647 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
648 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
649 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
650 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
651 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
652 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
653 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
654 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
655 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
656 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
657 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
658 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
659 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
660 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
661 def HasAVX : Predicate<"Subtarget->hasAVX()">;
662 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
663 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
664 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
665 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
666 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
667 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
668 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
669 def HasCDI : Predicate<"Subtarget->hasCDI()">;
670 def HasPFI : Predicate<"Subtarget->hasPFI()">;
671 def HasERI : Predicate<"Subtarget->hasERI()">;
673 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
674 def HasAES : Predicate<"Subtarget->hasAES()">;
675 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
676 def HasFMA : Predicate<"Subtarget->hasFMA()">;
677 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
678 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
679 def HasXOP : Predicate<"Subtarget->hasXOP()">;
680 def HasTBM : Predicate<"Subtarget->hasTBM()">;
681 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
682 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
683 def HasF16C : Predicate<"Subtarget->hasF16C()">;
684 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
685 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
686 def HasBMI : Predicate<"Subtarget->hasBMI()">;
687 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
688 def HasRTM : Predicate<"Subtarget->hasRTM()">;
689 def HasHLE : Predicate<"Subtarget->hasHLE()">;
690 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
691 def HasADX : Predicate<"Subtarget->hasADX()">;
692 def HasSHA : Predicate<"Subtarget->hasSHA()">;
693 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
694 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
695 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
696 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
697 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
698 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
699 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
700 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
701 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
702 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
703 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
704 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
705 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
706 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
707 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
708 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
709 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
710 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
711 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
712 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
713 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
714 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
715 "TM.getCodeModel() != CodeModel::Kernel">;
716 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
717 "TM.getCodeModel() == CodeModel::Kernel">;
718 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
719 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
720 def OptForSize : Predicate<"OptForSize">;
721 def OptForSpeed : Predicate<"!OptForSize">;
722 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
723 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
724 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
726 //===----------------------------------------------------------------------===//
727 // X86 Instruction Format Definitions.
730 include "X86InstrFormats.td"
732 //===----------------------------------------------------------------------===//
733 // Pattern fragments.
736 // X86 specific condition code. These correspond to CondCode in
737 // X86InstrInfo.h. They must be kept in synch.
738 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
739 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
740 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
741 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
742 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
743 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
744 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
745 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
746 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
747 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
748 def X86_COND_NO : PatLeaf<(i8 10)>;
749 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
750 def X86_COND_NS : PatLeaf<(i8 12)>;
751 def X86_COND_O : PatLeaf<(i8 13)>;
752 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
753 def X86_COND_S : PatLeaf<(i8 15)>;
755 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
756 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
757 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
758 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
761 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
764 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
766 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
768 def i64immZExt32SExt8 : ImmLeaf<i64, [{
769 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
772 // Helper fragments for loads.
773 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
774 // known to be 32-bit aligned or better. Ditto for i8 to i16.
775 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
776 LoadSDNode *LD = cast<LoadSDNode>(N);
777 ISD::LoadExtType ExtType = LD->getExtensionType();
778 if (ExtType == ISD::NON_EXTLOAD)
780 if (ExtType == ISD::EXTLOAD)
781 return LD->getAlignment() >= 2 && !LD->isVolatile();
785 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
786 LoadSDNode *LD = cast<LoadSDNode>(N);
787 ISD::LoadExtType ExtType = LD->getExtensionType();
788 if (ExtType == ISD::EXTLOAD)
789 return LD->getAlignment() >= 2 && !LD->isVolatile();
793 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
794 LoadSDNode *LD = cast<LoadSDNode>(N);
795 ISD::LoadExtType ExtType = LD->getExtensionType();
796 if (ExtType == ISD::NON_EXTLOAD)
798 if (ExtType == ISD::EXTLOAD)
799 return LD->getAlignment() >= 4 && !LD->isVolatile();
803 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
804 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
805 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
806 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
807 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
809 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
810 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
811 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
812 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
813 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
814 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
816 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
817 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
818 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
819 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
820 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
821 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
822 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
823 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
824 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
825 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
827 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
828 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
829 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
830 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
831 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
832 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
833 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
834 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
835 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
836 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
839 // An 'and' node with a single use.
840 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
841 return N->hasOneUse();
843 // An 'srl' node with a single use.
844 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
845 return N->hasOneUse();
847 // An 'trunc' node with a single use.
848 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
849 return N->hasOneUse();
852 //===----------------------------------------------------------------------===//
857 let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
858 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
859 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
860 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
861 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
862 "nop{l}\t$zero", [], IIC_NOP>, TB;
866 // Constructing a stack frame.
867 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
868 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
870 let SchedRW = [WriteALU] in {
871 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
872 def LEAVE : I<0xC9, RawFrm,
873 (outs), (ins), "leave", [], IIC_LEAVE>,
874 Requires<[Not64BitMode]>;
876 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
877 def LEAVE64 : I<0xC9, RawFrm,
878 (outs), (ins), "leave", [], IIC_LEAVE>,
879 Requires<[In64BitMode]>;
882 //===----------------------------------------------------------------------===//
883 // Miscellaneous Instructions.
886 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
887 let mayLoad = 1, SchedRW = [WriteLoad] in {
888 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
889 IIC_POP_REG16>, OpSize;
890 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
891 IIC_POP_REG>, OpSize16, Requires<[Not64BitMode]>;
892 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
893 IIC_POP_REG>, OpSize;
894 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
895 IIC_POP_MEM>, OpSize;
896 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
897 IIC_POP_REG>, OpSize16, Requires<[Not64BitMode]>;
898 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
899 IIC_POP_MEM>, Requires<[Not64BitMode]>;
901 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
902 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
903 OpSize16, Requires<[Not64BitMode]>;
904 } // mayLoad, SchedRW
906 let mayStore = 1, SchedRW = [WriteStore] in {
907 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
908 IIC_PUSH_REG>, OpSize;
909 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
910 IIC_PUSH_REG>, OpSize16, Requires<[Not64BitMode]>;
911 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
912 IIC_PUSH_REG>, OpSize;
913 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
914 IIC_PUSH_MEM>, OpSize;
915 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
916 IIC_PUSH_REG>, OpSize16, Requires<[Not64BitMode]>;
917 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
918 IIC_PUSH_MEM>, OpSize16, Requires<[Not64BitMode]>;
920 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
921 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
922 Requires<[Not64BitMode]>;
923 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
924 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
925 Requires<[Not64BitMode]>;
926 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
927 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
928 Requires<[Not64BitMode]>;
930 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
932 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
933 OpSize16, Requires<[Not64BitMode]>;
935 } // mayStore, SchedRW
938 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
939 let mayLoad = 1, SchedRW = [WriteLoad] in {
940 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
941 IIC_POP_REG>, Requires<[In64BitMode]>;
942 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
943 IIC_POP_REG>, Requires<[In64BitMode]>;
944 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
945 IIC_POP_MEM>, Requires<[In64BitMode]>;
946 } // mayLoad, SchedRW
947 let mayStore = 1, SchedRW = [WriteStore] in {
948 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
949 IIC_PUSH_REG>, Requires<[In64BitMode]>;
950 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
951 IIC_PUSH_REG>, Requires<[In64BitMode]>;
952 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
953 IIC_PUSH_MEM>, Requires<[In64BitMode]>;
954 } // mayStore, SchedRW
957 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1,
958 SchedRW = [WriteStore] in {
959 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
960 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
961 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
962 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
963 Requires<[In64BitMode]>;
964 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
965 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
968 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
969 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
970 Requires<[In64BitMode]>, Sched<[WriteLoad]>;
971 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
972 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
973 Requires<[In64BitMode]>, Sched<[WriteStore]>;
975 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
976 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
977 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
978 OpSize16, Requires<[Not64BitMode]>;
979 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
980 OpSize, Requires<[Not64BitMode]>;
982 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
983 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
984 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
985 OpSize16, Requires<[Not64BitMode]>;
986 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
987 OpSize, Requires<[Not64BitMode]>;
990 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
992 def BSWAP32r : I<0xC8, AddRegFrm,
993 (outs GR32:$dst), (ins GR32:$src),
995 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize16, TB;
997 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
999 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1000 } // Constraints = "$src = $dst", SchedRW
1002 // Bit scan instructions.
1003 let Defs = [EFLAGS] in {
1004 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1005 "bsf{w}\t{$src, $dst|$dst, $src}",
1006 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1007 IIC_BIT_SCAN_REG>, TB, OpSize, Sched<[WriteShift]>;
1008 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1009 "bsf{w}\t{$src, $dst|$dst, $src}",
1010 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1011 IIC_BIT_SCAN_MEM>, TB, OpSize, Sched<[WriteShiftLd]>;
1012 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1013 "bsf{l}\t{$src, $dst|$dst, $src}",
1014 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1015 IIC_BIT_SCAN_REG>, TB, OpSize16,
1016 Sched<[WriteShift]>;
1017 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1018 "bsf{l}\t{$src, $dst|$dst, $src}",
1019 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1020 IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
1021 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1022 "bsf{q}\t{$src, $dst|$dst, $src}",
1023 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1024 IIC_BIT_SCAN_REG>, TB, Sched<[WriteShift]>;
1025 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1026 "bsf{q}\t{$src, $dst|$dst, $src}",
1027 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1028 IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;
1030 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1031 "bsr{w}\t{$src, $dst|$dst, $src}",
1032 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1034 TB, OpSize, Sched<[WriteShift]>;
1035 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1036 "bsr{w}\t{$src, $dst|$dst, $src}",
1037 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1038 IIC_BIT_SCAN_MEM>, TB,
1039 OpSize, Sched<[WriteShiftLd]>;
1040 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1041 "bsr{l}\t{$src, $dst|$dst, $src}",
1042 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1043 IIC_BIT_SCAN_REG>, TB, OpSize16,
1044 Sched<[WriteShift]>;
1045 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1046 "bsr{l}\t{$src, $dst|$dst, $src}",
1047 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1048 IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
1049 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1050 "bsr{q}\t{$src, $dst|$dst, $src}",
1051 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BIT_SCAN_REG>, TB,
1052 Sched<[WriteShift]>;
1053 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1054 "bsr{q}\t{$src, $dst|$dst, $src}",
1055 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1056 IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;
1057 } // Defs = [EFLAGS]
1059 let SchedRW = [WriteMicrocoded] in {
1060 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1061 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1062 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>;
1063 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize;
1064 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>, OpSize16;
1065 def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>;
1068 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1069 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1070 def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>;
1071 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1072 def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize;
1073 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1074 def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>, OpSize16;
1075 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1076 def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>;
1078 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
1079 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
1080 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>,
1082 def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
1084 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
1085 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
1086 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>,
1088 def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>;
1091 //===----------------------------------------------------------------------===//
1092 // Move Instructions.
1094 let SchedRW = [WriteMove] in {
1095 let neverHasSideEffects = 1 in {
1096 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1097 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1098 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1099 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1100 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1101 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1102 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1103 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1106 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1107 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1108 "mov{b}\t{$src, $dst|$dst, $src}",
1109 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1110 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1111 "mov{w}\t{$src, $dst|$dst, $src}",
1112 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
1113 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1114 "mov{l}\t{$src, $dst|$dst, $src}",
1115 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize16;
1116 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1117 "movabs{q}\t{$src, $dst|$dst, $src}",
1118 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1119 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1120 "mov{q}\t{$src, $dst|$dst, $src}",
1121 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1125 let SchedRW = [WriteStore] in {
1126 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1127 "mov{b}\t{$src, $dst|$dst, $src}",
1128 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1129 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1130 "mov{w}\t{$src, $dst|$dst, $src}",
1131 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
1132 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1133 "mov{l}\t{$src, $dst|$dst, $src}",
1134 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1135 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1136 "mov{q}\t{$src, $dst|$dst, $src}",
1137 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1140 let hasSideEffects = 0 in {
1142 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1143 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1144 let SchedRW = [WriteALU] in {
1145 let mayLoad = 1 in {
1146 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1147 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1148 Requires<[Not64BitMode]>;
1149 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1150 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize,
1151 Requires<[Not64BitMode]>;
1152 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1153 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1154 OpSize16, Requires<[Not64BitMode]>;
1156 let mayStore = 1 in {
1157 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1158 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
1159 Requires<[Not64BitMode]>;
1160 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1161 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize,
1162 Requires<[Not64BitMode]>;
1163 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1164 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1165 OpSize16, Requires<[Not64BitMode]>;
1169 // These forms all have full 64-bit absolute addresses in their instructions
1170 // and use the movabs mnemonic to indicate this specific form.
1171 let mayLoad = 1 in {
1172 def MOV64o8a : RIi64_NOREX<0xA0, RawFrm, (outs), (ins offset8:$src),
1173 "movabs{b}\t{$src, %al|al, $src}", []>,
1174 Requires<[In64BitMode]>;
1175 def MOV64o16a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset16:$src),
1176 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize,
1177 Requires<[In64BitMode]>;
1178 def MOV64o32a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset32:$src),
1179 "movabs{l}\t{$src, %eax|eax, $src}", []>,
1180 Requires<[In64BitMode]>;
1181 def MOV64o64a : RIi64<0xA1, RawFrm, (outs), (ins offset64:$src),
1182 "movabs{q}\t{$src, %rax|rax, $src}", []>,
1183 Requires<[In64BitMode]>;
1186 let mayStore = 1 in {
1187 def MOV64ao8 : RIi64_NOREX<0xA2, RawFrm, (outs offset8:$dst), (ins),
1188 "movabs{b}\t{%al, $dst|$dst, al}", []>,
1189 Requires<[In64BitMode]>;
1190 def MOV64ao16 : RIi64_NOREX<0xA3, RawFrm, (outs offset16:$dst), (ins),
1191 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize,
1192 Requires<[In64BitMode]>;
1193 def MOV64ao32 : RIi64_NOREX<0xA3, RawFrm, (outs offset32:$dst), (ins),
1194 "movabs{l}\t{%eax, $dst|$dst, eax}", []>,
1195 Requires<[In64BitMode]>;
1196 def MOV64ao64 : RIi64<0xA3, RawFrm, (outs offset64:$dst), (ins),
1197 "movabs{q}\t{%rax, $dst|$dst, rax}", []>,
1198 Requires<[In64BitMode]>;
1200 } // hasSideEffects = 0
1202 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1203 SchedRW = [WriteMove] in {
1204 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1205 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1206 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1207 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1208 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1209 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1210 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1211 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1214 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1215 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1216 "mov{b}\t{$src, $dst|$dst, $src}",
1217 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1218 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1219 "mov{w}\t{$src, $dst|$dst, $src}",
1220 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
1221 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1222 "mov{l}\t{$src, $dst|$dst, $src}",
1223 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize16;
1224 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1225 "mov{q}\t{$src, $dst|$dst, $src}",
1226 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1229 let SchedRW = [WriteStore] in {
1230 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1231 "mov{b}\t{$src, $dst|$dst, $src}",
1232 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1233 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1234 "mov{w}\t{$src, $dst|$dst, $src}",
1235 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
1236 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1237 "mov{l}\t{$src, $dst|$dst, $src}",
1238 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1239 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1240 "mov{q}\t{$src, $dst|$dst, $src}",
1241 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1244 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1245 // that they can be used for copying and storing h registers, which can't be
1246 // encoded when a REX prefix is present.
1247 let isCodeGenOnly = 1 in {
1248 let neverHasSideEffects = 1 in
1249 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1250 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1251 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1253 let mayStore = 1, neverHasSideEffects = 1 in
1254 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1255 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1256 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1257 IIC_MOV_MEM>, Sched<[WriteStore]>;
1258 let mayLoad = 1, neverHasSideEffects = 1,
1259 canFoldAsLoad = 1, isReMaterializable = 1 in
1260 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1261 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1262 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1263 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1267 // Condition code ops, incl. set if equal/not equal/...
1268 let SchedRW = [WriteALU] in {
1269 let Defs = [EFLAGS], Uses = [AH] in
1270 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1271 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1272 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1273 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1274 IIC_AHF>; // AH = flags
1277 //===----------------------------------------------------------------------===//
1278 // Bit tests instructions: BT, BTS, BTR, BTC.
1280 let Defs = [EFLAGS] in {
1281 let SchedRW = [WriteALU] in {
1282 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1283 "bt{w}\t{$src2, $src1|$src1, $src2}",
1284 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1286 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1287 "bt{l}\t{$src2, $src1|$src1, $src2}",
1288 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1290 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1291 "bt{q}\t{$src2, $src1|$src1, $src2}",
1292 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1295 // Unlike with the register+register form, the memory+register form of the
1296 // bt instruction does not ignore the high bits of the index. From ISel's
1297 // perspective, this is pretty bizarre. Make these instructions disassembly
1300 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1301 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1302 "bt{w}\t{$src2, $src1|$src1, $src2}",
1303 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1304 // (implicit EFLAGS)]
1306 >, OpSize, TB, Requires<[FastBTMem]>;
1307 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1308 "bt{l}\t{$src2, $src1|$src1, $src2}",
1309 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1310 // (implicit EFLAGS)]
1312 >, OpSize16, TB, Requires<[FastBTMem]>;
1313 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1314 "bt{q}\t{$src2, $src1|$src1, $src2}",
1315 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1316 // (implicit EFLAGS)]
1321 let SchedRW = [WriteALU] in {
1322 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1323 "bt{w}\t{$src2, $src1|$src1, $src2}",
1324 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1325 IIC_BT_RI>, OpSize, TB;
1326 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1327 "bt{l}\t{$src2, $src1|$src1, $src2}",
1328 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1329 IIC_BT_RI>, OpSize16, TB;
1330 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1331 "bt{q}\t{$src2, $src1|$src1, $src2}",
1332 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1336 // Note that these instructions don't need FastBTMem because that
1337 // only applies when the other operand is in a register. When it's
1338 // an immediate, bt is still fast.
1339 let SchedRW = [WriteALU] in {
1340 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1341 "bt{w}\t{$src2, $src1|$src1, $src2}",
1342 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1343 ], IIC_BT_MI>, OpSize, TB;
1344 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1345 "bt{l}\t{$src2, $src1|$src1, $src2}",
1346 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1347 ], IIC_BT_MI>, OpSize16, TB;
1348 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1349 "bt{q}\t{$src2, $src1|$src1, $src2}",
1350 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1351 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1354 let hasSideEffects = 0 in {
1355 let SchedRW = [WriteALU] in {
1356 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1357 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1359 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1360 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1362 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1363 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1366 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1367 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1368 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1370 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1371 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1373 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1374 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1377 let SchedRW = [WriteALU] in {
1378 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1379 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1381 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1382 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1384 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1385 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1388 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1389 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1390 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1392 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1393 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1395 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1396 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1399 let SchedRW = [WriteALU] in {
1400 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1401 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1403 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1404 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1406 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1407 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1410 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1411 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1412 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1414 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1415 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1417 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1418 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1421 let SchedRW = [WriteALU] in {
1422 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1423 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1425 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1426 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1428 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1429 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1432 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1433 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1434 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1436 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1437 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1439 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1440 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1443 let SchedRW = [WriteALU] in {
1444 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1445 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1447 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1448 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1450 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1451 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1454 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1455 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1456 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1458 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1459 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1461 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1462 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1465 let SchedRW = [WriteALU] in {
1466 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1467 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1469 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1470 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1472 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1473 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1476 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1477 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1478 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1480 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1481 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1483 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1484 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1486 } // hasSideEffects = 0
1487 } // Defs = [EFLAGS]
1490 //===----------------------------------------------------------------------===//
1494 // Atomic swap. These are just normal xchg instructions. But since a memory
1495 // operand is referenced, the atomicity is ensured.
1496 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1497 InstrItinClass itin> {
1498 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1499 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1500 (ins GR8:$val, i8mem:$ptr),
1501 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1504 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1506 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1507 (ins GR16:$val, i16mem:$ptr),
1508 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1511 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1513 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1514 (ins GR32:$val, i32mem:$ptr),
1515 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1518 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1520 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1521 (ins GR64:$val, i64mem:$ptr),
1522 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1525 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1530 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1532 // Swap between registers.
1533 let SchedRW = [WriteALU] in {
1534 let Constraints = "$val = $dst" in {
1535 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1536 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1537 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1538 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
1539 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1540 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1542 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1543 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1546 // Swap between EAX and other registers.
1547 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1548 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize;
1549 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1550 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1551 OpSize16, Requires<[Not64BitMode]>;
1552 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1553 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1554 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1555 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1556 Requires<[In64BitMode]>;
1557 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1558 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1561 let SchedRW = [WriteALU] in {
1562 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1563 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1564 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1565 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1567 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1568 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1570 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1571 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1574 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1575 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1576 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1577 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1578 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1580 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1581 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1583 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1584 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1588 let SchedRW = [WriteALU] in {
1589 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1590 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1591 IIC_CMPXCHG_REG8>, TB;
1592 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1593 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1594 IIC_CMPXCHG_REG>, TB, OpSize;
1595 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1596 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1597 IIC_CMPXCHG_REG>, TB, OpSize16;
1598 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1599 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1600 IIC_CMPXCHG_REG>, TB;
1603 let SchedRW = [WriteALULd, WriteRMW] in {
1604 let mayLoad = 1, mayStore = 1 in {
1605 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1606 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1607 IIC_CMPXCHG_MEM8>, TB;
1608 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1609 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1610 IIC_CMPXCHG_MEM>, TB, OpSize;
1611 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1612 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1613 IIC_CMPXCHG_MEM>, TB, OpSize16;
1614 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1615 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1616 IIC_CMPXCHG_MEM>, TB;
1619 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1620 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1621 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1623 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1624 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1625 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1626 TB, Requires<[HasCmpxchg16b]>;
1630 // Lock instruction prefix
1631 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1633 // Rex64 instruction prefix
1634 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1635 Requires<[In64BitMode]>;
1637 // Data16 instruction prefix
1638 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1640 // Repeat string operation instruction prefixes
1641 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1642 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1643 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1644 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1645 // Repeat while not equal (used with CMPS and SCAS)
1646 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1650 // String manipulation instructions
1651 let SchedRW = [WriteMicrocoded] in {
1652 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
1653 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
1654 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>, OpSize16;
1655 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
1658 let SchedRW = [WriteSystem] in {
1659 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>;
1660 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize;
1661 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>, OpSize16;
1664 // Flag instructions
1665 let SchedRW = [WriteALU] in {
1666 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1667 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1668 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1669 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1670 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1671 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1672 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1674 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1677 // Table lookup instructions
1678 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1681 let SchedRW = [WriteMicrocoded] in {
1682 // ASCII Adjust After Addition
1683 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1684 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1685 Requires<[Not64BitMode]>;
1687 // ASCII Adjust AX Before Division
1688 // sets AL, AH and EFLAGS and uses AL and AH
1689 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1690 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1692 // ASCII Adjust AX After Multiply
1693 // sets AL, AH and EFLAGS and uses AL
1694 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1695 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1697 // ASCII Adjust AL After Subtraction - sets
1698 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1699 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1700 Requires<[Not64BitMode]>;
1702 // Decimal Adjust AL after Addition
1703 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1704 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1705 Requires<[Not64BitMode]>;
1707 // Decimal Adjust AL after Subtraction
1708 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1709 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1710 Requires<[Not64BitMode]>;
1713 let SchedRW = [WriteSystem] in {
1714 // Check Array Index Against Bounds
1715 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1716 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
1717 Requires<[Not64BitMode]>;
1718 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1719 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1720 Requires<[Not64BitMode]>;
1722 // Adjust RPL Field of Segment Selector
1723 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1724 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1725 Requires<[Not64BitMode]>;
1726 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1727 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1728 Requires<[Not64BitMode]>;
1731 //===----------------------------------------------------------------------===//
1732 // MOVBE Instructions
1734 let Predicates = [HasMOVBE] in {
1735 let SchedRW = [WriteALULd] in {
1736 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1737 "movbe{w}\t{$src, $dst|$dst, $src}",
1738 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1740 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1741 "movbe{l}\t{$src, $dst|$dst, $src}",
1742 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1744 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1745 "movbe{q}\t{$src, $dst|$dst, $src}",
1746 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1749 let SchedRW = [WriteStore] in {
1750 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1751 "movbe{w}\t{$src, $dst|$dst, $src}",
1752 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1754 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1755 "movbe{l}\t{$src, $dst|$dst, $src}",
1756 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1758 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1759 "movbe{q}\t{$src, $dst|$dst, $src}",
1760 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1765 //===----------------------------------------------------------------------===//
1766 // RDRAND Instruction
1768 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1769 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1771 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
1772 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1774 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1775 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1777 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1780 //===----------------------------------------------------------------------===//
1781 // RDSEED Instruction
1783 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1784 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1786 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize, TB;
1787 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1789 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
1790 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
1792 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
1795 //===----------------------------------------------------------------------===//
1796 // LZCNT Instruction
1798 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1799 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1800 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1801 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1803 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1804 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1805 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1806 (implicit EFLAGS)]>, XS, OpSize;
1808 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1809 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1810 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
1812 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1813 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1814 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1815 (implicit EFLAGS)]>, XS, OpSize16;
1817 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1818 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1819 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1821 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1822 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1823 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1824 (implicit EFLAGS)]>, XS;
1827 //===----------------------------------------------------------------------===//
1830 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1831 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1832 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1833 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1835 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1836 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1837 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1838 (implicit EFLAGS)]>, XS, OpSize;
1840 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1841 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1842 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
1844 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1845 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1846 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1847 (implicit EFLAGS)]>, XS, OpSize16;
1849 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1850 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1851 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1853 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1854 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1855 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1856 (implicit EFLAGS)]>, XS;
1859 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1860 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1862 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1863 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1864 [(set RC:$dst, (OpNode RC:$src)), (implicit EFLAGS)]>, T8, VEX_4V;
1865 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1866 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1867 [(set RC:$dst, (OpNode (ld_frag addr:$src))), (implicit EFLAGS)]>,
1871 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1872 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1874 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1875 X86blsr, loadi64>, VEX_W;
1876 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1877 X86blsmsk, loadi32>;
1878 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1879 X86blsmsk, loadi64>, VEX_W;
1880 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
1882 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
1883 X86blsi, loadi64>, VEX_W;
1886 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
1887 X86MemOperand x86memop, Intrinsic Int,
1889 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1890 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1891 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
1893 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
1894 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1895 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
1896 (implicit EFLAGS)]>, T8, VEX_4VOp3;
1899 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1900 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
1901 int_x86_bmi_bextr_32, loadi32>;
1902 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
1903 int_x86_bmi_bextr_64, loadi64>, VEX_W;
1906 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
1907 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
1908 int_x86_bmi_bzhi_32, loadi32>;
1909 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
1910 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
1913 def : Pat<(X86bzhi GR32:$src1, GR8:$src2),
1914 (BZHI32rr GR32:$src1,
1915 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1916 def : Pat<(X86bzhi (loadi32 addr:$src1), GR8:$src2),
1917 (BZHI32rm addr:$src1,
1918 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1919 def : Pat<(X86bzhi GR64:$src1, GR8:$src2),
1920 (BZHI64rr GR64:$src1,
1921 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1922 def : Pat<(X86bzhi (loadi64 addr:$src1), GR8:$src2),
1923 (BZHI64rm addr:$src1,
1924 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1926 let Predicates = [HasBMI] in {
1927 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
1928 (BEXTR32rr GR32:$src1, GR32:$src2)>;
1929 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
1930 (BEXTR32rm addr:$src1, GR32:$src2)>;
1931 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
1932 (BEXTR64rr GR64:$src1, GR64:$src2)>;
1933 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
1934 (BEXTR64rm addr:$src1, GR64:$src2)>;
1937 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
1938 X86MemOperand x86memop, Intrinsic Int,
1940 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1941 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1942 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
1944 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1945 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1946 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
1949 let Predicates = [HasBMI2] in {
1950 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
1951 int_x86_bmi_pdep_32, loadi32>, T8XD;
1952 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
1953 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
1954 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
1955 int_x86_bmi_pext_32, loadi32>, T8XS;
1956 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
1957 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
1960 //===----------------------------------------------------------------------===//
1963 let Predicates = [HasTBM], Defs = [EFLAGS] in {
1965 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
1966 X86MemOperand x86memop, PatFrag ld_frag,
1967 Intrinsic Int, Operand immtype,
1968 SDPatternOperator immoperator> {
1969 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
1970 !strconcat(OpcodeStr,
1971 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
1972 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
1974 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
1975 (ins x86memop:$src1, immtype:$cntl),
1976 !strconcat(OpcodeStr,
1977 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
1978 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
1982 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
1983 int_x86_tbm_bextri_u32, i32imm, imm>;
1984 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
1985 int_x86_tbm_bextri_u64, i64i32imm,
1986 i64immSExt32>, VEX_W;
1988 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
1989 RegisterClass RC, string OpcodeStr,
1990 X86MemOperand x86memop, PatFrag ld_frag> {
1991 let hasSideEffects = 0 in {
1992 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
1993 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
1994 []>, XOP, XOP9, VEX_4V;
1996 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
1997 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
1998 []>, XOP, XOP9, VEX_4V;
2002 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2003 Format FormReg, Format FormMem> {
2004 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2006 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2010 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2011 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2012 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2013 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2014 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2015 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2016 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2017 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2018 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2021 //===----------------------------------------------------------------------===//
2022 // Pattern fragments to auto generate TBM instructions.
2023 //===----------------------------------------------------------------------===//
2025 let Predicates = [HasTBM] in {
2026 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2027 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2028 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2029 (BEXTRI32mi addr:$src1, imm:$src2)>;
2030 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2031 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2032 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2033 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2035 // FIXME: patterns for the load versions are not implemented
2036 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2037 (BLCFILL32rr GR32:$src)>;
2038 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2039 (BLCFILL64rr GR64:$src)>;
2041 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2042 (BLCI32rr GR32:$src)>;
2043 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2044 (BLCI64rr GR64:$src)>;
2046 // Extra patterns because opt can optimize the above patterns to this.
2047 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2048 (BLCI32rr GR32:$src)>;
2049 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2050 (BLCI64rr GR64:$src)>;
2052 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2053 (BLCIC32rr GR32:$src)>;
2054 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2055 (BLCIC64rr GR64:$src)>;
2057 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2058 (BLCMSK32rr GR32:$src)>;
2059 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2060 (BLCMSK64rr GR64:$src)>;
2062 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2063 (BLCS32rr GR32:$src)>;
2064 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2065 (BLCS64rr GR64:$src)>;
2067 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2068 (BLSFILL32rr GR32:$src)>;
2069 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2070 (BLSFILL64rr GR64:$src)>;
2072 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2073 (BLSIC32rr GR32:$src)>;
2074 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2075 (BLSIC64rr GR64:$src)>;
2077 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2078 (T1MSKC32rr GR32:$src)>;
2079 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2080 (T1MSKC64rr GR64:$src)>;
2082 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2083 (TZMSK32rr GR32:$src)>;
2084 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2085 (TZMSK64rr GR64:$src)>;
2088 //===----------------------------------------------------------------------===//
2090 //===----------------------------------------------------------------------===//
2092 include "X86InstrArithmetic.td"
2093 include "X86InstrCMovSetCC.td"
2094 include "X86InstrExtension.td"
2095 include "X86InstrControl.td"
2096 include "X86InstrShiftRotate.td"
2098 // X87 Floating Point Stack.
2099 include "X86InstrFPStack.td"
2101 // SIMD support (SSE, MMX and AVX)
2102 include "X86InstrFragmentsSIMD.td"
2104 // FMA - Fused Multiply-Add support (requires FMA)
2105 include "X86InstrFMA.td"
2108 include "X86InstrXOP.td"
2110 // SSE, MMX and 3DNow! vector support.
2111 include "X86InstrSSE.td"
2112 include "X86InstrAVX512.td"
2113 include "X86InstrMMX.td"
2114 include "X86Instr3DNow.td"
2116 include "X86InstrVMX.td"
2117 include "X86InstrSVM.td"
2119 include "X86InstrTSX.td"
2121 // System instructions.
2122 include "X86InstrSystem.td"
2124 // Compiler Pseudo Instructions and Pat Patterns
2125 include "X86InstrCompiler.td"
2127 //===----------------------------------------------------------------------===//
2128 // Assembler Mnemonic Aliases
2129 //===----------------------------------------------------------------------===//
2131 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2132 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2133 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2135 def : MnemonicAlias<"cbw", "cbtw", "att">;
2136 def : MnemonicAlias<"cwde", "cwtl", "att">;
2137 def : MnemonicAlias<"cwd", "cwtd", "att">;
2138 def : MnemonicAlias<"cdq", "cltd", "att">;
2139 def : MnemonicAlias<"cdqe", "cltq", "att">;
2140 def : MnemonicAlias<"cqo", "cqto", "att">;
2142 // lret maps to lretl, it is not ambiguous with lretq.
2143 def : MnemonicAlias<"lret", "lretl", "att">;
2145 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2146 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2148 def : MnemonicAlias<"loopz", "loope", "att">;
2149 def : MnemonicAlias<"loopnz", "loopne", "att">;
2151 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2152 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2153 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2154 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2155 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2156 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2157 def : MnemonicAlias<"popfd", "popfl", "att">;
2159 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2160 // all modes. However: "push (addr)" and "push $42" should default to
2161 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2162 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2163 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2164 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2165 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2166 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2167 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2168 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2170 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2171 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2172 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2173 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2174 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2175 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2177 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2178 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2179 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2180 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2182 def : MnemonicAlias<"repe", "rep", "att">;
2183 def : MnemonicAlias<"repz", "rep", "att">;
2184 def : MnemonicAlias<"repnz", "repne", "att">;
2186 def : MnemonicAlias<"retl", "ret", "att">, Requires<[Not64BitMode]>;
2187 def : MnemonicAlias<"retq", "ret", "att">, Requires<[In64BitMode]>;
2189 def : MnemonicAlias<"salb", "shlb", "att">;
2190 def : MnemonicAlias<"salw", "shlw", "att">;
2191 def : MnemonicAlias<"sall", "shll", "att">;
2192 def : MnemonicAlias<"salq", "shlq", "att">;
2194 def : MnemonicAlias<"smovb", "movsb", "att">;
2195 def : MnemonicAlias<"smovw", "movsw", "att">;
2196 def : MnemonicAlias<"smovl", "movsl", "att">;
2197 def : MnemonicAlias<"smovq", "movsq", "att">;
2199 def : MnemonicAlias<"ud2a", "ud2", "att">;
2200 def : MnemonicAlias<"verrw", "verr", "att">;
2202 // System instruction aliases.
2203 def : MnemonicAlias<"iret", "iretl", "att">;
2204 def : MnemonicAlias<"sysret", "sysretl", "att">;
2205 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2207 def : MnemonicAlias<"lgdtl", "lgdt", "att">, Requires<[Not64BitMode]>;
2208 def : MnemonicAlias<"lgdtq", "lgdt", "att">, Requires<[In64BitMode]>;
2209 def : MnemonicAlias<"lidtl", "lidt", "att">, Requires<[Not64BitMode]>;
2210 def : MnemonicAlias<"lidtq", "lidt", "att">, Requires<[In64BitMode]>;
2211 def : MnemonicAlias<"sgdtl", "sgdt", "att">, Requires<[Not64BitMode]>;
2212 def : MnemonicAlias<"sgdtq", "sgdt", "att">, Requires<[In64BitMode]>;
2213 def : MnemonicAlias<"sidtl", "sidt", "att">, Requires<[Not64BitMode]>;
2214 def : MnemonicAlias<"sidtq", "sidt", "att">, Requires<[In64BitMode]>;
2217 // Floating point stack aliases.
2218 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2219 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2220 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2221 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2222 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2223 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2224 def : MnemonicAlias<"fildq", "fildll", "att">;
2225 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2226 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2227 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2228 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2229 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2230 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2231 def : MnemonicAlias<"fwait", "wait", "att">;
2234 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2236 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2237 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2239 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2240 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2241 /// example "setz" -> "sete".
2242 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2244 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2245 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2246 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2247 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2248 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2249 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2250 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2251 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2252 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2253 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2255 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2256 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2257 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2258 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2261 // Aliases for set<CC>
2262 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2263 // Aliases for j<CC>
2264 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2265 // Aliases for cmov<CC>{w,l,q}
2266 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2267 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2268 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2269 // No size suffix for intel-style asm.
2270 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2273 //===----------------------------------------------------------------------===//
2274 // Assembler Instruction Aliases
2275 //===----------------------------------------------------------------------===//
2277 // aad/aam default to base 10 if no operand is specified.
2278 def : InstAlias<"aad", (AAD8i8 10)>;
2279 def : InstAlias<"aam", (AAM8i8 10)>;
2281 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2282 // Likewise for btc/btr/bts.
2283 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2284 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2285 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2286 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2287 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2288 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2289 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2290 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2293 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2294 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2295 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2296 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2298 // div and idiv aliases for explicit A register.
2299 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2300 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2301 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2302 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2303 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2304 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2305 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2306 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2307 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2308 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2309 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2310 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2311 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2312 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2313 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2314 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2318 // Various unary fpstack operations default to operating on on ST1.
2319 // For example, "fxch" -> "fxch %st(1)"
2320 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2321 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2322 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2323 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2324 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2325 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2326 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2327 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2328 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2329 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2330 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2331 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2332 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2333 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2334 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2336 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2337 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2338 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2340 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2341 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2342 (Inst RST:$op), EmitAlias>;
2343 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2344 (Inst ST0), EmitAlias>;
2347 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2348 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2349 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2350 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2351 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2352 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2353 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2354 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2355 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2356 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2357 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2358 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2359 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2360 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2361 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2362 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2365 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2366 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2367 // solely because gas supports it.
2368 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2369 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2370 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2371 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2372 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2373 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2375 // We accept "fnstsw %eax" even though it only writes %ax.
2376 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2377 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2378 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2380 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2381 // this is compatible with what GAS does.
2382 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2383 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2384 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>, Requires<[Not16BitMode]>;
2385 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>, Requires<[Not16BitMode]>;
2386 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2387 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2388 def : InstAlias<"lcall *$dst", (FARCALL16m opaque32mem:$dst)>, Requires<[In16BitMode]>;
2389 def : InstAlias<"ljmp *$dst", (FARJMP16m opaque32mem:$dst)>, Requires<[In16BitMode]>;
2391 def : InstAlias<"call *$dst", (CALL64m i16mem:$dst)>, Requires<[In64BitMode]>;
2392 def : InstAlias<"jmp *$dst", (JMP64m i16mem:$dst)>, Requires<[In64BitMode]>;
2393 def : InstAlias<"call *$dst", (CALL32m i16mem:$dst)>, Requires<[In32BitMode]>;
2394 def : InstAlias<"jmp *$dst", (JMP32m i16mem:$dst)>, Requires<[In32BitMode]>;
2395 def : InstAlias<"call *$dst", (CALL16m i16mem:$dst)>, Requires<[In16BitMode]>;
2396 def : InstAlias<"jmp *$dst", (JMP16m i16mem:$dst)>, Requires<[In16BitMode]>;
2399 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2400 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
2401 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
2402 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
2403 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
2404 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
2405 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
2407 // inb %dx -> inb %al, %dx
2408 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2409 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2410 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2411 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2412 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2413 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2416 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2417 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2418 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2419 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2420 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2421 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2422 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2423 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2424 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2426 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2427 // the move. All segment/mem forms are equivalent, this has the shortest
2429 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
2430 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
2432 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2433 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
2435 // Match 'movq GR64, MMX' as an alias for movd.
2436 def : InstAlias<"movq $src, $dst",
2437 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2438 def : InstAlias<"movq $src, $dst",
2439 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2441 // movsd with no operands (as opposed to the SSE scalar move of a double) is an
2442 // alias for movsl. (as in rep; movsd)
2443 def : InstAlias<"movsd", (MOVSD), 0>;
2446 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2447 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2448 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2449 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2450 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2451 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2452 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2455 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2456 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2457 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2458 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2459 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2460 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2461 // Note: No GR32->GR64 movzx form.
2463 // outb %dx -> outb %al, %dx
2464 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2465 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2466 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2467 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2468 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2469 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2471 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2472 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2473 // errors, since its encoding is the most compact.
2474 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
2476 // shld/shrd op,op -> shld op, op, CL
2477 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2478 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2479 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2480 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2481 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2482 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2484 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2485 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2486 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2487 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2488 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2489 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2491 /* FIXME: This is disabled because the asm matcher is currently incapable of
2492 * matching a fixed immediate like $1.
2493 // "shl X, $1" is an alias for "shl X".
2494 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2495 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2496 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2497 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2498 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2499 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2500 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2501 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2502 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2503 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2504 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2505 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2506 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2507 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2508 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2509 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2510 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2513 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2514 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2515 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2516 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2519 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2520 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", (TEST8rm GR8 :$val, i8mem :$mem)>;
2521 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", (TEST16rm GR16:$val, i16mem:$mem)>;
2522 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", (TEST32rm GR32:$val, i32mem:$mem)>;
2523 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", (TEST64rm GR64:$val, i64mem:$mem)>;
2525 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2526 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", (XCHG8rm GR8 :$val, i8mem :$mem)>;
2527 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", (XCHG16rm GR16:$val, i16mem:$mem)>;
2528 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", (XCHG32rm GR32:$val, i32mem:$mem)>;
2529 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", (XCHG64rm GR64:$val, i64mem:$mem)>;
2531 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2532 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src)>;
2533 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src)>, Requires<[Not64BitMode]>;
2534 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2535 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src)>;