3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
44 def SDTX86SetCC_C : SDTypeProfile<1, 2,
46 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
48 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
50 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
52 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
53 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
54 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
56 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
57 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
60 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
62 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
66 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
68 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
70 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
72 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
74 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
76 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
78 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
80 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
81 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
82 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
83 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
85 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
140 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
141 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
142 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
143 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
146 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
147 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
149 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
150 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
152 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
153 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
154 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
155 SDT_X86SegmentBaseAddress, []>;
157 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
160 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
161 [SDNPHasChain, SDNPOptInFlag]>;
163 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
165 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
166 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
168 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
170 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
171 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
172 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
174 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
176 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
179 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
181 //===----------------------------------------------------------------------===//
182 // X86 Operand Definitions.
185 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
186 // the index operand of an address, to conform to x86 encoding restrictions.
187 def ptr_rc_nosp : PointerLikeRegClass<1>;
189 // *mem - Operand definitions for the funky X86 addressing mode operands.
191 def X86MemAsmOperand : AsmOperandClass {
195 def X86AbsMemAsmOperand : AsmOperandClass {
197 let SuperClass = X86MemAsmOperand;
199 def X86NoSegMemAsmOperand : AsmOperandClass {
200 let Name = "NoSegMem";
201 let SuperClass = X86MemAsmOperand;
203 class X86MemOperand<string printMethod> : Operand<iPTR> {
204 let PrintMethod = printMethod;
205 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
206 let ParserMatchClass = X86MemAsmOperand;
209 def opaque32mem : X86MemOperand<"printopaquemem">;
210 def opaque48mem : X86MemOperand<"printopaquemem">;
211 def opaque80mem : X86MemOperand<"printopaquemem">;
212 def opaque512mem : X86MemOperand<"printopaquemem">;
214 def i8mem : X86MemOperand<"printi8mem">;
215 def i16mem : X86MemOperand<"printi16mem">;
216 def i32mem : X86MemOperand<"printi32mem">;
217 def i64mem : X86MemOperand<"printi64mem">;
218 def i128mem : X86MemOperand<"printi128mem">;
219 //def i256mem : X86MemOperand<"printi256mem">;
220 def f32mem : X86MemOperand<"printf32mem">;
221 def f64mem : X86MemOperand<"printf64mem">;
222 def f80mem : X86MemOperand<"printf80mem">;
223 def f128mem : X86MemOperand<"printf128mem">;
224 //def f256mem : X86MemOperand<"printf256mem">;
226 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
227 // plain GR64, so that it doesn't potentially require a REX prefix.
228 def i8mem_NOREX : Operand<i64> {
229 let PrintMethod = "printi8mem";
230 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
231 let ParserMatchClass = X86MemAsmOperand;
234 def lea32mem : Operand<i32> {
235 let PrintMethod = "printlea32mem";
236 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
237 let ParserMatchClass = X86NoSegMemAsmOperand;
240 let ParserMatchClass = X86AbsMemAsmOperand,
241 PrintMethod = "print_pcrel_imm" in {
242 def i32imm_pcrel : Operand<i32>;
244 def offset8 : Operand<i64>;
245 def offset16 : Operand<i64>;
246 def offset32 : Operand<i64>;
247 def offset64 : Operand<i64>;
249 // Branch targets have OtherVT type and print as pc-relative values.
250 def brtarget : Operand<OtherVT>;
251 def brtarget8 : Operand<OtherVT>;
255 def SSECC : Operand<i8> {
256 let PrintMethod = "printSSECC";
259 def ImmSExt8AsmOperand : AsmOperandClass {
260 let Name = "ImmSExt8";
261 let SuperClass = ImmAsmOperand;
264 // A couple of more descriptive operand definitions.
265 // 16-bits but only 8 bits are significant.
266 def i16i8imm : Operand<i16> {
267 let ParserMatchClass = ImmSExt8AsmOperand;
269 // 32-bits but only 8 bits are significant.
270 def i32i8imm : Operand<i32> {
271 let ParserMatchClass = ImmSExt8AsmOperand;
274 //===----------------------------------------------------------------------===//
275 // X86 Complex Pattern Definitions.
278 // Define X86 specific addressing mode.
279 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
280 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
281 [add, sub, mul, X86mul_imm, shl, or, frameindex],
283 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
284 [tglobaltlsaddr], []>;
286 //===----------------------------------------------------------------------===//
287 // X86 Instruction Predicate Definitions.
288 def HasMMX : Predicate<"Subtarget->hasMMX()">;
289 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
290 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
291 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
292 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
293 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
294 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
295 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
296 def HasAVX : Predicate<"Subtarget->hasAVX()">;
297 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
298 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
299 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
300 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
301 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
302 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
303 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
304 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
305 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
306 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
307 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
308 "TM.getCodeModel() != CodeModel::Kernel">;
309 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
310 "TM.getCodeModel() == CodeModel::Kernel">;
311 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
312 def OptForSize : Predicate<"OptForSize">;
313 def OptForSpeed : Predicate<"!OptForSize">;
314 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
315 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
317 //===----------------------------------------------------------------------===//
318 // X86 Instruction Format Definitions.
321 include "X86InstrFormats.td"
323 //===----------------------------------------------------------------------===//
324 // Pattern fragments...
327 // X86 specific condition code. These correspond to CondCode in
328 // X86InstrInfo.h. They must be kept in synch.
329 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
330 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
331 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
332 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
333 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
334 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
335 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
336 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
337 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
338 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
339 def X86_COND_NO : PatLeaf<(i8 10)>;
340 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
341 def X86_COND_NS : PatLeaf<(i8 12)>;
342 def X86_COND_O : PatLeaf<(i8 13)>;
343 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
344 def X86_COND_S : PatLeaf<(i8 15)>;
346 def i16immSExt8 : PatLeaf<(i16 imm), [{
347 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
348 // sign extended field.
349 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
352 def i32immSExt8 : PatLeaf<(i32 imm), [{
353 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
354 // sign extended field.
355 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
358 // Helper fragments for loads.
359 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
360 // known to be 32-bit aligned or better. Ditto for i8 to i16.
361 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
362 LoadSDNode *LD = cast<LoadSDNode>(N);
363 if (const Value *Src = LD->getSrcValue())
364 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
365 if (PT->getAddressSpace() > 255)
367 ISD::LoadExtType ExtType = LD->getExtensionType();
368 if (ExtType == ISD::NON_EXTLOAD)
370 if (ExtType == ISD::EXTLOAD)
371 return LD->getAlignment() >= 2 && !LD->isVolatile();
375 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),
377 LoadSDNode *LD = cast<LoadSDNode>(N);
378 if (const Value *Src = LD->getSrcValue())
379 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
380 if (PT->getAddressSpace() > 255)
382 ISD::LoadExtType ExtType = LD->getExtensionType();
383 if (ExtType == ISD::EXTLOAD)
384 return LD->getAlignment() >= 2 && !LD->isVolatile();
388 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
389 LoadSDNode *LD = cast<LoadSDNode>(N);
390 if (const Value *Src = LD->getSrcValue())
391 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
392 if (PT->getAddressSpace() > 255)
394 ISD::LoadExtType ExtType = LD->getExtensionType();
395 if (ExtType == ISD::NON_EXTLOAD)
397 if (ExtType == ISD::EXTLOAD)
398 return LD->getAlignment() >= 4 && !LD->isVolatile();
402 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
403 LoadSDNode *LD = cast<LoadSDNode>(N);
404 if (const Value *Src = LD->getSrcValue())
405 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
406 if (PT->getAddressSpace() > 255)
408 if (LD->isVolatile())
410 ISD::LoadExtType ExtType = LD->getExtensionType();
411 if (ExtType == ISD::NON_EXTLOAD)
413 if (ExtType == ISD::EXTLOAD)
414 return LD->getAlignment() >= 4;
418 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
419 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
420 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
421 return PT->getAddressSpace() == 256;
425 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
426 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
427 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
428 return PT->getAddressSpace() == 257;
432 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
433 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
434 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
435 if (PT->getAddressSpace() > 255)
439 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
440 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
441 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
442 if (PT->getAddressSpace() > 255)
447 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
448 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
449 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
450 if (PT->getAddressSpace() > 255)
454 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
455 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
456 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
457 if (PT->getAddressSpace() > 255)
461 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
462 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
463 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
464 if (PT->getAddressSpace() > 255)
469 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
470 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
471 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
473 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
474 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
475 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
476 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
477 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
478 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
480 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
481 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
482 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
483 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
484 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
485 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
488 // An 'and' node with a single use.
489 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
490 return N->hasOneUse();
492 // An 'srl' node with a single use.
493 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
494 return N->hasOneUse();
496 // An 'trunc' node with a single use.
497 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
498 return N->hasOneUse();
501 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
502 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
503 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
504 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
506 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
507 APInt Mask = APInt::getAllOnesValue(BitWidth);
508 APInt KnownZero0, KnownOne0;
509 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
510 APInt KnownZero1, KnownOne1;
511 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
512 return (~KnownZero0 & ~KnownZero1) == 0;
516 // 'shld' and 'shrd' instruction patterns. Note that even though these have
517 // the srl and shl in their patterns, the C++ code must still check for them,
518 // because predicates are tested before children nodes are explored.
520 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
521 (or (srl node:$src1, node:$amt1),
522 (shl node:$src2, node:$amt2)), [{
523 assert(N->getOpcode() == ISD::OR);
524 return N->getOperand(0).getOpcode() == ISD::SRL &&
525 N->getOperand(1).getOpcode() == ISD::SHL &&
526 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
527 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
528 N->getOperand(0).getConstantOperandVal(1) ==
529 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
532 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
533 (or (shl node:$src1, node:$amt1),
534 (srl node:$src2, node:$amt2)), [{
535 assert(N->getOpcode() == ISD::OR);
536 return N->getOperand(0).getOpcode() == ISD::SHL &&
537 N->getOperand(1).getOpcode() == ISD::SRL &&
538 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
539 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
540 N->getOperand(0).getConstantOperandVal(1) ==
541 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
544 //===----------------------------------------------------------------------===//
545 // Instruction list...
548 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
549 // a stack adjustment and the codegen must know that they may modify the stack
550 // pointer before prolog-epilog rewriting occurs.
551 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
552 // sub / add which can clobber EFLAGS.
553 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
554 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
556 [(X86callseq_start timm:$amt)]>,
557 Requires<[In32BitMode]>;
558 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
560 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
561 Requires<[In32BitMode]>;
564 // x86-64 va_start lowering magic.
565 let usesCustomInserter = 1 in
566 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
569 i64imm:$regsavefi, i64imm:$offset,
571 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
572 [(X86vastart_save_xmm_regs GR8:$al,
577 let neverHasSideEffects = 1 in {
578 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
579 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
580 "nop{w}\t$zero", []>, TB, OpSize;
581 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
582 "nop{l}\t$zero", []>, TB;
586 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
587 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
588 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
589 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
591 // PIC base construction. This expands to code that looks like this:
594 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
595 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
598 //===----------------------------------------------------------------------===//
599 // Control Flow Instructions...
602 // Return instructions.
603 let isTerminator = 1, isReturn = 1, isBarrier = 1,
604 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
605 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
608 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
610 [(X86retflag timm:$amt)]>;
611 def LRET : I <0xCB, RawFrm, (outs), (ins),
613 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
617 // All branches are RawFrm, Void, Branch, and Terminators
618 let isBranch = 1, isTerminator = 1 in
619 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
620 I<opcode, RawFrm, (outs), ins, asm, pattern>;
622 let isBranch = 1, isBarrier = 1 in {
623 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
624 def JMP8 : IBr<0xEB, (ins brtarget8:$dst), "jmp\t$dst", []>;
628 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
629 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
630 [(brind GR32:$dst)]>;
631 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
632 [(brind (loadi32 addr:$dst))]>;
634 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
635 (ins i16imm:$seg, i16imm:$off),
636 "ljmp{w}\t$seg, $off", []>, OpSize;
637 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
638 (ins i16imm:$seg, i32imm:$off),
639 "ljmp{l}\t$seg, $off", []>;
641 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
642 "ljmp{w}\t{*}$dst", []>, OpSize;
643 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
644 "ljmp{l}\t{*}$dst", []>;
647 // Conditional branches
648 let Uses = [EFLAGS] in {
649 // Short conditional jumps
650 def JO8 : IBr<0x70, (ins brtarget8:$dst), "jo\t$dst", []>;
651 def JNO8 : IBr<0x71, (ins brtarget8:$dst), "jno\t$dst", []>;
652 def JB8 : IBr<0x72, (ins brtarget8:$dst), "jb\t$dst", []>;
653 def JAE8 : IBr<0x73, (ins brtarget8:$dst), "jae\t$dst", []>;
654 def JE8 : IBr<0x74, (ins brtarget8:$dst), "je\t$dst", []>;
655 def JNE8 : IBr<0x75, (ins brtarget8:$dst), "jne\t$dst", []>;
656 def JBE8 : IBr<0x76, (ins brtarget8:$dst), "jbe\t$dst", []>;
657 def JA8 : IBr<0x77, (ins brtarget8:$dst), "ja\t$dst", []>;
658 def JS8 : IBr<0x78, (ins brtarget8:$dst), "js\t$dst", []>;
659 def JNS8 : IBr<0x79, (ins brtarget8:$dst), "jns\t$dst", []>;
660 def JP8 : IBr<0x7A, (ins brtarget8:$dst), "jp\t$dst", []>;
661 def JNP8 : IBr<0x7B, (ins brtarget8:$dst), "jnp\t$dst", []>;
662 def JL8 : IBr<0x7C, (ins brtarget8:$dst), "jl\t$dst", []>;
663 def JGE8 : IBr<0x7D, (ins brtarget8:$dst), "jge\t$dst", []>;
664 def JLE8 : IBr<0x7E, (ins brtarget8:$dst), "jle\t$dst", []>;
665 def JG8 : IBr<0x7F, (ins brtarget8:$dst), "jg\t$dst", []>;
667 def JCXZ8 : IBr<0xE3, (ins brtarget8:$dst), "jcxz\t$dst", []>;
669 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
670 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
671 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
672 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
673 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
674 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
675 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
676 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
677 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
678 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
679 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
680 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
682 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
683 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
684 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
685 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
686 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
687 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
688 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
689 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
691 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
692 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
693 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
694 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
695 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
696 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
697 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
698 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
699 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
700 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
701 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
702 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
707 def LOOP : I<0xE2, RawFrm, (ins brtarget8:$dst), (outs), "loop\t$dst", []>;
708 def LOOPE : I<0xE1, RawFrm, (ins brtarget8:$dst), (outs), "loope\t$dst", []>;
709 def LOOPNE : I<0xE0, RawFrm, (ins brtarget8:$dst), (outs), "loopne\t$dst", []>;
711 //===----------------------------------------------------------------------===//
712 // Call Instructions...
715 // All calls clobber the non-callee saved registers. ESP is marked as
716 // a use to prevent stack-pointer assignments that appear immediately
717 // before calls from potentially appearing dead. Uses for argument
718 // registers are added manually.
719 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
720 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
721 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
722 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
724 def CALLpcrel32 : Ii32<0xE8, RawFrm,
725 (outs), (ins i32imm_pcrel:$dst,variable_ops),
727 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
728 "call\t{*}$dst", [(X86call GR32:$dst)]>;
729 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
730 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
732 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
733 (ins i16imm:$seg, i16imm:$off),
734 "lcall{w}\t$seg, $off", []>, OpSize;
735 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
736 (ins i16imm:$seg, i32imm:$off),
737 "lcall{l}\t$seg, $off", []>;
739 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
740 "lcall{w}\t{*}$dst", []>, OpSize;
741 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
742 "lcall{l}\t{*}$dst", []>;
745 // Constructing a stack frame.
747 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
748 "enter\t$len, $lvl", []>;
752 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
753 def TCRETURNdi : I<0, Pseudo, (outs),
754 (ins i32imm:$dst, i32imm:$offset, variable_ops),
755 "#TC_RETURN $dst $offset",
758 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
759 def TCRETURNri : I<0, Pseudo, (outs),
760 (ins GR32:$dst, i32imm:$offset, variable_ops),
761 "#TC_RETURN $dst $offset",
764 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
765 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst, variable_ops),
766 "jmp\t$dst # TAILCALL",
768 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
769 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst, variable_ops),
770 "jmp{l}\t{*}$dst # TAILCALL",
772 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
773 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst, variable_ops),
774 "jmp\t{*}$dst # TAILCALL", []>;
776 //===----------------------------------------------------------------------===//
777 // Miscellaneous Instructions...
779 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
780 def LEAVE : I<0xC9, RawFrm,
781 (outs), (ins), "leave", []>;
783 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
784 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
785 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
786 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
787 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
788 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
789 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
790 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
792 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
794 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
796 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
797 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
799 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
801 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
802 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
805 let mayStore = 1 in {
806 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
808 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
809 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
811 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
813 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
814 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
818 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
819 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
820 "push{l}\t$imm", []>;
821 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
822 "push{l}\t$imm", []>;
823 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
824 "push{l}\t$imm", []>;
827 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
828 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
829 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
831 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
832 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
833 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
836 let isTwoAddress = 1 in // GR32 = bswap GR32
837 def BSWAP32r : I<0xC8, AddRegFrm,
838 (outs GR32:$dst), (ins GR32:$src),
840 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
843 // Bit scan instructions.
844 let Defs = [EFLAGS] in {
845 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
846 "bsf{w}\t{$src, $dst|$dst, $src}",
847 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
848 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
849 "bsf{w}\t{$src, $dst|$dst, $src}",
850 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
851 (implicit EFLAGS)]>, TB;
852 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
853 "bsf{l}\t{$src, $dst|$dst, $src}",
854 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
855 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
856 "bsf{l}\t{$src, $dst|$dst, $src}",
857 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
858 (implicit EFLAGS)]>, TB;
860 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
861 "bsr{w}\t{$src, $dst|$dst, $src}",
862 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
863 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
864 "bsr{w}\t{$src, $dst|$dst, $src}",
865 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
866 (implicit EFLAGS)]>, TB;
867 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
868 "bsr{l}\t{$src, $dst|$dst, $src}",
869 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
870 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
871 "bsr{l}\t{$src, $dst|$dst, $src}",
872 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
873 (implicit EFLAGS)]>, TB;
876 let neverHasSideEffects = 1 in
877 def LEA16r : I<0x8D, MRMSrcMem,
878 (outs GR16:$dst), (ins lea32mem:$src),
879 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
880 let isReMaterializable = 1 in
881 def LEA32r : I<0x8D, MRMSrcMem,
882 (outs GR32:$dst), (ins lea32mem:$src),
883 "lea{l}\t{$src|$dst}, {$dst|$src}",
884 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
886 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
887 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
888 [(X86rep_movs i8)]>, REP;
889 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
890 [(X86rep_movs i16)]>, REP, OpSize;
891 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
892 [(X86rep_movs i32)]>, REP;
895 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
896 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
897 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
898 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
899 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
902 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
903 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
904 [(X86rep_stos i8)]>, REP;
905 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
906 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
907 [(X86rep_stos i16)]>, REP, OpSize;
908 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
909 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
910 [(X86rep_stos i32)]>, REP;
912 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
913 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
914 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
915 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
916 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
917 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
918 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
920 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
921 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
922 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
924 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
925 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
926 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
928 let Defs = [RAX, RDX] in
929 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
932 let isBarrier = 1, hasCtrlDep = 1 in {
933 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
936 def SYSCALL : I<0x05, RawFrm,
937 (outs), (ins), "syscall", []>, TB;
938 def SYSRET : I<0x07, RawFrm,
939 (outs), (ins), "sysret", []>, TB;
940 def SYSENTER : I<0x34, RawFrm,
941 (outs), (ins), "sysenter", []>, TB;
942 def SYSEXIT : I<0x35, RawFrm,
943 (outs), (ins), "sysexit", []>, TB;
945 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
948 //===----------------------------------------------------------------------===//
949 // Input/Output Instructions...
951 let Defs = [AL], Uses = [DX] in
952 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
953 "in{b}\t{%dx, %al|%AL, %DX}", []>;
954 let Defs = [AX], Uses = [DX] in
955 def IN16rr : I<0xED, RawFrm, (outs), (ins),
956 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
957 let Defs = [EAX], Uses = [DX] in
958 def IN32rr : I<0xED, RawFrm, (outs), (ins),
959 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
962 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
963 "in{b}\t{$port, %al|%AL, $port}", []>;
965 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
966 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
968 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
969 "in{l}\t{$port, %eax|%EAX, $port}", []>;
971 let Uses = [DX, AL] in
972 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
973 "out{b}\t{%al, %dx|%DX, %AL}", []>;
974 let Uses = [DX, AX] in
975 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
976 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
977 let Uses = [DX, EAX] in
978 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
979 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
982 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
983 "out{b}\t{%al, $port|$port, %AL}", []>;
985 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
986 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
988 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
989 "out{l}\t{%eax, $port|$port, %EAX}", []>;
991 def IN8 : I<0x6C, RawFrm, (outs), (ins),
993 def IN16 : I<0x6D, RawFrm, (outs), (ins),
994 "ins{w}", []>, OpSize;
995 def IN32 : I<0x6D, RawFrm, (outs), (ins),
998 //===----------------------------------------------------------------------===//
999 // Move Instructions...
1001 let neverHasSideEffects = 1 in {
1002 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1003 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1004 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1005 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1006 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1007 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1009 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1010 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1011 "mov{b}\t{$src, $dst|$dst, $src}",
1012 [(set GR8:$dst, imm:$src)]>;
1013 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1014 "mov{w}\t{$src, $dst|$dst, $src}",
1015 [(set GR16:$dst, imm:$src)]>, OpSize;
1016 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1017 "mov{l}\t{$src, $dst|$dst, $src}",
1018 [(set GR32:$dst, imm:$src)]>;
1021 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1022 "mov{b}\t{$src, $dst|$dst, $src}",
1023 [(store (i8 imm:$src), addr:$dst)]>;
1024 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1025 "mov{w}\t{$src, $dst|$dst, $src}",
1026 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
1027 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1028 "mov{l}\t{$src, $dst|$dst, $src}",
1029 [(store (i32 imm:$src), addr:$dst)]>;
1031 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src),
1032 "mov{b}\t{$src, %al|%al, $src}", []>;
1033 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
1034 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1035 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1036 "mov{l}\t{$src, %eax|%eax, $src}", []>;
1038 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1039 "mov{b}\t{%al, $dst|$dst, %al}", []>;
1040 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1041 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
1042 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1043 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
1045 // Moves to and from segment registers
1046 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1047 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1048 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1049 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1050 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1051 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1052 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1053 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1055 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1056 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1057 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1058 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1059 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1060 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1062 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
1063 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1064 "mov{b}\t{$src, $dst|$dst, $src}",
1065 [(set GR8:$dst, (loadi8 addr:$src))]>;
1066 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1067 "mov{w}\t{$src, $dst|$dst, $src}",
1068 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1069 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1070 "mov{l}\t{$src, $dst|$dst, $src}",
1071 [(set GR32:$dst, (loadi32 addr:$src))]>;
1074 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1075 "mov{b}\t{$src, $dst|$dst, $src}",
1076 [(store GR8:$src, addr:$dst)]>;
1077 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1078 "mov{w}\t{$src, $dst|$dst, $src}",
1079 [(store GR16:$src, addr:$dst)]>, OpSize;
1080 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1081 "mov{l}\t{$src, $dst|$dst, $src}",
1082 [(store GR32:$src, addr:$dst)]>;
1084 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1085 // that they can be used for copying and storing h registers, which can't be
1086 // encoded when a REX prefix is present.
1087 let neverHasSideEffects = 1 in
1088 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1089 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1090 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1092 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1093 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1094 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1096 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1097 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1098 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1099 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1101 // Moves to and from debug registers
1102 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1103 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1104 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1105 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1107 // Moves to and from control registers
1108 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
1109 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1110 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
1111 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1113 //===----------------------------------------------------------------------===//
1114 // Fixed-Register Multiplication and Division Instructions...
1117 // Extra precision multiplication
1118 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1119 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1120 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1121 // This probably ought to be moved to a def : Pat<> if the
1122 // syntax can be accepted.
1123 [(set AL, (mul AL, GR8:$src)),
1124 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1126 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1127 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1129 []>, OpSize; // AX,DX = AX*GR16
1131 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1132 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1134 []>; // EAX,EDX = EAX*GR32
1136 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1137 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1139 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1140 // This probably ought to be moved to a def : Pat<> if the
1141 // syntax can be accepted.
1142 [(set AL, (mul AL, (loadi8 addr:$src))),
1143 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1145 let mayLoad = 1, neverHasSideEffects = 1 in {
1146 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1147 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1149 []>, OpSize; // AX,DX = AX*[mem16]
1151 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1152 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1154 []>; // EAX,EDX = EAX*[mem32]
1157 let neverHasSideEffects = 1 in {
1158 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1159 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1161 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1162 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1163 OpSize; // AX,DX = AX*GR16
1164 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1165 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1166 // EAX,EDX = EAX*GR32
1167 let mayLoad = 1 in {
1168 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
1169 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1170 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1171 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1172 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1173 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1174 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1175 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1176 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1178 } // neverHasSideEffects
1180 // unsigned division/remainder
1181 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1182 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1183 "div{b}\t$src", []>;
1184 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1185 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1186 "div{w}\t$src", []>, OpSize;
1187 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1188 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1189 "div{l}\t$src", []>;
1190 let mayLoad = 1 in {
1191 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1192 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1193 "div{b}\t$src", []>;
1194 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1195 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1196 "div{w}\t$src", []>, OpSize;
1197 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1198 // EDX:EAX/[mem32] = EAX,EDX
1199 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1200 "div{l}\t$src", []>;
1203 // Signed division/remainder.
1204 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1205 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1206 "idiv{b}\t$src", []>;
1207 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1208 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1209 "idiv{w}\t$src", []>, OpSize;
1210 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1211 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1212 "idiv{l}\t$src", []>;
1213 let mayLoad = 1, mayLoad = 1 in {
1214 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
1215 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1216 "idiv{b}\t$src", []>;
1217 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1218 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1219 "idiv{w}\t$src", []>, OpSize;
1220 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1221 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1222 // EDX:EAX/[mem32] = EAX,EDX
1223 "idiv{l}\t$src", []>;
1226 //===----------------------------------------------------------------------===//
1227 // Two address Instructions.
1229 let isTwoAddress = 1 in {
1231 // Conditional moves
1232 let Uses = [EFLAGS] in {
1234 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1235 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1236 // however that requires promoting the operands, and can induce additional
1237 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1238 // clobber EFLAGS, because if one of the operands is zero, the expansion
1239 // could involve an xor.
1240 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
1241 def CMOV_GR8 : I<0, Pseudo,
1242 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1243 "#CMOV_GR8 PSEUDO!",
1244 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1245 imm:$cond, EFLAGS))]>;
1247 let isCommutable = 1 in {
1248 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1249 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1250 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1251 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1252 X86_COND_B, EFLAGS))]>,
1254 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1255 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1256 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1257 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1258 X86_COND_B, EFLAGS))]>,
1260 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1261 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1262 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1263 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1264 X86_COND_AE, EFLAGS))]>,
1266 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1267 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1268 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1269 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1270 X86_COND_AE, EFLAGS))]>,
1272 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1273 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1274 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1275 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1276 X86_COND_E, EFLAGS))]>,
1278 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1279 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1280 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1281 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1282 X86_COND_E, EFLAGS))]>,
1284 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1285 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1286 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1287 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1288 X86_COND_NE, EFLAGS))]>,
1290 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1291 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1292 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1293 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1294 X86_COND_NE, EFLAGS))]>,
1296 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1297 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1298 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1299 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1300 X86_COND_BE, EFLAGS))]>,
1302 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1303 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1304 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1305 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1306 X86_COND_BE, EFLAGS))]>,
1308 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1309 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1310 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1311 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1312 X86_COND_A, EFLAGS))]>,
1314 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1315 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1316 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1317 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1318 X86_COND_A, EFLAGS))]>,
1320 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1321 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1322 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1323 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1324 X86_COND_L, EFLAGS))]>,
1326 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1327 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1328 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1329 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1330 X86_COND_L, EFLAGS))]>,
1332 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1333 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1334 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1335 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1336 X86_COND_GE, EFLAGS))]>,
1338 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1339 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1340 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1341 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1342 X86_COND_GE, EFLAGS))]>,
1344 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1345 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1346 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1347 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1348 X86_COND_LE, EFLAGS))]>,
1350 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1351 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1352 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1353 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1354 X86_COND_LE, EFLAGS))]>,
1356 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1357 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1358 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1359 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1360 X86_COND_G, EFLAGS))]>,
1362 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1363 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1364 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1365 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1366 X86_COND_G, EFLAGS))]>,
1368 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1369 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1370 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1371 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1372 X86_COND_S, EFLAGS))]>,
1374 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1375 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1376 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1377 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1378 X86_COND_S, EFLAGS))]>,
1380 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1381 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1382 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1383 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1384 X86_COND_NS, EFLAGS))]>,
1386 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1387 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1388 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1389 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1390 X86_COND_NS, EFLAGS))]>,
1392 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1393 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1394 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1395 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1396 X86_COND_P, EFLAGS))]>,
1398 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1399 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1400 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1401 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1402 X86_COND_P, EFLAGS))]>,
1404 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1405 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1406 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1407 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1408 X86_COND_NP, EFLAGS))]>,
1410 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1411 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1412 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1413 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1414 X86_COND_NP, EFLAGS))]>,
1416 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1417 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1418 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1419 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1420 X86_COND_O, EFLAGS))]>,
1422 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1423 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1424 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1425 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1426 X86_COND_O, EFLAGS))]>,
1428 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1429 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1430 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1431 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1432 X86_COND_NO, EFLAGS))]>,
1434 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1435 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1436 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1437 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1438 X86_COND_NO, EFLAGS))]>,
1440 } // isCommutable = 1
1442 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1443 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1444 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1445 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1446 X86_COND_B, EFLAGS))]>,
1448 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1449 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1450 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1451 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1452 X86_COND_B, EFLAGS))]>,
1454 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1455 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1456 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1457 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1458 X86_COND_AE, EFLAGS))]>,
1460 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1461 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1462 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1463 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1464 X86_COND_AE, EFLAGS))]>,
1466 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1467 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1468 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1469 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1470 X86_COND_E, EFLAGS))]>,
1472 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1473 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1474 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1475 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1476 X86_COND_E, EFLAGS))]>,
1478 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1479 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1480 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1481 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1482 X86_COND_NE, EFLAGS))]>,
1484 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1485 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1486 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1487 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1488 X86_COND_NE, EFLAGS))]>,
1490 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1491 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1492 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1493 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1494 X86_COND_BE, EFLAGS))]>,
1496 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1497 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1498 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1499 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1500 X86_COND_BE, EFLAGS))]>,
1502 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1503 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1504 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1505 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1506 X86_COND_A, EFLAGS))]>,
1508 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1509 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1510 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1511 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1512 X86_COND_A, EFLAGS))]>,
1514 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1515 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1516 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1517 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1518 X86_COND_L, EFLAGS))]>,
1520 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1521 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1522 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1523 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1524 X86_COND_L, EFLAGS))]>,
1526 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1527 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1528 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1529 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1530 X86_COND_GE, EFLAGS))]>,
1532 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1533 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1534 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1535 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1536 X86_COND_GE, EFLAGS))]>,
1538 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1539 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1540 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1541 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1542 X86_COND_LE, EFLAGS))]>,
1544 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1545 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1546 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1547 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1548 X86_COND_LE, EFLAGS))]>,
1550 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1551 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1552 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1553 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1554 X86_COND_G, EFLAGS))]>,
1556 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1557 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1558 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1559 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1560 X86_COND_G, EFLAGS))]>,
1562 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1563 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1564 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1565 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1566 X86_COND_S, EFLAGS))]>,
1568 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1569 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1570 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1571 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1572 X86_COND_S, EFLAGS))]>,
1574 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1575 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1576 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1577 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1578 X86_COND_NS, EFLAGS))]>,
1580 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1581 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1582 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1583 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1584 X86_COND_NS, EFLAGS))]>,
1586 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1587 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1588 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1589 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1590 X86_COND_P, EFLAGS))]>,
1592 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1593 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1594 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1595 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1596 X86_COND_P, EFLAGS))]>,
1598 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1599 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1600 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1601 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1602 X86_COND_NP, EFLAGS))]>,
1604 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1605 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1606 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1607 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1608 X86_COND_NP, EFLAGS))]>,
1610 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1611 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1612 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1613 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1614 X86_COND_O, EFLAGS))]>,
1616 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1617 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1618 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1619 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1620 X86_COND_O, EFLAGS))]>,
1622 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1623 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1624 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1625 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1626 X86_COND_NO, EFLAGS))]>,
1628 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1629 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1630 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1631 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1632 X86_COND_NO, EFLAGS))]>,
1634 } // Uses = [EFLAGS]
1637 // unary instructions
1638 let CodeSize = 2 in {
1639 let Defs = [EFLAGS] in {
1640 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1641 [(set GR8:$dst, (ineg GR8:$src)),
1642 (implicit EFLAGS)]>;
1643 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1644 [(set GR16:$dst, (ineg GR16:$src)),
1645 (implicit EFLAGS)]>, OpSize;
1646 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1647 [(set GR32:$dst, (ineg GR32:$src)),
1648 (implicit EFLAGS)]>;
1649 let isTwoAddress = 0 in {
1650 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1651 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1652 (implicit EFLAGS)]>;
1653 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1654 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1655 (implicit EFLAGS)]>, OpSize;
1656 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1657 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1658 (implicit EFLAGS)]>;
1660 } // Defs = [EFLAGS]
1662 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1663 let AddedComplexity = 15 in {
1664 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1665 [(set GR8:$dst, (not GR8:$src))]>;
1666 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1667 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1668 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1669 [(set GR32:$dst, (not GR32:$src))]>;
1671 let isTwoAddress = 0 in {
1672 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1673 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1674 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1675 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1676 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1677 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1681 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1682 let Defs = [EFLAGS] in {
1684 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1685 [(set GR8:$dst, (add GR8:$src, 1)),
1686 (implicit EFLAGS)]>;
1687 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1688 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1690 [(set GR16:$dst, (add GR16:$src, 1)),
1691 (implicit EFLAGS)]>,
1692 OpSize, Requires<[In32BitMode]>;
1693 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1695 [(set GR32:$dst, (add GR32:$src, 1)),
1696 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1698 let isTwoAddress = 0, CodeSize = 2 in {
1699 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1700 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1701 (implicit EFLAGS)]>;
1702 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1703 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1704 (implicit EFLAGS)]>,
1705 OpSize, Requires<[In32BitMode]>;
1706 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1707 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1708 (implicit EFLAGS)]>,
1709 Requires<[In32BitMode]>;
1713 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1714 [(set GR8:$dst, (add GR8:$src, -1)),
1715 (implicit EFLAGS)]>;
1716 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1717 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1719 [(set GR16:$dst, (add GR16:$src, -1)),
1720 (implicit EFLAGS)]>,
1721 OpSize, Requires<[In32BitMode]>;
1722 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1724 [(set GR32:$dst, (add GR32:$src, -1)),
1725 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1728 let isTwoAddress = 0, CodeSize = 2 in {
1729 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1730 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1731 (implicit EFLAGS)]>;
1732 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1733 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1734 (implicit EFLAGS)]>,
1735 OpSize, Requires<[In32BitMode]>;
1736 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1737 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1738 (implicit EFLAGS)]>,
1739 Requires<[In32BitMode]>;
1741 } // Defs = [EFLAGS]
1743 // Logical operators...
1744 let Defs = [EFLAGS] in {
1745 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1746 def AND8rr : I<0x20, MRMDestReg,
1747 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1748 "and{b}\t{$src2, $dst|$dst, $src2}",
1749 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1750 (implicit EFLAGS)]>;
1751 def AND16rr : I<0x21, MRMDestReg,
1752 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1753 "and{w}\t{$src2, $dst|$dst, $src2}",
1754 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1755 (implicit EFLAGS)]>, OpSize;
1756 def AND32rr : I<0x21, MRMDestReg,
1757 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1758 "and{l}\t{$src2, $dst|$dst, $src2}",
1759 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1760 (implicit EFLAGS)]>;
1763 // AND instructions with the destination register in REG and the source register
1764 // in R/M. Included for the disassembler.
1765 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1766 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1767 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1768 (ins GR16:$src1, GR16:$src2),
1769 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1770 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1771 (ins GR32:$src1, GR32:$src2),
1772 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1774 def AND8rm : I<0x22, MRMSrcMem,
1775 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1776 "and{b}\t{$src2, $dst|$dst, $src2}",
1777 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1778 (implicit EFLAGS)]>;
1779 def AND16rm : I<0x23, MRMSrcMem,
1780 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1781 "and{w}\t{$src2, $dst|$dst, $src2}",
1782 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1783 (implicit EFLAGS)]>, OpSize;
1784 def AND32rm : I<0x23, MRMSrcMem,
1785 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1786 "and{l}\t{$src2, $dst|$dst, $src2}",
1787 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1788 (implicit EFLAGS)]>;
1790 def AND8ri : Ii8<0x80, MRM4r,
1791 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1792 "and{b}\t{$src2, $dst|$dst, $src2}",
1793 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1794 (implicit EFLAGS)]>;
1795 def AND16ri : Ii16<0x81, MRM4r,
1796 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1797 "and{w}\t{$src2, $dst|$dst, $src2}",
1798 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1799 (implicit EFLAGS)]>, OpSize;
1800 def AND32ri : Ii32<0x81, MRM4r,
1801 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1802 "and{l}\t{$src2, $dst|$dst, $src2}",
1803 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1804 (implicit EFLAGS)]>;
1805 def AND16ri8 : Ii8<0x83, MRM4r,
1806 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1807 "and{w}\t{$src2, $dst|$dst, $src2}",
1808 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1809 (implicit EFLAGS)]>,
1811 def AND32ri8 : Ii8<0x83, MRM4r,
1812 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1813 "and{l}\t{$src2, $dst|$dst, $src2}",
1814 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1815 (implicit EFLAGS)]>;
1817 let isTwoAddress = 0 in {
1818 def AND8mr : I<0x20, MRMDestMem,
1819 (outs), (ins i8mem :$dst, GR8 :$src),
1820 "and{b}\t{$src, $dst|$dst, $src}",
1821 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1822 (implicit EFLAGS)]>;
1823 def AND16mr : I<0x21, MRMDestMem,
1824 (outs), (ins i16mem:$dst, GR16:$src),
1825 "and{w}\t{$src, $dst|$dst, $src}",
1826 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1827 (implicit EFLAGS)]>,
1829 def AND32mr : I<0x21, MRMDestMem,
1830 (outs), (ins i32mem:$dst, GR32:$src),
1831 "and{l}\t{$src, $dst|$dst, $src}",
1832 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1833 (implicit EFLAGS)]>;
1834 def AND8mi : Ii8<0x80, MRM4m,
1835 (outs), (ins i8mem :$dst, i8imm :$src),
1836 "and{b}\t{$src, $dst|$dst, $src}",
1837 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1838 (implicit EFLAGS)]>;
1839 def AND16mi : Ii16<0x81, MRM4m,
1840 (outs), (ins i16mem:$dst, i16imm:$src),
1841 "and{w}\t{$src, $dst|$dst, $src}",
1842 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1843 (implicit EFLAGS)]>,
1845 def AND32mi : Ii32<0x81, MRM4m,
1846 (outs), (ins i32mem:$dst, i32imm:$src),
1847 "and{l}\t{$src, $dst|$dst, $src}",
1848 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1849 (implicit EFLAGS)]>;
1850 def AND16mi8 : Ii8<0x83, MRM4m,
1851 (outs), (ins i16mem:$dst, i16i8imm :$src),
1852 "and{w}\t{$src, $dst|$dst, $src}",
1853 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1854 (implicit EFLAGS)]>,
1856 def AND32mi8 : Ii8<0x83, MRM4m,
1857 (outs), (ins i32mem:$dst, i32i8imm :$src),
1858 "and{l}\t{$src, $dst|$dst, $src}",
1859 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1860 (implicit EFLAGS)]>;
1862 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1863 "and{b}\t{$src, %al|%al, $src}", []>;
1864 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1865 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1866 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1867 "and{l}\t{$src, %eax|%eax, $src}", []>;
1872 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1873 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1874 (ins GR8 :$src1, GR8 :$src2),
1875 "or{b}\t{$src2, $dst|$dst, $src2}",
1876 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1877 (implicit EFLAGS)]>;
1878 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1879 (ins GR16:$src1, GR16:$src2),
1880 "or{w}\t{$src2, $dst|$dst, $src2}",
1881 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1882 (implicit EFLAGS)]>, OpSize;
1883 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1884 (ins GR32:$src1, GR32:$src2),
1885 "or{l}\t{$src2, $dst|$dst, $src2}",
1886 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1887 (implicit EFLAGS)]>;
1890 // OR instructions with the destination register in REG and the source register
1891 // in R/M. Included for the disassembler.
1892 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1893 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1894 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1895 (ins GR16:$src1, GR16:$src2),
1896 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1897 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1898 (ins GR32:$src1, GR32:$src2),
1899 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1901 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst),
1902 (ins GR8 :$src1, i8mem :$src2),
1903 "or{b}\t{$src2, $dst|$dst, $src2}",
1904 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1905 (implicit EFLAGS)]>;
1906 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst),
1907 (ins GR16:$src1, i16mem:$src2),
1908 "or{w}\t{$src2, $dst|$dst, $src2}",
1909 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1910 (implicit EFLAGS)]>, OpSize;
1911 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst),
1912 (ins GR32:$src1, i32mem:$src2),
1913 "or{l}\t{$src2, $dst|$dst, $src2}",
1914 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1915 (implicit EFLAGS)]>;
1917 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1918 (ins GR8 :$src1, i8imm:$src2),
1919 "or{b}\t{$src2, $dst|$dst, $src2}",
1920 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1921 (implicit EFLAGS)]>;
1922 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1923 (ins GR16:$src1, i16imm:$src2),
1924 "or{w}\t{$src2, $dst|$dst, $src2}",
1925 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1926 (implicit EFLAGS)]>, OpSize;
1927 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1928 (ins GR32:$src1, i32imm:$src2),
1929 "or{l}\t{$src2, $dst|$dst, $src2}",
1930 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1931 (implicit EFLAGS)]>;
1933 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1934 (ins GR16:$src1, i16i8imm:$src2),
1935 "or{w}\t{$src2, $dst|$dst, $src2}",
1936 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1937 (implicit EFLAGS)]>, OpSize;
1938 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1939 (ins GR32:$src1, i32i8imm:$src2),
1940 "or{l}\t{$src2, $dst|$dst, $src2}",
1941 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1942 (implicit EFLAGS)]>;
1943 let isTwoAddress = 0 in {
1944 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1945 "or{b}\t{$src, $dst|$dst, $src}",
1946 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1947 (implicit EFLAGS)]>;
1948 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1949 "or{w}\t{$src, $dst|$dst, $src}",
1950 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1951 (implicit EFLAGS)]>, OpSize;
1952 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1953 "or{l}\t{$src, $dst|$dst, $src}",
1954 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1955 (implicit EFLAGS)]>;
1956 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1957 "or{b}\t{$src, $dst|$dst, $src}",
1958 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1959 (implicit EFLAGS)]>;
1960 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1961 "or{w}\t{$src, $dst|$dst, $src}",
1962 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1963 (implicit EFLAGS)]>,
1965 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1966 "or{l}\t{$src, $dst|$dst, $src}",
1967 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1968 (implicit EFLAGS)]>;
1969 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1970 "or{w}\t{$src, $dst|$dst, $src}",
1971 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1972 (implicit EFLAGS)]>,
1974 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1975 "or{l}\t{$src, $dst|$dst, $src}",
1976 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1977 (implicit EFLAGS)]>;
1979 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1980 "or{b}\t{$src, %al|%al, $src}", []>;
1981 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1982 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1983 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1984 "or{l}\t{$src, %eax|%eax, $src}", []>;
1985 } // isTwoAddress = 0
1988 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1989 def XOR8rr : I<0x30, MRMDestReg,
1990 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1991 "xor{b}\t{$src2, $dst|$dst, $src2}",
1992 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1993 (implicit EFLAGS)]>;
1994 def XOR16rr : I<0x31, MRMDestReg,
1995 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1996 "xor{w}\t{$src2, $dst|$dst, $src2}",
1997 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1998 (implicit EFLAGS)]>, OpSize;
1999 def XOR32rr : I<0x31, MRMDestReg,
2000 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2001 "xor{l}\t{$src2, $dst|$dst, $src2}",
2002 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
2003 (implicit EFLAGS)]>;
2004 } // isCommutable = 1
2006 // XOR instructions with the destination register in REG and the source register
2007 // in R/M. Included for the disassembler.
2008 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2009 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
2010 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
2011 (ins GR16:$src1, GR16:$src2),
2012 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2013 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
2014 (ins GR32:$src1, GR32:$src2),
2015 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2017 def XOR8rm : I<0x32, MRMSrcMem ,
2018 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2019 "xor{b}\t{$src2, $dst|$dst, $src2}",
2020 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
2021 (implicit EFLAGS)]>;
2022 def XOR16rm : I<0x33, MRMSrcMem ,
2023 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2024 "xor{w}\t{$src2, $dst|$dst, $src2}",
2025 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
2026 (implicit EFLAGS)]>,
2028 def XOR32rm : I<0x33, MRMSrcMem ,
2029 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2030 "xor{l}\t{$src2, $dst|$dst, $src2}",
2031 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
2032 (implicit EFLAGS)]>;
2034 def XOR8ri : Ii8<0x80, MRM6r,
2035 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2036 "xor{b}\t{$src2, $dst|$dst, $src2}",
2037 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
2038 (implicit EFLAGS)]>;
2039 def XOR16ri : Ii16<0x81, MRM6r,
2040 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2041 "xor{w}\t{$src2, $dst|$dst, $src2}",
2042 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
2043 (implicit EFLAGS)]>, OpSize;
2044 def XOR32ri : Ii32<0x81, MRM6r,
2045 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2046 "xor{l}\t{$src2, $dst|$dst, $src2}",
2047 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
2048 (implicit EFLAGS)]>;
2049 def XOR16ri8 : Ii8<0x83, MRM6r,
2050 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2051 "xor{w}\t{$src2, $dst|$dst, $src2}",
2052 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
2053 (implicit EFLAGS)]>,
2055 def XOR32ri8 : Ii8<0x83, MRM6r,
2056 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2057 "xor{l}\t{$src2, $dst|$dst, $src2}",
2058 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
2059 (implicit EFLAGS)]>;
2061 let isTwoAddress = 0 in {
2062 def XOR8mr : I<0x30, MRMDestMem,
2063 (outs), (ins i8mem :$dst, GR8 :$src),
2064 "xor{b}\t{$src, $dst|$dst, $src}",
2065 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2066 (implicit EFLAGS)]>;
2067 def XOR16mr : I<0x31, MRMDestMem,
2068 (outs), (ins i16mem:$dst, GR16:$src),
2069 "xor{w}\t{$src, $dst|$dst, $src}",
2070 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2071 (implicit EFLAGS)]>,
2073 def XOR32mr : I<0x31, MRMDestMem,
2074 (outs), (ins i32mem:$dst, GR32:$src),
2075 "xor{l}\t{$src, $dst|$dst, $src}",
2076 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2077 (implicit EFLAGS)]>;
2078 def XOR8mi : Ii8<0x80, MRM6m,
2079 (outs), (ins i8mem :$dst, i8imm :$src),
2080 "xor{b}\t{$src, $dst|$dst, $src}",
2081 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2082 (implicit EFLAGS)]>;
2083 def XOR16mi : Ii16<0x81, MRM6m,
2084 (outs), (ins i16mem:$dst, i16imm:$src),
2085 "xor{w}\t{$src, $dst|$dst, $src}",
2086 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2087 (implicit EFLAGS)]>,
2089 def XOR32mi : Ii32<0x81, MRM6m,
2090 (outs), (ins i32mem:$dst, i32imm:$src),
2091 "xor{l}\t{$src, $dst|$dst, $src}",
2092 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2093 (implicit EFLAGS)]>;
2094 def XOR16mi8 : Ii8<0x83, MRM6m,
2095 (outs), (ins i16mem:$dst, i16i8imm :$src),
2096 "xor{w}\t{$src, $dst|$dst, $src}",
2097 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2098 (implicit EFLAGS)]>,
2100 def XOR32mi8 : Ii8<0x83, MRM6m,
2101 (outs), (ins i32mem:$dst, i32i8imm :$src),
2102 "xor{l}\t{$src, $dst|$dst, $src}",
2103 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2104 (implicit EFLAGS)]>;
2106 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2107 "xor{b}\t{$src, %al|%al, $src}", []>;
2108 def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src),
2109 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2110 def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src),
2111 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2112 } // isTwoAddress = 0
2113 } // Defs = [EFLAGS]
2115 // Shift instructions
2116 let Defs = [EFLAGS] in {
2117 let Uses = [CL] in {
2118 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2119 "shl{b}\t{%cl, $dst|$dst, CL}",
2120 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2121 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2122 "shl{w}\t{%cl, $dst|$dst, CL}",
2123 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2124 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2125 "shl{l}\t{%cl, $dst|$dst, CL}",
2126 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2129 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2130 "shl{b}\t{$src2, $dst|$dst, $src2}",
2131 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2132 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2133 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2134 "shl{w}\t{$src2, $dst|$dst, $src2}",
2135 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2136 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2137 "shl{l}\t{$src2, $dst|$dst, $src2}",
2138 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2140 // NOTE: We don't include patterns for shifts of a register by one, because
2141 // 'add reg,reg' is cheaper.
2143 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2144 "shl{b}\t$dst", []>;
2145 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2146 "shl{w}\t$dst", []>, OpSize;
2147 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2148 "shl{l}\t$dst", []>;
2150 } // isConvertibleToThreeAddress = 1
2152 let isTwoAddress = 0 in {
2153 let Uses = [CL] in {
2154 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2155 "shl{b}\t{%cl, $dst|$dst, CL}",
2156 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2157 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2158 "shl{w}\t{%cl, $dst|$dst, CL}",
2159 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2160 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2161 "shl{l}\t{%cl, $dst|$dst, CL}",
2162 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2164 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2165 "shl{b}\t{$src, $dst|$dst, $src}",
2166 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2167 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2168 "shl{w}\t{$src, $dst|$dst, $src}",
2169 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2171 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2172 "shl{l}\t{$src, $dst|$dst, $src}",
2173 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2176 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2178 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2179 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2181 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2183 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2185 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2188 let Uses = [CL] in {
2189 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2190 "shr{b}\t{%cl, $dst|$dst, CL}",
2191 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2192 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2193 "shr{w}\t{%cl, $dst|$dst, CL}",
2194 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2195 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2196 "shr{l}\t{%cl, $dst|$dst, CL}",
2197 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2200 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2201 "shr{b}\t{$src2, $dst|$dst, $src2}",
2202 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2203 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2204 "shr{w}\t{$src2, $dst|$dst, $src2}",
2205 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2206 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2207 "shr{l}\t{$src2, $dst|$dst, $src2}",
2208 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2211 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2213 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2214 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2216 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2217 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2219 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2221 let isTwoAddress = 0 in {
2222 let Uses = [CL] in {
2223 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2224 "shr{b}\t{%cl, $dst|$dst, CL}",
2225 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2226 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2227 "shr{w}\t{%cl, $dst|$dst, CL}",
2228 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2230 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2231 "shr{l}\t{%cl, $dst|$dst, CL}",
2232 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2234 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2235 "shr{b}\t{$src, $dst|$dst, $src}",
2236 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2237 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2238 "shr{w}\t{$src, $dst|$dst, $src}",
2239 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2241 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2242 "shr{l}\t{$src, $dst|$dst, $src}",
2243 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2246 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2248 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2249 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2251 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2252 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2254 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2257 let Uses = [CL] in {
2258 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2259 "sar{b}\t{%cl, $dst|$dst, CL}",
2260 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2261 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2262 "sar{w}\t{%cl, $dst|$dst, CL}",
2263 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2264 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2265 "sar{l}\t{%cl, $dst|$dst, CL}",
2266 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2269 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2270 "sar{b}\t{$src2, $dst|$dst, $src2}",
2271 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2272 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2273 "sar{w}\t{$src2, $dst|$dst, $src2}",
2274 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2276 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2277 "sar{l}\t{$src2, $dst|$dst, $src2}",
2278 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2281 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2283 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2284 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2286 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2287 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2289 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2291 let isTwoAddress = 0 in {
2292 let Uses = [CL] in {
2293 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2294 "sar{b}\t{%cl, $dst|$dst, CL}",
2295 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2296 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2297 "sar{w}\t{%cl, $dst|$dst, CL}",
2298 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2299 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2300 "sar{l}\t{%cl, $dst|$dst, CL}",
2301 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2303 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2304 "sar{b}\t{$src, $dst|$dst, $src}",
2305 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2306 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2307 "sar{w}\t{$src, $dst|$dst, $src}",
2308 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2310 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2311 "sar{l}\t{$src, $dst|$dst, $src}",
2312 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2315 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2317 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2318 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2320 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2322 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2324 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2327 // Rotate instructions
2329 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2330 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2331 def RCL8m1 : I<0xD0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src),
2332 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2333 let Uses = [CL] in {
2334 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2335 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2336 def RCL8mCL : I<0xD2, MRM2m, (outs i8mem:$dst), (ins i8mem:$src),
2337 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2339 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2340 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2341 def RCL8mi : Ii8<0xC0, MRM2m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt),
2342 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2344 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2345 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2346 def RCL16m1 : I<0xD1, MRM2m, (outs i16mem:$dst), (ins i16mem:$src),
2347 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2348 let Uses = [CL] in {
2349 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2350 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2351 def RCL16mCL : I<0xD3, MRM2m, (outs i16mem:$dst), (ins i16mem:$src),
2352 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2354 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2355 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2356 def RCL16mi : Ii8<0xC1, MRM2m, (outs i16mem:$dst),
2357 (ins i16mem:$src, i8imm:$cnt),
2358 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2360 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2361 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2362 def RCL32m1 : I<0xD1, MRM2m, (outs i32mem:$dst), (ins i32mem:$src),
2363 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2364 let Uses = [CL] in {
2365 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2366 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2367 def RCL32mCL : I<0xD3, MRM2m, (outs i32mem:$dst), (ins i32mem:$src),
2368 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2370 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2371 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2372 def RCL32mi : Ii8<0xC1, MRM2m, (outs i32mem:$dst),
2373 (ins i32mem:$src, i8imm:$cnt),
2374 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2376 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2377 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2378 def RCR8m1 : I<0xD0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src),
2379 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2380 let Uses = [CL] in {
2381 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2382 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2383 def RCR8mCL : I<0xD2, MRM3m, (outs i8mem:$dst), (ins i8mem:$src),
2384 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2386 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2387 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2388 def RCR8mi : Ii8<0xC0, MRM3m, (outs i8mem:$dst), (ins i8mem:$src, i8imm:$cnt),
2389 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2391 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2392 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2393 def RCR16m1 : I<0xD1, MRM3m, (outs i16mem:$dst), (ins i16mem:$src),
2394 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2395 let Uses = [CL] in {
2396 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2397 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2398 def RCR16mCL : I<0xD3, MRM3m, (outs i16mem:$dst), (ins i16mem:$src),
2399 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2401 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2402 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2403 def RCR16mi : Ii8<0xC1, MRM3m, (outs i16mem:$dst),
2404 (ins i16mem:$src, i8imm:$cnt),
2405 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2407 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2408 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2409 def RCR32m1 : I<0xD1, MRM3m, (outs i32mem:$dst), (ins i32mem:$src),
2410 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2411 let Uses = [CL] in {
2412 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2413 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2414 def RCR32mCL : I<0xD3, MRM3m, (outs i32mem:$dst), (ins i32mem:$src),
2415 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2417 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2418 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2419 def RCR32mi : Ii8<0xC1, MRM3m, (outs i32mem:$dst),
2420 (ins i32mem:$src, i8imm:$cnt),
2421 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2423 // FIXME: provide shorter instructions when imm8 == 1
2424 let Uses = [CL] in {
2425 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2426 "rol{b}\t{%cl, $dst|$dst, CL}",
2427 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2428 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2429 "rol{w}\t{%cl, $dst|$dst, CL}",
2430 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2431 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2432 "rol{l}\t{%cl, $dst|$dst, CL}",
2433 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2436 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2437 "rol{b}\t{$src2, $dst|$dst, $src2}",
2438 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2439 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2440 "rol{w}\t{$src2, $dst|$dst, $src2}",
2441 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2443 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2444 "rol{l}\t{$src2, $dst|$dst, $src2}",
2445 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2448 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2450 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2451 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2453 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2454 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2456 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2458 let isTwoAddress = 0 in {
2459 let Uses = [CL] in {
2460 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2461 "rol{b}\t{%cl, $dst|$dst, CL}",
2462 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2463 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2464 "rol{w}\t{%cl, $dst|$dst, CL}",
2465 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2466 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2467 "rol{l}\t{%cl, $dst|$dst, CL}",
2468 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2470 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2471 "rol{b}\t{$src, $dst|$dst, $src}",
2472 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2473 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2474 "rol{w}\t{$src, $dst|$dst, $src}",
2475 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2477 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2478 "rol{l}\t{$src, $dst|$dst, $src}",
2479 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2482 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2484 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2485 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2487 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2489 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2491 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2494 let Uses = [CL] in {
2495 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2496 "ror{b}\t{%cl, $dst|$dst, CL}",
2497 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2498 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2499 "ror{w}\t{%cl, $dst|$dst, CL}",
2500 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2501 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2502 "ror{l}\t{%cl, $dst|$dst, CL}",
2503 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2506 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2507 "ror{b}\t{$src2, $dst|$dst, $src2}",
2508 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2509 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2510 "ror{w}\t{$src2, $dst|$dst, $src2}",
2511 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2513 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2514 "ror{l}\t{$src2, $dst|$dst, $src2}",
2515 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2518 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2520 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2521 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2523 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2524 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2526 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2528 let isTwoAddress = 0 in {
2529 let Uses = [CL] in {
2530 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2531 "ror{b}\t{%cl, $dst|$dst, CL}",
2532 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2533 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2534 "ror{w}\t{%cl, $dst|$dst, CL}",
2535 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2536 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2537 "ror{l}\t{%cl, $dst|$dst, CL}",
2538 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2540 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2541 "ror{b}\t{$src, $dst|$dst, $src}",
2542 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2543 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2544 "ror{w}\t{$src, $dst|$dst, $src}",
2545 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2547 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2548 "ror{l}\t{$src, $dst|$dst, $src}",
2549 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2552 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2554 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2555 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2557 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2559 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2561 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2566 // Double shift instructions (generalizations of rotate)
2567 let Uses = [CL] in {
2568 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2569 (ins GR32:$src1, GR32:$src2),
2570 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2571 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2572 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2573 (ins GR32:$src1, GR32:$src2),
2574 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2575 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2576 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2577 (ins GR16:$src1, GR16:$src2),
2578 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2579 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2581 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2582 (ins GR16:$src1, GR16:$src2),
2583 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2584 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2588 let isCommutable = 1 in { // These instructions commute to each other.
2589 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2591 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2592 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2593 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2596 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2598 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2599 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2600 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2603 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2605 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2606 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2607 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2610 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2612 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2613 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2614 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2619 let isTwoAddress = 0 in {
2620 let Uses = [CL] in {
2621 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2622 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2623 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2625 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2626 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2627 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2630 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2631 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2632 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2633 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2634 (i8 imm:$src3)), addr:$dst)]>,
2636 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2637 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2638 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2639 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2640 (i8 imm:$src3)), addr:$dst)]>,
2643 let Uses = [CL] in {
2644 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2645 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2646 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2647 addr:$dst)]>, TB, OpSize;
2648 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2649 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2650 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2651 addr:$dst)]>, TB, OpSize;
2653 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2654 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2655 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2656 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2657 (i8 imm:$src3)), addr:$dst)]>,
2659 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2660 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2661 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2662 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2663 (i8 imm:$src3)), addr:$dst)]>,
2666 } // Defs = [EFLAGS]
2670 let Defs = [EFLAGS] in {
2671 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2672 // Register-Register Addition
2673 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2674 (ins GR8 :$src1, GR8 :$src2),
2675 "add{b}\t{$src2, $dst|$dst, $src2}",
2676 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2677 (implicit EFLAGS)]>;
2679 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2680 // Register-Register Addition
2681 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2682 (ins GR16:$src1, GR16:$src2),
2683 "add{w}\t{$src2, $dst|$dst, $src2}",
2684 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2685 (implicit EFLAGS)]>, OpSize;
2686 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2687 (ins GR32:$src1, GR32:$src2),
2688 "add{l}\t{$src2, $dst|$dst, $src2}",
2689 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2690 (implicit EFLAGS)]>;
2691 } // end isConvertibleToThreeAddress
2692 } // end isCommutable
2694 // Register-Memory Addition
2695 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2696 (ins GR8 :$src1, i8mem :$src2),
2697 "add{b}\t{$src2, $dst|$dst, $src2}",
2698 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2699 (implicit EFLAGS)]>;
2700 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2701 (ins GR16:$src1, i16mem:$src2),
2702 "add{w}\t{$src2, $dst|$dst, $src2}",
2703 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2704 (implicit EFLAGS)]>, OpSize;
2705 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2706 (ins GR32:$src1, i32mem:$src2),
2707 "add{l}\t{$src2, $dst|$dst, $src2}",
2708 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2709 (implicit EFLAGS)]>;
2711 // Register-Register Addition - Equivalent to the normal rr forms (ADD8rr,
2712 // ADD16rr, and ADD32rr), but differently encoded.
2713 def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2714 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2715 def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2716 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2717 def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2718 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2720 // Register-Integer Addition
2721 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2722 "add{b}\t{$src2, $dst|$dst, $src2}",
2723 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2724 (implicit EFLAGS)]>;
2726 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2727 // Register-Integer Addition
2728 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2729 (ins GR16:$src1, i16imm:$src2),
2730 "add{w}\t{$src2, $dst|$dst, $src2}",
2731 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2732 (implicit EFLAGS)]>, OpSize;
2733 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2734 (ins GR32:$src1, i32imm:$src2),
2735 "add{l}\t{$src2, $dst|$dst, $src2}",
2736 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2737 (implicit EFLAGS)]>;
2738 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2739 (ins GR16:$src1, i16i8imm:$src2),
2740 "add{w}\t{$src2, $dst|$dst, $src2}",
2741 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2742 (implicit EFLAGS)]>, OpSize;
2743 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2744 (ins GR32:$src1, i32i8imm:$src2),
2745 "add{l}\t{$src2, $dst|$dst, $src2}",
2746 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2747 (implicit EFLAGS)]>;
2750 let isTwoAddress = 0 in {
2751 // Memory-Register Addition
2752 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2753 "add{b}\t{$src2, $dst|$dst, $src2}",
2754 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2755 (implicit EFLAGS)]>;
2756 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2757 "add{w}\t{$src2, $dst|$dst, $src2}",
2758 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2759 (implicit EFLAGS)]>, OpSize;
2760 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2761 "add{l}\t{$src2, $dst|$dst, $src2}",
2762 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2763 (implicit EFLAGS)]>;
2764 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2765 "add{b}\t{$src2, $dst|$dst, $src2}",
2766 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2767 (implicit EFLAGS)]>;
2768 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2769 "add{w}\t{$src2, $dst|$dst, $src2}",
2770 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2771 (implicit EFLAGS)]>, OpSize;
2772 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2773 "add{l}\t{$src2, $dst|$dst, $src2}",
2774 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2775 (implicit EFLAGS)]>;
2776 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2777 "add{w}\t{$src2, $dst|$dst, $src2}",
2778 [(store (add (load addr:$dst), i16immSExt8:$src2),
2780 (implicit EFLAGS)]>, OpSize;
2781 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2782 "add{l}\t{$src2, $dst|$dst, $src2}",
2783 [(store (add (load addr:$dst), i32immSExt8:$src2),
2785 (implicit EFLAGS)]>;
2788 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2789 "add{b}\t{$src, %al|%al, $src}", []>;
2790 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2791 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2792 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2793 "add{l}\t{$src, %eax|%eax, $src}", []>;
2796 let Uses = [EFLAGS] in {
2797 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2798 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2799 "adc{b}\t{$src2, $dst|$dst, $src2}",
2800 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2801 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2802 (ins GR16:$src1, GR16:$src2),
2803 "adc{w}\t{$src2, $dst|$dst, $src2}",
2804 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2805 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2806 (ins GR32:$src1, GR32:$src2),
2807 "adc{l}\t{$src2, $dst|$dst, $src2}",
2808 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2811 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2812 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2813 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2814 (ins GR16:$src1, GR16:$src2),
2815 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2816 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2817 (ins GR32:$src1, GR32:$src2),
2818 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2820 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2821 (ins GR8:$src1, i8mem:$src2),
2822 "adc{b}\t{$src2, $dst|$dst, $src2}",
2823 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2824 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2825 (ins GR16:$src1, i16mem:$src2),
2826 "adc{w}\t{$src2, $dst|$dst, $src2}",
2827 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2829 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2830 (ins GR32:$src1, i32mem:$src2),
2831 "adc{l}\t{$src2, $dst|$dst, $src2}",
2832 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2833 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2834 "adc{b}\t{$src2, $dst|$dst, $src2}",
2835 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2836 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2837 (ins GR16:$src1, i16imm:$src2),
2838 "adc{w}\t{$src2, $dst|$dst, $src2}",
2839 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2840 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2841 (ins GR16:$src1, i16i8imm:$src2),
2842 "adc{w}\t{$src2, $dst|$dst, $src2}",
2843 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2845 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2846 (ins GR32:$src1, i32imm:$src2),
2847 "adc{l}\t{$src2, $dst|$dst, $src2}",
2848 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2849 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2850 (ins GR32:$src1, i32i8imm:$src2),
2851 "adc{l}\t{$src2, $dst|$dst, $src2}",
2852 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2854 let isTwoAddress = 0 in {
2855 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2856 "adc{b}\t{$src2, $dst|$dst, $src2}",
2857 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2858 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2859 "adc{w}\t{$src2, $dst|$dst, $src2}",
2860 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2862 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2863 "adc{l}\t{$src2, $dst|$dst, $src2}",
2864 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2865 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2866 "adc{b}\t{$src2, $dst|$dst, $src2}",
2867 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2868 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2869 "adc{w}\t{$src2, $dst|$dst, $src2}",
2870 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2872 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2873 "adc{w}\t{$src2, $dst|$dst, $src2}",
2874 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2876 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2877 "adc{l}\t{$src2, $dst|$dst, $src2}",
2878 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2879 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2880 "adc{l}\t{$src2, $dst|$dst, $src2}",
2881 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2883 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2884 "adc{b}\t{$src, %al|%al, $src}", []>;
2885 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2886 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2887 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2888 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2890 } // Uses = [EFLAGS]
2892 // Register-Register Subtraction
2893 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2894 "sub{b}\t{$src2, $dst|$dst, $src2}",
2895 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2896 (implicit EFLAGS)]>;
2897 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2898 "sub{w}\t{$src2, $dst|$dst, $src2}",
2899 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2900 (implicit EFLAGS)]>, OpSize;
2901 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2902 "sub{l}\t{$src2, $dst|$dst, $src2}",
2903 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2904 (implicit EFLAGS)]>;
2906 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2907 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2908 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2909 (ins GR16:$src1, GR16:$src2),
2910 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2911 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2912 (ins GR32:$src1, GR32:$src2),
2913 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2915 // Register-Memory Subtraction
2916 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2917 (ins GR8 :$src1, i8mem :$src2),
2918 "sub{b}\t{$src2, $dst|$dst, $src2}",
2919 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2920 (implicit EFLAGS)]>;
2921 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2922 (ins GR16:$src1, i16mem:$src2),
2923 "sub{w}\t{$src2, $dst|$dst, $src2}",
2924 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2925 (implicit EFLAGS)]>, OpSize;
2926 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2927 (ins GR32:$src1, i32mem:$src2),
2928 "sub{l}\t{$src2, $dst|$dst, $src2}",
2929 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2930 (implicit EFLAGS)]>;
2932 // Register-Integer Subtraction
2933 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2934 (ins GR8:$src1, i8imm:$src2),
2935 "sub{b}\t{$src2, $dst|$dst, $src2}",
2936 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2937 (implicit EFLAGS)]>;
2938 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2939 (ins GR16:$src1, i16imm:$src2),
2940 "sub{w}\t{$src2, $dst|$dst, $src2}",
2941 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2942 (implicit EFLAGS)]>, OpSize;
2943 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2944 (ins GR32:$src1, i32imm:$src2),
2945 "sub{l}\t{$src2, $dst|$dst, $src2}",
2946 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2947 (implicit EFLAGS)]>;
2948 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2949 (ins GR16:$src1, i16i8imm:$src2),
2950 "sub{w}\t{$src2, $dst|$dst, $src2}",
2951 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2952 (implicit EFLAGS)]>, OpSize;
2953 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2954 (ins GR32:$src1, i32i8imm:$src2),
2955 "sub{l}\t{$src2, $dst|$dst, $src2}",
2956 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2957 (implicit EFLAGS)]>;
2959 let isTwoAddress = 0 in {
2960 // Memory-Register Subtraction
2961 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2962 "sub{b}\t{$src2, $dst|$dst, $src2}",
2963 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2964 (implicit EFLAGS)]>;
2965 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2966 "sub{w}\t{$src2, $dst|$dst, $src2}",
2967 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2968 (implicit EFLAGS)]>, OpSize;
2969 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2970 "sub{l}\t{$src2, $dst|$dst, $src2}",
2971 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2972 (implicit EFLAGS)]>;
2974 // Memory-Integer Subtraction
2975 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2976 "sub{b}\t{$src2, $dst|$dst, $src2}",
2977 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2978 (implicit EFLAGS)]>;
2979 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2980 "sub{w}\t{$src2, $dst|$dst, $src2}",
2981 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2982 (implicit EFLAGS)]>, OpSize;
2983 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2984 "sub{l}\t{$src2, $dst|$dst, $src2}",
2985 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2986 (implicit EFLAGS)]>;
2987 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2988 "sub{w}\t{$src2, $dst|$dst, $src2}",
2989 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2991 (implicit EFLAGS)]>, OpSize;
2992 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2993 "sub{l}\t{$src2, $dst|$dst, $src2}",
2994 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2996 (implicit EFLAGS)]>;
2998 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
2999 "sub{b}\t{$src, %al|%al, $src}", []>;
3000 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
3001 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3002 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
3003 "sub{l}\t{$src, %eax|%eax, $src}", []>;
3006 let Uses = [EFLAGS] in {
3007 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
3008 (ins GR8:$src1, GR8:$src2),
3009 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3010 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
3011 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
3012 (ins GR16:$src1, GR16:$src2),
3013 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3014 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3015 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3016 (ins GR32:$src1, GR32:$src2),
3017 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3018 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3020 let isTwoAddress = 0 in {
3021 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3022 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3023 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3024 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3025 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3026 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3028 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3029 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3030 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3031 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3032 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3033 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3034 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3035 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3036 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3038 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3039 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3040 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3042 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3043 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3044 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3045 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3046 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3047 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3049 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3050 "sbb{b}\t{$src, %al|%al, $src}", []>;
3051 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3052 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3053 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3054 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3057 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3058 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3059 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3060 (ins GR16:$src1, GR16:$src2),
3061 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3062 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3063 (ins GR32:$src1, GR32:$src2),
3064 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3066 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3067 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3068 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3069 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3070 (ins GR16:$src1, i16mem:$src2),
3071 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3072 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3074 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3075 (ins GR32:$src1, i32mem:$src2),
3076 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3077 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3078 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3079 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3080 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3081 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3082 (ins GR16:$src1, i16imm:$src2),
3083 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3084 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3085 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3086 (ins GR16:$src1, i16i8imm:$src2),
3087 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3088 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3090 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3091 (ins GR32:$src1, i32imm:$src2),
3092 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3093 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3094 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3095 (ins GR32:$src1, i32i8imm:$src2),
3096 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3097 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3098 } // Uses = [EFLAGS]
3099 } // Defs = [EFLAGS]
3101 let Defs = [EFLAGS] in {
3102 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3103 // Register-Register Signed Integer Multiply
3104 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3105 "imul{w}\t{$src2, $dst|$dst, $src2}",
3106 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
3107 (implicit EFLAGS)]>, TB, OpSize;
3108 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3109 "imul{l}\t{$src2, $dst|$dst, $src2}",
3110 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
3111 (implicit EFLAGS)]>, TB;
3114 // Register-Memory Signed Integer Multiply
3115 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3116 (ins GR16:$src1, i16mem:$src2),
3117 "imul{w}\t{$src2, $dst|$dst, $src2}",
3118 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
3119 (implicit EFLAGS)]>, TB, OpSize;
3120 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3121 (ins GR32:$src1, i32mem:$src2),
3122 "imul{l}\t{$src2, $dst|$dst, $src2}",
3123 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
3124 (implicit EFLAGS)]>, TB;
3125 } // Defs = [EFLAGS]
3126 } // end Two Address instructions
3128 // Suprisingly enough, these are not two address instructions!
3129 let Defs = [EFLAGS] in {
3130 // Register-Integer Signed Integer Multiply
3131 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3132 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3133 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3134 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
3135 (implicit EFLAGS)]>, OpSize;
3136 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3137 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3138 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3139 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
3140 (implicit EFLAGS)]>;
3141 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3142 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3143 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3144 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
3145 (implicit EFLAGS)]>, OpSize;
3146 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3147 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3148 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3149 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
3150 (implicit EFLAGS)]>;
3152 // Memory-Integer Signed Integer Multiply
3153 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3154 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3155 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3156 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
3157 (implicit EFLAGS)]>, OpSize;
3158 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3159 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3160 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3161 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
3162 (implicit EFLAGS)]>;
3163 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3164 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3165 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3166 [(set GR16:$dst, (mul (load addr:$src1),
3167 i16immSExt8:$src2)),
3168 (implicit EFLAGS)]>, OpSize;
3169 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3170 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3171 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3172 [(set GR32:$dst, (mul (load addr:$src1),
3173 i32immSExt8:$src2)),
3174 (implicit EFLAGS)]>;
3175 } // Defs = [EFLAGS]
3177 //===----------------------------------------------------------------------===//
3178 // Test instructions are just like AND, except they don't generate a result.
3180 let Defs = [EFLAGS] in {
3181 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3182 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
3183 "test{b}\t{$src2, $src1|$src1, $src2}",
3184 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
3185 (implicit EFLAGS)]>;
3186 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3187 "test{w}\t{$src2, $src1|$src1, $src2}",
3188 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
3189 (implicit EFLAGS)]>,
3191 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3192 "test{l}\t{$src2, $src1|$src1, $src2}",
3193 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
3194 (implicit EFLAGS)]>;
3197 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3198 "test{b}\t{$src, %al|%al, $src}", []>;
3199 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3200 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3201 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3202 "test{l}\t{$src, %eax|%eax, $src}", []>;
3204 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3205 "test{b}\t{$src2, $src1|$src1, $src2}",
3206 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
3207 (implicit EFLAGS)]>;
3208 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3209 "test{w}\t{$src2, $src1|$src1, $src2}",
3210 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
3211 (implicit EFLAGS)]>, OpSize;
3212 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3213 "test{l}\t{$src2, $src1|$src1, $src2}",
3214 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
3215 (implicit EFLAGS)]>;
3217 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3218 (outs), (ins GR8:$src1, i8imm:$src2),
3219 "test{b}\t{$src2, $src1|$src1, $src2}",
3220 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
3221 (implicit EFLAGS)]>;
3222 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3223 (outs), (ins GR16:$src1, i16imm:$src2),
3224 "test{w}\t{$src2, $src1|$src1, $src2}",
3225 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
3226 (implicit EFLAGS)]>, OpSize;
3227 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3228 (outs), (ins GR32:$src1, i32imm:$src2),
3229 "test{l}\t{$src2, $src1|$src1, $src2}",
3230 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
3231 (implicit EFLAGS)]>;
3233 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3234 (outs), (ins i8mem:$src1, i8imm:$src2),
3235 "test{b}\t{$src2, $src1|$src1, $src2}",
3236 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
3237 (implicit EFLAGS)]>;
3238 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3239 (outs), (ins i16mem:$src1, i16imm:$src2),
3240 "test{w}\t{$src2, $src1|$src1, $src2}",
3241 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
3242 (implicit EFLAGS)]>, OpSize;
3243 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3244 (outs), (ins i32mem:$src1, i32imm:$src2),
3245 "test{l}\t{$src2, $src1|$src1, $src2}",
3246 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
3247 (implicit EFLAGS)]>;
3248 } // Defs = [EFLAGS]
3251 // Condition code ops, incl. set if equal/not equal/...
3252 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3253 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3254 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3255 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3257 let Uses = [EFLAGS] in {
3258 // Use sbb to materialize carry bit.
3260 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3261 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins),
3262 "sbb{b}\t$dst, $dst",
3263 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3264 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins),
3265 "sbb{w}\t$dst, $dst",
3266 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3268 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins),
3269 "sbb{l}\t$dst, $dst",
3270 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3273 def SETEr : I<0x94, MRM0r,
3274 (outs GR8 :$dst), (ins),
3276 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3278 def SETEm : I<0x94, MRM0m,
3279 (outs), (ins i8mem:$dst),
3281 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3284 def SETNEr : I<0x95, MRM0r,
3285 (outs GR8 :$dst), (ins),
3287 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3289 def SETNEm : I<0x95, MRM0m,
3290 (outs), (ins i8mem:$dst),
3292 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3295 def SETLr : I<0x9C, MRM0r,
3296 (outs GR8 :$dst), (ins),
3298 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3299 TB; // GR8 = < signed
3300 def SETLm : I<0x9C, MRM0m,
3301 (outs), (ins i8mem:$dst),
3303 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3304 TB; // [mem8] = < signed
3306 def SETGEr : I<0x9D, MRM0r,
3307 (outs GR8 :$dst), (ins),
3309 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3310 TB; // GR8 = >= signed
3311 def SETGEm : I<0x9D, MRM0m,
3312 (outs), (ins i8mem:$dst),
3314 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3315 TB; // [mem8] = >= signed
3317 def SETLEr : I<0x9E, MRM0r,
3318 (outs GR8 :$dst), (ins),
3320 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3321 TB; // GR8 = <= signed
3322 def SETLEm : I<0x9E, MRM0m,
3323 (outs), (ins i8mem:$dst),
3325 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3326 TB; // [mem8] = <= signed
3328 def SETGr : I<0x9F, MRM0r,
3329 (outs GR8 :$dst), (ins),
3331 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3332 TB; // GR8 = > signed
3333 def SETGm : I<0x9F, MRM0m,
3334 (outs), (ins i8mem:$dst),
3336 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3337 TB; // [mem8] = > signed
3339 def SETBr : I<0x92, MRM0r,
3340 (outs GR8 :$dst), (ins),
3342 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3343 TB; // GR8 = < unsign
3344 def SETBm : I<0x92, MRM0m,
3345 (outs), (ins i8mem:$dst),
3347 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3348 TB; // [mem8] = < unsign
3350 def SETAEr : I<0x93, MRM0r,
3351 (outs GR8 :$dst), (ins),
3353 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3354 TB; // GR8 = >= unsign
3355 def SETAEm : I<0x93, MRM0m,
3356 (outs), (ins i8mem:$dst),
3358 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3359 TB; // [mem8] = >= unsign
3361 def SETBEr : I<0x96, MRM0r,
3362 (outs GR8 :$dst), (ins),
3364 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3365 TB; // GR8 = <= unsign
3366 def SETBEm : I<0x96, MRM0m,
3367 (outs), (ins i8mem:$dst),
3369 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3370 TB; // [mem8] = <= unsign
3372 def SETAr : I<0x97, MRM0r,
3373 (outs GR8 :$dst), (ins),
3375 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3376 TB; // GR8 = > signed
3377 def SETAm : I<0x97, MRM0m,
3378 (outs), (ins i8mem:$dst),
3380 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3381 TB; // [mem8] = > signed
3383 def SETSr : I<0x98, MRM0r,
3384 (outs GR8 :$dst), (ins),
3386 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3387 TB; // GR8 = <sign bit>
3388 def SETSm : I<0x98, MRM0m,
3389 (outs), (ins i8mem:$dst),
3391 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3392 TB; // [mem8] = <sign bit>
3393 def SETNSr : I<0x99, MRM0r,
3394 (outs GR8 :$dst), (ins),
3396 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3397 TB; // GR8 = !<sign bit>
3398 def SETNSm : I<0x99, MRM0m,
3399 (outs), (ins i8mem:$dst),
3401 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3402 TB; // [mem8] = !<sign bit>
3404 def SETPr : I<0x9A, MRM0r,
3405 (outs GR8 :$dst), (ins),
3407 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3409 def SETPm : I<0x9A, MRM0m,
3410 (outs), (ins i8mem:$dst),
3412 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3413 TB; // [mem8] = parity
3414 def SETNPr : I<0x9B, MRM0r,
3415 (outs GR8 :$dst), (ins),
3417 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3418 TB; // GR8 = not parity
3419 def SETNPm : I<0x9B, MRM0m,
3420 (outs), (ins i8mem:$dst),
3422 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3423 TB; // [mem8] = not parity
3425 def SETOr : I<0x90, MRM0r,
3426 (outs GR8 :$dst), (ins),
3428 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3429 TB; // GR8 = overflow
3430 def SETOm : I<0x90, MRM0m,
3431 (outs), (ins i8mem:$dst),
3433 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3434 TB; // [mem8] = overflow
3435 def SETNOr : I<0x91, MRM0r,
3436 (outs GR8 :$dst), (ins),
3438 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3439 TB; // GR8 = not overflow
3440 def SETNOm : I<0x91, MRM0m,
3441 (outs), (ins i8mem:$dst),
3443 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3444 TB; // [mem8] = not overflow
3445 } // Uses = [EFLAGS]
3448 // Integer comparisons
3449 let Defs = [EFLAGS] in {
3450 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3451 "cmp{b}\t{$src, %al|%al, $src}", []>;
3452 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3453 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3454 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3455 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3457 def CMP8rr : I<0x38, MRMDestReg,
3458 (outs), (ins GR8 :$src1, GR8 :$src2),
3459 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3460 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
3461 def CMP16rr : I<0x39, MRMDestReg,
3462 (outs), (ins GR16:$src1, GR16:$src2),
3463 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3464 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
3465 def CMP32rr : I<0x39, MRMDestReg,
3466 (outs), (ins GR32:$src1, GR32:$src2),
3467 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3468 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
3469 def CMP8mr : I<0x38, MRMDestMem,
3470 (outs), (ins i8mem :$src1, GR8 :$src2),
3471 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3472 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
3473 (implicit EFLAGS)]>;
3474 def CMP16mr : I<0x39, MRMDestMem,
3475 (outs), (ins i16mem:$src1, GR16:$src2),
3476 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3477 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
3478 (implicit EFLAGS)]>, OpSize;
3479 def CMP32mr : I<0x39, MRMDestMem,
3480 (outs), (ins i32mem:$src1, GR32:$src2),
3481 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3482 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
3483 (implicit EFLAGS)]>;
3484 def CMP8rm : I<0x3A, MRMSrcMem,
3485 (outs), (ins GR8 :$src1, i8mem :$src2),
3486 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3487 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
3488 (implicit EFLAGS)]>;
3489 def CMP16rm : I<0x3B, MRMSrcMem,
3490 (outs), (ins GR16:$src1, i16mem:$src2),
3491 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3492 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
3493 (implicit EFLAGS)]>, OpSize;
3494 def CMP32rm : I<0x3B, MRMSrcMem,
3495 (outs), (ins GR32:$src1, i32mem:$src2),
3496 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3497 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
3498 (implicit EFLAGS)]>;
3499 def CMP8mrmrr : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3500 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3501 def CMP16mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3502 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3503 def CMP32mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3504 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3505 def CMP8ri : Ii8<0x80, MRM7r,
3506 (outs), (ins GR8:$src1, i8imm:$src2),
3507 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3508 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
3509 def CMP16ri : Ii16<0x81, MRM7r,
3510 (outs), (ins GR16:$src1, i16imm:$src2),
3511 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3512 [(X86cmp GR16:$src1, imm:$src2),
3513 (implicit EFLAGS)]>, OpSize;
3514 def CMP32ri : Ii32<0x81, MRM7r,
3515 (outs), (ins GR32:$src1, i32imm:$src2),
3516 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3517 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
3518 def CMP8mi : Ii8 <0x80, MRM7m,
3519 (outs), (ins i8mem :$src1, i8imm :$src2),
3520 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3521 [(X86cmp (loadi8 addr:$src1), imm:$src2),
3522 (implicit EFLAGS)]>;
3523 def CMP16mi : Ii16<0x81, MRM7m,
3524 (outs), (ins i16mem:$src1, i16imm:$src2),
3525 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3526 [(X86cmp (loadi16 addr:$src1), imm:$src2),
3527 (implicit EFLAGS)]>, OpSize;
3528 def CMP32mi : Ii32<0x81, MRM7m,
3529 (outs), (ins i32mem:$src1, i32imm:$src2),
3530 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3531 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3532 (implicit EFLAGS)]>;
3533 def CMP16ri8 : Ii8<0x83, MRM7r,
3534 (outs), (ins GR16:$src1, i16i8imm:$src2),
3535 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3536 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3537 (implicit EFLAGS)]>, OpSize;
3538 def CMP16mi8 : Ii8<0x83, MRM7m,
3539 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3540 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3541 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3542 (implicit EFLAGS)]>, OpSize;
3543 def CMP32mi8 : Ii8<0x83, MRM7m,
3544 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3545 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3546 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3547 (implicit EFLAGS)]>;
3548 def CMP32ri8 : Ii8<0x83, MRM7r,
3549 (outs), (ins GR32:$src1, i32i8imm:$src2),
3550 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3551 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3552 (implicit EFLAGS)]>;
3553 } // Defs = [EFLAGS]
3556 // TODO: BTC, BTR, and BTS
3557 let Defs = [EFLAGS] in {
3558 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3559 "bt{w}\t{$src2, $src1|$src1, $src2}",
3560 [(X86bt GR16:$src1, GR16:$src2),
3561 (implicit EFLAGS)]>, OpSize, TB;
3562 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3563 "bt{l}\t{$src2, $src1|$src1, $src2}",
3564 [(X86bt GR32:$src1, GR32:$src2),
3565 (implicit EFLAGS)]>, TB;
3567 // Unlike with the register+register form, the memory+register form of the
3568 // bt instruction does not ignore the high bits of the index. From ISel's
3569 // perspective, this is pretty bizarre. Make these instructions disassembly
3572 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3573 "bt{w}\t{$src2, $src1|$src1, $src2}",
3574 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3575 // (implicit EFLAGS)]
3577 >, OpSize, TB, Requires<[FastBTMem]>;
3578 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3579 "bt{l}\t{$src2, $src1|$src1, $src2}",
3580 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3581 // (implicit EFLAGS)]
3583 >, TB, Requires<[FastBTMem]>;
3585 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3586 "bt{w}\t{$src2, $src1|$src1, $src2}",
3587 [(X86bt GR16:$src1, i16immSExt8:$src2),
3588 (implicit EFLAGS)]>, OpSize, TB;
3589 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3590 "bt{l}\t{$src2, $src1|$src1, $src2}",
3591 [(X86bt GR32:$src1, i32immSExt8:$src2),
3592 (implicit EFLAGS)]>, TB;
3593 // Note that these instructions don't need FastBTMem because that
3594 // only applies when the other operand is in a register. When it's
3595 // an immediate, bt is still fast.
3596 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3597 "bt{w}\t{$src2, $src1|$src1, $src2}",
3598 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3599 (implicit EFLAGS)]>, OpSize, TB;
3600 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3601 "bt{l}\t{$src2, $src1|$src1, $src2}",
3602 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3603 (implicit EFLAGS)]>, TB;
3605 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3606 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3607 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3608 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3609 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3610 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3611 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3612 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3613 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3614 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3615 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3616 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3617 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3618 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3619 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3620 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3622 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3623 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3624 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3625 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3626 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3627 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3628 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3629 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3630 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3631 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3632 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3633 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3634 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3635 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3636 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3637 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3639 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3640 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3641 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3642 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3643 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3644 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3645 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3646 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3647 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3648 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3649 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3650 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3651 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3652 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3653 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3654 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3655 } // Defs = [EFLAGS]
3657 // Sign/Zero extenders
3658 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3659 // of the register here. This has a smaller encoding and avoids a
3660 // partial-register update. Actual movsbw included for the disassembler.
3661 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3662 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3663 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3664 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3665 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3666 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3667 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3668 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3669 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3670 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3671 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3672 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3673 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3674 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3675 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3676 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3677 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3678 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3679 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3680 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3682 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3683 // of the register here. This has a smaller encoding and avoids a
3684 // partial-register update. Actual movzbw included for the disassembler.
3685 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3686 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3687 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3688 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3689 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3690 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3691 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3692 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3693 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3694 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3695 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3696 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3697 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3698 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3699 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3700 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3701 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3702 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3703 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3704 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3706 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3707 // except that they use GR32_NOREX for the output operand register class
3708 // instead of GR32. This allows them to operate on h registers on x86-64.
3709 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3710 (outs GR32_NOREX:$dst), (ins GR8:$src),
3711 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3714 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3715 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3716 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3719 let neverHasSideEffects = 1 in {
3720 let Defs = [AX], Uses = [AL] in
3721 def CBW : I<0x98, RawFrm, (outs), (ins),
3722 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3723 let Defs = [EAX], Uses = [AX] in
3724 def CWDE : I<0x98, RawFrm, (outs), (ins),
3725 "{cwtl|cwde}", []>; // EAX = signext(AX)
3727 let Defs = [AX,DX], Uses = [AX] in
3728 def CWD : I<0x99, RawFrm, (outs), (ins),
3729 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3730 let Defs = [EAX,EDX], Uses = [EAX] in
3731 def CDQ : I<0x99, RawFrm, (outs), (ins),
3732 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3735 //===----------------------------------------------------------------------===//
3736 // Alias Instructions
3737 //===----------------------------------------------------------------------===//
3739 // Alias instructions that map movr0 to xor.
3740 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3741 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3742 isCodeGenOnly = 1 in {
3743 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3744 "xor{b}\t$dst, $dst",
3745 [(set GR8:$dst, 0)]>;
3747 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3748 // encoding and avoids a partial-register update sometimes, but doing so
3749 // at isel time interferes with rematerialization in the current register
3750 // allocator. For now, this is rewritten when the instruction is lowered
3752 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3754 [(set GR16:$dst, 0)]>, OpSize;
3756 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3757 "xor{l}\t$dst, $dst",
3758 [(set GR32:$dst, 0)]>;
3761 //===----------------------------------------------------------------------===//
3762 // Thread Local Storage Instructions
3765 // All calls clobber the non-callee saved registers. ESP is marked as
3766 // a use to prevent stack-pointer assignments that appear immediately
3767 // before calls from potentially appearing dead.
3768 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3769 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3770 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3771 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3773 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3774 "leal\t$sym, %eax; "
3775 "call\t___tls_get_addr@PLT",
3776 [(X86tlsaddr tls32addr:$sym)]>,
3777 Requires<[In32BitMode]>;
3779 let AddedComplexity = 5, isCodeGenOnly = 1 in
3780 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3781 "movl\t%gs:$src, $dst",
3782 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3784 let AddedComplexity = 5, isCodeGenOnly = 1 in
3785 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3786 "movl\t%fs:$src, $dst",
3787 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3789 //===----------------------------------------------------------------------===//
3790 // EH Pseudo Instructions
3792 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3793 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3794 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3795 "ret\t#eh_return, addr: $addr",
3796 [(X86ehret GR32:$addr)]>;
3800 //===----------------------------------------------------------------------===//
3804 // Atomic swap. These are just normal xchg instructions. But since a memory
3805 // operand is referenced, the atomicity is ensured.
3806 let Constraints = "$val = $dst" in {
3807 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3808 (ins GR32:$val, i32mem:$ptr),
3809 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3810 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3811 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3812 (ins GR16:$val, i16mem:$ptr),
3813 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3814 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3816 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3817 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3818 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3820 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3821 "xchg{l}\t{$val, $src|$src, $val}", []>;
3822 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3823 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3824 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3825 "xchg{b}\t{$val, $src|$src, $val}", []>;
3828 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3829 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3830 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3831 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3833 // Atomic compare and swap.
3834 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3835 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3837 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3838 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3840 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3841 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3844 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3847 let Defs = [AX, EFLAGS], Uses = [AX] in {
3848 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3850 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3851 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3853 let Defs = [AL, EFLAGS], Uses = [AL] in {
3854 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3856 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3857 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3860 // Atomic exchange and add
3861 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3862 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3864 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3865 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3867 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3869 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3870 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3872 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3874 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3875 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3879 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3880 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3881 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3882 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3883 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3884 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3886 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3887 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3888 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3889 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3890 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3891 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3893 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3894 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3895 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3896 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3897 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3898 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3900 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3901 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3902 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3903 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3904 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3905 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3907 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3908 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3909 "cmpxchg8b\t$dst", []>, TB;
3911 // Optimized codegen when the non-memory output is not used.
3912 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3913 let Defs = [EFLAGS] in {
3914 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3916 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3917 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3919 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3920 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3922 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3923 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3925 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3926 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3928 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3929 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3931 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3932 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3934 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3935 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3937 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3939 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3941 "inc{b}\t$dst", []>, LOCK;
3942 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3944 "inc{w}\t$dst", []>, OpSize, LOCK;
3945 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3947 "inc{l}\t$dst", []>, LOCK;
3949 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3951 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3952 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3954 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3955 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3957 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3958 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3960 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3961 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3963 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3964 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3966 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3967 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3969 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3970 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3972 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3974 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3976 "dec{b}\t$dst", []>, LOCK;
3977 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3979 "dec{w}\t$dst", []>, OpSize, LOCK;
3980 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3982 "dec{l}\t$dst", []>, LOCK;
3985 // Atomic exchange, and, or, xor
3986 let Constraints = "$val = $dst", Defs = [EFLAGS],
3987 usesCustomInserter = 1 in {
3988 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3989 "#ATOMAND32 PSEUDO!",
3990 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3991 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3992 "#ATOMOR32 PSEUDO!",
3993 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3994 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3995 "#ATOMXOR32 PSEUDO!",
3996 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3997 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3998 "#ATOMNAND32 PSEUDO!",
3999 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
4000 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
4001 "#ATOMMIN32 PSEUDO!",
4002 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
4003 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4004 "#ATOMMAX32 PSEUDO!",
4005 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
4006 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4007 "#ATOMUMIN32 PSEUDO!",
4008 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
4009 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4010 "#ATOMUMAX32 PSEUDO!",
4011 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
4013 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4014 "#ATOMAND16 PSEUDO!",
4015 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4016 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4017 "#ATOMOR16 PSEUDO!",
4018 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4019 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4020 "#ATOMXOR16 PSEUDO!",
4021 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4022 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4023 "#ATOMNAND16 PSEUDO!",
4024 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4025 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4026 "#ATOMMIN16 PSEUDO!",
4027 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4028 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4029 "#ATOMMAX16 PSEUDO!",
4030 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4031 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4032 "#ATOMUMIN16 PSEUDO!",
4033 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4034 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4035 "#ATOMUMAX16 PSEUDO!",
4036 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4038 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4039 "#ATOMAND8 PSEUDO!",
4040 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4041 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4043 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4044 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4045 "#ATOMXOR8 PSEUDO!",
4046 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4047 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4048 "#ATOMNAND8 PSEUDO!",
4049 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4052 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4053 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4054 Uses = [EAX, EBX, ECX, EDX],
4055 mayLoad = 1, mayStore = 1,
4056 usesCustomInserter = 1 in {
4057 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4058 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4059 "#ATOMAND6432 PSEUDO!", []>;
4060 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4061 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4062 "#ATOMOR6432 PSEUDO!", []>;
4063 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4064 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4065 "#ATOMXOR6432 PSEUDO!", []>;
4066 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4067 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4068 "#ATOMNAND6432 PSEUDO!", []>;
4069 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4070 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4071 "#ATOMADD6432 PSEUDO!", []>;
4072 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4073 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4074 "#ATOMSUB6432 PSEUDO!", []>;
4075 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4076 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4077 "#ATOMSWAP6432 PSEUDO!", []>;
4080 // Segmentation support instructions.
4082 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4083 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4084 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4085 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4087 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4088 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4089 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4090 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4091 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4093 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4094 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4095 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4096 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4097 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4098 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4099 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4100 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4102 def INVLPG : I<0x01, RawFrm, (outs), (ins), "invlpg", []>, TB;
4104 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4105 "str{w}\t{$dst}", []>, TB;
4106 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4107 "str{w}\t{$dst}", []>, TB;
4108 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4109 "ltr{w}\t{$src}", []>, TB;
4110 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4111 "ltr{w}\t{$src}", []>, TB;
4113 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4114 "push{w}\t%fs", []>, OpSize, TB;
4115 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4116 "push{l}\t%fs", []>, TB;
4117 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4118 "push{w}\t%gs", []>, OpSize, TB;
4119 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4120 "push{l}\t%gs", []>, TB;
4122 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4123 "pop{w}\t%fs", []>, OpSize, TB;
4124 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4125 "pop{l}\t%fs", []>, TB;
4126 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4127 "pop{w}\t%gs", []>, OpSize, TB;
4128 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4129 "pop{l}\t%gs", []>, TB;
4131 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4132 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4133 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4134 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4135 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4136 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4137 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4138 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4139 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4140 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4141 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4142 "les{l}\t{$src, $dst|$dst, $src}", []>;
4143 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4144 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4145 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4146 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4147 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4148 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4149 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4150 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4152 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4153 "verr\t$seg", []>, TB;
4154 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4155 "verr\t$seg", []>, TB;
4156 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4157 "verw\t$seg", []>, TB;
4158 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4159 "verw\t$seg", []>, TB;
4161 // Descriptor-table support instructions
4163 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4164 "sgdt\t$dst", []>, TB;
4165 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4166 "sidt\t$dst", []>, TB;
4167 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4168 "sldt{w}\t$dst", []>, TB;
4169 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4170 "sldt{w}\t$dst", []>, TB;
4171 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4172 "lgdt\t$src", []>, TB;
4173 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4174 "lidt\t$src", []>, TB;
4175 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4176 "lldt{w}\t$src", []>, TB;
4177 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4178 "lldt{w}\t$src", []>, TB;
4180 // Lock instruction prefix
4181 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4183 // Repeat string operation instruction prefixes
4184 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4185 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4186 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4187 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4188 // Repeat while not equal (used with CMPS and SCAS)
4189 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4192 // Segment override instruction prefixes
4193 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4194 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4195 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4196 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4197 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4198 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4200 // String manipulation instructions
4202 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4203 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4204 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4206 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4207 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4208 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4210 // CPU flow control instructions
4212 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4213 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4215 // FPU control instructions
4217 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4219 // Flag instructions
4221 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4222 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4223 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4224 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4225 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4226 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4227 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4229 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4231 // Table lookup instructions
4233 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4235 // Specialized register support
4237 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4238 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4239 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4241 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4242 "smsw{w}\t$dst", []>, OpSize, TB;
4243 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4244 "smsw{l}\t$dst", []>, TB;
4245 // For memory operands, there is only a 16-bit form
4246 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4247 "smsw{w}\t$dst", []>, TB;
4249 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4250 "lmsw{w}\t$src", []>, TB;
4251 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4252 "lmsw{w}\t$src", []>, TB;
4254 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4256 // Cache instructions
4258 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4259 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4264 def INVEPT : I<0x38, RawFrm, (outs), (ins), "invept", []>, OpSize, TB;
4266 def INVVPID : I<0x38, RawFrm, (outs), (ins), "invvpid", []>, OpSize, TB;
4268 def VMCALL : I<0x01, RawFrm, (outs), (ins), "vmcall", []>, TB;
4269 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4270 "vmclear\t$vmcs", []>, OpSize, TB;
4272 def VMLAUNCH : I<0x01, RawFrm, (outs), (ins), "vmlaunch", []>, TB;
4274 def VMRESUME : I<0x01, RawFrm, (outs), (ins), "vmresume", []>, TB;
4275 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4276 "vmptrld\t$vmcs", []>, TB;
4277 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4278 "vmptrst\t$vmcs", []>, TB;
4279 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4280 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4281 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4282 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4283 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4284 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4285 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4286 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4287 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4288 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4289 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4290 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4291 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4292 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4293 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4294 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4296 def VMXOFF : I<0x01, RawFrm, (outs), (ins), "vmxoff", []>, OpSize;
4297 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4298 "vmxon\t{$vmxon}", []>, XD;
4300 //===----------------------------------------------------------------------===//
4301 // Non-Instruction Patterns
4302 //===----------------------------------------------------------------------===//
4304 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4305 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4306 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4307 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4308 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4309 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4310 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4312 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4313 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4314 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4315 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4316 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4317 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4318 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4319 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4320 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4321 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4323 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4324 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4325 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4326 (MOV32mi addr:$dst, texternalsym:$src)>;
4327 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4328 (MOV32mi addr:$dst, tblockaddress:$src)>;
4332 def : Pat<(X86tcret GR32:$dst, imm:$off),
4333 (TCRETURNri GR32:$dst, imm:$off)>;
4335 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4336 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4338 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4339 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4341 // Normal calls, with various flavors of addresses.
4342 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4343 (CALLpcrel32 tglobaladdr:$dst)>;
4344 def : Pat<(X86call (i32 texternalsym:$dst)),
4345 (CALLpcrel32 texternalsym:$dst)>;
4346 def : Pat<(X86call (i32 imm:$dst)),
4347 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4349 // X86 specific add which produces a flag.
4350 def : Pat<(addc GR32:$src1, GR32:$src2),
4351 (ADD32rr GR32:$src1, GR32:$src2)>;
4352 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4353 (ADD32rm GR32:$src1, addr:$src2)>;
4354 def : Pat<(addc GR32:$src1, imm:$src2),
4355 (ADD32ri GR32:$src1, imm:$src2)>;
4356 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4357 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4359 def : Pat<(subc GR32:$src1, GR32:$src2),
4360 (SUB32rr GR32:$src1, GR32:$src2)>;
4361 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4362 (SUB32rm GR32:$src1, addr:$src2)>;
4363 def : Pat<(subc GR32:$src1, imm:$src2),
4364 (SUB32ri GR32:$src1, imm:$src2)>;
4365 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4366 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4370 // TEST R,R is smaller than CMP R,0
4371 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
4372 (TEST8rr GR8:$src1, GR8:$src1)>;
4373 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
4374 (TEST16rr GR16:$src1, GR16:$src1)>;
4375 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
4376 (TEST32rr GR32:$src1, GR32:$src1)>;
4378 // Conditional moves with folded loads with operands swapped and conditions
4380 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4381 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4382 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4383 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4384 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4385 (CMOVB16rm GR16:$src2, addr:$src1)>;
4386 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4387 (CMOVB32rm GR32:$src2, addr:$src1)>;
4388 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4389 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4390 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4391 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4392 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4393 (CMOVE16rm GR16:$src2, addr:$src1)>;
4394 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4395 (CMOVE32rm GR32:$src2, addr:$src1)>;
4396 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4397 (CMOVA16rm GR16:$src2, addr:$src1)>;
4398 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4399 (CMOVA32rm GR32:$src2, addr:$src1)>;
4400 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4401 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4402 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4403 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4404 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4405 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4406 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4407 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4408 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4409 (CMOVL16rm GR16:$src2, addr:$src1)>;
4410 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4411 (CMOVL32rm GR32:$src2, addr:$src1)>;
4412 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4413 (CMOVG16rm GR16:$src2, addr:$src1)>;
4414 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4415 (CMOVG32rm GR32:$src2, addr:$src1)>;
4416 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4417 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4418 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4419 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4420 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4421 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4422 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4423 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4424 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4425 (CMOVP16rm GR16:$src2, addr:$src1)>;
4426 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4427 (CMOVP32rm GR32:$src2, addr:$src1)>;
4428 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4429 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4430 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4431 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4432 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4433 (CMOVS16rm GR16:$src2, addr:$src1)>;
4434 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4435 (CMOVS32rm GR32:$src2, addr:$src1)>;
4436 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4437 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4438 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4439 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4440 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4441 (CMOVO16rm GR16:$src2, addr:$src1)>;
4442 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4443 (CMOVO32rm GR32:$src2, addr:$src1)>;
4445 // zextload bool -> zextload byte
4446 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4447 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4448 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4450 // extload bool -> extload byte
4451 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4452 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4453 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4454 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4455 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4456 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4458 // anyext. Define these to do an explicit zero-extend to
4459 // avoid partial-register updates.
4460 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4461 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4462 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
4464 // (and (i32 load), 255) -> (zextload i8)
4465 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
4466 (MOVZX32rm8 addr:$src)>;
4467 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
4468 (MOVZX32rm16 addr:$src)>;
4470 //===----------------------------------------------------------------------===//
4472 //===----------------------------------------------------------------------===//
4474 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4475 // +128 doesn't, so in this special case use a sub instead of an add.
4476 def : Pat<(add GR16:$src1, 128),
4477 (SUB16ri8 GR16:$src1, -128)>;
4478 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4479 (SUB16mi8 addr:$dst, -128)>;
4480 def : Pat<(add GR32:$src1, 128),
4481 (SUB32ri8 GR32:$src1, -128)>;
4482 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4483 (SUB32mi8 addr:$dst, -128)>;
4485 // r & (2^16-1) ==> movz
4486 def : Pat<(and GR32:$src1, 0xffff),
4487 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4488 // r & (2^8-1) ==> movz
4489 def : Pat<(and GR32:$src1, 0xff),
4490 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4493 Requires<[In32BitMode]>;
4494 // r & (2^8-1) ==> movz
4495 def : Pat<(and GR16:$src1, 0xff),
4496 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4499 Requires<[In32BitMode]>;
4501 // sext_inreg patterns
4502 def : Pat<(sext_inreg GR32:$src, i16),
4503 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4504 def : Pat<(sext_inreg GR32:$src, i8),
4505 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4508 Requires<[In32BitMode]>;
4509 def : Pat<(sext_inreg GR16:$src, i8),
4510 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4513 Requires<[In32BitMode]>;
4516 def : Pat<(i16 (trunc GR32:$src)),
4517 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4518 def : Pat<(i8 (trunc GR32:$src)),
4519 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4521 Requires<[In32BitMode]>;
4522 def : Pat<(i8 (trunc GR16:$src)),
4523 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4525 Requires<[In32BitMode]>;
4527 // h-register tricks
4528 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4529 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4530 x86_subreg_8bit_hi)>,
4531 Requires<[In32BitMode]>;
4532 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4533 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4534 x86_subreg_8bit_hi)>,
4535 Requires<[In32BitMode]>;
4536 def : Pat<(srl GR16:$src, (i8 8)),
4539 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4540 x86_subreg_8bit_hi)),
4542 Requires<[In32BitMode]>;
4543 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4544 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4546 x86_subreg_8bit_hi))>,
4547 Requires<[In32BitMode]>;
4548 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4549 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4551 x86_subreg_8bit_hi))>,
4552 Requires<[In32BitMode]>;
4553 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4554 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4556 x86_subreg_8bit_hi))>,
4557 Requires<[In32BitMode]>;
4559 // (shl x, 1) ==> (add x, x)
4560 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4561 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4562 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4564 // (shl x (and y, 31)) ==> (shl x, y)
4565 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
4566 (SHL8rCL GR8:$src1)>;
4567 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
4568 (SHL16rCL GR16:$src1)>;
4569 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
4570 (SHL32rCL GR32:$src1)>;
4571 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4572 (SHL8mCL addr:$dst)>;
4573 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4574 (SHL16mCL addr:$dst)>;
4575 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4576 (SHL32mCL addr:$dst)>;
4578 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
4579 (SHR8rCL GR8:$src1)>;
4580 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
4581 (SHR16rCL GR16:$src1)>;
4582 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
4583 (SHR32rCL GR32:$src1)>;
4584 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4585 (SHR8mCL addr:$dst)>;
4586 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4587 (SHR16mCL addr:$dst)>;
4588 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4589 (SHR32mCL addr:$dst)>;
4591 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
4592 (SAR8rCL GR8:$src1)>;
4593 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
4594 (SAR16rCL GR16:$src1)>;
4595 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
4596 (SAR32rCL GR32:$src1)>;
4597 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4598 (SAR8mCL addr:$dst)>;
4599 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4600 (SAR16mCL addr:$dst)>;
4601 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
4602 (SAR32mCL addr:$dst)>;
4604 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
4605 def : Pat<(or (srl GR32:$src1, CL:$amt),
4606 (shl GR32:$src2, (sub 32, CL:$amt))),
4607 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4609 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
4610 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4611 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4613 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
4614 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4615 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4617 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4618 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4620 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4622 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
4623 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4625 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
4626 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
4627 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4629 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
4630 def : Pat<(or (shl GR32:$src1, CL:$amt),
4631 (srl GR32:$src2, (sub 32, CL:$amt))),
4632 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4634 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
4635 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4636 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4638 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
4639 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4640 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4642 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4643 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4645 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4647 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
4648 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4650 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
4651 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
4652 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4654 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
4655 def : Pat<(or (srl GR16:$src1, CL:$amt),
4656 (shl GR16:$src2, (sub 16, CL:$amt))),
4657 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4659 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
4660 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4661 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4663 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
4664 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4665 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4667 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4668 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4670 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4672 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
4673 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4675 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
4676 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
4677 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4679 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
4680 def : Pat<(or (shl GR16:$src1, CL:$amt),
4681 (srl GR16:$src2, (sub 16, CL:$amt))),
4682 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4684 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
4685 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4686 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4688 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
4689 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4690 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4692 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4693 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4695 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4697 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
4698 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4700 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
4701 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
4702 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4704 // (anyext (setcc_carry)) -> (setcc_carry)
4705 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4707 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4710 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4711 let AddedComplexity = 5 in { // Try this before the selecting to OR
4712 def : Pat<(parallel (or_is_add GR16:$src1, imm:$src2),
4714 (ADD16ri GR16:$src1, imm:$src2)>;
4715 def : Pat<(parallel (or_is_add GR32:$src1, imm:$src2),
4717 (ADD32ri GR32:$src1, imm:$src2)>;
4718 def : Pat<(parallel (or_is_add GR16:$src1, i16immSExt8:$src2),
4720 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4721 def : Pat<(parallel (or_is_add GR32:$src1, i32immSExt8:$src2),
4723 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4724 def : Pat<(parallel (or_is_add GR16:$src1, GR16:$src2),
4726 (ADD16rr GR16:$src1, GR16:$src2)>;
4727 def : Pat<(parallel (or_is_add GR32:$src1, GR32:$src2),
4729 (ADD32rr GR32:$src1, GR32:$src2)>;
4730 } // AddedComplexity
4732 //===----------------------------------------------------------------------===//
4733 // EFLAGS-defining Patterns
4734 //===----------------------------------------------------------------------===//
4736 // Register-Register Addition with EFLAGS result
4737 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
4739 (ADD8rr GR8:$src1, GR8:$src2)>;
4740 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
4742 (ADD16rr GR16:$src1, GR16:$src2)>;
4743 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
4745 (ADD32rr GR32:$src1, GR32:$src2)>;
4747 // Register-Memory Addition with EFLAGS result
4748 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
4750 (ADD8rm GR8:$src1, addr:$src2)>;
4751 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
4753 (ADD16rm GR16:$src1, addr:$src2)>;
4754 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
4756 (ADD32rm GR32:$src1, addr:$src2)>;
4758 // Register-Integer Addition with EFLAGS result
4759 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
4761 (ADD8ri GR8:$src1, imm:$src2)>;
4762 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
4764 (ADD16ri GR16:$src1, imm:$src2)>;
4765 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
4767 (ADD32ri GR32:$src1, imm:$src2)>;
4768 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
4770 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4771 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
4773 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4775 // Memory-Register Addition with EFLAGS result
4776 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
4779 (ADD8mr addr:$dst, GR8:$src2)>;
4780 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
4783 (ADD16mr addr:$dst, GR16:$src2)>;
4784 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
4787 (ADD32mr addr:$dst, GR32:$src2)>;
4789 // Memory-Integer Addition with EFLAGS result
4790 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
4793 (ADD8mi addr:$dst, imm:$src2)>;
4794 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
4797 (ADD16mi addr:$dst, imm:$src2)>;
4798 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
4801 (ADD32mi addr:$dst, imm:$src2)>;
4802 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4805 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
4806 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4809 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
4811 // Register-Register Subtraction with EFLAGS result
4812 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
4814 (SUB8rr GR8:$src1, GR8:$src2)>;
4815 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
4817 (SUB16rr GR16:$src1, GR16:$src2)>;
4818 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
4820 (SUB32rr GR32:$src1, GR32:$src2)>;
4822 // Register-Memory Subtraction with EFLAGS result
4823 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
4825 (SUB8rm GR8:$src1, addr:$src2)>;
4826 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
4828 (SUB16rm GR16:$src1, addr:$src2)>;
4829 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
4831 (SUB32rm GR32:$src1, addr:$src2)>;
4833 // Register-Integer Subtraction with EFLAGS result
4834 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
4836 (SUB8ri GR8:$src1, imm:$src2)>;
4837 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
4839 (SUB16ri GR16:$src1, imm:$src2)>;
4840 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
4842 (SUB32ri GR32:$src1, imm:$src2)>;
4843 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
4845 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4846 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
4848 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4850 // Memory-Register Subtraction with EFLAGS result
4851 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
4854 (SUB8mr addr:$dst, GR8:$src2)>;
4855 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
4858 (SUB16mr addr:$dst, GR16:$src2)>;
4859 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
4862 (SUB32mr addr:$dst, GR32:$src2)>;
4864 // Memory-Integer Subtraction with EFLAGS result
4865 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
4868 (SUB8mi addr:$dst, imm:$src2)>;
4869 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
4872 (SUB16mi addr:$dst, imm:$src2)>;
4873 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4876 (SUB32mi addr:$dst, imm:$src2)>;
4877 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4880 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4881 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4884 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4887 // Register-Register Signed Integer Multiply with EFLAGS result
4888 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4890 (IMUL16rr GR16:$src1, GR16:$src2)>;
4891 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4893 (IMUL32rr GR32:$src1, GR32:$src2)>;
4895 // Register-Memory Signed Integer Multiply with EFLAGS result
4896 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4898 (IMUL16rm GR16:$src1, addr:$src2)>;
4899 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4901 (IMUL32rm GR32:$src1, addr:$src2)>;
4903 // Register-Integer Signed Integer Multiply with EFLAGS result
4904 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4906 (IMUL16rri GR16:$src1, imm:$src2)>;
4907 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4909 (IMUL32rri GR32:$src1, imm:$src2)>;
4910 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4912 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4913 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4915 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4917 // Memory-Integer Signed Integer Multiply with EFLAGS result
4918 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4920 (IMUL16rmi addr:$src1, imm:$src2)>;
4921 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4923 (IMUL32rmi addr:$src1, imm:$src2)>;
4924 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4926 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4927 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4929 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4931 // Optimize multiply by 2 with EFLAGS result.
4932 let AddedComplexity = 2 in {
4933 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4935 (ADD16rr GR16:$src1, GR16:$src1)>;
4937 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4939 (ADD32rr GR32:$src1, GR32:$src1)>;
4942 // INC and DEC with EFLAGS result. Note that these do not set CF.
4943 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4945 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4948 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4950 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4954 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4955 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4956 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4958 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4959 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4960 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4961 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4963 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4965 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4966 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4967 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4969 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4970 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4971 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4972 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4974 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4976 // Register-Register Or with EFLAGS result
4977 def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
4979 (OR8rr GR8:$src1, GR8:$src2)>;
4980 def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2),
4982 (OR16rr GR16:$src1, GR16:$src2)>;
4983 def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2),
4985 (OR32rr GR32:$src1, GR32:$src2)>;
4987 // Register-Memory Or with EFLAGS result
4988 def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)),
4990 (OR8rm GR8:$src1, addr:$src2)>;
4991 def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)),
4993 (OR16rm GR16:$src1, addr:$src2)>;
4994 def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)),
4996 (OR32rm GR32:$src1, addr:$src2)>;
4998 // Register-Integer Or with EFLAGS result
4999 def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2),
5001 (OR8ri GR8:$src1, imm:$src2)>;
5002 def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2),
5004 (OR16ri GR16:$src1, imm:$src2)>;
5005 def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2),
5007 (OR32ri GR32:$src1, imm:$src2)>;
5008 def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
5010 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
5011 def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
5013 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
5015 // Memory-Register Or with EFLAGS result
5016 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
5019 (OR8mr addr:$dst, GR8:$src2)>;
5020 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2),
5023 (OR16mr addr:$dst, GR16:$src2)>;
5024 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2),
5027 (OR32mr addr:$dst, GR32:$src2)>;
5029 // Memory-Integer Or with EFLAGS result
5030 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2),
5033 (OR8mi addr:$dst, imm:$src2)>;
5034 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2),
5037 (OR16mi addr:$dst, imm:$src2)>;
5038 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2),
5041 (OR32mi addr:$dst, imm:$src2)>;
5042 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5045 (OR16mi8 addr:$dst, i16immSExt8:$src2)>;
5046 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5049 (OR32mi8 addr:$dst, i32immSExt8:$src2)>;
5051 // Register-Register XOr with EFLAGS result
5052 def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
5054 (XOR8rr GR8:$src1, GR8:$src2)>;
5055 def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2),
5057 (XOR16rr GR16:$src1, GR16:$src2)>;
5058 def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2),
5060 (XOR32rr GR32:$src1, GR32:$src2)>;
5062 // Register-Memory XOr with EFLAGS result
5063 def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)),
5065 (XOR8rm GR8:$src1, addr:$src2)>;
5066 def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)),
5068 (XOR16rm GR16:$src1, addr:$src2)>;
5069 def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)),
5071 (XOR32rm GR32:$src1, addr:$src2)>;
5073 // Register-Integer XOr with EFLAGS result
5074 def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2),
5076 (XOR8ri GR8:$src1, imm:$src2)>;
5077 def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2),
5079 (XOR16ri GR16:$src1, imm:$src2)>;
5080 def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2),
5082 (XOR32ri GR32:$src1, imm:$src2)>;
5083 def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2),
5085 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
5086 def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
5088 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
5090 // Memory-Register XOr with EFLAGS result
5091 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
5094 (XOR8mr addr:$dst, GR8:$src2)>;
5095 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2),
5098 (XOR16mr addr:$dst, GR16:$src2)>;
5099 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2),
5102 (XOR32mr addr:$dst, GR32:$src2)>;
5104 // Memory-Integer XOr with EFLAGS result
5105 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2),
5108 (XOR8mi addr:$dst, imm:$src2)>;
5109 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2),
5112 (XOR16mi addr:$dst, imm:$src2)>;
5113 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2),
5116 (XOR32mi addr:$dst, imm:$src2)>;
5117 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5120 (XOR16mi8 addr:$dst, i16immSExt8:$src2)>;
5121 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5124 (XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
5126 // Register-Register And with EFLAGS result
5127 def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
5129 (AND8rr GR8:$src1, GR8:$src2)>;
5130 def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2),
5132 (AND16rr GR16:$src1, GR16:$src2)>;
5133 def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2),
5135 (AND32rr GR32:$src1, GR32:$src2)>;
5137 // Register-Memory And with EFLAGS result
5138 def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)),
5140 (AND8rm GR8:$src1, addr:$src2)>;
5141 def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)),
5143 (AND16rm GR16:$src1, addr:$src2)>;
5144 def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)),
5146 (AND32rm GR32:$src1, addr:$src2)>;
5148 // Register-Integer And with EFLAGS result
5149 def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2),
5151 (AND8ri GR8:$src1, imm:$src2)>;
5152 def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2),
5154 (AND16ri GR16:$src1, imm:$src2)>;
5155 def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2),
5157 (AND32ri GR32:$src1, imm:$src2)>;
5158 def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2),
5160 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
5161 def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
5163 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
5165 // Memory-Register And with EFLAGS result
5166 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
5169 (AND8mr addr:$dst, GR8:$src2)>;
5170 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2),
5173 (AND16mr addr:$dst, GR16:$src2)>;
5174 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2),
5177 (AND32mr addr:$dst, GR32:$src2)>;
5179 // Memory-Integer And with EFLAGS result
5180 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2),
5183 (AND8mi addr:$dst, imm:$src2)>;
5184 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2),
5187 (AND16mi addr:$dst, imm:$src2)>;
5188 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2),
5191 (AND32mi addr:$dst, imm:$src2)>;
5192 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5195 (AND16mi8 addr:$dst, i16immSExt8:$src2)>;
5196 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5199 (AND32mi8 addr:$dst, i32immSExt8:$src2)>;
5201 // -disable-16bit support.
5202 def : Pat<(truncstorei16 (i32 imm:$src), addr:$dst),
5203 (MOV16mi addr:$dst, imm:$src)>;
5204 def : Pat<(truncstorei16 GR32:$src, addr:$dst),
5205 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
5206 def : Pat<(i32 (sextloadi16 addr:$dst)),
5207 (MOVSX32rm16 addr:$dst)>;
5208 def : Pat<(i32 (zextloadi16 addr:$dst)),
5209 (MOVZX32rm16 addr:$dst)>;
5210 def : Pat<(i32 (extloadi16 addr:$dst)),
5211 (MOVZX32rm16 addr:$dst)>;
5213 //===----------------------------------------------------------------------===//
5214 // Floating Point Stack Support
5215 //===----------------------------------------------------------------------===//
5217 include "X86InstrFPStack.td"
5219 //===----------------------------------------------------------------------===//
5221 //===----------------------------------------------------------------------===//
5223 include "X86Instr64bit.td"
5225 //===----------------------------------------------------------------------===//
5226 // XMM Floating point support (requires SSE / SSE2)
5227 //===----------------------------------------------------------------------===//
5229 include "X86InstrSSE.td"
5231 //===----------------------------------------------------------------------===//
5232 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
5233 //===----------------------------------------------------------------------===//
5235 include "X86InstrMMX.td"