3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
44 def SDTX86SetCC_C : SDTypeProfile<1, 2,
46 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
48 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
50 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
52 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
53 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
54 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
56 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
57 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
60 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
62 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
66 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
68 def SDTX86Void : SDTypeProfile<0, 0, []>;
70 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
72 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
74 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
76 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
78 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
80 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
81 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
82 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
83 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
85 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
140 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
141 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
142 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
143 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
146 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
147 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
149 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
150 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
152 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
153 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
154 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
155 SDT_X86SegmentBaseAddress, []>;
157 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
160 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
161 [SDNPHasChain, SDNPOptInFlag]>;
163 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
165 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
166 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
168 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
170 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
171 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
172 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
174 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
176 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
179 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
181 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
182 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
184 //===----------------------------------------------------------------------===//
185 // X86 Operand Definitions.
188 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
189 // the index operand of an address, to conform to x86 encoding restrictions.
190 def ptr_rc_nosp : PointerLikeRegClass<1>;
192 // *mem - Operand definitions for the funky X86 addressing mode operands.
194 def X86MemAsmOperand : AsmOperandClass {
198 def X86AbsMemAsmOperand : AsmOperandClass {
200 let SuperClass = X86MemAsmOperand;
202 def X86NoSegMemAsmOperand : AsmOperandClass {
203 let Name = "NoSegMem";
204 let SuperClass = X86MemAsmOperand;
206 class X86MemOperand<string printMethod> : Operand<iPTR> {
207 let PrintMethod = printMethod;
208 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
209 let ParserMatchClass = X86MemAsmOperand;
212 def opaque32mem : X86MemOperand<"printopaquemem">;
213 def opaque48mem : X86MemOperand<"printopaquemem">;
214 def opaque80mem : X86MemOperand<"printopaquemem">;
215 def opaque512mem : X86MemOperand<"printopaquemem">;
217 def i8mem : X86MemOperand<"printi8mem">;
218 def i16mem : X86MemOperand<"printi16mem">;
219 def i32mem : X86MemOperand<"printi32mem">;
220 def i64mem : X86MemOperand<"printi64mem">;
221 def i128mem : X86MemOperand<"printi128mem">;
222 //def i256mem : X86MemOperand<"printi256mem">;
223 def f32mem : X86MemOperand<"printf32mem">;
224 def f64mem : X86MemOperand<"printf64mem">;
225 def f80mem : X86MemOperand<"printf80mem">;
226 def f128mem : X86MemOperand<"printf128mem">;
227 //def f256mem : X86MemOperand<"printf256mem">;
229 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
230 // plain GR64, so that it doesn't potentially require a REX prefix.
231 def i8mem_NOREX : Operand<i64> {
232 let PrintMethod = "printi8mem";
233 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
234 let ParserMatchClass = X86MemAsmOperand;
237 def lea32mem : Operand<i32> {
238 let PrintMethod = "printlea32mem";
239 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
240 let ParserMatchClass = X86NoSegMemAsmOperand;
243 let ParserMatchClass = X86AbsMemAsmOperand,
244 PrintMethod = "print_pcrel_imm" in {
245 def i32imm_pcrel : Operand<i32>;
247 def offset8 : Operand<i64>;
248 def offset16 : Operand<i64>;
249 def offset32 : Operand<i64>;
250 def offset64 : Operand<i64>;
252 // Branch targets have OtherVT type and print as pc-relative values.
253 def brtarget : Operand<OtherVT>;
254 def brtarget8 : Operand<OtherVT>;
258 def SSECC : Operand<i8> {
259 let PrintMethod = "printSSECC";
262 def ImmSExt8AsmOperand : AsmOperandClass {
263 let Name = "ImmSExt8";
264 let SuperClass = ImmAsmOperand;
267 // A couple of more descriptive operand definitions.
268 // 16-bits but only 8 bits are significant.
269 def i16i8imm : Operand<i16> {
270 let ParserMatchClass = ImmSExt8AsmOperand;
272 // 32-bits but only 8 bits are significant.
273 def i32i8imm : Operand<i32> {
274 let ParserMatchClass = ImmSExt8AsmOperand;
277 //===----------------------------------------------------------------------===//
278 // X86 Complex Pattern Definitions.
281 // Define X86 specific addressing mode.
282 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
283 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
284 [add, sub, mul, X86mul_imm, shl, or, frameindex],
286 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
287 [tglobaltlsaddr], []>;
289 //===----------------------------------------------------------------------===//
290 // X86 Instruction Predicate Definitions.
291 def HasMMX : Predicate<"Subtarget->hasMMX()">;
292 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
293 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
294 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
295 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
296 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
297 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
298 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
299 def HasAVX : Predicate<"Subtarget->hasAVX()">;
300 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
301 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
302 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
303 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
304 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
305 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
306 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
307 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
308 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
309 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
310 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
311 "TM.getCodeModel() != CodeModel::Kernel">;
312 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
313 "TM.getCodeModel() == CodeModel::Kernel">;
314 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
315 def OptForSize : Predicate<"OptForSize">;
316 def OptForSpeed : Predicate<"!OptForSize">;
317 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
318 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
320 //===----------------------------------------------------------------------===//
321 // X86 Instruction Format Definitions.
324 include "X86InstrFormats.td"
326 //===----------------------------------------------------------------------===//
327 // Pattern fragments...
330 // X86 specific condition code. These correspond to CondCode in
331 // X86InstrInfo.h. They must be kept in synch.
332 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
333 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
334 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
335 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
336 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
337 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
338 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
339 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
340 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
341 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
342 def X86_COND_NO : PatLeaf<(i8 10)>;
343 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
344 def X86_COND_NS : PatLeaf<(i8 12)>;
345 def X86_COND_O : PatLeaf<(i8 13)>;
346 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
347 def X86_COND_S : PatLeaf<(i8 15)>;
349 def immSext8 : PatLeaf<(imm), [{
350 return N->getSExtValue() == (int8_t)N->getSExtValue();
353 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
354 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
356 /// Load patterns: these constraint the match to the right address space.
357 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
358 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
359 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
360 if (PT->getAddressSpace() > 255)
365 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
366 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
367 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
368 return PT->getAddressSpace() == 256;
372 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
373 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
374 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
375 return PT->getAddressSpace() == 257;
380 // Helper fragments for loads.
381 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
382 // known to be 32-bit aligned or better. Ditto for i8 to i16.
383 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
384 LoadSDNode *LD = cast<LoadSDNode>(N);
385 if (const Value *Src = LD->getSrcValue())
386 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
387 if (PT->getAddressSpace() > 255)
389 ISD::LoadExtType ExtType = LD->getExtensionType();
390 if (ExtType == ISD::NON_EXTLOAD)
392 if (ExtType == ISD::EXTLOAD)
393 return LD->getAlignment() >= 2 && !LD->isVolatile();
397 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
398 LoadSDNode *LD = cast<LoadSDNode>(N);
399 if (const Value *Src = LD->getSrcValue())
400 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
401 if (PT->getAddressSpace() > 255)
403 ISD::LoadExtType ExtType = LD->getExtensionType();
404 if (ExtType == ISD::EXTLOAD)
405 return LD->getAlignment() >= 2 && !LD->isVolatile();
409 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
410 LoadSDNode *LD = cast<LoadSDNode>(N);
411 if (const Value *Src = LD->getSrcValue())
412 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
413 if (PT->getAddressSpace() > 255)
415 ISD::LoadExtType ExtType = LD->getExtensionType();
416 if (ExtType == ISD::NON_EXTLOAD)
418 if (ExtType == ISD::EXTLOAD)
419 return LD->getAlignment() >= 4 && !LD->isVolatile();
423 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
424 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
425 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
426 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
427 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
429 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
430 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
431 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
433 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
434 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
435 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
436 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
437 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
438 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
440 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
441 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
442 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
443 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
444 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
445 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
448 // An 'and' node with a single use.
449 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
450 return N->hasOneUse();
452 // An 'srl' node with a single use.
453 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
454 return N->hasOneUse();
456 // An 'trunc' node with a single use.
457 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
458 return N->hasOneUse();
461 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
462 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
463 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
464 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
466 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
467 APInt Mask = APInt::getAllOnesValue(BitWidth);
468 APInt KnownZero0, KnownOne0;
469 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
470 APInt KnownZero1, KnownOne1;
471 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
472 return (~KnownZero0 & ~KnownZero1) == 0;
476 // 'shld' and 'shrd' instruction patterns. Note that even though these have
477 // the srl and shl in their patterns, the C++ code must still check for them,
478 // because predicates are tested before children nodes are explored.
480 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
481 (or (srl node:$src1, node:$amt1),
482 (shl node:$src2, node:$amt2)), [{
483 assert(N->getOpcode() == ISD::OR);
484 return N->getOperand(0).getOpcode() == ISD::SRL &&
485 N->getOperand(1).getOpcode() == ISD::SHL &&
486 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
487 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
488 N->getOperand(0).getConstantOperandVal(1) ==
489 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
492 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
493 (or (shl node:$src1, node:$amt1),
494 (srl node:$src2, node:$amt2)), [{
495 assert(N->getOpcode() == ISD::OR);
496 return N->getOperand(0).getOpcode() == ISD::SHL &&
497 N->getOperand(1).getOpcode() == ISD::SRL &&
498 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
499 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
500 N->getOperand(0).getConstantOperandVal(1) ==
501 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
504 //===----------------------------------------------------------------------===//
505 // Instruction list...
508 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
509 // a stack adjustment and the codegen must know that they may modify the stack
510 // pointer before prolog-epilog rewriting occurs.
511 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
512 // sub / add which can clobber EFLAGS.
513 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
514 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
516 [(X86callseq_start timm:$amt)]>,
517 Requires<[In32BitMode]>;
518 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
520 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
521 Requires<[In32BitMode]>;
524 // x86-64 va_start lowering magic.
525 let usesCustomInserter = 1 in {
526 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
529 i64imm:$regsavefi, i64imm:$offset,
531 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
532 [(X86vastart_save_xmm_regs GR8:$al,
536 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
537 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
538 // one go. Touching the stack at 4K increments is necessary to ensure that the
539 // guard pages used by the OS virtual memory manager are allocated in correct
541 // The main point of having separate instruction are extra unmodelled effects
542 // (compared to ordinary calls) like stack pointer change.
544 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
545 "# dynamic stack allocation",
550 let neverHasSideEffects = 1 in {
551 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
552 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
553 "nop{w}\t$zero", []>, TB, OpSize;
554 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
555 "nop{l}\t$zero", []>, TB;
559 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int\t3", []>;
560 def INT : I<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
561 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
562 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
564 // PIC base construction. This expands to code that looks like this:
567 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
568 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
571 //===----------------------------------------------------------------------===//
572 // Control Flow Instructions.
575 // Return instructions.
576 let isTerminator = 1, isReturn = 1, isBarrier = 1,
577 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
578 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
581 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
583 [(X86retflag timm:$amt)]>;
584 def LRET : I <0xCB, RawFrm, (outs), (ins),
586 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
590 // Unconditional branches.
591 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
592 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
593 "jmp\t$dst", [(br bb:$dst)]>;
594 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
598 // Conditional Branches.
599 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
600 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
601 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
602 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
603 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
607 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
608 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
609 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
610 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
611 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
612 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
613 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
614 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
615 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
616 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
617 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
618 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
619 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
620 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
621 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
622 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
624 // FIXME: What about the CX/RCX versions of this instruction?
625 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
626 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
631 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
632 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
633 [(brind GR32:$dst)]>;
634 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
635 [(brind (loadi32 addr:$dst))]>;
637 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
638 (ins i16imm:$seg, i16imm:$off),
639 "ljmp{w}\t$seg, $off", []>, OpSize;
640 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
641 (ins i16imm:$seg, i32imm:$off),
642 "ljmp{l}\t$seg, $off", []>;
644 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
645 "ljmp{w}\t{*}$dst", []>, OpSize;
646 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
647 "ljmp{l}\t{*}$dst", []>;
653 def LOOP : I<0xE2, RawFrm, (ins brtarget8:$dst), (outs), "loop\t$dst", []>;
654 def LOOPE : I<0xE1, RawFrm, (ins brtarget8:$dst), (outs), "loope\t$dst", []>;
655 def LOOPNE : I<0xE0, RawFrm, (ins brtarget8:$dst), (outs), "loopne\t$dst", []>;
657 //===----------------------------------------------------------------------===//
658 // Call Instructions...
661 // All calls clobber the non-callee saved registers. ESP is marked as
662 // a use to prevent stack-pointer assignments that appear immediately
663 // before calls from potentially appearing dead. Uses for argument
664 // registers are added manually.
665 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
666 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
667 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
668 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
670 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
671 (outs), (ins i32imm_pcrel:$dst,variable_ops),
673 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
674 "call\t{*}$dst", [(X86call GR32:$dst)]>;
675 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
676 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
678 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
679 (ins i16imm:$seg, i16imm:$off),
680 "lcall{w}\t$seg, $off", []>, OpSize;
681 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
682 (ins i16imm:$seg, i32imm:$off),
683 "lcall{l}\t$seg, $off", []>;
685 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
686 "lcall{w}\t{*}$dst", []>, OpSize;
687 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
688 "lcall{l}\t{*}$dst", []>;
691 // Constructing a stack frame.
693 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
694 "enter\t$len, $lvl", []>;
698 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
699 def TCRETURNdi : I<0, Pseudo, (outs),
700 (ins i32imm:$dst, i32imm:$offset, variable_ops),
701 "#TC_RETURN $dst $offset",
704 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
705 def TCRETURNri : I<0, Pseudo, (outs),
706 (ins GR32:$dst, i32imm:$offset, variable_ops),
707 "#TC_RETURN $dst $offset",
710 // FIXME: The should be pseudo instructions that are lowered when going to
712 let isCall = 1, isBranch = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
713 def TAILJMPd : Ii32<0xE9, RawFrm, (outs),(ins i32imm_pcrel:$dst,variable_ops),
714 "jmp\t$dst # TAILCALL",
716 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
717 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst, variable_ops),
718 "jmp{l}\t{*}$dst # TAILCALL",
720 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
721 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst, variable_ops),
722 "jmp\t{*}$dst # TAILCALL", []>;
724 //===----------------------------------------------------------------------===//
725 // Miscellaneous Instructions...
727 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
728 def LEAVE : I<0xC9, RawFrm,
729 (outs), (ins), "leave", []>;
731 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
732 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
733 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
734 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
735 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
736 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
737 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
738 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
740 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
742 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
744 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
745 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
747 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
749 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
750 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
753 let mayStore = 1 in {
754 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
756 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
757 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
759 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
761 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
762 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
766 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
767 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
768 "push{l}\t$imm", []>;
769 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
770 "push{l}\t$imm", []>;
771 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
772 "push{l}\t$imm", []>;
775 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
776 def POPF : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
777 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf{l}", []>;
779 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
780 def PUSHF : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
781 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf{l}", []>;
784 let isTwoAddress = 1 in // GR32 = bswap GR32
785 def BSWAP32r : I<0xC8, AddRegFrm,
786 (outs GR32:$dst), (ins GR32:$src),
788 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
791 // Bit scan instructions.
792 let Defs = [EFLAGS] in {
793 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
794 "bsf{w}\t{$src, $dst|$dst, $src}",
795 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
796 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
797 "bsf{w}\t{$src, $dst|$dst, $src}",
798 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
799 (implicit EFLAGS)]>, TB;
800 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
801 "bsf{l}\t{$src, $dst|$dst, $src}",
802 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
803 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
804 "bsf{l}\t{$src, $dst|$dst, $src}",
805 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
806 (implicit EFLAGS)]>, TB;
808 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
809 "bsr{w}\t{$src, $dst|$dst, $src}",
810 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
811 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
812 "bsr{w}\t{$src, $dst|$dst, $src}",
813 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
814 (implicit EFLAGS)]>, TB;
815 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
816 "bsr{l}\t{$src, $dst|$dst, $src}",
817 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
818 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
819 "bsr{l}\t{$src, $dst|$dst, $src}",
820 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
821 (implicit EFLAGS)]>, TB;
824 let neverHasSideEffects = 1 in
825 def LEA16r : I<0x8D, MRMSrcMem,
826 (outs GR16:$dst), (ins lea32mem:$src),
827 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
828 let isReMaterializable = 1 in
829 def LEA32r : I<0x8D, MRMSrcMem,
830 (outs GR32:$dst), (ins lea32mem:$src),
831 "lea{l}\t{$src|$dst}, {$dst|$src}",
832 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
834 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
835 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
836 [(X86rep_movs i8)]>, REP;
837 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
838 [(X86rep_movs i16)]>, REP, OpSize;
839 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
840 [(X86rep_movs i32)]>, REP;
843 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
844 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
845 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
846 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
847 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
850 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
851 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
852 [(X86rep_stos i8)]>, REP;
853 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
854 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
855 [(X86rep_stos i16)]>, REP, OpSize;
856 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
857 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
858 [(X86rep_stos i32)]>, REP;
860 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
861 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
862 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
863 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
864 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
865 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
866 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
868 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
869 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
870 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
872 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
873 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
874 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
876 let Defs = [RAX, RDX] in
877 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
880 let Defs = [RAX, RCX, RDX] in
881 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
883 let isBarrier = 1, hasCtrlDep = 1 in {
884 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
887 def SYSCALL : I<0x05, RawFrm,
888 (outs), (ins), "syscall", []>, TB;
889 def SYSRET : I<0x07, RawFrm,
890 (outs), (ins), "sysret", []>, TB;
891 def SYSENTER : I<0x34, RawFrm,
892 (outs), (ins), "sysenter", []>, TB;
893 def SYSEXIT : I<0x35, RawFrm,
894 (outs), (ins), "sysexit", []>, TB;
896 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
899 //===----------------------------------------------------------------------===//
900 // Input/Output Instructions...
902 let Defs = [AL], Uses = [DX] in
903 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
904 "in{b}\t{%dx, %al|%AL, %DX}", []>;
905 let Defs = [AX], Uses = [DX] in
906 def IN16rr : I<0xED, RawFrm, (outs), (ins),
907 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
908 let Defs = [EAX], Uses = [DX] in
909 def IN32rr : I<0xED, RawFrm, (outs), (ins),
910 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
913 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
914 "in{b}\t{$port, %al|%AL, $port}", []>;
916 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
917 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
919 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
920 "in{l}\t{$port, %eax|%EAX, $port}", []>;
922 let Uses = [DX, AL] in
923 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
924 "out{b}\t{%al, %dx|%DX, %AL}", []>;
925 let Uses = [DX, AX] in
926 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
927 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
928 let Uses = [DX, EAX] in
929 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
930 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
933 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
934 "out{b}\t{%al, $port|$port, %AL}", []>;
936 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
937 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
939 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
940 "out{l}\t{%eax, $port|$port, %EAX}", []>;
942 def IN8 : I<0x6C, RawFrm, (outs), (ins),
944 def IN16 : I<0x6D, RawFrm, (outs), (ins),
945 "ins{w}", []>, OpSize;
946 def IN32 : I<0x6D, RawFrm, (outs), (ins),
949 //===----------------------------------------------------------------------===//
950 // Move Instructions...
952 let neverHasSideEffects = 1 in {
953 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
954 "mov{b}\t{$src, $dst|$dst, $src}", []>;
955 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
956 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
957 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
958 "mov{l}\t{$src, $dst|$dst, $src}", []>;
960 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
961 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
962 "mov{b}\t{$src, $dst|$dst, $src}",
963 [(set GR8:$dst, imm:$src)]>;
964 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
965 "mov{w}\t{$src, $dst|$dst, $src}",
966 [(set GR16:$dst, imm:$src)]>, OpSize;
967 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
968 "mov{l}\t{$src, $dst|$dst, $src}",
969 [(set GR32:$dst, imm:$src)]>;
972 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
973 "mov{b}\t{$src, $dst|$dst, $src}",
974 [(store (i8 imm:$src), addr:$dst)]>;
975 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
976 "mov{w}\t{$src, $dst|$dst, $src}",
977 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
978 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
979 "mov{l}\t{$src, $dst|$dst, $src}",
980 [(store (i32 imm:$src), addr:$dst)]>;
982 def MOV8o8a : Ii8 <0xA0, RawFrm, (outs), (ins offset8:$src),
983 "mov{b}\t{$src, %al|%al, $src}", []>;
984 def MOV16o16a : Ii16 <0xA1, RawFrm, (outs), (ins offset16:$src),
985 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
986 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
987 "mov{l}\t{$src, %eax|%eax, $src}", []>;
989 def MOV8ao8 : Ii8 <0xA2, RawFrm, (outs offset8:$dst), (ins),
990 "mov{b}\t{%al, $dst|$dst, %al}", []>;
991 def MOV16ao16 : Ii16 <0xA3, RawFrm, (outs offset16:$dst), (ins),
992 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
993 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
994 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
996 // Moves to and from segment registers
997 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
998 "mov{w}\t{$src, $dst|$dst, $src}", []>;
999 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1000 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1001 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1002 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1003 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1004 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1006 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1007 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1008 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1009 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1010 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1011 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1013 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1014 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1015 "mov{b}\t{$src, $dst|$dst, $src}",
1016 [(set GR8:$dst, (loadi8 addr:$src))]>;
1017 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1018 "mov{w}\t{$src, $dst|$dst, $src}",
1019 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1020 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1021 "mov{l}\t{$src, $dst|$dst, $src}",
1022 [(set GR32:$dst, (loadi32 addr:$src))]>;
1025 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1026 "mov{b}\t{$src, $dst|$dst, $src}",
1027 [(store GR8:$src, addr:$dst)]>;
1028 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1029 "mov{w}\t{$src, $dst|$dst, $src}",
1030 [(store GR16:$src, addr:$dst)]>, OpSize;
1031 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1032 "mov{l}\t{$src, $dst|$dst, $src}",
1033 [(store GR32:$src, addr:$dst)]>;
1035 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1036 // that they can be used for copying and storing h registers, which can't be
1037 // encoded when a REX prefix is present.
1038 let neverHasSideEffects = 1 in
1039 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1040 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1041 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1043 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1044 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1045 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1047 canFoldAsLoad = 1, isReMaterializable = 1 in
1048 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1049 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1050 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1052 // Moves to and from debug registers
1053 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1054 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1055 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1056 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1058 // Moves to and from control registers
1059 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG_32:$src),
1060 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1061 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG_32:$dst), (ins GR32:$src),
1062 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
1064 //===----------------------------------------------------------------------===//
1065 // Fixed-Register Multiplication and Division Instructions...
1068 // Extra precision multiplication
1070 // AL is really implied by AX, by the registers in Defs must match the
1071 // SDNode results (i8, i32).
1072 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1073 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1074 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1075 // This probably ought to be moved to a def : Pat<> if the
1076 // syntax can be accepted.
1077 [(set AL, (mul AL, GR8:$src)),
1078 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1080 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1081 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1083 []>, OpSize; // AX,DX = AX*GR16
1085 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1086 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1088 []>; // EAX,EDX = EAX*GR32
1090 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1091 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1093 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1094 // This probably ought to be moved to a def : Pat<> if the
1095 // syntax can be accepted.
1096 [(set AL, (mul AL, (loadi8 addr:$src))),
1097 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1099 let mayLoad = 1, neverHasSideEffects = 1 in {
1100 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1101 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1103 []>, OpSize; // AX,DX = AX*[mem16]
1105 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1106 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1108 []>; // EAX,EDX = EAX*[mem32]
1111 let neverHasSideEffects = 1 in {
1112 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1113 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1115 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1116 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1117 OpSize; // AX,DX = AX*GR16
1118 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1119 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1120 // EAX,EDX = EAX*GR32
1121 let mayLoad = 1 in {
1122 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1123 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1124 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1125 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1126 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1127 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1128 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1129 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1130 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1132 } // neverHasSideEffects
1134 // unsigned division/remainder
1135 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1136 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1137 "div{b}\t$src", []>;
1138 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1139 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1140 "div{w}\t$src", []>, OpSize;
1141 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1142 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1143 "div{l}\t$src", []>;
1144 let mayLoad = 1 in {
1145 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1146 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1147 "div{b}\t$src", []>;
1148 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1149 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1150 "div{w}\t$src", []>, OpSize;
1151 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1152 // EDX:EAX/[mem32] = EAX,EDX
1153 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1154 "div{l}\t$src", []>;
1157 // Signed division/remainder.
1158 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1159 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1160 "idiv{b}\t$src", []>;
1161 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1162 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1163 "idiv{w}\t$src", []>, OpSize;
1164 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1165 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1166 "idiv{l}\t$src", []>;
1167 let mayLoad = 1, mayLoad = 1 in {
1168 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1169 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1170 "idiv{b}\t$src", []>;
1171 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1172 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1173 "idiv{w}\t$src", []>, OpSize;
1174 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1175 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1176 // EDX:EAX/[mem32] = EAX,EDX
1177 "idiv{l}\t$src", []>;
1180 //===----------------------------------------------------------------------===//
1181 // Two address Instructions.
1183 let isTwoAddress = 1 in {
1185 // Conditional moves
1186 let Uses = [EFLAGS] in {
1188 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1189 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1190 // however that requires promoting the operands, and can induce additional
1191 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1192 // clobber EFLAGS, because if one of the operands is zero, the expansion
1193 // could involve an xor.
1194 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in
1195 def CMOV_GR8 : I<0, Pseudo,
1196 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1197 "#CMOV_GR8 PSEUDO!",
1198 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1199 imm:$cond, EFLAGS))]>;
1201 let isCommutable = 1 in {
1202 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1203 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1204 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1205 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1206 X86_COND_B, EFLAGS))]>,
1208 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1209 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1210 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1211 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1212 X86_COND_B, EFLAGS))]>,
1214 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1215 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1216 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1217 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1218 X86_COND_AE, EFLAGS))]>,
1220 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1221 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1222 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1223 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1224 X86_COND_AE, EFLAGS))]>,
1226 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1227 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1228 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1229 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1230 X86_COND_E, EFLAGS))]>,
1232 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1233 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1234 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1235 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1236 X86_COND_E, EFLAGS))]>,
1238 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1239 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1240 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1241 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1242 X86_COND_NE, EFLAGS))]>,
1244 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1245 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1246 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1247 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1248 X86_COND_NE, EFLAGS))]>,
1250 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1251 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1252 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1253 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1254 X86_COND_BE, EFLAGS))]>,
1256 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1257 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1258 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1259 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1260 X86_COND_BE, EFLAGS))]>,
1262 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1263 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1264 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1265 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1266 X86_COND_A, EFLAGS))]>,
1268 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1269 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1270 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1271 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1272 X86_COND_A, EFLAGS))]>,
1274 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1275 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1276 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1277 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1278 X86_COND_L, EFLAGS))]>,
1280 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1281 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1282 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1283 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1284 X86_COND_L, EFLAGS))]>,
1286 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1287 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1288 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1289 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1290 X86_COND_GE, EFLAGS))]>,
1292 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1293 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1294 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1295 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1296 X86_COND_GE, EFLAGS))]>,
1298 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1299 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1300 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1301 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1302 X86_COND_LE, EFLAGS))]>,
1304 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1305 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1306 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1307 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1308 X86_COND_LE, EFLAGS))]>,
1310 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1311 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1312 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1314 X86_COND_G, EFLAGS))]>,
1316 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1317 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1318 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1319 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1320 X86_COND_G, EFLAGS))]>,
1322 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1323 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1324 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1325 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1326 X86_COND_S, EFLAGS))]>,
1328 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1329 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1330 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1331 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1332 X86_COND_S, EFLAGS))]>,
1334 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1335 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1336 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1337 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1338 X86_COND_NS, EFLAGS))]>,
1340 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1341 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1342 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1343 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1344 X86_COND_NS, EFLAGS))]>,
1346 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1347 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1348 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1349 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1350 X86_COND_P, EFLAGS))]>,
1352 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1353 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1354 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1355 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1356 X86_COND_P, EFLAGS))]>,
1358 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1359 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1360 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1361 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1362 X86_COND_NP, EFLAGS))]>,
1364 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1365 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1366 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1367 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1368 X86_COND_NP, EFLAGS))]>,
1370 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1371 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1372 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1373 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1374 X86_COND_O, EFLAGS))]>,
1376 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1377 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1378 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1379 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1380 X86_COND_O, EFLAGS))]>,
1382 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1383 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1384 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1385 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1386 X86_COND_NO, EFLAGS))]>,
1388 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1389 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1390 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1391 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1392 X86_COND_NO, EFLAGS))]>,
1394 } // isCommutable = 1
1396 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1397 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1398 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1399 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1400 X86_COND_B, EFLAGS))]>,
1402 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1403 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1404 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1405 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1406 X86_COND_B, EFLAGS))]>,
1408 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1409 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1410 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1411 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1412 X86_COND_AE, EFLAGS))]>,
1414 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1415 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1416 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1417 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1418 X86_COND_AE, EFLAGS))]>,
1420 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1421 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1422 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1423 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1424 X86_COND_E, EFLAGS))]>,
1426 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1427 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1428 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1429 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1430 X86_COND_E, EFLAGS))]>,
1432 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1433 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1434 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1435 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1436 X86_COND_NE, EFLAGS))]>,
1438 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1439 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1440 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1441 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1442 X86_COND_NE, EFLAGS))]>,
1444 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1445 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1446 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1447 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1448 X86_COND_BE, EFLAGS))]>,
1450 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1451 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1452 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1453 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1454 X86_COND_BE, EFLAGS))]>,
1456 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1457 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1458 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1459 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1460 X86_COND_A, EFLAGS))]>,
1462 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1463 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1464 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1465 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1466 X86_COND_A, EFLAGS))]>,
1468 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1469 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1470 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1471 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1472 X86_COND_L, EFLAGS))]>,
1474 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1475 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1476 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1477 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1478 X86_COND_L, EFLAGS))]>,
1480 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1481 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1482 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1483 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1484 X86_COND_GE, EFLAGS))]>,
1486 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1487 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1488 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1489 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1490 X86_COND_GE, EFLAGS))]>,
1492 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1493 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1494 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1495 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1496 X86_COND_LE, EFLAGS))]>,
1498 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1499 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1500 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1501 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1502 X86_COND_LE, EFLAGS))]>,
1504 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1505 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1506 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1507 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1508 X86_COND_G, EFLAGS))]>,
1510 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1511 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1512 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1513 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1514 X86_COND_G, EFLAGS))]>,
1516 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1517 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1518 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1519 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1520 X86_COND_S, EFLAGS))]>,
1522 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1523 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1524 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1525 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1526 X86_COND_S, EFLAGS))]>,
1528 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1529 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1530 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1531 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1532 X86_COND_NS, EFLAGS))]>,
1534 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1535 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1536 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1537 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1538 X86_COND_NS, EFLAGS))]>,
1540 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1541 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1542 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1543 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1544 X86_COND_P, EFLAGS))]>,
1546 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1547 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1548 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1549 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1550 X86_COND_P, EFLAGS))]>,
1552 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1553 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1554 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1555 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1556 X86_COND_NP, EFLAGS))]>,
1558 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1559 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1560 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1561 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1562 X86_COND_NP, EFLAGS))]>,
1564 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1565 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1566 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1567 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1568 X86_COND_O, EFLAGS))]>,
1570 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1571 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1572 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1573 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1574 X86_COND_O, EFLAGS))]>,
1576 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1577 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1578 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1579 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1580 X86_COND_NO, EFLAGS))]>,
1582 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1583 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1584 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1585 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1586 X86_COND_NO, EFLAGS))]>,
1588 } // Uses = [EFLAGS]
1591 // unary instructions
1592 let CodeSize = 2 in {
1593 let Defs = [EFLAGS] in {
1594 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1595 [(set GR8:$dst, (ineg GR8:$src)),
1596 (implicit EFLAGS)]>;
1597 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1598 [(set GR16:$dst, (ineg GR16:$src)),
1599 (implicit EFLAGS)]>, OpSize;
1600 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1601 [(set GR32:$dst, (ineg GR32:$src)),
1602 (implicit EFLAGS)]>;
1603 let isTwoAddress = 0 in {
1604 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1605 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1606 (implicit EFLAGS)]>;
1607 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1608 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1609 (implicit EFLAGS)]>, OpSize;
1610 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1611 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1612 (implicit EFLAGS)]>;
1614 } // Defs = [EFLAGS]
1616 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1617 let AddedComplexity = 15 in {
1618 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1619 [(set GR8:$dst, (not GR8:$src))]>;
1620 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1621 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1622 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1623 [(set GR32:$dst, (not GR32:$src))]>;
1625 let isTwoAddress = 0 in {
1626 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1627 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1628 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1629 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1630 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1631 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1635 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1636 let Defs = [EFLAGS] in {
1638 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1639 [(set GR8:$dst, (add GR8:$src, 1)),
1640 (implicit EFLAGS)]>;
1641 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1642 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1644 [(set GR16:$dst, (add GR16:$src, 1)),
1645 (implicit EFLAGS)]>,
1646 OpSize, Requires<[In32BitMode]>;
1647 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1649 [(set GR32:$dst, (add GR32:$src, 1)),
1650 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1652 let isTwoAddress = 0, CodeSize = 2 in {
1653 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1654 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1655 (implicit EFLAGS)]>;
1656 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1657 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1658 (implicit EFLAGS)]>,
1659 OpSize, Requires<[In32BitMode]>;
1660 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1661 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1662 (implicit EFLAGS)]>,
1663 Requires<[In32BitMode]>;
1667 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1668 [(set GR8:$dst, (add GR8:$src, -1)),
1669 (implicit EFLAGS)]>;
1670 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1671 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1673 [(set GR16:$dst, (add GR16:$src, -1)),
1674 (implicit EFLAGS)]>,
1675 OpSize, Requires<[In32BitMode]>;
1676 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1678 [(set GR32:$dst, (add GR32:$src, -1)),
1679 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1682 let isTwoAddress = 0, CodeSize = 2 in {
1683 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1684 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1685 (implicit EFLAGS)]>;
1686 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1687 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1688 (implicit EFLAGS)]>,
1689 OpSize, Requires<[In32BitMode]>;
1690 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1691 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1692 (implicit EFLAGS)]>,
1693 Requires<[In32BitMode]>;
1695 } // Defs = [EFLAGS]
1697 // Logical operators...
1698 let Defs = [EFLAGS] in {
1699 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1700 def AND8rr : I<0x20, MRMDestReg,
1701 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1702 "and{b}\t{$src2, $dst|$dst, $src2}",
1703 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1704 (implicit EFLAGS)]>;
1705 def AND16rr : I<0x21, MRMDestReg,
1706 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1707 "and{w}\t{$src2, $dst|$dst, $src2}",
1708 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1709 (implicit EFLAGS)]>, OpSize;
1710 def AND32rr : I<0x21, MRMDestReg,
1711 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1712 "and{l}\t{$src2, $dst|$dst, $src2}",
1713 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1714 (implicit EFLAGS)]>;
1717 // AND instructions with the destination register in REG and the source register
1718 // in R/M. Included for the disassembler.
1719 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1720 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1721 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1722 (ins GR16:$src1, GR16:$src2),
1723 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1724 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1725 (ins GR32:$src1, GR32:$src2),
1726 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1728 def AND8rm : I<0x22, MRMSrcMem,
1729 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1730 "and{b}\t{$src2, $dst|$dst, $src2}",
1731 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1732 (implicit EFLAGS)]>;
1733 def AND16rm : I<0x23, MRMSrcMem,
1734 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1735 "and{w}\t{$src2, $dst|$dst, $src2}",
1736 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1737 (implicit EFLAGS)]>, OpSize;
1738 def AND32rm : I<0x23, MRMSrcMem,
1739 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1740 "and{l}\t{$src2, $dst|$dst, $src2}",
1741 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1742 (implicit EFLAGS)]>;
1744 def AND8ri : Ii8<0x80, MRM4r,
1745 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1746 "and{b}\t{$src2, $dst|$dst, $src2}",
1747 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1748 (implicit EFLAGS)]>;
1749 def AND16ri : Ii16<0x81, MRM4r,
1750 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1751 "and{w}\t{$src2, $dst|$dst, $src2}",
1752 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1753 (implicit EFLAGS)]>, OpSize;
1754 def AND32ri : Ii32<0x81, MRM4r,
1755 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1756 "and{l}\t{$src2, $dst|$dst, $src2}",
1757 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1758 (implicit EFLAGS)]>;
1759 def AND16ri8 : Ii8<0x83, MRM4r,
1760 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1761 "and{w}\t{$src2, $dst|$dst, $src2}",
1762 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1763 (implicit EFLAGS)]>,
1765 def AND32ri8 : Ii8<0x83, MRM4r,
1766 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1767 "and{l}\t{$src2, $dst|$dst, $src2}",
1768 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1769 (implicit EFLAGS)]>;
1771 let isTwoAddress = 0 in {
1772 def AND8mr : I<0x20, MRMDestMem,
1773 (outs), (ins i8mem :$dst, GR8 :$src),
1774 "and{b}\t{$src, $dst|$dst, $src}",
1775 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1776 (implicit EFLAGS)]>;
1777 def AND16mr : I<0x21, MRMDestMem,
1778 (outs), (ins i16mem:$dst, GR16:$src),
1779 "and{w}\t{$src, $dst|$dst, $src}",
1780 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1781 (implicit EFLAGS)]>,
1783 def AND32mr : I<0x21, MRMDestMem,
1784 (outs), (ins i32mem:$dst, GR32:$src),
1785 "and{l}\t{$src, $dst|$dst, $src}",
1786 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1787 (implicit EFLAGS)]>;
1788 def AND8mi : Ii8<0x80, MRM4m,
1789 (outs), (ins i8mem :$dst, i8imm :$src),
1790 "and{b}\t{$src, $dst|$dst, $src}",
1791 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1792 (implicit EFLAGS)]>;
1793 def AND16mi : Ii16<0x81, MRM4m,
1794 (outs), (ins i16mem:$dst, i16imm:$src),
1795 "and{w}\t{$src, $dst|$dst, $src}",
1796 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1797 (implicit EFLAGS)]>,
1799 def AND32mi : Ii32<0x81, MRM4m,
1800 (outs), (ins i32mem:$dst, i32imm:$src),
1801 "and{l}\t{$src, $dst|$dst, $src}",
1802 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1803 (implicit EFLAGS)]>;
1804 def AND16mi8 : Ii8<0x83, MRM4m,
1805 (outs), (ins i16mem:$dst, i16i8imm :$src),
1806 "and{w}\t{$src, $dst|$dst, $src}",
1807 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1808 (implicit EFLAGS)]>,
1810 def AND32mi8 : Ii8<0x83, MRM4m,
1811 (outs), (ins i32mem:$dst, i32i8imm :$src),
1812 "and{l}\t{$src, $dst|$dst, $src}",
1813 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1814 (implicit EFLAGS)]>;
1816 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1817 "and{b}\t{$src, %al|%al, $src}", []>;
1818 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1819 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1820 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1821 "and{l}\t{$src, %eax|%eax, $src}", []>;
1826 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1827 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1828 (ins GR8 :$src1, GR8 :$src2),
1829 "or{b}\t{$src2, $dst|$dst, $src2}",
1830 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1831 (implicit EFLAGS)]>;
1832 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1833 (ins GR16:$src1, GR16:$src2),
1834 "or{w}\t{$src2, $dst|$dst, $src2}",
1835 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1836 (implicit EFLAGS)]>, OpSize;
1837 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1838 (ins GR32:$src1, GR32:$src2),
1839 "or{l}\t{$src2, $dst|$dst, $src2}",
1840 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1841 (implicit EFLAGS)]>;
1844 // OR instructions with the destination register in REG and the source register
1845 // in R/M. Included for the disassembler.
1846 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1847 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1848 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1849 (ins GR16:$src1, GR16:$src2),
1850 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1851 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1852 (ins GR32:$src1, GR32:$src2),
1853 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1855 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst),
1856 (ins GR8 :$src1, i8mem :$src2),
1857 "or{b}\t{$src2, $dst|$dst, $src2}",
1858 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1859 (implicit EFLAGS)]>;
1860 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst),
1861 (ins GR16:$src1, i16mem:$src2),
1862 "or{w}\t{$src2, $dst|$dst, $src2}",
1863 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1864 (implicit EFLAGS)]>, OpSize;
1865 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst),
1866 (ins GR32:$src1, i32mem:$src2),
1867 "or{l}\t{$src2, $dst|$dst, $src2}",
1868 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1869 (implicit EFLAGS)]>;
1871 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1872 (ins GR8 :$src1, i8imm:$src2),
1873 "or{b}\t{$src2, $dst|$dst, $src2}",
1874 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1875 (implicit EFLAGS)]>;
1876 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1877 (ins GR16:$src1, i16imm:$src2),
1878 "or{w}\t{$src2, $dst|$dst, $src2}",
1879 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1880 (implicit EFLAGS)]>, OpSize;
1881 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1882 (ins GR32:$src1, i32imm:$src2),
1883 "or{l}\t{$src2, $dst|$dst, $src2}",
1884 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1885 (implicit EFLAGS)]>;
1887 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1888 (ins GR16:$src1, i16i8imm:$src2),
1889 "or{w}\t{$src2, $dst|$dst, $src2}",
1890 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1891 (implicit EFLAGS)]>, OpSize;
1892 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1893 (ins GR32:$src1, i32i8imm:$src2),
1894 "or{l}\t{$src2, $dst|$dst, $src2}",
1895 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1896 (implicit EFLAGS)]>;
1897 let isTwoAddress = 0 in {
1898 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1899 "or{b}\t{$src, $dst|$dst, $src}",
1900 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1901 (implicit EFLAGS)]>;
1902 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1903 "or{w}\t{$src, $dst|$dst, $src}",
1904 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1905 (implicit EFLAGS)]>, OpSize;
1906 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1907 "or{l}\t{$src, $dst|$dst, $src}",
1908 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1909 (implicit EFLAGS)]>;
1910 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1911 "or{b}\t{$src, $dst|$dst, $src}",
1912 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1913 (implicit EFLAGS)]>;
1914 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1915 "or{w}\t{$src, $dst|$dst, $src}",
1916 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1917 (implicit EFLAGS)]>,
1919 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1920 "or{l}\t{$src, $dst|$dst, $src}",
1921 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1922 (implicit EFLAGS)]>;
1923 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1924 "or{w}\t{$src, $dst|$dst, $src}",
1925 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1926 (implicit EFLAGS)]>,
1928 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1929 "or{l}\t{$src, $dst|$dst, $src}",
1930 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1931 (implicit EFLAGS)]>;
1933 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1934 "or{b}\t{$src, %al|%al, $src}", []>;
1935 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1936 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1937 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1938 "or{l}\t{$src, %eax|%eax, $src}", []>;
1939 } // isTwoAddress = 0
1942 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1943 def XOR8rr : I<0x30, MRMDestReg,
1944 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1945 "xor{b}\t{$src2, $dst|$dst, $src2}",
1946 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1947 (implicit EFLAGS)]>;
1948 def XOR16rr : I<0x31, MRMDestReg,
1949 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1950 "xor{w}\t{$src2, $dst|$dst, $src2}",
1951 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1952 (implicit EFLAGS)]>, OpSize;
1953 def XOR32rr : I<0x31, MRMDestReg,
1954 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1955 "xor{l}\t{$src2, $dst|$dst, $src2}",
1956 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1957 (implicit EFLAGS)]>;
1958 } // isCommutable = 1
1960 // XOR instructions with the destination register in REG and the source register
1961 // in R/M. Included for the disassembler.
1962 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1963 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
1964 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
1965 (ins GR16:$src1, GR16:$src2),
1966 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1967 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
1968 (ins GR32:$src1, GR32:$src2),
1969 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
1971 def XOR8rm : I<0x32, MRMSrcMem ,
1972 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1973 "xor{b}\t{$src2, $dst|$dst, $src2}",
1974 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1975 (implicit EFLAGS)]>;
1976 def XOR16rm : I<0x33, MRMSrcMem ,
1977 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1978 "xor{w}\t{$src2, $dst|$dst, $src2}",
1979 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1980 (implicit EFLAGS)]>,
1982 def XOR32rm : I<0x33, MRMSrcMem ,
1983 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1984 "xor{l}\t{$src2, $dst|$dst, $src2}",
1985 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1986 (implicit EFLAGS)]>;
1988 def XOR8ri : Ii8<0x80, MRM6r,
1989 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1990 "xor{b}\t{$src2, $dst|$dst, $src2}",
1991 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1992 (implicit EFLAGS)]>;
1993 def XOR16ri : Ii16<0x81, MRM6r,
1994 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1995 "xor{w}\t{$src2, $dst|$dst, $src2}",
1996 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1997 (implicit EFLAGS)]>, OpSize;
1998 def XOR32ri : Ii32<0x81, MRM6r,
1999 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2000 "xor{l}\t{$src2, $dst|$dst, $src2}",
2001 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
2002 (implicit EFLAGS)]>;
2003 def XOR16ri8 : Ii8<0x83, MRM6r,
2004 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2005 "xor{w}\t{$src2, $dst|$dst, $src2}",
2006 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
2007 (implicit EFLAGS)]>,
2009 def XOR32ri8 : Ii8<0x83, MRM6r,
2010 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2011 "xor{l}\t{$src2, $dst|$dst, $src2}",
2012 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
2013 (implicit EFLAGS)]>;
2015 let isTwoAddress = 0 in {
2016 def XOR8mr : I<0x30, MRMDestMem,
2017 (outs), (ins i8mem :$dst, GR8 :$src),
2018 "xor{b}\t{$src, $dst|$dst, $src}",
2019 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2020 (implicit EFLAGS)]>;
2021 def XOR16mr : I<0x31, MRMDestMem,
2022 (outs), (ins i16mem:$dst, GR16:$src),
2023 "xor{w}\t{$src, $dst|$dst, $src}",
2024 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2025 (implicit EFLAGS)]>,
2027 def XOR32mr : I<0x31, MRMDestMem,
2028 (outs), (ins i32mem:$dst, GR32:$src),
2029 "xor{l}\t{$src, $dst|$dst, $src}",
2030 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2031 (implicit EFLAGS)]>;
2032 def XOR8mi : Ii8<0x80, MRM6m,
2033 (outs), (ins i8mem :$dst, i8imm :$src),
2034 "xor{b}\t{$src, $dst|$dst, $src}",
2035 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2036 (implicit EFLAGS)]>;
2037 def XOR16mi : Ii16<0x81, MRM6m,
2038 (outs), (ins i16mem:$dst, i16imm:$src),
2039 "xor{w}\t{$src, $dst|$dst, $src}",
2040 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2041 (implicit EFLAGS)]>,
2043 def XOR32mi : Ii32<0x81, MRM6m,
2044 (outs), (ins i32mem:$dst, i32imm:$src),
2045 "xor{l}\t{$src, $dst|$dst, $src}",
2046 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2047 (implicit EFLAGS)]>;
2048 def XOR16mi8 : Ii8<0x83, MRM6m,
2049 (outs), (ins i16mem:$dst, i16i8imm :$src),
2050 "xor{w}\t{$src, $dst|$dst, $src}",
2051 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2052 (implicit EFLAGS)]>,
2054 def XOR32mi8 : Ii8<0x83, MRM6m,
2055 (outs), (ins i32mem:$dst, i32i8imm :$src),
2056 "xor{l}\t{$src, $dst|$dst, $src}",
2057 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2058 (implicit EFLAGS)]>;
2060 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2061 "xor{b}\t{$src, %al|%al, $src}", []>;
2062 def XOR16i16 : Ii16 <0x35, RawFrm, (outs), (ins i16imm:$src),
2063 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2064 def XOR32i32 : Ii32 <0x35, RawFrm, (outs), (ins i32imm:$src),
2065 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2066 } // isTwoAddress = 0
2067 } // Defs = [EFLAGS]
2069 // Shift instructions
2070 let Defs = [EFLAGS] in {
2071 let Uses = [CL] in {
2072 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2073 "shl{b}\t{%cl, $dst|$dst, CL}",
2074 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2075 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2076 "shl{w}\t{%cl, $dst|$dst, CL}",
2077 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2078 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2079 "shl{l}\t{%cl, $dst|$dst, CL}",
2080 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2083 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2084 "shl{b}\t{$src2, $dst|$dst, $src2}",
2085 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2086 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2087 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2088 "shl{w}\t{$src2, $dst|$dst, $src2}",
2089 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2090 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2091 "shl{l}\t{$src2, $dst|$dst, $src2}",
2092 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2094 // NOTE: We don't include patterns for shifts of a register by one, because
2095 // 'add reg,reg' is cheaper.
2097 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2098 "shl{b}\t$dst", []>;
2099 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2100 "shl{w}\t$dst", []>, OpSize;
2101 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2102 "shl{l}\t$dst", []>;
2104 } // isConvertibleToThreeAddress = 1
2106 let isTwoAddress = 0 in {
2107 let Uses = [CL] in {
2108 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2109 "shl{b}\t{%cl, $dst|$dst, CL}",
2110 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2111 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2112 "shl{w}\t{%cl, $dst|$dst, CL}",
2113 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2114 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2115 "shl{l}\t{%cl, $dst|$dst, CL}",
2116 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2118 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2119 "shl{b}\t{$src, $dst|$dst, $src}",
2120 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2121 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2122 "shl{w}\t{$src, $dst|$dst, $src}",
2123 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2125 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2126 "shl{l}\t{$src, $dst|$dst, $src}",
2127 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2130 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2132 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2133 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2135 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2137 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2139 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2142 let Uses = [CL] in {
2143 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2144 "shr{b}\t{%cl, $dst|$dst, CL}",
2145 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2146 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2147 "shr{w}\t{%cl, $dst|$dst, CL}",
2148 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2149 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2150 "shr{l}\t{%cl, $dst|$dst, CL}",
2151 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2154 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2155 "shr{b}\t{$src2, $dst|$dst, $src2}",
2156 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2157 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2158 "shr{w}\t{$src2, $dst|$dst, $src2}",
2159 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2160 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2161 "shr{l}\t{$src2, $dst|$dst, $src2}",
2162 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2165 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2167 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2168 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2170 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2171 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2173 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2175 let isTwoAddress = 0 in {
2176 let Uses = [CL] in {
2177 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2178 "shr{b}\t{%cl, $dst|$dst, CL}",
2179 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2180 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2181 "shr{w}\t{%cl, $dst|$dst, CL}",
2182 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2184 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2185 "shr{l}\t{%cl, $dst|$dst, CL}",
2186 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2188 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2189 "shr{b}\t{$src, $dst|$dst, $src}",
2190 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2191 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2192 "shr{w}\t{$src, $dst|$dst, $src}",
2193 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2195 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2196 "shr{l}\t{$src, $dst|$dst, $src}",
2197 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2200 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2202 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2203 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2205 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2206 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2208 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2211 let Uses = [CL] in {
2212 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2213 "sar{b}\t{%cl, $dst|$dst, CL}",
2214 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2215 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2216 "sar{w}\t{%cl, $dst|$dst, CL}",
2217 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2218 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2219 "sar{l}\t{%cl, $dst|$dst, CL}",
2220 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2223 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2224 "sar{b}\t{$src2, $dst|$dst, $src2}",
2225 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2226 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2227 "sar{w}\t{$src2, $dst|$dst, $src2}",
2228 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2230 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2231 "sar{l}\t{$src2, $dst|$dst, $src2}",
2232 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2235 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2237 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2238 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2240 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2241 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2243 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2245 let isTwoAddress = 0 in {
2246 let Uses = [CL] in {
2247 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2248 "sar{b}\t{%cl, $dst|$dst, CL}",
2249 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2250 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2251 "sar{w}\t{%cl, $dst|$dst, CL}",
2252 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2253 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2254 "sar{l}\t{%cl, $dst|$dst, CL}",
2255 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2257 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2258 "sar{b}\t{$src, $dst|$dst, $src}",
2259 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2260 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2261 "sar{w}\t{$src, $dst|$dst, $src}",
2262 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2264 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2265 "sar{l}\t{$src, $dst|$dst, $src}",
2266 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2269 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2271 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2272 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2274 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2276 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2278 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2281 // Rotate instructions
2283 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2284 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2285 let Uses = [CL] in {
2286 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2287 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2289 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2290 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2292 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2293 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2294 let Uses = [CL] in {
2295 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2296 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2298 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2299 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2301 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2302 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2303 let Uses = [CL] in {
2304 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2305 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2307 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2308 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2310 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2311 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2312 let Uses = [CL] in {
2313 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2314 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2316 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2317 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2319 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2320 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2321 let Uses = [CL] in {
2322 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2323 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2325 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2326 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2328 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2329 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2330 let Uses = [CL] in {
2331 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2332 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2334 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2335 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2337 let isTwoAddress = 0 in {
2338 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2339 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2340 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2341 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2342 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2343 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2344 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2345 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2346 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2347 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2348 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2349 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2350 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2351 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2352 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2353 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2354 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2355 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2356 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2357 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2358 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2359 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2360 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2361 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2363 let Uses = [CL] in {
2364 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2365 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2366 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2367 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2368 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2369 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2370 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2371 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2372 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2373 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2374 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2375 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2379 // FIXME: provide shorter instructions when imm8 == 1
2380 let Uses = [CL] in {
2381 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2382 "rol{b}\t{%cl, $dst|$dst, CL}",
2383 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2384 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2385 "rol{w}\t{%cl, $dst|$dst, CL}",
2386 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2387 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2388 "rol{l}\t{%cl, $dst|$dst, CL}",
2389 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2392 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2393 "rol{b}\t{$src2, $dst|$dst, $src2}",
2394 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2395 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2396 "rol{w}\t{$src2, $dst|$dst, $src2}",
2397 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2399 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2400 "rol{l}\t{$src2, $dst|$dst, $src2}",
2401 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2404 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2406 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2407 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2409 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2410 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2412 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2414 let isTwoAddress = 0 in {
2415 let Uses = [CL] in {
2416 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2417 "rol{b}\t{%cl, $dst|$dst, CL}",
2418 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2419 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2420 "rol{w}\t{%cl, $dst|$dst, CL}",
2421 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2422 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2423 "rol{l}\t{%cl, $dst|$dst, CL}",
2424 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2426 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2427 "rol{b}\t{$src, $dst|$dst, $src}",
2428 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2429 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2430 "rol{w}\t{$src, $dst|$dst, $src}",
2431 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2433 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2434 "rol{l}\t{$src, $dst|$dst, $src}",
2435 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2438 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2440 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2441 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2443 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2445 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2447 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2450 let Uses = [CL] in {
2451 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2452 "ror{b}\t{%cl, $dst|$dst, CL}",
2453 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2454 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2455 "ror{w}\t{%cl, $dst|$dst, CL}",
2456 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2457 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2458 "ror{l}\t{%cl, $dst|$dst, CL}",
2459 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2462 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2463 "ror{b}\t{$src2, $dst|$dst, $src2}",
2464 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2465 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2466 "ror{w}\t{$src2, $dst|$dst, $src2}",
2467 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2469 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2470 "ror{l}\t{$src2, $dst|$dst, $src2}",
2471 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2474 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2476 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2477 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2479 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2480 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2482 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2484 let isTwoAddress = 0 in {
2485 let Uses = [CL] in {
2486 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2487 "ror{b}\t{%cl, $dst|$dst, CL}",
2488 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2489 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2490 "ror{w}\t{%cl, $dst|$dst, CL}",
2491 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2492 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2493 "ror{l}\t{%cl, $dst|$dst, CL}",
2494 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2496 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2497 "ror{b}\t{$src, $dst|$dst, $src}",
2498 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2499 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2500 "ror{w}\t{$src, $dst|$dst, $src}",
2501 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2503 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2504 "ror{l}\t{$src, $dst|$dst, $src}",
2505 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2508 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2510 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2511 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2513 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2515 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2517 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2522 // Double shift instructions (generalizations of rotate)
2523 let Uses = [CL] in {
2524 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2525 (ins GR32:$src1, GR32:$src2),
2526 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2527 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2528 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2529 (ins GR32:$src1, GR32:$src2),
2530 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2531 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2532 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2533 (ins GR16:$src1, GR16:$src2),
2534 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2535 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2537 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2538 (ins GR16:$src1, GR16:$src2),
2539 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2540 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2544 let isCommutable = 1 in { // These instructions commute to each other.
2545 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2547 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2548 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2549 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2552 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2554 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2555 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2556 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2559 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2561 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2562 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2563 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2566 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2568 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2569 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2570 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2575 let isTwoAddress = 0 in {
2576 let Uses = [CL] in {
2577 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2578 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2579 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2581 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2582 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2583 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2586 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2587 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2588 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2589 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2590 (i8 imm:$src3)), addr:$dst)]>,
2592 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2593 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2594 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2595 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2596 (i8 imm:$src3)), addr:$dst)]>,
2599 let Uses = [CL] in {
2600 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2601 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2602 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2603 addr:$dst)]>, TB, OpSize;
2604 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2605 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2606 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2607 addr:$dst)]>, TB, OpSize;
2609 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2610 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2611 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2612 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2613 (i8 imm:$src3)), addr:$dst)]>,
2615 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2616 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2617 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2618 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2619 (i8 imm:$src3)), addr:$dst)]>,
2622 } // Defs = [EFLAGS]
2626 let Defs = [EFLAGS] in {
2627 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2628 // Register-Register Addition
2629 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2630 (ins GR8 :$src1, GR8 :$src2),
2631 "add{b}\t{$src2, $dst|$dst, $src2}",
2632 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2633 (implicit EFLAGS)]>;
2635 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2636 // Register-Register Addition
2637 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2638 (ins GR16:$src1, GR16:$src2),
2639 "add{w}\t{$src2, $dst|$dst, $src2}",
2640 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2641 (implicit EFLAGS)]>, OpSize;
2642 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2643 (ins GR32:$src1, GR32:$src2),
2644 "add{l}\t{$src2, $dst|$dst, $src2}",
2645 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2646 (implicit EFLAGS)]>;
2647 } // end isConvertibleToThreeAddress
2648 } // end isCommutable
2650 // Register-Memory Addition
2651 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2652 (ins GR8 :$src1, i8mem :$src2),
2653 "add{b}\t{$src2, $dst|$dst, $src2}",
2654 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2655 (implicit EFLAGS)]>;
2656 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2657 (ins GR16:$src1, i16mem:$src2),
2658 "add{w}\t{$src2, $dst|$dst, $src2}",
2659 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2660 (implicit EFLAGS)]>, OpSize;
2661 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2662 (ins GR32:$src1, i32mem:$src2),
2663 "add{l}\t{$src2, $dst|$dst, $src2}",
2664 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2665 (implicit EFLAGS)]>;
2667 // Register-Register Addition - Equivalent to the normal rr forms (ADD8rr,
2668 // ADD16rr, and ADD32rr), but differently encoded.
2669 def ADD8mrmrr: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2670 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2671 def ADD16mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2672 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2673 def ADD32mrmrr: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2674 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2676 // Register-Integer Addition
2677 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2678 "add{b}\t{$src2, $dst|$dst, $src2}",
2679 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2680 (implicit EFLAGS)]>;
2682 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2683 // Register-Integer Addition
2684 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2685 (ins GR16:$src1, i16imm:$src2),
2686 "add{w}\t{$src2, $dst|$dst, $src2}",
2687 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2688 (implicit EFLAGS)]>, OpSize;
2689 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2690 (ins GR32:$src1, i32imm:$src2),
2691 "add{l}\t{$src2, $dst|$dst, $src2}",
2692 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2693 (implicit EFLAGS)]>;
2694 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2695 (ins GR16:$src1, i16i8imm:$src2),
2696 "add{w}\t{$src2, $dst|$dst, $src2}",
2697 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2698 (implicit EFLAGS)]>, OpSize;
2699 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2700 (ins GR32:$src1, i32i8imm:$src2),
2701 "add{l}\t{$src2, $dst|$dst, $src2}",
2702 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2703 (implicit EFLAGS)]>;
2706 let isTwoAddress = 0 in {
2707 // Memory-Register Addition
2708 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2709 "add{b}\t{$src2, $dst|$dst, $src2}",
2710 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2711 (implicit EFLAGS)]>;
2712 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2713 "add{w}\t{$src2, $dst|$dst, $src2}",
2714 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2715 (implicit EFLAGS)]>, OpSize;
2716 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2717 "add{l}\t{$src2, $dst|$dst, $src2}",
2718 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2719 (implicit EFLAGS)]>;
2720 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2721 "add{b}\t{$src2, $dst|$dst, $src2}",
2722 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2723 (implicit EFLAGS)]>;
2724 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2725 "add{w}\t{$src2, $dst|$dst, $src2}",
2726 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2727 (implicit EFLAGS)]>, OpSize;
2728 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2729 "add{l}\t{$src2, $dst|$dst, $src2}",
2730 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2731 (implicit EFLAGS)]>;
2732 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2733 "add{w}\t{$src2, $dst|$dst, $src2}",
2734 [(store (add (load addr:$dst), i16immSExt8:$src2),
2736 (implicit EFLAGS)]>, OpSize;
2737 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2738 "add{l}\t{$src2, $dst|$dst, $src2}",
2739 [(store (add (load addr:$dst), i32immSExt8:$src2),
2741 (implicit EFLAGS)]>;
2744 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2745 "add{b}\t{$src, %al|%al, $src}", []>;
2746 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2747 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2748 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2749 "add{l}\t{$src, %eax|%eax, $src}", []>;
2752 let Uses = [EFLAGS] in {
2753 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2754 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2755 "adc{b}\t{$src2, $dst|$dst, $src2}",
2756 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2757 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2758 (ins GR16:$src1, GR16:$src2),
2759 "adc{w}\t{$src2, $dst|$dst, $src2}",
2760 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2761 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2762 (ins GR32:$src1, GR32:$src2),
2763 "adc{l}\t{$src2, $dst|$dst, $src2}",
2764 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2767 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2768 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2769 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2770 (ins GR16:$src1, GR16:$src2),
2771 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2772 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2773 (ins GR32:$src1, GR32:$src2),
2774 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2776 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2777 (ins GR8:$src1, i8mem:$src2),
2778 "adc{b}\t{$src2, $dst|$dst, $src2}",
2779 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2780 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2781 (ins GR16:$src1, i16mem:$src2),
2782 "adc{w}\t{$src2, $dst|$dst, $src2}",
2783 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2785 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2786 (ins GR32:$src1, i32mem:$src2),
2787 "adc{l}\t{$src2, $dst|$dst, $src2}",
2788 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2789 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2790 "adc{b}\t{$src2, $dst|$dst, $src2}",
2791 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2792 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2793 (ins GR16:$src1, i16imm:$src2),
2794 "adc{w}\t{$src2, $dst|$dst, $src2}",
2795 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2796 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2797 (ins GR16:$src1, i16i8imm:$src2),
2798 "adc{w}\t{$src2, $dst|$dst, $src2}",
2799 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2801 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2802 (ins GR32:$src1, i32imm:$src2),
2803 "adc{l}\t{$src2, $dst|$dst, $src2}",
2804 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2805 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2806 (ins GR32:$src1, i32i8imm:$src2),
2807 "adc{l}\t{$src2, $dst|$dst, $src2}",
2808 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2810 let isTwoAddress = 0 in {
2811 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2812 "adc{b}\t{$src2, $dst|$dst, $src2}",
2813 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2814 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2815 "adc{w}\t{$src2, $dst|$dst, $src2}",
2816 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2818 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2819 "adc{l}\t{$src2, $dst|$dst, $src2}",
2820 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2821 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2822 "adc{b}\t{$src2, $dst|$dst, $src2}",
2823 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2824 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2825 "adc{w}\t{$src2, $dst|$dst, $src2}",
2826 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2828 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2829 "adc{w}\t{$src2, $dst|$dst, $src2}",
2830 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2832 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2833 "adc{l}\t{$src2, $dst|$dst, $src2}",
2834 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2835 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2836 "adc{l}\t{$src2, $dst|$dst, $src2}",
2837 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2839 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2840 "adc{b}\t{$src, %al|%al, $src}", []>;
2841 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2842 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2843 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2844 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2846 } // Uses = [EFLAGS]
2848 // Register-Register Subtraction
2849 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2850 "sub{b}\t{$src2, $dst|$dst, $src2}",
2851 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2852 (implicit EFLAGS)]>;
2853 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2854 "sub{w}\t{$src2, $dst|$dst, $src2}",
2855 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2856 (implicit EFLAGS)]>, OpSize;
2857 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2858 "sub{l}\t{$src2, $dst|$dst, $src2}",
2859 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2860 (implicit EFLAGS)]>;
2862 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2863 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2864 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2865 (ins GR16:$src1, GR16:$src2),
2866 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2867 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2868 (ins GR32:$src1, GR32:$src2),
2869 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2871 // Register-Memory Subtraction
2872 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2873 (ins GR8 :$src1, i8mem :$src2),
2874 "sub{b}\t{$src2, $dst|$dst, $src2}",
2875 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2876 (implicit EFLAGS)]>;
2877 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2878 (ins GR16:$src1, i16mem:$src2),
2879 "sub{w}\t{$src2, $dst|$dst, $src2}",
2880 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2881 (implicit EFLAGS)]>, OpSize;
2882 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2883 (ins GR32:$src1, i32mem:$src2),
2884 "sub{l}\t{$src2, $dst|$dst, $src2}",
2885 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2886 (implicit EFLAGS)]>;
2888 // Register-Integer Subtraction
2889 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2890 (ins GR8:$src1, i8imm:$src2),
2891 "sub{b}\t{$src2, $dst|$dst, $src2}",
2892 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2893 (implicit EFLAGS)]>;
2894 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2895 (ins GR16:$src1, i16imm:$src2),
2896 "sub{w}\t{$src2, $dst|$dst, $src2}",
2897 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2898 (implicit EFLAGS)]>, OpSize;
2899 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2900 (ins GR32:$src1, i32imm:$src2),
2901 "sub{l}\t{$src2, $dst|$dst, $src2}",
2902 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2903 (implicit EFLAGS)]>;
2904 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2905 (ins GR16:$src1, i16i8imm:$src2),
2906 "sub{w}\t{$src2, $dst|$dst, $src2}",
2907 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2908 (implicit EFLAGS)]>, OpSize;
2909 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2910 (ins GR32:$src1, i32i8imm:$src2),
2911 "sub{l}\t{$src2, $dst|$dst, $src2}",
2912 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2913 (implicit EFLAGS)]>;
2915 let isTwoAddress = 0 in {
2916 // Memory-Register Subtraction
2917 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2918 "sub{b}\t{$src2, $dst|$dst, $src2}",
2919 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2920 (implicit EFLAGS)]>;
2921 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2922 "sub{w}\t{$src2, $dst|$dst, $src2}",
2923 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2924 (implicit EFLAGS)]>, OpSize;
2925 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2926 "sub{l}\t{$src2, $dst|$dst, $src2}",
2927 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2928 (implicit EFLAGS)]>;
2930 // Memory-Integer Subtraction
2931 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2932 "sub{b}\t{$src2, $dst|$dst, $src2}",
2933 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2934 (implicit EFLAGS)]>;
2935 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2936 "sub{w}\t{$src2, $dst|$dst, $src2}",
2937 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2938 (implicit EFLAGS)]>, OpSize;
2939 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2940 "sub{l}\t{$src2, $dst|$dst, $src2}",
2941 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2942 (implicit EFLAGS)]>;
2943 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2944 "sub{w}\t{$src2, $dst|$dst, $src2}",
2945 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2947 (implicit EFLAGS)]>, OpSize;
2948 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2949 "sub{l}\t{$src2, $dst|$dst, $src2}",
2950 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2952 (implicit EFLAGS)]>;
2954 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
2955 "sub{b}\t{$src, %al|%al, $src}", []>;
2956 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
2957 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2958 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
2959 "sub{l}\t{$src, %eax|%eax, $src}", []>;
2962 let Uses = [EFLAGS] in {
2963 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2964 (ins GR8:$src1, GR8:$src2),
2965 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2966 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2967 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2968 (ins GR16:$src1, GR16:$src2),
2969 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2970 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2971 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2972 (ins GR32:$src1, GR32:$src2),
2973 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2974 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2976 let isTwoAddress = 0 in {
2977 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2978 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2979 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2980 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2981 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2982 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2984 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2985 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2986 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2987 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2988 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2989 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2990 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2991 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2992 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2994 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2995 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2996 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2998 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2999 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3000 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3001 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3002 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3003 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3005 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3006 "sbb{b}\t{$src, %al|%al, $src}", []>;
3007 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3008 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3009 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3010 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3013 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3014 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3015 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3016 (ins GR16:$src1, GR16:$src2),
3017 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3018 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3019 (ins GR32:$src1, GR32:$src2),
3020 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3022 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3023 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3024 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3025 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3026 (ins GR16:$src1, i16mem:$src2),
3027 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3028 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3030 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3031 (ins GR32:$src1, i32mem:$src2),
3032 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3033 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3034 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3035 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3036 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3037 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3038 (ins GR16:$src1, i16imm:$src2),
3039 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3040 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3041 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3042 (ins GR16:$src1, i16i8imm:$src2),
3043 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3044 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3046 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3047 (ins GR32:$src1, i32imm:$src2),
3048 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3049 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3050 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3051 (ins GR32:$src1, i32i8imm:$src2),
3052 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3053 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3054 } // Uses = [EFLAGS]
3055 } // Defs = [EFLAGS]
3057 let Defs = [EFLAGS] in {
3058 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3059 // Register-Register Signed Integer Multiply
3060 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3061 "imul{w}\t{$src2, $dst|$dst, $src2}",
3062 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
3063 (implicit EFLAGS)]>, TB, OpSize;
3064 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3065 "imul{l}\t{$src2, $dst|$dst, $src2}",
3066 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
3067 (implicit EFLAGS)]>, TB;
3070 // Register-Memory Signed Integer Multiply
3071 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3072 (ins GR16:$src1, i16mem:$src2),
3073 "imul{w}\t{$src2, $dst|$dst, $src2}",
3074 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
3075 (implicit EFLAGS)]>, TB, OpSize;
3076 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3077 (ins GR32:$src1, i32mem:$src2),
3078 "imul{l}\t{$src2, $dst|$dst, $src2}",
3079 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
3080 (implicit EFLAGS)]>, TB;
3081 } // Defs = [EFLAGS]
3082 } // end Two Address instructions
3084 // Suprisingly enough, these are not two address instructions!
3085 let Defs = [EFLAGS] in {
3086 // Register-Integer Signed Integer Multiply
3087 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3088 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3089 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3090 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
3091 (implicit EFLAGS)]>, OpSize;
3092 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3093 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3094 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3095 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
3096 (implicit EFLAGS)]>;
3097 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3098 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3099 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3100 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
3101 (implicit EFLAGS)]>, OpSize;
3102 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3103 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3104 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3105 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
3106 (implicit EFLAGS)]>;
3108 // Memory-Integer Signed Integer Multiply
3109 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3110 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3111 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3112 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
3113 (implicit EFLAGS)]>, OpSize;
3114 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3115 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3116 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3117 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
3118 (implicit EFLAGS)]>;
3119 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3120 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3121 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3122 [(set GR16:$dst, (mul (load addr:$src1),
3123 i16immSExt8:$src2)),
3124 (implicit EFLAGS)]>, OpSize;
3125 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3126 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3127 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3128 [(set GR32:$dst, (mul (load addr:$src1),
3129 i32immSExt8:$src2)),
3130 (implicit EFLAGS)]>;
3131 } // Defs = [EFLAGS]
3133 //===----------------------------------------------------------------------===//
3134 // Test instructions are just like AND, except they don't generate a result.
3136 let Defs = [EFLAGS] in {
3137 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3138 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3139 "test{b}\t{$src2, $src1|$src1, $src2}",
3140 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
3141 (implicit EFLAGS)]>;
3142 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3143 "test{w}\t{$src2, $src1|$src1, $src2}",
3144 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
3145 (implicit EFLAGS)]>,
3147 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3148 "test{l}\t{$src2, $src1|$src1, $src2}",
3149 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
3150 (implicit EFLAGS)]>;
3153 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3154 "test{b}\t{$src, %al|%al, $src}", []>;
3155 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3156 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3157 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3158 "test{l}\t{$src, %eax|%eax, $src}", []>;
3160 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3161 "test{b}\t{$src2, $src1|$src1, $src2}",
3162 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
3163 (implicit EFLAGS)]>;
3164 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3165 "test{w}\t{$src2, $src1|$src1, $src2}",
3166 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
3167 (implicit EFLAGS)]>, OpSize;
3168 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3169 "test{l}\t{$src2, $src1|$src1, $src2}",
3170 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
3171 (implicit EFLAGS)]>;
3173 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3174 (outs), (ins GR8:$src1, i8imm:$src2),
3175 "test{b}\t{$src2, $src1|$src1, $src2}",
3176 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
3177 (implicit EFLAGS)]>;
3178 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3179 (outs), (ins GR16:$src1, i16imm:$src2),
3180 "test{w}\t{$src2, $src1|$src1, $src2}",
3181 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
3182 (implicit EFLAGS)]>, OpSize;
3183 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3184 (outs), (ins GR32:$src1, i32imm:$src2),
3185 "test{l}\t{$src2, $src1|$src1, $src2}",
3186 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
3187 (implicit EFLAGS)]>;
3189 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3190 (outs), (ins i8mem:$src1, i8imm:$src2),
3191 "test{b}\t{$src2, $src1|$src1, $src2}",
3192 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
3193 (implicit EFLAGS)]>;
3194 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3195 (outs), (ins i16mem:$src1, i16imm:$src2),
3196 "test{w}\t{$src2, $src1|$src1, $src2}",
3197 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
3198 (implicit EFLAGS)]>, OpSize;
3199 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3200 (outs), (ins i32mem:$src1, i32imm:$src2),
3201 "test{l}\t{$src2, $src1|$src1, $src2}",
3202 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
3203 (implicit EFLAGS)]>;
3204 } // Defs = [EFLAGS]
3207 // Condition code ops, incl. set if equal/not equal/...
3208 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3209 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3210 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3211 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3213 let Uses = [EFLAGS] in {
3214 // Use sbb to materialize carry bit.
3215 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3216 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3217 // However, Pat<> can't replicate the destination reg into the inputs of the
3219 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3221 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3222 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3223 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3224 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3226 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3227 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3230 def SETEr : I<0x94, MRM0r,
3231 (outs GR8 :$dst), (ins),
3233 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3235 def SETEm : I<0x94, MRM0m,
3236 (outs), (ins i8mem:$dst),
3238 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3241 def SETNEr : I<0x95, MRM0r,
3242 (outs GR8 :$dst), (ins),
3244 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3246 def SETNEm : I<0x95, MRM0m,
3247 (outs), (ins i8mem:$dst),
3249 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3252 def SETLr : I<0x9C, MRM0r,
3253 (outs GR8 :$dst), (ins),
3255 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3256 TB; // GR8 = < signed
3257 def SETLm : I<0x9C, MRM0m,
3258 (outs), (ins i8mem:$dst),
3260 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3261 TB; // [mem8] = < signed
3263 def SETGEr : I<0x9D, MRM0r,
3264 (outs GR8 :$dst), (ins),
3266 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3267 TB; // GR8 = >= signed
3268 def SETGEm : I<0x9D, MRM0m,
3269 (outs), (ins i8mem:$dst),
3271 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3272 TB; // [mem8] = >= signed
3274 def SETLEr : I<0x9E, MRM0r,
3275 (outs GR8 :$dst), (ins),
3277 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3278 TB; // GR8 = <= signed
3279 def SETLEm : I<0x9E, MRM0m,
3280 (outs), (ins i8mem:$dst),
3282 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3283 TB; // [mem8] = <= signed
3285 def SETGr : I<0x9F, MRM0r,
3286 (outs GR8 :$dst), (ins),
3288 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3289 TB; // GR8 = > signed
3290 def SETGm : I<0x9F, MRM0m,
3291 (outs), (ins i8mem:$dst),
3293 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3294 TB; // [mem8] = > signed
3296 def SETBr : I<0x92, MRM0r,
3297 (outs GR8 :$dst), (ins),
3299 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3300 TB; // GR8 = < unsign
3301 def SETBm : I<0x92, MRM0m,
3302 (outs), (ins i8mem:$dst),
3304 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3305 TB; // [mem8] = < unsign
3307 def SETAEr : I<0x93, MRM0r,
3308 (outs GR8 :$dst), (ins),
3310 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3311 TB; // GR8 = >= unsign
3312 def SETAEm : I<0x93, MRM0m,
3313 (outs), (ins i8mem:$dst),
3315 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3316 TB; // [mem8] = >= unsign
3318 def SETBEr : I<0x96, MRM0r,
3319 (outs GR8 :$dst), (ins),
3321 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3322 TB; // GR8 = <= unsign
3323 def SETBEm : I<0x96, MRM0m,
3324 (outs), (ins i8mem:$dst),
3326 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3327 TB; // [mem8] = <= unsign
3329 def SETAr : I<0x97, MRM0r,
3330 (outs GR8 :$dst), (ins),
3332 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3333 TB; // GR8 = > signed
3334 def SETAm : I<0x97, MRM0m,
3335 (outs), (ins i8mem:$dst),
3337 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3338 TB; // [mem8] = > signed
3340 def SETSr : I<0x98, MRM0r,
3341 (outs GR8 :$dst), (ins),
3343 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3344 TB; // GR8 = <sign bit>
3345 def SETSm : I<0x98, MRM0m,
3346 (outs), (ins i8mem:$dst),
3348 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3349 TB; // [mem8] = <sign bit>
3350 def SETNSr : I<0x99, MRM0r,
3351 (outs GR8 :$dst), (ins),
3353 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3354 TB; // GR8 = !<sign bit>
3355 def SETNSm : I<0x99, MRM0m,
3356 (outs), (ins i8mem:$dst),
3358 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3359 TB; // [mem8] = !<sign bit>
3361 def SETPr : I<0x9A, MRM0r,
3362 (outs GR8 :$dst), (ins),
3364 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3366 def SETPm : I<0x9A, MRM0m,
3367 (outs), (ins i8mem:$dst),
3369 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3370 TB; // [mem8] = parity
3371 def SETNPr : I<0x9B, MRM0r,
3372 (outs GR8 :$dst), (ins),
3374 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3375 TB; // GR8 = not parity
3376 def SETNPm : I<0x9B, MRM0m,
3377 (outs), (ins i8mem:$dst),
3379 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3380 TB; // [mem8] = not parity
3382 def SETOr : I<0x90, MRM0r,
3383 (outs GR8 :$dst), (ins),
3385 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3386 TB; // GR8 = overflow
3387 def SETOm : I<0x90, MRM0m,
3388 (outs), (ins i8mem:$dst),
3390 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3391 TB; // [mem8] = overflow
3392 def SETNOr : I<0x91, MRM0r,
3393 (outs GR8 :$dst), (ins),
3395 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3396 TB; // GR8 = not overflow
3397 def SETNOm : I<0x91, MRM0m,
3398 (outs), (ins i8mem:$dst),
3400 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3401 TB; // [mem8] = not overflow
3402 } // Uses = [EFLAGS]
3405 // Integer comparisons
3406 let Defs = [EFLAGS] in {
3407 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3408 "cmp{b}\t{$src, %al|%al, $src}", []>;
3409 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3410 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3411 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3412 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3414 def CMP8rr : I<0x38, MRMDestReg,
3415 (outs), (ins GR8 :$src1, GR8 :$src2),
3416 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3417 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
3418 def CMP16rr : I<0x39, MRMDestReg,
3419 (outs), (ins GR16:$src1, GR16:$src2),
3420 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3421 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
3422 def CMP32rr : I<0x39, MRMDestReg,
3423 (outs), (ins GR32:$src1, GR32:$src2),
3424 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3425 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
3426 def CMP8mr : I<0x38, MRMDestMem,
3427 (outs), (ins i8mem :$src1, GR8 :$src2),
3428 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3429 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
3430 (implicit EFLAGS)]>;
3431 def CMP16mr : I<0x39, MRMDestMem,
3432 (outs), (ins i16mem:$src1, GR16:$src2),
3433 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3434 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
3435 (implicit EFLAGS)]>, OpSize;
3436 def CMP32mr : I<0x39, MRMDestMem,
3437 (outs), (ins i32mem:$src1, GR32:$src2),
3438 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3439 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
3440 (implicit EFLAGS)]>;
3441 def CMP8rm : I<0x3A, MRMSrcMem,
3442 (outs), (ins GR8 :$src1, i8mem :$src2),
3443 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3444 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
3445 (implicit EFLAGS)]>;
3446 def CMP16rm : I<0x3B, MRMSrcMem,
3447 (outs), (ins GR16:$src1, i16mem:$src2),
3448 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3449 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
3450 (implicit EFLAGS)]>, OpSize;
3451 def CMP32rm : I<0x3B, MRMSrcMem,
3452 (outs), (ins GR32:$src1, i32mem:$src2),
3453 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3454 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
3455 (implicit EFLAGS)]>;
3456 def CMP8mrmrr : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3457 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3458 def CMP16mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3459 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3460 def CMP32mrmrr : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3461 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3462 def CMP8ri : Ii8<0x80, MRM7r,
3463 (outs), (ins GR8:$src1, i8imm:$src2),
3464 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3465 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
3466 def CMP16ri : Ii16<0x81, MRM7r,
3467 (outs), (ins GR16:$src1, i16imm:$src2),
3468 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3469 [(X86cmp GR16:$src1, imm:$src2),
3470 (implicit EFLAGS)]>, OpSize;
3471 def CMP32ri : Ii32<0x81, MRM7r,
3472 (outs), (ins GR32:$src1, i32imm:$src2),
3473 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3474 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
3475 def CMP8mi : Ii8 <0x80, MRM7m,
3476 (outs), (ins i8mem :$src1, i8imm :$src2),
3477 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3478 [(X86cmp (loadi8 addr:$src1), imm:$src2),
3479 (implicit EFLAGS)]>;
3480 def CMP16mi : Ii16<0x81, MRM7m,
3481 (outs), (ins i16mem:$src1, i16imm:$src2),
3482 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3483 [(X86cmp (loadi16 addr:$src1), imm:$src2),
3484 (implicit EFLAGS)]>, OpSize;
3485 def CMP32mi : Ii32<0x81, MRM7m,
3486 (outs), (ins i32mem:$src1, i32imm:$src2),
3487 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3488 [(X86cmp (loadi32 addr:$src1), imm:$src2),
3489 (implicit EFLAGS)]>;
3490 def CMP16ri8 : Ii8<0x83, MRM7r,
3491 (outs), (ins GR16:$src1, i16i8imm:$src2),
3492 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3493 [(X86cmp GR16:$src1, i16immSExt8:$src2),
3494 (implicit EFLAGS)]>, OpSize;
3495 def CMP16mi8 : Ii8<0x83, MRM7m,
3496 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3497 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3498 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
3499 (implicit EFLAGS)]>, OpSize;
3500 def CMP32mi8 : Ii8<0x83, MRM7m,
3501 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3502 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3503 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
3504 (implicit EFLAGS)]>;
3505 def CMP32ri8 : Ii8<0x83, MRM7r,
3506 (outs), (ins GR32:$src1, i32i8imm:$src2),
3507 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3508 [(X86cmp GR32:$src1, i32immSExt8:$src2),
3509 (implicit EFLAGS)]>;
3510 } // Defs = [EFLAGS]
3513 // TODO: BTC, BTR, and BTS
3514 let Defs = [EFLAGS] in {
3515 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3516 "bt{w}\t{$src2, $src1|$src1, $src2}",
3517 [(X86bt GR16:$src1, GR16:$src2),
3518 (implicit EFLAGS)]>, OpSize, TB;
3519 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3520 "bt{l}\t{$src2, $src1|$src1, $src2}",
3521 [(X86bt GR32:$src1, GR32:$src2),
3522 (implicit EFLAGS)]>, TB;
3524 // Unlike with the register+register form, the memory+register form of the
3525 // bt instruction does not ignore the high bits of the index. From ISel's
3526 // perspective, this is pretty bizarre. Make these instructions disassembly
3529 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3530 "bt{w}\t{$src2, $src1|$src1, $src2}",
3531 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3532 // (implicit EFLAGS)]
3534 >, OpSize, TB, Requires<[FastBTMem]>;
3535 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3536 "bt{l}\t{$src2, $src1|$src1, $src2}",
3537 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3538 // (implicit EFLAGS)]
3540 >, TB, Requires<[FastBTMem]>;
3542 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3543 "bt{w}\t{$src2, $src1|$src1, $src2}",
3544 [(X86bt GR16:$src1, i16immSExt8:$src2),
3545 (implicit EFLAGS)]>, OpSize, TB;
3546 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3547 "bt{l}\t{$src2, $src1|$src1, $src2}",
3548 [(X86bt GR32:$src1, i32immSExt8:$src2),
3549 (implicit EFLAGS)]>, TB;
3550 // Note that these instructions don't need FastBTMem because that
3551 // only applies when the other operand is in a register. When it's
3552 // an immediate, bt is still fast.
3553 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3554 "bt{w}\t{$src2, $src1|$src1, $src2}",
3555 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3556 (implicit EFLAGS)]>, OpSize, TB;
3557 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3558 "bt{l}\t{$src2, $src1|$src1, $src2}",
3559 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3560 (implicit EFLAGS)]>, TB;
3562 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3563 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3564 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3565 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3566 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3567 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3568 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3569 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3570 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3571 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3572 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3573 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3574 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3575 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3576 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3577 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3579 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3580 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3581 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3582 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3583 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3584 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3585 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3586 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3587 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3588 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3589 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3590 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3591 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3592 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3593 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3594 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3596 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3597 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3598 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3599 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3600 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3601 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3602 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3603 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3604 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3605 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3606 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3607 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3608 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3609 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3610 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3611 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3612 } // Defs = [EFLAGS]
3614 // Sign/Zero extenders
3615 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3616 // of the register here. This has a smaller encoding and avoids a
3617 // partial-register update. Actual movsbw included for the disassembler.
3618 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3619 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3620 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3621 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3622 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3623 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3624 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3625 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3626 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3627 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3628 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3629 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3630 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3631 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3632 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3633 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3634 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3635 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3636 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3637 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3639 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3640 // of the register here. This has a smaller encoding and avoids a
3641 // partial-register update. Actual movzbw included for the disassembler.
3642 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3643 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3644 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3645 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3646 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3647 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3648 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3649 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3650 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3651 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3652 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3653 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3654 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3655 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3656 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3657 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3658 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3659 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3660 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3661 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3663 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3664 // except that they use GR32_NOREX for the output operand register class
3665 // instead of GR32. This allows them to operate on h registers on x86-64.
3666 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3667 (outs GR32_NOREX:$dst), (ins GR8:$src),
3668 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3671 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3672 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3673 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3676 let neverHasSideEffects = 1 in {
3677 let Defs = [AX], Uses = [AL] in
3678 def CBW : I<0x98, RawFrm, (outs), (ins),
3679 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3680 let Defs = [EAX], Uses = [AX] in
3681 def CWDE : I<0x98, RawFrm, (outs), (ins),
3682 "{cwtl|cwde}", []>; // EAX = signext(AX)
3684 let Defs = [AX,DX], Uses = [AX] in
3685 def CWD : I<0x99, RawFrm, (outs), (ins),
3686 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3687 let Defs = [EAX,EDX], Uses = [EAX] in
3688 def CDQ : I<0x99, RawFrm, (outs), (ins),
3689 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3692 //===----------------------------------------------------------------------===//
3693 // Alias Instructions
3694 //===----------------------------------------------------------------------===//
3696 // Alias instructions that map movr0 to xor.
3697 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3698 // FIXME: Set encoding to pseudo.
3699 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3700 isCodeGenOnly = 1 in {
3701 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3702 [(set GR8:$dst, 0)]>;
3704 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3705 // encoding and avoids a partial-register update sometimes, but doing so
3706 // at isel time interferes with rematerialization in the current register
3707 // allocator. For now, this is rewritten when the instruction is lowered
3709 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3711 [(set GR16:$dst, 0)]>, OpSize;
3713 // FIXME: Set encoding to pseudo.
3714 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3715 [(set GR32:$dst, 0)]>;
3718 //===----------------------------------------------------------------------===//
3719 // Thread Local Storage Instructions
3722 // All calls clobber the non-callee saved registers. ESP is marked as
3723 // a use to prevent stack-pointer assignments that appear immediately
3724 // before calls from potentially appearing dead.
3725 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3726 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3727 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3728 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3730 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3731 "leal\t$sym, %eax; "
3732 "call\t___tls_get_addr@PLT",
3733 [(X86tlsaddr tls32addr:$sym)]>,
3734 Requires<[In32BitMode]>;
3736 let AddedComplexity = 5, isCodeGenOnly = 1 in
3737 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3738 "movl\t%gs:$src, $dst",
3739 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3741 let AddedComplexity = 5, isCodeGenOnly = 1 in
3742 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3743 "movl\t%fs:$src, $dst",
3744 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3746 //===----------------------------------------------------------------------===//
3747 // EH Pseudo Instructions
3749 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3750 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3751 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3752 "ret\t#eh_return, addr: $addr",
3753 [(X86ehret GR32:$addr)]>;
3757 //===----------------------------------------------------------------------===//
3761 // Atomic swap. These are just normal xchg instructions. But since a memory
3762 // operand is referenced, the atomicity is ensured.
3763 let Constraints = "$val = $dst" in {
3764 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3765 (ins GR32:$val, i32mem:$ptr),
3766 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3767 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3768 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3769 (ins GR16:$val, i16mem:$ptr),
3770 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3771 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3773 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3774 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3775 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3777 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3778 "xchg{l}\t{$val, $src|$src, $val}", []>;
3779 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3780 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3781 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3782 "xchg{b}\t{$val, $src|$src, $val}", []>;
3785 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3786 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3787 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3788 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3790 // Atomic compare and swap.
3791 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3792 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3794 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3795 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3797 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3798 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3801 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3804 let Defs = [AX, EFLAGS], Uses = [AX] in {
3805 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3807 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3808 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3810 let Defs = [AL, EFLAGS], Uses = [AL] in {
3811 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3813 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3814 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3817 // Atomic exchange and add
3818 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3819 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3821 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3822 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3824 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3826 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3827 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3829 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3831 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3832 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3836 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3837 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3838 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3839 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3840 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3841 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3843 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3844 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3845 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3846 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3847 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3848 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3850 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3851 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3852 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3853 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3854 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3855 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3857 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3858 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3859 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3860 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3861 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3862 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3864 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3865 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3866 "cmpxchg8b\t$dst", []>, TB;
3868 // Optimized codegen when the non-memory output is not used.
3869 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3870 let Defs = [EFLAGS] in {
3871 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3873 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3874 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3876 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3877 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3879 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3880 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3882 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3883 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3885 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3886 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3888 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3889 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3891 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3892 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3894 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3896 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3898 "inc{b}\t$dst", []>, LOCK;
3899 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3901 "inc{w}\t$dst", []>, OpSize, LOCK;
3902 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3904 "inc{l}\t$dst", []>, LOCK;
3906 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3908 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3909 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3911 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3912 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3914 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3915 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3917 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3918 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3920 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3921 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3923 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3924 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3926 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3927 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3929 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3931 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3933 "dec{b}\t$dst", []>, LOCK;
3934 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3936 "dec{w}\t$dst", []>, OpSize, LOCK;
3937 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3939 "dec{l}\t$dst", []>, LOCK;
3942 // Atomic exchange, and, or, xor
3943 let Constraints = "$val = $dst", Defs = [EFLAGS],
3944 usesCustomInserter = 1 in {
3945 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3946 "#ATOMAND32 PSEUDO!",
3947 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3948 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3949 "#ATOMOR32 PSEUDO!",
3950 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3951 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3952 "#ATOMXOR32 PSEUDO!",
3953 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3954 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3955 "#ATOMNAND32 PSEUDO!",
3956 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3957 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3958 "#ATOMMIN32 PSEUDO!",
3959 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3960 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3961 "#ATOMMAX32 PSEUDO!",
3962 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3963 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3964 "#ATOMUMIN32 PSEUDO!",
3965 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3966 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3967 "#ATOMUMAX32 PSEUDO!",
3968 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3970 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3971 "#ATOMAND16 PSEUDO!",
3972 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3973 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3974 "#ATOMOR16 PSEUDO!",
3975 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3976 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3977 "#ATOMXOR16 PSEUDO!",
3978 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3979 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3980 "#ATOMNAND16 PSEUDO!",
3981 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3982 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3983 "#ATOMMIN16 PSEUDO!",
3984 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3985 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3986 "#ATOMMAX16 PSEUDO!",
3987 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3988 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3989 "#ATOMUMIN16 PSEUDO!",
3990 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3991 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3992 "#ATOMUMAX16 PSEUDO!",
3993 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3995 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3996 "#ATOMAND8 PSEUDO!",
3997 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3998 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4000 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4001 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4002 "#ATOMXOR8 PSEUDO!",
4003 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4004 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4005 "#ATOMNAND8 PSEUDO!",
4006 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4009 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4010 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4011 Uses = [EAX, EBX, ECX, EDX],
4012 mayLoad = 1, mayStore = 1,
4013 usesCustomInserter = 1 in {
4014 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4015 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4016 "#ATOMAND6432 PSEUDO!", []>;
4017 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4018 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4019 "#ATOMOR6432 PSEUDO!", []>;
4020 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4021 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4022 "#ATOMXOR6432 PSEUDO!", []>;
4023 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4024 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4025 "#ATOMNAND6432 PSEUDO!", []>;
4026 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4027 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4028 "#ATOMADD6432 PSEUDO!", []>;
4029 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4030 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4031 "#ATOMSUB6432 PSEUDO!", []>;
4032 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4033 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4034 "#ATOMSWAP6432 PSEUDO!", []>;
4037 // Segmentation support instructions.
4039 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4040 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4041 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4042 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4044 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4045 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4046 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4047 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4048 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4050 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4051 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4052 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4053 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4054 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4055 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4056 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4057 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4059 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4061 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4062 "str{w}\t{$dst}", []>, TB;
4063 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4064 "str{w}\t{$dst}", []>, TB;
4065 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4066 "ltr{w}\t{$src}", []>, TB;
4067 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4068 "ltr{w}\t{$src}", []>, TB;
4070 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4071 "push{w}\t%fs", []>, OpSize, TB;
4072 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4073 "push{l}\t%fs", []>, TB;
4074 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4075 "push{w}\t%gs", []>, OpSize, TB;
4076 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4077 "push{l}\t%gs", []>, TB;
4079 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4080 "pop{w}\t%fs", []>, OpSize, TB;
4081 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4082 "pop{l}\t%fs", []>, TB;
4083 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4084 "pop{w}\t%gs", []>, OpSize, TB;
4085 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4086 "pop{l}\t%gs", []>, TB;
4088 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4089 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4090 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4091 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4092 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4093 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4094 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4095 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4096 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4097 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4098 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4099 "les{l}\t{$src, $dst|$dst, $src}", []>;
4100 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4101 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4102 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4103 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4104 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4105 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4106 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4107 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4109 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4110 "verr\t$seg", []>, TB;
4111 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4112 "verr\t$seg", []>, TB;
4113 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4114 "verw\t$seg", []>, TB;
4115 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4116 "verw\t$seg", []>, TB;
4118 // Descriptor-table support instructions
4120 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4121 "sgdt\t$dst", []>, TB;
4122 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4123 "sidt\t$dst", []>, TB;
4124 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4125 "sldt{w}\t$dst", []>, TB;
4126 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4127 "sldt{w}\t$dst", []>, TB;
4128 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4129 "lgdt\t$src", []>, TB;
4130 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4131 "lidt\t$src", []>, TB;
4132 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4133 "lldt{w}\t$src", []>, TB;
4134 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4135 "lldt{w}\t$src", []>, TB;
4137 // Lock instruction prefix
4138 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4140 // Repeat string operation instruction prefixes
4141 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4142 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4143 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4144 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4145 // Repeat while not equal (used with CMPS and SCAS)
4146 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4149 // Segment override instruction prefixes
4150 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4151 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4152 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4153 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4154 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4155 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4157 // String manipulation instructions
4159 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4160 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4161 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4163 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4164 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4165 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4167 // CPU flow control instructions
4169 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4170 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4172 // FPU control instructions
4174 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4176 // Flag instructions
4178 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4179 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4180 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4181 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4182 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4183 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4184 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4186 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4188 // Table lookup instructions
4190 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4192 // Specialized register support
4194 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4195 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4196 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4198 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4199 "smsw{w}\t$dst", []>, OpSize, TB;
4200 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4201 "smsw{l}\t$dst", []>, TB;
4202 // For memory operands, there is only a 16-bit form
4203 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4204 "smsw{w}\t$dst", []>, TB;
4206 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4207 "lmsw{w}\t$src", []>, TB;
4208 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4209 "lmsw{w}\t$src", []>, TB;
4211 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4213 // Cache instructions
4215 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4216 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4221 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4223 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4225 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4226 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4227 "vmclear\t$vmcs", []>, OpSize, TB;
4229 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4231 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4232 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4233 "vmptrld\t$vmcs", []>, TB;
4234 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4235 "vmptrst\t$vmcs", []>, TB;
4236 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4237 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4238 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4239 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4240 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4241 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4242 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4243 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4244 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4245 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4246 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4247 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4248 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4249 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4250 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4251 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4253 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4254 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4255 "vmxon\t{$vmxon}", []>, XD;
4257 //===----------------------------------------------------------------------===//
4258 // Non-Instruction Patterns
4259 //===----------------------------------------------------------------------===//
4261 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4262 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4263 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4264 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4265 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4266 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4267 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4269 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4270 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4271 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4272 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4273 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4274 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4275 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4276 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4277 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4278 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4280 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4281 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4282 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4283 (MOV32mi addr:$dst, texternalsym:$src)>;
4284 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4285 (MOV32mi addr:$dst, tblockaddress:$src)>;
4289 def : Pat<(X86tcret GR32:$dst, imm:$off),
4290 (TCRETURNri GR32:$dst, imm:$off)>;
4292 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4293 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4295 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4296 (TCRETURNdi texternalsym:$dst, imm:$off)>;
4298 // Normal calls, with various flavors of addresses.
4299 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4300 (CALLpcrel32 tglobaladdr:$dst)>;
4301 def : Pat<(X86call (i32 texternalsym:$dst)),
4302 (CALLpcrel32 texternalsym:$dst)>;
4303 def : Pat<(X86call (i32 imm:$dst)),
4304 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4306 // X86 specific add which produces a flag.
4307 def : Pat<(addc GR32:$src1, GR32:$src2),
4308 (ADD32rr GR32:$src1, GR32:$src2)>;
4309 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4310 (ADD32rm GR32:$src1, addr:$src2)>;
4311 def : Pat<(addc GR32:$src1, imm:$src2),
4312 (ADD32ri GR32:$src1, imm:$src2)>;
4313 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4314 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4316 def : Pat<(subc GR32:$src1, GR32:$src2),
4317 (SUB32rr GR32:$src1, GR32:$src2)>;
4318 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4319 (SUB32rm GR32:$src1, addr:$src2)>;
4320 def : Pat<(subc GR32:$src1, imm:$src2),
4321 (SUB32ri GR32:$src1, imm:$src2)>;
4322 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4323 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4327 // TEST R,R is smaller than CMP R,0
4328 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
4329 (TEST8rr GR8:$src1, GR8:$src1)>;
4330 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
4331 (TEST16rr GR16:$src1, GR16:$src1)>;
4332 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
4333 (TEST32rr GR32:$src1, GR32:$src1)>;
4335 // Conditional moves with folded loads with operands swapped and conditions
4337 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4338 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4339 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4340 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4341 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4342 (CMOVB16rm GR16:$src2, addr:$src1)>;
4343 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4344 (CMOVB32rm GR32:$src2, addr:$src1)>;
4345 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4346 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4347 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4348 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4349 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4350 (CMOVE16rm GR16:$src2, addr:$src1)>;
4351 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4352 (CMOVE32rm GR32:$src2, addr:$src1)>;
4353 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4354 (CMOVA16rm GR16:$src2, addr:$src1)>;
4355 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4356 (CMOVA32rm GR32:$src2, addr:$src1)>;
4357 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4358 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4359 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4360 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4361 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4362 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4363 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4364 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4365 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4366 (CMOVL16rm GR16:$src2, addr:$src1)>;
4367 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4368 (CMOVL32rm GR32:$src2, addr:$src1)>;
4369 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4370 (CMOVG16rm GR16:$src2, addr:$src1)>;
4371 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4372 (CMOVG32rm GR32:$src2, addr:$src1)>;
4373 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4374 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4375 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4376 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4377 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4378 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4379 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4380 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4381 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4382 (CMOVP16rm GR16:$src2, addr:$src1)>;
4383 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4384 (CMOVP32rm GR32:$src2, addr:$src1)>;
4385 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4386 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4387 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4388 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4389 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4390 (CMOVS16rm GR16:$src2, addr:$src1)>;
4391 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4392 (CMOVS32rm GR32:$src2, addr:$src1)>;
4393 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4394 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4395 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4396 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4397 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4398 (CMOVO16rm GR16:$src2, addr:$src1)>;
4399 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4400 (CMOVO32rm GR32:$src2, addr:$src1)>;
4402 // zextload bool -> zextload byte
4403 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4404 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4405 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4407 // extload bool -> extload byte
4408 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4409 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4410 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4411 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4412 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4413 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4415 // anyext. Define these to do an explicit zero-extend to
4416 // avoid partial-register updates.
4417 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4418 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4419 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
4421 //===----------------------------------------------------------------------===//
4423 //===----------------------------------------------------------------------===//
4425 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4426 // +128 doesn't, so in this special case use a sub instead of an add.
4427 def : Pat<(add GR16:$src1, 128),
4428 (SUB16ri8 GR16:$src1, -128)>;
4429 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4430 (SUB16mi8 addr:$dst, -128)>;
4431 def : Pat<(add GR32:$src1, 128),
4432 (SUB32ri8 GR32:$src1, -128)>;
4433 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4434 (SUB32mi8 addr:$dst, -128)>;
4436 // r & (2^16-1) ==> movz
4437 def : Pat<(and GR32:$src1, 0xffff),
4438 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4439 // r & (2^8-1) ==> movz
4440 def : Pat<(and GR32:$src1, 0xff),
4441 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4444 Requires<[In32BitMode]>;
4445 // r & (2^8-1) ==> movz
4446 def : Pat<(and GR16:$src1, 0xff),
4447 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4450 Requires<[In32BitMode]>;
4452 // sext_inreg patterns
4453 def : Pat<(sext_inreg GR32:$src, i16),
4454 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4455 def : Pat<(sext_inreg GR32:$src, i8),
4456 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4459 Requires<[In32BitMode]>;
4460 def : Pat<(sext_inreg GR16:$src, i8),
4461 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4464 Requires<[In32BitMode]>;
4467 def : Pat<(i16 (trunc GR32:$src)),
4468 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4469 def : Pat<(i8 (trunc GR32:$src)),
4470 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4472 Requires<[In32BitMode]>;
4473 def : Pat<(i8 (trunc GR16:$src)),
4474 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4476 Requires<[In32BitMode]>;
4478 // h-register tricks
4479 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4480 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4481 x86_subreg_8bit_hi)>,
4482 Requires<[In32BitMode]>;
4483 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4484 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4485 x86_subreg_8bit_hi)>,
4486 Requires<[In32BitMode]>;
4487 def : Pat<(srl GR16:$src, (i8 8)),
4490 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4491 x86_subreg_8bit_hi)),
4493 Requires<[In32BitMode]>;
4494 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4495 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4497 x86_subreg_8bit_hi))>,
4498 Requires<[In32BitMode]>;
4499 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4500 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4502 x86_subreg_8bit_hi))>,
4503 Requires<[In32BitMode]>;
4504 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4505 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4507 x86_subreg_8bit_hi))>,
4508 Requires<[In32BitMode]>;
4510 // (shl x, 1) ==> (add x, x)
4511 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4512 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4513 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4515 // (shl x (and y, 31)) ==> (shl x, y)
4516 def : Pat<(shl GR8:$src1, (and CL, 31)),
4517 (SHL8rCL GR8:$src1)>;
4518 def : Pat<(shl GR16:$src1, (and CL, 31)),
4519 (SHL16rCL GR16:$src1)>;
4520 def : Pat<(shl GR32:$src1, (and CL, 31)),
4521 (SHL32rCL GR32:$src1)>;
4522 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4523 (SHL8mCL addr:$dst)>;
4524 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4525 (SHL16mCL addr:$dst)>;
4526 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4527 (SHL32mCL addr:$dst)>;
4529 def : Pat<(srl GR8:$src1, (and CL, 31)),
4530 (SHR8rCL GR8:$src1)>;
4531 def : Pat<(srl GR16:$src1, (and CL, 31)),
4532 (SHR16rCL GR16:$src1)>;
4533 def : Pat<(srl GR32:$src1, (and CL, 31)),
4534 (SHR32rCL GR32:$src1)>;
4535 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4536 (SHR8mCL addr:$dst)>;
4537 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4538 (SHR16mCL addr:$dst)>;
4539 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4540 (SHR32mCL addr:$dst)>;
4542 def : Pat<(sra GR8:$src1, (and CL, 31)),
4543 (SAR8rCL GR8:$src1)>;
4544 def : Pat<(sra GR16:$src1, (and CL, 31)),
4545 (SAR16rCL GR16:$src1)>;
4546 def : Pat<(sra GR32:$src1, (and CL, 31)),
4547 (SAR32rCL GR32:$src1)>;
4548 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4549 (SAR8mCL addr:$dst)>;
4550 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4551 (SAR16mCL addr:$dst)>;
4552 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4553 (SAR32mCL addr:$dst)>;
4555 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
4556 def : Pat<(or (srl GR32:$src1, CL:$amt),
4557 (shl GR32:$src2, (sub 32, CL:$amt))),
4558 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4560 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
4561 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4562 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4564 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
4565 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4566 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
4568 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4569 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4571 (SHRD32mrCL addr:$dst, GR32:$src2)>;
4573 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm/*:$amt2*/)),
4574 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4576 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
4577 GR32:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4578 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4580 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
4581 def : Pat<(or (shl GR32:$src1, CL:$amt),
4582 (srl GR32:$src2, (sub 32, CL:$amt))),
4583 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4585 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
4586 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
4587 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4589 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
4590 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4591 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
4593 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
4594 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
4596 (SHLD32mrCL addr:$dst, GR32:$src2)>;
4598 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm/*:$amt2*/)),
4599 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
4601 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
4602 GR32:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4603 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
4605 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
4606 def : Pat<(or (srl GR16:$src1, CL:$amt),
4607 (shl GR16:$src2, (sub 16, CL:$amt))),
4608 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4610 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
4611 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4612 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4614 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
4615 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4616 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
4618 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4619 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4621 (SHRD16mrCL addr:$dst, GR16:$src2)>;
4623 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm/*:$amt2*/)),
4624 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4626 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
4627 GR16:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4628 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4630 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
4631 def : Pat<(or (shl GR16:$src1, CL:$amt),
4632 (srl GR16:$src2, (sub 16, CL:$amt))),
4633 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4635 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
4636 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
4637 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4639 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
4640 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4641 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
4643 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
4644 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
4646 (SHLD16mrCL addr:$dst, GR16:$src2)>;
4648 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm/*:$amt2*/)),
4649 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
4651 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
4652 GR16:$src2, (i8 imm/*:$amt2*/)), addr:$dst),
4653 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
4655 // (anyext (setcc_carry)) -> (setcc_carry)
4656 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4658 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4661 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4662 let AddedComplexity = 5 in { // Try this before the selecting to OR
4663 def : Pat<(parallel (or_is_add GR16:$src1, imm:$src2),
4665 (ADD16ri GR16:$src1, imm:$src2)>;
4666 def : Pat<(parallel (or_is_add GR32:$src1, imm:$src2),
4668 (ADD32ri GR32:$src1, imm:$src2)>;
4669 def : Pat<(parallel (or_is_add GR16:$src1, i16immSExt8:$src2),
4671 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4672 def : Pat<(parallel (or_is_add GR32:$src1, i32immSExt8:$src2),
4674 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4675 def : Pat<(parallel (or_is_add GR16:$src1, GR16:$src2),
4677 (ADD16rr GR16:$src1, GR16:$src2)>;
4678 def : Pat<(parallel (or_is_add GR32:$src1, GR32:$src2),
4680 (ADD32rr GR32:$src1, GR32:$src2)>;
4681 } // AddedComplexity
4683 //===----------------------------------------------------------------------===//
4684 // EFLAGS-defining Patterns
4685 //===----------------------------------------------------------------------===//
4687 // Register-Register Addition with EFLAGS result
4688 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
4690 (ADD8rr GR8:$src1, GR8:$src2)>;
4691 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
4693 (ADD16rr GR16:$src1, GR16:$src2)>;
4694 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
4696 (ADD32rr GR32:$src1, GR32:$src2)>;
4698 // Register-Memory Addition with EFLAGS result
4699 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
4701 (ADD8rm GR8:$src1, addr:$src2)>;
4702 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
4704 (ADD16rm GR16:$src1, addr:$src2)>;
4705 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
4707 (ADD32rm GR32:$src1, addr:$src2)>;
4709 // Register-Integer Addition with EFLAGS result
4710 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
4712 (ADD8ri GR8:$src1, imm:$src2)>;
4713 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
4715 (ADD16ri GR16:$src1, imm:$src2)>;
4716 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
4718 (ADD32ri GR32:$src1, imm:$src2)>;
4719 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
4721 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4722 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
4724 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4726 // Memory-Register Addition with EFLAGS result
4727 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
4730 (ADD8mr addr:$dst, GR8:$src2)>;
4731 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
4734 (ADD16mr addr:$dst, GR16:$src2)>;
4735 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
4738 (ADD32mr addr:$dst, GR32:$src2)>;
4740 // Memory-Integer Addition with EFLAGS result
4741 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
4744 (ADD8mi addr:$dst, imm:$src2)>;
4745 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
4748 (ADD16mi addr:$dst, imm:$src2)>;
4749 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
4752 (ADD32mi addr:$dst, imm:$src2)>;
4753 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4756 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
4757 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4760 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
4762 // Register-Register Subtraction with EFLAGS result
4763 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
4765 (SUB8rr GR8:$src1, GR8:$src2)>;
4766 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
4768 (SUB16rr GR16:$src1, GR16:$src2)>;
4769 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
4771 (SUB32rr GR32:$src1, GR32:$src2)>;
4773 // Register-Memory Subtraction with EFLAGS result
4774 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
4776 (SUB8rm GR8:$src1, addr:$src2)>;
4777 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
4779 (SUB16rm GR16:$src1, addr:$src2)>;
4780 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
4782 (SUB32rm GR32:$src1, addr:$src2)>;
4784 // Register-Integer Subtraction with EFLAGS result
4785 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
4787 (SUB8ri GR8:$src1, imm:$src2)>;
4788 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
4790 (SUB16ri GR16:$src1, imm:$src2)>;
4791 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
4793 (SUB32ri GR32:$src1, imm:$src2)>;
4794 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
4796 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4797 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
4799 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4801 // Memory-Register Subtraction with EFLAGS result
4802 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
4805 (SUB8mr addr:$dst, GR8:$src2)>;
4806 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
4809 (SUB16mr addr:$dst, GR16:$src2)>;
4810 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
4813 (SUB32mr addr:$dst, GR32:$src2)>;
4815 // Memory-Integer Subtraction with EFLAGS result
4816 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
4819 (SUB8mi addr:$dst, imm:$src2)>;
4820 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
4823 (SUB16mi addr:$dst, imm:$src2)>;
4824 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
4827 (SUB32mi addr:$dst, imm:$src2)>;
4828 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4831 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
4832 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4835 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
4838 // Register-Register Signed Integer Multiply with EFLAGS result
4839 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
4841 (IMUL16rr GR16:$src1, GR16:$src2)>;
4842 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
4844 (IMUL32rr GR32:$src1, GR32:$src2)>;
4846 // Register-Memory Signed Integer Multiply with EFLAGS result
4847 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
4849 (IMUL16rm GR16:$src1, addr:$src2)>;
4850 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
4852 (IMUL32rm GR32:$src1, addr:$src2)>;
4854 // Register-Integer Signed Integer Multiply with EFLAGS result
4855 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
4857 (IMUL16rri GR16:$src1, imm:$src2)>;
4858 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
4860 (IMUL32rri GR32:$src1, imm:$src2)>;
4861 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
4863 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4864 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
4866 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4868 // Memory-Integer Signed Integer Multiply with EFLAGS result
4869 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
4871 (IMUL16rmi addr:$src1, imm:$src2)>;
4872 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
4874 (IMUL32rmi addr:$src1, imm:$src2)>;
4875 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
4877 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4878 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
4880 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4882 // Optimize multiply by 2 with EFLAGS result.
4883 let AddedComplexity = 2 in {
4884 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
4886 (ADD16rr GR16:$src1, GR16:$src1)>;
4888 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
4890 (ADD32rr GR32:$src1, GR32:$src1)>;
4893 // INC and DEC with EFLAGS result. Note that these do not set CF.
4894 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
4896 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
4899 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
4901 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
4905 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
4906 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4907 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
4909 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
4910 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
4911 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4912 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
4914 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
4916 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
4917 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4918 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
4920 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
4921 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
4922 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4923 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
4925 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
4927 // Register-Register Or with EFLAGS result
4928 def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
4930 (OR8rr GR8:$src1, GR8:$src2)>;
4931 def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2),
4933 (OR16rr GR16:$src1, GR16:$src2)>;
4934 def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2),
4936 (OR32rr GR32:$src1, GR32:$src2)>;
4938 // Register-Memory Or with EFLAGS result
4939 def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)),
4941 (OR8rm GR8:$src1, addr:$src2)>;
4942 def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)),
4944 (OR16rm GR16:$src1, addr:$src2)>;
4945 def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)),
4947 (OR32rm GR32:$src1, addr:$src2)>;
4949 // Register-Integer Or with EFLAGS result
4950 def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2),
4952 (OR8ri GR8:$src1, imm:$src2)>;
4953 def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2),
4955 (OR16ri GR16:$src1, imm:$src2)>;
4956 def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2),
4958 (OR32ri GR32:$src1, imm:$src2)>;
4959 def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
4961 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4962 def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
4964 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4966 // Memory-Register Or with EFLAGS result
4967 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
4970 (OR8mr addr:$dst, GR8:$src2)>;
4971 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2),
4974 (OR16mr addr:$dst, GR16:$src2)>;
4975 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2),
4978 (OR32mr addr:$dst, GR32:$src2)>;
4980 // Memory-Integer Or with EFLAGS result
4981 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2),
4984 (OR8mi addr:$dst, imm:$src2)>;
4985 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2),
4988 (OR16mi addr:$dst, imm:$src2)>;
4989 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2),
4992 (OR32mi addr:$dst, imm:$src2)>;
4993 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4996 (OR16mi8 addr:$dst, i16immSExt8:$src2)>;
4997 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5000 (OR32mi8 addr:$dst, i32immSExt8:$src2)>;
5002 // Register-Register XOr with EFLAGS result
5003 def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
5005 (XOR8rr GR8:$src1, GR8:$src2)>;
5006 def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2),
5008 (XOR16rr GR16:$src1, GR16:$src2)>;
5009 def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2),
5011 (XOR32rr GR32:$src1, GR32:$src2)>;
5013 // Register-Memory XOr with EFLAGS result
5014 def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)),
5016 (XOR8rm GR8:$src1, addr:$src2)>;
5017 def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)),
5019 (XOR16rm GR16:$src1, addr:$src2)>;
5020 def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)),
5022 (XOR32rm GR32:$src1, addr:$src2)>;
5024 // Register-Integer XOr with EFLAGS result
5025 def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2),
5027 (XOR8ri GR8:$src1, imm:$src2)>;
5028 def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2),
5030 (XOR16ri GR16:$src1, imm:$src2)>;
5031 def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2),
5033 (XOR32ri GR32:$src1, imm:$src2)>;
5034 def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2),
5036 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
5037 def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
5039 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
5041 // Memory-Register XOr with EFLAGS result
5042 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
5045 (XOR8mr addr:$dst, GR8:$src2)>;
5046 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2),
5049 (XOR16mr addr:$dst, GR16:$src2)>;
5050 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2),
5053 (XOR32mr addr:$dst, GR32:$src2)>;
5055 // Memory-Integer XOr with EFLAGS result
5056 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2),
5059 (XOR8mi addr:$dst, imm:$src2)>;
5060 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2),
5063 (XOR16mi addr:$dst, imm:$src2)>;
5064 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2),
5067 (XOR32mi addr:$dst, imm:$src2)>;
5068 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5071 (XOR16mi8 addr:$dst, i16immSExt8:$src2)>;
5072 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5075 (XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
5077 // Register-Register And with EFLAGS result
5078 def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
5080 (AND8rr GR8:$src1, GR8:$src2)>;
5081 def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2),
5083 (AND16rr GR16:$src1, GR16:$src2)>;
5084 def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2),
5086 (AND32rr GR32:$src1, GR32:$src2)>;
5088 // Register-Memory And with EFLAGS result
5089 def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)),
5091 (AND8rm GR8:$src1, addr:$src2)>;
5092 def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)),
5094 (AND16rm GR16:$src1, addr:$src2)>;
5095 def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)),
5097 (AND32rm GR32:$src1, addr:$src2)>;
5099 // Register-Integer And with EFLAGS result
5100 def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2),
5102 (AND8ri GR8:$src1, imm:$src2)>;
5103 def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2),
5105 (AND16ri GR16:$src1, imm:$src2)>;
5106 def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2),
5108 (AND32ri GR32:$src1, imm:$src2)>;
5109 def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2),
5111 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
5112 def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
5114 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
5116 // Memory-Register And with EFLAGS result
5117 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
5120 (AND8mr addr:$dst, GR8:$src2)>;
5121 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2),
5124 (AND16mr addr:$dst, GR16:$src2)>;
5125 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2),
5128 (AND32mr addr:$dst, GR32:$src2)>;
5130 // Memory-Integer And with EFLAGS result
5131 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2),
5134 (AND8mi addr:$dst, imm:$src2)>;
5135 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2),
5138 (AND16mi addr:$dst, imm:$src2)>;
5139 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2),
5142 (AND32mi addr:$dst, imm:$src2)>;
5143 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2),
5146 (AND16mi8 addr:$dst, i16immSExt8:$src2)>;
5147 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
5150 (AND32mi8 addr:$dst, i32immSExt8:$src2)>;
5152 // -disable-16bit support.
5153 def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
5154 (MOV16mi addr:$dst, imm:$src)>;
5155 def : Pat<(truncstorei16 GR32:$src, addr:$dst),
5156 (MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
5157 def : Pat<(i32 (sextloadi16 addr:$dst)),
5158 (MOVSX32rm16 addr:$dst)>;
5159 def : Pat<(i32 (zextloadi16 addr:$dst)),
5160 (MOVZX32rm16 addr:$dst)>;
5161 def : Pat<(i32 (extloadi16 addr:$dst)),
5162 (MOVZX32rm16 addr:$dst)>;
5164 //===----------------------------------------------------------------------===//
5165 // Floating Point Stack Support
5166 //===----------------------------------------------------------------------===//
5168 include "X86InstrFPStack.td"
5170 //===----------------------------------------------------------------------===//
5172 //===----------------------------------------------------------------------===//
5174 include "X86Instr64bit.td"
5176 //===----------------------------------------------------------------------===//
5177 // SIMD support (SSE, MMX and AVX)
5178 //===----------------------------------------------------------------------===//
5180 include "X86InstrFragmentsSIMD.td"
5182 //===----------------------------------------------------------------------===//
5183 // XMM Floating point support (requires SSE / SSE2)
5184 //===----------------------------------------------------------------------===//
5186 include "X86InstrSSE.td"
5188 //===----------------------------------------------------------------------===//
5189 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
5190 //===----------------------------------------------------------------------===//
5192 include "X86InstrMMX.td"