1 //===----------------------------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
79 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
81 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
82 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
83 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
84 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
86 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
87 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
89 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
90 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
92 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
93 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
95 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
96 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
98 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
99 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
101 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
102 [SDNPHasChain, SDNPMayStore,
103 SDNPMayLoad, SDNPMemOperand]>;
104 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
105 [SDNPHasChain, SDNPMayStore,
106 SDNPMayLoad, SDNPMemOperand]>;
107 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
108 [SDNPHasChain, SDNPMayStore,
109 SDNPMayLoad, SDNPMemOperand]>;
110 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
111 [SDNPHasChain, SDNPMayStore,
112 SDNPMayLoad, SDNPMemOperand]>;
113 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
114 [SDNPHasChain, SDNPMayStore,
115 SDNPMayLoad, SDNPMemOperand]>;
116 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
117 [SDNPHasChain, SDNPMayStore,
118 SDNPMayLoad, SDNPMemOperand]>;
119 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
120 [SDNPHasChain, SDNPMayStore,
121 SDNPMayLoad, SDNPMemOperand]>;
122 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
123 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
125 def X86vastart_save_xmm_regs :
126 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
127 SDT_X86VASTART_SAVE_XMM_REGS,
128 [SDNPHasChain, SDNPVariadic]>;
130 def X86callseq_start :
131 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
132 [SDNPHasChain, SDNPOutFlag]>;
134 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
135 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
137 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
138 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
141 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
142 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
143 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
144 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
147 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
148 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
150 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
151 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
153 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
154 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
155 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
156 SDT_X86SegmentBaseAddress, []>;
158 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
161 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
162 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
164 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
166 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
167 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
169 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
172 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
173 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
174 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
176 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
178 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
181 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
183 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
184 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
186 //===----------------------------------------------------------------------===//
187 // X86 Operand Definitions.
190 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
191 // the index operand of an address, to conform to x86 encoding restrictions.
192 def ptr_rc_nosp : PointerLikeRegClass<1>;
194 // *mem - Operand definitions for the funky X86 addressing mode operands.
196 def X86MemAsmOperand : AsmOperandClass {
200 def X86NoSegMemAsmOperand : AsmOperandClass {
201 let Name = "NoSegMem";
202 let SuperClass = X86MemAsmOperand;
204 def X86AbsMemAsmOperand : AsmOperandClass {
206 let SuperClass = X86NoSegMemAsmOperand;
208 class X86MemOperand<string printMethod> : Operand<iPTR> {
209 let PrintMethod = printMethod;
210 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
211 let ParserMatchClass = X86MemAsmOperand;
214 def opaque32mem : X86MemOperand<"printopaquemem">;
215 def opaque48mem : X86MemOperand<"printopaquemem">;
216 def opaque80mem : X86MemOperand<"printopaquemem">;
217 def opaque512mem : X86MemOperand<"printopaquemem">;
219 def i8mem : X86MemOperand<"printi8mem">;
220 def i16mem : X86MemOperand<"printi16mem">;
221 def i32mem : X86MemOperand<"printi32mem">;
222 def i64mem : X86MemOperand<"printi64mem">;
223 def i128mem : X86MemOperand<"printi128mem">;
224 //def i256mem : X86MemOperand<"printi256mem">;
225 def f32mem : X86MemOperand<"printf32mem">;
226 def f64mem : X86MemOperand<"printf64mem">;
227 def f80mem : X86MemOperand<"printf80mem">;
228 def f128mem : X86MemOperand<"printf128mem">;
229 //def f256mem : X86MemOperand<"printf256mem">;
231 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
232 // plain GR64, so that it doesn't potentially require a REX prefix.
233 def i8mem_NOREX : Operand<i64> {
234 let PrintMethod = "printi8mem";
235 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
236 let ParserMatchClass = X86MemAsmOperand;
239 // Special i32mem for addresses of load folding tail calls. These are not
240 // allowed to use callee-saved registers since they must be scheduled
241 // after callee-saved register are popped.
242 def i32mem_TC : Operand<i32> {
243 let PrintMethod = "printi32mem";
244 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
245 let ParserMatchClass = X86MemAsmOperand;
248 def lea32mem : Operand<i32> {
249 let PrintMethod = "printlea32mem";
250 let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
251 let ParserMatchClass = X86NoSegMemAsmOperand;
254 let ParserMatchClass = X86AbsMemAsmOperand,
255 PrintMethod = "print_pcrel_imm" in {
256 def i32imm_pcrel : Operand<i32>;
258 def offset8 : Operand<i64>;
259 def offset16 : Operand<i64>;
260 def offset32 : Operand<i64>;
261 def offset64 : Operand<i64>;
263 // Branch targets have OtherVT type and print as pc-relative values.
264 def brtarget : Operand<OtherVT>;
265 def brtarget8 : Operand<OtherVT>;
269 def SSECC : Operand<i8> {
270 let PrintMethod = "printSSECC";
273 def ImmSExt8AsmOperand : AsmOperandClass {
274 let Name = "ImmSExt8";
275 let SuperClass = ImmAsmOperand;
278 // A couple of more descriptive operand definitions.
279 // 16-bits but only 8 bits are significant.
280 def i16i8imm : Operand<i16> {
281 let ParserMatchClass = ImmSExt8AsmOperand;
283 // 32-bits but only 8 bits are significant.
284 def i32i8imm : Operand<i32> {
285 let ParserMatchClass = ImmSExt8AsmOperand;
288 //===----------------------------------------------------------------------===//
289 // X86 Complex Pattern Definitions.
292 // Define X86 specific addressing mode.
293 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
294 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
295 [add, sub, mul, X86mul_imm, shl, or, frameindex],
297 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
298 [tglobaltlsaddr], []>;
300 //===----------------------------------------------------------------------===//
301 // X86 Instruction Predicate Definitions.
302 def HasCMov : Predicate<"Subtarget->hasCMov()">;
303 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
304 def HasMMX : Predicate<"Subtarget->hasMMX()">;
305 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
306 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
307 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
308 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
309 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
310 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
311 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
312 def HasAVX : Predicate<"Subtarget->hasAVX()">;
313 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
314 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
315 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
316 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
317 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
318 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
319 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
320 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
321 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
322 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
323 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
324 "TM.getCodeModel() != CodeModel::Kernel">;
325 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
326 "TM.getCodeModel() == CodeModel::Kernel">;
327 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
328 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
329 def OptForSize : Predicate<"OptForSize">;
330 def OptForSpeed : Predicate<"!OptForSize">;
331 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
332 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
333 def HasAES : Predicate<"Subtarget->hasAES()">;
335 //===----------------------------------------------------------------------===//
336 // X86 Instruction Format Definitions.
339 include "X86InstrFormats.td"
341 //===----------------------------------------------------------------------===//
342 // Pattern fragments...
345 // X86 specific condition code. These correspond to CondCode in
346 // X86InstrInfo.h. They must be kept in synch.
347 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
348 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
349 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
350 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
351 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
352 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
353 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
354 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
355 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
356 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
357 def X86_COND_NO : PatLeaf<(i8 10)>;
358 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
359 def X86_COND_NS : PatLeaf<(i8 12)>;
360 def X86_COND_O : PatLeaf<(i8 13)>;
361 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
362 def X86_COND_S : PatLeaf<(i8 15)>;
364 def immSext8 : PatLeaf<(imm), [{
365 return N->getSExtValue() == (int8_t)N->getSExtValue();
368 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
369 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
371 /// Load patterns: these constraint the match to the right address space.
372 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
373 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
374 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
375 if (PT->getAddressSpace() > 255)
380 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
381 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
382 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
383 return PT->getAddressSpace() == 256;
387 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
388 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
389 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
390 return PT->getAddressSpace() == 257;
395 // Helper fragments for loads.
396 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
397 // known to be 32-bit aligned or better. Ditto for i8 to i16.
398 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
399 LoadSDNode *LD = cast<LoadSDNode>(N);
400 if (const Value *Src = LD->getSrcValue())
401 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
402 if (PT->getAddressSpace() > 255)
404 ISD::LoadExtType ExtType = LD->getExtensionType();
405 if (ExtType == ISD::NON_EXTLOAD)
407 if (ExtType == ISD::EXTLOAD)
408 return LD->getAlignment() >= 2 && !LD->isVolatile();
412 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
413 LoadSDNode *LD = cast<LoadSDNode>(N);
414 if (const Value *Src = LD->getSrcValue())
415 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
416 if (PT->getAddressSpace() > 255)
418 ISD::LoadExtType ExtType = LD->getExtensionType();
419 if (ExtType == ISD::EXTLOAD)
420 return LD->getAlignment() >= 2 && !LD->isVolatile();
424 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
425 LoadSDNode *LD = cast<LoadSDNode>(N);
426 if (const Value *Src = LD->getSrcValue())
427 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
428 if (PT->getAddressSpace() > 255)
430 ISD::LoadExtType ExtType = LD->getExtensionType();
431 if (ExtType == ISD::NON_EXTLOAD)
433 if (ExtType == ISD::EXTLOAD)
434 return LD->getAlignment() >= 4 && !LD->isVolatile();
438 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
439 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
440 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
441 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
442 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
444 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
445 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
446 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
448 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
449 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
450 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
451 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
452 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
453 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
455 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
456 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
457 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
458 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
459 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
460 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
463 // An 'and' node with a single use.
464 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
465 return N->hasOneUse();
467 // An 'srl' node with a single use.
468 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
469 return N->hasOneUse();
471 // An 'trunc' node with a single use.
472 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
473 return N->hasOneUse();
476 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
477 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
478 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
479 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
481 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
482 APInt Mask = APInt::getAllOnesValue(BitWidth);
483 APInt KnownZero0, KnownOne0;
484 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
485 APInt KnownZero1, KnownOne1;
486 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
487 return (~KnownZero0 & ~KnownZero1) == 0;
490 //===----------------------------------------------------------------------===//
491 // Instruction list...
494 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
495 // a stack adjustment and the codegen must know that they may modify the stack
496 // pointer before prolog-epilog rewriting occurs.
497 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
498 // sub / add which can clobber EFLAGS.
499 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
500 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
502 [(X86callseq_start timm:$amt)]>,
503 Requires<[In32BitMode]>;
504 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
506 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
507 Requires<[In32BitMode]>;
510 // x86-64 va_start lowering magic.
511 let usesCustomInserter = 1 in {
512 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
515 i64imm:$regsavefi, i64imm:$offset,
517 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
518 [(X86vastart_save_xmm_regs GR8:$al,
522 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
523 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
524 // one go. Touching the stack at 4K increments is necessary to ensure that the
525 // guard pages used by the OS virtual memory manager are allocated in correct
527 // The main point of having separate instruction are extra unmodelled effects
528 // (compared to ordinary calls) like stack pointer change.
530 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
531 "# dynamic stack allocation",
536 let neverHasSideEffects = 1 in {
537 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
538 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
539 "nop{w}\t$zero", []>, TB, OpSize;
540 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
541 "nop{l}\t$zero", []>, TB;
545 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
546 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", []>;
547 // FIXME: need to make sure that "int $3" matches int3
548 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
549 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
550 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
552 // PIC base construction. This expands to code that looks like this:
555 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
556 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
559 //===----------------------------------------------------------------------===//
560 // Control Flow Instructions.
563 // Return instructions.
564 let isTerminator = 1, isReturn = 1, isBarrier = 1,
565 hasCtrlDep = 1, FPForm = SpecialFP in {
566 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
569 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
571 [(X86retflag timm:$amt)]>;
572 def LRET : I <0xCB, RawFrm, (outs), (ins),
574 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
578 // Unconditional branches.
579 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
580 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
581 "jmp\t$dst", [(br bb:$dst)]>;
582 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
586 // Conditional Branches.
587 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
588 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
589 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
590 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
591 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
595 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
596 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
597 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
598 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
599 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
600 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
601 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
602 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
603 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
604 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
605 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
606 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
607 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
608 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
609 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
610 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
612 // FIXME: What about the CX/RCX versions of this instruction?
613 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
614 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
619 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
620 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
621 [(brind GR32:$dst)]>;
622 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
623 [(brind (loadi32 addr:$dst))]>;
625 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
626 (ins i16imm:$seg, i16imm:$off),
627 "ljmp{w}\t$seg, $off", []>, OpSize;
628 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
629 (ins i16imm:$seg, i32imm:$off),
630 "ljmp{l}\t$seg, $off", []>;
632 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
633 "ljmp{w}\t{*}$dst", []>, OpSize;
634 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
635 "ljmp{l}\t{*}$dst", []>;
641 def LOOP : I<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
642 def LOOPE : I<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
643 def LOOPNE : I<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
645 //===----------------------------------------------------------------------===//
646 // Call Instructions...
649 // All calls clobber the non-callee saved registers. ESP is marked as
650 // a use to prevent stack-pointer assignments that appear immediately
651 // before calls from potentially appearing dead. Uses for argument
652 // registers are added manually.
653 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
654 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
655 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
656 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
658 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
659 (outs), (ins i32imm_pcrel:$dst,variable_ops),
661 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
662 "call\t{*}$dst", [(X86call GR32:$dst)]>;
663 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
664 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
666 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
667 (ins i16imm:$seg, i16imm:$off),
668 "lcall{w}\t$seg, $off", []>, OpSize;
669 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
670 (ins i16imm:$seg, i32imm:$off),
671 "lcall{l}\t$seg, $off", []>;
673 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
674 "lcall{w}\t{*}$dst", []>, OpSize;
675 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
676 "lcall{l}\t{*}$dst", []>;
679 // Constructing a stack frame.
681 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
682 "enter\t$len, $lvl", []>;
686 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
687 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
688 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
689 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
690 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
692 def TCRETURNdi : I<0, Pseudo, (outs),
693 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
694 "#TC_RETURN $dst $offset", []>;
695 def TCRETURNri : I<0, Pseudo, (outs),
696 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
697 "#TC_RETURN $dst $offset", []>;
699 def TCRETURNmi : I<0, Pseudo, (outs),
700 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
701 "#TC_RETURN $dst $offset", []>;
703 // FIXME: The should be pseudo instructions that are lowered when going to
705 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
706 (ins i32imm_pcrel:$dst, variable_ops),
707 "jmp\t$dst # TAILCALL",
709 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
710 "jmp{l}\t{*}$dst # TAILCALL",
713 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
714 "jmp{l}\t{*}$dst # TAILCALL", []>;
716 // FIXME: This is a hack so that MCInst lowering can preserve the TAILCALL
717 // marker on instructions, while still being able to relax.
718 let isCodeGenOnly = 1 in {
719 def TAILJMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
720 "jmp\t$dst # TAILCALL", []>;
724 //===----------------------------------------------------------------------===//
725 // Miscellaneous Instructions...
727 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
728 def LEAVE : I<0xC9, RawFrm,
729 (outs), (ins), "leave", []>;
731 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
732 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
734 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
735 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
736 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
737 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
739 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
740 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
742 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
744 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
746 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
747 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
749 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
751 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
752 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
755 let mayStore = 1 in {
756 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
758 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
759 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
761 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
763 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
764 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
768 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
769 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
770 "push{l}\t$imm", []>;
771 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
772 "push{w}\t$imm", []>, OpSize;
773 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
774 "push{l}\t$imm", []>;
777 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
778 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
779 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
780 Requires<[In32BitMode]>;
782 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
783 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
784 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
785 Requires<[In32BitMode]>;
788 let isTwoAddress = 1 in // GR32 = bswap GR32
789 def BSWAP32r : I<0xC8, AddRegFrm,
790 (outs GR32:$dst), (ins GR32:$src),
792 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
795 // Bit scan instructions.
796 let Defs = [EFLAGS] in {
797 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
798 "bsf{w}\t{$src, $dst|$dst, $src}",
799 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
800 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
801 "bsf{w}\t{$src, $dst|$dst, $src}",
802 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
804 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
805 "bsf{l}\t{$src, $dst|$dst, $src}",
806 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
807 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
808 "bsf{l}\t{$src, $dst|$dst, $src}",
809 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
811 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
812 "bsr{w}\t{$src, $dst|$dst, $src}",
813 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
814 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
815 "bsr{w}\t{$src, $dst|$dst, $src}",
816 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
818 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
819 "bsr{l}\t{$src, $dst|$dst, $src}",
820 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
821 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
822 "bsr{l}\t{$src, $dst|$dst, $src}",
823 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
826 let neverHasSideEffects = 1 in
827 def LEA16r : I<0x8D, MRMSrcMem,
828 (outs GR16:$dst), (ins lea32mem:$src),
829 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
830 let isReMaterializable = 1 in
831 def LEA32r : I<0x8D, MRMSrcMem,
832 (outs GR32:$dst), (ins lea32mem:$src),
833 "lea{l}\t{$src|$dst}, {$dst|$src}",
834 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
836 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
837 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
838 [(X86rep_movs i8)]>, REP;
839 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
840 [(X86rep_movs i16)]>, REP, OpSize;
841 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
842 [(X86rep_movs i32)]>, REP;
845 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
846 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
847 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
848 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
849 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
852 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
853 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
854 [(X86rep_stos i8)]>, REP;
855 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
856 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
857 [(X86rep_stos i16)]>, REP, OpSize;
858 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
859 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
860 [(X86rep_stos i32)]>, REP;
862 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
863 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
864 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
865 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
866 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
867 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
868 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
870 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
871 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
872 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
874 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
875 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
876 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
878 let Defs = [RAX, RDX] in
879 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
882 let Defs = [RAX, RCX, RDX] in
883 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
885 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
886 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
889 def SYSCALL : I<0x05, RawFrm,
890 (outs), (ins), "syscall", []>, TB;
891 def SYSRET : I<0x07, RawFrm,
892 (outs), (ins), "sysret", []>, TB;
893 def SYSENTER : I<0x34, RawFrm,
894 (outs), (ins), "sysenter", []>, TB;
895 def SYSEXIT : I<0x35, RawFrm,
896 (outs), (ins), "sysexit", []>, TB;
898 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
901 //===----------------------------------------------------------------------===//
902 // Input/Output Instructions...
904 let Defs = [AL], Uses = [DX] in
905 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
906 "in{b}\t{%dx, %al|%AL, %DX}", []>;
907 let Defs = [AX], Uses = [DX] in
908 def IN16rr : I<0xED, RawFrm, (outs), (ins),
909 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
910 let Defs = [EAX], Uses = [DX] in
911 def IN32rr : I<0xED, RawFrm, (outs), (ins),
912 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
915 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
916 "in{b}\t{$port, %al|%AL, $port}", []>;
918 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
919 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
921 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
922 "in{l}\t{$port, %eax|%EAX, $port}", []>;
924 let Uses = [DX, AL] in
925 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
926 "out{b}\t{%al, %dx|%DX, %AL}", []>;
927 let Uses = [DX, AX] in
928 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
929 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
930 let Uses = [DX, EAX] in
931 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
932 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
935 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
936 "out{b}\t{%al, $port|$port, %AL}", []>;
938 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
939 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
941 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
942 "out{l}\t{%eax, $port|$port, %EAX}", []>;
944 def IN8 : I<0x6C, RawFrm, (outs), (ins),
946 def IN16 : I<0x6D, RawFrm, (outs), (ins),
947 "ins{w}", []>, OpSize;
948 def IN32 : I<0x6D, RawFrm, (outs), (ins),
951 //===----------------------------------------------------------------------===//
952 // Move Instructions...
954 let neverHasSideEffects = 1 in {
955 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
956 "mov{b}\t{$src, $dst|$dst, $src}", []>;
957 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
958 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
959 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
960 "mov{l}\t{$src, $dst|$dst, $src}", []>;
962 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
963 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
964 "mov{b}\t{$src, $dst|$dst, $src}",
965 [(set GR8:$dst, imm:$src)]>;
966 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
967 "mov{w}\t{$src, $dst|$dst, $src}",
968 [(set GR16:$dst, imm:$src)]>, OpSize;
969 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
970 "mov{l}\t{$src, $dst|$dst, $src}",
971 [(set GR32:$dst, imm:$src)]>;
974 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
975 "mov{b}\t{$src, $dst|$dst, $src}",
976 [(store (i8 imm:$src), addr:$dst)]>;
977 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
978 "mov{w}\t{$src, $dst|$dst, $src}",
979 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
980 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
981 "mov{l}\t{$src, $dst|$dst, $src}",
982 [(store (i32 imm:$src), addr:$dst)]>;
984 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
985 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
986 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
987 "mov{b}\t{$src, %al|%al, $src}", []>;
988 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
989 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
990 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
991 "mov{l}\t{$src, %eax|%eax, $src}", []>;
992 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
993 "mov{b}\t{%al, $dst|$dst, %al}", []>;
994 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
995 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize;
996 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
997 "mov{l}\t{%eax, $dst|$dst, %eax}", []>;
999 // Moves to and from segment registers
1000 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1001 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1002 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1003 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1004 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1005 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1006 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1007 "mov{w}\t{$src, $dst|$dst, $src}", []>;
1009 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1010 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1011 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1012 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1013 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1014 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1016 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1017 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1018 "mov{b}\t{$src, $dst|$dst, $src}",
1019 [(set GR8:$dst, (loadi8 addr:$src))]>;
1020 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1021 "mov{w}\t{$src, $dst|$dst, $src}",
1022 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1023 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1024 "mov{l}\t{$src, $dst|$dst, $src}",
1025 [(set GR32:$dst, (loadi32 addr:$src))]>;
1028 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1029 "mov{b}\t{$src, $dst|$dst, $src}",
1030 [(store GR8:$src, addr:$dst)]>;
1031 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1032 "mov{w}\t{$src, $dst|$dst, $src}",
1033 [(store GR16:$src, addr:$dst)]>, OpSize;
1034 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1035 "mov{l}\t{$src, $dst|$dst, $src}",
1036 [(store GR32:$src, addr:$dst)]>;
1038 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1039 let neverHasSideEffects = 1 in
1040 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1041 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1044 canFoldAsLoad = 1, isReMaterializable = 1 in
1045 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1046 "mov{l}\t{$src, $dst|$dst, $src}",
1050 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1051 "mov{l}\t{$src, $dst|$dst, $src}",
1054 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1055 // that they can be used for copying and storing h registers, which can't be
1056 // encoded when a REX prefix is present.
1057 let neverHasSideEffects = 1 in
1058 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1059 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1060 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1062 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1063 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1064 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1066 canFoldAsLoad = 1, isReMaterializable = 1 in
1067 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1068 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1069 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1071 // Moves to and from debug registers
1072 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1073 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1074 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1075 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1077 // Moves to and from control registers
1078 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
1079 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1080 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
1081 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1083 //===----------------------------------------------------------------------===//
1084 // Fixed-Register Multiplication and Division Instructions...
1087 // Extra precision multiplication
1089 // AL is really implied by AX, by the registers in Defs must match the
1090 // SDNode results (i8, i32).
1091 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1092 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1093 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1094 // This probably ought to be moved to a def : Pat<> if the
1095 // syntax can be accepted.
1096 [(set AL, (mul AL, GR8:$src)),
1097 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1099 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1100 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1102 []>, OpSize; // AX,DX = AX*GR16
1104 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1105 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1107 []>; // EAX,EDX = EAX*GR32
1109 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1110 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1112 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1113 // This probably ought to be moved to a def : Pat<> if the
1114 // syntax can be accepted.
1115 [(set AL, (mul AL, (loadi8 addr:$src))),
1116 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1118 let mayLoad = 1, neverHasSideEffects = 1 in {
1119 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1120 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1122 []>, OpSize; // AX,DX = AX*[mem16]
1124 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1125 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1127 []>; // EAX,EDX = EAX*[mem32]
1130 let neverHasSideEffects = 1 in {
1131 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1132 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1134 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1135 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1136 OpSize; // AX,DX = AX*GR16
1137 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1138 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1139 // EAX,EDX = EAX*GR32
1140 let mayLoad = 1 in {
1141 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1142 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1143 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1144 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1145 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1146 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1147 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1148 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1149 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1151 } // neverHasSideEffects
1153 // unsigned division/remainder
1154 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1155 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1156 "div{b}\t$src", []>;
1157 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1158 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1159 "div{w}\t$src", []>, OpSize;
1160 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1161 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1162 "div{l}\t$src", []>;
1163 let mayLoad = 1 in {
1164 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1165 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1166 "div{b}\t$src", []>;
1167 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1168 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1169 "div{w}\t$src", []>, OpSize;
1170 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1171 // EDX:EAX/[mem32] = EAX,EDX
1172 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1173 "div{l}\t$src", []>;
1176 // Signed division/remainder.
1177 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1178 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1179 "idiv{b}\t$src", []>;
1180 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1181 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1182 "idiv{w}\t$src", []>, OpSize;
1183 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1184 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1185 "idiv{l}\t$src", []>;
1186 let mayLoad = 1, mayLoad = 1 in {
1187 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1188 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1189 "idiv{b}\t$src", []>;
1190 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1191 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1192 "idiv{w}\t$src", []>, OpSize;
1193 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1194 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1195 // EDX:EAX/[mem32] = EAX,EDX
1196 "idiv{l}\t$src", []>;
1199 //===----------------------------------------------------------------------===//
1200 // Two address Instructions.
1202 let isTwoAddress = 1 in {
1204 // Conditional moves
1205 let Uses = [EFLAGS] in {
1207 let Predicates = [HasCMov] in {
1208 let isCommutable = 1 in {
1209 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1210 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1211 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1212 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1213 X86_COND_B, EFLAGS))]>,
1215 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1216 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1217 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1218 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1219 X86_COND_B, EFLAGS))]>,
1221 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1222 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1223 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1224 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1225 X86_COND_AE, EFLAGS))]>,
1227 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1228 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1229 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1230 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1231 X86_COND_AE, EFLAGS))]>,
1233 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1234 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1235 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1236 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1237 X86_COND_E, EFLAGS))]>,
1239 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1240 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1241 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1242 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1243 X86_COND_E, EFLAGS))]>,
1245 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1246 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1247 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1248 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1249 X86_COND_NE, EFLAGS))]>,
1251 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1252 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1253 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1254 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1255 X86_COND_NE, EFLAGS))]>,
1257 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1258 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1259 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1260 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1261 X86_COND_BE, EFLAGS))]>,
1263 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1264 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1265 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1266 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1267 X86_COND_BE, EFLAGS))]>,
1269 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1270 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1271 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1272 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1273 X86_COND_A, EFLAGS))]>,
1275 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1276 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1277 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1278 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1279 X86_COND_A, EFLAGS))]>,
1281 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1282 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1283 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1284 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1285 X86_COND_L, EFLAGS))]>,
1287 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1288 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1289 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1290 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1291 X86_COND_L, EFLAGS))]>,
1293 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1294 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1295 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1296 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1297 X86_COND_GE, EFLAGS))]>,
1299 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1300 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1301 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1302 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1303 X86_COND_GE, EFLAGS))]>,
1305 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1306 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1307 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1308 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1309 X86_COND_LE, EFLAGS))]>,
1311 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1312 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1313 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1314 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1315 X86_COND_LE, EFLAGS))]>,
1317 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1318 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1319 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1320 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1321 X86_COND_G, EFLAGS))]>,
1323 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1324 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1325 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1326 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1327 X86_COND_G, EFLAGS))]>,
1329 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1330 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1331 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1332 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1333 X86_COND_S, EFLAGS))]>,
1335 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1336 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1337 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1338 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1339 X86_COND_S, EFLAGS))]>,
1341 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1342 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1343 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1344 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1345 X86_COND_NS, EFLAGS))]>,
1347 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1348 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1349 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1350 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1351 X86_COND_NS, EFLAGS))]>,
1353 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1354 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1355 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1356 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1357 X86_COND_P, EFLAGS))]>,
1359 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1360 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1361 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1362 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1363 X86_COND_P, EFLAGS))]>,
1365 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1366 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1367 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1368 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1369 X86_COND_NP, EFLAGS))]>,
1371 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1372 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1373 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1374 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1375 X86_COND_NP, EFLAGS))]>,
1377 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1378 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1379 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1380 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1381 X86_COND_O, EFLAGS))]>,
1383 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1384 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1385 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1386 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1387 X86_COND_O, EFLAGS))]>,
1389 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1390 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1391 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1392 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1393 X86_COND_NO, EFLAGS))]>,
1395 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1396 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1397 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1398 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1399 X86_COND_NO, EFLAGS))]>,
1401 } // isCommutable = 1
1403 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1404 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1405 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1406 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1407 X86_COND_B, EFLAGS))]>,
1409 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1410 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1411 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1412 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1413 X86_COND_B, EFLAGS))]>,
1415 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1416 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1417 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1418 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1419 X86_COND_AE, EFLAGS))]>,
1421 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1422 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1423 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1424 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1425 X86_COND_AE, EFLAGS))]>,
1427 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1428 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1429 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1430 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1431 X86_COND_E, EFLAGS))]>,
1433 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1434 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1435 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1436 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1437 X86_COND_E, EFLAGS))]>,
1439 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1440 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1441 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1442 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1443 X86_COND_NE, EFLAGS))]>,
1445 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1446 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1447 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1448 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1449 X86_COND_NE, EFLAGS))]>,
1451 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1452 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1453 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1454 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1455 X86_COND_BE, EFLAGS))]>,
1457 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1458 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1459 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1460 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1461 X86_COND_BE, EFLAGS))]>,
1463 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1464 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1465 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1466 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1467 X86_COND_A, EFLAGS))]>,
1469 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1470 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1471 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1472 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1473 X86_COND_A, EFLAGS))]>,
1475 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1476 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1477 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1478 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1479 X86_COND_L, EFLAGS))]>,
1481 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1482 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1483 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1484 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1485 X86_COND_L, EFLAGS))]>,
1487 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1488 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1489 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1490 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1491 X86_COND_GE, EFLAGS))]>,
1493 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1494 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1495 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1496 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1497 X86_COND_GE, EFLAGS))]>,
1499 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1500 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1501 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1502 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1503 X86_COND_LE, EFLAGS))]>,
1505 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1506 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1507 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1508 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1509 X86_COND_LE, EFLAGS))]>,
1511 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1512 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1513 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1514 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1515 X86_COND_G, EFLAGS))]>,
1517 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1518 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1519 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1520 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1521 X86_COND_G, EFLAGS))]>,
1523 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1524 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1525 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1526 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1527 X86_COND_S, EFLAGS))]>,
1529 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1530 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1531 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1532 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1533 X86_COND_S, EFLAGS))]>,
1535 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1536 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1537 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1538 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1539 X86_COND_NS, EFLAGS))]>,
1541 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1542 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1543 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1544 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1545 X86_COND_NS, EFLAGS))]>,
1547 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1548 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1549 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1550 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1551 X86_COND_P, EFLAGS))]>,
1553 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1554 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1555 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1556 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1557 X86_COND_P, EFLAGS))]>,
1559 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1560 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1561 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1562 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1563 X86_COND_NP, EFLAGS))]>,
1565 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1566 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1567 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1568 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1569 X86_COND_NP, EFLAGS))]>,
1571 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1572 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1573 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1574 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1575 X86_COND_O, EFLAGS))]>,
1577 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1578 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1579 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1580 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1581 X86_COND_O, EFLAGS))]>,
1583 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1584 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1585 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1586 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1587 X86_COND_NO, EFLAGS))]>,
1589 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1590 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1591 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1592 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1593 X86_COND_NO, EFLAGS))]>,
1595 } // Predicates = [HasCMov]
1597 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1598 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1599 // however that requires promoting the operands, and can induce additional
1600 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1601 // clobber EFLAGS, because if one of the operands is zero, the expansion
1602 // could involve an xor.
1603 let usesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS] in {
1604 def CMOV_GR8 : I<0, Pseudo,
1605 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1606 "#CMOV_GR8 PSEUDO!",
1607 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1608 imm:$cond, EFLAGS))]>;
1610 let Predicates = [NoCMov] in {
1611 def CMOV_GR32 : I<0, Pseudo,
1612 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1613 "#CMOV_GR32* PSEUDO!",
1615 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1616 def CMOV_GR16 : I<0, Pseudo,
1617 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1618 "#CMOV_GR16* PSEUDO!",
1620 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1621 def CMOV_RFP32 : I<0, Pseudo,
1622 (outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1623 "#CMOV_RFP32 PSEUDO!",
1624 [(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1626 def CMOV_RFP64 : I<0, Pseudo,
1627 (outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1628 "#CMOV_RFP64 PSEUDO!",
1629 [(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1631 def CMOV_RFP80 : I<0, Pseudo,
1632 (outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1633 "#CMOV_RFP80 PSEUDO!",
1634 [(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1636 } // Predicates = [NoCMov]
1637 } // UsesCustomInserter = 1, isTwoAddress = 0, Defs = [EFLAGS]
1638 } // Uses = [EFLAGS]
1641 // unary instructions
1642 let CodeSize = 2 in {
1643 let Defs = [EFLAGS] in {
1644 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1645 [(set GR8:$dst, (ineg GR8:$src)),
1646 (implicit EFLAGS)]>;
1647 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1648 [(set GR16:$dst, (ineg GR16:$src)),
1649 (implicit EFLAGS)]>, OpSize;
1650 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1651 [(set GR32:$dst, (ineg GR32:$src)),
1652 (implicit EFLAGS)]>;
1653 let isTwoAddress = 0 in {
1654 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1655 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1656 (implicit EFLAGS)]>;
1657 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1658 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1659 (implicit EFLAGS)]>, OpSize;
1660 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1661 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1662 (implicit EFLAGS)]>;
1664 } // Defs = [EFLAGS]
1666 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1667 let AddedComplexity = 15 in {
1668 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1669 [(set GR8:$dst, (not GR8:$src))]>;
1670 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1671 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1672 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1673 [(set GR32:$dst, (not GR32:$src))]>;
1675 let isTwoAddress = 0 in {
1676 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1677 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1678 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1679 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1680 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1681 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1685 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1686 let Defs = [EFLAGS] in {
1688 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1689 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src))]>;
1691 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1692 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1694 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src))]>,
1695 OpSize, Requires<[In32BitMode]>;
1696 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1698 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src))]>,
1699 Requires<[In32BitMode]>;
1701 let isTwoAddress = 0, CodeSize = 2 in {
1702 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1703 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1704 (implicit EFLAGS)]>;
1705 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1706 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1707 (implicit EFLAGS)]>,
1708 OpSize, Requires<[In32BitMode]>;
1709 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1710 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1711 (implicit EFLAGS)]>,
1712 Requires<[In32BitMode]>;
1716 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1717 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src))]>;
1718 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1719 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
1721 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src))]>,
1722 OpSize, Requires<[In32BitMode]>;
1723 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
1725 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src))]>,
1726 Requires<[In32BitMode]>;
1729 let isTwoAddress = 0, CodeSize = 2 in {
1730 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1731 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1732 (implicit EFLAGS)]>;
1733 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1734 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1735 (implicit EFLAGS)]>,
1736 OpSize, Requires<[In32BitMode]>;
1737 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1738 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1739 (implicit EFLAGS)]>,
1740 Requires<[In32BitMode]>;
1742 } // Defs = [EFLAGS]
1744 // Logical operators...
1745 let Defs = [EFLAGS] in {
1746 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1747 def AND8rr : I<0x20, MRMDestReg,
1748 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1749 "and{b}\t{$src2, $dst|$dst, $src2}",
1750 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1751 def AND16rr : I<0x21, MRMDestReg,
1752 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1753 "and{w}\t{$src2, $dst|$dst, $src2}",
1754 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1755 GR16:$src2))]>, OpSize;
1756 def AND32rr : I<0x21, MRMDestReg,
1757 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1758 "and{l}\t{$src2, $dst|$dst, $src2}",
1759 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1763 // AND instructions with the destination register in REG and the source register
1764 // in R/M. Included for the disassembler.
1765 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1766 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1767 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1768 (ins GR16:$src1, GR16:$src2),
1769 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1770 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1771 (ins GR32:$src1, GR32:$src2),
1772 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1774 def AND8rm : I<0x22, MRMSrcMem,
1775 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1776 "and{b}\t{$src2, $dst|$dst, $src2}",
1777 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1778 (loadi8 addr:$src2)))]>;
1779 def AND16rm : I<0x23, MRMSrcMem,
1780 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1781 "and{w}\t{$src2, $dst|$dst, $src2}",
1782 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1783 (loadi16 addr:$src2)))]>,
1785 def AND32rm : I<0x23, MRMSrcMem,
1786 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1787 "and{l}\t{$src2, $dst|$dst, $src2}",
1788 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1789 (loadi32 addr:$src2)))]>;
1791 def AND8ri : Ii8<0x80, MRM4r,
1792 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1793 "and{b}\t{$src2, $dst|$dst, $src2}",
1794 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1796 def AND16ri : Ii16<0x81, MRM4r,
1797 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1798 "and{w}\t{$src2, $dst|$dst, $src2}",
1799 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1800 imm:$src2))]>, OpSize;
1801 def AND32ri : Ii32<0x81, MRM4r,
1802 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1803 "and{l}\t{$src2, $dst|$dst, $src2}",
1804 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1806 def AND16ri8 : Ii8<0x83, MRM4r,
1807 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1808 "and{w}\t{$src2, $dst|$dst, $src2}",
1809 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1810 i16immSExt8:$src2))]>,
1812 def AND32ri8 : Ii8<0x83, MRM4r,
1813 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1814 "and{l}\t{$src2, $dst|$dst, $src2}",
1815 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1816 i32immSExt8:$src2))]>;
1818 let isTwoAddress = 0 in {
1819 def AND8mr : I<0x20, MRMDestMem,
1820 (outs), (ins i8mem :$dst, GR8 :$src),
1821 "and{b}\t{$src, $dst|$dst, $src}",
1822 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1823 (implicit EFLAGS)]>;
1824 def AND16mr : I<0x21, MRMDestMem,
1825 (outs), (ins i16mem:$dst, GR16:$src),
1826 "and{w}\t{$src, $dst|$dst, $src}",
1827 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1828 (implicit EFLAGS)]>,
1830 def AND32mr : I<0x21, MRMDestMem,
1831 (outs), (ins i32mem:$dst, GR32:$src),
1832 "and{l}\t{$src, $dst|$dst, $src}",
1833 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1834 (implicit EFLAGS)]>;
1835 def AND8mi : Ii8<0x80, MRM4m,
1836 (outs), (ins i8mem :$dst, i8imm :$src),
1837 "and{b}\t{$src, $dst|$dst, $src}",
1838 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1839 (implicit EFLAGS)]>;
1840 def AND16mi : Ii16<0x81, MRM4m,
1841 (outs), (ins i16mem:$dst, i16imm:$src),
1842 "and{w}\t{$src, $dst|$dst, $src}",
1843 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1844 (implicit EFLAGS)]>,
1846 def AND32mi : Ii32<0x81, MRM4m,
1847 (outs), (ins i32mem:$dst, i32imm:$src),
1848 "and{l}\t{$src, $dst|$dst, $src}",
1849 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1850 (implicit EFLAGS)]>;
1851 def AND16mi8 : Ii8<0x83, MRM4m,
1852 (outs), (ins i16mem:$dst, i16i8imm :$src),
1853 "and{w}\t{$src, $dst|$dst, $src}",
1854 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1855 (implicit EFLAGS)]>,
1857 def AND32mi8 : Ii8<0x83, MRM4m,
1858 (outs), (ins i32mem:$dst, i32i8imm :$src),
1859 "and{l}\t{$src, $dst|$dst, $src}",
1860 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1861 (implicit EFLAGS)]>;
1863 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1864 "and{b}\t{$src, %al|%al, $src}", []>;
1865 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1866 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1867 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1868 "and{l}\t{$src, %eax|%eax, $src}", []>;
1873 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1874 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1875 (ins GR8 :$src1, GR8 :$src2),
1876 "or{b}\t{$src2, $dst|$dst, $src2}",
1877 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1878 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1879 (ins GR16:$src1, GR16:$src2),
1880 "or{w}\t{$src2, $dst|$dst, $src2}",
1881 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1883 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1884 (ins GR32:$src1, GR32:$src2),
1885 "or{l}\t{$src2, $dst|$dst, $src2}",
1886 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1889 // OR instructions with the destination register in REG and the source register
1890 // in R/M. Included for the disassembler.
1891 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1892 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1893 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1894 (ins GR16:$src1, GR16:$src2),
1895 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1896 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1897 (ins GR32:$src1, GR32:$src2),
1898 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1900 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
1901 (ins GR8 :$src1, i8mem :$src2),
1902 "or{b}\t{$src2, $dst|$dst, $src2}",
1903 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
1904 (load addr:$src2)))]>;
1905 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
1906 (ins GR16:$src1, i16mem:$src2),
1907 "or{w}\t{$src2, $dst|$dst, $src2}",
1908 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1909 (load addr:$src2)))]>,
1911 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
1912 (ins GR32:$src1, i32mem:$src2),
1913 "or{l}\t{$src2, $dst|$dst, $src2}",
1914 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1915 (load addr:$src2)))]>;
1917 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
1918 (ins GR8 :$src1, i8imm:$src2),
1919 "or{b}\t{$src2, $dst|$dst, $src2}",
1920 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
1921 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
1922 (ins GR16:$src1, i16imm:$src2),
1923 "or{w}\t{$src2, $dst|$dst, $src2}",
1924 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1925 imm:$src2))]>, OpSize;
1926 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
1927 (ins GR32:$src1, i32imm:$src2),
1928 "or{l}\t{$src2, $dst|$dst, $src2}",
1929 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1932 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
1933 (ins GR16:$src1, i16i8imm:$src2),
1934 "or{w}\t{$src2, $dst|$dst, $src2}",
1935 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1936 i16immSExt8:$src2))]>, OpSize;
1937 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
1938 (ins GR32:$src1, i32i8imm:$src2),
1939 "or{l}\t{$src2, $dst|$dst, $src2}",
1940 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
1941 i32immSExt8:$src2))]>;
1942 let isTwoAddress = 0 in {
1943 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1944 "or{b}\t{$src, $dst|$dst, $src}",
1945 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1946 (implicit EFLAGS)]>;
1947 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1948 "or{w}\t{$src, $dst|$dst, $src}",
1949 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1950 (implicit EFLAGS)]>, OpSize;
1951 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1952 "or{l}\t{$src, $dst|$dst, $src}",
1953 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1954 (implicit EFLAGS)]>;
1955 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1956 "or{b}\t{$src, $dst|$dst, $src}",
1957 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1958 (implicit EFLAGS)]>;
1959 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1960 "or{w}\t{$src, $dst|$dst, $src}",
1961 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1962 (implicit EFLAGS)]>,
1964 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1965 "or{l}\t{$src, $dst|$dst, $src}",
1966 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1967 (implicit EFLAGS)]>;
1968 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1969 "or{w}\t{$src, $dst|$dst, $src}",
1970 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1971 (implicit EFLAGS)]>,
1973 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1974 "or{l}\t{$src, $dst|$dst, $src}",
1975 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1976 (implicit EFLAGS)]>;
1978 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
1979 "or{b}\t{$src, %al|%al, $src}", []>;
1980 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
1981 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1982 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
1983 "or{l}\t{$src, %eax|%eax, $src}", []>;
1984 } // isTwoAddress = 0
1987 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1988 def XOR8rr : I<0x30, MRMDestReg,
1989 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1990 "xor{b}\t{$src2, $dst|$dst, $src2}",
1991 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
1993 def XOR16rr : I<0x31, MRMDestReg,
1994 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1995 "xor{w}\t{$src2, $dst|$dst, $src2}",
1996 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
1997 GR16:$src2))]>, OpSize;
1998 def XOR32rr : I<0x31, MRMDestReg,
1999 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2000 "xor{l}\t{$src2, $dst|$dst, $src2}",
2001 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2003 } // isCommutable = 1
2005 // XOR instructions with the destination register in REG and the source register
2006 // in R/M. Included for the disassembler.
2007 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2008 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
2009 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
2010 (ins GR16:$src1, GR16:$src2),
2011 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2012 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
2013 (ins GR32:$src1, GR32:$src2),
2014 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2016 def XOR8rm : I<0x32, MRMSrcMem,
2017 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2018 "xor{b}\t{$src2, $dst|$dst, $src2}",
2019 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2020 (load addr:$src2)))]>;
2021 def XOR16rm : I<0x33, MRMSrcMem,
2022 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2023 "xor{w}\t{$src2, $dst|$dst, $src2}",
2024 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2025 (load addr:$src2)))]>,
2027 def XOR32rm : I<0x33, MRMSrcMem,
2028 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2029 "xor{l}\t{$src2, $dst|$dst, $src2}",
2030 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2031 (load addr:$src2)))]>;
2033 def XOR8ri : Ii8<0x80, MRM6r,
2034 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2035 "xor{b}\t{$src2, $dst|$dst, $src2}",
2036 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
2037 def XOR16ri : Ii16<0x81, MRM6r,
2038 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2039 "xor{w}\t{$src2, $dst|$dst, $src2}",
2040 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2041 imm:$src2))]>, OpSize;
2042 def XOR32ri : Ii32<0x81, MRM6r,
2043 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2044 "xor{l}\t{$src2, $dst|$dst, $src2}",
2045 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2047 def XOR16ri8 : Ii8<0x83, MRM6r,
2048 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2049 "xor{w}\t{$src2, $dst|$dst, $src2}",
2050 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2051 i16immSExt8:$src2))]>,
2053 def XOR32ri8 : Ii8<0x83, MRM6r,
2054 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2055 "xor{l}\t{$src2, $dst|$dst, $src2}",
2056 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2057 i32immSExt8:$src2))]>;
2059 let isTwoAddress = 0 in {
2060 def XOR8mr : I<0x30, MRMDestMem,
2061 (outs), (ins i8mem :$dst, GR8 :$src),
2062 "xor{b}\t{$src, $dst|$dst, $src}",
2063 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2064 (implicit EFLAGS)]>;
2065 def XOR16mr : I<0x31, MRMDestMem,
2066 (outs), (ins i16mem:$dst, GR16:$src),
2067 "xor{w}\t{$src, $dst|$dst, $src}",
2068 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2069 (implicit EFLAGS)]>,
2071 def XOR32mr : I<0x31, MRMDestMem,
2072 (outs), (ins i32mem:$dst, GR32:$src),
2073 "xor{l}\t{$src, $dst|$dst, $src}",
2074 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2075 (implicit EFLAGS)]>;
2076 def XOR8mi : Ii8<0x80, MRM6m,
2077 (outs), (ins i8mem :$dst, i8imm :$src),
2078 "xor{b}\t{$src, $dst|$dst, $src}",
2079 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2080 (implicit EFLAGS)]>;
2081 def XOR16mi : Ii16<0x81, MRM6m,
2082 (outs), (ins i16mem:$dst, i16imm:$src),
2083 "xor{w}\t{$src, $dst|$dst, $src}",
2084 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2085 (implicit EFLAGS)]>,
2087 def XOR32mi : Ii32<0x81, MRM6m,
2088 (outs), (ins i32mem:$dst, i32imm:$src),
2089 "xor{l}\t{$src, $dst|$dst, $src}",
2090 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2091 (implicit EFLAGS)]>;
2092 def XOR16mi8 : Ii8<0x83, MRM6m,
2093 (outs), (ins i16mem:$dst, i16i8imm :$src),
2094 "xor{w}\t{$src, $dst|$dst, $src}",
2095 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2096 (implicit EFLAGS)]>,
2098 def XOR32mi8 : Ii8<0x83, MRM6m,
2099 (outs), (ins i32mem:$dst, i32i8imm :$src),
2100 "xor{l}\t{$src, $dst|$dst, $src}",
2101 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2102 (implicit EFLAGS)]>;
2104 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2105 "xor{b}\t{$src, %al|%al, $src}", []>;
2106 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
2107 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2108 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
2109 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2110 } // isTwoAddress = 0
2111 } // Defs = [EFLAGS]
2113 // Shift instructions
2114 let Defs = [EFLAGS] in {
2115 let Uses = [CL] in {
2116 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
2117 "shl{b}\t{%cl, $dst|$dst, CL}",
2118 [(set GR8:$dst, (shl GR8:$src, CL))]>;
2119 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
2120 "shl{w}\t{%cl, $dst|$dst, CL}",
2121 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
2122 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
2123 "shl{l}\t{%cl, $dst|$dst, CL}",
2124 [(set GR32:$dst, (shl GR32:$src, CL))]>;
2127 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2128 "shl{b}\t{$src2, $dst|$dst, $src2}",
2129 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2130 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2131 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2132 "shl{w}\t{$src2, $dst|$dst, $src2}",
2133 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2134 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2135 "shl{l}\t{$src2, $dst|$dst, $src2}",
2136 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2138 // NOTE: We don't include patterns for shifts of a register by one, because
2139 // 'add reg,reg' is cheaper.
2141 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2142 "shl{b}\t$dst", []>;
2143 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2144 "shl{w}\t$dst", []>, OpSize;
2145 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2146 "shl{l}\t$dst", []>;
2148 } // isConvertibleToThreeAddress = 1
2150 let isTwoAddress = 0 in {
2151 let Uses = [CL] in {
2152 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2153 "shl{b}\t{%cl, $dst|$dst, CL}",
2154 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2155 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2156 "shl{w}\t{%cl, $dst|$dst, CL}",
2157 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2158 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2159 "shl{l}\t{%cl, $dst|$dst, CL}",
2160 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2162 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2163 "shl{b}\t{$src, $dst|$dst, $src}",
2164 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2165 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2166 "shl{w}\t{$src, $dst|$dst, $src}",
2167 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2169 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2170 "shl{l}\t{$src, $dst|$dst, $src}",
2171 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2174 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2176 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2177 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2179 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2181 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2183 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2186 let Uses = [CL] in {
2187 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
2188 "shr{b}\t{%cl, $dst|$dst, CL}",
2189 [(set GR8:$dst, (srl GR8:$src, CL))]>;
2190 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
2191 "shr{w}\t{%cl, $dst|$dst, CL}",
2192 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
2193 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
2194 "shr{l}\t{%cl, $dst|$dst, CL}",
2195 [(set GR32:$dst, (srl GR32:$src, CL))]>;
2198 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2199 "shr{b}\t{$src2, $dst|$dst, $src2}",
2200 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2201 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2202 "shr{w}\t{$src2, $dst|$dst, $src2}",
2203 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2204 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2205 "shr{l}\t{$src2, $dst|$dst, $src2}",
2206 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2209 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2211 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2212 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2214 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2215 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2217 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2219 let isTwoAddress = 0 in {
2220 let Uses = [CL] in {
2221 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2222 "shr{b}\t{%cl, $dst|$dst, CL}",
2223 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2224 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2225 "shr{w}\t{%cl, $dst|$dst, CL}",
2226 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2228 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2229 "shr{l}\t{%cl, $dst|$dst, CL}",
2230 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2232 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2233 "shr{b}\t{$src, $dst|$dst, $src}",
2234 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2235 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2236 "shr{w}\t{$src, $dst|$dst, $src}",
2237 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2239 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2240 "shr{l}\t{$src, $dst|$dst, $src}",
2241 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2244 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2246 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2247 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2249 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2250 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2252 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2255 let Uses = [CL] in {
2256 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
2257 "sar{b}\t{%cl, $dst|$dst, CL}",
2258 [(set GR8:$dst, (sra GR8:$src, CL))]>;
2259 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
2260 "sar{w}\t{%cl, $dst|$dst, CL}",
2261 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
2262 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
2263 "sar{l}\t{%cl, $dst|$dst, CL}",
2264 [(set GR32:$dst, (sra GR32:$src, CL))]>;
2267 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2268 "sar{b}\t{$src2, $dst|$dst, $src2}",
2269 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2270 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2271 "sar{w}\t{$src2, $dst|$dst, $src2}",
2272 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2274 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2275 "sar{l}\t{$src2, $dst|$dst, $src2}",
2276 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2279 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2281 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2282 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2284 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2285 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2287 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2289 let isTwoAddress = 0 in {
2290 let Uses = [CL] in {
2291 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2292 "sar{b}\t{%cl, $dst|$dst, CL}",
2293 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2294 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2295 "sar{w}\t{%cl, $dst|$dst, CL}",
2296 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2297 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2298 "sar{l}\t{%cl, $dst|$dst, CL}",
2299 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2301 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2302 "sar{b}\t{$src, $dst|$dst, $src}",
2303 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2304 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2305 "sar{w}\t{$src, $dst|$dst, $src}",
2306 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2308 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2309 "sar{l}\t{$src, $dst|$dst, $src}",
2310 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2313 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2315 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2316 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2318 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2320 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2322 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2325 // Rotate instructions
2327 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2328 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2329 let Uses = [CL] in {
2330 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src),
2331 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2333 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2334 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2336 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2337 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2338 let Uses = [CL] in {
2339 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src),
2340 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2342 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2343 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2345 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2346 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2347 let Uses = [CL] in {
2348 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src),
2349 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2351 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2352 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2354 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2355 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2356 let Uses = [CL] in {
2357 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src),
2358 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2360 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src, i8imm:$cnt),
2361 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2363 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2364 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2365 let Uses = [CL] in {
2366 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src),
2367 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2369 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src, i8imm:$cnt),
2370 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2372 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2373 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2374 let Uses = [CL] in {
2375 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src),
2376 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2378 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src, i8imm:$cnt),
2379 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2381 let isTwoAddress = 0 in {
2382 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2383 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2384 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2385 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2386 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2387 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2388 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2389 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2390 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2391 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2392 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2393 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2394 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2395 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2396 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2397 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2398 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2399 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2400 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2401 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2402 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2403 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2404 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2405 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2407 let Uses = [CL] in {
2408 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2409 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2410 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2411 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2412 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2413 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2414 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2415 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2416 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2417 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2418 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2419 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2423 // FIXME: provide shorter instructions when imm8 == 1
2424 let Uses = [CL] in {
2425 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
2426 "rol{b}\t{%cl, $dst|$dst, CL}",
2427 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
2428 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
2429 "rol{w}\t{%cl, $dst|$dst, CL}",
2430 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
2431 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
2432 "rol{l}\t{%cl, $dst|$dst, CL}",
2433 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
2436 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2437 "rol{b}\t{$src2, $dst|$dst, $src2}",
2438 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2439 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2440 "rol{w}\t{$src2, $dst|$dst, $src2}",
2441 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2443 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2444 "rol{l}\t{$src2, $dst|$dst, $src2}",
2445 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2448 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2450 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2451 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2453 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2454 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2456 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2458 let isTwoAddress = 0 in {
2459 let Uses = [CL] in {
2460 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2461 "rol{b}\t{%cl, $dst|$dst, CL}",
2462 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2463 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2464 "rol{w}\t{%cl, $dst|$dst, CL}",
2465 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2466 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2467 "rol{l}\t{%cl, $dst|$dst, CL}",
2468 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2470 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2471 "rol{b}\t{$src, $dst|$dst, $src}",
2472 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2473 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2474 "rol{w}\t{$src, $dst|$dst, $src}",
2475 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2477 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2478 "rol{l}\t{$src, $dst|$dst, $src}",
2479 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2482 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2484 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2485 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2487 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2489 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2491 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2494 let Uses = [CL] in {
2495 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2496 "ror{b}\t{%cl, $dst|$dst, CL}",
2497 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2498 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2499 "ror{w}\t{%cl, $dst|$dst, CL}",
2500 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2501 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2502 "ror{l}\t{%cl, $dst|$dst, CL}",
2503 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2506 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2507 "ror{b}\t{$src2, $dst|$dst, $src2}",
2508 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2509 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2510 "ror{w}\t{$src2, $dst|$dst, $src2}",
2511 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2513 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2514 "ror{l}\t{$src2, $dst|$dst, $src2}",
2515 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2518 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2520 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2521 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2523 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2524 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2526 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2528 let isTwoAddress = 0 in {
2529 let Uses = [CL] in {
2530 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2531 "ror{b}\t{%cl, $dst|$dst, CL}",
2532 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2533 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2534 "ror{w}\t{%cl, $dst|$dst, CL}",
2535 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2536 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2537 "ror{l}\t{%cl, $dst|$dst, CL}",
2538 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2540 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2541 "ror{b}\t{$src, $dst|$dst, $src}",
2542 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2543 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2544 "ror{w}\t{$src, $dst|$dst, $src}",
2545 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2547 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2548 "ror{l}\t{$src, $dst|$dst, $src}",
2549 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2552 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2554 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2555 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2557 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2559 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2561 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2566 // Double shift instructions (generalizations of rotate)
2567 let Uses = [CL] in {
2568 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2569 (ins GR32:$src1, GR32:$src2),
2570 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2571 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2572 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2573 (ins GR32:$src1, GR32:$src2),
2574 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2575 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2576 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2577 (ins GR16:$src1, GR16:$src2),
2578 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2579 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2581 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2582 (ins GR16:$src1, GR16:$src2),
2583 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2584 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2588 let isCommutable = 1 in { // These instructions commute to each other.
2589 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2591 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2592 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2593 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2596 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2598 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2599 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2600 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2603 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2605 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2606 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2607 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2610 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2612 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2613 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2614 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2619 let isTwoAddress = 0 in {
2620 let Uses = [CL] in {
2621 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2622 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2623 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2625 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2626 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2627 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2630 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2631 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2632 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2633 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2634 (i8 imm:$src3)), addr:$dst)]>,
2636 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2637 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2638 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2639 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2640 (i8 imm:$src3)), addr:$dst)]>,
2643 let Uses = [CL] in {
2644 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2645 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2646 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2647 addr:$dst)]>, TB, OpSize;
2648 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2649 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2650 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2651 addr:$dst)]>, TB, OpSize;
2653 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2654 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2655 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2656 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2657 (i8 imm:$src3)), addr:$dst)]>,
2659 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2660 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2661 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2662 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2663 (i8 imm:$src3)), addr:$dst)]>,
2666 } // Defs = [EFLAGS]
2670 let Defs = [EFLAGS] in {
2671 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2672 // Register-Register Addition
2673 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2674 (ins GR8 :$src1, GR8 :$src2),
2675 "add{b}\t{$src2, $dst|$dst, $src2}",
2676 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2678 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2679 // Register-Register Addition
2680 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2681 (ins GR16:$src1, GR16:$src2),
2682 "add{w}\t{$src2, $dst|$dst, $src2}",
2683 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2684 GR16:$src2))]>, OpSize;
2685 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2686 (ins GR32:$src1, GR32:$src2),
2687 "add{l}\t{$src2, $dst|$dst, $src2}",
2688 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2690 } // end isConvertibleToThreeAddress
2691 } // end isCommutable
2693 // These are alternate spellings for use by the disassembler, we mark them as
2694 // code gen only to ensure they aren't matched by the assembler.
2695 let isCodeGenOnly = 1 in {
2696 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2697 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2698 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2699 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2700 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2701 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2704 // Register-Memory Addition
2705 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2706 (ins GR8 :$src1, i8mem :$src2),
2707 "add{b}\t{$src2, $dst|$dst, $src2}",
2708 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2709 (load addr:$src2)))]>;
2710 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2711 (ins GR16:$src1, i16mem:$src2),
2712 "add{w}\t{$src2, $dst|$dst, $src2}",
2713 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2714 (load addr:$src2)))]>, OpSize;
2715 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2716 (ins GR32:$src1, i32mem:$src2),
2717 "add{l}\t{$src2, $dst|$dst, $src2}",
2718 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2719 (load addr:$src2)))]>;
2721 // Register-Integer Addition
2722 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2723 "add{b}\t{$src2, $dst|$dst, $src2}",
2724 [(set GR8:$dst, EFLAGS,
2725 (X86add_flag GR8:$src1, imm:$src2))]>;
2727 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2728 // Register-Integer Addition
2729 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2730 (ins GR16:$src1, i16imm:$src2),
2731 "add{w}\t{$src2, $dst|$dst, $src2}",
2732 [(set GR16:$dst, EFLAGS,
2733 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2734 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2735 (ins GR32:$src1, i32imm:$src2),
2736 "add{l}\t{$src2, $dst|$dst, $src2}",
2737 [(set GR32:$dst, EFLAGS,
2738 (X86add_flag GR32:$src1, imm:$src2))]>;
2739 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2740 (ins GR16:$src1, i16i8imm:$src2),
2741 "add{w}\t{$src2, $dst|$dst, $src2}",
2742 [(set GR16:$dst, EFLAGS,
2743 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2744 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2745 (ins GR32:$src1, i32i8imm:$src2),
2746 "add{l}\t{$src2, $dst|$dst, $src2}",
2747 [(set GR32:$dst, EFLAGS,
2748 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2751 let isTwoAddress = 0 in {
2752 // Memory-Register Addition
2753 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2754 "add{b}\t{$src2, $dst|$dst, $src2}",
2755 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2756 (implicit EFLAGS)]>;
2757 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2758 "add{w}\t{$src2, $dst|$dst, $src2}",
2759 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2760 (implicit EFLAGS)]>, OpSize;
2761 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2762 "add{l}\t{$src2, $dst|$dst, $src2}",
2763 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2764 (implicit EFLAGS)]>;
2765 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2766 "add{b}\t{$src2, $dst|$dst, $src2}",
2767 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2768 (implicit EFLAGS)]>;
2769 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2770 "add{w}\t{$src2, $dst|$dst, $src2}",
2771 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2772 (implicit EFLAGS)]>, OpSize;
2773 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2774 "add{l}\t{$src2, $dst|$dst, $src2}",
2775 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2776 (implicit EFLAGS)]>;
2777 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2778 "add{w}\t{$src2, $dst|$dst, $src2}",
2779 [(store (add (load addr:$dst), i16immSExt8:$src2),
2781 (implicit EFLAGS)]>, OpSize;
2782 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2783 "add{l}\t{$src2, $dst|$dst, $src2}",
2784 [(store (add (load addr:$dst), i32immSExt8:$src2),
2786 (implicit EFLAGS)]>;
2789 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2790 "add{b}\t{$src, %al|%al, $src}", []>;
2791 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2792 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2793 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2794 "add{l}\t{$src, %eax|%eax, $src}", []>;
2797 let Uses = [EFLAGS] in {
2798 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2799 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2800 "adc{b}\t{$src2, $dst|$dst, $src2}",
2801 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2802 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2803 (ins GR16:$src1, GR16:$src2),
2804 "adc{w}\t{$src2, $dst|$dst, $src2}",
2805 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2806 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2807 (ins GR32:$src1, GR32:$src2),
2808 "adc{l}\t{$src2, $dst|$dst, $src2}",
2809 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2812 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2813 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2814 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2815 (ins GR16:$src1, GR16:$src2),
2816 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2817 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2818 (ins GR32:$src1, GR32:$src2),
2819 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2821 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2822 (ins GR8:$src1, i8mem:$src2),
2823 "adc{b}\t{$src2, $dst|$dst, $src2}",
2824 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2825 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2826 (ins GR16:$src1, i16mem:$src2),
2827 "adc{w}\t{$src2, $dst|$dst, $src2}",
2828 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2830 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2831 (ins GR32:$src1, i32mem:$src2),
2832 "adc{l}\t{$src2, $dst|$dst, $src2}",
2833 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2834 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2835 "adc{b}\t{$src2, $dst|$dst, $src2}",
2836 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2837 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2838 (ins GR16:$src1, i16imm:$src2),
2839 "adc{w}\t{$src2, $dst|$dst, $src2}",
2840 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2841 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2842 (ins GR16:$src1, i16i8imm:$src2),
2843 "adc{w}\t{$src2, $dst|$dst, $src2}",
2844 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2846 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2847 (ins GR32:$src1, i32imm:$src2),
2848 "adc{l}\t{$src2, $dst|$dst, $src2}",
2849 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2850 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2851 (ins GR32:$src1, i32i8imm:$src2),
2852 "adc{l}\t{$src2, $dst|$dst, $src2}",
2853 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2855 let isTwoAddress = 0 in {
2856 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2857 "adc{b}\t{$src2, $dst|$dst, $src2}",
2858 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2859 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2860 "adc{w}\t{$src2, $dst|$dst, $src2}",
2861 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2863 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2864 "adc{l}\t{$src2, $dst|$dst, $src2}",
2865 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2866 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2867 "adc{b}\t{$src2, $dst|$dst, $src2}",
2868 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2869 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2870 "adc{w}\t{$src2, $dst|$dst, $src2}",
2871 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2873 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2874 "adc{w}\t{$src2, $dst|$dst, $src2}",
2875 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2877 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2878 "adc{l}\t{$src2, $dst|$dst, $src2}",
2879 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2880 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2881 "adc{l}\t{$src2, $dst|$dst, $src2}",
2882 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2884 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2885 "adc{b}\t{$src, %al|%al, $src}", []>;
2886 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2887 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2888 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2889 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2891 } // Uses = [EFLAGS]
2893 // Register-Register Subtraction
2894 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2895 "sub{b}\t{$src2, $dst|$dst, $src2}",
2896 [(set GR8:$dst, EFLAGS,
2897 (X86sub_flag GR8:$src1, GR8:$src2))]>;
2898 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2899 "sub{w}\t{$src2, $dst|$dst, $src2}",
2900 [(set GR16:$dst, EFLAGS,
2901 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
2902 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2903 "sub{l}\t{$src2, $dst|$dst, $src2}",
2904 [(set GR32:$dst, EFLAGS,
2905 (X86sub_flag GR32:$src1, GR32:$src2))]>;
2907 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2908 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
2909 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
2910 (ins GR16:$src1, GR16:$src2),
2911 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2912 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
2913 (ins GR32:$src1, GR32:$src2),
2914 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
2916 // Register-Memory Subtraction
2917 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2918 (ins GR8 :$src1, i8mem :$src2),
2919 "sub{b}\t{$src2, $dst|$dst, $src2}",
2920 [(set GR8:$dst, EFLAGS,
2921 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
2922 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2923 (ins GR16:$src1, i16mem:$src2),
2924 "sub{w}\t{$src2, $dst|$dst, $src2}",
2925 [(set GR16:$dst, EFLAGS,
2926 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
2927 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2928 (ins GR32:$src1, i32mem:$src2),
2929 "sub{l}\t{$src2, $dst|$dst, $src2}",
2930 [(set GR32:$dst, EFLAGS,
2931 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
2933 // Register-Integer Subtraction
2934 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2935 (ins GR8:$src1, i8imm:$src2),
2936 "sub{b}\t{$src2, $dst|$dst, $src2}",
2937 [(set GR8:$dst, EFLAGS,
2938 (X86sub_flag GR8:$src1, imm:$src2))]>;
2939 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2940 (ins GR16:$src1, i16imm:$src2),
2941 "sub{w}\t{$src2, $dst|$dst, $src2}",
2942 [(set GR16:$dst, EFLAGS,
2943 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
2944 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2945 (ins GR32:$src1, i32imm:$src2),
2946 "sub{l}\t{$src2, $dst|$dst, $src2}",
2947 [(set GR32:$dst, EFLAGS,
2948 (X86sub_flag GR32:$src1, imm:$src2))]>;
2949 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2950 (ins GR16:$src1, i16i8imm:$src2),
2951 "sub{w}\t{$src2, $dst|$dst, $src2}",
2952 [(set GR16:$dst, EFLAGS,
2953 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2954 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2955 (ins GR32:$src1, i32i8imm:$src2),
2956 "sub{l}\t{$src2, $dst|$dst, $src2}",
2957 [(set GR32:$dst, EFLAGS,
2958 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
2960 let isTwoAddress = 0 in {
2961 // Memory-Register Subtraction
2962 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2963 "sub{b}\t{$src2, $dst|$dst, $src2}",
2964 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2965 (implicit EFLAGS)]>;
2966 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2967 "sub{w}\t{$src2, $dst|$dst, $src2}",
2968 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2969 (implicit EFLAGS)]>, OpSize;
2970 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2971 "sub{l}\t{$src2, $dst|$dst, $src2}",
2972 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2973 (implicit EFLAGS)]>;
2975 // Memory-Integer Subtraction
2976 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2977 "sub{b}\t{$src2, $dst|$dst, $src2}",
2978 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2979 (implicit EFLAGS)]>;
2980 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2981 "sub{w}\t{$src2, $dst|$dst, $src2}",
2982 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2983 (implicit EFLAGS)]>, OpSize;
2984 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2985 "sub{l}\t{$src2, $dst|$dst, $src2}",
2986 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2987 (implicit EFLAGS)]>;
2988 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2989 "sub{w}\t{$src2, $dst|$dst, $src2}",
2990 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2992 (implicit EFLAGS)]>, OpSize;
2993 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2994 "sub{l}\t{$src2, $dst|$dst, $src2}",
2995 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2997 (implicit EFLAGS)]>;
2999 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
3000 "sub{b}\t{$src, %al|%al, $src}", []>;
3001 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
3002 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3003 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
3004 "sub{l}\t{$src, %eax|%eax, $src}", []>;
3007 let Uses = [EFLAGS] in {
3008 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
3009 (ins GR8:$src1, GR8:$src2),
3010 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3011 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
3012 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
3013 (ins GR16:$src1, GR16:$src2),
3014 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3015 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3016 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3017 (ins GR32:$src1, GR32:$src2),
3018 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3019 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3021 let isTwoAddress = 0 in {
3022 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3023 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3024 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3025 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3026 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3027 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3029 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3030 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3031 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3032 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3033 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3034 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3035 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3036 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3037 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3039 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3040 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3041 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3043 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3044 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3045 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3046 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3047 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3048 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3050 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3051 "sbb{b}\t{$src, %al|%al, $src}", []>;
3052 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3053 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3054 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3055 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3058 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3059 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3060 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3061 (ins GR16:$src1, GR16:$src2),
3062 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3063 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3064 (ins GR32:$src1, GR32:$src2),
3065 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3067 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3068 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3069 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3070 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3071 (ins GR16:$src1, i16mem:$src2),
3072 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3073 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3075 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3076 (ins GR32:$src1, i32mem:$src2),
3077 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3078 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3079 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3080 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3081 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3082 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3083 (ins GR16:$src1, i16imm:$src2),
3084 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3085 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3086 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3087 (ins GR16:$src1, i16i8imm:$src2),
3088 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3089 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3091 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3092 (ins GR32:$src1, i32imm:$src2),
3093 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3094 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3095 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3096 (ins GR32:$src1, i32i8imm:$src2),
3097 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3098 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3099 } // Uses = [EFLAGS]
3100 } // Defs = [EFLAGS]
3102 let Defs = [EFLAGS] in {
3103 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3104 // Register-Register Signed Integer Multiply
3105 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3106 "imul{w}\t{$src2, $dst|$dst, $src2}",
3107 [(set GR16:$dst, EFLAGS,
3108 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
3109 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3110 "imul{l}\t{$src2, $dst|$dst, $src2}",
3111 [(set GR32:$dst, EFLAGS,
3112 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
3115 // Register-Memory Signed Integer Multiply
3116 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3117 (ins GR16:$src1, i16mem:$src2),
3118 "imul{w}\t{$src2, $dst|$dst, $src2}",
3119 [(set GR16:$dst, EFLAGS,
3120 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
3122 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3123 (ins GR32:$src1, i32mem:$src2),
3124 "imul{l}\t{$src2, $dst|$dst, $src2}",
3125 [(set GR32:$dst, EFLAGS,
3126 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
3127 } // Defs = [EFLAGS]
3128 } // end Two Address instructions
3130 // Suprisingly enough, these are not two address instructions!
3131 let Defs = [EFLAGS] in {
3132 // Register-Integer Signed Integer Multiply
3133 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3134 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3135 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3136 [(set GR16:$dst, EFLAGS,
3137 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
3138 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3139 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3140 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3141 [(set GR32:$dst, EFLAGS,
3142 (X86smul_flag GR32:$src1, imm:$src2))]>;
3143 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3144 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3145 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3146 [(set GR16:$dst, EFLAGS,
3147 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
3149 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3150 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3151 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3152 [(set GR32:$dst, EFLAGS,
3153 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
3155 // Memory-Integer Signed Integer Multiply
3156 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3157 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3158 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3159 [(set GR16:$dst, EFLAGS,
3160 (X86smul_flag (load addr:$src1), imm:$src2))]>,
3162 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3163 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3164 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3165 [(set GR32:$dst, EFLAGS,
3166 (X86smul_flag (load addr:$src1), imm:$src2))]>;
3167 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3168 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3169 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3170 [(set GR16:$dst, EFLAGS,
3171 (X86smul_flag (load addr:$src1),
3172 i16immSExt8:$src2))]>, OpSize;
3173 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3174 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3175 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3176 [(set GR32:$dst, EFLAGS,
3177 (X86smul_flag (load addr:$src1),
3178 i32immSExt8:$src2))]>;
3179 } // Defs = [EFLAGS]
3181 //===----------------------------------------------------------------------===//
3182 // Test instructions are just like AND, except they don't generate a result.
3184 let Defs = [EFLAGS] in {
3185 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3186 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3187 "test{b}\t{$src2, $src1|$src1, $src2}",
3188 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3189 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3190 "test{w}\t{$src2, $src1|$src1, $src2}",
3191 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3194 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3195 "test{l}\t{$src2, $src1|$src1, $src2}",
3196 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3200 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3201 "test{b}\t{$src, %al|%al, $src}", []>;
3202 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3203 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3204 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3205 "test{l}\t{$src, %eax|%eax, $src}", []>;
3207 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3208 "test{b}\t{$src2, $src1|$src1, $src2}",
3209 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3211 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3212 "test{w}\t{$src2, $src1|$src1, $src2}",
3213 [(set EFLAGS, (X86cmp (and GR16:$src1,
3214 (loadi16 addr:$src2)), 0))]>, OpSize;
3215 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3216 "test{l}\t{$src2, $src1|$src1, $src2}",
3217 [(set EFLAGS, (X86cmp (and GR32:$src1,
3218 (loadi32 addr:$src2)), 0))]>;
3220 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3221 (outs), (ins GR8:$src1, i8imm:$src2),
3222 "test{b}\t{$src2, $src1|$src1, $src2}",
3223 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3224 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3225 (outs), (ins GR16:$src1, i16imm:$src2),
3226 "test{w}\t{$src2, $src1|$src1, $src2}",
3227 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3229 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3230 (outs), (ins GR32:$src1, i32imm:$src2),
3231 "test{l}\t{$src2, $src1|$src1, $src2}",
3232 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3234 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3235 (outs), (ins i8mem:$src1, i8imm:$src2),
3236 "test{b}\t{$src2, $src1|$src1, $src2}",
3237 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3239 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3240 (outs), (ins i16mem:$src1, i16imm:$src2),
3241 "test{w}\t{$src2, $src1|$src1, $src2}",
3242 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3244 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3245 (outs), (ins i32mem:$src1, i32imm:$src2),
3246 "test{l}\t{$src2, $src1|$src1, $src2}",
3247 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3249 } // Defs = [EFLAGS]
3252 // Condition code ops, incl. set if equal/not equal/...
3253 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3254 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3255 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3256 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3258 let Uses = [EFLAGS] in {
3259 // Use sbb to materialize carry bit.
3260 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3261 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3262 // However, Pat<> can't replicate the destination reg into the inputs of the
3264 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3266 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3267 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3268 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3269 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3271 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3272 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3275 def SETEr : I<0x94, MRM0r,
3276 (outs GR8 :$dst), (ins),
3278 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3280 def SETEm : I<0x94, MRM0m,
3281 (outs), (ins i8mem:$dst),
3283 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3286 def SETNEr : I<0x95, MRM0r,
3287 (outs GR8 :$dst), (ins),
3289 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3291 def SETNEm : I<0x95, MRM0m,
3292 (outs), (ins i8mem:$dst),
3294 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3297 def SETLr : I<0x9C, MRM0r,
3298 (outs GR8 :$dst), (ins),
3300 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3301 TB; // GR8 = < signed
3302 def SETLm : I<0x9C, MRM0m,
3303 (outs), (ins i8mem:$dst),
3305 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3306 TB; // [mem8] = < signed
3308 def SETGEr : I<0x9D, MRM0r,
3309 (outs GR8 :$dst), (ins),
3311 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3312 TB; // GR8 = >= signed
3313 def SETGEm : I<0x9D, MRM0m,
3314 (outs), (ins i8mem:$dst),
3316 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3317 TB; // [mem8] = >= signed
3319 def SETLEr : I<0x9E, MRM0r,
3320 (outs GR8 :$dst), (ins),
3322 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3323 TB; // GR8 = <= signed
3324 def SETLEm : I<0x9E, MRM0m,
3325 (outs), (ins i8mem:$dst),
3327 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3328 TB; // [mem8] = <= signed
3330 def SETGr : I<0x9F, MRM0r,
3331 (outs GR8 :$dst), (ins),
3333 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3334 TB; // GR8 = > signed
3335 def SETGm : I<0x9F, MRM0m,
3336 (outs), (ins i8mem:$dst),
3338 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3339 TB; // [mem8] = > signed
3341 def SETBr : I<0x92, MRM0r,
3342 (outs GR8 :$dst), (ins),
3344 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3345 TB; // GR8 = < unsign
3346 def SETBm : I<0x92, MRM0m,
3347 (outs), (ins i8mem:$dst),
3349 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3350 TB; // [mem8] = < unsign
3352 def SETAEr : I<0x93, MRM0r,
3353 (outs GR8 :$dst), (ins),
3355 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3356 TB; // GR8 = >= unsign
3357 def SETAEm : I<0x93, MRM0m,
3358 (outs), (ins i8mem:$dst),
3360 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3361 TB; // [mem8] = >= unsign
3363 def SETBEr : I<0x96, MRM0r,
3364 (outs GR8 :$dst), (ins),
3366 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3367 TB; // GR8 = <= unsign
3368 def SETBEm : I<0x96, MRM0m,
3369 (outs), (ins i8mem:$dst),
3371 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3372 TB; // [mem8] = <= unsign
3374 def SETAr : I<0x97, MRM0r,
3375 (outs GR8 :$dst), (ins),
3377 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3378 TB; // GR8 = > signed
3379 def SETAm : I<0x97, MRM0m,
3380 (outs), (ins i8mem:$dst),
3382 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3383 TB; // [mem8] = > signed
3385 def SETSr : I<0x98, MRM0r,
3386 (outs GR8 :$dst), (ins),
3388 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3389 TB; // GR8 = <sign bit>
3390 def SETSm : I<0x98, MRM0m,
3391 (outs), (ins i8mem:$dst),
3393 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3394 TB; // [mem8] = <sign bit>
3395 def SETNSr : I<0x99, MRM0r,
3396 (outs GR8 :$dst), (ins),
3398 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3399 TB; // GR8 = !<sign bit>
3400 def SETNSm : I<0x99, MRM0m,
3401 (outs), (ins i8mem:$dst),
3403 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3404 TB; // [mem8] = !<sign bit>
3406 def SETPr : I<0x9A, MRM0r,
3407 (outs GR8 :$dst), (ins),
3409 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3411 def SETPm : I<0x9A, MRM0m,
3412 (outs), (ins i8mem:$dst),
3414 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3415 TB; // [mem8] = parity
3416 def SETNPr : I<0x9B, MRM0r,
3417 (outs GR8 :$dst), (ins),
3419 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3420 TB; // GR8 = not parity
3421 def SETNPm : I<0x9B, MRM0m,
3422 (outs), (ins i8mem:$dst),
3424 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3425 TB; // [mem8] = not parity
3427 def SETOr : I<0x90, MRM0r,
3428 (outs GR8 :$dst), (ins),
3430 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3431 TB; // GR8 = overflow
3432 def SETOm : I<0x90, MRM0m,
3433 (outs), (ins i8mem:$dst),
3435 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3436 TB; // [mem8] = overflow
3437 def SETNOr : I<0x91, MRM0r,
3438 (outs GR8 :$dst), (ins),
3440 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3441 TB; // GR8 = not overflow
3442 def SETNOm : I<0x91, MRM0m,
3443 (outs), (ins i8mem:$dst),
3445 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3446 TB; // [mem8] = not overflow
3447 } // Uses = [EFLAGS]
3450 // Integer comparisons
3451 let Defs = [EFLAGS] in {
3452 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3453 "cmp{b}\t{$src, %al|%al, $src}", []>;
3454 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3455 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3456 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3457 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3459 def CMP8rr : I<0x38, MRMDestReg,
3460 (outs), (ins GR8 :$src1, GR8 :$src2),
3461 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3462 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3463 def CMP16rr : I<0x39, MRMDestReg,
3464 (outs), (ins GR16:$src1, GR16:$src2),
3465 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3466 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3467 def CMP32rr : I<0x39, MRMDestReg,
3468 (outs), (ins GR32:$src1, GR32:$src2),
3469 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3470 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3471 def CMP8mr : I<0x38, MRMDestMem,
3472 (outs), (ins i8mem :$src1, GR8 :$src2),
3473 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3474 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3475 def CMP16mr : I<0x39, MRMDestMem,
3476 (outs), (ins i16mem:$src1, GR16:$src2),
3477 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3478 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3480 def CMP32mr : I<0x39, MRMDestMem,
3481 (outs), (ins i32mem:$src1, GR32:$src2),
3482 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3483 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3484 def CMP8rm : I<0x3A, MRMSrcMem,
3485 (outs), (ins GR8 :$src1, i8mem :$src2),
3486 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3487 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3488 def CMP16rm : I<0x3B, MRMSrcMem,
3489 (outs), (ins GR16:$src1, i16mem:$src2),
3490 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3491 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3493 def CMP32rm : I<0x3B, MRMSrcMem,
3494 (outs), (ins GR32:$src1, i32mem:$src2),
3495 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3496 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3498 // These are alternate spellings for use by the disassembler, we mark them as
3499 // code gen only to ensure they aren't matched by the assembler.
3500 let isCodeGenOnly = 1 in {
3501 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3502 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3503 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3504 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3505 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3506 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3509 def CMP8ri : Ii8<0x80, MRM7r,
3510 (outs), (ins GR8:$src1, i8imm:$src2),
3511 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3512 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3513 def CMP16ri : Ii16<0x81, MRM7r,
3514 (outs), (ins GR16:$src1, i16imm:$src2),
3515 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3516 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3517 def CMP32ri : Ii32<0x81, MRM7r,
3518 (outs), (ins GR32:$src1, i32imm:$src2),
3519 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3520 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3521 def CMP8mi : Ii8 <0x80, MRM7m,
3522 (outs), (ins i8mem :$src1, i8imm :$src2),
3523 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3524 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3525 def CMP16mi : Ii16<0x81, MRM7m,
3526 (outs), (ins i16mem:$src1, i16imm:$src2),
3527 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3528 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3530 def CMP32mi : Ii32<0x81, MRM7m,
3531 (outs), (ins i32mem:$src1, i32imm:$src2),
3532 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3533 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3534 def CMP16ri8 : Ii8<0x83, MRM7r,
3535 (outs), (ins GR16:$src1, i16i8imm:$src2),
3536 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3537 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3539 def CMP16mi8 : Ii8<0x83, MRM7m,
3540 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3541 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3542 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3543 i16immSExt8:$src2))]>, OpSize;
3544 def CMP32mi8 : Ii8<0x83, MRM7m,
3545 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3546 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3547 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3548 i32immSExt8:$src2))]>;
3549 def CMP32ri8 : Ii8<0x83, MRM7r,
3550 (outs), (ins GR32:$src1, i32i8imm:$src2),
3551 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3552 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3553 } // Defs = [EFLAGS]
3556 // TODO: BTC, BTR, and BTS
3557 let Defs = [EFLAGS] in {
3558 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3559 "bt{w}\t{$src2, $src1|$src1, $src2}",
3560 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3561 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3562 "bt{l}\t{$src2, $src1|$src1, $src2}",
3563 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3565 // Unlike with the register+register form, the memory+register form of the
3566 // bt instruction does not ignore the high bits of the index. From ISel's
3567 // perspective, this is pretty bizarre. Make these instructions disassembly
3570 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3571 "bt{w}\t{$src2, $src1|$src1, $src2}",
3572 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3573 // (implicit EFLAGS)]
3575 >, OpSize, TB, Requires<[FastBTMem]>;
3576 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3577 "bt{l}\t{$src2, $src1|$src1, $src2}",
3578 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3579 // (implicit EFLAGS)]
3581 >, TB, Requires<[FastBTMem]>;
3583 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3584 "bt{w}\t{$src2, $src1|$src1, $src2}",
3585 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3587 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3588 "bt{l}\t{$src2, $src1|$src1, $src2}",
3589 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3590 // Note that these instructions don't need FastBTMem because that
3591 // only applies when the other operand is in a register. When it's
3592 // an immediate, bt is still fast.
3593 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3594 "bt{w}\t{$src2, $src1|$src1, $src2}",
3595 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3597 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3598 "bt{l}\t{$src2, $src1|$src1, $src2}",
3599 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3602 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3603 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3604 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3605 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3606 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3607 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3608 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3609 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3610 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3611 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3612 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3613 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3614 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3615 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3616 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3617 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3619 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3620 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3621 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3622 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3623 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3624 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3625 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3626 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3627 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3628 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3629 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3630 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3631 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3632 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3633 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3634 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3636 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3637 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3638 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3639 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3640 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3641 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3642 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3643 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3644 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3645 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3646 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3647 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3648 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3649 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3650 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3651 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3652 } // Defs = [EFLAGS]
3654 // Sign/Zero extenders
3655 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3656 // of the register here. This has a smaller encoding and avoids a
3657 // partial-register update. Actual movsbw included for the disassembler.
3658 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3659 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3660 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3661 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3662 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3663 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3664 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3665 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3666 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3667 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3668 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3669 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3670 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3671 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3672 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3673 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3674 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3675 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3676 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3677 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3679 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3680 // of the register here. This has a smaller encoding and avoids a
3681 // partial-register update. Actual movzbw included for the disassembler.
3682 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3683 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3684 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3685 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3686 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3687 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3688 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3689 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3690 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3691 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3692 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3693 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3694 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3695 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3696 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3697 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3698 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3699 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3700 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3701 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3703 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3704 // except that they use GR32_NOREX for the output operand register class
3705 // instead of GR32. This allows them to operate on h registers on x86-64.
3706 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3707 (outs GR32_NOREX:$dst), (ins GR8:$src),
3708 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3711 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3712 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3713 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3716 let neverHasSideEffects = 1 in {
3717 let Defs = [AX], Uses = [AL] in
3718 def CBW : I<0x98, RawFrm, (outs), (ins),
3719 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3720 let Defs = [EAX], Uses = [AX] in
3721 def CWDE : I<0x98, RawFrm, (outs), (ins),
3722 "{cwtl|cwde}", []>; // EAX = signext(AX)
3724 let Defs = [AX,DX], Uses = [AX] in
3725 def CWD : I<0x99, RawFrm, (outs), (ins),
3726 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3727 let Defs = [EAX,EDX], Uses = [EAX] in
3728 def CDQ : I<0x99, RawFrm, (outs), (ins),
3729 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3732 //===----------------------------------------------------------------------===//
3733 // Alias Instructions
3734 //===----------------------------------------------------------------------===//
3736 // Alias instructions that map movr0 to xor.
3737 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3738 // FIXME: Set encoding to pseudo.
3739 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3740 isCodeGenOnly = 1 in {
3741 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3742 [(set GR8:$dst, 0)]>;
3744 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3745 // encoding and avoids a partial-register update sometimes, but doing so
3746 // at isel time interferes with rematerialization in the current register
3747 // allocator. For now, this is rewritten when the instruction is lowered
3749 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3751 [(set GR16:$dst, 0)]>, OpSize;
3753 // FIXME: Set encoding to pseudo.
3754 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3755 [(set GR32:$dst, 0)]>;
3758 //===----------------------------------------------------------------------===//
3759 // Thread Local Storage Instructions
3762 // All calls clobber the non-callee saved registers. ESP is marked as
3763 // a use to prevent stack-pointer assignments that appear immediately
3764 // before calls from potentially appearing dead.
3765 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3766 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3767 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3768 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3770 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3771 "leal\t$sym, %eax; "
3772 "call\t___tls_get_addr@PLT",
3773 [(X86tlsaddr tls32addr:$sym)]>,
3774 Requires<[In32BitMode]>;
3776 let AddedComplexity = 5, isCodeGenOnly = 1 in
3777 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3778 "movl\t%gs:$src, $dst",
3779 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3781 let AddedComplexity = 5, isCodeGenOnly = 1 in
3782 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3783 "movl\t%fs:$src, $dst",
3784 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3786 //===----------------------------------------------------------------------===//
3787 // EH Pseudo Instructions
3789 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3790 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3791 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3792 "ret\t#eh_return, addr: $addr",
3793 [(X86ehret GR32:$addr)]>;
3797 //===----------------------------------------------------------------------===//
3801 // Atomic swap. These are just normal xchg instructions. But since a memory
3802 // operand is referenced, the atomicity is ensured.
3803 let Constraints = "$val = $dst" in {
3804 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3805 (ins GR32:$val, i32mem:$ptr),
3806 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3807 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3808 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3809 (ins GR16:$val, i16mem:$ptr),
3810 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3811 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3813 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3814 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3815 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3817 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3818 "xchg{l}\t{$val, $src|$src, $val}", []>;
3819 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3820 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3821 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3822 "xchg{b}\t{$val, $src|$src, $val}", []>;
3825 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3826 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3827 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3828 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3830 // Atomic compare and swap.
3831 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3832 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3834 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3835 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3837 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3838 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3841 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3844 let Defs = [AX, EFLAGS], Uses = [AX] in {
3845 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3847 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3848 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3850 let Defs = [AL, EFLAGS], Uses = [AL] in {
3851 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3853 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3854 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3857 // Atomic exchange and add
3858 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3859 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3861 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3862 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3864 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3866 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3867 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3869 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3871 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3872 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3876 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3877 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3878 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3879 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3880 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3881 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3883 let mayLoad = 1, mayStore = 1 in {
3884 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3885 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3886 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3887 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3888 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3889 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3892 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3893 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3894 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3895 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3896 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3897 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3899 let mayLoad = 1, mayStore = 1 in {
3900 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3901 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
3902 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3903 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3904 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3905 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
3908 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
3909 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
3910 "cmpxchg8b\t$dst", []>, TB;
3912 // Optimized codegen when the non-memory output is not used.
3913 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
3914 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
3915 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3917 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3918 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3920 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3921 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3923 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3924 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
3926 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3927 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
3929 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3930 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
3932 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3933 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3935 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3936 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3938 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3940 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
3942 "inc{b}\t$dst", []>, LOCK;
3943 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
3945 "inc{w}\t$dst", []>, OpSize, LOCK;
3946 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
3948 "inc{l}\t$dst", []>, LOCK;
3950 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3952 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3953 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3955 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3956 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3958 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3959 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3961 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3962 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3964 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3965 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3967 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3968 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3970 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
3971 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3973 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
3975 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
3977 "dec{b}\t$dst", []>, LOCK;
3978 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
3980 "dec{w}\t$dst", []>, OpSize, LOCK;
3981 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
3983 "dec{l}\t$dst", []>, LOCK;
3986 // Atomic exchange, and, or, xor
3987 let Constraints = "$val = $dst", Defs = [EFLAGS],
3988 usesCustomInserter = 1 in {
3989 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3990 "#ATOMAND32 PSEUDO!",
3991 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3992 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3993 "#ATOMOR32 PSEUDO!",
3994 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3995 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3996 "#ATOMXOR32 PSEUDO!",
3997 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3998 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3999 "#ATOMNAND32 PSEUDO!",
4000 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
4001 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
4002 "#ATOMMIN32 PSEUDO!",
4003 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
4004 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4005 "#ATOMMAX32 PSEUDO!",
4006 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
4007 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4008 "#ATOMUMIN32 PSEUDO!",
4009 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
4010 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4011 "#ATOMUMAX32 PSEUDO!",
4012 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
4014 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4015 "#ATOMAND16 PSEUDO!",
4016 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4017 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4018 "#ATOMOR16 PSEUDO!",
4019 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4020 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4021 "#ATOMXOR16 PSEUDO!",
4022 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4023 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4024 "#ATOMNAND16 PSEUDO!",
4025 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4026 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4027 "#ATOMMIN16 PSEUDO!",
4028 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4029 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4030 "#ATOMMAX16 PSEUDO!",
4031 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4032 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4033 "#ATOMUMIN16 PSEUDO!",
4034 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4035 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4036 "#ATOMUMAX16 PSEUDO!",
4037 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4039 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4040 "#ATOMAND8 PSEUDO!",
4041 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4042 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4044 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4045 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4046 "#ATOMXOR8 PSEUDO!",
4047 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4048 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4049 "#ATOMNAND8 PSEUDO!",
4050 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4053 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4054 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4055 Uses = [EAX, EBX, ECX, EDX],
4056 mayLoad = 1, mayStore = 1,
4057 usesCustomInserter = 1 in {
4058 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4059 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4060 "#ATOMAND6432 PSEUDO!", []>;
4061 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4062 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4063 "#ATOMOR6432 PSEUDO!", []>;
4064 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4065 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4066 "#ATOMXOR6432 PSEUDO!", []>;
4067 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4068 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4069 "#ATOMNAND6432 PSEUDO!", []>;
4070 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4071 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4072 "#ATOMADD6432 PSEUDO!", []>;
4073 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4074 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4075 "#ATOMSUB6432 PSEUDO!", []>;
4076 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4077 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4078 "#ATOMSWAP6432 PSEUDO!", []>;
4081 // Segmentation support instructions.
4083 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4084 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4085 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4086 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4088 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4089 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4090 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4091 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4092 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4094 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4095 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4096 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4097 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4098 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4099 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4100 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4101 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4103 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4105 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4106 "str{w}\t{$dst}", []>, TB;
4107 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4108 "str{w}\t{$dst}", []>, TB;
4109 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4110 "ltr{w}\t{$src}", []>, TB;
4111 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4112 "ltr{w}\t{$src}", []>, TB;
4114 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4115 "push{w}\t%fs", []>, OpSize, TB;
4116 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4117 "push{l}\t%fs", []>, TB;
4118 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4119 "push{w}\t%gs", []>, OpSize, TB;
4120 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4121 "push{l}\t%gs", []>, TB;
4123 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4124 "pop{w}\t%fs", []>, OpSize, TB;
4125 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4126 "pop{l}\t%fs", []>, TB;
4127 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4128 "pop{w}\t%gs", []>, OpSize, TB;
4129 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4130 "pop{l}\t%gs", []>, TB;
4132 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4133 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4134 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4135 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4136 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4137 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4138 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4139 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4140 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4141 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4142 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4143 "les{l}\t{$src, $dst|$dst, $src}", []>;
4144 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4145 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4146 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4147 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4148 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4149 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4150 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4151 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4153 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4154 "verr\t$seg", []>, TB;
4155 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4156 "verr\t$seg", []>, TB;
4157 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4158 "verw\t$seg", []>, TB;
4159 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4160 "verw\t$seg", []>, TB;
4162 // Descriptor-table support instructions
4164 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4165 "sgdt\t$dst", []>, TB;
4166 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4167 "sidt\t$dst", []>, TB;
4168 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4169 "sldt{w}\t$dst", []>, TB;
4170 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4171 "sldt{w}\t$dst", []>, TB;
4172 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4173 "lgdt\t$src", []>, TB;
4174 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4175 "lidt\t$src", []>, TB;
4176 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4177 "lldt{w}\t$src", []>, TB;
4178 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4179 "lldt{w}\t$src", []>, TB;
4181 // Lock instruction prefix
4182 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4184 // Repeat string operation instruction prefixes
4185 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4186 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4187 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4188 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4189 // Repeat while not equal (used with CMPS and SCAS)
4190 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4193 // Segment override instruction prefixes
4194 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4195 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4196 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4197 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4198 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4199 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4201 // String manipulation instructions
4203 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4204 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4205 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4207 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4208 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4209 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4211 // CPU flow control instructions
4213 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4214 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4216 // FPU control instructions
4218 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4220 // Flag instructions
4222 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4223 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4224 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4225 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4226 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4227 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4228 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4230 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4232 // Table lookup instructions
4234 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4236 // Specialized register support
4238 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4239 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4240 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4242 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4243 "smsw{w}\t$dst", []>, OpSize, TB;
4244 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4245 "smsw{l}\t$dst", []>, TB;
4246 // For memory operands, there is only a 16-bit form
4247 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4248 "smsw{w}\t$dst", []>, TB;
4250 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4251 "lmsw{w}\t$src", []>, TB;
4252 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4253 "lmsw{w}\t$src", []>, TB;
4255 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4257 // Cache instructions
4259 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4260 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4265 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4267 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4269 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4270 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4271 "vmclear\t$vmcs", []>, OpSize, TB;
4273 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4275 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4276 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4277 "vmptrld\t$vmcs", []>, TB;
4278 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4279 "vmptrst\t$vmcs", []>, TB;
4280 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4281 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4282 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4283 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4284 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4285 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4286 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4287 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4288 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4289 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4290 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4291 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4292 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4293 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4294 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4295 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4297 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4298 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4299 "vmxon\t{$vmxon}", []>, XS;
4301 //===----------------------------------------------------------------------===//
4302 // Non-Instruction Patterns
4303 //===----------------------------------------------------------------------===//
4305 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4306 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4307 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4308 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4309 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4310 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4311 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4313 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4314 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4315 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4316 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4317 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4318 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4319 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4320 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4321 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4322 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4324 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4325 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4326 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4327 (MOV32mi addr:$dst, texternalsym:$src)>;
4328 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4329 (MOV32mi addr:$dst, tblockaddress:$src)>;
4333 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4334 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4335 Requires<[In32BitMode]>;
4337 // FIXME: This is disabled for 32-bit PIC mode because the global base
4338 // register which is part of the address mode may be assigned a
4339 // callee-saved register.
4340 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4341 (TCRETURNmi addr:$dst, imm:$off)>,
4342 Requires<[In32BitMode, IsNotPIC]>;
4344 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4345 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4346 Requires<[In32BitMode]>;
4348 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4349 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4350 Requires<[In32BitMode]>;
4352 // Normal calls, with various flavors of addresses.
4353 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4354 (CALLpcrel32 tglobaladdr:$dst)>;
4355 def : Pat<(X86call (i32 texternalsym:$dst)),
4356 (CALLpcrel32 texternalsym:$dst)>;
4357 def : Pat<(X86call (i32 imm:$dst)),
4358 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4360 // X86 specific add which produces a flag.
4361 def : Pat<(addc GR32:$src1, GR32:$src2),
4362 (ADD32rr GR32:$src1, GR32:$src2)>;
4363 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4364 (ADD32rm GR32:$src1, addr:$src2)>;
4365 def : Pat<(addc GR32:$src1, imm:$src2),
4366 (ADD32ri GR32:$src1, imm:$src2)>;
4367 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4368 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4370 def : Pat<(subc GR32:$src1, GR32:$src2),
4371 (SUB32rr GR32:$src1, GR32:$src2)>;
4372 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4373 (SUB32rm GR32:$src1, addr:$src2)>;
4374 def : Pat<(subc GR32:$src1, imm:$src2),
4375 (SUB32ri GR32:$src1, imm:$src2)>;
4376 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4377 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4381 // TEST R,R is smaller than CMP R,0
4382 def : Pat<(X86cmp GR8:$src1, 0),
4383 (TEST8rr GR8:$src1, GR8:$src1)>;
4384 def : Pat<(X86cmp GR16:$src1, 0),
4385 (TEST16rr GR16:$src1, GR16:$src1)>;
4386 def : Pat<(X86cmp GR32:$src1, 0),
4387 (TEST32rr GR32:$src1, GR32:$src1)>;
4389 // Conditional moves with folded loads with operands swapped and conditions
4391 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4392 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4393 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4394 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4395 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4396 (CMOVB16rm GR16:$src2, addr:$src1)>;
4397 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4398 (CMOVB32rm GR32:$src2, addr:$src1)>;
4399 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4400 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4401 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4402 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4403 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4404 (CMOVE16rm GR16:$src2, addr:$src1)>;
4405 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4406 (CMOVE32rm GR32:$src2, addr:$src1)>;
4407 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4408 (CMOVA16rm GR16:$src2, addr:$src1)>;
4409 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4410 (CMOVA32rm GR32:$src2, addr:$src1)>;
4411 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4412 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4413 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4414 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4415 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4416 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4417 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4418 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4419 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4420 (CMOVL16rm GR16:$src2, addr:$src1)>;
4421 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4422 (CMOVL32rm GR32:$src2, addr:$src1)>;
4423 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4424 (CMOVG16rm GR16:$src2, addr:$src1)>;
4425 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4426 (CMOVG32rm GR32:$src2, addr:$src1)>;
4427 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4428 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4429 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4430 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4431 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4432 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4433 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4434 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4435 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4436 (CMOVP16rm GR16:$src2, addr:$src1)>;
4437 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4438 (CMOVP32rm GR32:$src2, addr:$src1)>;
4439 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4440 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4441 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4442 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4443 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4444 (CMOVS16rm GR16:$src2, addr:$src1)>;
4445 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4446 (CMOVS32rm GR32:$src2, addr:$src1)>;
4447 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4448 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4449 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4450 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4451 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4452 (CMOVO16rm GR16:$src2, addr:$src1)>;
4453 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4454 (CMOVO32rm GR32:$src2, addr:$src1)>;
4456 // zextload bool -> zextload byte
4457 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4458 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4459 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4461 // extload bool -> extload byte
4462 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4463 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4464 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4465 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4466 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4467 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4469 // anyext. Define these to do an explicit zero-extend to
4470 // avoid partial-register updates.
4471 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4472 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4474 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
4475 def : Pat<(i32 (anyext GR16:$src)),
4476 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
4479 //===----------------------------------------------------------------------===//
4481 //===----------------------------------------------------------------------===//
4483 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4484 // +128 doesn't, so in this special case use a sub instead of an add.
4485 def : Pat<(add GR16:$src1, 128),
4486 (SUB16ri8 GR16:$src1, -128)>;
4487 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4488 (SUB16mi8 addr:$dst, -128)>;
4489 def : Pat<(add GR32:$src1, 128),
4490 (SUB32ri8 GR32:$src1, -128)>;
4491 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4492 (SUB32mi8 addr:$dst, -128)>;
4494 // r & (2^16-1) ==> movz
4495 def : Pat<(and GR32:$src1, 0xffff),
4496 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
4497 // r & (2^8-1) ==> movz
4498 def : Pat<(and GR32:$src1, 0xff),
4499 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4502 Requires<[In32BitMode]>;
4503 // r & (2^8-1) ==> movz
4504 def : Pat<(and GR16:$src1, 0xff),
4505 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4508 Requires<[In32BitMode]>;
4510 // sext_inreg patterns
4511 def : Pat<(sext_inreg GR32:$src, i16),
4512 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
4513 def : Pat<(sext_inreg GR32:$src, i8),
4514 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4517 Requires<[In32BitMode]>;
4518 def : Pat<(sext_inreg GR16:$src, i8),
4519 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4522 Requires<[In32BitMode]>;
4525 def : Pat<(i16 (trunc GR32:$src)),
4526 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
4527 def : Pat<(i8 (trunc GR32:$src)),
4528 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4530 Requires<[In32BitMode]>;
4531 def : Pat<(i8 (trunc GR16:$src)),
4532 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4534 Requires<[In32BitMode]>;
4536 // h-register tricks
4537 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4538 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4539 x86_subreg_8bit_hi)>,
4540 Requires<[In32BitMode]>;
4541 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4542 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4543 x86_subreg_8bit_hi)>,
4544 Requires<[In32BitMode]>;
4545 def : Pat<(srl GR16:$src, (i8 8)),
4548 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4549 x86_subreg_8bit_hi)),
4551 Requires<[In32BitMode]>;
4552 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4553 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4555 x86_subreg_8bit_hi))>,
4556 Requires<[In32BitMode]>;
4557 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4558 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4560 x86_subreg_8bit_hi))>,
4561 Requires<[In32BitMode]>;
4562 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4563 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4565 x86_subreg_8bit_hi))>,
4566 Requires<[In32BitMode]>;
4567 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
4568 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4570 x86_subreg_8bit_hi))>,
4571 Requires<[In32BitMode]>;
4573 // (shl x, 1) ==> (add x, x)
4574 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4575 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4576 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4578 // (shl x (and y, 31)) ==> (shl x, y)
4579 def : Pat<(shl GR8:$src1, (and CL, 31)),
4580 (SHL8rCL GR8:$src1)>;
4581 def : Pat<(shl GR16:$src1, (and CL, 31)),
4582 (SHL16rCL GR16:$src1)>;
4583 def : Pat<(shl GR32:$src1, (and CL, 31)),
4584 (SHL32rCL GR32:$src1)>;
4585 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4586 (SHL8mCL addr:$dst)>;
4587 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4588 (SHL16mCL addr:$dst)>;
4589 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4590 (SHL32mCL addr:$dst)>;
4592 def : Pat<(srl GR8:$src1, (and CL, 31)),
4593 (SHR8rCL GR8:$src1)>;
4594 def : Pat<(srl GR16:$src1, (and CL, 31)),
4595 (SHR16rCL GR16:$src1)>;
4596 def : Pat<(srl GR32:$src1, (and CL, 31)),
4597 (SHR32rCL GR32:$src1)>;
4598 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4599 (SHR8mCL addr:$dst)>;
4600 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4601 (SHR16mCL addr:$dst)>;
4602 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4603 (SHR32mCL addr:$dst)>;
4605 def : Pat<(sra GR8:$src1, (and CL, 31)),
4606 (SAR8rCL GR8:$src1)>;
4607 def : Pat<(sra GR16:$src1, (and CL, 31)),
4608 (SAR16rCL GR16:$src1)>;
4609 def : Pat<(sra GR32:$src1, (and CL, 31)),
4610 (SAR32rCL GR32:$src1)>;
4611 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4612 (SAR8mCL addr:$dst)>;
4613 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4614 (SAR16mCL addr:$dst)>;
4615 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4616 (SAR32mCL addr:$dst)>;
4618 // (anyext (setcc_carry)) -> (setcc_carry)
4619 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4621 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4623 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
4626 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4627 let AddedComplexity = 5 in { // Try this before the selecting to OR
4628 def : Pat<(or_is_add GR16:$src1, imm:$src2),
4629 (ADD16ri GR16:$src1, imm:$src2)>;
4630 def : Pat<(or_is_add GR32:$src1, imm:$src2),
4631 (ADD32ri GR32:$src1, imm:$src2)>;
4632 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
4633 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4634 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
4635 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4636 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
4637 (ADD16rr GR16:$src1, GR16:$src2)>;
4638 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
4639 (ADD32rr GR32:$src1, GR32:$src2)>;
4640 } // AddedComplexity
4642 //===----------------------------------------------------------------------===//
4643 // EFLAGS-defining Patterns
4644 //===----------------------------------------------------------------------===//
4647 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
4648 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
4649 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
4652 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
4653 (ADD8rm GR8:$src1, addr:$src2)>;
4654 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
4655 (ADD16rm GR16:$src1, addr:$src2)>;
4656 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
4657 (ADD32rm GR32:$src1, addr:$src2)>;
4660 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
4661 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
4662 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
4663 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
4664 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4665 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
4666 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4669 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
4670 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
4671 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
4674 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
4675 (SUB8rm GR8:$src1, addr:$src2)>;
4676 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
4677 (SUB16rm GR16:$src1, addr:$src2)>;
4678 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
4679 (SUB32rm GR32:$src1, addr:$src2)>;
4682 def : Pat<(sub GR8:$src1, imm:$src2),
4683 (SUB8ri GR8:$src1, imm:$src2)>;
4684 def : Pat<(sub GR16:$src1, imm:$src2),
4685 (SUB16ri GR16:$src1, imm:$src2)>;
4686 def : Pat<(sub GR32:$src1, imm:$src2),
4687 (SUB32ri GR32:$src1, imm:$src2)>;
4688 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
4689 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4690 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
4691 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4694 def : Pat<(mul GR16:$src1, GR16:$src2),
4695 (IMUL16rr GR16:$src1, GR16:$src2)>;
4696 def : Pat<(mul GR32:$src1, GR32:$src2),
4697 (IMUL32rr GR32:$src1, GR32:$src2)>;
4700 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
4701 (IMUL16rm GR16:$src1, addr:$src2)>;
4702 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
4703 (IMUL32rm GR32:$src1, addr:$src2)>;
4706 def : Pat<(mul GR16:$src1, imm:$src2),
4707 (IMUL16rri GR16:$src1, imm:$src2)>;
4708 def : Pat<(mul GR32:$src1, imm:$src2),
4709 (IMUL32rri GR32:$src1, imm:$src2)>;
4710 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
4711 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4712 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
4713 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4715 // reg = mul mem, imm
4716 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
4717 (IMUL16rmi addr:$src1, imm:$src2)>;
4718 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
4719 (IMUL32rmi addr:$src1, imm:$src2)>;
4720 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
4721 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4722 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
4723 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4725 // Optimize multiply by 2 with EFLAGS result.
4726 let AddedComplexity = 2 in {
4727 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
4728 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
4731 // Patterns for nodes that do not produce flags, for instructions that do.
4734 def : Pat<(add GR8:$src , 1), (INC8r GR8:$src)>;
4735 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>, Requires<[In32BitMode]>;
4736 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>, Requires<[In32BitMode]>;
4739 def : Pat<(add GR8:$src , -1), (DEC8r GR8:$src)>;
4740 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
4741 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
4744 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
4745 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
4746 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
4749 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
4750 (OR8rm GR8:$src1, addr:$src2)>;
4751 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
4752 (OR16rm GR16:$src1, addr:$src2)>;
4753 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
4754 (OR32rm GR32:$src1, addr:$src2)>;
4757 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
4758 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
4759 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
4760 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
4761 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4762 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
4763 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4766 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
4767 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
4768 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
4771 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
4772 (XOR8rm GR8:$src1, addr:$src2)>;
4773 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
4774 (XOR16rm GR16:$src1, addr:$src2)>;
4775 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
4776 (XOR32rm GR32:$src1, addr:$src2)>;
4779 def : Pat<(xor GR8:$src1, imm:$src2),
4780 (XOR8ri GR8:$src1, imm:$src2)>;
4781 def : Pat<(xor GR16:$src1, imm:$src2),
4782 (XOR16ri GR16:$src1, imm:$src2)>;
4783 def : Pat<(xor GR32:$src1, imm:$src2),
4784 (XOR32ri GR32:$src1, imm:$src2)>;
4785 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
4786 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4787 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
4788 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4791 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
4792 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
4793 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
4796 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
4797 (AND8rm GR8:$src1, addr:$src2)>;
4798 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
4799 (AND16rm GR16:$src1, addr:$src2)>;
4800 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
4801 (AND32rm GR32:$src1, addr:$src2)>;
4804 def : Pat<(and GR8:$src1, imm:$src2),
4805 (AND8ri GR8:$src1, imm:$src2)>;
4806 def : Pat<(and GR16:$src1, imm:$src2),
4807 (AND16ri GR16:$src1, imm:$src2)>;
4808 def : Pat<(and GR32:$src1, imm:$src2),
4809 (AND32ri GR32:$src1, imm:$src2)>;
4810 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
4811 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4812 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
4813 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4815 //===----------------------------------------------------------------------===//
4816 // Floating Point Stack Support
4817 //===----------------------------------------------------------------------===//
4819 include "X86InstrFPStack.td"
4821 //===----------------------------------------------------------------------===//
4823 //===----------------------------------------------------------------------===//
4825 include "X86Instr64bit.td"
4827 //===----------------------------------------------------------------------===//
4828 // SIMD support (SSE, MMX and AVX)
4829 //===----------------------------------------------------------------------===//
4831 include "X86InstrFragmentsSIMD.td"
4833 //===----------------------------------------------------------------------===//
4834 // XMM Floating point support (requires SSE / SSE2)
4835 //===----------------------------------------------------------------------===//
4837 include "X86InstrSSE.td"
4839 //===----------------------------------------------------------------------===//
4840 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4841 //===----------------------------------------------------------------------===//
4843 include "X86InstrMMX.td"