1 //===- X86InstrInfo.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
30 def SDTX86BrCond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i8>]>;
33 def SDTX86SetCC : SDTypeProfile<1, 1,
34 [SDTCisVT<0, i8>, SDTCisVT<1, i8>]>;
36 def SDTX86Ret : SDTypeProfile<0, 1, [SDTCisVT<0, i16>]>;
38 def SDT_X86CallSeqStart : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
39 def SDT_X86CallSeqEnd : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
42 def SDT_X86Call : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
44 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
46 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
48 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def SDT_X86TLSADDR : SDTypeProfile<1, 1, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
52 def SDT_X86TLSTP : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
54 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
56 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
57 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
59 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest,
60 [SDNPHasChain, SDNPOutFlag]>;
62 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov,
63 [SDNPInFlag, SDNPOutFlag]>;
64 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
65 [SDNPHasChain, SDNPInFlag]>;
66 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC,
67 [SDNPInFlag, SDNPOutFlag]>;
69 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
70 [SDNPHasChain, SDNPOptInFlag]>;
72 def X86callseq_start :
73 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
74 [SDNPHasChain, SDNPOutFlag]>;
76 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
77 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
79 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
80 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
82 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
83 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
85 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
86 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
87 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
88 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
90 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
91 [SDNPHasChain, SDNPOutFlag]>;
93 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
94 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
96 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
97 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
98 def X86TLStp : SDNode<"X86ISD::THREAD_POINTER", SDT_X86TLSTP, []>;
100 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
104 //===----------------------------------------------------------------------===//
105 // X86 Operand Definitions.
108 // *mem - Operand definitions for the funky X86 addressing mode operands.
110 class X86MemOperand<string printMethod> : Operand<iPTR> {
111 let PrintMethod = printMethod;
112 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
115 def i8mem : X86MemOperand<"printi8mem">;
116 def i16mem : X86MemOperand<"printi16mem">;
117 def i32mem : X86MemOperand<"printi32mem">;
118 def i64mem : X86MemOperand<"printi64mem">;
119 def i128mem : X86MemOperand<"printi128mem">;
120 def f32mem : X86MemOperand<"printf32mem">;
121 def f64mem : X86MemOperand<"printf64mem">;
122 def f80mem : X86MemOperand<"printf80mem">;
123 def f128mem : X86MemOperand<"printf128mem">;
125 def lea32mem : Operand<i32> {
126 let PrintMethod = "printi32mem";
127 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
130 def SSECC : Operand<i8> {
131 let PrintMethod = "printSSECC";
134 def piclabel: Operand<i32> {
135 let PrintMethod = "printPICLabel";
138 // A couple of more descriptive operand definitions.
139 // 16-bits but only 8 bits are significant.
140 def i16i8imm : Operand<i16>;
141 // 32-bits but only 8 bits are significant.
142 def i32i8imm : Operand<i32>;
144 // Branch targets have OtherVT type.
145 def brtarget : Operand<OtherVT>;
147 //===----------------------------------------------------------------------===//
148 // X86 Complex Pattern Definitions.
151 // Define X86 specific addressing mode.
152 def addr : ComplexPattern<iPTR, 4, "SelectAddr", [], []>;
153 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
154 [add, mul, shl, or, frameindex], []>;
156 //===----------------------------------------------------------------------===//
157 // X86 Instruction Predicate Definitions.
158 def HasMMX : Predicate<"Subtarget->hasMMX()">;
159 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
160 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
161 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
162 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
163 def FPStack : Predicate<"!Subtarget->hasSSE2()">;
164 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
165 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
166 def HasLow4G : Predicate<"Subtarget->hasLow4GUserSpaceAddress()">;
167 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
168 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
169 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
171 //===----------------------------------------------------------------------===//
172 // X86 Instruction Format Definitions.
175 include "X86InstrFormats.td"
177 //===----------------------------------------------------------------------===//
178 // Pattern fragments...
181 // X86 specific condition code. These correspond to CondCode in
182 // X86InstrInfo.h. They must be kept in synch.
183 def X86_COND_A : PatLeaf<(i8 0)>;
184 def X86_COND_AE : PatLeaf<(i8 1)>;
185 def X86_COND_B : PatLeaf<(i8 2)>;
186 def X86_COND_BE : PatLeaf<(i8 3)>;
187 def X86_COND_E : PatLeaf<(i8 4)>;
188 def X86_COND_G : PatLeaf<(i8 5)>;
189 def X86_COND_GE : PatLeaf<(i8 6)>;
190 def X86_COND_L : PatLeaf<(i8 7)>;
191 def X86_COND_LE : PatLeaf<(i8 8)>;
192 def X86_COND_NE : PatLeaf<(i8 9)>;
193 def X86_COND_NO : PatLeaf<(i8 10)>;
194 def X86_COND_NP : PatLeaf<(i8 11)>;
195 def X86_COND_NS : PatLeaf<(i8 12)>;
196 def X86_COND_O : PatLeaf<(i8 13)>;
197 def X86_COND_P : PatLeaf<(i8 14)>;
198 def X86_COND_S : PatLeaf<(i8 15)>;
200 def i16immSExt8 : PatLeaf<(i16 imm), [{
201 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
202 // sign extended field.
203 return (int16_t)N->getValue() == (int8_t)N->getValue();
206 def i32immSExt8 : PatLeaf<(i32 imm), [{
207 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
208 // sign extended field.
209 return (int32_t)N->getValue() == (int8_t)N->getValue();
212 // Helper fragments for loads.
213 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
214 def loadi16 : PatFrag<(ops node:$ptr), (i16 (load node:$ptr))>;
215 def loadi32 : PatFrag<(ops node:$ptr), (i32 (load node:$ptr))>;
216 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
218 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
219 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
220 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
222 def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextloadi1 node:$ptr))>;
223 def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextloadi1 node:$ptr))>;
224 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
225 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
226 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
228 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
229 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
230 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
231 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
232 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
233 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
235 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
236 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
237 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
238 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
239 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
240 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
242 //===----------------------------------------------------------------------===//
243 // Instruction list...
246 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
247 // a stack adjustment and the codegen must know that they may modify the stack
248 // pointer before prolog-epilog rewriting occurs.
249 def ADJCALLSTACKDOWN : I<0, Pseudo, (outs), (ins i32imm:$amt), "#ADJCALLSTACKDOWN",
250 [(X86callseq_start imm:$amt)]>, Imp<[ESP],[ESP]>;
251 def ADJCALLSTACKUP : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
253 [(X86callseq_end imm:$amt1, imm:$amt2)]>,
255 def IMPLICIT_USE : I<0, Pseudo, (outs), (ins variable_ops),
256 "#IMPLICIT_USE", []>;
257 def IMPLICIT_DEF : I<0, Pseudo, (outs variable_ops), (ins),
258 "#IMPLICIT_DEF", []>;
259 def IMPLICIT_DEF_GR8 : I<0, Pseudo, (outs GR8:$dst), (ins),
260 "#IMPLICIT_DEF $dst",
261 [(set GR8:$dst, (undef))]>;
262 def IMPLICIT_DEF_GR16 : I<0, Pseudo, (outs GR16:$dst), (ins),
263 "#IMPLICIT_DEF $dst",
264 [(set GR16:$dst, (undef))]>;
265 def IMPLICIT_DEF_GR32 : I<0, Pseudo, (outs GR32:$dst), (ins),
266 "#IMPLICIT_DEF $dst",
267 [(set GR32:$dst, (undef))]>;
270 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
273 //===----------------------------------------------------------------------===//
274 // Control Flow Instructions...
277 // Return instructions.
278 let isTerminator = 1, isReturn = 1, isBarrier = 1,
280 def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
281 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret\t$amt",
282 [(X86retflag imm:$amt)]>;
285 // All branches are RawFrm, Void, Branch, and Terminators
286 let isBranch = 1, isTerminator = 1 in
287 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
288 I<opcode, RawFrm, (outs), ins, asm, pattern>;
291 let isBranch = 1, isBarrier = 1 in
292 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
294 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
295 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
296 [(brind GR32:$dst)]>;
297 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
298 [(brind (loadi32 addr:$dst))]>;
301 // Conditional branches
302 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
303 [(X86brcond bb:$dst, X86_COND_E)]>, TB;
304 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
305 [(X86brcond bb:$dst, X86_COND_NE)]>, TB;
306 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
307 [(X86brcond bb:$dst, X86_COND_L)]>, TB;
308 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
309 [(X86brcond bb:$dst, X86_COND_LE)]>, TB;
310 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
311 [(X86brcond bb:$dst, X86_COND_G)]>, TB;
312 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
313 [(X86brcond bb:$dst, X86_COND_GE)]>, TB;
315 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
316 [(X86brcond bb:$dst, X86_COND_B)]>, TB;
317 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
318 [(X86brcond bb:$dst, X86_COND_BE)]>, TB;
319 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
320 [(X86brcond bb:$dst, X86_COND_A)]>, TB;
321 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
322 [(X86brcond bb:$dst, X86_COND_AE)]>, TB;
324 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
325 [(X86brcond bb:$dst, X86_COND_S)]>, TB;
326 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
327 [(X86brcond bb:$dst, X86_COND_NS)]>, TB;
328 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
329 [(X86brcond bb:$dst, X86_COND_P)]>, TB;
330 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
331 [(X86brcond bb:$dst, X86_COND_NP)]>, TB;
332 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
333 [(X86brcond bb:$dst, X86_COND_O)]>, TB;
334 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
335 [(X86brcond bb:$dst, X86_COND_NO)]>, TB;
337 //===----------------------------------------------------------------------===//
338 // Call Instructions...
341 // All calls clobber the non-callee saved registers...
342 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
343 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
344 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in {
345 def CALLpcrel32 : I<0xE8, RawFrm, (outs), (ins i32imm:$dst, variable_ops),
346 "call\t${dst:call}", []>;
347 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
348 "call\t{*}$dst", [(X86call GR32:$dst)]>;
349 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
350 "call\t{*}$dst", []>;
354 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
355 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp\t${dst:call} # TAIL CALL",
357 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
358 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp\t{*}$dst # TAIL CALL",
360 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
361 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
362 "jmp\t{*}$dst # TAIL CALL", []>;
364 //===----------------------------------------------------------------------===//
365 // Miscellaneous Instructions...
367 def LEAVE : I<0xC9, RawFrm,
368 (outs), (ins), "leave", []>, Imp<[EBP,ESP],[EBP,ESP]>;
369 def POP32r : I<0x58, AddRegFrm,
370 (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, Imp<[ESP],[ESP]>;
372 def PUSH32r : I<0x50, AddRegFrm,
373 (outs), (ins GR32:$reg), "push{l}\t$reg", []>, Imp<[ESP],[ESP]>;
375 def MovePCtoStack : I<0, Pseudo, (outs), (ins piclabel:$label),
378 let isTwoAddress = 1 in // GR32 = bswap GR32
379 def BSWAP32r : I<0xC8, AddRegFrm,
380 (outs GR32:$dst), (ins GR32:$src),
382 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
384 // FIXME: Model xchg* as two address instructions?
385 def XCHG8rr : I<0x86, MRMDestReg, // xchg GR8, GR8
386 (outs), (ins GR8:$src1, GR8:$src2),
387 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
388 def XCHG16rr : I<0x87, MRMDestReg, // xchg GR16, GR16
389 (outs), (ins GR16:$src1, GR16:$src2),
390 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
391 def XCHG32rr : I<0x87, MRMDestReg, // xchg GR32, GR32
392 (outs), (ins GR32:$src1, GR32:$src2),
393 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
395 def XCHG8mr : I<0x86, MRMDestMem,
396 (outs), (ins i8mem:$src1, GR8:$src2),
397 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
398 def XCHG16mr : I<0x87, MRMDestMem,
399 (outs), (ins i16mem:$src1, GR16:$src2),
400 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
401 def XCHG32mr : I<0x87, MRMDestMem,
402 (outs), (ins i32mem:$src1, GR32:$src2),
403 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
404 def XCHG8rm : I<0x86, MRMSrcMem,
405 (outs), (ins GR8:$src1, i8mem:$src2),
406 "xchg{b}\t{$src2|$src1}, {$src1|$src2}", []>;
407 def XCHG16rm : I<0x87, MRMSrcMem,
408 (outs), (ins GR16:$src1, i16mem:$src2),
409 "xchg{w}\t{$src2|$src1}, {$src1|$src2}", []>, OpSize;
410 def XCHG32rm : I<0x87, MRMSrcMem,
411 (outs), (ins GR32:$src1, i32mem:$src2),
412 "xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
414 def LEA16r : I<0x8D, MRMSrcMem,
415 (outs GR16:$dst), (ins i32mem:$src),
416 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
417 def LEA32r : I<0x8D, MRMSrcMem,
418 (outs GR32:$dst), (ins lea32mem:$src),
419 "lea{l}\t{$src|$dst}, {$dst|$src}",
420 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
422 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
424 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
425 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
426 [(X86rep_movs i16)]>,
427 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize;
428 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
429 [(X86rep_movs i32)]>,
430 Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP;
432 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
434 Imp<[AL,ECX,EDI], [ECX,EDI]>, REP;
435 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
436 [(X86rep_stos i16)]>,
437 Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize;
438 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
439 [(X86rep_stos i32)]>,
440 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
442 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
443 TB, Imp<[],[RAX,RDX]>;
445 //===----------------------------------------------------------------------===//
446 // Input/Output Instructions...
448 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
449 "in{b}\t{%dx, %al|%AL, %DX}",
450 []>, Imp<[DX], [AL]>;
451 def IN16rr : I<0xED, RawFrm, (outs), (ins),
452 "in{w}\t{%dx, %ax|%AX, %DX}",
453 []>, Imp<[DX], [AX]>, OpSize;
454 def IN32rr : I<0xED, RawFrm, (outs), (ins),
455 "in{l}\t{%dx, %eax|%EAX, %DX}",
456 []>, Imp<[DX],[EAX]>;
458 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
459 "in{b}\t{$port, %al|%AL, $port}",
462 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
463 "in{w}\t{$port, %ax|%AX, $port}",
465 Imp<[], [AX]>, OpSize;
466 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
467 "in{l}\t{$port, %eax|%EAX, $port}",
471 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
472 "out{b}\t{%al, %dx|%DX, %AL}",
473 []>, Imp<[DX, AL], []>;
474 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
475 "out{w}\t{%ax, %dx|%DX, %AX}",
476 []>, Imp<[DX, AX], []>, OpSize;
477 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
478 "out{l}\t{%eax, %dx|%DX, %EAX}",
479 []>, Imp<[DX, EAX], []>;
481 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
482 "out{b}\t{%al, $port|$port, %AL}",
485 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
486 "out{w}\t{%ax, $port|$port, %AX}",
488 Imp<[AX], []>, OpSize;
489 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
490 "out{l}\t{%eax, $port|$port, %EAX}",
494 //===----------------------------------------------------------------------===//
495 // Move Instructions...
497 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
498 "mov{b}\t{$src, $dst|$dst, $src}", []>;
499 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
500 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
501 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
502 "mov{l}\t{$src, $dst|$dst, $src}", []>;
503 let isReMaterializable = 1 in {
504 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
505 "mov{b}\t{$src, $dst|$dst, $src}",
506 [(set GR8:$dst, imm:$src)]>;
507 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
508 "mov{w}\t{$src, $dst|$dst, $src}",
509 [(set GR16:$dst, imm:$src)]>, OpSize;
510 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
511 "mov{l}\t{$src, $dst|$dst, $src}",
512 [(set GR32:$dst, imm:$src)]>;
514 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
515 "mov{b}\t{$src, $dst|$dst, $src}",
516 [(store (i8 imm:$src), addr:$dst)]>;
517 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
518 "mov{w}\t{$src, $dst|$dst, $src}",
519 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
520 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
521 "mov{l}\t{$src, $dst|$dst, $src}",
522 [(store (i32 imm:$src), addr:$dst)]>;
525 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
526 "mov{b}\t{$src, $dst|$dst, $src}",
527 [(set GR8:$dst, (load addr:$src))]>;
528 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
529 "mov{w}\t{$src, $dst|$dst, $src}",
530 [(set GR16:$dst, (load addr:$src))]>, OpSize;
531 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
532 "mov{l}\t{$src, $dst|$dst, $src}",
533 [(set GR32:$dst, (load addr:$src))]>;
536 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
537 "mov{b}\t{$src, $dst|$dst, $src}",
538 [(store GR8:$src, addr:$dst)]>;
539 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
540 "mov{w}\t{$src, $dst|$dst, $src}",
541 [(store GR16:$src, addr:$dst)]>, OpSize;
542 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
543 "mov{l}\t{$src, $dst|$dst, $src}",
544 [(store GR32:$src, addr:$dst)]>;
546 //===----------------------------------------------------------------------===//
547 // Fixed-Register Multiplication and Division Instructions...
550 // Extra precision multiplication
551 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
552 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
553 // This probably ought to be moved to a def : Pat<> if the
554 // syntax can be accepted.
555 [(set AL, (mul AL, GR8:$src))]>,
556 Imp<[AL],[AL,AH]>; // AL,AH = AL*GR8
557 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
558 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
559 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), "mul{l}\t$src", []>,
560 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
561 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
563 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
564 // This probably ought to be moved to a def : Pat<> if the
565 // syntax can be accepted.
566 [(set AL, (mul AL, (loadi8 addr:$src)))]>,
567 Imp<[AL],[AL,AH]>; // AL,AH = AL*[mem8]
568 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
569 "mul{w}\t$src", []>, Imp<[AX],[AX,DX]>,
570 OpSize; // AX,DX = AX*[mem16]
571 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
572 "mul{l}\t$src", []>, Imp<[EAX],[EAX,EDX]>;// EAX,EDX = EAX*[mem32]
574 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>,
575 Imp<[AL],[AL,AH]>; // AL,AH = AL*GR8
576 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
577 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
578 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>,
579 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*GR32
580 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
581 "imul{b}\t$src", []>, Imp<[AL],[AL,AH]>; // AL,AH = AL*[mem8]
582 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
583 "imul{w}\t$src", []>, Imp<[AX],[AX,DX]>,
584 OpSize; // AX,DX = AX*[mem16]
585 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
586 "imul{l}\t$src", []>,
587 Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
589 // unsigned division/remainder
590 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
591 "div{b}\t$src", []>, Imp<[AX],[AX]>;
592 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
593 "div{w}\t$src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
594 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
595 "div{l}\t$src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
596 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
597 "div{b}\t$src", []>, Imp<[AX],[AX]>;
598 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
599 "div{w}\t$src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
600 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
601 "div{l}\t$src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
603 // Signed division/remainder.
604 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
605 "idiv{b}\t$src", []>, Imp<[AX],[AX]>;
606 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
607 "idiv{w}\t$src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
608 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
609 "idiv{l}\t$src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
610 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
611 "idiv{b}\t$src", []>, Imp<[AX],[AX]>;
612 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
613 "idiv{w}\t$src", []>, Imp<[AX,DX],[AX,DX]>, OpSize;
614 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
615 "idiv{l}\t$src", []>, Imp<[EAX,EDX],[EAX,EDX]>;
618 //===----------------------------------------------------------------------===//
619 // Two address Instructions...
621 let isTwoAddress = 1 in {
624 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
625 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
626 "cmovb\t{$src2, $dst|$dst, $src2}",
627 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
630 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
631 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
632 "cmovb\t{$src2, $dst|$dst, $src2}",
633 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
636 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
637 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
638 "cmovb\t{$src2, $dst|$dst, $src2}",
639 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
642 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
643 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
644 "cmovb\t{$src2, $dst|$dst, $src2}",
645 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
649 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
650 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
651 "cmovae\t{$src2, $dst|$dst, $src2}",
652 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
655 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
656 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
657 "cmovae\t{$src2, $dst|$dst, $src2}",
658 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
661 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
662 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
663 "cmovae\t{$src2, $dst|$dst, $src2}",
664 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
667 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
668 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
669 "cmovae\t{$src2, $dst|$dst, $src2}",
670 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
674 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
675 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
676 "cmove\t{$src2, $dst|$dst, $src2}",
677 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
680 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
681 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
682 "cmove\t{$src2, $dst|$dst, $src2}",
683 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
686 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
687 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
688 "cmove\t{$src2, $dst|$dst, $src2}",
689 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
692 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
693 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
694 "cmove\t{$src2, $dst|$dst, $src2}",
695 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
699 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
700 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
701 "cmovne\t{$src2, $dst|$dst, $src2}",
702 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
705 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
706 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
707 "cmovne\t{$src2, $dst|$dst, $src2}",
708 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
711 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
712 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
713 "cmovne\t{$src2, $dst|$dst, $src2}",
714 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
717 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
718 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
719 "cmovne\t{$src2, $dst|$dst, $src2}",
720 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
724 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
725 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
726 "cmovbe\t{$src2, $dst|$dst, $src2}",
727 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
730 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
731 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
732 "cmovbe\t{$src2, $dst|$dst, $src2}",
733 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
736 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
737 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
738 "cmovbe\t{$src2, $dst|$dst, $src2}",
739 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
742 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
743 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
744 "cmovbe\t{$src2, $dst|$dst, $src2}",
745 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
749 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
750 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
751 "cmova\t{$src2, $dst|$dst, $src2}",
752 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
755 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
756 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
757 "cmova\t{$src2, $dst|$dst, $src2}",
758 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
761 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
762 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
763 "cmova\t{$src2, $dst|$dst, $src2}",
764 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
767 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
768 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
769 "cmova\t{$src2, $dst|$dst, $src2}",
770 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
774 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
775 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
776 "cmovl\t{$src2, $dst|$dst, $src2}",
777 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
780 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
781 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
782 "cmovl\t{$src2, $dst|$dst, $src2}",
783 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
786 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
787 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
788 "cmovl\t{$src2, $dst|$dst, $src2}",
789 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
792 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
793 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
794 "cmovl\t{$src2, $dst|$dst, $src2}",
795 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
799 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
800 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
801 "cmovge\t{$src2, $dst|$dst, $src2}",
802 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
805 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
806 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
807 "cmovge\t{$src2, $dst|$dst, $src2}",
808 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
811 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
812 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
813 "cmovge\t{$src2, $dst|$dst, $src2}",
814 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
817 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
818 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
819 "cmovge\t{$src2, $dst|$dst, $src2}",
820 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
824 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
825 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
826 "cmovle\t{$src2, $dst|$dst, $src2}",
827 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
830 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
831 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
832 "cmovle\t{$src2, $dst|$dst, $src2}",
833 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
836 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
837 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
838 "cmovle\t{$src2, $dst|$dst, $src2}",
839 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
842 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
843 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
844 "cmovle\t{$src2, $dst|$dst, $src2}",
845 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
849 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
850 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
851 "cmovg\t{$src2, $dst|$dst, $src2}",
852 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
855 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
856 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
857 "cmovg\t{$src2, $dst|$dst, $src2}",
858 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
861 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
862 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
863 "cmovg\t{$src2, $dst|$dst, $src2}",
864 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
867 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
868 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
869 "cmovg\t{$src2, $dst|$dst, $src2}",
870 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
874 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
875 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
876 "cmovs\t{$src2, $dst|$dst, $src2}",
877 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
880 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
881 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
882 "cmovs\t{$src2, $dst|$dst, $src2}",
883 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
886 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
887 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
888 "cmovs\t{$src2, $dst|$dst, $src2}",
889 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
892 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
893 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
894 "cmovs\t{$src2, $dst|$dst, $src2}",
895 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
899 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
900 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
901 "cmovns\t{$src2, $dst|$dst, $src2}",
902 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
905 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
906 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
907 "cmovns\t{$src2, $dst|$dst, $src2}",
908 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
911 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
912 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
913 "cmovns\t{$src2, $dst|$dst, $src2}",
914 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
917 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
918 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
919 "cmovns\t{$src2, $dst|$dst, $src2}",
920 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
924 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
925 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
926 "cmovp\t{$src2, $dst|$dst, $src2}",
927 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
930 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
931 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
932 "cmovp\t{$src2, $dst|$dst, $src2}",
933 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
936 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
937 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
938 "cmovp\t{$src2, $dst|$dst, $src2}",
939 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
942 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
943 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
944 "cmovp\t{$src2, $dst|$dst, $src2}",
945 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
949 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
950 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
951 "cmovnp\t{$src2, $dst|$dst, $src2}",
952 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
955 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
956 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
957 "cmovnp\t{$src2, $dst|$dst, $src2}",
958 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
961 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
962 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
963 "cmovnp\t{$src2, $dst|$dst, $src2}",
964 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
967 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
968 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
969 "cmovnp\t{$src2, $dst|$dst, $src2}",
970 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
975 // unary instructions
976 let CodeSize = 2 in {
977 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
978 [(set GR8:$dst, (ineg GR8:$src))]>;
979 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
980 [(set GR16:$dst, (ineg GR16:$src))]>, OpSize;
981 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
982 [(set GR32:$dst, (ineg GR32:$src))]>;
983 let isTwoAddress = 0 in {
984 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
985 [(store (ineg (loadi8 addr:$dst)), addr:$dst)]>;
986 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
987 [(store (ineg (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
988 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
989 [(store (ineg (loadi32 addr:$dst)), addr:$dst)]>;
993 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
994 [(set GR8:$dst, (not GR8:$src))]>;
995 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
996 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
997 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
998 [(set GR32:$dst, (not GR32:$src))]>;
999 let isTwoAddress = 0 in {
1000 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1001 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1002 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1003 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1004 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1005 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1009 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1011 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1012 [(set GR8:$dst, (add GR8:$src, 1))]>;
1013 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1014 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1015 [(set GR16:$dst, (add GR16:$src, 1))]>,
1016 OpSize, Requires<[In32BitMode]>;
1017 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1018 [(set GR32:$dst, (add GR32:$src, 1))]>, Requires<[In32BitMode]>;
1020 let isTwoAddress = 0, CodeSize = 2 in {
1021 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1022 [(store (add (loadi8 addr:$dst), 1), addr:$dst)]>;
1023 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1024 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>, OpSize;
1025 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1026 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>;
1030 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1031 [(set GR8:$dst, (add GR8:$src, -1))]>;
1032 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1033 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1034 [(set GR16:$dst, (add GR16:$src, -1))]>,
1035 OpSize, Requires<[In32BitMode]>;
1036 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1037 [(set GR32:$dst, (add GR32:$src, -1))]>, Requires<[In32BitMode]>;
1040 let isTwoAddress = 0, CodeSize = 2 in {
1041 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1042 [(store (add (loadi8 addr:$dst), -1), addr:$dst)]>;
1043 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1044 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>, OpSize;
1045 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1046 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>;
1049 // Logical operators...
1050 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1051 def AND8rr : I<0x20, MRMDestReg,
1052 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1053 "and{b}\t{$src2, $dst|$dst, $src2}",
1054 [(set GR8:$dst, (and GR8:$src1, GR8:$src2))]>;
1055 def AND16rr : I<0x21, MRMDestReg,
1056 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1057 "and{w}\t{$src2, $dst|$dst, $src2}",
1058 [(set GR16:$dst, (and GR16:$src1, GR16:$src2))]>, OpSize;
1059 def AND32rr : I<0x21, MRMDestReg,
1060 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1061 "and{l}\t{$src2, $dst|$dst, $src2}",
1062 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
1065 def AND8rm : I<0x22, MRMSrcMem,
1066 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1067 "and{b}\t{$src2, $dst|$dst, $src2}",
1068 [(set GR8:$dst, (and GR8:$src1, (load addr:$src2)))]>;
1069 def AND16rm : I<0x23, MRMSrcMem,
1070 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1071 "and{w}\t{$src2, $dst|$dst, $src2}",
1072 [(set GR16:$dst, (and GR16:$src1, (load addr:$src2)))]>, OpSize;
1073 def AND32rm : I<0x23, MRMSrcMem,
1074 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1075 "and{l}\t{$src2, $dst|$dst, $src2}",
1076 [(set GR32:$dst, (and GR32:$src1, (load addr:$src2)))]>;
1078 def AND8ri : Ii8<0x80, MRM4r,
1079 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1080 "and{b}\t{$src2, $dst|$dst, $src2}",
1081 [(set GR8:$dst, (and GR8:$src1, imm:$src2))]>;
1082 def AND16ri : Ii16<0x81, MRM4r,
1083 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1084 "and{w}\t{$src2, $dst|$dst, $src2}",
1085 [(set GR16:$dst, (and GR16:$src1, imm:$src2))]>, OpSize;
1086 def AND32ri : Ii32<0x81, MRM4r,
1087 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1088 "and{l}\t{$src2, $dst|$dst, $src2}",
1089 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
1090 def AND16ri8 : Ii8<0x83, MRM4r,
1091 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1092 "and{w}\t{$src2, $dst|$dst, $src2}",
1093 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2))]>,
1095 def AND32ri8 : Ii8<0x83, MRM4r,
1096 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1097 "and{l}\t{$src2, $dst|$dst, $src2}",
1098 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2))]>;
1100 let isTwoAddress = 0 in {
1101 def AND8mr : I<0x20, MRMDestMem,
1102 (outs), (ins i8mem :$dst, GR8 :$src),
1103 "and{b}\t{$src, $dst|$dst, $src}",
1104 [(store (and (load addr:$dst), GR8:$src), addr:$dst)]>;
1105 def AND16mr : I<0x21, MRMDestMem,
1106 (outs), (ins i16mem:$dst, GR16:$src),
1107 "and{w}\t{$src, $dst|$dst, $src}",
1108 [(store (and (load addr:$dst), GR16:$src), addr:$dst)]>,
1110 def AND32mr : I<0x21, MRMDestMem,
1111 (outs), (ins i32mem:$dst, GR32:$src),
1112 "and{l}\t{$src, $dst|$dst, $src}",
1113 [(store (and (load addr:$dst), GR32:$src), addr:$dst)]>;
1114 def AND8mi : Ii8<0x80, MRM4m,
1115 (outs), (ins i8mem :$dst, i8imm :$src),
1116 "and{b}\t{$src, $dst|$dst, $src}",
1117 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1118 def AND16mi : Ii16<0x81, MRM4m,
1119 (outs), (ins i16mem:$dst, i16imm:$src),
1120 "and{w}\t{$src, $dst|$dst, $src}",
1121 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1123 def AND32mi : Ii32<0x81, MRM4m,
1124 (outs), (ins i32mem:$dst, i32imm:$src),
1125 "and{l}\t{$src, $dst|$dst, $src}",
1126 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1127 def AND16mi8 : Ii8<0x83, MRM4m,
1128 (outs), (ins i16mem:$dst, i16i8imm :$src),
1129 "and{w}\t{$src, $dst|$dst, $src}",
1130 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1132 def AND32mi8 : Ii8<0x83, MRM4m,
1133 (outs), (ins i32mem:$dst, i32i8imm :$src),
1134 "and{l}\t{$src, $dst|$dst, $src}",
1135 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1139 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1140 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1141 "or{b}\t{$src2, $dst|$dst, $src2}",
1142 [(set GR8:$dst, (or GR8:$src1, GR8:$src2))]>;
1143 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1144 "or{w}\t{$src2, $dst|$dst, $src2}",
1145 [(set GR16:$dst, (or GR16:$src1, GR16:$src2))]>, OpSize;
1146 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1147 "or{l}\t{$src2, $dst|$dst, $src2}",
1148 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
1150 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1151 "or{b}\t{$src2, $dst|$dst, $src2}",
1152 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2)))]>;
1153 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1154 "or{w}\t{$src2, $dst|$dst, $src2}",
1155 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2)))]>, OpSize;
1156 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1157 "or{l}\t{$src2, $dst|$dst, $src2}",
1158 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2)))]>;
1160 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1161 "or{b}\t{$src2, $dst|$dst, $src2}",
1162 [(set GR8:$dst, (or GR8:$src1, imm:$src2))]>;
1163 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1164 "or{w}\t{$src2, $dst|$dst, $src2}",
1165 [(set GR16:$dst, (or GR16:$src1, imm:$src2))]>, OpSize;
1166 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1167 "or{l}\t{$src2, $dst|$dst, $src2}",
1168 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
1170 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1171 "or{w}\t{$src2, $dst|$dst, $src2}",
1172 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2))]>, OpSize;
1173 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1174 "or{l}\t{$src2, $dst|$dst, $src2}",
1175 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2))]>;
1176 let isTwoAddress = 0 in {
1177 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1178 "or{b}\t{$src, $dst|$dst, $src}",
1179 [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>;
1180 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1181 "or{w}\t{$src, $dst|$dst, $src}",
1182 [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>, OpSize;
1183 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1184 "or{l}\t{$src, $dst|$dst, $src}",
1185 [(store (or (load addr:$dst), GR32:$src), addr:$dst)]>;
1186 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1187 "or{b}\t{$src, $dst|$dst, $src}",
1188 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1189 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1190 "or{w}\t{$src, $dst|$dst, $src}",
1191 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1193 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1194 "or{l}\t{$src, $dst|$dst, $src}",
1195 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1196 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1197 "or{w}\t{$src, $dst|$dst, $src}",
1198 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1200 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1201 "or{l}\t{$src, $dst|$dst, $src}",
1202 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1206 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1207 def XOR8rr : I<0x30, MRMDestReg,
1208 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1209 "xor{b}\t{$src2, $dst|$dst, $src2}",
1210 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2))]>;
1211 def XOR16rr : I<0x31, MRMDestReg,
1212 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1213 "xor{w}\t{$src2, $dst|$dst, $src2}",
1214 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2))]>, OpSize;
1215 def XOR32rr : I<0x31, MRMDestReg,
1216 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1217 "xor{l}\t{$src2, $dst|$dst, $src2}",
1218 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
1221 def XOR8rm : I<0x32, MRMSrcMem ,
1222 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1223 "xor{b}\t{$src2, $dst|$dst, $src2}",
1224 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2)))]>;
1225 def XOR16rm : I<0x33, MRMSrcMem ,
1226 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1227 "xor{w}\t{$src2, $dst|$dst, $src2}",
1228 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2)))]>, OpSize;
1229 def XOR32rm : I<0x33, MRMSrcMem ,
1230 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1231 "xor{l}\t{$src2, $dst|$dst, $src2}",
1232 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2)))]>;
1234 def XOR8ri : Ii8<0x80, MRM6r,
1235 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1236 "xor{b}\t{$src2, $dst|$dst, $src2}",
1237 [(set GR8:$dst, (xor GR8:$src1, imm:$src2))]>;
1238 def XOR16ri : Ii16<0x81, MRM6r,
1239 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1240 "xor{w}\t{$src2, $dst|$dst, $src2}",
1241 [(set GR16:$dst, (xor GR16:$src1, imm:$src2))]>, OpSize;
1242 def XOR32ri : Ii32<0x81, MRM6r,
1243 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1244 "xor{l}\t{$src2, $dst|$dst, $src2}",
1245 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
1246 def XOR16ri8 : Ii8<0x83, MRM6r,
1247 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1248 "xor{w}\t{$src2, $dst|$dst, $src2}",
1249 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2))]>,
1251 def XOR32ri8 : Ii8<0x83, MRM6r,
1252 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1253 "xor{l}\t{$src2, $dst|$dst, $src2}",
1254 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2))]>;
1255 let isTwoAddress = 0 in {
1256 def XOR8mr : I<0x30, MRMDestMem,
1257 (outs), (ins i8mem :$dst, GR8 :$src),
1258 "xor{b}\t{$src, $dst|$dst, $src}",
1259 [(store (xor (load addr:$dst), GR8:$src), addr:$dst)]>;
1260 def XOR16mr : I<0x31, MRMDestMem,
1261 (outs), (ins i16mem:$dst, GR16:$src),
1262 "xor{w}\t{$src, $dst|$dst, $src}",
1263 [(store (xor (load addr:$dst), GR16:$src), addr:$dst)]>,
1265 def XOR32mr : I<0x31, MRMDestMem,
1266 (outs), (ins i32mem:$dst, GR32:$src),
1267 "xor{l}\t{$src, $dst|$dst, $src}",
1268 [(store (xor (load addr:$dst), GR32:$src), addr:$dst)]>;
1269 def XOR8mi : Ii8<0x80, MRM6m,
1270 (outs), (ins i8mem :$dst, i8imm :$src),
1271 "xor{b}\t{$src, $dst|$dst, $src}",
1272 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst)]>;
1273 def XOR16mi : Ii16<0x81, MRM6m,
1274 (outs), (ins i16mem:$dst, i16imm:$src),
1275 "xor{w}\t{$src, $dst|$dst, $src}",
1276 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst)]>,
1278 def XOR32mi : Ii32<0x81, MRM6m,
1279 (outs), (ins i32mem:$dst, i32imm:$src),
1280 "xor{l}\t{$src, $dst|$dst, $src}",
1281 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst)]>;
1282 def XOR16mi8 : Ii8<0x83, MRM6m,
1283 (outs), (ins i16mem:$dst, i16i8imm :$src),
1284 "xor{w}\t{$src, $dst|$dst, $src}",
1285 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst)]>,
1287 def XOR32mi8 : Ii8<0x83, MRM6m,
1288 (outs), (ins i32mem:$dst, i32i8imm :$src),
1289 "xor{l}\t{$src, $dst|$dst, $src}",
1290 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst)]>;
1293 // Shift instructions
1294 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1295 "shl{b}\t{%cl, $dst|$dst, %CL}",
1296 [(set GR8:$dst, (shl GR8:$src, CL))]>, Imp<[CL],[]>;
1297 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1298 "shl{w}\t{%cl, $dst|$dst, %CL}",
1299 [(set GR16:$dst, (shl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1300 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1301 "shl{l}\t{%cl, $dst|$dst, %CL}",
1302 [(set GR32:$dst, (shl GR32:$src, CL))]>, Imp<[CL],[]>;
1304 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1305 "shl{b}\t{$src2, $dst|$dst, $src2}",
1306 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1307 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1308 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1309 "shl{w}\t{$src2, $dst|$dst, $src2}",
1310 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1311 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1312 "shl{l}\t{$src2, $dst|$dst, $src2}",
1313 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1316 // Shift left by one. Not used because (add x, x) is slightly cheaper.
1317 def SHL8r1 : I<0xD0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
1318 "shl{b}\t$dst", []>;
1319 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
1320 "shl{w}\t$dst", []>, OpSize;
1321 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
1322 "shl{l}\t$dst", []>;
1324 let isTwoAddress = 0 in {
1325 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1326 "shl{b}\t{%cl, $dst|$dst, %CL}",
1327 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>,
1329 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1330 "shl{w}\t{%cl, $dst|$dst, %CL}",
1331 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>,
1332 Imp<[CL],[]>, OpSize;
1333 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1334 "shl{l}\t{%cl, $dst|$dst, %CL}",
1335 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>,
1337 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1338 "shl{b}\t{$src, $dst|$dst, $src}",
1339 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1340 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1341 "shl{w}\t{$src, $dst|$dst, $src}",
1342 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1344 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1345 "shl{l}\t{$src, $dst|$dst, $src}",
1346 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1349 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1351 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1352 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1354 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1356 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1358 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1361 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1362 "shr{b}\t{%cl, $dst|$dst, %CL}",
1363 [(set GR8:$dst, (srl GR8:$src, CL))]>, Imp<[CL],[]>;
1364 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1365 "shr{w}\t{%cl, $dst|$dst, %CL}",
1366 [(set GR16:$dst, (srl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1367 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1368 "shr{l}\t{%cl, $dst|$dst, %CL}",
1369 [(set GR32:$dst, (srl GR32:$src, CL))]>, Imp<[CL],[]>;
1371 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1372 "shr{b}\t{$src2, $dst|$dst, $src2}",
1373 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1374 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1375 "shr{w}\t{$src2, $dst|$dst, $src2}",
1376 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1377 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1378 "shr{l}\t{$src2, $dst|$dst, $src2}",
1379 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1382 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1384 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1385 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1387 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1388 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1390 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1392 let isTwoAddress = 0 in {
1393 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1394 "shr{b}\t{%cl, $dst|$dst, %CL}",
1395 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>,
1397 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1398 "shr{w}\t{%cl, $dst|$dst, %CL}",
1399 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1400 Imp<[CL],[]>, OpSize;
1401 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1402 "shr{l}\t{%cl, $dst|$dst, %CL}",
1403 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>,
1405 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1406 "shr{b}\t{$src, $dst|$dst, $src}",
1407 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1408 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1409 "shr{w}\t{$src, $dst|$dst, $src}",
1410 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1412 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1413 "shr{l}\t{$src, $dst|$dst, $src}",
1414 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1417 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1419 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1420 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1422 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1423 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1425 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1428 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1429 "sar{b}\t{%cl, $dst|$dst, %CL}",
1430 [(set GR8:$dst, (sra GR8:$src, CL))]>, Imp<[CL],[]>;
1431 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1432 "sar{w}\t{%cl, $dst|$dst, %CL}",
1433 [(set GR16:$dst, (sra GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1434 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1435 "sar{l}\t{%cl, $dst|$dst, %CL}",
1436 [(set GR32:$dst, (sra GR32:$src, CL))]>, Imp<[CL],[]>;
1438 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1439 "sar{b}\t{$src2, $dst|$dst, $src2}",
1440 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1441 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1442 "sar{w}\t{$src2, $dst|$dst, $src2}",
1443 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1445 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1446 "sar{l}\t{$src2, $dst|$dst, $src2}",
1447 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1450 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1452 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1453 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1455 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1456 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1458 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1460 let isTwoAddress = 0 in {
1461 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1462 "sar{b}\t{%cl, $dst|$dst, %CL}",
1463 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>,
1465 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1466 "sar{w}\t{%cl, $dst|$dst, %CL}",
1467 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>,
1468 Imp<[CL],[]>, OpSize;
1469 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1470 "sar{l}\t{%cl, $dst|$dst, %CL}",
1471 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>,
1473 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1474 "sar{b}\t{$src, $dst|$dst, $src}",
1475 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1476 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1477 "sar{w}\t{$src, $dst|$dst, $src}",
1478 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1480 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1481 "sar{l}\t{$src, $dst|$dst, $src}",
1482 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1485 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1487 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1488 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1490 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1492 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1494 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1497 // Rotate instructions
1498 // FIXME: provide shorter instructions when imm8 == 1
1499 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1500 "rol{b}\t{%cl, $dst|$dst, %CL}",
1501 [(set GR8:$dst, (rotl GR8:$src, CL))]>, Imp<[CL],[]>;
1502 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1503 "rol{w}\t{%cl, $dst|$dst, %CL}",
1504 [(set GR16:$dst, (rotl GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1505 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1506 "rol{l}\t{%cl, $dst|$dst, %CL}",
1507 [(set GR32:$dst, (rotl GR32:$src, CL))]>, Imp<[CL],[]>;
1509 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1510 "rol{b}\t{$src2, $dst|$dst, $src2}",
1511 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1512 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1513 "rol{w}\t{$src2, $dst|$dst, $src2}",
1514 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1515 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1516 "rol{l}\t{$src2, $dst|$dst, $src2}",
1517 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1520 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1522 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1523 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1525 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1526 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1528 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1530 let isTwoAddress = 0 in {
1531 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1532 "rol{b}\t{%cl, $dst|$dst, %CL}",
1533 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>,
1535 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1536 "rol{w}\t{%cl, $dst|$dst, %CL}",
1537 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>,
1538 Imp<[CL],[]>, OpSize;
1539 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1540 "rol{l}\t{%cl, $dst|$dst, %CL}",
1541 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>,
1543 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1544 "rol{b}\t{$src, $dst|$dst, $src}",
1545 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1546 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1547 "rol{w}\t{$src, $dst|$dst, $src}",
1548 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1550 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
1551 "rol{l}\t{$src, $dst|$dst, $src}",
1552 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1555 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
1557 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1558 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
1560 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1562 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
1564 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1567 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
1568 "ror{b}\t{%cl, $dst|$dst, %CL}",
1569 [(set GR8:$dst, (rotr GR8:$src, CL))]>, Imp<[CL],[]>;
1570 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
1571 "ror{w}\t{%cl, $dst|$dst, %CL}",
1572 [(set GR16:$dst, (rotr GR16:$src, CL))]>, Imp<[CL],[]>, OpSize;
1573 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
1574 "ror{l}\t{%cl, $dst|$dst, %CL}",
1575 [(set GR32:$dst, (rotr GR32:$src, CL))]>, Imp<[CL],[]>;
1577 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1578 "ror{b}\t{$src2, $dst|$dst, $src2}",
1579 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
1580 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1581 "ror{w}\t{$src2, $dst|$dst, $src2}",
1582 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1583 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1584 "ror{l}\t{$src2, $dst|$dst, $src2}",
1585 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
1588 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1590 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
1591 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
1593 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
1594 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
1596 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
1598 let isTwoAddress = 0 in {
1599 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
1600 "ror{b}\t{%cl, $dst|$dst, %CL}",
1601 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>,
1603 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
1604 "ror{w}\t{%cl, $dst|$dst, %CL}",
1605 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>,
1606 Imp<[CL],[]>, OpSize;
1607 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
1608 "ror{l}\t{%cl, $dst|$dst, %CL}",
1609 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>,
1611 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1612 "ror{b}\t{$src, $dst|$dst, $src}",
1613 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1614 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
1615 "ror{w}\t{$src, $dst|$dst, $src}",
1616 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1618 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
1619 "ror{l}\t{$src, $dst|$dst, $src}",
1620 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1623 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
1625 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1626 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
1628 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1630 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
1632 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1637 // Double shift instructions (generalizations of rotate)
1638 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1639 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1640 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>,
1642 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1643 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1644 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>,
1646 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1647 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1648 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
1649 Imp<[CL],[]>, TB, OpSize;
1650 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1651 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1652 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
1653 Imp<[CL],[]>, TB, OpSize;
1655 let isCommutable = 1 in { // These instructions commute to each other.
1656 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
1657 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1658 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1659 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
1662 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
1663 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
1664 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1665 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
1668 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
1669 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1670 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1671 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
1674 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
1675 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
1676 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1677 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
1682 let isTwoAddress = 0 in {
1683 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1684 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1685 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
1688 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1689 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1690 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
1693 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
1694 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1695 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1696 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
1697 (i8 imm:$src3)), addr:$dst)]>,
1699 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
1700 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
1701 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1702 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
1703 (i8 imm:$src3)), addr:$dst)]>,
1706 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1707 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1708 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
1710 Imp<[CL],[]>, TB, OpSize;
1711 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1712 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
1713 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
1715 Imp<[CL],[]>, TB, OpSize;
1716 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
1717 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1718 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1719 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
1720 (i8 imm:$src3)), addr:$dst)]>,
1722 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
1723 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
1724 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1725 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
1726 (i8 imm:$src3)), addr:$dst)]>,
1732 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
1733 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1734 "add{b}\t{$src2, $dst|$dst, $src2}",
1735 [(set GR8:$dst, (add GR8:$src1, GR8:$src2))]>;
1736 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1737 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1738 "add{w}\t{$src2, $dst|$dst, $src2}",
1739 [(set GR16:$dst, (add GR16:$src1, GR16:$src2))]>, OpSize;
1740 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1741 "add{l}\t{$src2, $dst|$dst, $src2}",
1742 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
1743 } // end isConvertibleToThreeAddress
1744 } // end isCommutable
1745 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1746 "add{b}\t{$src2, $dst|$dst, $src2}",
1747 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2)))]>;
1748 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1749 "add{w}\t{$src2, $dst|$dst, $src2}",
1750 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2)))]>, OpSize;
1751 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1752 "add{l}\t{$src2, $dst|$dst, $src2}",
1753 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2)))]>;
1755 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1756 "add{b}\t{$src2, $dst|$dst, $src2}",
1757 [(set GR8:$dst, (add GR8:$src1, imm:$src2))]>;
1759 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1760 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1761 "add{w}\t{$src2, $dst|$dst, $src2}",
1762 [(set GR16:$dst, (add GR16:$src1, imm:$src2))]>, OpSize;
1763 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1764 "add{l}\t{$src2, $dst|$dst, $src2}",
1765 [(set GR32:$dst, (add GR32:$src1, imm:$src2))]>;
1766 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1767 "add{w}\t{$src2, $dst|$dst, $src2}",
1768 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2))]>,
1770 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1771 "add{l}\t{$src2, $dst|$dst, $src2}",
1772 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2))]>;
1775 let isTwoAddress = 0 in {
1776 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1777 "add{b}\t{$src2, $dst|$dst, $src2}",
1778 [(store (add (load addr:$dst), GR8:$src2), addr:$dst)]>;
1779 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1780 "add{w}\t{$src2, $dst|$dst, $src2}",
1781 [(store (add (load addr:$dst), GR16:$src2), addr:$dst)]>,
1783 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1784 "add{l}\t{$src2, $dst|$dst, $src2}",
1785 [(store (add (load addr:$dst), GR32:$src2), addr:$dst)]>;
1786 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
1787 "add{b}\t{$src2, $dst|$dst, $src2}",
1788 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1789 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
1790 "add{w}\t{$src2, $dst|$dst, $src2}",
1791 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1793 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
1794 "add{l}\t{$src2, $dst|$dst, $src2}",
1795 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1796 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1797 "add{w}\t{$src2, $dst|$dst, $src2}",
1798 [(store (add (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1800 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1801 "add{l}\t{$src2, $dst|$dst, $src2}",
1802 [(store (add (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1805 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
1806 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1807 "adc{l}\t{$src2, $dst|$dst, $src2}",
1808 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
1810 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1811 "adc{l}\t{$src2, $dst|$dst, $src2}",
1812 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
1813 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1814 "adc{l}\t{$src2, $dst|$dst, $src2}",
1815 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
1816 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1817 "adc{l}\t{$src2, $dst|$dst, $src2}",
1818 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
1820 let isTwoAddress = 0 in {
1821 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1822 "adc{l}\t{$src2, $dst|$dst, $src2}",
1823 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
1824 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
1825 "adc{l}\t{$src2, $dst|$dst, $src2}",
1826 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1827 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1828 "adc{l}\t{$src2, $dst|$dst, $src2}",
1829 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1832 def SUB8rr : I<0x28, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1833 "sub{b}\t{$src2, $dst|$dst, $src2}",
1834 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2))]>;
1835 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1836 "sub{w}\t{$src2, $dst|$dst, $src2}",
1837 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2))]>, OpSize;
1838 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1839 "sub{l}\t{$src2, $dst|$dst, $src2}",
1840 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
1841 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1842 "sub{b}\t{$src2, $dst|$dst, $src2}",
1843 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2)))]>;
1844 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1845 "sub{w}\t{$src2, $dst|$dst, $src2}",
1846 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2)))]>, OpSize;
1847 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1848 "sub{l}\t{$src2, $dst|$dst, $src2}",
1849 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2)))]>;
1851 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1852 "sub{b}\t{$src2, $dst|$dst, $src2}",
1853 [(set GR8:$dst, (sub GR8:$src1, imm:$src2))]>;
1854 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1855 "sub{w}\t{$src2, $dst|$dst, $src2}",
1856 [(set GR16:$dst, (sub GR16:$src1, imm:$src2))]>, OpSize;
1857 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1858 "sub{l}\t{$src2, $dst|$dst, $src2}",
1859 [(set GR32:$dst, (sub GR32:$src1, imm:$src2))]>;
1860 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1861 "sub{w}\t{$src2, $dst|$dst, $src2}",
1862 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2))]>,
1864 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1865 "sub{l}\t{$src2, $dst|$dst, $src2}",
1866 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2))]>;
1867 let isTwoAddress = 0 in {
1868 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
1869 "sub{b}\t{$src2, $dst|$dst, $src2}",
1870 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst)]>;
1871 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
1872 "sub{w}\t{$src2, $dst|$dst, $src2}",
1873 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst)]>,
1875 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1876 "sub{l}\t{$src2, $dst|$dst, $src2}",
1877 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst)]>;
1878 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
1879 "sub{b}\t{$src2, $dst|$dst, $src2}",
1880 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1881 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
1882 "sub{w}\t{$src2, $dst|$dst, $src2}",
1883 [(store (sub (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
1885 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
1886 "sub{l}\t{$src2, $dst|$dst, $src2}",
1887 [(store (sub (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1888 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
1889 "sub{w}\t{$src2, $dst|$dst, $src2}",
1890 [(store (sub (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
1892 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1893 "sub{l}\t{$src2, $dst|$dst, $src2}",
1894 [(store (sub (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1897 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1898 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1899 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
1901 let isTwoAddress = 0 in {
1902 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
1903 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1904 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
1905 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
1906 "sbb{b}\t{$src2, $dst|$dst, $src2}",
1907 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
1908 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
1909 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1910 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
1911 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
1912 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1913 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
1915 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1916 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1917 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
1918 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1919 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1920 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
1921 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1922 "sbb{l}\t{$src2, $dst|$dst, $src2}",
1923 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
1925 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
1926 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1927 "imul{w}\t{$src2, $dst|$dst, $src2}",
1928 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2))]>, TB, OpSize;
1929 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1930 "imul{l}\t{$src2, $dst|$dst, $src2}",
1931 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>, TB;
1933 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1934 "imul{w}\t{$src2, $dst|$dst, $src2}",
1935 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2)))]>,
1937 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1938 "imul{l}\t{$src2, $dst|$dst, $src2}",
1939 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2)))]>, TB;
1941 } // end Two Address instructions
1943 // Suprisingly enough, these are not two address instructions!
1944 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
1945 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1946 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1947 [(set GR16:$dst, (mul GR16:$src1, imm:$src2))]>, OpSize;
1948 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
1949 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1950 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1951 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
1952 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
1953 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1954 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1955 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2))]>,
1957 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
1958 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1959 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1960 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2))]>;
1962 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
1963 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
1964 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1965 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2))]>,
1967 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
1968 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
1969 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1970 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2))]>;
1971 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
1972 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
1973 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1974 [(set GR16:$dst, (mul (load addr:$src1), i16immSExt8:$src2))]>,
1976 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
1977 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
1978 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1979 [(set GR32:$dst, (mul (load addr:$src1), i32immSExt8:$src2))]>;
1981 //===----------------------------------------------------------------------===//
1982 // Test instructions are just like AND, except they don't generate a result.
1984 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
1985 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
1986 "test{b}\t{$src2, $src1|$src1, $src2}",
1987 [(X86cmp (and GR8:$src1, GR8:$src2), 0)]>;
1988 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1989 "test{w}\t{$src2, $src1|$src1, $src2}",
1990 [(X86cmp (and GR16:$src1, GR16:$src2), 0)]>, OpSize;
1991 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1992 "test{l}\t{$src2, $src1|$src1, $src2}",
1993 [(X86cmp (and GR32:$src1, GR32:$src2), 0)]>;
1996 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
1997 "test{b}\t{$src2, $src1|$src1, $src2}",
1998 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)]>;
1999 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2000 "test{w}\t{$src2, $src1|$src1, $src2}",
2001 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)]>,
2003 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2004 "test{l}\t{$src2, $src1|$src1, $src2}",
2005 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)]>;
2007 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2008 (outs), (ins GR8:$src1, i8imm:$src2),
2009 "test{b}\t{$src2, $src1|$src1, $src2}",
2010 [(X86cmp (and GR8:$src1, imm:$src2), 0)]>;
2011 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2012 (outs), (ins GR16:$src1, i16imm:$src2),
2013 "test{w}\t{$src2, $src1|$src1, $src2}",
2014 [(X86cmp (and GR16:$src1, imm:$src2), 0)]>, OpSize;
2015 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2016 (outs), (ins GR32:$src1, i32imm:$src2),
2017 "test{l}\t{$src2, $src1|$src1, $src2}",
2018 [(X86cmp (and GR32:$src1, imm:$src2), 0)]>;
2020 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2021 (outs), (ins i8mem:$src1, i8imm:$src2),
2022 "test{b}\t{$src2, $src1|$src1, $src2}",
2023 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)]>;
2024 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2025 (outs), (ins i16mem:$src1, i16imm:$src2),
2026 "test{w}\t{$src2, $src1|$src1, $src2}",
2027 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)]>,
2029 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2030 (outs), (ins i32mem:$src1, i32imm:$src2),
2031 "test{l}\t{$src2, $src1|$src1, $src2}",
2032 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)]>;
2035 // Condition code ops, incl. set if equal/not equal/...
2036 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>, Imp<[AH],[]>; // flags = AH
2037 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, Imp<[],[AH]>; // AH = flags
2039 def SETEr : I<0x94, MRM0r,
2040 (outs GR8 :$dst), (ins),
2042 [(set GR8:$dst, (X86setcc X86_COND_E))]>,
2044 def SETEm : I<0x94, MRM0m,
2045 (outs), (ins i8mem:$dst),
2047 [(store (X86setcc X86_COND_E), addr:$dst)]>,
2049 def SETNEr : I<0x95, MRM0r,
2050 (outs GR8 :$dst), (ins),
2052 [(set GR8:$dst, (X86setcc X86_COND_NE))]>,
2054 def SETNEm : I<0x95, MRM0m,
2055 (outs), (ins i8mem:$dst),
2057 [(store (X86setcc X86_COND_NE), addr:$dst)]>,
2059 def SETLr : I<0x9C, MRM0r,
2060 (outs GR8 :$dst), (ins),
2062 [(set GR8:$dst, (X86setcc X86_COND_L))]>,
2063 TB; // GR8 = < signed
2064 def SETLm : I<0x9C, MRM0m,
2065 (outs), (ins i8mem:$dst),
2067 [(store (X86setcc X86_COND_L), addr:$dst)]>,
2068 TB; // [mem8] = < signed
2069 def SETGEr : I<0x9D, MRM0r,
2070 (outs GR8 :$dst), (ins),
2072 [(set GR8:$dst, (X86setcc X86_COND_GE))]>,
2073 TB; // GR8 = >= signed
2074 def SETGEm : I<0x9D, MRM0m,
2075 (outs), (ins i8mem:$dst),
2077 [(store (X86setcc X86_COND_GE), addr:$dst)]>,
2078 TB; // [mem8] = >= signed
2079 def SETLEr : I<0x9E, MRM0r,
2080 (outs GR8 :$dst), (ins),
2082 [(set GR8:$dst, (X86setcc X86_COND_LE))]>,
2083 TB; // GR8 = <= signed
2084 def SETLEm : I<0x9E, MRM0m,
2085 (outs), (ins i8mem:$dst),
2087 [(store (X86setcc X86_COND_LE), addr:$dst)]>,
2088 TB; // [mem8] = <= signed
2089 def SETGr : I<0x9F, MRM0r,
2090 (outs GR8 :$dst), (ins),
2092 [(set GR8:$dst, (X86setcc X86_COND_G))]>,
2093 TB; // GR8 = > signed
2094 def SETGm : I<0x9F, MRM0m,
2095 (outs), (ins i8mem:$dst),
2097 [(store (X86setcc X86_COND_G), addr:$dst)]>,
2098 TB; // [mem8] = > signed
2100 def SETBr : I<0x92, MRM0r,
2101 (outs GR8 :$dst), (ins),
2103 [(set GR8:$dst, (X86setcc X86_COND_B))]>,
2104 TB; // GR8 = < unsign
2105 def SETBm : I<0x92, MRM0m,
2106 (outs), (ins i8mem:$dst),
2108 [(store (X86setcc X86_COND_B), addr:$dst)]>,
2109 TB; // [mem8] = < unsign
2110 def SETAEr : I<0x93, MRM0r,
2111 (outs GR8 :$dst), (ins),
2113 [(set GR8:$dst, (X86setcc X86_COND_AE))]>,
2114 TB; // GR8 = >= unsign
2115 def SETAEm : I<0x93, MRM0m,
2116 (outs), (ins i8mem:$dst),
2118 [(store (X86setcc X86_COND_AE), addr:$dst)]>,
2119 TB; // [mem8] = >= unsign
2120 def SETBEr : I<0x96, MRM0r,
2121 (outs GR8 :$dst), (ins),
2123 [(set GR8:$dst, (X86setcc X86_COND_BE))]>,
2124 TB; // GR8 = <= unsign
2125 def SETBEm : I<0x96, MRM0m,
2126 (outs), (ins i8mem:$dst),
2128 [(store (X86setcc X86_COND_BE), addr:$dst)]>,
2129 TB; // [mem8] = <= unsign
2130 def SETAr : I<0x97, MRM0r,
2131 (outs GR8 :$dst), (ins),
2133 [(set GR8:$dst, (X86setcc X86_COND_A))]>,
2134 TB; // GR8 = > signed
2135 def SETAm : I<0x97, MRM0m,
2136 (outs), (ins i8mem:$dst),
2138 [(store (X86setcc X86_COND_A), addr:$dst)]>,
2139 TB; // [mem8] = > signed
2141 def SETSr : I<0x98, MRM0r,
2142 (outs GR8 :$dst), (ins),
2144 [(set GR8:$dst, (X86setcc X86_COND_S))]>,
2145 TB; // GR8 = <sign bit>
2146 def SETSm : I<0x98, MRM0m,
2147 (outs), (ins i8mem:$dst),
2149 [(store (X86setcc X86_COND_S), addr:$dst)]>,
2150 TB; // [mem8] = <sign bit>
2151 def SETNSr : I<0x99, MRM0r,
2152 (outs GR8 :$dst), (ins),
2154 [(set GR8:$dst, (X86setcc X86_COND_NS))]>,
2155 TB; // GR8 = !<sign bit>
2156 def SETNSm : I<0x99, MRM0m,
2157 (outs), (ins i8mem:$dst),
2159 [(store (X86setcc X86_COND_NS), addr:$dst)]>,
2160 TB; // [mem8] = !<sign bit>
2161 def SETPr : I<0x9A, MRM0r,
2162 (outs GR8 :$dst), (ins),
2164 [(set GR8:$dst, (X86setcc X86_COND_P))]>,
2166 def SETPm : I<0x9A, MRM0m,
2167 (outs), (ins i8mem:$dst),
2169 [(store (X86setcc X86_COND_P), addr:$dst)]>,
2170 TB; // [mem8] = parity
2171 def SETNPr : I<0x9B, MRM0r,
2172 (outs GR8 :$dst), (ins),
2174 [(set GR8:$dst, (X86setcc X86_COND_NP))]>,
2175 TB; // GR8 = not parity
2176 def SETNPm : I<0x9B, MRM0m,
2177 (outs), (ins i8mem:$dst),
2179 [(store (X86setcc X86_COND_NP), addr:$dst)]>,
2180 TB; // [mem8] = not parity
2182 // Integer comparisons
2183 def CMP8rr : I<0x38, MRMDestReg,
2184 (outs), (ins GR8 :$src1, GR8 :$src2),
2185 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2186 [(X86cmp GR8:$src1, GR8:$src2)]>;
2187 def CMP16rr : I<0x39, MRMDestReg,
2188 (outs), (ins GR16:$src1, GR16:$src2),
2189 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2190 [(X86cmp GR16:$src1, GR16:$src2)]>, OpSize;
2191 def CMP32rr : I<0x39, MRMDestReg,
2192 (outs), (ins GR32:$src1, GR32:$src2),
2193 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2194 [(X86cmp GR32:$src1, GR32:$src2)]>;
2195 def CMP8mr : I<0x38, MRMDestMem,
2196 (outs), (ins i8mem :$src1, GR8 :$src2),
2197 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2198 [(X86cmp (loadi8 addr:$src1), GR8:$src2)]>;
2199 def CMP16mr : I<0x39, MRMDestMem,
2200 (outs), (ins i16mem:$src1, GR16:$src2),
2201 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2202 [(X86cmp (loadi16 addr:$src1), GR16:$src2)]>, OpSize;
2203 def CMP32mr : I<0x39, MRMDestMem,
2204 (outs), (ins i32mem:$src1, GR32:$src2),
2205 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2206 [(X86cmp (loadi32 addr:$src1), GR32:$src2)]>;
2207 def CMP8rm : I<0x3A, MRMSrcMem,
2208 (outs), (ins GR8 :$src1, i8mem :$src2),
2209 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2210 [(X86cmp GR8:$src1, (loadi8 addr:$src2))]>;
2211 def CMP16rm : I<0x3B, MRMSrcMem,
2212 (outs), (ins GR16:$src1, i16mem:$src2),
2213 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2214 [(X86cmp GR16:$src1, (loadi16 addr:$src2))]>, OpSize;
2215 def CMP32rm : I<0x3B, MRMSrcMem,
2216 (outs), (ins GR32:$src1, i32mem:$src2),
2217 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2218 [(X86cmp GR32:$src1, (loadi32 addr:$src2))]>;
2219 def CMP8ri : Ii8<0x80, MRM7r,
2220 (outs), (ins GR8:$src1, i8imm:$src2),
2221 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2222 [(X86cmp GR8:$src1, imm:$src2)]>;
2223 def CMP16ri : Ii16<0x81, MRM7r,
2224 (outs), (ins GR16:$src1, i16imm:$src2),
2225 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2226 [(X86cmp GR16:$src1, imm:$src2)]>, OpSize;
2227 def CMP32ri : Ii32<0x81, MRM7r,
2228 (outs), (ins GR32:$src1, i32imm:$src2),
2229 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2230 [(X86cmp GR32:$src1, imm:$src2)]>;
2231 def CMP8mi : Ii8 <0x80, MRM7m,
2232 (outs), (ins i8mem :$src1, i8imm :$src2),
2233 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2234 [(X86cmp (loadi8 addr:$src1), imm:$src2)]>;
2235 def CMP16mi : Ii16<0x81, MRM7m,
2236 (outs), (ins i16mem:$src1, i16imm:$src2),
2237 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2238 [(X86cmp (loadi16 addr:$src1), imm:$src2)]>, OpSize;
2239 def CMP32mi : Ii32<0x81, MRM7m,
2240 (outs), (ins i32mem:$src1, i32imm:$src2),
2241 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2242 [(X86cmp (loadi32 addr:$src1), imm:$src2)]>;
2243 def CMP16ri8 : Ii8<0x83, MRM7r,
2244 (outs), (ins GR16:$src1, i16i8imm:$src2),
2245 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2246 [(X86cmp GR16:$src1, i16immSExt8:$src2)]>, OpSize;
2247 def CMP16mi8 : Ii8<0x83, MRM7m,
2248 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2249 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2250 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2)]>, OpSize;
2251 def CMP32mi8 : Ii8<0x83, MRM7m,
2252 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2253 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2254 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2)]>;
2255 def CMP32ri8 : Ii8<0x83, MRM7r,
2256 (outs), (ins GR32:$src1, i32i8imm:$src2),
2257 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2258 [(X86cmp GR32:$src1, i32immSExt8:$src2)]>;
2260 // Sign/Zero extenders
2261 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2262 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2263 [(set GR16:$dst, (sext GR8:$src))]>, TB, OpSize;
2264 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2265 "movs{bw|x}\t{$src, $dst|$dst, $src}",
2266 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB, OpSize;
2267 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2268 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2269 [(set GR32:$dst, (sext GR8:$src))]>, TB;
2270 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2271 "movs{bl|x}\t{$src, $dst|$dst, $src}",
2272 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
2273 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2274 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2275 [(set GR32:$dst, (sext GR16:$src))]>, TB;
2276 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2277 "movs{wl|x}\t{$src, $dst|$dst, $src}",
2278 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
2280 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
2281 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2282 [(set GR16:$dst, (zext GR8:$src))]>, TB, OpSize;
2283 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
2284 "movz{bw|x}\t{$src, $dst|$dst, $src}",
2285 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB, OpSize;
2286 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
2287 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2288 [(set GR32:$dst, (zext GR8:$src))]>, TB;
2289 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
2290 "movz{bl|x}\t{$src, $dst|$dst, $src}",
2291 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
2292 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
2293 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2294 [(set GR32:$dst, (zext GR16:$src))]>, TB;
2295 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
2296 "movz{wl|x}\t{$src, $dst|$dst, $src}",
2297 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
2299 def CBW : I<0x98, RawFrm, (outs), (ins),
2300 "{cbtw|cbw}", []>, Imp<[AL],[AX]>, OpSize; // AX = signext(AL)
2301 def CWDE : I<0x98, RawFrm, (outs), (ins),
2302 "{cwtl|cwde}", []>, Imp<[AX],[EAX]>; // EAX = signext(AX)
2304 def CWD : I<0x99, RawFrm, (outs), (ins),
2305 "{cwtd|cwd}", []>, Imp<[AX],[AX,DX]>, OpSize; // DX:AX = signext(AX)
2306 def CDQ : I<0x99, RawFrm, (outs), (ins),
2307 "{cltd|cdq}", []>, Imp<[EAX],[EAX,EDX]>; // EDX:EAX = signext(EAX)
2310 //===----------------------------------------------------------------------===//
2311 // Alias Instructions
2312 //===----------------------------------------------------------------------===//
2314 // Alias instructions that map movr0 to xor.
2315 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2316 let isReMaterializable = 1 in {
2317 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
2318 "xor{b}\t$dst, $dst",
2319 [(set GR8:$dst, 0)]>;
2320 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
2321 "xor{w}\t$dst, $dst",
2322 [(set GR16:$dst, 0)]>, OpSize;
2323 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
2324 "xor{l}\t$dst, $dst",
2325 [(set GR32:$dst, 0)]>;
2328 // Basic operations on GR16 / GR32 subclasses GR16_ and GR32_ which contains only
2329 // those registers that have GR8 sub-registers (i.e. AX - DX, EAX - EDX).
2330 def MOV16to16_ : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16:$src),
2331 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2332 def MOV32to32_ : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32:$src),
2333 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2335 def MOV16_rr : I<0x89, MRMDestReg, (outs GR16_:$dst), (ins GR16_:$src),
2336 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2337 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
2338 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2340 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
2341 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2342 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
2343 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2345 def MOV16_mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16_:$src),
2346 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
2347 def MOV32_mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32_:$src),
2348 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2350 //===----------------------------------------------------------------------===//
2351 // Thread Local Storage Instructions
2354 def TLS_addr : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$sym),
2355 "leal\t${sym:mem}(,%ebx,1), $dst",
2356 [(set GR32:$dst, (X86tlsaddr tglobaltlsaddr:$sym))]>,
2359 let AddedComplexity = 10 in
2360 def TLS_gs_rr : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
2361 "movl\t%gs:($src), $dst",
2362 [(set GR32:$dst, (load (add X86TLStp, GR32:$src)))]>;
2364 let AddedComplexity = 15 in
2365 def TLS_gs_ri : I<0, Pseudo, (outs GR32:$dst), (ins i32imm:$src),
2366 "movl\t%gs:${src:mem}, $dst",
2368 (load (add X86TLStp, (X86Wrapper tglobaltlsaddr:$src))))]>;
2370 def TLS_tp : I<0, Pseudo, (outs GR32:$dst), (ins),
2371 "movl\t%gs:0, $dst",
2372 [(set GR32:$dst, X86TLStp)]>;
2374 //===----------------------------------------------------------------------===//
2375 // DWARF Pseudo Instructions
2378 def DWARF_LOC : I<0, Pseudo, (outs),
2379 (ins i32imm:$line, i32imm:$col, i32imm:$file),
2380 "; .loc ${file:debug}, ${line:debug}, ${col:debug}",
2381 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
2384 //===----------------------------------------------------------------------===//
2385 // EH Pseudo Instructions
2387 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2389 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
2390 "ret\t#eh_return, addr: $addr",
2391 [(X86ehret GR32:$addr)]>;
2395 //===----------------------------------------------------------------------===//
2396 // Non-Instruction Patterns
2397 //===----------------------------------------------------------------------===//
2399 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
2400 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
2401 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
2402 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)), (MOV32ri tglobaltlsaddr:$dst)>;
2403 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
2404 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
2406 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
2407 (ADD32ri GR32:$src1, tconstpool:$src2)>;
2408 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
2409 (ADD32ri GR32:$src1, tjumptable:$src2)>;
2410 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
2411 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
2412 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
2413 (ADD32ri GR32:$src1, texternalsym:$src2)>;
2415 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
2416 (MOV32mi addr:$dst, tglobaladdr:$src)>;
2417 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
2418 (MOV32mi addr:$dst, texternalsym:$src)>;
2421 def : Pat<(X86tailcall GR32:$dst),
2422 (CALL32r GR32:$dst)>;
2424 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
2425 (CALLpcrel32 tglobaladdr:$dst)>;
2426 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
2427 (CALLpcrel32 texternalsym:$dst)>;
2429 def : Pat<(X86call (i32 tglobaladdr:$dst)),
2430 (CALLpcrel32 tglobaladdr:$dst)>;
2431 def : Pat<(X86call (i32 texternalsym:$dst)),
2432 (CALLpcrel32 texternalsym:$dst)>;
2434 // X86 specific add which produces a flag.
2435 def : Pat<(addc GR32:$src1, GR32:$src2),
2436 (ADD32rr GR32:$src1, GR32:$src2)>;
2437 def : Pat<(addc GR32:$src1, (load addr:$src2)),
2438 (ADD32rm GR32:$src1, addr:$src2)>;
2439 def : Pat<(addc GR32:$src1, imm:$src2),
2440 (ADD32ri GR32:$src1, imm:$src2)>;
2441 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
2442 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
2444 def : Pat<(subc GR32:$src1, GR32:$src2),
2445 (SUB32rr GR32:$src1, GR32:$src2)>;
2446 def : Pat<(subc GR32:$src1, (load addr:$src2)),
2447 (SUB32rm GR32:$src1, addr:$src2)>;
2448 def : Pat<(subc GR32:$src1, imm:$src2),
2449 (SUB32ri GR32:$src1, imm:$src2)>;
2450 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
2451 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
2453 def : Pat<(truncstorei1 (i8 imm:$src), addr:$dst),
2454 (MOV8mi addr:$dst, imm:$src)>;
2455 def : Pat<(truncstorei1 GR8:$src, addr:$dst),
2456 (MOV8mr addr:$dst, GR8:$src)>;
2460 // TEST R,R is smaller than CMP R,0
2461 def : Pat<(X86cmp GR8:$src1, 0),
2462 (TEST8rr GR8:$src1, GR8:$src1)>;
2463 def : Pat<(X86cmp GR16:$src1, 0),
2464 (TEST16rr GR16:$src1, GR16:$src1)>;
2465 def : Pat<(X86cmp GR32:$src1, 0),
2466 (TEST32rr GR32:$src1, GR32:$src1)>;
2468 // {s|z}extload bool -> {s|z}extload byte
2469 def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
2470 def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
2471 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2472 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2473 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2475 // extload bool -> extload byte
2476 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
2477 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
2478 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
2479 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
2480 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
2481 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
2484 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
2485 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
2486 def : Pat<(i32 (anyext GR16:$src)), (MOVZX32rr16 GR16:$src)>;
2487 def : Pat<(i16 (anyext (loadi8 addr:$src))), (MOVZX16rm8 addr:$src)>;
2488 def : Pat<(i32 (anyext (loadi8 addr:$src))), (MOVZX32rm8 addr:$src)>;
2489 def : Pat<(i32 (anyext (loadi16 addr:$src))), (MOVZX32rm16 addr:$src)>;
2491 //===----------------------------------------------------------------------===//
2493 //===----------------------------------------------------------------------===//
2495 // (shl x, 1) ==> (add x, x)
2496 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
2497 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
2498 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
2500 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
2501 def : Pat<(or (srl GR32:$src1, CL:$amt),
2502 (shl GR32:$src2, (sub 32, CL:$amt))),
2503 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
2505 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
2506 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2507 (SHRD32mrCL addr:$dst, GR32:$src2)>;
2509 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
2510 def : Pat<(or (shl GR32:$src1, CL:$amt),
2511 (srl GR32:$src2, (sub 32, CL:$amt))),
2512 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
2514 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
2515 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
2516 (SHLD32mrCL addr:$dst, GR32:$src2)>;
2518 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
2519 def : Pat<(or (srl GR16:$src1, CL:$amt),
2520 (shl GR16:$src2, (sub 16, CL:$amt))),
2521 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
2523 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
2524 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2525 (SHRD16mrCL addr:$dst, GR16:$src2)>;
2527 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
2528 def : Pat<(or (shl GR16:$src1, CL:$amt),
2529 (srl GR16:$src2, (sub 16, CL:$amt))),
2530 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
2532 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
2533 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
2534 (SHLD16mrCL addr:$dst, GR16:$src2)>;
2537 //===----------------------------------------------------------------------===//
2538 // Floating Point Stack Support
2539 //===----------------------------------------------------------------------===//
2541 include "X86InstrFPStack.td"
2543 //===----------------------------------------------------------------------===//
2545 //===----------------------------------------------------------------------===//
2547 include "X86InstrX86-64.td"
2549 //===----------------------------------------------------------------------===//
2550 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
2551 //===----------------------------------------------------------------------===//
2553 include "X86InstrMMX.td"
2555 //===----------------------------------------------------------------------===//
2556 // XMM Floating point support (requires SSE / SSE2)
2557 //===----------------------------------------------------------------------===//
2559 include "X86InstrSSE.td"