1 //===----------------------------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
32 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 def SDTX86BrCond : SDTypeProfile<0, 3,
39 [SDTCisVT<0, OtherVT>,
40 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
42 def SDTX86SetCC : SDTypeProfile<1, 2,
44 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86SetCC_C : SDTypeProfile<1, 2,
47 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
49 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
51 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
53 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
54 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
55 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
57 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
58 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
61 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
63 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
67 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
69 def SDTX86Void : SDTypeProfile<0, 0, []>;
71 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
73 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
75 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
77 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
79 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
81 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
83 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
84 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
85 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
86 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
88 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
89 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
91 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
92 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
94 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
95 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
97 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
100 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
101 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
103 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
104 [SDNPHasChain, SDNPMayStore,
105 SDNPMayLoad, SDNPMemOperand]>;
106 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
107 [SDNPHasChain, SDNPMayStore,
108 SDNPMayLoad, SDNPMemOperand]>;
109 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
110 [SDNPHasChain, SDNPMayStore,
111 SDNPMayLoad, SDNPMemOperand]>;
112 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
113 [SDNPHasChain, SDNPMayStore,
114 SDNPMayLoad, SDNPMemOperand]>;
115 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
116 [SDNPHasChain, SDNPMayStore,
117 SDNPMayLoad, SDNPMemOperand]>;
118 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
119 [SDNPHasChain, SDNPMayStore,
120 SDNPMayLoad, SDNPMemOperand]>;
121 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
122 [SDNPHasChain, SDNPMayStore,
123 SDNPMayLoad, SDNPMemOperand]>;
124 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
125 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
127 def X86vastart_save_xmm_regs :
128 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
129 SDT_X86VASTART_SAVE_XMM_REGS,
130 [SDNPHasChain, SDNPVariadic]>;
132 def X86callseq_start :
133 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
134 [SDNPHasChain, SDNPOutFlag]>;
136 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
137 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
139 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
140 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
143 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
144 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
145 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
146 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
149 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
150 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
152 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
153 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
155 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
156 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
157 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
158 SDT_X86SegmentBaseAddress, []>;
160 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
163 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
164 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
166 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
168 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
169 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
171 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags,
174 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
175 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
176 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
178 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
180 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
183 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
185 def X86MingwAlloca : SDNode<"X86ISD::MINGW_ALLOCA", SDTX86Void,
186 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
188 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
191 //===----------------------------------------------------------------------===//
192 // X86 Operand Definitions.
195 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
196 // the index operand of an address, to conform to x86 encoding restrictions.
197 def ptr_rc_nosp : PointerLikeRegClass<1>;
199 // *mem - Operand definitions for the funky X86 addressing mode operands.
201 def X86MemAsmOperand : AsmOperandClass {
203 let SuperClasses = [];
205 def X86AbsMemAsmOperand : AsmOperandClass {
207 let SuperClasses = [X86MemAsmOperand];
209 class X86MemOperand<string printMethod> : Operand<iPTR> {
210 let PrintMethod = printMethod;
211 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
212 let ParserMatchClass = X86MemAsmOperand;
215 def opaque32mem : X86MemOperand<"printopaquemem">;
216 def opaque48mem : X86MemOperand<"printopaquemem">;
217 def opaque80mem : X86MemOperand<"printopaquemem">;
218 def opaque512mem : X86MemOperand<"printopaquemem">;
220 def i8mem : X86MemOperand<"printi8mem">;
221 def i16mem : X86MemOperand<"printi16mem">;
222 def i32mem : X86MemOperand<"printi32mem">;
223 def i64mem : X86MemOperand<"printi64mem">;
224 def i128mem : X86MemOperand<"printi128mem">;
225 //def i256mem : X86MemOperand<"printi256mem">;
226 def f32mem : X86MemOperand<"printf32mem">;
227 def f64mem : X86MemOperand<"printf64mem">;
228 def f80mem : X86MemOperand<"printf80mem">;
229 def f128mem : X86MemOperand<"printf128mem">;
230 def f256mem : X86MemOperand<"printf256mem">;
232 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
233 // plain GR64, so that it doesn't potentially require a REX prefix.
234 def i8mem_NOREX : Operand<i64> {
235 let PrintMethod = "printi8mem";
236 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
237 let ParserMatchClass = X86MemAsmOperand;
240 // Special i32mem for addresses of load folding tail calls. These are not
241 // allowed to use callee-saved registers since they must be scheduled
242 // after callee-saved register are popped.
243 def i32mem_TC : Operand<i32> {
244 let PrintMethod = "printi32mem";
245 let MIOperandInfo = (ops GR32_TC, i8imm, GR32_TC, i32imm, i8imm);
246 let ParserMatchClass = X86MemAsmOperand;
250 let ParserMatchClass = X86AbsMemAsmOperand,
251 PrintMethod = "print_pcrel_imm" in {
252 def i32imm_pcrel : Operand<i32>;
253 def i16imm_pcrel : Operand<i16>;
255 def offset8 : Operand<i64>;
256 def offset16 : Operand<i64>;
257 def offset32 : Operand<i64>;
258 def offset64 : Operand<i64>;
260 // Branch targets have OtherVT type and print as pc-relative values.
261 def brtarget : Operand<OtherVT>;
262 def brtarget8 : Operand<OtherVT>;
266 def SSECC : Operand<i8> {
267 let PrintMethod = "printSSECC";
270 class ImmSExtAsmOperandClass : AsmOperandClass {
271 let SuperClasses = [ImmAsmOperand];
272 let RenderMethod = "addImmOperands";
275 // Sign-extended immediate classes. We don't need to define the full lattice
276 // here because there is no instruction with an ambiguity between ImmSExti64i32
279 // The strange ranges come from the fact that the assembler always works with
280 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
281 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
284 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
285 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
286 let Name = "ImmSExti64i32";
289 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
290 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
291 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
292 let Name = "ImmSExti16i8";
293 let SuperClasses = [ImmSExti64i32AsmOperand];
296 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
297 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
298 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
299 let Name = "ImmSExti32i8";
303 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
304 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
305 let Name = "ImmSExti64i8";
306 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
307 ImmSExti64i32AsmOperand];
310 // A couple of more descriptive operand definitions.
311 // 16-bits but only 8 bits are significant.
312 def i16i8imm : Operand<i16> {
313 let ParserMatchClass = ImmSExti16i8AsmOperand;
315 // 32-bits but only 8 bits are significant.
316 def i32i8imm : Operand<i32> {
317 let ParserMatchClass = ImmSExti32i8AsmOperand;
320 //===----------------------------------------------------------------------===//
321 // X86 Complex Pattern Definitions.
324 // Define X86 specific addressing mode.
325 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
326 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
327 [add, sub, mul, X86mul_imm, shl, or, frameindex],
329 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
330 [tglobaltlsaddr], []>;
332 //===----------------------------------------------------------------------===//
333 // X86 Instruction Predicate Definitions.
334 def HasCMov : Predicate<"Subtarget->hasCMov()">;
335 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
336 def HasMMX : Predicate<"Subtarget->hasMMX()">;
337 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
338 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
339 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
340 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
341 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
342 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
343 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
344 def HasAVX : Predicate<"Subtarget->hasAVX()">;
345 def HasFMA3 : Predicate<"Subtarget->hasFMA3()">;
346 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
347 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
348 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
349 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
350 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
351 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
352 def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">;
353 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
354 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
355 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
356 "TM.getCodeModel() != CodeModel::Kernel">;
357 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
358 "TM.getCodeModel() == CodeModel::Kernel">;
359 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
360 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
361 def OptForSize : Predicate<"OptForSize">;
362 def OptForSpeed : Predicate<"!OptForSize">;
363 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
364 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
365 def HasAES : Predicate<"Subtarget->hasAES()">;
367 //===----------------------------------------------------------------------===//
368 // X86 Instruction Format Definitions.
371 include "X86InstrFormats.td"
373 //===----------------------------------------------------------------------===//
374 // Pattern fragments...
377 // X86 specific condition code. These correspond to CondCode in
378 // X86InstrInfo.h. They must be kept in synch.
379 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
380 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
381 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
382 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
383 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
384 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
385 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
386 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
387 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
388 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
389 def X86_COND_NO : PatLeaf<(i8 10)>;
390 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
391 def X86_COND_NS : PatLeaf<(i8 12)>;
392 def X86_COND_O : PatLeaf<(i8 13)>;
393 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
394 def X86_COND_S : PatLeaf<(i8 15)>;
396 def immSext8 : PatLeaf<(imm), [{
397 return N->getSExtValue() == (int8_t)N->getSExtValue();
400 def i16immSExt8 : PatLeaf<(i16 immSext8)>;
401 def i32immSExt8 : PatLeaf<(i32 immSext8)>;
403 /// Load patterns: these constraint the match to the right address space.
404 def dsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
405 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
406 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
407 if (PT->getAddressSpace() > 255)
412 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
413 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
414 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
415 return PT->getAddressSpace() == 256;
419 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
420 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
421 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
422 return PT->getAddressSpace() == 257;
427 // Helper fragments for loads.
428 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
429 // known to be 32-bit aligned or better. Ditto for i8 to i16.
430 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
431 LoadSDNode *LD = cast<LoadSDNode>(N);
432 if (const Value *Src = LD->getSrcValue())
433 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
434 if (PT->getAddressSpace() > 255)
436 ISD::LoadExtType ExtType = LD->getExtensionType();
437 if (ExtType == ISD::NON_EXTLOAD)
439 if (ExtType == ISD::EXTLOAD)
440 return LD->getAlignment() >= 2 && !LD->isVolatile();
444 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
445 LoadSDNode *LD = cast<LoadSDNode>(N);
446 if (const Value *Src = LD->getSrcValue())
447 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
448 if (PT->getAddressSpace() > 255)
450 ISD::LoadExtType ExtType = LD->getExtensionType();
451 if (ExtType == ISD::EXTLOAD)
452 return LD->getAlignment() >= 2 && !LD->isVolatile();
456 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
457 LoadSDNode *LD = cast<LoadSDNode>(N);
458 if (const Value *Src = LD->getSrcValue())
459 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
460 if (PT->getAddressSpace() > 255)
462 ISD::LoadExtType ExtType = LD->getExtensionType();
463 if (ExtType == ISD::NON_EXTLOAD)
465 if (ExtType == ISD::EXTLOAD)
466 return LD->getAlignment() >= 4 && !LD->isVolatile();
470 def loadi8 : PatFrag<(ops node:$ptr), (i8 (dsload node:$ptr))>;
471 def loadi64 : PatFrag<(ops node:$ptr), (i64 (dsload node:$ptr))>;
472 def loadf32 : PatFrag<(ops node:$ptr), (f32 (dsload node:$ptr))>;
473 def loadf64 : PatFrag<(ops node:$ptr), (f64 (dsload node:$ptr))>;
474 def loadf80 : PatFrag<(ops node:$ptr), (f80 (dsload node:$ptr))>;
476 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
477 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
478 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
480 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
481 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
482 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
483 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
484 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
485 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
487 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
488 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
489 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
490 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
491 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
492 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
495 // An 'and' node with a single use.
496 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
497 return N->hasOneUse();
499 // An 'srl' node with a single use.
500 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
501 return N->hasOneUse();
503 // An 'trunc' node with a single use.
504 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
505 return N->hasOneUse();
508 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
509 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
510 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
511 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
513 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
514 APInt Mask = APInt::getAllOnesValue(BitWidth);
515 APInt KnownZero0, KnownOne0;
516 CurDAG->ComputeMaskedBits(N->getOperand(0), Mask, KnownZero0, KnownOne0, 0);
517 APInt KnownZero1, KnownOne1;
518 CurDAG->ComputeMaskedBits(N->getOperand(1), Mask, KnownZero1, KnownOne1, 0);
519 return (~KnownZero0 & ~KnownZero1) == 0;
522 //===----------------------------------------------------------------------===//
523 // Instruction list...
526 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
527 // a stack adjustment and the codegen must know that they may modify the stack
528 // pointer before prolog-epilog rewriting occurs.
529 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
530 // sub / add which can clobber EFLAGS.
531 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
532 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
534 [(X86callseq_start timm:$amt)]>,
535 Requires<[In32BitMode]>;
536 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
538 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
539 Requires<[In32BitMode]>;
542 // x86-64 va_start lowering magic.
543 let usesCustomInserter = 1 in {
544 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
547 i64imm:$regsavefi, i64imm:$offset,
549 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
550 [(X86vastart_save_xmm_regs GR8:$al,
554 // Dynamic stack allocation yields _alloca call for Cygwin/Mingw targets. Calls
555 // to _alloca is needed to probe the stack when allocating more than 4k bytes in
556 // one go. Touching the stack at 4K increments is necessary to ensure that the
557 // guard pages used by the OS virtual memory manager are allocated in correct
559 // The main point of having separate instruction are extra unmodelled effects
560 // (compared to ordinary calls) like stack pointer change.
562 def MINGW_ALLOCA : I<0, Pseudo, (outs), (ins),
563 "# dynamic stack allocation",
568 let neverHasSideEffects = 1 in {
569 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
570 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
571 "nop{w}\t$zero", []>, TB, OpSize;
572 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
573 "nop{l}\t$zero", []>, TB;
577 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
578 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3", []>;
579 // FIXME: need to make sure that "int $3" matches int3
580 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap", []>;
581 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize;
582 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l}", []>;
584 // PIC base construction. This expands to code that looks like this:
587 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
588 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
591 //===----------------------------------------------------------------------===//
592 // Control Flow Instructions.
595 // Return instructions.
596 let isTerminator = 1, isReturn = 1, isBarrier = 1,
597 hasCtrlDep = 1, FPForm = SpecialFP in {
598 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
601 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
603 [(X86retflag timm:$amt)]>;
604 def LRET : I <0xCB, RawFrm, (outs), (ins),
606 def LRETI : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
610 // Unconditional branches.
611 let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
612 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
613 "jmp\t$dst", [(br bb:$dst)]>;
614 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
618 // Conditional Branches.
619 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
620 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
621 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
622 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
623 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
627 defm JO : ICBr<0x70, 0x80, "jo\t$dst" , X86_COND_O>;
628 defm JNO : ICBr<0x71, 0x81, "jno\t$dst" , X86_COND_NO>;
629 defm JB : ICBr<0x72, 0x82, "jb\t$dst" , X86_COND_B>;
630 defm JAE : ICBr<0x73, 0x83, "jae\t$dst", X86_COND_AE>;
631 defm JE : ICBr<0x74, 0x84, "je\t$dst" , X86_COND_E>;
632 defm JNE : ICBr<0x75, 0x85, "jne\t$dst", X86_COND_NE>;
633 defm JBE : ICBr<0x76, 0x86, "jbe\t$dst", X86_COND_BE>;
634 defm JA : ICBr<0x77, 0x87, "ja\t$dst" , X86_COND_A>;
635 defm JS : ICBr<0x78, 0x88, "js\t$dst" , X86_COND_S>;
636 defm JNS : ICBr<0x79, 0x89, "jns\t$dst", X86_COND_NS>;
637 defm JP : ICBr<0x7A, 0x8A, "jp\t$dst" , X86_COND_P>;
638 defm JNP : ICBr<0x7B, 0x8B, "jnp\t$dst", X86_COND_NP>;
639 defm JL : ICBr<0x7C, 0x8C, "jl\t$dst" , X86_COND_L>;
640 defm JGE : ICBr<0x7D, 0x8D, "jge\t$dst", X86_COND_GE>;
641 defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
642 defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
644 // FIXME: What about the CX/RCX versions of this instruction?
645 let Uses = [ECX], isBranch = 1, isTerminator = 1 in
646 def JCXZ8 : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst),
651 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
652 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
653 [(brind GR32:$dst)]>;
654 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
655 [(brind (loadi32 addr:$dst))]>;
657 def FARJMP16i : Iseg16<0xEA, RawFrm, (outs),
658 (ins i16imm:$seg, i16imm:$off),
659 "ljmp{w}\t$seg, $off", []>, OpSize;
660 def FARJMP32i : Iseg32<0xEA, RawFrm, (outs),
661 (ins i16imm:$seg, i32imm:$off),
662 "ljmp{l}\t$seg, $off", []>;
664 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
665 "ljmp{w}\t{*}$dst", []>, OpSize;
666 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
667 "ljmp{l}\t{*}$dst", []>;
673 def LOOP : I<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>;
674 def LOOPE : I<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>;
675 def LOOPNE : I<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>;
677 //===----------------------------------------------------------------------===//
678 // Call Instructions...
681 // All calls clobber the non-callee saved registers. ESP is marked as
682 // a use to prevent stack-pointer assignments that appear immediately
683 // before calls from potentially appearing dead. Uses for argument
684 // registers are added manually.
685 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
686 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
687 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
688 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
690 def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
691 (outs), (ins i32imm_pcrel:$dst,variable_ops),
693 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
694 "call\t{*}$dst", [(X86call GR32:$dst)]>;
695 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
696 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
698 def FARCALL16i : Iseg16<0x9A, RawFrm, (outs),
699 (ins i16imm:$seg, i16imm:$off),
700 "lcall{w}\t$seg, $off", []>, OpSize;
701 def FARCALL32i : Iseg32<0x9A, RawFrm, (outs),
702 (ins i16imm:$seg, i32imm:$off),
703 "lcall{l}\t$seg, $off", []>;
705 def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
706 "lcall{w}\t{*}$dst", []>, OpSize;
707 def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
708 "lcall{l}\t{*}$dst", []>;
710 // callw for 16 bit code for the assembler.
711 let isAsmParserOnly = 1 in
712 def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
713 (outs), (ins i16imm_pcrel:$dst, variable_ops),
714 "callw\t$dst", []>, OpSize;
717 // Constructing a stack frame.
719 def ENTER : I<0xC8, RawFrm, (outs), (ins i16imm:$len, i8imm:$lvl),
720 "enter\t$len, $lvl", []>;
724 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
725 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
726 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
727 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
728 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
730 def TCRETURNdi : I<0, Pseudo, (outs),
731 (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops),
732 "#TC_RETURN $dst $offset", []>;
733 def TCRETURNri : I<0, Pseudo, (outs),
734 (ins GR32_TC:$dst, i32imm:$offset, variable_ops),
735 "#TC_RETURN $dst $offset", []>;
737 def TCRETURNmi : I<0, Pseudo, (outs),
738 (ins i32mem_TC:$dst, i32imm:$offset, variable_ops),
739 "#TC_RETURN $dst $offset", []>;
741 // FIXME: The should be pseudo instructions that are lowered when going to
743 def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs),
744 (ins i32imm_pcrel:$dst, variable_ops),
745 "jmp\t$dst # TAILCALL",
747 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
748 "", []>; // FIXME: Remove encoding when JIT is dead.
750 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops),
751 "jmp{l}\t{*}$dst # TAILCALL", []>;
754 //===----------------------------------------------------------------------===//
755 // Miscellaneous Instructions...
757 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
758 def LEAVE : I<0xC9, RawFrm,
759 (outs), (ins), "leave", []>;
761 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
762 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
764 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
765 "popcnt{w}\t{$src, $dst|$dst, $src}", []>, OpSize, XS;
766 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
767 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
769 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
770 "popcnt{l}\t{$src, $dst|$dst, $src}", []>, XS;
772 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
774 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
776 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
777 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>,
779 def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", []>,
781 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
782 def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", []>;
785 let mayStore = 1 in {
786 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
788 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
789 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
791 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[]>,
793 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
794 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[]>;
798 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
799 def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
800 "push{l}\t$imm", []>;
801 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
802 "push{w}\t$imm", []>, OpSize;
803 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
804 "push{l}\t$imm", []>;
807 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in {
808 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
809 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>,
810 Requires<[In32BitMode]>;
812 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in {
813 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
814 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>,
815 Requires<[In32BitMode]>;
818 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
819 mayLoad=1, neverHasSideEffects=1 in {
820 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", []>,
821 Requires<[In32BitMode]>;
823 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
824 mayStore=1, neverHasSideEffects=1 in {
825 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", []>,
826 Requires<[In32BitMode]>;
829 let Uses = [EFLAGS], Constraints = "$src = $dst" in // GR32 = bswap GR32
830 def BSWAP32r : I<0xC8, AddRegFrm,
831 (outs GR32:$dst), (ins GR32:$src),
833 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
836 // Bit scan instructions.
837 let Defs = [EFLAGS] in {
838 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
839 "bsf{w}\t{$src, $dst|$dst, $src}",
840 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
841 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
842 "bsf{w}\t{$src, $dst|$dst, $src}",
843 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
845 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
846 "bsf{l}\t{$src, $dst|$dst, $src}",
847 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
848 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
849 "bsf{l}\t{$src, $dst|$dst, $src}",
850 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
852 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
853 "bsr{w}\t{$src, $dst|$dst, $src}",
854 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, TB, OpSize;
855 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
856 "bsr{w}\t{$src, $dst|$dst, $src}",
857 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, TB,
859 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
860 "bsr{l}\t{$src, $dst|$dst, $src}",
861 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, TB;
862 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
863 "bsr{l}\t{$src, $dst|$dst, $src}",
864 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, TB;
867 let neverHasSideEffects = 1 in
868 def LEA16r : I<0x8D, MRMSrcMem,
869 (outs GR16:$dst), (ins i32mem:$src),
870 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
871 let isReMaterializable = 1 in
872 def LEA32r : I<0x8D, MRMSrcMem,
873 (outs GR32:$dst), (ins i32mem:$src),
874 "lea{l}\t{$src|$dst}, {$dst|$src}",
875 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
877 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
878 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
879 [(X86rep_movs i8)]>, REP;
880 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
881 [(X86rep_movs i16)]>, REP, OpSize;
882 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
883 [(X86rep_movs i32)]>, REP;
886 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
887 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
888 def MOVSB : I<0xA4, RawFrm, (outs), (ins), "{movsb}", []>;
889 def MOVSW : I<0xA5, RawFrm, (outs), (ins), "{movsw}", []>, OpSize;
890 def MOVSD : I<0xA5, RawFrm, (outs), (ins), "{movsl|movsd}", []>;
893 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI], isCodeGenOnly = 1 in
894 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
895 [(X86rep_stos i8)]>, REP;
896 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI], isCodeGenOnly = 1 in
897 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
898 [(X86rep_stos i16)]>, REP, OpSize;
899 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI], isCodeGenOnly = 1 in
900 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
901 [(X86rep_stos i32)]>, REP;
903 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
904 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
905 def STOSB : I<0xAA, RawFrm, (outs), (ins), "{stosb}", []>;
906 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
907 def STOSW : I<0xAB, RawFrm, (outs), (ins), "{stosw}", []>, OpSize;
908 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
909 def STOSD : I<0xAB, RawFrm, (outs), (ins), "{stosl|stosd}", []>;
911 def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scas{b}", []>;
912 def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scas{w}", []>, OpSize;
913 def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l}", []>;
915 def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
916 def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
917 def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
919 let Defs = [RAX, RDX] in
920 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
923 let Defs = [RAX, RCX, RDX] in
924 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
926 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
927 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
930 def SYSCALL : I<0x05, RawFrm,
931 (outs), (ins), "syscall", []>, TB;
932 def SYSRET : I<0x07, RawFrm,
933 (outs), (ins), "sysret", []>, TB;
934 def SYSENTER : I<0x34, RawFrm,
935 (outs), (ins), "sysenter", []>, TB;
936 def SYSEXIT : I<0x35, RawFrm,
937 (outs), (ins), "sysexit", []>, TB;
939 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
942 //===----------------------------------------------------------------------===//
943 // Input/Output Instructions...
945 let Defs = [AL], Uses = [DX] in
946 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
947 "in{b}\t{%dx, %al|%AL, %DX}", []>;
948 let Defs = [AX], Uses = [DX] in
949 def IN16rr : I<0xED, RawFrm, (outs), (ins),
950 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
951 let Defs = [EAX], Uses = [DX] in
952 def IN32rr : I<0xED, RawFrm, (outs), (ins),
953 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
956 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
957 "in{b}\t{$port, %al|%AL, $port}", []>;
959 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
960 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
962 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
963 "in{l}\t{$port, %eax|%EAX, $port}", []>;
965 let Uses = [DX, AL] in
966 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
967 "out{b}\t{%al, %dx|%DX, %AL}", []>;
968 let Uses = [DX, AX] in
969 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
970 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
971 let Uses = [DX, EAX] in
972 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
973 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
976 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
977 "out{b}\t{%al, $port|$port, %AL}", []>;
979 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
980 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
982 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
983 "out{l}\t{%eax, $port|$port, %EAX}", []>;
985 def IN8 : I<0x6C, RawFrm, (outs), (ins),
987 def IN16 : I<0x6D, RawFrm, (outs), (ins),
988 "ins{w}", []>, OpSize;
989 def IN32 : I<0x6D, RawFrm, (outs), (ins),
992 //===----------------------------------------------------------------------===//
993 // Move Instructions...
995 let neverHasSideEffects = 1 in {
996 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
997 "mov{b}\t{$src, $dst|$dst, $src}", []>;
998 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
999 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1000 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1001 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1003 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1004 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1005 "mov{b}\t{$src, $dst|$dst, $src}",
1006 [(set GR8:$dst, imm:$src)]>;
1007 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1008 "mov{w}\t{$src, $dst|$dst, $src}",
1009 [(set GR16:$dst, imm:$src)]>, OpSize;
1010 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1011 "mov{l}\t{$src, $dst|$dst, $src}",
1012 [(set GR32:$dst, imm:$src)]>;
1015 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1016 "mov{b}\t{$src, $dst|$dst, $src}",
1017 [(store (i8 imm:$src), addr:$dst)]>;
1018 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1019 "mov{w}\t{$src, $dst|$dst, $src}",
1020 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
1021 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1022 "mov{l}\t{$src, $dst|$dst, $src}",
1023 [(store (i32 imm:$src), addr:$dst)]>;
1025 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1026 /// 32-bit offset from the PC. These are only valid in x86-32 mode.
1027 def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src),
1028 "mov{b}\t{$src, %al|%al, $src}", []>,
1029 Requires<[In32BitMode]>;
1030 def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src),
1031 "mov{w}\t{$src, %ax|%ax, $src}", []>, OpSize,
1032 Requires<[In32BitMode]>;
1033 def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src),
1034 "mov{l}\t{$src, %eax|%eax, $src}", []>,
1035 Requires<[In32BitMode]>;
1036 def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins),
1037 "mov{b}\t{%al, $dst|$dst, %al}", []>,
1038 Requires<[In32BitMode]>;
1039 def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins),
1040 "mov{w}\t{%ax, $dst|$dst, %ax}", []>, OpSize,
1041 Requires<[In32BitMode]>;
1042 def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
1043 "mov{l}\t{%eax, $dst|$dst, %eax}", []>,
1044 Requires<[In32BitMode]>;
1046 // Moves to and from segment registers
1047 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
1048 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1049 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
1050 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1051 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
1052 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1053 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
1054 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1055 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
1056 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1057 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
1058 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1059 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
1060 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1061 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
1062 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1064 let isCodeGenOnly = 1 in {
1065 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1066 "mov{b}\t{$src, $dst|$dst, $src}", []>;
1067 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1068 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
1069 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1070 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1073 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1074 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1075 "mov{b}\t{$src, $dst|$dst, $src}",
1076 [(set GR8:$dst, (loadi8 addr:$src))]>;
1077 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1078 "mov{w}\t{$src, $dst|$dst, $src}",
1079 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
1080 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1081 "mov{l}\t{$src, $dst|$dst, $src}",
1082 [(set GR32:$dst, (loadi32 addr:$src))]>;
1085 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1086 "mov{b}\t{$src, $dst|$dst, $src}",
1087 [(store GR8:$src, addr:$dst)]>;
1088 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1089 "mov{w}\t{$src, $dst|$dst, $src}",
1090 [(store GR16:$src, addr:$dst)]>, OpSize;
1091 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1092 "mov{l}\t{$src, $dst|$dst, $src}",
1093 [(store GR32:$src, addr:$dst)]>;
1095 /// Versions of MOV32rr, MOV32rm, and MOV32mr for i32mem_TC and GR32_TC.
1096 let isCodeGenOnly = 1 in {
1097 let neverHasSideEffects = 1 in
1098 def MOV32rr_TC : I<0x89, MRMDestReg, (outs GR32_TC:$dst), (ins GR32_TC:$src),
1099 "mov{l}\t{$src, $dst|$dst, $src}", []>;
1102 canFoldAsLoad = 1, isReMaterializable = 1 in
1103 def MOV32rm_TC : I<0x8B, MRMSrcMem, (outs GR32_TC:$dst), (ins i32mem_TC:$src),
1104 "mov{l}\t{$src, $dst|$dst, $src}",
1108 def MOV32mr_TC : I<0x89, MRMDestMem, (outs), (ins i32mem_TC:$dst, GR32_TC:$src),
1109 "mov{l}\t{$src, $dst|$dst, $src}",
1113 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1114 // that they can be used for copying and storing h registers, which can't be
1115 // encoded when a REX prefix is present.
1116 let isCodeGenOnly = 1 in {
1117 let neverHasSideEffects = 1 in
1118 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1119 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1120 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1122 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1123 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1124 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1126 canFoldAsLoad = 1, isReMaterializable = 1 in
1127 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1128 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1129 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
1132 // Moves to and from debug registers
1133 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
1134 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1135 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
1136 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1138 // Moves to and from control registers
1139 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
1140 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1141 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
1142 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
1144 //===----------------------------------------------------------------------===//
1145 // Fixed-Register Multiplication and Division Instructions...
1148 // Extra precision multiplication
1150 // AL is really implied by AX, by the registers in Defs must match the
1151 // SDNode results (i8, i32).
1152 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1153 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
1154 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1155 // This probably ought to be moved to a def : Pat<> if the
1156 // syntax can be accepted.
1157 [(set AL, (mul AL, GR8:$src)),
1158 (implicit EFLAGS)]>; // AL,AH = AL*GR8
1160 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
1161 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
1163 []>, OpSize; // AX,DX = AX*GR16
1165 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
1166 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
1168 []>; // EAX,EDX = EAX*GR32
1170 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1171 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
1173 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
1174 // This probably ought to be moved to a def : Pat<> if the
1175 // syntax can be accepted.
1176 [(set AL, (mul AL, (loadi8 addr:$src))),
1177 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
1179 let mayLoad = 1, neverHasSideEffects = 1 in {
1180 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1181 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
1183 []>, OpSize; // AX,DX = AX*[mem16]
1185 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1186 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
1188 []>; // EAX,EDX = EAX*[mem32]
1191 let neverHasSideEffects = 1 in {
1192 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1193 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
1195 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1196 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
1197 OpSize; // AX,DX = AX*GR16
1198 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1199 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
1200 // EAX,EDX = EAX*GR32
1201 let mayLoad = 1 in {
1202 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
1203 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
1204 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
1205 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
1206 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
1207 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
1208 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
1209 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
1210 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
1212 } // neverHasSideEffects
1214 // unsigned division/remainder
1215 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1216 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1217 "div{b}\t$src", []>;
1218 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1219 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1220 "div{w}\t$src", []>, OpSize;
1221 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1222 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1223 "div{l}\t$src", []>;
1224 let mayLoad = 1 in {
1225 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1226 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1227 "div{b}\t$src", []>;
1228 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1229 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1230 "div{w}\t$src", []>, OpSize;
1231 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1232 // EDX:EAX/[mem32] = EAX,EDX
1233 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
1234 "div{l}\t$src", []>;
1237 // Signed division/remainder.
1238 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1239 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
1240 "idiv{b}\t$src", []>;
1241 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1242 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
1243 "idiv{w}\t$src", []>, OpSize;
1244 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1245 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
1246 "idiv{l}\t$src", []>;
1247 let mayLoad = 1, mayLoad = 1 in {
1248 let Defs = [AL,EFLAGS,AX], Uses = [AX] in
1249 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
1250 "idiv{b}\t$src", []>;
1251 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
1252 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
1253 "idiv{w}\t$src", []>, OpSize;
1254 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
1255 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
1256 // EDX:EAX/[mem32] = EAX,EDX
1257 "idiv{l}\t$src", []>;
1260 //===----------------------------------------------------------------------===//
1261 // Two address Instructions.
1263 let Constraints = "$src1 = $dst" in {
1265 // Conditional moves
1266 let Uses = [EFLAGS] in {
1268 let Predicates = [HasCMov] in {
1269 let isCommutable = 1 in {
1270 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
1271 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1272 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1273 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1274 X86_COND_B, EFLAGS))]>,
1276 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
1277 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1278 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1279 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1280 X86_COND_B, EFLAGS))]>,
1282 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
1283 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1284 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1285 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1286 X86_COND_AE, EFLAGS))]>,
1288 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
1289 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1290 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1291 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1292 X86_COND_AE, EFLAGS))]>,
1294 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
1295 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1296 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1297 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1298 X86_COND_E, EFLAGS))]>,
1300 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
1301 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1302 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1303 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1304 X86_COND_E, EFLAGS))]>,
1306 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
1307 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1308 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1309 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1310 X86_COND_NE, EFLAGS))]>,
1312 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
1313 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1314 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1315 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1316 X86_COND_NE, EFLAGS))]>,
1318 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
1319 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1320 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1321 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1322 X86_COND_BE, EFLAGS))]>,
1324 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1325 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1326 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1327 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1328 X86_COND_BE, EFLAGS))]>,
1330 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1331 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1332 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1333 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1334 X86_COND_A, EFLAGS))]>,
1336 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1337 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1338 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1339 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1340 X86_COND_A, EFLAGS))]>,
1342 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1343 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1344 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1345 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1346 X86_COND_L, EFLAGS))]>,
1348 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1349 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1350 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1351 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1352 X86_COND_L, EFLAGS))]>,
1354 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1355 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1356 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1357 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1358 X86_COND_GE, EFLAGS))]>,
1360 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1361 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1362 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1363 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1364 X86_COND_GE, EFLAGS))]>,
1366 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1367 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1368 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1369 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1370 X86_COND_LE, EFLAGS))]>,
1372 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1373 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1374 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1375 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1376 X86_COND_LE, EFLAGS))]>,
1378 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1379 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1380 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1381 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1382 X86_COND_G, EFLAGS))]>,
1384 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1385 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1386 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1387 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1388 X86_COND_G, EFLAGS))]>,
1390 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1391 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1392 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1393 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1394 X86_COND_S, EFLAGS))]>,
1396 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1397 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1398 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1399 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1400 X86_COND_S, EFLAGS))]>,
1402 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1403 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1404 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1405 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1406 X86_COND_NS, EFLAGS))]>,
1408 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1409 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1410 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1411 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1412 X86_COND_NS, EFLAGS))]>,
1414 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1415 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1416 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1417 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1418 X86_COND_P, EFLAGS))]>,
1420 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1421 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1422 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1423 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1424 X86_COND_P, EFLAGS))]>,
1426 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1427 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1428 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1429 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1430 X86_COND_NP, EFLAGS))]>,
1432 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1433 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1434 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1435 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1436 X86_COND_NP, EFLAGS))]>,
1438 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1439 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1440 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1441 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1442 X86_COND_O, EFLAGS))]>,
1444 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1445 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1446 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1447 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1448 X86_COND_O, EFLAGS))]>,
1450 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1451 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1452 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1453 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1454 X86_COND_NO, EFLAGS))]>,
1456 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1457 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1458 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1459 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1460 X86_COND_NO, EFLAGS))]>,
1462 } // isCommutable = 1
1464 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1465 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1466 "cmovb{w}\t{$src2, $dst|$dst, $src2}",
1467 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1468 X86_COND_B, EFLAGS))]>,
1470 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1471 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1472 "cmovb{l}\t{$src2, $dst|$dst, $src2}",
1473 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1474 X86_COND_B, EFLAGS))]>,
1476 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1477 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1478 "cmovae{w}\t{$src2, $dst|$dst, $src2}",
1479 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1480 X86_COND_AE, EFLAGS))]>,
1482 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1483 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1484 "cmovae{l}\t{$src2, $dst|$dst, $src2}",
1485 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1486 X86_COND_AE, EFLAGS))]>,
1488 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1489 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1490 "cmove{w}\t{$src2, $dst|$dst, $src2}",
1491 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1492 X86_COND_E, EFLAGS))]>,
1494 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1495 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1496 "cmove{l}\t{$src2, $dst|$dst, $src2}",
1497 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1498 X86_COND_E, EFLAGS))]>,
1500 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1501 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1502 "cmovne{w}\t{$src2, $dst|$dst, $src2}",
1503 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1504 X86_COND_NE, EFLAGS))]>,
1506 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1507 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1508 "cmovne{l}\t{$src2, $dst|$dst, $src2}",
1509 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1510 X86_COND_NE, EFLAGS))]>,
1512 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1513 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1514 "cmovbe{w}\t{$src2, $dst|$dst, $src2}",
1515 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1516 X86_COND_BE, EFLAGS))]>,
1518 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1519 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1520 "cmovbe{l}\t{$src2, $dst|$dst, $src2}",
1521 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1522 X86_COND_BE, EFLAGS))]>,
1524 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1525 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1526 "cmova{w}\t{$src2, $dst|$dst, $src2}",
1527 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1528 X86_COND_A, EFLAGS))]>,
1530 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1531 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1532 "cmova{l}\t{$src2, $dst|$dst, $src2}",
1533 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1534 X86_COND_A, EFLAGS))]>,
1536 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1537 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1538 "cmovl{w}\t{$src2, $dst|$dst, $src2}",
1539 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1540 X86_COND_L, EFLAGS))]>,
1542 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1543 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1544 "cmovl{l}\t{$src2, $dst|$dst, $src2}",
1545 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1546 X86_COND_L, EFLAGS))]>,
1548 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1549 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1550 "cmovge{w}\t{$src2, $dst|$dst, $src2}",
1551 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1552 X86_COND_GE, EFLAGS))]>,
1554 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1555 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1556 "cmovge{l}\t{$src2, $dst|$dst, $src2}",
1557 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1558 X86_COND_GE, EFLAGS))]>,
1560 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1561 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1562 "cmovle{w}\t{$src2, $dst|$dst, $src2}",
1563 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1564 X86_COND_LE, EFLAGS))]>,
1566 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1567 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1568 "cmovle{l}\t{$src2, $dst|$dst, $src2}",
1569 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1570 X86_COND_LE, EFLAGS))]>,
1572 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1573 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1574 "cmovg{w}\t{$src2, $dst|$dst, $src2}",
1575 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1576 X86_COND_G, EFLAGS))]>,
1578 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1579 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1580 "cmovg{l}\t{$src2, $dst|$dst, $src2}",
1581 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1582 X86_COND_G, EFLAGS))]>,
1584 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1585 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1586 "cmovs{w}\t{$src2, $dst|$dst, $src2}",
1587 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1588 X86_COND_S, EFLAGS))]>,
1590 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1591 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1592 "cmovs{l}\t{$src2, $dst|$dst, $src2}",
1593 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1594 X86_COND_S, EFLAGS))]>,
1596 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1597 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1598 "cmovns{w}\t{$src2, $dst|$dst, $src2}",
1599 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1600 X86_COND_NS, EFLAGS))]>,
1602 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1603 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1604 "cmovns{l}\t{$src2, $dst|$dst, $src2}",
1605 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1606 X86_COND_NS, EFLAGS))]>,
1608 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1609 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1610 "cmovp{w}\t{$src2, $dst|$dst, $src2}",
1611 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1612 X86_COND_P, EFLAGS))]>,
1614 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1615 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1616 "cmovp{l}\t{$src2, $dst|$dst, $src2}",
1617 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1618 X86_COND_P, EFLAGS))]>,
1620 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1621 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1622 "cmovnp{w}\t{$src2, $dst|$dst, $src2}",
1623 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1624 X86_COND_NP, EFLAGS))]>,
1626 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1627 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1628 "cmovnp{l}\t{$src2, $dst|$dst, $src2}",
1629 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1630 X86_COND_NP, EFLAGS))]>,
1632 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1633 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1634 "cmovo{w}\t{$src2, $dst|$dst, $src2}",
1635 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1636 X86_COND_O, EFLAGS))]>,
1638 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1639 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1640 "cmovo{l}\t{$src2, $dst|$dst, $src2}",
1641 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1642 X86_COND_O, EFLAGS))]>,
1644 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1645 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1646 "cmovno{w}\t{$src2, $dst|$dst, $src2}",
1647 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1648 X86_COND_NO, EFLAGS))]>,
1650 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1651 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1652 "cmovno{l}\t{$src2, $dst|$dst, $src2}",
1653 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1654 X86_COND_NO, EFLAGS))]>,
1656 } // Predicates = [HasCMov]
1658 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
1659 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
1660 // however that requires promoting the operands, and can induce additional
1661 // i8 register pressure. Note that CMOV_GR8 is conservatively considered to
1662 // clobber EFLAGS, because if one of the operands is zero, the expansion
1663 // could involve an xor.
1664 let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
1665 def CMOV_GR8 : I<0, Pseudo,
1666 (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
1667 "#CMOV_GR8 PSEUDO!",
1668 [(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
1669 imm:$cond, EFLAGS))]>;
1671 let Predicates = [NoCMov] in {
1672 def CMOV_GR32 : I<0, Pseudo,
1673 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
1674 "#CMOV_GR32* PSEUDO!",
1676 (X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
1677 def CMOV_GR16 : I<0, Pseudo,
1678 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
1679 "#CMOV_GR16* PSEUDO!",
1681 (X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
1682 def CMOV_RFP32 : I<0, Pseudo,
1684 (ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
1685 "#CMOV_RFP32 PSEUDO!",
1687 (X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
1689 def CMOV_RFP64 : I<0, Pseudo,
1691 (ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
1692 "#CMOV_RFP64 PSEUDO!",
1694 (X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
1696 def CMOV_RFP80 : I<0, Pseudo,
1698 (ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
1699 "#CMOV_RFP80 PSEUDO!",
1701 (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
1703 } // Predicates = [NoCMov]
1704 } // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
1705 } // Uses = [EFLAGS]
1708 // unary instructions
1709 let CodeSize = 2 in {
1710 let Defs = [EFLAGS] in {
1711 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
1713 [(set GR8:$dst, (ineg GR8:$src1)),
1714 (implicit EFLAGS)]>;
1715 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
1717 [(set GR16:$dst, (ineg GR16:$src1)),
1718 (implicit EFLAGS)]>, OpSize;
1719 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
1721 [(set GR32:$dst, (ineg GR32:$src1)),
1722 (implicit EFLAGS)]>;
1724 let Constraints = "" in {
1725 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
1727 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1728 (implicit EFLAGS)]>;
1729 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
1731 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1732 (implicit EFLAGS)]>, OpSize;
1733 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
1735 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1736 (implicit EFLAGS)]>;
1737 } // Constraints = ""
1738 } // Defs = [EFLAGS]
1740 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1741 let AddedComplexity = 15 in {
1742 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
1744 [(set GR8:$dst, (not GR8:$src1))]>;
1745 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
1747 [(set GR16:$dst, (not GR16:$src1))]>, OpSize;
1748 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
1750 [(set GR32:$dst, (not GR32:$src1))]>;
1752 let Constraints = "" in {
1753 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
1755 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1756 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
1758 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1759 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
1761 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1762 } // Constraints = ""
1765 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1766 let Defs = [EFLAGS] in {
1768 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1770 [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
1772 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1773 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1775 [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))]>,
1776 OpSize, Requires<[In32BitMode]>;
1777 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1779 [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))]>,
1780 Requires<[In32BitMode]>;
1782 let Constraints = "", CodeSize = 2 in {
1783 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1784 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1785 (implicit EFLAGS)]>;
1786 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1787 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1788 (implicit EFLAGS)]>,
1789 OpSize, Requires<[In32BitMode]>;
1790 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1791 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1792 (implicit EFLAGS)]>,
1793 Requires<[In32BitMode]>;
1794 } // Constraints = "", CodeSize = 2
1797 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
1799 [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))]>;
1800 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1801 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
1803 [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))]>,
1804 OpSize, Requires<[In32BitMode]>;
1805 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
1807 [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))]>,
1808 Requires<[In32BitMode]>;
1811 let Constraints = "", CodeSize = 2 in {
1812 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1813 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1814 (implicit EFLAGS)]>;
1815 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1816 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1817 (implicit EFLAGS)]>,
1818 OpSize, Requires<[In32BitMode]>;
1819 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1820 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1821 (implicit EFLAGS)]>,
1822 Requires<[In32BitMode]>;
1823 } // Constraints = "", CodeSize = 2
1824 } // Defs = [EFLAGS]
1826 // Logical operators...
1827 let Defs = [EFLAGS] in {
1828 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1829 def AND8rr : I<0x20, MRMDestReg,
1830 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1831 "and{b}\t{$src2, $dst|$dst, $src2}",
1832 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1, GR8:$src2))]>;
1833 def AND16rr : I<0x21, MRMDestReg,
1834 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1835 "and{w}\t{$src2, $dst|$dst, $src2}",
1836 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1837 GR16:$src2))]>, OpSize;
1838 def AND32rr : I<0x21, MRMDestReg,
1839 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1840 "and{l}\t{$src2, $dst|$dst, $src2}",
1841 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1845 // AND instructions with the destination register in REG and the source register
1846 // in R/M. Included for the disassembler.
1847 let isCodeGenOnly = 1 in {
1848 def AND8rr_REV : I<0x22, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1849 "and{b}\t{$src2, $dst|$dst, $src2}", []>;
1850 def AND16rr_REV : I<0x23, MRMSrcReg, (outs GR16:$dst),
1851 (ins GR16:$src1, GR16:$src2),
1852 "and{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1853 def AND32rr_REV : I<0x23, MRMSrcReg, (outs GR32:$dst),
1854 (ins GR32:$src1, GR32:$src2),
1855 "and{l}\t{$src2, $dst|$dst, $src2}", []>;
1858 def AND8rm : I<0x22, MRMSrcMem,
1859 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1860 "and{b}\t{$src2, $dst|$dst, $src2}",
1861 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1862 (loadi8 addr:$src2)))]>;
1863 def AND16rm : I<0x23, MRMSrcMem,
1864 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1865 "and{w}\t{$src2, $dst|$dst, $src2}",
1866 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1867 (loadi16 addr:$src2)))]>,
1869 def AND32rm : I<0x23, MRMSrcMem,
1870 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1871 "and{l}\t{$src2, $dst|$dst, $src2}",
1872 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1873 (loadi32 addr:$src2)))]>;
1875 def AND8ri : Ii8<0x80, MRM4r,
1876 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1877 "and{b}\t{$src2, $dst|$dst, $src2}",
1878 [(set GR8:$dst, EFLAGS, (X86and_flag GR8:$src1,
1880 def AND16ri : Ii16<0x81, MRM4r,
1881 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1882 "and{w}\t{$src2, $dst|$dst, $src2}",
1883 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1884 imm:$src2))]>, OpSize;
1885 def AND32ri : Ii32<0x81, MRM4r,
1886 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1887 "and{l}\t{$src2, $dst|$dst, $src2}",
1888 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1890 def AND16ri8 : Ii8<0x83, MRM4r,
1891 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1892 "and{w}\t{$src2, $dst|$dst, $src2}",
1893 [(set GR16:$dst, EFLAGS, (X86and_flag GR16:$src1,
1894 i16immSExt8:$src2))]>,
1896 def AND32ri8 : Ii8<0x83, MRM4r,
1897 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1898 "and{l}\t{$src2, $dst|$dst, $src2}",
1899 [(set GR32:$dst, EFLAGS, (X86and_flag GR32:$src1,
1900 i32immSExt8:$src2))]>;
1902 let Constraints = "" in {
1903 def AND8mr : I<0x20, MRMDestMem,
1904 (outs), (ins i8mem :$dst, GR8 :$src),
1905 "and{b}\t{$src, $dst|$dst, $src}",
1906 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1907 (implicit EFLAGS)]>;
1908 def AND16mr : I<0x21, MRMDestMem,
1909 (outs), (ins i16mem:$dst, GR16:$src),
1910 "and{w}\t{$src, $dst|$dst, $src}",
1911 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1912 (implicit EFLAGS)]>,
1914 def AND32mr : I<0x21, MRMDestMem,
1915 (outs), (ins i32mem:$dst, GR32:$src),
1916 "and{l}\t{$src, $dst|$dst, $src}",
1917 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1918 (implicit EFLAGS)]>;
1919 def AND8mi : Ii8<0x80, MRM4m,
1920 (outs), (ins i8mem :$dst, i8imm :$src),
1921 "and{b}\t{$src, $dst|$dst, $src}",
1922 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1923 (implicit EFLAGS)]>;
1924 def AND16mi : Ii16<0x81, MRM4m,
1925 (outs), (ins i16mem:$dst, i16imm:$src),
1926 "and{w}\t{$src, $dst|$dst, $src}",
1927 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1928 (implicit EFLAGS)]>,
1930 def AND32mi : Ii32<0x81, MRM4m,
1931 (outs), (ins i32mem:$dst, i32imm:$src),
1932 "and{l}\t{$src, $dst|$dst, $src}",
1933 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1934 (implicit EFLAGS)]>;
1935 def AND16mi8 : Ii8<0x83, MRM4m,
1936 (outs), (ins i16mem:$dst, i16i8imm :$src),
1937 "and{w}\t{$src, $dst|$dst, $src}",
1938 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1939 (implicit EFLAGS)]>,
1941 def AND32mi8 : Ii8<0x83, MRM4m,
1942 (outs), (ins i32mem:$dst, i32i8imm :$src),
1943 "and{l}\t{$src, $dst|$dst, $src}",
1944 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1945 (implicit EFLAGS)]>;
1947 def AND8i8 : Ii8<0x24, RawFrm, (outs), (ins i8imm:$src),
1948 "and{b}\t{$src, %al|%al, $src}", []>;
1949 def AND16i16 : Ii16<0x25, RawFrm, (outs), (ins i16imm:$src),
1950 "and{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
1951 def AND32i32 : Ii32<0x25, RawFrm, (outs), (ins i32imm:$src),
1952 "and{l}\t{$src, %eax|%eax, $src}", []>;
1954 } // Constraints = ""
1957 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1958 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst),
1959 (ins GR8 :$src1, GR8 :$src2),
1960 "or{b}\t{$src2, $dst|$dst, $src2}",
1961 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1, GR8:$src2))]>;
1962 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst),
1963 (ins GR16:$src1, GR16:$src2),
1964 "or{w}\t{$src2, $dst|$dst, $src2}",
1965 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,GR16:$src2))]>,
1967 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst),
1968 (ins GR32:$src1, GR32:$src2),
1969 "or{l}\t{$src2, $dst|$dst, $src2}",
1970 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,GR32:$src2))]>;
1973 // OR instructions with the destination register in REG and the source register
1974 // in R/M. Included for the disassembler.
1975 let isCodeGenOnly = 1 in {
1976 def OR8rr_REV : I<0x0A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
1977 "or{b}\t{$src2, $dst|$dst, $src2}", []>;
1978 def OR16rr_REV : I<0x0B, MRMSrcReg, (outs GR16:$dst),
1979 (ins GR16:$src1, GR16:$src2),
1980 "or{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
1981 def OR32rr_REV : I<0x0B, MRMSrcReg, (outs GR32:$dst),
1982 (ins GR32:$src1, GR32:$src2),
1983 "or{l}\t{$src2, $dst|$dst, $src2}", []>;
1986 def OR8rm : I<0x0A, MRMSrcMem, (outs GR8 :$dst),
1987 (ins GR8 :$src1, i8mem :$src2),
1988 "or{b}\t{$src2, $dst|$dst, $src2}",
1989 [(set GR8:$dst, EFLAGS, (X86or_flag GR8:$src1,
1990 (load addr:$src2)))]>;
1991 def OR16rm : I<0x0B, MRMSrcMem, (outs GR16:$dst),
1992 (ins GR16:$src1, i16mem:$src2),
1993 "or{w}\t{$src2, $dst|$dst, $src2}",
1994 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
1995 (load addr:$src2)))]>,
1997 def OR32rm : I<0x0B, MRMSrcMem, (outs GR32:$dst),
1998 (ins GR32:$src1, i32mem:$src2),
1999 "or{l}\t{$src2, $dst|$dst, $src2}",
2000 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2001 (load addr:$src2)))]>;
2003 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst),
2004 (ins GR8 :$src1, i8imm:$src2),
2005 "or{b}\t{$src2, $dst|$dst, $src2}",
2006 [(set GR8:$dst,EFLAGS, (X86or_flag GR8:$src1, imm:$src2))]>;
2007 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst),
2008 (ins GR16:$src1, i16imm:$src2),
2009 "or{w}\t{$src2, $dst|$dst, $src2}",
2010 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2011 imm:$src2))]>, OpSize;
2012 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst),
2013 (ins GR32:$src1, i32imm:$src2),
2014 "or{l}\t{$src2, $dst|$dst, $src2}",
2015 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2018 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst),
2019 (ins GR16:$src1, i16i8imm:$src2),
2020 "or{w}\t{$src2, $dst|$dst, $src2}",
2021 [(set GR16:$dst, EFLAGS, (X86or_flag GR16:$src1,
2022 i16immSExt8:$src2))]>, OpSize;
2023 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst),
2024 (ins GR32:$src1, i32i8imm:$src2),
2025 "or{l}\t{$src2, $dst|$dst, $src2}",
2026 [(set GR32:$dst, EFLAGS, (X86or_flag GR32:$src1,
2027 i32immSExt8:$src2))]>;
2028 let Constraints = "" in {
2029 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
2030 "or{b}\t{$src, $dst|$dst, $src}",
2031 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
2032 (implicit EFLAGS)]>;
2033 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
2034 "or{w}\t{$src, $dst|$dst, $src}",
2035 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
2036 (implicit EFLAGS)]>, OpSize;
2037 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2038 "or{l}\t{$src, $dst|$dst, $src}",
2039 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
2040 (implicit EFLAGS)]>;
2041 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2042 "or{b}\t{$src, $dst|$dst, $src}",
2043 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
2044 (implicit EFLAGS)]>;
2045 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
2046 "or{w}\t{$src, $dst|$dst, $src}",
2047 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
2048 (implicit EFLAGS)]>,
2050 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
2051 "or{l}\t{$src, $dst|$dst, $src}",
2052 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
2053 (implicit EFLAGS)]>;
2054 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
2055 "or{w}\t{$src, $dst|$dst, $src}",
2056 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
2057 (implicit EFLAGS)]>,
2059 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
2060 "or{l}\t{$src, $dst|$dst, $src}",
2061 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
2062 (implicit EFLAGS)]>;
2064 def OR8i8 : Ii8 <0x0C, RawFrm, (outs), (ins i8imm:$src),
2065 "or{b}\t{$src, %al|%al, $src}", []>;
2066 def OR16i16 : Ii16 <0x0D, RawFrm, (outs), (ins i16imm:$src),
2067 "or{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2068 def OR32i32 : Ii32 <0x0D, RawFrm, (outs), (ins i32imm:$src),
2069 "or{l}\t{$src, %eax|%eax, $src}", []>;
2070 } // Constraints = ""
2073 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
2074 def XOR8rr : I<0x30, MRMDestReg,
2075 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
2076 "xor{b}\t{$src2, $dst|$dst, $src2}",
2077 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2079 def XOR16rr : I<0x31, MRMDestReg,
2080 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2081 "xor{w}\t{$src2, $dst|$dst, $src2}",
2082 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2083 GR16:$src2))]>, OpSize;
2084 def XOR32rr : I<0x31, MRMDestReg,
2085 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2086 "xor{l}\t{$src2, $dst|$dst, $src2}",
2087 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2089 } // isCommutable = 1
2091 // XOR instructions with the destination register in REG and the source register
2092 // in R/M. Included for the disassembler.
2093 let isCodeGenOnly = 1 in {
2094 def XOR8rr_REV : I<0x32, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2095 "xor{b}\t{$src2, $dst|$dst, $src2}", []>;
2096 def XOR16rr_REV : I<0x33, MRMSrcReg, (outs GR16:$dst),
2097 (ins GR16:$src1, GR16:$src2),
2098 "xor{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2099 def XOR32rr_REV : I<0x33, MRMSrcReg, (outs GR32:$dst),
2100 (ins GR32:$src1, GR32:$src2),
2101 "xor{l}\t{$src2, $dst|$dst, $src2}", []>;
2104 def XOR8rm : I<0x32, MRMSrcMem,
2105 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
2106 "xor{b}\t{$src2, $dst|$dst, $src2}",
2107 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1,
2108 (load addr:$src2)))]>;
2109 def XOR16rm : I<0x33, MRMSrcMem,
2110 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
2111 "xor{w}\t{$src2, $dst|$dst, $src2}",
2112 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2113 (load addr:$src2)))]>,
2115 def XOR32rm : I<0x33, MRMSrcMem,
2116 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2117 "xor{l}\t{$src2, $dst|$dst, $src2}",
2118 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2119 (load addr:$src2)))]>;
2121 def XOR8ri : Ii8<0x80, MRM6r,
2122 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2123 "xor{b}\t{$src2, $dst|$dst, $src2}",
2124 [(set GR8:$dst, EFLAGS, (X86xor_flag GR8:$src1, imm:$src2))]>;
2125 def XOR16ri : Ii16<0x81, MRM6r,
2126 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2127 "xor{w}\t{$src2, $dst|$dst, $src2}",
2128 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2129 imm:$src2))]>, OpSize;
2130 def XOR32ri : Ii32<0x81, MRM6r,
2131 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2132 "xor{l}\t{$src2, $dst|$dst, $src2}",
2133 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2135 def XOR16ri8 : Ii8<0x83, MRM6r,
2136 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2137 "xor{w}\t{$src2, $dst|$dst, $src2}",
2138 [(set GR16:$dst, EFLAGS, (X86xor_flag GR16:$src1,
2139 i16immSExt8:$src2))]>,
2141 def XOR32ri8 : Ii8<0x83, MRM6r,
2142 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2143 "xor{l}\t{$src2, $dst|$dst, $src2}",
2144 [(set GR32:$dst, EFLAGS, (X86xor_flag GR32:$src1,
2145 i32immSExt8:$src2))]>;
2147 let Constraints = "" in {
2148 def XOR8mr : I<0x30, MRMDestMem,
2149 (outs), (ins i8mem :$dst, GR8 :$src),
2150 "xor{b}\t{$src, $dst|$dst, $src}",
2151 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
2152 (implicit EFLAGS)]>;
2153 def XOR16mr : I<0x31, MRMDestMem,
2154 (outs), (ins i16mem:$dst, GR16:$src),
2155 "xor{w}\t{$src, $dst|$dst, $src}",
2156 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
2157 (implicit EFLAGS)]>,
2159 def XOR32mr : I<0x31, MRMDestMem,
2160 (outs), (ins i32mem:$dst, GR32:$src),
2161 "xor{l}\t{$src, $dst|$dst, $src}",
2162 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
2163 (implicit EFLAGS)]>;
2164 def XOR8mi : Ii8<0x80, MRM6m,
2165 (outs), (ins i8mem :$dst, i8imm :$src),
2166 "xor{b}\t{$src, $dst|$dst, $src}",
2167 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
2168 (implicit EFLAGS)]>;
2169 def XOR16mi : Ii16<0x81, MRM6m,
2170 (outs), (ins i16mem:$dst, i16imm:$src),
2171 "xor{w}\t{$src, $dst|$dst, $src}",
2172 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
2173 (implicit EFLAGS)]>,
2175 def XOR32mi : Ii32<0x81, MRM6m,
2176 (outs), (ins i32mem:$dst, i32imm:$src),
2177 "xor{l}\t{$src, $dst|$dst, $src}",
2178 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
2179 (implicit EFLAGS)]>;
2180 def XOR16mi8 : Ii8<0x83, MRM6m,
2181 (outs), (ins i16mem:$dst, i16i8imm :$src),
2182 "xor{w}\t{$src, $dst|$dst, $src}",
2183 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
2184 (implicit EFLAGS)]>,
2186 def XOR32mi8 : Ii8<0x83, MRM6m,
2187 (outs), (ins i32mem:$dst, i32i8imm :$src),
2188 "xor{l}\t{$src, $dst|$dst, $src}",
2189 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
2190 (implicit EFLAGS)]>;
2192 def XOR8i8 : Ii8 <0x34, RawFrm, (outs), (ins i8imm:$src),
2193 "xor{b}\t{$src, %al|%al, $src}", []>;
2194 def XOR16i16 : Ii16<0x35, RawFrm, (outs), (ins i16imm:$src),
2195 "xor{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2196 def XOR32i32 : Ii32<0x35, RawFrm, (outs), (ins i32imm:$src),
2197 "xor{l}\t{$src, %eax|%eax, $src}", []>;
2198 } // Constraints = ""
2199 } // Defs = [EFLAGS]
2201 // Shift instructions
2202 let Defs = [EFLAGS] in {
2203 let Uses = [CL] in {
2204 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
2205 "shl{b}\t{%cl, $dst|$dst, CL}",
2206 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
2207 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2208 "shl{w}\t{%cl, $dst|$dst, CL}",
2209 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
2210 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2211 "shl{l}\t{%cl, $dst|$dst, CL}",
2212 [(set GR32:$dst, (shl GR32:$src1, CL))]>;
2215 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2216 "shl{b}\t{$src2, $dst|$dst, $src2}",
2217 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
2219 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2220 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2221 "shl{w}\t{$src2, $dst|$dst, $src2}",
2222 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2223 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2224 "shl{l}\t{$src2, $dst|$dst, $src2}",
2225 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
2227 // NOTE: We don't include patterns for shifts of a register by one, because
2228 // 'add reg,reg' is cheaper.
2230 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
2231 "shl{b}\t$dst", []>;
2232 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
2233 "shl{w}\t$dst", []>, OpSize;
2234 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
2235 "shl{l}\t$dst", []>;
2237 } // isConvertibleToThreeAddress = 1
2239 let Constraints = "" in {
2240 let Uses = [CL] in {
2241 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
2242 "shl{b}\t{%cl, $dst|$dst, CL}",
2243 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
2244 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
2245 "shl{w}\t{%cl, $dst|$dst, CL}",
2246 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2247 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
2248 "shl{l}\t{%cl, $dst|$dst, CL}",
2249 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
2251 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
2252 "shl{b}\t{$src, $dst|$dst, $src}",
2253 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2254 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
2255 "shl{w}\t{$src, $dst|$dst, $src}",
2256 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2258 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
2259 "shl{l}\t{$src, $dst|$dst, $src}",
2260 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2263 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
2265 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2266 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
2268 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2270 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
2272 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2273 } // Constraints = ""
2275 let Uses = [CL] in {
2276 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
2277 "shr{b}\t{%cl, $dst|$dst, CL}",
2278 [(set GR8:$dst, (srl GR8:$src1, CL))]>;
2279 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2280 "shr{w}\t{%cl, $dst|$dst, CL}",
2281 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
2282 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2283 "shr{l}\t{%cl, $dst|$dst, CL}",
2284 [(set GR32:$dst, (srl GR32:$src1, CL))]>;
2287 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2288 "shr{b}\t{$src2, $dst|$dst, $src2}",
2289 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
2290 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2291 "shr{w}\t{$src2, $dst|$dst, $src2}",
2292 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2293 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2294 "shr{l}\t{$src2, $dst|$dst, $src2}",
2295 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
2298 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
2300 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
2301 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
2303 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
2304 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
2306 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
2308 let Constraints = "" in {
2309 let Uses = [CL] in {
2310 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
2311 "shr{b}\t{%cl, $dst|$dst, CL}",
2312 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
2313 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
2314 "shr{w}\t{%cl, $dst|$dst, CL}",
2315 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
2317 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
2318 "shr{l}\t{%cl, $dst|$dst, CL}",
2319 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
2321 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
2322 "shr{b}\t{$src, $dst|$dst, $src}",
2323 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2324 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
2325 "shr{w}\t{$src, $dst|$dst, $src}",
2326 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2328 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
2329 "shr{l}\t{$src, $dst|$dst, $src}",
2330 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2333 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
2335 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2336 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
2338 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
2339 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
2341 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2342 } // Constraints = ""
2344 let Uses = [CL] in {
2345 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2346 "sar{b}\t{%cl, $dst|$dst, CL}",
2347 [(set GR8:$dst, (sra GR8:$src1, CL))]>;
2348 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2349 "sar{w}\t{%cl, $dst|$dst, CL}",
2350 [(set GR16:$dst, (sra GR16:$src1, CL))]>, OpSize;
2351 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2352 "sar{l}\t{%cl, $dst|$dst, CL}",
2353 [(set GR32:$dst, (sra GR32:$src1, CL))]>;
2356 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2357 "sar{b}\t{$src2, $dst|$dst, $src2}",
2358 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
2359 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2360 "sar{w}\t{$src2, $dst|$dst, $src2}",
2361 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
2363 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2364 "sar{l}\t{$src2, $dst|$dst, $src2}",
2365 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
2368 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
2370 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
2371 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
2373 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
2374 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
2376 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
2378 let Constraints = "" in {
2379 let Uses = [CL] in {
2380 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
2381 "sar{b}\t{%cl, $dst|$dst, CL}",
2382 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
2383 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
2384 "sar{w}\t{%cl, $dst|$dst, CL}",
2385 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2386 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
2387 "sar{l}\t{%cl, $dst|$dst, CL}",
2388 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
2390 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
2391 "sar{b}\t{$src, $dst|$dst, $src}",
2392 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2393 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
2394 "sar{w}\t{$src, $dst|$dst, $src}",
2395 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2397 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
2398 "sar{l}\t{$src, $dst|$dst, $src}",
2399 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2402 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
2404 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2405 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
2407 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2409 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
2411 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2412 } // Constraints = ""
2414 // Rotate instructions
2416 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2417 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2418 let Uses = [CL] in {
2419 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
2420 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2422 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2423 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2425 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2426 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2427 let Uses = [CL] in {
2428 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
2429 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2431 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2432 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2434 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2435 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2436 let Uses = [CL] in {
2437 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
2438 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2440 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2441 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2443 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2444 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2445 let Uses = [CL] in {
2446 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
2447 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2449 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
2450 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2452 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2453 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2454 let Uses = [CL] in {
2455 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
2456 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2458 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
2459 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2461 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2462 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2463 let Uses = [CL] in {
2464 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
2465 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2467 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
2468 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2470 let Constraints = "" in {
2471 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
2472 "rcl{b}\t{1, $dst|$dst, 1}", []>;
2473 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2474 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2475 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
2476 "rcl{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2477 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2478 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2479 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
2480 "rcl{l}\t{1, $dst|$dst, 1}", []>;
2481 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2482 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2483 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
2484 "rcr{b}\t{1, $dst|$dst, 1}", []>;
2485 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
2486 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", []>;
2487 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
2488 "rcr{w}\t{1, $dst|$dst, 1}", []>, OpSize;
2489 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
2490 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
2491 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
2492 "rcr{l}\t{1, $dst|$dst, 1}", []>;
2493 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
2494 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", []>;
2496 let Uses = [CL] in {
2497 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
2498 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
2499 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
2500 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2501 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
2502 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
2503 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
2504 "rcr{b}\t{%cl, $dst|$dst, CL}", []>;
2505 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
2506 "rcr{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
2507 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
2508 "rcr{l}\t{%cl, $dst|$dst, CL}", []>;
2510 } // Constraints = ""
2512 // FIXME: provide shorter instructions when imm8 == 1
2513 let Uses = [CL] in {
2514 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2515 "rol{b}\t{%cl, $dst|$dst, CL}",
2516 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
2517 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2518 "rol{w}\t{%cl, $dst|$dst, CL}",
2519 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize;
2520 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2521 "rol{l}\t{%cl, $dst|$dst, CL}",
2522 [(set GR32:$dst, (rotl GR32:$src1, CL))]>;
2525 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2526 "rol{b}\t{$src2, $dst|$dst, $src2}",
2527 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
2528 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2529 "rol{w}\t{$src2, $dst|$dst, $src2}",
2530 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
2532 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2533 "rol{l}\t{$src2, $dst|$dst, $src2}",
2534 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
2537 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
2539 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
2540 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
2542 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
2543 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
2545 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
2547 let Constraints = "" in {
2548 let Uses = [CL] in {
2549 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
2550 "rol{b}\t{%cl, $dst|$dst, CL}",
2551 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
2552 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
2553 "rol{w}\t{%cl, $dst|$dst, CL}",
2554 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2555 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
2556 "rol{l}\t{%cl, $dst|$dst, CL}",
2557 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
2559 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
2560 "rol{b}\t{$src, $dst|$dst, $src}",
2561 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2562 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
2563 "rol{w}\t{$src, $dst|$dst, $src}",
2564 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2566 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2567 "rol{l}\t{$src, $dst|$dst, $src}",
2568 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2571 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2573 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2574 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2576 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2578 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2580 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2581 } // Constraints = ""
2583 let Uses = [CL] in {
2584 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2585 "ror{b}\t{%cl, $dst|$dst, CL}",
2586 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
2587 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2588 "ror{w}\t{%cl, $dst|$dst, CL}",
2589 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize;
2590 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2591 "ror{l}\t{%cl, $dst|$dst, CL}",
2592 [(set GR32:$dst, (rotr GR32:$src1, CL))]>;
2595 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2596 "ror{b}\t{$src2, $dst|$dst, $src2}",
2597 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2598 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2599 "ror{w}\t{$src2, $dst|$dst, $src2}",
2600 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
2602 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2603 "ror{l}\t{$src2, $dst|$dst, $src2}",
2604 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2607 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2609 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2610 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2612 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2613 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2615 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2617 let Constraints = "" in {
2618 let Uses = [CL] in {
2619 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2620 "ror{b}\t{%cl, $dst|$dst, CL}",
2621 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2622 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2623 "ror{w}\t{%cl, $dst|$dst, CL}",
2624 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2625 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2626 "ror{l}\t{%cl, $dst|$dst, CL}",
2627 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2629 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2630 "ror{b}\t{$src, $dst|$dst, $src}",
2631 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2632 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2633 "ror{w}\t{$src, $dst|$dst, $src}",
2634 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2636 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2637 "ror{l}\t{$src, $dst|$dst, $src}",
2638 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2641 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2643 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2644 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2646 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2648 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2650 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2651 } // Constraints = ""
2654 // Double shift instructions (generalizations of rotate)
2655 let Uses = [CL] in {
2656 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
2657 (ins GR32:$src1, GR32:$src2),
2658 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2659 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2660 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
2661 (ins GR32:$src1, GR32:$src2),
2662 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2663 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2664 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
2665 (ins GR16:$src1, GR16:$src2),
2666 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2667 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2669 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
2670 (ins GR16:$src1, GR16:$src2),
2671 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2672 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2676 let isCommutable = 1 in { // These instructions commute to each other.
2677 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2679 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2680 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2681 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2684 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2686 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2687 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2688 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2691 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2693 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2694 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2695 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2698 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2700 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2701 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2702 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2707 let Constraints = "" in {
2708 let Uses = [CL] in {
2709 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2710 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2711 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2713 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2714 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2715 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2718 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2719 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2720 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2721 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2722 (i8 imm:$src3)), addr:$dst)]>,
2724 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2725 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2726 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2727 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2728 (i8 imm:$src3)), addr:$dst)]>,
2731 let Uses = [CL] in {
2732 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2733 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2734 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2735 addr:$dst)]>, TB, OpSize;
2736 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2737 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2738 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2739 addr:$dst)]>, TB, OpSize;
2741 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2742 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2743 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2744 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2745 (i8 imm:$src3)), addr:$dst)]>,
2747 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2748 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2749 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2750 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2751 (i8 imm:$src3)), addr:$dst)]>,
2753 } // Constraints = ""
2754 } // Defs = [EFLAGS]
2758 let Defs = [EFLAGS] in {
2759 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2760 // Register-Register Addition
2761 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2762 (ins GR8 :$src1, GR8 :$src2),
2763 "add{b}\t{$src2, $dst|$dst, $src2}",
2764 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1, GR8:$src2))]>;
2766 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2767 // Register-Register Addition
2768 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2769 (ins GR16:$src1, GR16:$src2),
2770 "add{w}\t{$src2, $dst|$dst, $src2}",
2771 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2772 GR16:$src2))]>, OpSize;
2773 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2774 (ins GR32:$src1, GR32:$src2),
2775 "add{l}\t{$src2, $dst|$dst, $src2}",
2776 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2778 } // end isConvertibleToThreeAddress
2779 } // end isCommutable
2781 // These are alternate spellings for use by the disassembler, we mark them as
2782 // code gen only to ensure they aren't matched by the assembler.
2783 let isCodeGenOnly = 1 in {
2784 def ADD8rr_alt: I<0x02, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2785 "add{b}\t{$src2, $dst|$dst, $src2}", []>;
2786 def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2),
2787 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2788 def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2),
2789 "add{l}\t{$src2, $dst|$dst, $src2}", []>;
2792 // Register-Memory Addition
2793 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2794 (ins GR8 :$src1, i8mem :$src2),
2795 "add{b}\t{$src2, $dst|$dst, $src2}",
2796 [(set GR8:$dst, EFLAGS, (X86add_flag GR8:$src1,
2797 (load addr:$src2)))]>;
2798 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2799 (ins GR16:$src1, i16mem:$src2),
2800 "add{w}\t{$src2, $dst|$dst, $src2}",
2801 [(set GR16:$dst, EFLAGS, (X86add_flag GR16:$src1,
2802 (load addr:$src2)))]>, OpSize;
2803 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2804 (ins GR32:$src1, i32mem:$src2),
2805 "add{l}\t{$src2, $dst|$dst, $src2}",
2806 [(set GR32:$dst, EFLAGS, (X86add_flag GR32:$src1,
2807 (load addr:$src2)))]>;
2809 // Register-Integer Addition
2810 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2811 "add{b}\t{$src2, $dst|$dst, $src2}",
2812 [(set GR8:$dst, EFLAGS,
2813 (X86add_flag GR8:$src1, imm:$src2))]>;
2815 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2816 // Register-Integer Addition
2817 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2818 (ins GR16:$src1, i16imm:$src2),
2819 "add{w}\t{$src2, $dst|$dst, $src2}",
2820 [(set GR16:$dst, EFLAGS,
2821 (X86add_flag GR16:$src1, imm:$src2))]>, OpSize;
2822 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2823 (ins GR32:$src1, i32imm:$src2),
2824 "add{l}\t{$src2, $dst|$dst, $src2}",
2825 [(set GR32:$dst, EFLAGS,
2826 (X86add_flag GR32:$src1, imm:$src2))]>;
2827 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2828 (ins GR16:$src1, i16i8imm:$src2),
2829 "add{w}\t{$src2, $dst|$dst, $src2}",
2830 [(set GR16:$dst, EFLAGS,
2831 (X86add_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
2832 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2833 (ins GR32:$src1, i32i8imm:$src2),
2834 "add{l}\t{$src2, $dst|$dst, $src2}",
2835 [(set GR32:$dst, EFLAGS,
2836 (X86add_flag GR32:$src1, i32immSExt8:$src2))]>;
2839 let Constraints = "" in {
2840 // Memory-Register Addition
2841 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2842 "add{b}\t{$src2, $dst|$dst, $src2}",
2843 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2844 (implicit EFLAGS)]>;
2845 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2846 "add{w}\t{$src2, $dst|$dst, $src2}",
2847 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2848 (implicit EFLAGS)]>, OpSize;
2849 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2850 "add{l}\t{$src2, $dst|$dst, $src2}",
2851 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2852 (implicit EFLAGS)]>;
2853 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2854 "add{b}\t{$src2, $dst|$dst, $src2}",
2855 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2856 (implicit EFLAGS)]>;
2857 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2858 "add{w}\t{$src2, $dst|$dst, $src2}",
2859 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2860 (implicit EFLAGS)]>, OpSize;
2861 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2862 "add{l}\t{$src2, $dst|$dst, $src2}",
2863 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2864 (implicit EFLAGS)]>;
2865 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2866 "add{w}\t{$src2, $dst|$dst, $src2}",
2867 [(store (add (load addr:$dst), i16immSExt8:$src2),
2869 (implicit EFLAGS)]>, OpSize;
2870 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2871 "add{l}\t{$src2, $dst|$dst, $src2}",
2872 [(store (add (load addr:$dst), i32immSExt8:$src2),
2874 (implicit EFLAGS)]>;
2877 def ADD8i8 : Ii8<0x04, RawFrm, (outs), (ins i8imm:$src),
2878 "add{b}\t{$src, %al|%al, $src}", []>;
2879 def ADD16i16 : Ii16<0x05, RawFrm, (outs), (ins i16imm:$src),
2880 "add{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2881 def ADD32i32 : Ii32<0x05, RawFrm, (outs), (ins i32imm:$src),
2882 "add{l}\t{$src, %eax|%eax, $src}", []>;
2883 } // Constraints = ""
2885 let Uses = [EFLAGS] in {
2886 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2887 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2888 "adc{b}\t{$src2, $dst|$dst, $src2}",
2889 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2890 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2891 (ins GR16:$src1, GR16:$src2),
2892 "adc{w}\t{$src2, $dst|$dst, $src2}",
2893 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2894 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2895 (ins GR32:$src1, GR32:$src2),
2896 "adc{l}\t{$src2, $dst|$dst, $src2}",
2897 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2900 let isCodeGenOnly = 1 in {
2901 def ADC8rr_REV : I<0x12, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2902 "adc{b}\t{$src2, $dst|$dst, $src2}", []>;
2903 def ADC16rr_REV : I<0x13, MRMSrcReg, (outs GR16:$dst),
2904 (ins GR16:$src1, GR16:$src2),
2905 "adc{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
2906 def ADC32rr_REV : I<0x13, MRMSrcReg, (outs GR32:$dst),
2907 (ins GR32:$src1, GR32:$src2),
2908 "adc{l}\t{$src2, $dst|$dst, $src2}", []>;
2911 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2912 (ins GR8:$src1, i8mem:$src2),
2913 "adc{b}\t{$src2, $dst|$dst, $src2}",
2914 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2915 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2916 (ins GR16:$src1, i16mem:$src2),
2917 "adc{w}\t{$src2, $dst|$dst, $src2}",
2918 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2920 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2921 (ins GR32:$src1, i32mem:$src2),
2922 "adc{l}\t{$src2, $dst|$dst, $src2}",
2923 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2924 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2925 "adc{b}\t{$src2, $dst|$dst, $src2}",
2926 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2927 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2928 (ins GR16:$src1, i16imm:$src2),
2929 "adc{w}\t{$src2, $dst|$dst, $src2}",
2930 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2931 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2932 (ins GR16:$src1, i16i8imm:$src2),
2933 "adc{w}\t{$src2, $dst|$dst, $src2}",
2934 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2936 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2937 (ins GR32:$src1, i32imm:$src2),
2938 "adc{l}\t{$src2, $dst|$dst, $src2}",
2939 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2940 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2941 (ins GR32:$src1, i32i8imm:$src2),
2942 "adc{l}\t{$src2, $dst|$dst, $src2}",
2943 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2945 let Constraints = "" in {
2946 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2947 "adc{b}\t{$src2, $dst|$dst, $src2}",
2948 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2949 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2950 "adc{w}\t{$src2, $dst|$dst, $src2}",
2951 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2953 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2954 "adc{l}\t{$src2, $dst|$dst, $src2}",
2955 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2956 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2957 "adc{b}\t{$src2, $dst|$dst, $src2}",
2958 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2959 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2960 "adc{w}\t{$src2, $dst|$dst, $src2}",
2961 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2963 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2964 "adc{w}\t{$src2, $dst|$dst, $src2}",
2965 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2967 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2968 "adc{l}\t{$src2, $dst|$dst, $src2}",
2969 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2970 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2971 "adc{l}\t{$src2, $dst|$dst, $src2}",
2972 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2974 def ADC8i8 : Ii8<0x14, RawFrm, (outs), (ins i8imm:$src),
2975 "adc{b}\t{$src, %al|%al, $src}", []>;
2976 def ADC16i16 : Ii16<0x15, RawFrm, (outs), (ins i16imm:$src),
2977 "adc{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
2978 def ADC32i32 : Ii32<0x15, RawFrm, (outs), (ins i32imm:$src),
2979 "adc{l}\t{$src, %eax|%eax, $src}", []>;
2980 } // Constraints = ""
2981 } // Uses = [EFLAGS]
2983 // Register-Register Subtraction
2984 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2985 "sub{b}\t{$src2, $dst|$dst, $src2}",
2986 [(set GR8:$dst, EFLAGS,
2987 (X86sub_flag GR8:$src1, GR8:$src2))]>;
2988 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2989 "sub{w}\t{$src2, $dst|$dst, $src2}",
2990 [(set GR16:$dst, EFLAGS,
2991 (X86sub_flag GR16:$src1, GR16:$src2))]>, OpSize;
2992 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2993 "sub{l}\t{$src2, $dst|$dst, $src2}",
2994 [(set GR32:$dst, EFLAGS,
2995 (X86sub_flag GR32:$src1, GR32:$src2))]>;
2997 let isCodeGenOnly = 1 in {
2998 def SUB8rr_REV : I<0x2A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2999 "sub{b}\t{$src2, $dst|$dst, $src2}", []>;
3000 def SUB16rr_REV : I<0x2B, MRMSrcReg, (outs GR16:$dst),
3001 (ins GR16:$src1, GR16:$src2),
3002 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3003 def SUB32rr_REV : I<0x2B, MRMSrcReg, (outs GR32:$dst),
3004 (ins GR32:$src1, GR32:$src2),
3005 "sub{l}\t{$src2, $dst|$dst, $src2}", []>;
3008 // Register-Memory Subtraction
3009 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
3010 (ins GR8 :$src1, i8mem :$src2),
3011 "sub{b}\t{$src2, $dst|$dst, $src2}",
3012 [(set GR8:$dst, EFLAGS,
3013 (X86sub_flag GR8:$src1, (load addr:$src2)))]>;
3014 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
3015 (ins GR16:$src1, i16mem:$src2),
3016 "sub{w}\t{$src2, $dst|$dst, $src2}",
3017 [(set GR16:$dst, EFLAGS,
3018 (X86sub_flag GR16:$src1, (load addr:$src2)))]>, OpSize;
3019 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
3020 (ins GR32:$src1, i32mem:$src2),
3021 "sub{l}\t{$src2, $dst|$dst, $src2}",
3022 [(set GR32:$dst, EFLAGS,
3023 (X86sub_flag GR32:$src1, (load addr:$src2)))]>;
3025 // Register-Integer Subtraction
3026 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
3027 (ins GR8:$src1, i8imm:$src2),
3028 "sub{b}\t{$src2, $dst|$dst, $src2}",
3029 [(set GR8:$dst, EFLAGS,
3030 (X86sub_flag GR8:$src1, imm:$src2))]>;
3031 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
3032 (ins GR16:$src1, i16imm:$src2),
3033 "sub{w}\t{$src2, $dst|$dst, $src2}",
3034 [(set GR16:$dst, EFLAGS,
3035 (X86sub_flag GR16:$src1, imm:$src2))]>, OpSize;
3036 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
3037 (ins GR32:$src1, i32imm:$src2),
3038 "sub{l}\t{$src2, $dst|$dst, $src2}",
3039 [(set GR32:$dst, EFLAGS,
3040 (X86sub_flag GR32:$src1, imm:$src2))]>;
3041 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
3042 (ins GR16:$src1, i16i8imm:$src2),
3043 "sub{w}\t{$src2, $dst|$dst, $src2}",
3044 [(set GR16:$dst, EFLAGS,
3045 (X86sub_flag GR16:$src1, i16immSExt8:$src2))]>, OpSize;
3046 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
3047 (ins GR32:$src1, i32i8imm:$src2),
3048 "sub{l}\t{$src2, $dst|$dst, $src2}",
3049 [(set GR32:$dst, EFLAGS,
3050 (X86sub_flag GR32:$src1, i32immSExt8:$src2))]>;
3052 let Constraints = "" in {
3053 // Memory-Register Subtraction
3054 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
3055 "sub{b}\t{$src2, $dst|$dst, $src2}",
3056 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
3057 (implicit EFLAGS)]>;
3058 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3059 "sub{w}\t{$src2, $dst|$dst, $src2}",
3060 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
3061 (implicit EFLAGS)]>, OpSize;
3062 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3063 "sub{l}\t{$src2, $dst|$dst, $src2}",
3064 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
3065 (implicit EFLAGS)]>;
3067 // Memory-Integer Subtraction
3068 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
3069 "sub{b}\t{$src2, $dst|$dst, $src2}",
3070 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
3071 (implicit EFLAGS)]>;
3072 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
3073 "sub{w}\t{$src2, $dst|$dst, $src2}",
3074 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
3075 (implicit EFLAGS)]>, OpSize;
3076 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
3077 "sub{l}\t{$src2, $dst|$dst, $src2}",
3078 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
3079 (implicit EFLAGS)]>;
3080 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3081 "sub{w}\t{$src2, $dst|$dst, $src2}",
3082 [(store (sub (load addr:$dst), i16immSExt8:$src2),
3084 (implicit EFLAGS)]>, OpSize;
3085 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3086 "sub{l}\t{$src2, $dst|$dst, $src2}",
3087 [(store (sub (load addr:$dst), i32immSExt8:$src2),
3089 (implicit EFLAGS)]>;
3091 def SUB8i8 : Ii8<0x2C, RawFrm, (outs), (ins i8imm:$src),
3092 "sub{b}\t{$src, %al|%al, $src}", []>;
3093 def SUB16i16 : Ii16<0x2D, RawFrm, (outs), (ins i16imm:$src),
3094 "sub{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3095 def SUB32i32 : Ii32<0x2D, RawFrm, (outs), (ins i32imm:$src),
3096 "sub{l}\t{$src, %eax|%eax, $src}", []>;
3097 } // Constraints = ""
3099 let Uses = [EFLAGS] in {
3100 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
3101 (ins GR8:$src1, GR8:$src2),
3102 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3103 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
3104 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
3105 (ins GR16:$src1, GR16:$src2),
3106 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3107 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
3108 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
3109 (ins GR32:$src1, GR32:$src2),
3110 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3111 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
3113 let Constraints = "" in {
3114 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
3115 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3116 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
3117 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
3118 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3119 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
3121 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
3122 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3123 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
3124 def SBB8mi : Ii8<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
3125 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3126 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
3127 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
3128 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3129 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
3131 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
3132 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3133 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
3135 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
3136 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3137 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
3138 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
3139 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3140 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
3142 def SBB8i8 : Ii8<0x1C, RawFrm, (outs), (ins i8imm:$src),
3143 "sbb{b}\t{$src, %al|%al, $src}", []>;
3144 def SBB16i16 : Ii16<0x1D, RawFrm, (outs), (ins i16imm:$src),
3145 "sbb{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3146 def SBB32i32 : Ii32<0x1D, RawFrm, (outs), (ins i32imm:$src),
3147 "sbb{l}\t{$src, %eax|%eax, $src}", []>;
3148 } // Constraints = ""
3150 let isCodeGenOnly = 1 in {
3151 def SBB8rr_REV : I<0x1A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
3152 "sbb{b}\t{$src2, $dst|$dst, $src2}", []>;
3153 def SBB16rr_REV : I<0x1B, MRMSrcReg, (outs GR16:$dst),
3154 (ins GR16:$src1, GR16:$src2),
3155 "sbb{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize;
3156 def SBB32rr_REV : I<0x1B, MRMSrcReg, (outs GR32:$dst),
3157 (ins GR32:$src1, GR32:$src2),
3158 "sbb{l}\t{$src2, $dst|$dst, $src2}", []>;
3161 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
3162 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3163 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
3164 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
3165 (ins GR16:$src1, i16mem:$src2),
3166 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3167 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
3169 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
3170 (ins GR32:$src1, i32mem:$src2),
3171 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3172 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
3173 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
3174 "sbb{b}\t{$src2, $dst|$dst, $src2}",
3175 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
3176 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
3177 (ins GR16:$src1, i16imm:$src2),
3178 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3179 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
3180 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
3181 (ins GR16:$src1, i16i8imm:$src2),
3182 "sbb{w}\t{$src2, $dst|$dst, $src2}",
3183 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
3185 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
3186 (ins GR32:$src1, i32imm:$src2),
3187 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3188 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
3189 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
3190 (ins GR32:$src1, i32i8imm:$src2),
3191 "sbb{l}\t{$src2, $dst|$dst, $src2}",
3192 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
3193 } // Uses = [EFLAGS]
3194 } // Defs = [EFLAGS]
3196 let Defs = [EFLAGS] in {
3197 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
3198 // Register-Register Signed Integer Multiply
3199 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
3200 "imul{w}\t{$src2, $dst|$dst, $src2}",
3201 [(set GR16:$dst, EFLAGS,
3202 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
3203 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
3204 "imul{l}\t{$src2, $dst|$dst, $src2}",
3205 [(set GR32:$dst, EFLAGS,
3206 (X86smul_flag GR32:$src1, GR32:$src2))]>, TB;
3209 // Register-Memory Signed Integer Multiply
3210 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
3211 (ins GR16:$src1, i16mem:$src2),
3212 "imul{w}\t{$src2, $dst|$dst, $src2}",
3213 [(set GR16:$dst, EFLAGS,
3214 (X86smul_flag GR16:$src1, (load addr:$src2)))]>,
3216 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
3217 (ins GR32:$src1, i32mem:$src2),
3218 "imul{l}\t{$src2, $dst|$dst, $src2}",
3219 [(set GR32:$dst, EFLAGS,
3220 (X86smul_flag GR32:$src1, (load addr:$src2)))]>, TB;
3221 } // Defs = [EFLAGS]
3222 } // end Two Address instructions
3224 // Suprisingly enough, these are not two address instructions!
3225 let Defs = [EFLAGS] in {
3226 // Register-Integer Signed Integer Multiply
3227 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
3228 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
3229 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3230 [(set GR16:$dst, EFLAGS,
3231 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
3232 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
3233 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
3234 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3235 [(set GR32:$dst, EFLAGS,
3236 (X86smul_flag GR32:$src1, imm:$src2))]>;
3237 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
3238 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
3239 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3240 [(set GR16:$dst, EFLAGS,
3241 (X86smul_flag GR16:$src1, i16immSExt8:$src2))]>,
3243 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
3244 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
3245 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3246 [(set GR32:$dst, EFLAGS,
3247 (X86smul_flag GR32:$src1, i32immSExt8:$src2))]>;
3249 // Memory-Integer Signed Integer Multiply
3250 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
3251 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
3252 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3253 [(set GR16:$dst, EFLAGS,
3254 (X86smul_flag (load addr:$src1), imm:$src2))]>,
3256 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
3257 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
3258 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3259 [(set GR32:$dst, EFLAGS,
3260 (X86smul_flag (load addr:$src1), imm:$src2))]>;
3261 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
3262 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
3263 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3264 [(set GR16:$dst, EFLAGS,
3265 (X86smul_flag (load addr:$src1),
3266 i16immSExt8:$src2))]>, OpSize;
3267 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
3268 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
3269 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3270 [(set GR32:$dst, EFLAGS,
3271 (X86smul_flag (load addr:$src1),
3272 i32immSExt8:$src2))]>;
3273 } // Defs = [EFLAGS]
3275 //===----------------------------------------------------------------------===//
3276 // Test instructions are just like AND, except they don't generate a result.
3278 let Defs = [EFLAGS] in {
3279 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
3280 def TEST8rr : I<0x84, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3281 "test{b}\t{$src2, $src1|$src1, $src2}",
3282 [(set EFLAGS, (X86cmp (and_su GR8:$src1, GR8:$src2), 0))]>;
3283 def TEST16rr : I<0x85, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3284 "test{w}\t{$src2, $src1|$src1, $src2}",
3285 [(set EFLAGS, (X86cmp (and_su GR16:$src1, GR16:$src2),
3288 def TEST32rr : I<0x85, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3289 "test{l}\t{$src2, $src1|$src1, $src2}",
3290 [(set EFLAGS, (X86cmp (and_su GR32:$src1, GR32:$src2),
3294 def TEST8i8 : Ii8<0xA8, RawFrm, (outs), (ins i8imm:$src),
3295 "test{b}\t{$src, %al|%al, $src}", []>;
3296 def TEST16i16 : Ii16<0xA9, RawFrm, (outs), (ins i16imm:$src),
3297 "test{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3298 def TEST32i32 : Ii32<0xA9, RawFrm, (outs), (ins i32imm:$src),
3299 "test{l}\t{$src, %eax|%eax, $src}", []>;
3301 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
3302 "test{b}\t{$src2, $src1|$src1, $src2}",
3303 [(set EFLAGS, (X86cmp (and GR8:$src1, (loadi8 addr:$src2)),
3305 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
3306 "test{w}\t{$src2, $src1|$src1, $src2}",
3307 [(set EFLAGS, (X86cmp (and GR16:$src1,
3308 (loadi16 addr:$src2)), 0))]>, OpSize;
3309 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
3310 "test{l}\t{$src2, $src1|$src1, $src2}",
3311 [(set EFLAGS, (X86cmp (and GR32:$src1,
3312 (loadi32 addr:$src2)), 0))]>;
3314 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
3315 (outs), (ins GR8:$src1, i8imm:$src2),
3316 "test{b}\t{$src2, $src1|$src1, $src2}",
3317 [(set EFLAGS, (X86cmp (and_su GR8:$src1, imm:$src2), 0))]>;
3318 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
3319 (outs), (ins GR16:$src1, i16imm:$src2),
3320 "test{w}\t{$src2, $src1|$src1, $src2}",
3321 [(set EFLAGS, (X86cmp (and_su GR16:$src1, imm:$src2), 0))]>,
3323 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
3324 (outs), (ins GR32:$src1, i32imm:$src2),
3325 "test{l}\t{$src2, $src1|$src1, $src2}",
3326 [(set EFLAGS, (X86cmp (and_su GR32:$src1, imm:$src2), 0))]>;
3328 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
3329 (outs), (ins i8mem:$src1, i8imm:$src2),
3330 "test{b}\t{$src2, $src1|$src1, $src2}",
3331 [(set EFLAGS, (X86cmp (and (loadi8 addr:$src1), imm:$src2),
3333 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
3334 (outs), (ins i16mem:$src1, i16imm:$src2),
3335 "test{w}\t{$src2, $src1|$src1, $src2}",
3336 [(set EFLAGS, (X86cmp (and (loadi16 addr:$src1), imm:$src2),
3338 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
3339 (outs), (ins i32mem:$src1, i32imm:$src2),
3340 "test{l}\t{$src2, $src1|$src1, $src2}",
3341 [(set EFLAGS, (X86cmp (and (loadi32 addr:$src1), imm:$src2),
3343 } // Defs = [EFLAGS]
3346 // Condition code ops, incl. set if equal/not equal/...
3347 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
3348 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
3349 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
3350 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
3352 let Uses = [EFLAGS] in {
3353 // Use sbb to materialize carry bit.
3354 let Defs = [EFLAGS], isCodeGenOnly = 1 in {
3355 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
3356 // However, Pat<> can't replicate the destination reg into the inputs of the
3358 // FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces
3360 def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "",
3361 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3362 def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "",
3363 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>,
3365 def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "",
3366 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
3369 def SETEr : I<0x94, MRM0r,
3370 (outs GR8 :$dst), (ins),
3372 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
3374 def SETEm : I<0x94, MRM0m,
3375 (outs), (ins i8mem:$dst),
3377 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
3380 def SETNEr : I<0x95, MRM0r,
3381 (outs GR8 :$dst), (ins),
3383 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
3385 def SETNEm : I<0x95, MRM0m,
3386 (outs), (ins i8mem:$dst),
3388 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
3391 def SETLr : I<0x9C, MRM0r,
3392 (outs GR8 :$dst), (ins),
3394 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
3395 TB; // GR8 = < signed
3396 def SETLm : I<0x9C, MRM0m,
3397 (outs), (ins i8mem:$dst),
3399 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
3400 TB; // [mem8] = < signed
3402 def SETGEr : I<0x9D, MRM0r,
3403 (outs GR8 :$dst), (ins),
3405 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
3406 TB; // GR8 = >= signed
3407 def SETGEm : I<0x9D, MRM0m,
3408 (outs), (ins i8mem:$dst),
3410 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
3411 TB; // [mem8] = >= signed
3413 def SETLEr : I<0x9E, MRM0r,
3414 (outs GR8 :$dst), (ins),
3416 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
3417 TB; // GR8 = <= signed
3418 def SETLEm : I<0x9E, MRM0m,
3419 (outs), (ins i8mem:$dst),
3421 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
3422 TB; // [mem8] = <= signed
3424 def SETGr : I<0x9F, MRM0r,
3425 (outs GR8 :$dst), (ins),
3427 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
3428 TB; // GR8 = > signed
3429 def SETGm : I<0x9F, MRM0m,
3430 (outs), (ins i8mem:$dst),
3432 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
3433 TB; // [mem8] = > signed
3435 def SETBr : I<0x92, MRM0r,
3436 (outs GR8 :$dst), (ins),
3438 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
3439 TB; // GR8 = < unsign
3440 def SETBm : I<0x92, MRM0m,
3441 (outs), (ins i8mem:$dst),
3443 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
3444 TB; // [mem8] = < unsign
3446 def SETAEr : I<0x93, MRM0r,
3447 (outs GR8 :$dst), (ins),
3449 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
3450 TB; // GR8 = >= unsign
3451 def SETAEm : I<0x93, MRM0m,
3452 (outs), (ins i8mem:$dst),
3454 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
3455 TB; // [mem8] = >= unsign
3457 def SETBEr : I<0x96, MRM0r,
3458 (outs GR8 :$dst), (ins),
3460 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
3461 TB; // GR8 = <= unsign
3462 def SETBEm : I<0x96, MRM0m,
3463 (outs), (ins i8mem:$dst),
3465 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
3466 TB; // [mem8] = <= unsign
3468 def SETAr : I<0x97, MRM0r,
3469 (outs GR8 :$dst), (ins),
3471 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
3472 TB; // GR8 = > signed
3473 def SETAm : I<0x97, MRM0m,
3474 (outs), (ins i8mem:$dst),
3476 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
3477 TB; // [mem8] = > signed
3479 def SETSr : I<0x98, MRM0r,
3480 (outs GR8 :$dst), (ins),
3482 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
3483 TB; // GR8 = <sign bit>
3484 def SETSm : I<0x98, MRM0m,
3485 (outs), (ins i8mem:$dst),
3487 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
3488 TB; // [mem8] = <sign bit>
3489 def SETNSr : I<0x99, MRM0r,
3490 (outs GR8 :$dst), (ins),
3492 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
3493 TB; // GR8 = !<sign bit>
3494 def SETNSm : I<0x99, MRM0m,
3495 (outs), (ins i8mem:$dst),
3497 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
3498 TB; // [mem8] = !<sign bit>
3500 def SETPr : I<0x9A, MRM0r,
3501 (outs GR8 :$dst), (ins),
3503 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
3505 def SETPm : I<0x9A, MRM0m,
3506 (outs), (ins i8mem:$dst),
3508 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
3509 TB; // [mem8] = parity
3510 def SETNPr : I<0x9B, MRM0r,
3511 (outs GR8 :$dst), (ins),
3513 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
3514 TB; // GR8 = not parity
3515 def SETNPm : I<0x9B, MRM0m,
3516 (outs), (ins i8mem:$dst),
3518 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
3519 TB; // [mem8] = not parity
3521 def SETOr : I<0x90, MRM0r,
3522 (outs GR8 :$dst), (ins),
3524 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
3525 TB; // GR8 = overflow
3526 def SETOm : I<0x90, MRM0m,
3527 (outs), (ins i8mem:$dst),
3529 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
3530 TB; // [mem8] = overflow
3531 def SETNOr : I<0x91, MRM0r,
3532 (outs GR8 :$dst), (ins),
3534 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
3535 TB; // GR8 = not overflow
3536 def SETNOm : I<0x91, MRM0m,
3537 (outs), (ins i8mem:$dst),
3539 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
3540 TB; // [mem8] = not overflow
3541 } // Uses = [EFLAGS]
3544 // Integer comparisons
3545 let Defs = [EFLAGS] in {
3546 def CMP8i8 : Ii8<0x3C, RawFrm, (outs), (ins i8imm:$src),
3547 "cmp{b}\t{$src, %al|%al, $src}", []>;
3548 def CMP16i16 : Ii16<0x3D, RawFrm, (outs), (ins i16imm:$src),
3549 "cmp{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3550 def CMP32i32 : Ii32<0x3D, RawFrm, (outs), (ins i32imm:$src),
3551 "cmp{l}\t{$src, %eax|%eax, $src}", []>;
3553 def CMP8rr : I<0x38, MRMDestReg,
3554 (outs), (ins GR8 :$src1, GR8 :$src2),
3555 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3556 [(set EFLAGS, (X86cmp GR8:$src1, GR8:$src2))]>;
3557 def CMP16rr : I<0x39, MRMDestReg,
3558 (outs), (ins GR16:$src1, GR16:$src2),
3559 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3560 [(set EFLAGS, (X86cmp GR16:$src1, GR16:$src2))]>, OpSize;
3561 def CMP32rr : I<0x39, MRMDestReg,
3562 (outs), (ins GR32:$src1, GR32:$src2),
3563 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3564 [(set EFLAGS, (X86cmp GR32:$src1, GR32:$src2))]>;
3565 def CMP8mr : I<0x38, MRMDestMem,
3566 (outs), (ins i8mem :$src1, GR8 :$src2),
3567 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3568 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), GR8:$src2))]>;
3569 def CMP16mr : I<0x39, MRMDestMem,
3570 (outs), (ins i16mem:$src1, GR16:$src2),
3571 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3572 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), GR16:$src2))]>,
3574 def CMP32mr : I<0x39, MRMDestMem,
3575 (outs), (ins i32mem:$src1, GR32:$src2),
3576 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3577 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), GR32:$src2))]>;
3578 def CMP8rm : I<0x3A, MRMSrcMem,
3579 (outs), (ins GR8 :$src1, i8mem :$src2),
3580 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3581 [(set EFLAGS, (X86cmp GR8:$src1, (loadi8 addr:$src2)))]>;
3582 def CMP16rm : I<0x3B, MRMSrcMem,
3583 (outs), (ins GR16:$src1, i16mem:$src2),
3584 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3585 [(set EFLAGS, (X86cmp GR16:$src1, (loadi16 addr:$src2)))]>,
3587 def CMP32rm : I<0x3B, MRMSrcMem,
3588 (outs), (ins GR32:$src1, i32mem:$src2),
3589 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3590 [(set EFLAGS, (X86cmp GR32:$src1, (loadi32 addr:$src2)))]>;
3592 // These are alternate spellings for use by the disassembler, we mark them as
3593 // code gen only to ensure they aren't matched by the assembler.
3594 let isCodeGenOnly = 1 in {
3595 def CMP8rr_alt : I<0x3A, MRMSrcReg, (outs), (ins GR8:$src1, GR8:$src2),
3596 "cmp{b}\t{$src2, $src1|$src1, $src2}", []>;
3597 def CMP16rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
3598 "cmp{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize;
3599 def CMP32rr_alt : I<0x3B, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
3600 "cmp{l}\t{$src2, $src1|$src1, $src2}", []>;
3603 def CMP8ri : Ii8<0x80, MRM7r,
3604 (outs), (ins GR8:$src1, i8imm:$src2),
3605 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3606 [(set EFLAGS, (X86cmp GR8:$src1, imm:$src2))]>;
3607 def CMP16ri : Ii16<0x81, MRM7r,
3608 (outs), (ins GR16:$src1, i16imm:$src2),
3609 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3610 [(set EFLAGS, (X86cmp GR16:$src1, imm:$src2))]>, OpSize;
3611 def CMP32ri : Ii32<0x81, MRM7r,
3612 (outs), (ins GR32:$src1, i32imm:$src2),
3613 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3614 [(set EFLAGS, (X86cmp GR32:$src1, imm:$src2))]>;
3615 def CMP8mi : Ii8 <0x80, MRM7m,
3616 (outs), (ins i8mem :$src1, i8imm :$src2),
3617 "cmp{b}\t{$src2, $src1|$src1, $src2}",
3618 [(set EFLAGS, (X86cmp (loadi8 addr:$src1), imm:$src2))]>;
3619 def CMP16mi : Ii16<0x81, MRM7m,
3620 (outs), (ins i16mem:$src1, i16imm:$src2),
3621 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3622 [(set EFLAGS, (X86cmp (loadi16 addr:$src1), imm:$src2))]>,
3624 def CMP32mi : Ii32<0x81, MRM7m,
3625 (outs), (ins i32mem:$src1, i32imm:$src2),
3626 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3627 [(set EFLAGS, (X86cmp (loadi32 addr:$src1), imm:$src2))]>;
3628 def CMP16ri8 : Ii8<0x83, MRM7r,
3629 (outs), (ins GR16:$src1, i16i8imm:$src2),
3630 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3631 [(set EFLAGS, (X86cmp GR16:$src1, i16immSExt8:$src2))]>,
3633 def CMP16mi8 : Ii8<0x83, MRM7m,
3634 (outs), (ins i16mem:$src1, i16i8imm:$src2),
3635 "cmp{w}\t{$src2, $src1|$src1, $src2}",
3636 [(set EFLAGS, (X86cmp (loadi16 addr:$src1),
3637 i16immSExt8:$src2))]>, OpSize;
3638 def CMP32mi8 : Ii8<0x83, MRM7m,
3639 (outs), (ins i32mem:$src1, i32i8imm:$src2),
3640 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3641 [(set EFLAGS, (X86cmp (loadi32 addr:$src1),
3642 i32immSExt8:$src2))]>;
3643 def CMP32ri8 : Ii8<0x83, MRM7r,
3644 (outs), (ins GR32:$src1, i32i8imm:$src2),
3645 "cmp{l}\t{$src2, $src1|$src1, $src2}",
3646 [(set EFLAGS, (X86cmp GR32:$src1, i32immSExt8:$src2))]>;
3647 } // Defs = [EFLAGS]
3650 // TODO: BTC, BTR, and BTS
3651 let Defs = [EFLAGS] in {
3652 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3653 "bt{w}\t{$src2, $src1|$src1, $src2}",
3654 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, OpSize, TB;
3655 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3656 "bt{l}\t{$src2, $src1|$src1, $src2}",
3657 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, TB;
3659 // Unlike with the register+register form, the memory+register form of the
3660 // bt instruction does not ignore the high bits of the index. From ISel's
3661 // perspective, this is pretty bizarre. Make these instructions disassembly
3664 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3665 "bt{w}\t{$src2, $src1|$src1, $src2}",
3666 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
3667 // (implicit EFLAGS)]
3669 >, OpSize, TB, Requires<[FastBTMem]>;
3670 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3671 "bt{l}\t{$src2, $src1|$src1, $src2}",
3672 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
3673 // (implicit EFLAGS)]
3675 >, TB, Requires<[FastBTMem]>;
3677 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3678 "bt{w}\t{$src2, $src1|$src1, $src2}",
3679 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))]>,
3681 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3682 "bt{l}\t{$src2, $src1|$src1, $src2}",
3683 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))]>, TB;
3684 // Note that these instructions don't need FastBTMem because that
3685 // only applies when the other operand is in a register. When it's
3686 // an immediate, bt is still fast.
3687 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3688 "bt{w}\t{$src2, $src1|$src1, $src2}",
3689 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
3691 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3692 "bt{l}\t{$src2, $src1|$src1, $src2}",
3693 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
3696 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3697 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3698 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3699 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3700 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3701 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3702 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3703 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3704 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3705 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3706 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3707 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3708 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3709 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3710 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3711 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3713 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3714 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3715 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3716 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3717 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3718 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3719 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3720 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3721 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3722 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3723 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3724 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3725 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3726 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3727 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3728 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3730 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
3731 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3732 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
3733 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3734 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
3735 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3736 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
3737 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3738 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
3739 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3740 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
3741 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3742 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3743 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize, TB;
3744 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3745 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, TB;
3746 } // Defs = [EFLAGS]
3748 // Sign/Zero extenders
3749 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3750 // of the register here. This has a smaller encoding and avoids a
3751 // partial-register update. Actual movsbw included for the disassembler.
3752 def MOVSX16rr8W : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3753 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3754 def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3755 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3756 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3757 "", [(set GR16:$dst, (sext GR8:$src))]>, TB;
3758 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3759 "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3760 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3761 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3762 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3763 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3764 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3765 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3766 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3767 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3768 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3769 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3770 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3771 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3773 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3774 // of the register here. This has a smaller encoding and avoids a
3775 // partial-register update. Actual movzbw included for the disassembler.
3776 def MOVZX16rr8W : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
3777 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3778 def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
3779 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3780 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3781 "", [(set GR16:$dst, (zext GR8:$src))]>, TB;
3782 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3783 "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3784 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3785 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3786 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3787 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3788 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3789 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3790 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3791 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3792 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3793 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3794 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3795 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3797 // These are the same as the regular MOVZX32rr8 and MOVZX32rm8
3798 // except that they use GR32_NOREX for the output operand register class
3799 // instead of GR32. This allows them to operate on h registers on x86-64.
3800 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3801 (outs GR32_NOREX:$dst), (ins GR8:$src),
3802 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3805 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3806 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3807 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3810 let neverHasSideEffects = 1 in {
3811 let Defs = [AX], Uses = [AL] in
3812 def CBW : I<0x98, RawFrm, (outs), (ins),
3813 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3814 let Defs = [EAX], Uses = [AX] in
3815 def CWDE : I<0x98, RawFrm, (outs), (ins),
3816 "{cwtl|cwde}", []>; // EAX = signext(AX)
3818 let Defs = [AX,DX], Uses = [AX] in
3819 def CWD : I<0x99, RawFrm, (outs), (ins),
3820 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3821 let Defs = [EAX,EDX], Uses = [EAX] in
3822 def CDQ : I<0x99, RawFrm, (outs), (ins),
3823 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3826 //===----------------------------------------------------------------------===//
3827 // Alias Instructions
3828 //===----------------------------------------------------------------------===//
3830 // Alias instructions that map movr0 to xor.
3831 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3832 // FIXME: Set encoding to pseudo.
3833 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
3834 isCodeGenOnly = 1 in {
3835 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins), "",
3836 [(set GR8:$dst, 0)]>;
3838 // We want to rewrite MOV16r0 in terms of MOV32r0, because it's a smaller
3839 // encoding and avoids a partial-register update sometimes, but doing so
3840 // at isel time interferes with rematerialization in the current register
3841 // allocator. For now, this is rewritten when the instruction is lowered
3843 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3845 [(set GR16:$dst, 0)]>, OpSize;
3847 // FIXME: Set encoding to pseudo.
3848 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "",
3849 [(set GR32:$dst, 0)]>;
3852 //===----------------------------------------------------------------------===//
3853 // Thread Local Storage Instructions
3857 // All calls clobber the non-callee saved registers. ESP is marked as
3858 // a use to prevent stack-pointer assignments that appear immediately
3859 // before calls from potentially appearing dead.
3860 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3861 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3862 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3863 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3865 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
3866 "leal\t$sym, %eax; "
3867 "call\t___tls_get_addr@PLT",
3868 [(X86tlsaddr tls32addr:$sym)]>,
3869 Requires<[In32BitMode]>;
3871 // Darwin TLS Support
3872 // For i386, the address of the thunk is passed on the stack, on return the
3873 // address of the variable is in %eax. %ecx is trashed during the function
3874 // call. All other registers are preserved.
3875 let Defs = [EAX, ECX],
3877 usesCustomInserter = 1 in
3878 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
3880 [(X86TLSCall addr:$sym)]>,
3881 Requires<[In32BitMode]>;
3883 let AddedComplexity = 5, isCodeGenOnly = 1 in
3884 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3885 "movl\t%gs:$src, $dst",
3886 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3888 let AddedComplexity = 5, isCodeGenOnly = 1 in
3889 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3890 "movl\t%fs:$src, $dst",
3891 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3893 //===----------------------------------------------------------------------===//
3894 // EH Pseudo Instructions
3896 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3897 hasCtrlDep = 1, isCodeGenOnly = 1 in {
3898 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3899 "ret\t#eh_return, addr: $addr",
3900 [(X86ehret GR32:$addr)]>;
3904 //===----------------------------------------------------------------------===//
3908 // Atomic swap. These are just normal xchg instructions. But since a memory
3909 // operand is referenced, the atomicity is ensured.
3910 let Constraints = "$val = $dst" in {
3911 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),
3912 (ins GR32:$val, i32mem:$ptr),
3913 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3914 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3915 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),
3916 (ins GR16:$val, i16mem:$ptr),
3917 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3918 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3920 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3921 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3922 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3924 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
3925 "xchg{l}\t{$val, $src|$src, $val}", []>;
3926 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
3927 "xchg{w}\t{$val, $src|$src, $val}", []>, OpSize;
3928 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
3929 "xchg{b}\t{$val, $src|$src, $val}", []>;
3932 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
3933 "xchg{w}\t{$src, %ax|%ax, $src}", []>, OpSize;
3934 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
3935 "xchg{l}\t{$src, %eax|%eax, $src}", []>;
3937 // Atomic compare and swap.
3938 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3939 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3941 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3942 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3944 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3945 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$ptr),
3948 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3951 let Defs = [AX, EFLAGS], Uses = [AX] in {
3952 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3954 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3955 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3957 let Defs = [AL, EFLAGS], Uses = [AL] in {
3958 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3960 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3961 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3964 // Atomic exchange and add
3965 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3966 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins GR32:$val, i32mem:$ptr),
3968 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3969 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3971 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins GR16:$val, i16mem:$ptr),
3973 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3974 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3976 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr),
3978 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3979 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3983 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
3984 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3985 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
3986 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3987 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
3988 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3990 let mayLoad = 1, mayStore = 1 in {
3991 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
3992 "xadd{b}\t{$src, $dst|$dst, $src}", []>, TB;
3993 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
3994 "xadd{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
3995 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3996 "xadd{l}\t{$src, $dst|$dst, $src}", []>, TB;
3999 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
4000 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
4001 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
4002 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4003 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4004 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
4006 let mayLoad = 1, mayStore = 1 in {
4007 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
4008 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB;
4009 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
4010 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4011 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
4012 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB;
4015 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
4016 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
4017 "cmpxchg8b\t$dst", []>, TB;
4019 // Optimized codegen when the non-memory output is not used.
4020 // FIXME: Use normal add / sub instructions and add lock prefix dynamically.
4021 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1 in {
4022 def LOCK_ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
4024 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4025 def LOCK_ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
4027 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4028 def LOCK_ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
4030 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4031 def LOCK_ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
4033 "add{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4034 def LOCK_ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
4036 "add{w}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4037 def LOCK_ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
4039 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4040 def LOCK_ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4042 "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4043 def LOCK_ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4045 "add{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4047 def LOCK_INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst),
4049 "inc{b}\t$dst", []>, LOCK;
4050 def LOCK_INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst),
4052 "inc{w}\t$dst", []>, OpSize, LOCK;
4053 def LOCK_INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst),
4055 "inc{l}\t$dst", []>, LOCK;
4057 def LOCK_SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
4059 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4060 def LOCK_SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
4062 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4063 def LOCK_SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
4065 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4066 def LOCK_SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
4068 "sub{b}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4069 def LOCK_SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
4071 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4072 def LOCK_SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
4074 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4075 def LOCK_SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
4077 "sub{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize, LOCK;
4078 def LOCK_SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
4080 "sub{l}\t{$src2, $dst|$dst, $src2}", []>, LOCK;
4082 def LOCK_DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst),
4084 "dec{b}\t$dst", []>, LOCK;
4085 def LOCK_DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst),
4087 "dec{w}\t$dst", []>, OpSize, LOCK;
4088 def LOCK_DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst),
4090 "dec{l}\t$dst", []>, LOCK;
4093 // Atomic exchange, and, or, xor
4094 let Constraints = "$val = $dst", Defs = [EFLAGS],
4095 usesCustomInserter = 1 in {
4096 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4097 "#ATOMAND32 PSEUDO!",
4098 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
4099 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4100 "#ATOMOR32 PSEUDO!",
4101 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
4102 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4103 "#ATOMXOR32 PSEUDO!",
4104 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
4105 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4106 "#ATOMNAND32 PSEUDO!",
4107 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
4108 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
4109 "#ATOMMIN32 PSEUDO!",
4110 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
4111 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4112 "#ATOMMAX32 PSEUDO!",
4113 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
4114 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4115 "#ATOMUMIN32 PSEUDO!",
4116 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
4117 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
4118 "#ATOMUMAX32 PSEUDO!",
4119 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
4121 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4122 "#ATOMAND16 PSEUDO!",
4123 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
4124 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4125 "#ATOMOR16 PSEUDO!",
4126 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
4127 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4128 "#ATOMXOR16 PSEUDO!",
4129 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
4130 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4131 "#ATOMNAND16 PSEUDO!",
4132 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
4133 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
4134 "#ATOMMIN16 PSEUDO!",
4135 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
4136 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4137 "#ATOMMAX16 PSEUDO!",
4138 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
4139 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4140 "#ATOMUMIN16 PSEUDO!",
4141 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
4142 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
4143 "#ATOMUMAX16 PSEUDO!",
4144 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
4146 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4147 "#ATOMAND8 PSEUDO!",
4148 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
4149 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4151 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
4152 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4153 "#ATOMXOR8 PSEUDO!",
4154 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
4155 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
4156 "#ATOMNAND8 PSEUDO!",
4157 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
4160 let Constraints = "$val1 = $dst1, $val2 = $dst2",
4161 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
4162 Uses = [EAX, EBX, ECX, EDX],
4163 mayLoad = 1, mayStore = 1,
4164 usesCustomInserter = 1 in {
4165 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4166 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4167 "#ATOMAND6432 PSEUDO!", []>;
4168 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4169 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4170 "#ATOMOR6432 PSEUDO!", []>;
4171 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4172 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4173 "#ATOMXOR6432 PSEUDO!", []>;
4174 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4175 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4176 "#ATOMNAND6432 PSEUDO!", []>;
4177 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4178 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4179 "#ATOMADD6432 PSEUDO!", []>;
4180 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4181 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4182 "#ATOMSUB6432 PSEUDO!", []>;
4183 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
4184 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
4185 "#ATOMSWAP6432 PSEUDO!", []>;
4188 // Segmentation support instructions.
4190 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4191 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4192 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4193 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4195 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
4196 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
4197 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4198 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4199 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
4201 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4202 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4203 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4204 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4205 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4206 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4207 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4208 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
4210 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
4212 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
4213 "str{w}\t{$dst}", []>, TB;
4214 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
4215 "str{w}\t{$dst}", []>, TB;
4216 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
4217 "ltr{w}\t{$src}", []>, TB;
4218 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
4219 "ltr{w}\t{$src}", []>, TB;
4221 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
4222 "push{w}\t%fs", []>, OpSize, TB;
4223 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
4224 "push{l}\t%fs", []>, TB;
4225 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
4226 "push{w}\t%gs", []>, OpSize, TB;
4227 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
4228 "push{l}\t%gs", []>, TB;
4230 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
4231 "pop{w}\t%fs", []>, OpSize, TB;
4232 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
4233 "pop{l}\t%fs", []>, TB;
4234 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
4235 "pop{w}\t%gs", []>, OpSize, TB;
4236 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
4237 "pop{l}\t%gs", []>, TB;
4239 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4240 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4241 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4242 "lds{l}\t{$src, $dst|$dst, $src}", []>;
4243 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4244 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4245 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4246 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
4247 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4248 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
4249 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4250 "les{l}\t{$src, $dst|$dst, $src}", []>;
4251 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4252 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4253 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4254 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4255 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
4256 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
4257 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
4258 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
4260 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
4261 "verr\t$seg", []>, TB;
4262 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
4263 "verr\t$seg", []>, TB;
4264 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
4265 "verw\t$seg", []>, TB;
4266 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
4267 "verw\t$seg", []>, TB;
4269 // Descriptor-table support instructions
4271 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
4272 "sgdt\t$dst", []>, TB;
4273 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
4274 "sidt\t$dst", []>, TB;
4275 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
4276 "sldt{w}\t$dst", []>, TB;
4277 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
4278 "sldt{w}\t$dst", []>, TB;
4279 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
4280 "lgdt\t$src", []>, TB;
4281 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
4282 "lidt\t$src", []>, TB;
4283 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
4284 "lldt{w}\t$src", []>, TB;
4285 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
4286 "lldt{w}\t$src", []>, TB;
4288 // Lock instruction prefix
4289 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
4291 // Repeat string operation instruction prefixes
4292 // These uses the DF flag in the EFLAGS register to inc or dec ECX
4293 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
4294 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
4295 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
4296 // Repeat while not equal (used with CMPS and SCAS)
4297 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
4300 // Segment override instruction prefixes
4301 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
4302 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
4303 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
4304 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
4305 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
4306 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
4308 // String manipulation instructions
4310 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
4311 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
4312 def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", []>;
4314 def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
4315 def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
4316 def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
4318 // CPU flow control instructions
4320 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
4321 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
4323 // FPU control instructions
4325 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
4327 // Flag instructions
4329 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
4330 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
4331 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
4332 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", []>;
4333 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>;
4334 def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>;
4335 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
4337 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
4339 // Table lookup instructions
4341 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
4343 // Specialized register support
4345 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
4346 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
4347 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
4349 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
4350 "smsw{w}\t$dst", []>, OpSize, TB;
4351 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
4352 "smsw{l}\t$dst", []>, TB;
4353 // For memory operands, there is only a 16-bit form
4354 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
4355 "smsw{w}\t$dst", []>, TB;
4357 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
4358 "lmsw{w}\t$src", []>, TB;
4359 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
4360 "lmsw{w}\t$src", []>, TB;
4362 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
4364 // Cache instructions
4366 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
4367 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
4372 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
4374 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
4376 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
4377 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4378 "vmclear\t$vmcs", []>, OpSize, TB;
4380 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
4382 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4383 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
4384 "vmptrld\t$vmcs", []>, TB;
4385 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4386 "vmptrst\t$vmcs", []>, TB;
4387 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
4388 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4389 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
4390 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB;
4391 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
4392 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4393 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
4394 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB;
4395 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4396 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4397 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4398 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB;
4399 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4400 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4401 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4402 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB;
4404 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
4405 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
4406 "vmxon\t{$vmxon}", []>, XS;
4408 //===----------------------------------------------------------------------===//
4409 // Non-Instruction Patterns
4410 //===----------------------------------------------------------------------===//
4412 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
4413 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
4414 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
4415 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
4416 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
4417 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
4418 def : Pat<(i32 (X86Wrapper tblockaddress:$dst)), (MOV32ri tblockaddress:$dst)>;
4420 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
4421 (ADD32ri GR32:$src1, tconstpool:$src2)>;
4422 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
4423 (ADD32ri GR32:$src1, tjumptable:$src2)>;
4424 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
4425 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
4426 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
4427 (ADD32ri GR32:$src1, texternalsym:$src2)>;
4428 def : Pat<(add GR32:$src1, (X86Wrapper tblockaddress:$src2)),
4429 (ADD32ri GR32:$src1, tblockaddress:$src2)>;
4431 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
4432 (MOV32mi addr:$dst, tglobaladdr:$src)>;
4433 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
4434 (MOV32mi addr:$dst, texternalsym:$src)>;
4435 def : Pat<(store (i32 (X86Wrapper tblockaddress:$src)), addr:$dst),
4436 (MOV32mi addr:$dst, tblockaddress:$src)>;
4440 def : Pat<(X86tcret GR32_TC:$dst, imm:$off),
4441 (TCRETURNri GR32_TC:$dst, imm:$off)>,
4442 Requires<[In32BitMode]>;
4444 // FIXME: This is disabled for 32-bit PIC mode because the global base
4445 // register which is part of the address mode may be assigned a
4446 // callee-saved register.
4447 def : Pat<(X86tcret (load addr:$dst), imm:$off),
4448 (TCRETURNmi addr:$dst, imm:$off)>,
4449 Requires<[In32BitMode, IsNotPIC]>;
4451 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
4452 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4453 Requires<[In32BitMode]>;
4455 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
4456 (TCRETURNdi texternalsym:$dst, imm:$off)>,
4457 Requires<[In32BitMode]>;
4459 // Normal calls, with various flavors of addresses.
4460 def : Pat<(X86call (i32 tglobaladdr:$dst)),
4461 (CALLpcrel32 tglobaladdr:$dst)>;
4462 def : Pat<(X86call (i32 texternalsym:$dst)),
4463 (CALLpcrel32 texternalsym:$dst)>;
4464 def : Pat<(X86call (i32 imm:$dst)),
4465 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
4467 // X86 specific add which produces a flag.
4468 def : Pat<(addc GR32:$src1, GR32:$src2),
4469 (ADD32rr GR32:$src1, GR32:$src2)>;
4470 def : Pat<(addc GR32:$src1, (load addr:$src2)),
4471 (ADD32rm GR32:$src1, addr:$src2)>;
4472 def : Pat<(addc GR32:$src1, imm:$src2),
4473 (ADD32ri GR32:$src1, imm:$src2)>;
4474 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
4475 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4477 def : Pat<(subc GR32:$src1, GR32:$src2),
4478 (SUB32rr GR32:$src1, GR32:$src2)>;
4479 def : Pat<(subc GR32:$src1, (load addr:$src2)),
4480 (SUB32rm GR32:$src1, addr:$src2)>;
4481 def : Pat<(subc GR32:$src1, imm:$src2),
4482 (SUB32ri GR32:$src1, imm:$src2)>;
4483 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
4484 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4488 // TEST R,R is smaller than CMP R,0
4489 def : Pat<(X86cmp GR8:$src1, 0),
4490 (TEST8rr GR8:$src1, GR8:$src1)>;
4491 def : Pat<(X86cmp GR16:$src1, 0),
4492 (TEST16rr GR16:$src1, GR16:$src1)>;
4493 def : Pat<(X86cmp GR32:$src1, 0),
4494 (TEST32rr GR32:$src1, GR32:$src1)>;
4496 // Conditional moves with folded loads with operands swapped and conditions
4498 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
4499 (CMOVAE16rm GR16:$src2, addr:$src1)>;
4500 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
4501 (CMOVAE32rm GR32:$src2, addr:$src1)>;
4502 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
4503 (CMOVB16rm GR16:$src2, addr:$src1)>;
4504 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
4505 (CMOVB32rm GR32:$src2, addr:$src1)>;
4506 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
4507 (CMOVNE16rm GR16:$src2, addr:$src1)>;
4508 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
4509 (CMOVNE32rm GR32:$src2, addr:$src1)>;
4510 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
4511 (CMOVE16rm GR16:$src2, addr:$src1)>;
4512 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
4513 (CMOVE32rm GR32:$src2, addr:$src1)>;
4514 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
4515 (CMOVA16rm GR16:$src2, addr:$src1)>;
4516 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
4517 (CMOVA32rm GR32:$src2, addr:$src1)>;
4518 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
4519 (CMOVBE16rm GR16:$src2, addr:$src1)>;
4520 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
4521 (CMOVBE32rm GR32:$src2, addr:$src1)>;
4522 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
4523 (CMOVGE16rm GR16:$src2, addr:$src1)>;
4524 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
4525 (CMOVGE32rm GR32:$src2, addr:$src1)>;
4526 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
4527 (CMOVL16rm GR16:$src2, addr:$src1)>;
4528 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
4529 (CMOVL32rm GR32:$src2, addr:$src1)>;
4530 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
4531 (CMOVG16rm GR16:$src2, addr:$src1)>;
4532 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
4533 (CMOVG32rm GR32:$src2, addr:$src1)>;
4534 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
4535 (CMOVLE16rm GR16:$src2, addr:$src1)>;
4536 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
4537 (CMOVLE32rm GR32:$src2, addr:$src1)>;
4538 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
4539 (CMOVNP16rm GR16:$src2, addr:$src1)>;
4540 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
4541 (CMOVNP32rm GR32:$src2, addr:$src1)>;
4542 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
4543 (CMOVP16rm GR16:$src2, addr:$src1)>;
4544 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
4545 (CMOVP32rm GR32:$src2, addr:$src1)>;
4546 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
4547 (CMOVNS16rm GR16:$src2, addr:$src1)>;
4548 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
4549 (CMOVNS32rm GR32:$src2, addr:$src1)>;
4550 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
4551 (CMOVS16rm GR16:$src2, addr:$src1)>;
4552 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
4553 (CMOVS32rm GR32:$src2, addr:$src1)>;
4554 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
4555 (CMOVNO16rm GR16:$src2, addr:$src1)>;
4556 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
4557 (CMOVNO32rm GR32:$src2, addr:$src1)>;
4558 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
4559 (CMOVO16rm GR16:$src2, addr:$src1)>;
4560 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
4561 (CMOVO32rm GR32:$src2, addr:$src1)>;
4563 // zextload bool -> zextload byte
4564 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4565 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4566 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4568 // extload bool -> extload byte
4569 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
4570 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
4571 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
4572 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
4573 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
4574 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
4576 // anyext. Define these to do an explicit zero-extend to
4577 // avoid partial-register updates.
4578 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>;
4579 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
4581 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
4582 def : Pat<(i32 (anyext GR16:$src)),
4583 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
4586 //===----------------------------------------------------------------------===//
4588 //===----------------------------------------------------------------------===//
4590 // Odd encoding trick: -128 fits into an 8-bit immediate field while
4591 // +128 doesn't, so in this special case use a sub instead of an add.
4592 def : Pat<(add GR16:$src1, 128),
4593 (SUB16ri8 GR16:$src1, -128)>;
4594 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
4595 (SUB16mi8 addr:$dst, -128)>;
4596 def : Pat<(add GR32:$src1, 128),
4597 (SUB32ri8 GR32:$src1, -128)>;
4598 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
4599 (SUB32mi8 addr:$dst, -128)>;
4601 // r & (2^16-1) ==> movz
4602 def : Pat<(and GR32:$src1, 0xffff),
4603 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
4604 // r & (2^8-1) ==> movz
4605 def : Pat<(and GR32:$src1, 0xff),
4606 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
4609 Requires<[In32BitMode]>;
4610 // r & (2^8-1) ==> movz
4611 def : Pat<(and GR16:$src1, 0xff),
4612 (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1,
4615 Requires<[In32BitMode]>;
4617 // sext_inreg patterns
4618 def : Pat<(sext_inreg GR32:$src, i16),
4619 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
4620 def : Pat<(sext_inreg GR32:$src, i8),
4621 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4624 Requires<[In32BitMode]>;
4625 def : Pat<(sext_inreg GR16:$src, i8),
4626 (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4629 Requires<[In32BitMode]>;
4632 def : Pat<(i16 (trunc GR32:$src)),
4633 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
4634 def : Pat<(i8 (trunc GR32:$src)),
4635 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4637 Requires<[In32BitMode]>;
4638 def : Pat<(i8 (trunc GR16:$src)),
4639 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4641 Requires<[In32BitMode]>;
4643 // h-register tricks
4644 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
4645 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4647 Requires<[In32BitMode]>;
4648 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
4649 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
4651 Requires<[In32BitMode]>;
4652 def : Pat<(srl GR16:$src, (i8 8)),
4655 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
4658 Requires<[In32BitMode]>;
4659 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
4660 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4663 Requires<[In32BitMode]>;
4664 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
4665 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
4668 Requires<[In32BitMode]>;
4669 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
4670 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4673 Requires<[In32BitMode]>;
4674 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
4675 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
4678 Requires<[In32BitMode]>;
4680 // (shl x, 1) ==> (add x, x)
4681 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
4682 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
4683 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
4685 // (shl x (and y, 31)) ==> (shl x, y)
4686 def : Pat<(shl GR8:$src1, (and CL, 31)),
4687 (SHL8rCL GR8:$src1)>;
4688 def : Pat<(shl GR16:$src1, (and CL, 31)),
4689 (SHL16rCL GR16:$src1)>;
4690 def : Pat<(shl GR32:$src1, (and CL, 31)),
4691 (SHL32rCL GR32:$src1)>;
4692 def : Pat<(store (shl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4693 (SHL8mCL addr:$dst)>;
4694 def : Pat<(store (shl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4695 (SHL16mCL addr:$dst)>;
4696 def : Pat<(store (shl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4697 (SHL32mCL addr:$dst)>;
4699 def : Pat<(srl GR8:$src1, (and CL, 31)),
4700 (SHR8rCL GR8:$src1)>;
4701 def : Pat<(srl GR16:$src1, (and CL, 31)),
4702 (SHR16rCL GR16:$src1)>;
4703 def : Pat<(srl GR32:$src1, (and CL, 31)),
4704 (SHR32rCL GR32:$src1)>;
4705 def : Pat<(store (srl (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4706 (SHR8mCL addr:$dst)>;
4707 def : Pat<(store (srl (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4708 (SHR16mCL addr:$dst)>;
4709 def : Pat<(store (srl (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4710 (SHR32mCL addr:$dst)>;
4712 def : Pat<(sra GR8:$src1, (and CL, 31)),
4713 (SAR8rCL GR8:$src1)>;
4714 def : Pat<(sra GR16:$src1, (and CL, 31)),
4715 (SAR16rCL GR16:$src1)>;
4716 def : Pat<(sra GR32:$src1, (and CL, 31)),
4717 (SAR32rCL GR32:$src1)>;
4718 def : Pat<(store (sra (loadi8 addr:$dst), (and CL, 31)), addr:$dst),
4719 (SAR8mCL addr:$dst)>;
4720 def : Pat<(store (sra (loadi16 addr:$dst), (and CL, 31)), addr:$dst),
4721 (SAR16mCL addr:$dst)>;
4722 def : Pat<(store (sra (loadi32 addr:$dst), (and CL, 31)), addr:$dst),
4723 (SAR32mCL addr:$dst)>;
4725 // (anyext (setcc_carry)) -> (setcc_carry)
4726 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4728 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
4730 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
4733 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
4734 let AddedComplexity = 5 in { // Try this before the selecting to OR
4735 def : Pat<(or_is_add GR16:$src1, imm:$src2),
4736 (ADD16ri GR16:$src1, imm:$src2)>;
4737 def : Pat<(or_is_add GR32:$src1, imm:$src2),
4738 (ADD32ri GR32:$src1, imm:$src2)>;
4739 def : Pat<(or_is_add GR16:$src1, i16immSExt8:$src2),
4740 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4741 def : Pat<(or_is_add GR32:$src1, i32immSExt8:$src2),
4742 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4743 def : Pat<(or_is_add GR16:$src1, GR16:$src2),
4744 (ADD16rr GR16:$src1, GR16:$src2)>;
4745 def : Pat<(or_is_add GR32:$src1, GR32:$src2),
4746 (ADD32rr GR32:$src1, GR32:$src2)>;
4747 } // AddedComplexity
4749 //===----------------------------------------------------------------------===//
4750 // EFLAGS-defining Patterns
4751 //===----------------------------------------------------------------------===//
4754 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
4755 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
4756 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
4759 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
4760 (ADD8rm GR8:$src1, addr:$src2)>;
4761 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
4762 (ADD16rm GR16:$src1, addr:$src2)>;
4763 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
4764 (ADD32rm GR32:$src1, addr:$src2)>;
4767 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
4768 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
4769 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
4770 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
4771 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
4772 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
4773 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
4776 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
4777 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
4778 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
4781 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
4782 (SUB8rm GR8:$src1, addr:$src2)>;
4783 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
4784 (SUB16rm GR16:$src1, addr:$src2)>;
4785 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
4786 (SUB32rm GR32:$src1, addr:$src2)>;
4789 def : Pat<(sub GR8:$src1, imm:$src2),
4790 (SUB8ri GR8:$src1, imm:$src2)>;
4791 def : Pat<(sub GR16:$src1, imm:$src2),
4792 (SUB16ri GR16:$src1, imm:$src2)>;
4793 def : Pat<(sub GR32:$src1, imm:$src2),
4794 (SUB32ri GR32:$src1, imm:$src2)>;
4795 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
4796 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
4797 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
4798 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
4801 def : Pat<(mul GR16:$src1, GR16:$src2),
4802 (IMUL16rr GR16:$src1, GR16:$src2)>;
4803 def : Pat<(mul GR32:$src1, GR32:$src2),
4804 (IMUL32rr GR32:$src1, GR32:$src2)>;
4807 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
4808 (IMUL16rm GR16:$src1, addr:$src2)>;
4809 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
4810 (IMUL32rm GR32:$src1, addr:$src2)>;
4813 def : Pat<(mul GR16:$src1, imm:$src2),
4814 (IMUL16rri GR16:$src1, imm:$src2)>;
4815 def : Pat<(mul GR32:$src1, imm:$src2),
4816 (IMUL32rri GR32:$src1, imm:$src2)>;
4817 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
4818 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
4819 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
4820 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
4822 // reg = mul mem, imm
4823 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
4824 (IMUL16rmi addr:$src1, imm:$src2)>;
4825 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
4826 (IMUL32rmi addr:$src1, imm:$src2)>;
4827 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
4828 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
4829 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
4830 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
4832 // Optimize multiply by 2 with EFLAGS result.
4833 let AddedComplexity = 2 in {
4834 def : Pat<(X86smul_flag GR16:$src1, 2), (ADD16rr GR16:$src1, GR16:$src1)>;
4835 def : Pat<(X86smul_flag GR32:$src1, 2), (ADD32rr GR32:$src1, GR32:$src1)>;
4838 // Patterns for nodes that do not produce flags, for instructions that do.
4841 def : Pat<(add GR8:$src1 , 1), (INC8r GR8:$src1)>;
4842 def : Pat<(add GR16:$src1, 1), (INC16r GR16:$src1)>, Requires<[In32BitMode]>;
4843 def : Pat<(add GR32:$src1, 1), (INC32r GR32:$src1)>, Requires<[In32BitMode]>;
4846 def : Pat<(add GR8:$src1 , -1), (DEC8r GR8:$src1)>;
4847 def : Pat<(add GR16:$src1, -1), (DEC16r GR16:$src1)>, Requires<[In32BitMode]>;
4848 def : Pat<(add GR32:$src1, -1), (DEC32r GR32:$src1)>, Requires<[In32BitMode]>;
4851 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
4852 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
4853 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
4856 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
4857 (OR8rm GR8:$src1, addr:$src2)>;
4858 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
4859 (OR16rm GR16:$src1, addr:$src2)>;
4860 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
4861 (OR32rm GR32:$src1, addr:$src2)>;
4864 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
4865 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
4866 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
4867 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
4868 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4869 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
4870 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4873 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
4874 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
4875 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
4878 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
4879 (XOR8rm GR8:$src1, addr:$src2)>;
4880 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
4881 (XOR16rm GR16:$src1, addr:$src2)>;
4882 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
4883 (XOR32rm GR32:$src1, addr:$src2)>;
4886 def : Pat<(xor GR8:$src1, imm:$src2),
4887 (XOR8ri GR8:$src1, imm:$src2)>;
4888 def : Pat<(xor GR16:$src1, imm:$src2),
4889 (XOR16ri GR16:$src1, imm:$src2)>;
4890 def : Pat<(xor GR32:$src1, imm:$src2),
4891 (XOR32ri GR32:$src1, imm:$src2)>;
4892 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
4893 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4894 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
4895 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4898 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
4899 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
4900 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
4903 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
4904 (AND8rm GR8:$src1, addr:$src2)>;
4905 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
4906 (AND16rm GR16:$src1, addr:$src2)>;
4907 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
4908 (AND32rm GR32:$src1, addr:$src2)>;
4911 def : Pat<(and GR8:$src1, imm:$src2),
4912 (AND8ri GR8:$src1, imm:$src2)>;
4913 def : Pat<(and GR16:$src1, imm:$src2),
4914 (AND16ri GR16:$src1, imm:$src2)>;
4915 def : Pat<(and GR32:$src1, imm:$src2),
4916 (AND32ri GR32:$src1, imm:$src2)>;
4917 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
4918 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4919 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
4920 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4922 //===----------------------------------------------------------------------===//
4923 // Floating Point Stack Support
4924 //===----------------------------------------------------------------------===//
4926 include "X86InstrFPStack.td"
4928 //===----------------------------------------------------------------------===//
4930 //===----------------------------------------------------------------------===//
4932 include "X86Instr64bit.td"
4934 //===----------------------------------------------------------------------===//
4935 // SIMD support (SSE, MMX and AVX)
4936 //===----------------------------------------------------------------------===//
4938 include "X86InstrFragmentsSIMD.td"
4940 //===----------------------------------------------------------------------===//
4941 // XMM Floating point support (requires SSE / SSE2)
4942 //===----------------------------------------------------------------------===//
4944 include "X86InstrSSE.td"
4946 //===----------------------------------------------------------------------===//
4947 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
4948 //===----------------------------------------------------------------------===//
4950 include "X86InstrMMX.td"