1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
117 [SDNPHasChain,SDNPSideEffect]>;
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
146 [SDNPHasChain, SDNPSideEffect]>;
148 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
155 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
158 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
159 [SDNPHasChain, SDNPMayStore,
160 SDNPMayLoad, SDNPMemOperand]>;
161 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
162 [SDNPHasChain, SDNPMayStore,
163 SDNPMayLoad, SDNPMemOperand]>;
164 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
165 [SDNPHasChain, SDNPMayStore,
166 SDNPMayLoad, SDNPMemOperand]>;
167 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
177 [SDNPHasChain, SDNPMayStore,
178 SDNPMayLoad, SDNPMemOperand]>;
179 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
180 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
182 def X86vastart_save_xmm_regs :
183 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
184 SDT_X86VASTART_SAVE_XMM_REGS,
185 [SDNPHasChain, SDNPVariadic]>;
187 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
188 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
190 def X86callseq_start :
191 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
192 [SDNPHasChain, SDNPOutGlue]>;
194 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
195 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
197 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
198 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
201 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
202 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
203 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
204 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
207 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
208 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
210 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
211 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
213 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
214 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
216 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
217 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
219 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
222 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
223 SDTypeProfile<1, 1, [SDTCisInt<0>,
225 [SDNPHasChain, SDNPSideEffect]>;
226 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
227 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
228 [SDNPHasChain, SDNPSideEffect]>;
230 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
231 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
233 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
235 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
236 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
238 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
240 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
241 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
243 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
244 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
245 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
247 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
249 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
252 def X86blsi : SDNode<"X86ISD::BLSI", SDTIntUnaryOp>;
253 def X86blsmsk : SDNode<"X86ISD::BLSMSK", SDTIntUnaryOp>;
254 def X86blsr : SDNode<"X86ISD::BLSR", SDTIntUnaryOp>;
255 def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntShiftOp>;
256 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
258 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
260 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
261 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
263 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
266 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
267 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
269 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
270 [SDNPHasChain, SDNPOutGlue]>;
272 //===----------------------------------------------------------------------===//
273 // X86 Operand Definitions.
276 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
277 // the index operand of an address, to conform to x86 encoding restrictions.
278 def ptr_rc_nosp : PointerLikeRegClass<1>;
280 // *mem - Operand definitions for the funky X86 addressing mode operands.
282 def X86MemAsmOperand : AsmOperandClass {
285 def X86Mem8AsmOperand : AsmOperandClass {
286 let Name = "Mem8"; let RenderMethod = "addMemOperands";
288 def X86Mem16AsmOperand : AsmOperandClass {
289 let Name = "Mem16"; let RenderMethod = "addMemOperands";
291 def X86Mem32AsmOperand : AsmOperandClass {
292 let Name = "Mem32"; let RenderMethod = "addMemOperands";
294 def X86Mem64AsmOperand : AsmOperandClass {
295 let Name = "Mem64"; let RenderMethod = "addMemOperands";
297 def X86Mem80AsmOperand : AsmOperandClass {
298 let Name = "Mem80"; let RenderMethod = "addMemOperands";
300 def X86Mem128AsmOperand : AsmOperandClass {
301 let Name = "Mem128"; let RenderMethod = "addMemOperands";
303 def X86Mem256AsmOperand : AsmOperandClass {
304 let Name = "Mem256"; let RenderMethod = "addMemOperands";
306 def X86Mem512AsmOperand : AsmOperandClass {
307 let Name = "Mem512"; let RenderMethod = "addMemOperands";
310 // Gather mem operands
311 def X86MemVX32Operand : AsmOperandClass {
312 let Name = "MemVX32"; let RenderMethod = "addMemOperands";
314 def X86MemVY32Operand : AsmOperandClass {
315 let Name = "MemVY32"; let RenderMethod = "addMemOperands";
317 def X86MemVZ32Operand : AsmOperandClass {
318 let Name = "MemVZ32"; let RenderMethod = "addMemOperands";
320 def X86MemVX64Operand : AsmOperandClass {
321 let Name = "MemVX64"; let RenderMethod = "addMemOperands";
323 def X86MemVY64Operand : AsmOperandClass {
324 let Name = "MemVY64"; let RenderMethod = "addMemOperands";
326 def X86MemVZ64Operand : AsmOperandClass {
327 let Name = "MemVZ64"; let RenderMethod = "addMemOperands";
330 def X86AbsMemAsmOperand : AsmOperandClass {
332 let SuperClasses = [X86MemAsmOperand];
334 class X86MemOperand<string printMethod> : Operand<iPTR> {
335 let PrintMethod = printMethod;
336 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
337 let ParserMatchClass = X86MemAsmOperand;
340 let OperandType = "OPERAND_MEMORY" in {
341 def opaque32mem : X86MemOperand<"printopaquemem">;
342 def opaque48mem : X86MemOperand<"printopaquemem">;
343 def opaque80mem : X86MemOperand<"printopaquemem">;
344 def opaque512mem : X86MemOperand<"printopaquemem">;
346 def i8mem : X86MemOperand<"printi8mem"> {
347 let ParserMatchClass = X86Mem8AsmOperand; }
348 def i16mem : X86MemOperand<"printi16mem"> {
349 let ParserMatchClass = X86Mem16AsmOperand; }
350 def i32mem : X86MemOperand<"printi32mem"> {
351 let ParserMatchClass = X86Mem32AsmOperand; }
352 def i64mem : X86MemOperand<"printi64mem"> {
353 let ParserMatchClass = X86Mem64AsmOperand; }
354 def i128mem : X86MemOperand<"printi128mem"> {
355 let ParserMatchClass = X86Mem128AsmOperand; }
356 def i256mem : X86MemOperand<"printi256mem"> {
357 let ParserMatchClass = X86Mem256AsmOperand; }
358 def i512mem : X86MemOperand<"printi512mem"> {
359 let ParserMatchClass = X86Mem512AsmOperand; }
360 def f32mem : X86MemOperand<"printf32mem"> {
361 let ParserMatchClass = X86Mem32AsmOperand; }
362 def f64mem : X86MemOperand<"printf64mem"> {
363 let ParserMatchClass = X86Mem64AsmOperand; }
364 def f80mem : X86MemOperand<"printf80mem"> {
365 let ParserMatchClass = X86Mem80AsmOperand; }
366 def f128mem : X86MemOperand<"printf128mem"> {
367 let ParserMatchClass = X86Mem128AsmOperand; }
368 def f256mem : X86MemOperand<"printf256mem">{
369 let ParserMatchClass = X86Mem256AsmOperand; }
370 def f512mem : X86MemOperand<"printf512mem">{
371 let ParserMatchClass = X86Mem512AsmOperand; }
372 def v512mem : Operand<iPTR> {
373 let PrintMethod = "printf512mem";
374 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
375 let ParserMatchClass = X86Mem512AsmOperand; }
377 // Gather mem operands
378 def vx32mem : X86MemOperand<"printi32mem">{
379 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
380 let ParserMatchClass = X86MemVX32Operand; }
381 def vy32mem : X86MemOperand<"printi32mem">{
382 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
383 let ParserMatchClass = X86MemVY32Operand; }
384 def vx64mem : X86MemOperand<"printi64mem">{
385 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
386 let ParserMatchClass = X86MemVX64Operand; }
387 def vy64mem : X86MemOperand<"printi64mem">{
388 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
389 let ParserMatchClass = X86MemVY64Operand; }
390 def vy64xmem : X86MemOperand<"printi64mem">{
391 let MIOperandInfo = (ops ptr_rc, i8imm, VR256X, i32imm, i8imm);
392 let ParserMatchClass = X86MemVY64Operand; }
393 def vz32mem : X86MemOperand<"printi32mem">{
394 let MIOperandInfo = (ops ptr_rc, i16imm, VR512, i32imm, i8imm);
395 let ParserMatchClass = X86MemVZ32Operand; }
396 def vz64mem : X86MemOperand<"printi64mem">{
397 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
398 let ParserMatchClass = X86MemVZ64Operand; }
401 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
402 // plain GR64, so that it doesn't potentially require a REX prefix.
403 def i8mem_NOREX : Operand<i64> {
404 let PrintMethod = "printi8mem";
405 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
406 let ParserMatchClass = X86Mem8AsmOperand;
407 let OperandType = "OPERAND_MEMORY";
410 // GPRs available for tailcall.
411 // It represents GR32_TC, GR64_TC or GR64_TCW64.
412 def ptr_rc_tailcall : PointerLikeRegClass<2>;
414 // Special i32mem for addresses of load folding tail calls. These are not
415 // allowed to use callee-saved registers since they must be scheduled
416 // after callee-saved register are popped.
417 def i32mem_TC : Operand<i32> {
418 let PrintMethod = "printi32mem";
419 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
421 let ParserMatchClass = X86Mem32AsmOperand;
422 let OperandType = "OPERAND_MEMORY";
425 // Special i64mem for addresses of load folding tail calls. These are not
426 // allowed to use callee-saved registers since they must be scheduled
427 // after callee-saved register are popped.
428 def i64mem_TC : Operand<i64> {
429 let PrintMethod = "printi64mem";
430 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
431 ptr_rc_tailcall, i32imm, i8imm);
432 let ParserMatchClass = X86Mem64AsmOperand;
433 let OperandType = "OPERAND_MEMORY";
436 let OperandType = "OPERAND_PCREL",
437 ParserMatchClass = X86AbsMemAsmOperand,
438 PrintMethod = "printPCRelImm" in {
439 def i32imm_pcrel : Operand<i32>;
440 def i16imm_pcrel : Operand<i16>;
442 // Branch targets have OtherVT type and print as pc-relative values.
443 def brtarget : Operand<OtherVT>;
444 def brtarget8 : Operand<OtherVT>;
448 def X86SrcIdx8Operand : AsmOperandClass {
449 let Name = "SrcIdx8";
450 let RenderMethod = "addSrcIdxOperands";
451 let SuperClasses = [X86Mem8AsmOperand];
453 def X86SrcIdx16Operand : AsmOperandClass {
454 let Name = "SrcIdx16";
455 let RenderMethod = "addSrcIdxOperands";
456 let SuperClasses = [X86Mem16AsmOperand];
458 def X86SrcIdx32Operand : AsmOperandClass {
459 let Name = "SrcIdx32";
460 let RenderMethod = "addSrcIdxOperands";
461 let SuperClasses = [X86Mem32AsmOperand];
463 def X86SrcIdx64Operand : AsmOperandClass {
464 let Name = "SrcIdx64";
465 let RenderMethod = "addSrcIdxOperands";
466 let SuperClasses = [X86Mem64AsmOperand];
468 def X86DstIdx8Operand : AsmOperandClass {
469 let Name = "DstIdx8";
470 let RenderMethod = "addDstIdxOperands";
471 let SuperClasses = [X86Mem8AsmOperand];
473 def X86DstIdx16Operand : AsmOperandClass {
474 let Name = "DstIdx16";
475 let RenderMethod = "addDstIdxOperands";
476 let SuperClasses = [X86Mem16AsmOperand];
478 def X86DstIdx32Operand : AsmOperandClass {
479 let Name = "DstIdx32";
480 let RenderMethod = "addDstIdxOperands";
481 let SuperClasses = [X86Mem32AsmOperand];
483 def X86DstIdx64Operand : AsmOperandClass {
484 let Name = "DstIdx64";
485 let RenderMethod = "addDstIdxOperands";
486 let SuperClasses = [X86Mem64AsmOperand];
488 def X86MemOffs8AsmOperand : AsmOperandClass {
489 let Name = "MemOffs8";
490 let RenderMethod = "addMemOffsOperands";
491 let SuperClasses = [X86Mem8AsmOperand];
493 def X86MemOffs16AsmOperand : AsmOperandClass {
494 let Name = "MemOffs16";
495 let RenderMethod = "addMemOffsOperands";
496 let SuperClasses = [X86Mem16AsmOperand];
498 def X86MemOffs32AsmOperand : AsmOperandClass {
499 let Name = "MemOffs32";
500 let RenderMethod = "addMemOffsOperands";
501 let SuperClasses = [X86Mem32AsmOperand];
503 def X86MemOffs64AsmOperand : AsmOperandClass {
504 let Name = "MemOffs64";
505 let RenderMethod = "addMemOffsOperands";
506 let SuperClasses = [X86Mem64AsmOperand];
508 let OperandType = "OPERAND_MEMORY" in {
509 def srcidx8 : Operand<iPTR> {
510 let ParserMatchClass = X86SrcIdx8Operand;
511 let MIOperandInfo = (ops ptr_rc, i8imm);
512 let PrintMethod = "printSrcIdx8"; }
513 def srcidx16 : Operand<iPTR> {
514 let ParserMatchClass = X86SrcIdx16Operand;
515 let MIOperandInfo = (ops ptr_rc, i8imm);
516 let PrintMethod = "printSrcIdx16"; }
517 def srcidx32 : Operand<iPTR> {
518 let ParserMatchClass = X86SrcIdx32Operand;
519 let MIOperandInfo = (ops ptr_rc, i8imm);
520 let PrintMethod = "printSrcIdx32"; }
521 def srcidx64 : Operand<iPTR> {
522 let ParserMatchClass = X86SrcIdx64Operand;
523 let MIOperandInfo = (ops ptr_rc, i8imm);
524 let PrintMethod = "printSrcIdx64"; }
525 def dstidx8 : Operand<iPTR> {
526 let ParserMatchClass = X86DstIdx8Operand;
527 let MIOperandInfo = (ops ptr_rc);
528 let PrintMethod = "printDstIdx8"; }
529 def dstidx16 : Operand<iPTR> {
530 let ParserMatchClass = X86DstIdx16Operand;
531 let MIOperandInfo = (ops ptr_rc);
532 let PrintMethod = "printDstIdx16"; }
533 def dstidx32 : Operand<iPTR> {
534 let ParserMatchClass = X86DstIdx32Operand;
535 let MIOperandInfo = (ops ptr_rc);
536 let PrintMethod = "printDstIdx32"; }
537 def dstidx64 : Operand<iPTR> {
538 let ParserMatchClass = X86DstIdx64Operand;
539 let MIOperandInfo = (ops ptr_rc);
540 let PrintMethod = "printDstIdx64"; }
541 def offset8 : Operand<iPTR> {
542 let ParserMatchClass = X86MemOffs8AsmOperand;
543 let MIOperandInfo = (ops i64imm, i8imm);
544 let PrintMethod = "printMemOffs8"; }
545 def offset16 : Operand<iPTR> {
546 let ParserMatchClass = X86MemOffs16AsmOperand;
547 let MIOperandInfo = (ops i64imm, i8imm);
548 let PrintMethod = "printMemOffs16"; }
549 def offset32 : Operand<iPTR> {
550 let ParserMatchClass = X86MemOffs32AsmOperand;
551 let MIOperandInfo = (ops i64imm, i8imm);
552 let PrintMethod = "printMemOffs32"; }
553 def offset64 : Operand<iPTR> {
554 let ParserMatchClass = X86MemOffs64AsmOperand;
555 let MIOperandInfo = (ops i64imm, i8imm);
556 let PrintMethod = "printMemOffs64"; }
560 def SSECC : Operand<i8> {
561 let PrintMethod = "printSSECC";
562 let OperandType = "OPERAND_IMMEDIATE";
565 def AVXCC : Operand<i8> {
566 let PrintMethod = "printAVXCC";
567 let OperandType = "OPERAND_IMMEDIATE";
570 class ImmSExtAsmOperandClass : AsmOperandClass {
571 let SuperClasses = [ImmAsmOperand];
572 let RenderMethod = "addImmOperands";
575 class ImmZExtAsmOperandClass : AsmOperandClass {
576 let SuperClasses = [ImmAsmOperand];
577 let RenderMethod = "addImmOperands";
580 def X86GR32orGR64AsmOperand : AsmOperandClass {
581 let Name = "GR32orGR64";
584 def GR32orGR64 : RegisterOperand<GR32> {
585 let ParserMatchClass = X86GR32orGR64AsmOperand;
588 def AVX512RC : Operand<i32> {
589 let PrintMethod = "printRoundingControl";
590 let OperandType = "OPERAND_IMMEDIATE";
592 // Sign-extended immediate classes. We don't need to define the full lattice
593 // here because there is no instruction with an ambiguity between ImmSExti64i32
596 // The strange ranges come from the fact that the assembler always works with
597 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
598 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
601 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
602 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
603 let Name = "ImmSExti64i32";
606 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
607 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
608 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
609 let Name = "ImmSExti16i8";
610 let SuperClasses = [ImmSExti64i32AsmOperand];
613 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
614 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
615 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
616 let Name = "ImmSExti32i8";
620 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {
621 let Name = "ImmZExtu32u8";
626 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
627 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
628 let Name = "ImmSExti64i8";
629 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
630 ImmSExti64i32AsmOperand];
633 // A couple of more descriptive operand definitions.
634 // 16-bits but only 8 bits are significant.
635 def i16i8imm : Operand<i16> {
636 let ParserMatchClass = ImmSExti16i8AsmOperand;
637 let OperandType = "OPERAND_IMMEDIATE";
639 // 32-bits but only 8 bits are significant.
640 def i32i8imm : Operand<i32> {
641 let ParserMatchClass = ImmSExti32i8AsmOperand;
642 let OperandType = "OPERAND_IMMEDIATE";
644 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned.
645 def u32u8imm : Operand<i32> {
646 let ParserMatchClass = ImmZExtu32u8AsmOperand;
647 let OperandType = "OPERAND_IMMEDIATE";
650 // 64-bits but only 32 bits are significant.
651 def i64i32imm : Operand<i64> {
652 let ParserMatchClass = ImmSExti64i32AsmOperand;
653 let OperandType = "OPERAND_IMMEDIATE";
656 // 64-bits but only 32 bits are significant, and those bits are treated as being
658 def i64i32imm_pcrel : Operand<i64> {
659 let PrintMethod = "printPCRelImm";
660 let ParserMatchClass = X86AbsMemAsmOperand;
661 let OperandType = "OPERAND_PCREL";
664 // 64-bits but only 8 bits are significant.
665 def i64i8imm : Operand<i64> {
666 let ParserMatchClass = ImmSExti64i8AsmOperand;
667 let OperandType = "OPERAND_IMMEDIATE";
670 def lea64_32mem : Operand<i32> {
671 let PrintMethod = "printi32mem";
672 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
673 let ParserMatchClass = X86MemAsmOperand;
676 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
677 def lea64mem : Operand<i64> {
678 let PrintMethod = "printi64mem";
679 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
680 let ParserMatchClass = X86MemAsmOperand;
684 //===----------------------------------------------------------------------===//
685 // X86 Complex Pattern Definitions.
688 // Define X86 specific addressing mode.
689 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
690 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
691 [add, sub, mul, X86mul_imm, shl, or, frameindex],
693 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
694 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
695 [add, sub, mul, X86mul_imm, shl, or,
696 frameindex, X86WrapperRIP],
699 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
700 [tglobaltlsaddr], []>;
702 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
703 [tglobaltlsaddr], []>;
705 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
706 [add, sub, mul, X86mul_imm, shl, or, frameindex,
709 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
710 [tglobaltlsaddr], []>;
712 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
713 [tglobaltlsaddr], []>;
715 //===----------------------------------------------------------------------===//
716 // X86 Instruction Predicate Definitions.
717 def HasCMov : Predicate<"Subtarget->hasCMov()">;
718 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
720 def HasMMX : Predicate<"Subtarget->hasMMX()">;
721 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
722 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
723 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
724 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
725 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
726 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
727 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
728 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
729 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
730 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
731 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
732 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
733 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
734 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
735 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
736 def HasAVX : Predicate<"Subtarget->hasAVX()">;
737 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
738 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
739 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
740 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
741 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
742 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
743 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
744 def HasCDI : Predicate<"Subtarget->hasCDI()">;
745 def HasPFI : Predicate<"Subtarget->hasPFI()">;
746 def HasERI : Predicate<"Subtarget->hasERI()">;
748 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
749 def HasAES : Predicate<"Subtarget->hasAES()">;
750 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
751 def HasFMA : Predicate<"Subtarget->hasFMA()">;
752 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
753 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
754 def HasXOP : Predicate<"Subtarget->hasXOP()">;
755 def HasTBM : Predicate<"Subtarget->hasTBM()">;
756 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
757 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
758 def HasF16C : Predicate<"Subtarget->hasF16C()">;
759 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
760 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
761 def HasBMI : Predicate<"Subtarget->hasBMI()">;
762 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
763 def HasRTM : Predicate<"Subtarget->hasRTM()">;
764 def HasHLE : Predicate<"Subtarget->hasHLE()">;
765 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
766 def HasADX : Predicate<"Subtarget->hasADX()">;
767 def HasSHA : Predicate<"Subtarget->hasSHA()">;
768 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
769 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
770 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
771 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
772 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
773 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
774 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
775 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
776 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
777 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
778 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
779 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
780 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
781 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
782 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
783 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
784 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
785 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
786 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
787 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
788 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
789 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
790 "TM.getCodeModel() != CodeModel::Kernel">;
791 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
792 "TM.getCodeModel() == CodeModel::Kernel">;
793 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
794 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
795 def OptForSize : Predicate<"OptForSize">;
796 def OptForSpeed : Predicate<"!OptForSize">;
797 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
798 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
799 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
801 //===----------------------------------------------------------------------===//
802 // X86 Instruction Format Definitions.
805 include "X86InstrFormats.td"
807 //===----------------------------------------------------------------------===//
808 // Pattern fragments.
811 // X86 specific condition code. These correspond to CondCode in
812 // X86InstrInfo.h. They must be kept in synch.
813 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
814 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
815 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
816 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
817 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
818 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
819 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
820 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
821 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
822 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
823 def X86_COND_NO : PatLeaf<(i8 10)>;
824 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
825 def X86_COND_NS : PatLeaf<(i8 12)>;
826 def X86_COND_O : PatLeaf<(i8 13)>;
827 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
828 def X86_COND_S : PatLeaf<(i8 15)>;
830 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
831 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
832 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
833 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
836 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
839 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
841 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
843 def i64immZExt32SExt8 : ImmLeaf<i64, [{
844 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
847 // Helper fragments for loads.
848 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
849 // known to be 32-bit aligned or better. Ditto for i8 to i16.
850 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
851 LoadSDNode *LD = cast<LoadSDNode>(N);
852 ISD::LoadExtType ExtType = LD->getExtensionType();
853 if (ExtType == ISD::NON_EXTLOAD)
855 if (ExtType == ISD::EXTLOAD)
856 return LD->getAlignment() >= 2 && !LD->isVolatile();
860 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
861 LoadSDNode *LD = cast<LoadSDNode>(N);
862 ISD::LoadExtType ExtType = LD->getExtensionType();
863 if (ExtType == ISD::EXTLOAD)
864 return LD->getAlignment() >= 2 && !LD->isVolatile();
868 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
869 LoadSDNode *LD = cast<LoadSDNode>(N);
870 ISD::LoadExtType ExtType = LD->getExtensionType();
871 if (ExtType == ISD::NON_EXTLOAD)
873 if (ExtType == ISD::EXTLOAD)
874 return LD->getAlignment() >= 4 && !LD->isVolatile();
878 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
879 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
880 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
881 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
882 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
884 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
885 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
886 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
887 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
888 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
889 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
891 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
892 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
893 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
894 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
895 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
896 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
897 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
898 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
899 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
900 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
902 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
903 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
904 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
905 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
906 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
907 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
908 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
909 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
910 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
911 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
914 // An 'and' node with a single use.
915 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
916 return N->hasOneUse();
918 // An 'srl' node with a single use.
919 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
920 return N->hasOneUse();
922 // An 'trunc' node with a single use.
923 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
924 return N->hasOneUse();
927 //===----------------------------------------------------------------------===//
932 let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
933 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
934 def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
935 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
936 def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
937 "nop{l}\t$zero", [], IIC_NOP>, TB;
941 // Constructing a stack frame.
942 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
943 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
945 let SchedRW = [WriteALU] in {
946 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
947 def LEAVE : I<0xC9, RawFrm,
948 (outs), (ins), "leave", [], IIC_LEAVE>,
949 Requires<[Not64BitMode]>;
951 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in
952 def LEAVE64 : I<0xC9, RawFrm,
953 (outs), (ins), "leave", [], IIC_LEAVE>,
954 Requires<[In64BitMode]>;
957 //===----------------------------------------------------------------------===//
958 // Miscellaneous Instructions.
961 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
962 let mayLoad = 1, SchedRW = [WriteLoad] in {
963 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
964 IIC_POP_REG16>, OpSize;
965 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
966 IIC_POP_REG>, OpSize16, Requires<[Not64BitMode]>;
967 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
968 IIC_POP_REG>, OpSize;
969 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
970 IIC_POP_MEM>, OpSize;
971 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
972 IIC_POP_REG>, OpSize16, Requires<[Not64BitMode]>;
973 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
974 IIC_POP_MEM>, Requires<[Not64BitMode]>;
976 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
977 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
978 OpSize16, Requires<[Not64BitMode]>;
979 } // mayLoad, SchedRW
981 let mayStore = 1, SchedRW = [WriteStore] in {
982 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
983 IIC_PUSH_REG>, OpSize;
984 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
985 IIC_PUSH_REG>, OpSize16, Requires<[Not64BitMode]>;
986 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
987 IIC_PUSH_REG>, OpSize;
988 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
989 IIC_PUSH_MEM>, OpSize;
990 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
991 IIC_PUSH_REG>, OpSize16, Requires<[Not64BitMode]>;
992 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
993 IIC_PUSH_MEM>, OpSize16, Requires<[Not64BitMode]>;
995 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
996 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
997 Requires<[Not64BitMode]>;
998 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
999 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1000 Requires<[Not64BitMode]>;
1001 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1002 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
1003 Requires<[Not64BitMode]>;
1004 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1005 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1006 Requires<[Not64BitMode]>;
1008 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
1010 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
1011 OpSize16, Requires<[Not64BitMode]>;
1013 } // mayStore, SchedRW
1016 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in {
1017 let mayLoad = 1, SchedRW = [WriteLoad] in {
1018 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1019 IIC_POP_REG>, Requires<[In64BitMode]>;
1020 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1021 IIC_POP_REG>, Requires<[In64BitMode]>;
1022 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
1023 IIC_POP_MEM>, Requires<[In64BitMode]>;
1024 } // mayLoad, SchedRW
1025 let mayStore = 1, SchedRW = [WriteStore] in {
1026 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1027 IIC_PUSH_REG>, Requires<[In64BitMode]>;
1028 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1029 IIC_PUSH_REG>, Requires<[In64BitMode]>;
1030 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1031 IIC_PUSH_MEM>, Requires<[In64BitMode]>;
1032 } // mayStore, SchedRW
1035 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1,
1036 SchedRW = [WriteStore] in {
1037 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1038 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1039 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1040 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
1041 Requires<[In64BitMode]>;
1042 def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1043 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1046 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
1047 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1048 Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1049 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
1050 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1051 Requires<[In64BitMode]>, Sched<[WriteStore]>;
1053 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1054 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
1055 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1056 OpSize16, Requires<[Not64BitMode]>;
1057 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1058 OpSize, Requires<[Not64BitMode]>;
1060 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1061 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
1062 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1063 OpSize16, Requires<[Not64BitMode]>;
1064 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1065 OpSize, Requires<[Not64BitMode]>;
1068 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1069 // GR32 = bswap GR32
1070 def BSWAP32r : I<0xC8, AddRegFrm,
1071 (outs GR32:$dst), (ins GR32:$src),
1073 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize16, TB;
1075 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1077 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1078 } // Constraints = "$src = $dst", SchedRW
1080 // Bit scan instructions.
1081 let Defs = [EFLAGS] in {
1082 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1083 "bsf{w}\t{$src, $dst|$dst, $src}",
1084 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1085 IIC_BIT_SCAN_REG>, TB, OpSize, Sched<[WriteShift]>;
1086 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1087 "bsf{w}\t{$src, $dst|$dst, $src}",
1088 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1089 IIC_BIT_SCAN_MEM>, TB, OpSize, Sched<[WriteShiftLd]>;
1090 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1091 "bsf{l}\t{$src, $dst|$dst, $src}",
1092 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1093 IIC_BIT_SCAN_REG>, TB, OpSize16,
1094 Sched<[WriteShift]>;
1095 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1096 "bsf{l}\t{$src, $dst|$dst, $src}",
1097 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1098 IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
1099 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1100 "bsf{q}\t{$src, $dst|$dst, $src}",
1101 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1102 IIC_BIT_SCAN_REG>, TB, Sched<[WriteShift]>;
1103 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1104 "bsf{q}\t{$src, $dst|$dst, $src}",
1105 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1106 IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;
1108 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1109 "bsr{w}\t{$src, $dst|$dst, $src}",
1110 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1112 TB, OpSize, Sched<[WriteShift]>;
1113 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1114 "bsr{w}\t{$src, $dst|$dst, $src}",
1115 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1116 IIC_BIT_SCAN_MEM>, TB,
1117 OpSize, Sched<[WriteShiftLd]>;
1118 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1119 "bsr{l}\t{$src, $dst|$dst, $src}",
1120 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1121 IIC_BIT_SCAN_REG>, TB, OpSize16,
1122 Sched<[WriteShift]>;
1123 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1124 "bsr{l}\t{$src, $dst|$dst, $src}",
1125 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1126 IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
1127 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1128 "bsr{q}\t{$src, $dst|$dst, $src}",
1129 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BIT_SCAN_REG>, TB,
1130 Sched<[WriteShift]>;
1131 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1132 "bsr{q}\t{$src, $dst|$dst, $src}",
1133 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1134 IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;
1135 } // Defs = [EFLAGS]
1137 let SchedRW = [WriteMicrocoded] in {
1138 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1139 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1140 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1141 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1142 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1143 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize;
1144 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1145 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1146 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1147 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1150 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1151 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1152 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1153 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1154 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1155 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1156 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize;
1157 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1158 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1159 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize16;
1160 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1161 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1162 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1164 def SCAS8 : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1165 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1166 def SCAS16 : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1167 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize;
1168 def SCAS32 : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1169 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize16;
1170 def SCAS64 : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1171 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1173 def CMPS8 : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1174 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1175 def CMPS16 : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1176 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize;
1177 def CMPS32 : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1178 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1179 def CMPS64 : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1180 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1183 //===----------------------------------------------------------------------===//
1184 // Move Instructions.
1186 let SchedRW = [WriteMove] in {
1187 let neverHasSideEffects = 1 in {
1188 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1189 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1190 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1191 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1192 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1193 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1194 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1195 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1198 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1199 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1200 "mov{b}\t{$src, $dst|$dst, $src}",
1201 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1202 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1203 "mov{w}\t{$src, $dst|$dst, $src}",
1204 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
1205 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1206 "mov{l}\t{$src, $dst|$dst, $src}",
1207 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize16;
1208 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1209 "movabs{q}\t{$src, $dst|$dst, $src}",
1210 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1211 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1212 "mov{q}\t{$src, $dst|$dst, $src}",
1213 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1217 let SchedRW = [WriteStore] in {
1218 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1219 "mov{b}\t{$src, $dst|$dst, $src}",
1220 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1221 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1222 "mov{w}\t{$src, $dst|$dst, $src}",
1223 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
1224 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1225 "mov{l}\t{$src, $dst|$dst, $src}",
1226 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1227 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1228 "mov{q}\t{$src, $dst|$dst, $src}",
1229 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1232 let hasSideEffects = 0 in {
1234 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a
1235 /// 32-bit offset from the segment base. These are only valid in x86-32 mode.
1236 let SchedRW = [WriteALU] in {
1237 let mayLoad = 1 in {
1238 def MOV8o8a : Ii32 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
1239 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1240 Requires<[In32BitMode]>;
1241 def MOV16o16a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1242 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize,
1243 Requires<[In32BitMode]>;
1244 def MOV32o32a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
1245 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1246 OpSize16, Requires<[In32BitMode]>;
1248 def MOV8o8a_16 : Ii16 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
1249 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1250 AdSize, Requires<[In16BitMode]>;
1251 def MOV16o16a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1252 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize,
1253 AdSize, Requires<[In16BitMode]>;
1254 def MOV32o32a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
1255 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1256 AdSize, OpSize16, Requires<[In16BitMode]>;
1258 let mayStore = 1 in {
1259 def MOV8ao8 : Ii32 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
1260 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
1261 Requires<[In32BitMode]>;
1262 def MOV16ao16 : Ii32 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1263 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize,
1264 Requires<[In32BitMode]>;
1265 def MOV32ao32 : Ii32 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
1266 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1267 OpSize16, Requires<[In32BitMode]>;
1269 def MOV8ao8_16 : Ii16 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
1270 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
1271 AdSize, Requires<[In16BitMode]>;
1272 def MOV16ao16_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1273 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize,
1274 AdSize, Requires<[In16BitMode]>;
1275 def MOV32ao32_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
1276 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1277 OpSize16, AdSize, Requires<[In16BitMode]>;
1281 // These forms all have full 64-bit absolute addresses in their instructions
1282 // and use the movabs mnemonic to indicate this specific form.
1283 let mayLoad = 1 in {
1284 def MOV64o8a : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
1285 "movabs{b}\t{$src, %al|al, $src}", []>,
1286 Requires<[In64BitMode]>;
1287 def MOV64o16a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
1288 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize,
1289 Requires<[In64BitMode]>;
1290 def MOV64o32a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
1291 "movabs{l}\t{$src, %eax|eax, $src}", []>,
1292 Requires<[In64BitMode]>;
1293 def MOV64o64a : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64:$src),
1294 "movabs{q}\t{$src, %rax|rax, $src}", []>,
1295 Requires<[In64BitMode]>;
1298 let mayStore = 1 in {
1299 def MOV64ao8 : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
1300 "movabs{b}\t{%al, $dst|$dst, al}", []>,
1301 Requires<[In64BitMode]>;
1302 def MOV64ao16 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
1303 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize,
1304 Requires<[In64BitMode]>;
1305 def MOV64ao32 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
1306 "movabs{l}\t{%eax, $dst|$dst, eax}", []>,
1307 Requires<[In64BitMode]>;
1308 def MOV64ao64 : RIi64<0xA3, RawFrmMemOffs, (outs offset64:$dst), (ins),
1309 "movabs{q}\t{%rax, $dst|$dst, rax}", []>,
1310 Requires<[In64BitMode]>;
1312 } // hasSideEffects = 0
1314 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1315 SchedRW = [WriteMove] in {
1316 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1317 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1318 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1319 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
1320 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1321 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1322 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1323 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1326 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1327 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1328 "mov{b}\t{$src, $dst|$dst, $src}",
1329 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1330 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1331 "mov{w}\t{$src, $dst|$dst, $src}",
1332 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
1333 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1334 "mov{l}\t{$src, $dst|$dst, $src}",
1335 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize16;
1336 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1337 "mov{q}\t{$src, $dst|$dst, $src}",
1338 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1341 let SchedRW = [WriteStore] in {
1342 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1343 "mov{b}\t{$src, $dst|$dst, $src}",
1344 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1345 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1346 "mov{w}\t{$src, $dst|$dst, $src}",
1347 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
1348 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1349 "mov{l}\t{$src, $dst|$dst, $src}",
1350 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1351 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1352 "mov{q}\t{$src, $dst|$dst, $src}",
1353 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1356 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1357 // that they can be used for copying and storing h registers, which can't be
1358 // encoded when a REX prefix is present.
1359 let isCodeGenOnly = 1 in {
1360 let neverHasSideEffects = 1 in
1361 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1362 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1363 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1365 let mayStore = 1, neverHasSideEffects = 1 in
1366 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1367 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1368 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1369 IIC_MOV_MEM>, Sched<[WriteStore]>;
1370 let mayLoad = 1, neverHasSideEffects = 1,
1371 canFoldAsLoad = 1, isReMaterializable = 1 in
1372 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1373 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1374 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1375 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1379 // Condition code ops, incl. set if equal/not equal/...
1380 let SchedRW = [WriteALU] in {
1381 let Defs = [EFLAGS], Uses = [AH] in
1382 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1383 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1384 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
1385 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1386 IIC_AHF>; // AH = flags
1389 //===----------------------------------------------------------------------===//
1390 // Bit tests instructions: BT, BTS, BTR, BTC.
1392 let Defs = [EFLAGS] in {
1393 let SchedRW = [WriteALU] in {
1394 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1395 "bt{w}\t{$src2, $src1|$src1, $src2}",
1396 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1398 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1399 "bt{l}\t{$src2, $src1|$src1, $src2}",
1400 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1402 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1403 "bt{q}\t{$src2, $src1|$src1, $src2}",
1404 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1407 // Unlike with the register+register form, the memory+register form of the
1408 // bt instruction does not ignore the high bits of the index. From ISel's
1409 // perspective, this is pretty bizarre. Make these instructions disassembly
1412 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1413 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1414 "bt{w}\t{$src2, $src1|$src1, $src2}",
1415 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1416 // (implicit EFLAGS)]
1418 >, OpSize, TB, Requires<[FastBTMem]>;
1419 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1420 "bt{l}\t{$src2, $src1|$src1, $src2}",
1421 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1422 // (implicit EFLAGS)]
1424 >, OpSize16, TB, Requires<[FastBTMem]>;
1425 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1426 "bt{q}\t{$src2, $src1|$src1, $src2}",
1427 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1428 // (implicit EFLAGS)]
1433 let SchedRW = [WriteALU] in {
1434 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1435 "bt{w}\t{$src2, $src1|$src1, $src2}",
1436 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1437 IIC_BT_RI>, OpSize, TB;
1438 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1439 "bt{l}\t{$src2, $src1|$src1, $src2}",
1440 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1441 IIC_BT_RI>, OpSize16, TB;
1442 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1443 "bt{q}\t{$src2, $src1|$src1, $src2}",
1444 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1448 // Note that these instructions don't need FastBTMem because that
1449 // only applies when the other operand is in a register. When it's
1450 // an immediate, bt is still fast.
1451 let SchedRW = [WriteALU] in {
1452 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1453 "bt{w}\t{$src2, $src1|$src1, $src2}",
1454 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1455 ], IIC_BT_MI>, OpSize, TB;
1456 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1457 "bt{l}\t{$src2, $src1|$src1, $src2}",
1458 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1459 ], IIC_BT_MI>, OpSize16, TB;
1460 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1461 "bt{q}\t{$src2, $src1|$src1, $src2}",
1462 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1463 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1466 let hasSideEffects = 0 in {
1467 let SchedRW = [WriteALU] in {
1468 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1469 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1471 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1472 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1474 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1475 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1478 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1479 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1480 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1482 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1483 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1485 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1486 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1489 let SchedRW = [WriteALU] in {
1490 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1491 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1493 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1494 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1496 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1497 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1500 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1501 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1502 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1504 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1505 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1507 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1508 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1511 let SchedRW = [WriteALU] in {
1512 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1513 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1515 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1516 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1518 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1519 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1522 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1523 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1524 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1526 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1527 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1529 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1530 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1533 let SchedRW = [WriteALU] in {
1534 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1535 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1537 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1538 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1540 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1541 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1544 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1545 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1546 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1548 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1549 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1551 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1552 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1555 let SchedRW = [WriteALU] in {
1556 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1557 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1559 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1560 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1562 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1563 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1566 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1567 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1568 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1570 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1571 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1573 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1574 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1577 let SchedRW = [WriteALU] in {
1578 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1579 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1581 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1582 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1584 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1585 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1588 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1589 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1590 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1592 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1593 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1595 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1596 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1598 } // hasSideEffects = 0
1599 } // Defs = [EFLAGS]
1602 //===----------------------------------------------------------------------===//
1606 // Atomic swap. These are just normal xchg instructions. But since a memory
1607 // operand is referenced, the atomicity is ensured.
1608 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1609 InstrItinClass itin> {
1610 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1611 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1612 (ins GR8:$val, i8mem:$ptr),
1613 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1616 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1618 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1619 (ins GR16:$val, i16mem:$ptr),
1620 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1623 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1625 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1626 (ins GR32:$val, i32mem:$ptr),
1627 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1630 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1632 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1633 (ins GR64:$val, i64mem:$ptr),
1634 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1637 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1642 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1644 // Swap between registers.
1645 let SchedRW = [WriteALU] in {
1646 let Constraints = "$val = $dst" in {
1647 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1648 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1649 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1650 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
1651 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1652 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1654 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1655 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1658 // Swap between EAX and other registers.
1659 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1660 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize;
1661 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1662 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1663 OpSize16, Requires<[Not64BitMode]>;
1664 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1665 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1666 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1667 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1668 Requires<[In64BitMode]>;
1669 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1670 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1673 let SchedRW = [WriteALU] in {
1674 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1675 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1676 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1677 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1679 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1680 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1682 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1683 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1686 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1687 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1688 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1689 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1690 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1692 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1693 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1695 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1696 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1700 let SchedRW = [WriteALU] in {
1701 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1702 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1703 IIC_CMPXCHG_REG8>, TB;
1704 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1705 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1706 IIC_CMPXCHG_REG>, TB, OpSize;
1707 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1708 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1709 IIC_CMPXCHG_REG>, TB, OpSize16;
1710 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1711 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1712 IIC_CMPXCHG_REG>, TB;
1715 let SchedRW = [WriteALULd, WriteRMW] in {
1716 let mayLoad = 1, mayStore = 1 in {
1717 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1718 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1719 IIC_CMPXCHG_MEM8>, TB;
1720 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1721 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1722 IIC_CMPXCHG_MEM>, TB, OpSize;
1723 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1724 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1725 IIC_CMPXCHG_MEM>, TB, OpSize16;
1726 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1727 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1728 IIC_CMPXCHG_MEM>, TB;
1731 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1732 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1733 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1735 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1736 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1737 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1738 TB, Requires<[HasCmpxchg16b]>;
1742 // Lock instruction prefix
1743 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1745 // Rex64 instruction prefix
1746 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1747 Requires<[In64BitMode]>;
1749 // Data16 instruction prefix
1750 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1752 // Repeat string operation instruction prefixes
1753 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1754 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1755 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1756 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1757 // Repeat while not equal (used with CMPS and SCAS)
1758 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1762 // String manipulation instructions
1763 let SchedRW = [WriteMicrocoded] in {
1764 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1765 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1766 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1767 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize;
1768 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1769 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize16;
1770 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1771 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1774 let SchedRW = [WriteSystem] in {
1775 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1776 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1777 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1778 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize;
1779 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1780 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1783 // Flag instructions
1784 let SchedRW = [WriteALU] in {
1785 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1786 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1787 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1788 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1789 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1790 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1791 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1793 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1796 // Table lookup instructions
1797 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1800 let SchedRW = [WriteMicrocoded] in {
1801 // ASCII Adjust After Addition
1802 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1803 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1804 Requires<[Not64BitMode]>;
1806 // ASCII Adjust AX Before Division
1807 // sets AL, AH and EFLAGS and uses AL and AH
1808 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1809 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1811 // ASCII Adjust AX After Multiply
1812 // sets AL, AH and EFLAGS and uses AL
1813 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1814 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1816 // ASCII Adjust AL After Subtraction - sets
1817 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1818 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1819 Requires<[Not64BitMode]>;
1821 // Decimal Adjust AL after Addition
1822 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1823 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1824 Requires<[Not64BitMode]>;
1826 // Decimal Adjust AL after Subtraction
1827 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1828 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1829 Requires<[Not64BitMode]>;
1832 let SchedRW = [WriteSystem] in {
1833 // Check Array Index Against Bounds
1834 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1835 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
1836 Requires<[Not64BitMode]>;
1837 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1838 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1839 Requires<[Not64BitMode]>;
1841 // Adjust RPL Field of Segment Selector
1842 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1843 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1844 Requires<[Not64BitMode]>;
1845 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1846 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1847 Requires<[Not64BitMode]>;
1850 //===----------------------------------------------------------------------===//
1851 // MOVBE Instructions
1853 let Predicates = [HasMOVBE] in {
1854 let SchedRW = [WriteALULd] in {
1855 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1856 "movbe{w}\t{$src, $dst|$dst, $src}",
1857 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1859 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1860 "movbe{l}\t{$src, $dst|$dst, $src}",
1861 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1863 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1864 "movbe{q}\t{$src, $dst|$dst, $src}",
1865 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1868 let SchedRW = [WriteStore] in {
1869 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1870 "movbe{w}\t{$src, $dst|$dst, $src}",
1871 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1873 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1874 "movbe{l}\t{$src, $dst|$dst, $src}",
1875 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1877 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1878 "movbe{q}\t{$src, $dst|$dst, $src}",
1879 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1884 //===----------------------------------------------------------------------===//
1885 // RDRAND Instruction
1887 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1888 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1890 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
1891 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1893 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1894 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
1896 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
1899 //===----------------------------------------------------------------------===//
1900 // RDSEED Instruction
1902 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
1903 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
1905 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize, TB;
1906 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
1908 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
1909 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
1911 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
1914 //===----------------------------------------------------------------------===//
1915 // LZCNT Instruction
1917 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
1918 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1919 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1920 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
1922 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1923 "lzcnt{w}\t{$src, $dst|$dst, $src}",
1924 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
1925 (implicit EFLAGS)]>, XS, OpSize;
1927 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1928 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1929 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
1931 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1932 "lzcnt{l}\t{$src, $dst|$dst, $src}",
1933 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
1934 (implicit EFLAGS)]>, XS, OpSize16;
1936 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1937 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1938 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
1940 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1941 "lzcnt{q}\t{$src, $dst|$dst, $src}",
1942 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
1943 (implicit EFLAGS)]>, XS;
1946 //===----------------------------------------------------------------------===//
1949 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1950 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1951 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1952 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
1954 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1955 "tzcnt{w}\t{$src, $dst|$dst, $src}",
1956 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
1957 (implicit EFLAGS)]>, XS, OpSize;
1959 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1960 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1961 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
1963 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1964 "tzcnt{l}\t{$src, $dst|$dst, $src}",
1965 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
1966 (implicit EFLAGS)]>, XS, OpSize16;
1968 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1969 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1970 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
1972 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1973 "tzcnt{q}\t{$src, $dst|$dst, $src}",
1974 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
1975 (implicit EFLAGS)]>, XS;
1978 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
1979 RegisterClass RC, X86MemOperand x86memop, SDNode OpNode,
1981 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
1982 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1983 [(set RC:$dst, (OpNode RC:$src)), (implicit EFLAGS)]>, T8, VEX_4V;
1984 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
1985 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1986 [(set RC:$dst, (OpNode (ld_frag addr:$src))), (implicit EFLAGS)]>,
1990 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1991 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
1993 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
1994 X86blsr, loadi64>, VEX_W;
1995 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
1996 X86blsmsk, loadi32>;
1997 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
1998 X86blsmsk, loadi64>, VEX_W;
1999 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
2001 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
2002 X86blsi, loadi64>, VEX_W;
2005 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2006 X86MemOperand x86memop, Intrinsic Int,
2008 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2009 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2010 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2012 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2013 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2014 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2015 (implicit EFLAGS)]>, T8, VEX_4VOp3;
2018 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2019 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2020 int_x86_bmi_bextr_32, loadi32>;
2021 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2022 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2025 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2026 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2027 int_x86_bmi_bzhi_32, loadi32>;
2028 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2029 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2032 def : Pat<(X86bzhi GR32:$src1, GR8:$src2),
2033 (BZHI32rr GR32:$src1,
2034 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
2035 def : Pat<(X86bzhi (loadi32 addr:$src1), GR8:$src2),
2036 (BZHI32rm addr:$src1,
2037 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
2038 def : Pat<(X86bzhi GR64:$src1, GR8:$src2),
2039 (BZHI64rr GR64:$src1,
2040 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
2041 def : Pat<(X86bzhi (loadi64 addr:$src1), GR8:$src2),
2042 (BZHI64rm addr:$src1,
2043 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
2045 let Predicates = [HasBMI] in {
2046 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2047 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2048 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2049 (BEXTR32rm addr:$src1, GR32:$src2)>;
2050 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2051 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2052 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2053 (BEXTR64rm addr:$src1, GR64:$src2)>;
2056 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2057 X86MemOperand x86memop, Intrinsic Int,
2059 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2060 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2061 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2063 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2064 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2065 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2068 let Predicates = [HasBMI2] in {
2069 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2070 int_x86_bmi_pdep_32, loadi32>, T8XD;
2071 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2072 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2073 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2074 int_x86_bmi_pext_32, loadi32>, T8XS;
2075 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2076 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2079 //===----------------------------------------------------------------------===//
2082 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2084 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2085 X86MemOperand x86memop, PatFrag ld_frag,
2086 Intrinsic Int, Operand immtype,
2087 SDPatternOperator immoperator> {
2088 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2089 !strconcat(OpcodeStr,
2090 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2091 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2093 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2094 (ins x86memop:$src1, immtype:$cntl),
2095 !strconcat(OpcodeStr,
2096 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2097 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2101 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2102 int_x86_tbm_bextri_u32, i32imm, imm>;
2103 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2104 int_x86_tbm_bextri_u64, i64i32imm,
2105 i64immSExt32>, VEX_W;
2107 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2108 RegisterClass RC, string OpcodeStr,
2109 X86MemOperand x86memop, PatFrag ld_frag> {
2110 let hasSideEffects = 0 in {
2111 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2112 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2113 []>, XOP, XOP9, VEX_4V;
2115 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2116 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2117 []>, XOP, XOP9, VEX_4V;
2121 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2122 Format FormReg, Format FormMem> {
2123 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2125 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2129 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2130 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2131 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2132 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2133 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2134 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2135 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2136 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2137 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2140 //===----------------------------------------------------------------------===//
2141 // Pattern fragments to auto generate TBM instructions.
2142 //===----------------------------------------------------------------------===//
2144 let Predicates = [HasTBM] in {
2145 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2146 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2147 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2148 (BEXTRI32mi addr:$src1, imm:$src2)>;
2149 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2150 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2151 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2152 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2154 // FIXME: patterns for the load versions are not implemented
2155 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2156 (BLCFILL32rr GR32:$src)>;
2157 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2158 (BLCFILL64rr GR64:$src)>;
2160 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2161 (BLCI32rr GR32:$src)>;
2162 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2163 (BLCI64rr GR64:$src)>;
2165 // Extra patterns because opt can optimize the above patterns to this.
2166 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2167 (BLCI32rr GR32:$src)>;
2168 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2169 (BLCI64rr GR64:$src)>;
2171 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2172 (BLCIC32rr GR32:$src)>;
2173 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2174 (BLCIC64rr GR64:$src)>;
2176 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2177 (BLCMSK32rr GR32:$src)>;
2178 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2179 (BLCMSK64rr GR64:$src)>;
2181 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2182 (BLCS32rr GR32:$src)>;
2183 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2184 (BLCS64rr GR64:$src)>;
2186 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2187 (BLSFILL32rr GR32:$src)>;
2188 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2189 (BLSFILL64rr GR64:$src)>;
2191 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2192 (BLSIC32rr GR32:$src)>;
2193 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2194 (BLSIC64rr GR64:$src)>;
2196 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2197 (T1MSKC32rr GR32:$src)>;
2198 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2199 (T1MSKC64rr GR64:$src)>;
2201 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2202 (TZMSK32rr GR32:$src)>;
2203 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2204 (TZMSK64rr GR64:$src)>;
2207 //===----------------------------------------------------------------------===//
2209 //===----------------------------------------------------------------------===//
2211 include "X86InstrArithmetic.td"
2212 include "X86InstrCMovSetCC.td"
2213 include "X86InstrExtension.td"
2214 include "X86InstrControl.td"
2215 include "X86InstrShiftRotate.td"
2217 // X87 Floating Point Stack.
2218 include "X86InstrFPStack.td"
2220 // SIMD support (SSE, MMX and AVX)
2221 include "X86InstrFragmentsSIMD.td"
2223 // FMA - Fused Multiply-Add support (requires FMA)
2224 include "X86InstrFMA.td"
2227 include "X86InstrXOP.td"
2229 // SSE, MMX and 3DNow! vector support.
2230 include "X86InstrSSE.td"
2231 include "X86InstrAVX512.td"
2232 include "X86InstrMMX.td"
2233 include "X86Instr3DNow.td"
2235 include "X86InstrVMX.td"
2236 include "X86InstrSVM.td"
2238 include "X86InstrTSX.td"
2240 // System instructions.
2241 include "X86InstrSystem.td"
2243 // Compiler Pseudo Instructions and Pat Patterns
2244 include "X86InstrCompiler.td"
2246 //===----------------------------------------------------------------------===//
2247 // Assembler Mnemonic Aliases
2248 //===----------------------------------------------------------------------===//
2250 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2251 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2252 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2254 def : MnemonicAlias<"cbw", "cbtw", "att">;
2255 def : MnemonicAlias<"cwde", "cwtl", "att">;
2256 def : MnemonicAlias<"cwd", "cwtd", "att">;
2257 def : MnemonicAlias<"cdq", "cltd", "att">;
2258 def : MnemonicAlias<"cdqe", "cltq", "att">;
2259 def : MnemonicAlias<"cqo", "cqto", "att">;
2261 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2262 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2263 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2265 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2266 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2268 def : MnemonicAlias<"loopz", "loope", "att">;
2269 def : MnemonicAlias<"loopnz", "loopne", "att">;
2271 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2272 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2273 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2274 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2275 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2276 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2277 def : MnemonicAlias<"popfd", "popfl", "att">;
2279 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2280 // all modes. However: "push (addr)" and "push $42" should default to
2281 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2282 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2283 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2284 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2285 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2286 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2287 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2288 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2290 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2291 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2292 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2293 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2294 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2295 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2297 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2298 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2299 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2300 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2302 def : MnemonicAlias<"repe", "rep", "att">;
2303 def : MnemonicAlias<"repz", "rep", "att">;
2304 def : MnemonicAlias<"repnz", "repne", "att">;
2306 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2307 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2308 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2310 def : MnemonicAlias<"salb", "shlb", "att">;
2311 def : MnemonicAlias<"salw", "shlw", "att">;
2312 def : MnemonicAlias<"sall", "shll", "att">;
2313 def : MnemonicAlias<"salq", "shlq", "att">;
2315 def : MnemonicAlias<"smovb", "movsb", "att">;
2316 def : MnemonicAlias<"smovw", "movsw", "att">;
2317 def : MnemonicAlias<"smovl", "movsl", "att">;
2318 def : MnemonicAlias<"smovq", "movsq", "att">;
2320 def : MnemonicAlias<"ud2a", "ud2", "att">;
2321 def : MnemonicAlias<"verrw", "verr", "att">;
2323 // System instruction aliases.
2324 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2325 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2326 def : MnemonicAlias<"sysret", "sysretl", "att">;
2327 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2329 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2330 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2331 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2332 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2333 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2334 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2335 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2336 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2337 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2338 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2339 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2340 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2343 // Floating point stack aliases.
2344 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2345 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2346 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2347 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2348 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2349 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2350 def : MnemonicAlias<"fildq", "fildll", "att">;
2351 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2352 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2353 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2354 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2355 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2356 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2357 def : MnemonicAlias<"fwait", "wait", "att">;
2360 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2362 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2363 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2365 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2366 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2367 /// example "setz" -> "sete".
2368 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2370 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2371 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2372 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2373 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2374 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2375 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2376 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2377 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2378 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2379 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2381 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2382 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2383 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2384 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2387 // Aliases for set<CC>
2388 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2389 // Aliases for j<CC>
2390 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2391 // Aliases for cmov<CC>{w,l,q}
2392 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2393 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2394 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2395 // No size suffix for intel-style asm.
2396 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2399 //===----------------------------------------------------------------------===//
2400 // Assembler Instruction Aliases
2401 //===----------------------------------------------------------------------===//
2403 // aad/aam default to base 10 if no operand is specified.
2404 def : InstAlias<"aad", (AAD8i8 10)>;
2405 def : InstAlias<"aam", (AAM8i8 10)>;
2407 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2408 // Likewise for btc/btr/bts.
2409 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2410 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2411 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2412 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2413 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2414 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2415 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2416 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2419 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2420 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2421 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2422 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2424 // lods aliases. Accept the destination being omitted because it's implicit
2425 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2426 // in the destination.
2427 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2428 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2429 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2430 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2431 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2432 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2433 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2434 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2436 // stos aliases. Accept the source being omitted because it's implicit in
2437 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2439 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2440 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2441 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2442 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2443 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2444 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2445 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2446 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2448 // scas aliases. Accept the destination being omitted because it's implicit
2449 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2450 // in the destination.
2451 def : InstAlias<"scasb $dst", (SCAS8 dstidx8:$dst), 0>;
2452 def : InstAlias<"scasw $dst", (SCAS16 dstidx16:$dst), 0>;
2453 def : InstAlias<"scas{l|d} $dst", (SCAS32 dstidx32:$dst), 0>;
2454 def : InstAlias<"scasq $dst", (SCAS64 dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2455 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCAS8 dstidx8:$dst), 0>;
2456 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCAS16 dstidx16:$dst), 0>;
2457 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCAS32 dstidx32:$dst), 0>;
2458 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCAS64 dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2460 // div and idiv aliases for explicit A register.
2461 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2462 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2463 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2464 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2465 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2466 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2467 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2468 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2469 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2470 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2471 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2472 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2473 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2474 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2475 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2476 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2480 // Various unary fpstack operations default to operating on on ST1.
2481 // For example, "fxch" -> "fxch %st(1)"
2482 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2483 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2484 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2485 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2486 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2487 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2488 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2489 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2490 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2491 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2492 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2493 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2494 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2495 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2496 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2498 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2499 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2500 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2502 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2503 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2504 (Inst RST:$op), EmitAlias>;
2505 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2506 (Inst ST0), EmitAlias>;
2509 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2510 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2511 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2512 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2513 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2514 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2515 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2516 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2517 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2518 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2519 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2520 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2521 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2522 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2523 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2524 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2527 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2528 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2529 // solely because gas supports it.
2530 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2531 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2532 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2533 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2534 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2535 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2537 // We accept "fnstsw %eax" even though it only writes %ax.
2538 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2539 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2540 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2542 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2543 // this is compatible with what GAS does.
2544 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2545 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2546 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>, Requires<[Not16BitMode]>;
2547 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>, Requires<[Not16BitMode]>;
2548 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2549 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2550 def : InstAlias<"lcall *$dst", (FARCALL16m opaque32mem:$dst)>, Requires<[In16BitMode]>;
2551 def : InstAlias<"ljmp *$dst", (FARJMP16m opaque32mem:$dst)>, Requires<[In16BitMode]>;
2553 def : InstAlias<"call *$dst", (CALL64m i16mem:$dst)>, Requires<[In64BitMode]>;
2554 def : InstAlias<"jmp *$dst", (JMP64m i16mem:$dst)>, Requires<[In64BitMode]>;
2555 def : InstAlias<"call *$dst", (CALL32m i16mem:$dst)>, Requires<[In32BitMode]>;
2556 def : InstAlias<"jmp *$dst", (JMP32m i16mem:$dst)>, Requires<[In32BitMode]>;
2557 def : InstAlias<"call *$dst", (CALL16m i16mem:$dst)>, Requires<[In16BitMode]>;
2558 def : InstAlias<"jmp *$dst", (JMP16m i16mem:$dst)>, Requires<[In16BitMode]>;
2561 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2562 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>;
2563 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>;
2564 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>;
2565 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>;
2566 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
2567 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
2569 // inb %dx -> inb %al, %dx
2570 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2571 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2572 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2573 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2574 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2575 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2578 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2579 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2580 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2581 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2582 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2583 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2584 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2585 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2586 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2588 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2589 // the move. All segment/mem forms are equivalent, this has the shortest
2591 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>;
2592 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>;
2594 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2595 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
2597 // Match 'movq GR64, MMX' as an alias for movd.
2598 def : InstAlias<"movq $src, $dst",
2599 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2600 def : InstAlias<"movq $src, $dst",
2601 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2604 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2605 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2606 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2607 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2608 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2609 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2610 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2613 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2614 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2615 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2616 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2617 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2618 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2619 // Note: No GR32->GR64 movzx form.
2621 // outb %dx -> outb %al, %dx
2622 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2623 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2624 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2625 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2626 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2627 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2629 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2630 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2631 // errors, since its encoding is the most compact.
2632 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>;
2634 // shld/shrd op,op -> shld op, op, CL
2635 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2636 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2637 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2638 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2639 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2640 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2642 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2643 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2644 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2645 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2646 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2647 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2649 /* FIXME: This is disabled because the asm matcher is currently incapable of
2650 * matching a fixed immediate like $1.
2651 // "shl X, $1" is an alias for "shl X".
2652 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2653 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2654 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2655 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2656 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2657 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2658 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2659 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2660 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2661 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2662 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2663 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2664 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2665 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2666 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2667 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2668 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2671 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2672 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2673 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2674 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2677 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2678 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", (TEST8rm GR8 :$val, i8mem :$mem)>;
2679 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", (TEST16rm GR16:$val, i16mem:$mem)>;
2680 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", (TEST32rm GR32:$val, i32mem:$mem)>;
2681 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", (TEST64rm GR64:$val, i64mem:$mem)>;
2683 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2684 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", (XCHG8rm GR8 :$val, i8mem :$mem)>;
2685 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", (XCHG16rm GR16:$val, i16mem:$mem)>;
2686 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", (XCHG32rm GR32:$val, i32mem:$mem)>;
2687 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", (XCHG64rm GR64:$val, i64mem:$mem)>;
2689 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2690 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src)>;
2691 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src)>, Requires<[Not64BitMode]>;
2692 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
2693 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src)>;