1 //===- X86InstrInfo.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
26 def SDTX86Cmov : SDTypeProfile<1, 4,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
28 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
30 // Unary and binary operator instructions that set EFLAGS as a side-effect.
31 def SDTUnaryArithWithFlags : SDTypeProfile<1, 1,
33 def SDTBinaryArithWithFlags : SDTypeProfile<1, 2,
37 def SDTX86BrCond : SDTypeProfile<0, 3,
38 [SDTCisVT<0, OtherVT>,
39 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
41 def SDTX86SetCC : SDTypeProfile<1, 2,
43 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
45 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
47 def SDTX86cas8 : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
49 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
50 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
51 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
53 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
54 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
57 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
59 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
61 def SDTX86RdTsc : SDTypeProfile<0, 0, []>;
63 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
65 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
67 def SDT_X86SegmentBaseAddress : SDTypeProfile<1, 1, [SDTCisPtrTy<0>]>;
69 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
71 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
73 def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
74 def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
75 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
76 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
78 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
80 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
82 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
83 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
85 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
87 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
88 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
90 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8,
91 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
93 def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary,
94 [SDNPHasChain, SDNPMayStore,
95 SDNPMayLoad, SDNPMemOperand]>;
96 def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary,
97 [SDNPHasChain, SDNPMayStore,
98 SDNPMayLoad, SDNPMemOperand]>;
99 def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary,
100 [SDNPHasChain, SDNPMayStore,
101 SDNPMayLoad, SDNPMemOperand]>;
102 def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary,
103 [SDNPHasChain, SDNPMayStore,
104 SDNPMayLoad, SDNPMemOperand]>;
105 def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary,
106 [SDNPHasChain, SDNPMayStore,
107 SDNPMayLoad, SDNPMemOperand]>;
108 def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary,
109 [SDNPHasChain, SDNPMayStore,
110 SDNPMayLoad, SDNPMemOperand]>;
111 def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary,
112 [SDNPHasChain, SDNPMayStore,
113 SDNPMayLoad, SDNPMemOperand]>;
114 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
115 [SDNPHasChain, SDNPOptInFlag]>;
117 def X86callseq_start :
118 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
119 [SDNPHasChain, SDNPOutFlag]>;
121 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
122 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
124 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
125 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
127 def X86tailcall: SDNode<"X86ISD::TAILCALL", SDT_X86Call,
128 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
130 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
131 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore]>;
132 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
133 [SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
136 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
137 [SDNPHasChain, SDNPOutFlag, SDNPSideEffect]>;
139 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
140 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
142 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
143 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
144 def X86SegmentBaseAddress : SDNode<"X86ISD::SegmentBaseAddress",
145 SDT_X86SegmentBaseAddress, []>;
147 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
150 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
151 [SDNPHasChain, SDNPOptInFlag]>;
153 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags>;
154 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
155 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags>;
156 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
157 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
158 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
160 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
162 //===----------------------------------------------------------------------===//
163 // X86 Operand Definitions.
166 def i32imm_pcrel : Operand<i32> {
167 let PrintMethod = "print_pcrel_imm";
171 // *mem - Operand definitions for the funky X86 addressing mode operands.
173 class X86MemOperand<string printMethod> : Operand<iPTR> {
174 let PrintMethod = printMethod;
175 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm);
178 def i8mem : X86MemOperand<"printi8mem">;
179 def i16mem : X86MemOperand<"printi16mem">;
180 def i32mem : X86MemOperand<"printi32mem">;
181 def i64mem : X86MemOperand<"printi64mem">;
182 def i128mem : X86MemOperand<"printi128mem">;
183 def f32mem : X86MemOperand<"printf32mem">;
184 def f64mem : X86MemOperand<"printf64mem">;
185 def f80mem : X86MemOperand<"printf80mem">;
186 def f128mem : X86MemOperand<"printf128mem">;
188 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
189 // plain GR64, so that it doesn't potentially require a REX prefix.
190 def i8mem_NOREX : Operand<i64> {
191 let PrintMethod = "printi8mem";
192 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX, i32imm, i8imm);
195 def lea32mem : Operand<i32> {
196 let PrintMethod = "printlea32mem";
197 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
200 def SSECC : Operand<i8> {
201 let PrintMethod = "printSSECC";
204 def piclabel: Operand<i32> {
205 let PrintMethod = "printPICLabel";
208 // A couple of more descriptive operand definitions.
209 // 16-bits but only 8 bits are significant.
210 def i16i8imm : Operand<i16>;
211 // 32-bits but only 8 bits are significant.
212 def i32i8imm : Operand<i32>;
214 // Branch targets have OtherVT type and print as pc-relative values.
215 def brtarget : Operand<OtherVT> {
216 let PrintMethod = "print_pcrel_imm";
219 //===----------------------------------------------------------------------===//
220 // X86 Complex Pattern Definitions.
223 // Define X86 specific addressing mode.
224 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], []>;
225 def lea32addr : ComplexPattern<i32, 4, "SelectLEAAddr",
226 [add, sub, mul, shl, or, frameindex], []>;
227 def tls32addr : ComplexPattern<i32, 4, "SelectTLSADDRAddr",
228 [tglobaltlsaddr], []>;
230 //===----------------------------------------------------------------------===//
231 // X86 Instruction Predicate Definitions.
232 def HasMMX : Predicate<"Subtarget->hasMMX()">;
233 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
234 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
235 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
236 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
237 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
238 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
239 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
240 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
241 def In32BitMode : Predicate<"!Subtarget->is64Bit()">;
242 def In64BitMode : Predicate<"Subtarget->is64Bit()">;
243 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
244 def NotSmallCode : Predicate<"TM.getCodeModel() != CodeModel::Small">;
245 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
246 def OptForSpeed : Predicate<"!OptForSize">;
247 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
248 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
250 //===----------------------------------------------------------------------===//
251 // X86 Instruction Format Definitions.
254 include "X86InstrFormats.td"
256 //===----------------------------------------------------------------------===//
257 // Pattern fragments...
260 // X86 specific condition code. These correspond to CondCode in
261 // X86InstrInfo.h. They must be kept in synch.
262 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
263 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
264 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
265 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
266 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
267 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
268 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
269 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
270 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
271 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
272 def X86_COND_NO : PatLeaf<(i8 10)>;
273 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
274 def X86_COND_NS : PatLeaf<(i8 12)>;
275 def X86_COND_O : PatLeaf<(i8 13)>;
276 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
277 def X86_COND_S : PatLeaf<(i8 15)>;
279 def i16immSExt8 : PatLeaf<(i16 imm), [{
280 // i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit
281 // sign extended field.
282 return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
285 def i32immSExt8 : PatLeaf<(i32 imm), [{
286 // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
287 // sign extended field.
288 return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
291 // Helper fragments for loads.
292 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
293 // known to be 32-bit aligned or better. Ditto for i8 to i16.
294 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
295 LoadSDNode *LD = cast<LoadSDNode>(N);
296 if (const Value *Src = LD->getSrcValue())
297 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
298 if (PT->getAddressSpace() > 255)
300 ISD::LoadExtType ExtType = LD->getExtensionType();
301 if (ExtType == ISD::NON_EXTLOAD)
303 if (ExtType == ISD::EXTLOAD)
304 return LD->getAlignment() >= 2 && !LD->isVolatile();
308 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
309 LoadSDNode *LD = cast<LoadSDNode>(N);
310 if (const Value *Src = LD->getSrcValue())
311 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
312 if (PT->getAddressSpace() > 255)
314 ISD::LoadExtType ExtType = LD->getExtensionType();
315 if (ExtType == ISD::EXTLOAD)
316 return LD->getAlignment() >= 2 && !LD->isVolatile();
320 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
321 LoadSDNode *LD = cast<LoadSDNode>(N);
322 if (const Value *Src = LD->getSrcValue())
323 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
324 if (PT->getAddressSpace() > 255)
326 ISD::LoadExtType ExtType = LD->getExtensionType();
327 if (ExtType == ISD::NON_EXTLOAD)
329 if (ExtType == ISD::EXTLOAD)
330 return LD->getAlignment() >= 4 && !LD->isVolatile();
334 def nvloadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
335 LoadSDNode *LD = cast<LoadSDNode>(N);
336 if (const Value *Src = LD->getSrcValue())
337 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
338 if (PT->getAddressSpace() > 255)
340 if (LD->isVolatile())
342 ISD::LoadExtType ExtType = LD->getExtensionType();
343 if (ExtType == ISD::NON_EXTLOAD)
345 if (ExtType == ISD::EXTLOAD)
346 return LD->getAlignment() >= 4;
350 def gsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
351 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
352 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
353 return PT->getAddressSpace() == 256;
357 def fsload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
358 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
359 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
360 return PT->getAddressSpace() == 257;
364 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr)), [{
365 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
366 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
367 if (PT->getAddressSpace() > 255)
371 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr)), [{
372 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
373 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
374 if (PT->getAddressSpace() > 255)
379 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr)), [{
380 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
381 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
382 if (PT->getAddressSpace() > 255)
386 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr)), [{
387 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
388 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
389 if (PT->getAddressSpace() > 255)
393 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr)), [{
394 if (const Value *Src = cast<LoadSDNode>(N)->getSrcValue())
395 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
396 if (PT->getAddressSpace() > 255)
401 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
402 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
403 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
405 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
406 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
407 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
408 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
409 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
410 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
412 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
413 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
414 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
415 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
416 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
417 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
420 // An 'and' node with a single use.
421 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
422 return N->hasOneUse();
424 // An 'srl' node with a single use.
425 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
426 return N->hasOneUse();
428 // An 'trunc' node with a single use.
429 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
430 return N->hasOneUse();
433 // 'shld' and 'shrd' instruction patterns. Note that even though these have
434 // the srl and shl in their patterns, the C++ code must still check for them,
435 // because predicates are tested before children nodes are explored.
437 def shrd : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
438 (or (srl node:$src1, node:$amt1),
439 (shl node:$src2, node:$amt2)), [{
440 assert(N->getOpcode() == ISD::OR);
441 return N->getOperand(0).getOpcode() == ISD::SRL &&
442 N->getOperand(1).getOpcode() == ISD::SHL &&
443 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
444 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
445 N->getOperand(0).getConstantOperandVal(1) ==
446 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
449 def shld : PatFrag<(ops node:$src1, node:$amt1, node:$src2, node:$amt2),
450 (or (shl node:$src1, node:$amt1),
451 (srl node:$src2, node:$amt2)), [{
452 assert(N->getOpcode() == ISD::OR);
453 return N->getOperand(0).getOpcode() == ISD::SHL &&
454 N->getOperand(1).getOpcode() == ISD::SRL &&
455 isa<ConstantSDNode>(N->getOperand(0).getOperand(1)) &&
456 isa<ConstantSDNode>(N->getOperand(1).getOperand(1)) &&
457 N->getOperand(0).getConstantOperandVal(1) ==
458 N->getValueSizeInBits(0) - N->getOperand(1).getConstantOperandVal(1);
461 //===----------------------------------------------------------------------===//
462 // Instruction list...
465 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
466 // a stack adjustment and the codegen must know that they may modify the stack
467 // pointer before prolog-epilog rewriting occurs.
468 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
469 // sub / add which can clobber EFLAGS.
470 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
471 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
473 [(X86callseq_start timm:$amt)]>,
474 Requires<[In32BitMode]>;
475 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
477 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
478 Requires<[In32BitMode]>;
482 let neverHasSideEffects = 1 in
483 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
486 let neverHasSideEffects = 1, isNotDuplicable = 1, Uses = [ESP] in
487 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins piclabel:$label),
491 //===----------------------------------------------------------------------===//
492 // Control Flow Instructions...
495 // Return instructions.
496 let isTerminator = 1, isReturn = 1, isBarrier = 1,
497 hasCtrlDep = 1, FPForm = SpecialFP, FPFormBits = SpecialFP.Value in {
498 def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
501 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
503 [(X86retflag imm:$amt)]>;
506 // All branches are RawFrm, Void, Branch, and Terminators
507 let isBranch = 1, isTerminator = 1 in
508 class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
509 I<opcode, RawFrm, (outs), ins, asm, pattern>;
511 let isBranch = 1, isBarrier = 1 in
512 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp\t$dst", [(br bb:$dst)]>;
515 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
516 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
517 [(brind GR32:$dst)]>;
518 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
519 [(brind (loadi32 addr:$dst))]>;
522 // Conditional branches
523 let Uses = [EFLAGS] in {
524 def JE : IBr<0x84, (ins brtarget:$dst), "je\t$dst",
525 [(X86brcond bb:$dst, X86_COND_E, EFLAGS)]>, TB;
526 def JNE : IBr<0x85, (ins brtarget:$dst), "jne\t$dst",
527 [(X86brcond bb:$dst, X86_COND_NE, EFLAGS)]>, TB;
528 def JL : IBr<0x8C, (ins brtarget:$dst), "jl\t$dst",
529 [(X86brcond bb:$dst, X86_COND_L, EFLAGS)]>, TB;
530 def JLE : IBr<0x8E, (ins brtarget:$dst), "jle\t$dst",
531 [(X86brcond bb:$dst, X86_COND_LE, EFLAGS)]>, TB;
532 def JG : IBr<0x8F, (ins brtarget:$dst), "jg\t$dst",
533 [(X86brcond bb:$dst, X86_COND_G, EFLAGS)]>, TB;
534 def JGE : IBr<0x8D, (ins brtarget:$dst), "jge\t$dst",
535 [(X86brcond bb:$dst, X86_COND_GE, EFLAGS)]>, TB;
537 def JB : IBr<0x82, (ins brtarget:$dst), "jb\t$dst",
538 [(X86brcond bb:$dst, X86_COND_B, EFLAGS)]>, TB;
539 def JBE : IBr<0x86, (ins brtarget:$dst), "jbe\t$dst",
540 [(X86brcond bb:$dst, X86_COND_BE, EFLAGS)]>, TB;
541 def JA : IBr<0x87, (ins brtarget:$dst), "ja\t$dst",
542 [(X86brcond bb:$dst, X86_COND_A, EFLAGS)]>, TB;
543 def JAE : IBr<0x83, (ins brtarget:$dst), "jae\t$dst",
544 [(X86brcond bb:$dst, X86_COND_AE, EFLAGS)]>, TB;
546 def JS : IBr<0x88, (ins brtarget:$dst), "js\t$dst",
547 [(X86brcond bb:$dst, X86_COND_S, EFLAGS)]>, TB;
548 def JNS : IBr<0x89, (ins brtarget:$dst), "jns\t$dst",
549 [(X86brcond bb:$dst, X86_COND_NS, EFLAGS)]>, TB;
550 def JP : IBr<0x8A, (ins brtarget:$dst), "jp\t$dst",
551 [(X86brcond bb:$dst, X86_COND_P, EFLAGS)]>, TB;
552 def JNP : IBr<0x8B, (ins brtarget:$dst), "jnp\t$dst",
553 [(X86brcond bb:$dst, X86_COND_NP, EFLAGS)]>, TB;
554 def JO : IBr<0x80, (ins brtarget:$dst), "jo\t$dst",
555 [(X86brcond bb:$dst, X86_COND_O, EFLAGS)]>, TB;
556 def JNO : IBr<0x81, (ins brtarget:$dst), "jno\t$dst",
557 [(X86brcond bb:$dst, X86_COND_NO, EFLAGS)]>, TB;
560 //===----------------------------------------------------------------------===//
561 // Call Instructions...
564 // All calls clobber the non-callee saved registers. ESP is marked as
565 // a use to prevent stack-pointer assignments that appear immediately
566 // before calls from potentially appearing dead. Uses for argument
567 // registers are added manually.
568 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
569 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
570 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
571 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
573 def CALLpcrel32 : Ii32<0xE8, RawFrm,
574 (outs), (ins i32imm_pcrel:$dst,variable_ops),
576 def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst, variable_ops),
577 "call\t{*}$dst", [(X86call GR32:$dst)]>;
578 def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops),
579 "call\t{*}$dst", [(X86call (loadi32 addr:$dst))]>;
584 def TAILCALL : I<0, Pseudo, (outs), (ins),
588 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
589 def TCRETURNdi : I<0, Pseudo, (outs), (ins i32imm:$dst, i32imm:$offset, variable_ops),
590 "#TC_RETURN $dst $offset",
593 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
594 def TCRETURNri : I<0, Pseudo, (outs), (ins GR32:$dst, i32imm:$offset, variable_ops),
595 "#TC_RETURN $dst $offset",
598 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
600 def TAILJMPd : IBr<0xE9, (ins i32imm_pcrel:$dst), "jmp\t$dst # TAILCALL",
602 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
603 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst # TAILCALL",
605 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
606 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
607 "jmp\t{*}$dst # TAILCALL", []>;
609 //===----------------------------------------------------------------------===//
610 // Miscellaneous Instructions...
612 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in
613 def LEAVE : I<0xC9, RawFrm,
614 (outs), (ins), "leave", []>;
616 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
618 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>;
621 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>;
624 let Defs = [ESP], Uses = [ESP], neverHasSideEffects = 1, mayStore = 1 in {
625 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i8imm:$imm),
626 "push{l}\t$imm", []>;
627 def PUSH32i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
628 "push{l}\t$imm", []>;
629 def PUSH32i32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
630 "push{l}\t$imm", []>;
633 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, neverHasSideEffects=1 in
634 def POPFD : I<0x9D, RawFrm, (outs), (ins), "popf", []>;
635 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
636 def PUSHFD : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
638 let isTwoAddress = 1 in // GR32 = bswap GR32
639 def BSWAP32r : I<0xC8, AddRegFrm,
640 (outs GR32:$dst), (ins GR32:$src),
642 [(set GR32:$dst, (bswap GR32:$src))]>, TB;
645 // Bit scan instructions.
646 let Defs = [EFLAGS] in {
647 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
648 "bsf{w}\t{$src, $dst|$dst, $src}",
649 [(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
650 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
651 "bsf{w}\t{$src, $dst|$dst, $src}",
652 [(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
653 (implicit EFLAGS)]>, TB;
654 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
655 "bsf{l}\t{$src, $dst|$dst, $src}",
656 [(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
657 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
658 "bsf{l}\t{$src, $dst|$dst, $src}",
659 [(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
660 (implicit EFLAGS)]>, TB;
662 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
663 "bsr{w}\t{$src, $dst|$dst, $src}",
664 [(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
665 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
666 "bsr{w}\t{$src, $dst|$dst, $src}",
667 [(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
668 (implicit EFLAGS)]>, TB;
669 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
670 "bsr{l}\t{$src, $dst|$dst, $src}",
671 [(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
672 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
673 "bsr{l}\t{$src, $dst|$dst, $src}",
674 [(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
675 (implicit EFLAGS)]>, TB;
678 let neverHasSideEffects = 1 in
679 def LEA16r : I<0x8D, MRMSrcMem,
680 (outs GR16:$dst), (ins i32mem:$src),
681 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
682 let isReMaterializable = 1 in
683 def LEA32r : I<0x8D, MRMSrcMem,
684 (outs GR32:$dst), (ins lea32mem:$src),
685 "lea{l}\t{$src|$dst}, {$dst|$src}",
686 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In32BitMode]>;
688 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI] in {
689 def REP_MOVSB : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
690 [(X86rep_movs i8)]>, REP;
691 def REP_MOVSW : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
692 [(X86rep_movs i16)]>, REP, OpSize;
693 def REP_MOVSD : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
694 [(X86rep_movs i32)]>, REP;
697 let Defs = [ECX,EDI], Uses = [AL,ECX,EDI] in
698 def REP_STOSB : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
699 [(X86rep_stos i8)]>, REP;
700 let Defs = [ECX,EDI], Uses = [AX,ECX,EDI] in
701 def REP_STOSW : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
702 [(X86rep_stos i16)]>, REP, OpSize;
703 let Defs = [ECX,EDI], Uses = [EAX,ECX,EDI] in
704 def REP_STOSD : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
705 [(X86rep_stos i32)]>, REP;
707 let Defs = [RAX, RDX] in
708 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
711 let isBarrier = 1, hasCtrlDep = 1 in {
712 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
715 //===----------------------------------------------------------------------===//
716 // Input/Output Instructions...
718 let Defs = [AL], Uses = [DX] in
719 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
720 "in{b}\t{%dx, %al|%AL, %DX}", []>;
721 let Defs = [AX], Uses = [DX] in
722 def IN16rr : I<0xED, RawFrm, (outs), (ins),
723 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
724 let Defs = [EAX], Uses = [DX] in
725 def IN32rr : I<0xED, RawFrm, (outs), (ins),
726 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
729 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i16i8imm:$port),
730 "in{b}\t{$port, %al|%AL, $port}", []>;
732 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
733 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
735 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i16i8imm:$port),
736 "in{l}\t{$port, %eax|%EAX, $port}", []>;
738 let Uses = [DX, AL] in
739 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
740 "out{b}\t{%al, %dx|%DX, %AL}", []>;
741 let Uses = [DX, AX] in
742 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
743 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
744 let Uses = [DX, EAX] in
745 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
746 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
749 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i16i8imm:$port),
750 "out{b}\t{%al, $port|$port, %AL}", []>;
752 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
753 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
755 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i16i8imm:$port),
756 "out{l}\t{%eax, $port|$port, %EAX}", []>;
758 //===----------------------------------------------------------------------===//
759 // Move Instructions...
761 let neverHasSideEffects = 1 in {
762 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
763 "mov{b}\t{$src, $dst|$dst, $src}", []>;
764 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
765 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
766 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
767 "mov{l}\t{$src, $dst|$dst, $src}", []>;
769 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
770 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
771 "mov{b}\t{$src, $dst|$dst, $src}",
772 [(set GR8:$dst, imm:$src)]>;
773 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
774 "mov{w}\t{$src, $dst|$dst, $src}",
775 [(set GR16:$dst, imm:$src)]>, OpSize;
776 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
777 "mov{l}\t{$src, $dst|$dst, $src}",
778 [(set GR32:$dst, imm:$src)]>;
780 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
781 "mov{b}\t{$src, $dst|$dst, $src}",
782 [(store (i8 imm:$src), addr:$dst)]>;
783 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
784 "mov{w}\t{$src, $dst|$dst, $src}",
785 [(store (i16 imm:$src), addr:$dst)]>, OpSize;
786 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
787 "mov{l}\t{$src, $dst|$dst, $src}",
788 [(store (i32 imm:$src), addr:$dst)]>;
790 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
791 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
792 "mov{b}\t{$src, $dst|$dst, $src}",
793 [(set GR8:$dst, (loadi8 addr:$src))]>;
794 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
795 "mov{w}\t{$src, $dst|$dst, $src}",
796 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize;
797 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
798 "mov{l}\t{$src, $dst|$dst, $src}",
799 [(set GR32:$dst, (loadi32 addr:$src))]>;
802 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
803 "mov{b}\t{$src, $dst|$dst, $src}",
804 [(store GR8:$src, addr:$dst)]>;
805 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
806 "mov{w}\t{$src, $dst|$dst, $src}",
807 [(store GR16:$src, addr:$dst)]>, OpSize;
808 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
809 "mov{l}\t{$src, $dst|$dst, $src}",
810 [(store GR32:$src, addr:$dst)]>;
812 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
813 // that they can be used for copying and storing h registers, which can't be
814 // encoded when a REX prefix is present.
815 let neverHasSideEffects = 1 in
816 def MOV8rr_NOREX : I<0x88, MRMDestReg,
817 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
818 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
820 def MOV8mr_NOREX : I<0x88, MRMDestMem,
821 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
822 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
824 canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
825 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
826 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
827 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
829 //===----------------------------------------------------------------------===//
830 // Fixed-Register Multiplication and Division Instructions...
833 // Extra precision multiplication
834 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
835 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
836 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
837 // This probably ought to be moved to a def : Pat<> if the
838 // syntax can be accepted.
839 [(set AL, (mul AL, GR8:$src)),
840 (implicit EFLAGS)]>; // AL,AH = AL*GR8
842 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
843 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
845 []>, OpSize; // AX,DX = AX*GR16
847 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
848 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
850 []>; // EAX,EDX = EAX*GR32
852 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
853 def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src),
855 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
856 // This probably ought to be moved to a def : Pat<> if the
857 // syntax can be accepted.
858 [(set AL, (mul AL, (loadi8 addr:$src))),
859 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
861 let mayLoad = 1, neverHasSideEffects = 1 in {
862 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
863 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
865 []>, OpSize; // AX,DX = AX*[mem16]
867 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
868 def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
870 []>; // EAX,EDX = EAX*[mem32]
873 let neverHasSideEffects = 1 in {
874 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
875 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>;
877 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
878 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
879 OpSize; // AX,DX = AX*GR16
880 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
881 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
882 // EAX,EDX = EAX*GR32
884 let Defs = [AL,AH,EFLAGS], Uses = [AL] in
885 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
886 "imul{b}\t$src", []>; // AL,AH = AL*[mem8]
887 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
888 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
889 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
890 let Defs = [EAX,EDX], Uses = [EAX] in
891 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
892 "imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
894 } // neverHasSideEffects
896 // unsigned division/remainder
897 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
898 def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
900 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
901 def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
902 "div{w}\t$src", []>, OpSize;
903 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
904 def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
907 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
908 def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
910 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
911 def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
912 "div{w}\t$src", []>, OpSize;
913 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
914 def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
918 // Signed division/remainder.
919 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
920 def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
921 "idiv{b}\t$src", []>;
922 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
923 def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
924 "idiv{w}\t$src", []>, OpSize;
925 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
926 def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
927 "idiv{l}\t$src", []>;
928 let mayLoad = 1, mayLoad = 1 in {
929 let Defs = [AL,AH,EFLAGS], Uses = [AX] in
930 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
931 "idiv{b}\t$src", []>;
932 let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
933 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
934 "idiv{w}\t$src", []>, OpSize;
935 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
936 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX
937 "idiv{l}\t$src", []>;
940 //===----------------------------------------------------------------------===//
941 // Two address Instructions.
943 let isTwoAddress = 1 in {
946 let Uses = [EFLAGS] in {
947 let isCommutable = 1 in {
948 def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, GR16 = GR16
949 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
950 "cmovb\t{$src2, $dst|$dst, $src2}",
951 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
952 X86_COND_B, EFLAGS))]>,
954 def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, GR32 = GR32
955 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
956 "cmovb\t{$src2, $dst|$dst, $src2}",
957 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
958 X86_COND_B, EFLAGS))]>,
960 def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, GR16 = GR16
961 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
962 "cmovae\t{$src2, $dst|$dst, $src2}",
963 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
964 X86_COND_AE, EFLAGS))]>,
966 def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, GR32 = GR32
967 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
968 "cmovae\t{$src2, $dst|$dst, $src2}",
969 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
970 X86_COND_AE, EFLAGS))]>,
972 def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, GR16 = GR16
973 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
974 "cmove\t{$src2, $dst|$dst, $src2}",
975 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
976 X86_COND_E, EFLAGS))]>,
978 def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, GR32 = GR32
979 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
980 "cmove\t{$src2, $dst|$dst, $src2}",
981 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
982 X86_COND_E, EFLAGS))]>,
984 def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, GR16 = GR16
985 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
986 "cmovne\t{$src2, $dst|$dst, $src2}",
987 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
988 X86_COND_NE, EFLAGS))]>,
990 def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, GR32 = GR32
991 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
992 "cmovne\t{$src2, $dst|$dst, $src2}",
993 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
994 X86_COND_NE, EFLAGS))]>,
996 def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, GR16 = GR16
997 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
998 "cmovbe\t{$src2, $dst|$dst, $src2}",
999 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1000 X86_COND_BE, EFLAGS))]>,
1002 def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, GR32 = GR32
1003 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1004 "cmovbe\t{$src2, $dst|$dst, $src2}",
1005 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1006 X86_COND_BE, EFLAGS))]>,
1008 def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, GR16 = GR16
1009 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1010 "cmova\t{$src2, $dst|$dst, $src2}",
1011 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1012 X86_COND_A, EFLAGS))]>,
1014 def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, GR32 = GR32
1015 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1016 "cmova\t{$src2, $dst|$dst, $src2}",
1017 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1018 X86_COND_A, EFLAGS))]>,
1020 def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, GR16 = GR16
1021 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1022 "cmovl\t{$src2, $dst|$dst, $src2}",
1023 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1024 X86_COND_L, EFLAGS))]>,
1026 def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, GR32 = GR32
1027 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1028 "cmovl\t{$src2, $dst|$dst, $src2}",
1029 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1030 X86_COND_L, EFLAGS))]>,
1032 def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, GR16 = GR16
1033 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1034 "cmovge\t{$src2, $dst|$dst, $src2}",
1035 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1036 X86_COND_GE, EFLAGS))]>,
1038 def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, GR32 = GR32
1039 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1040 "cmovge\t{$src2, $dst|$dst, $src2}",
1041 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1042 X86_COND_GE, EFLAGS))]>,
1044 def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, GR16 = GR16
1045 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1046 "cmovle\t{$src2, $dst|$dst, $src2}",
1047 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1048 X86_COND_LE, EFLAGS))]>,
1050 def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, GR32 = GR32
1051 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1052 "cmovle\t{$src2, $dst|$dst, $src2}",
1053 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1054 X86_COND_LE, EFLAGS))]>,
1056 def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, GR16 = GR16
1057 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1058 "cmovg\t{$src2, $dst|$dst, $src2}",
1059 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1060 X86_COND_G, EFLAGS))]>,
1062 def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, GR32 = GR32
1063 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1064 "cmovg\t{$src2, $dst|$dst, $src2}",
1065 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1066 X86_COND_G, EFLAGS))]>,
1068 def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, GR16 = GR16
1069 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1070 "cmovs\t{$src2, $dst|$dst, $src2}",
1071 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1072 X86_COND_S, EFLAGS))]>,
1074 def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, GR32 = GR32
1075 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1076 "cmovs\t{$src2, $dst|$dst, $src2}",
1077 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1078 X86_COND_S, EFLAGS))]>,
1080 def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, GR16 = GR16
1081 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1082 "cmovns\t{$src2, $dst|$dst, $src2}",
1083 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1084 X86_COND_NS, EFLAGS))]>,
1086 def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, GR32 = GR32
1087 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1088 "cmovns\t{$src2, $dst|$dst, $src2}",
1089 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1090 X86_COND_NS, EFLAGS))]>,
1092 def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, GR16 = GR16
1093 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1094 "cmovp\t{$src2, $dst|$dst, $src2}",
1095 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1096 X86_COND_P, EFLAGS))]>,
1098 def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, GR32 = GR32
1099 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1100 "cmovp\t{$src2, $dst|$dst, $src2}",
1101 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1102 X86_COND_P, EFLAGS))]>,
1104 def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, GR16 = GR16
1105 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1106 "cmovnp\t{$src2, $dst|$dst, $src2}",
1107 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1108 X86_COND_NP, EFLAGS))]>,
1110 def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, GR32 = GR32
1111 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1112 "cmovnp\t{$src2, $dst|$dst, $src2}",
1113 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1114 X86_COND_NP, EFLAGS))]>,
1116 def CMOVO16rr : I<0x40, MRMSrcReg, // if overflow, GR16 = GR16
1117 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1118 "cmovo\t{$src2, $dst|$dst, $src2}",
1119 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1120 X86_COND_O, EFLAGS))]>,
1122 def CMOVO32rr : I<0x40, MRMSrcReg, // if overflow, GR32 = GR32
1123 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1124 "cmovo\t{$src2, $dst|$dst, $src2}",
1125 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1126 X86_COND_O, EFLAGS))]>,
1128 def CMOVNO16rr : I<0x41, MRMSrcReg, // if !overflow, GR16 = GR16
1129 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1130 "cmovno\t{$src2, $dst|$dst, $src2}",
1131 [(set GR16:$dst, (X86cmov GR16:$src1, GR16:$src2,
1132 X86_COND_NO, EFLAGS))]>,
1134 def CMOVNO32rr : I<0x41, MRMSrcReg, // if !overflow, GR32 = GR32
1135 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1136 "cmovno\t{$src2, $dst|$dst, $src2}",
1137 [(set GR32:$dst, (X86cmov GR32:$src1, GR32:$src2,
1138 X86_COND_NO, EFLAGS))]>,
1140 } // isCommutable = 1
1142 def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, GR16 = [mem16]
1143 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1144 "cmovb\t{$src2, $dst|$dst, $src2}",
1145 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1146 X86_COND_B, EFLAGS))]>,
1148 def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, GR32 = [mem32]
1149 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1150 "cmovb\t{$src2, $dst|$dst, $src2}",
1151 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1152 X86_COND_B, EFLAGS))]>,
1154 def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, GR16 = [mem16]
1155 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1156 "cmovae\t{$src2, $dst|$dst, $src2}",
1157 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1158 X86_COND_AE, EFLAGS))]>,
1160 def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, GR32 = [mem32]
1161 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1162 "cmovae\t{$src2, $dst|$dst, $src2}",
1163 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1164 X86_COND_AE, EFLAGS))]>,
1166 def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, GR16 = [mem16]
1167 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1168 "cmove\t{$src2, $dst|$dst, $src2}",
1169 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1170 X86_COND_E, EFLAGS))]>,
1172 def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, GR32 = [mem32]
1173 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1174 "cmove\t{$src2, $dst|$dst, $src2}",
1175 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1176 X86_COND_E, EFLAGS))]>,
1178 def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, GR16 = [mem16]
1179 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1180 "cmovne\t{$src2, $dst|$dst, $src2}",
1181 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1182 X86_COND_NE, EFLAGS))]>,
1184 def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, GR32 = [mem32]
1185 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1186 "cmovne\t{$src2, $dst|$dst, $src2}",
1187 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1188 X86_COND_NE, EFLAGS))]>,
1190 def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, GR16 = [mem16]
1191 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1192 "cmovbe\t{$src2, $dst|$dst, $src2}",
1193 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1194 X86_COND_BE, EFLAGS))]>,
1196 def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, GR32 = [mem32]
1197 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1198 "cmovbe\t{$src2, $dst|$dst, $src2}",
1199 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1200 X86_COND_BE, EFLAGS))]>,
1202 def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, GR16 = [mem16]
1203 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1204 "cmova\t{$src2, $dst|$dst, $src2}",
1205 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1206 X86_COND_A, EFLAGS))]>,
1208 def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, GR32 = [mem32]
1209 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1210 "cmova\t{$src2, $dst|$dst, $src2}",
1211 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1212 X86_COND_A, EFLAGS))]>,
1214 def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, GR16 = [mem16]
1215 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1216 "cmovl\t{$src2, $dst|$dst, $src2}",
1217 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1218 X86_COND_L, EFLAGS))]>,
1220 def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, GR32 = [mem32]
1221 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1222 "cmovl\t{$src2, $dst|$dst, $src2}",
1223 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1224 X86_COND_L, EFLAGS))]>,
1226 def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, GR16 = [mem16]
1227 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1228 "cmovge\t{$src2, $dst|$dst, $src2}",
1229 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1230 X86_COND_GE, EFLAGS))]>,
1232 def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, GR32 = [mem32]
1233 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1234 "cmovge\t{$src2, $dst|$dst, $src2}",
1235 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1236 X86_COND_GE, EFLAGS))]>,
1238 def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, GR16 = [mem16]
1239 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1240 "cmovle\t{$src2, $dst|$dst, $src2}",
1241 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1242 X86_COND_LE, EFLAGS))]>,
1244 def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, GR32 = [mem32]
1245 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1246 "cmovle\t{$src2, $dst|$dst, $src2}",
1247 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1248 X86_COND_LE, EFLAGS))]>,
1250 def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, GR16 = [mem16]
1251 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1252 "cmovg\t{$src2, $dst|$dst, $src2}",
1253 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1254 X86_COND_G, EFLAGS))]>,
1256 def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, GR32 = [mem32]
1257 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1258 "cmovg\t{$src2, $dst|$dst, $src2}",
1259 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1260 X86_COND_G, EFLAGS))]>,
1262 def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, GR16 = [mem16]
1263 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1264 "cmovs\t{$src2, $dst|$dst, $src2}",
1265 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1266 X86_COND_S, EFLAGS))]>,
1268 def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, GR32 = [mem32]
1269 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1270 "cmovs\t{$src2, $dst|$dst, $src2}",
1271 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1272 X86_COND_S, EFLAGS))]>,
1274 def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, GR16 = [mem16]
1275 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1276 "cmovns\t{$src2, $dst|$dst, $src2}",
1277 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1278 X86_COND_NS, EFLAGS))]>,
1280 def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, GR32 = [mem32]
1281 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1282 "cmovns\t{$src2, $dst|$dst, $src2}",
1283 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1284 X86_COND_NS, EFLAGS))]>,
1286 def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, GR16 = [mem16]
1287 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1288 "cmovp\t{$src2, $dst|$dst, $src2}",
1289 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1290 X86_COND_P, EFLAGS))]>,
1292 def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, GR32 = [mem32]
1293 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1294 "cmovp\t{$src2, $dst|$dst, $src2}",
1295 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1296 X86_COND_P, EFLAGS))]>,
1298 def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, GR16 = [mem16]
1299 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1300 "cmovnp\t{$src2, $dst|$dst, $src2}",
1301 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1302 X86_COND_NP, EFLAGS))]>,
1304 def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, GR32 = [mem32]
1305 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1306 "cmovnp\t{$src2, $dst|$dst, $src2}",
1307 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1308 X86_COND_NP, EFLAGS))]>,
1310 def CMOVO16rm : I<0x40, MRMSrcMem, // if overflow, GR16 = [mem16]
1311 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1312 "cmovo\t{$src2, $dst|$dst, $src2}",
1313 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1314 X86_COND_O, EFLAGS))]>,
1316 def CMOVO32rm : I<0x40, MRMSrcMem, // if overflow, GR32 = [mem32]
1317 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1318 "cmovo\t{$src2, $dst|$dst, $src2}",
1319 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1320 X86_COND_O, EFLAGS))]>,
1322 def CMOVNO16rm : I<0x41, MRMSrcMem, // if !overflow, GR16 = [mem16]
1323 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1324 "cmovno\t{$src2, $dst|$dst, $src2}",
1325 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
1326 X86_COND_NO, EFLAGS))]>,
1328 def CMOVNO32rm : I<0x41, MRMSrcMem, // if !overflow, GR32 = [mem32]
1329 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1330 "cmovno\t{$src2, $dst|$dst, $src2}",
1331 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
1332 X86_COND_NO, EFLAGS))]>,
1334 } // Uses = [EFLAGS]
1337 // unary instructions
1338 let CodeSize = 2 in {
1339 let Defs = [EFLAGS] in {
1340 def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src), "neg{b}\t$dst",
1341 [(set GR8:$dst, (ineg GR8:$src)),
1342 (implicit EFLAGS)]>;
1343 def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src), "neg{w}\t$dst",
1344 [(set GR16:$dst, (ineg GR16:$src)),
1345 (implicit EFLAGS)]>, OpSize;
1346 def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src), "neg{l}\t$dst",
1347 [(set GR32:$dst, (ineg GR32:$src)),
1348 (implicit EFLAGS)]>;
1349 let isTwoAddress = 0 in {
1350 def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), "neg{b}\t$dst",
1351 [(store (ineg (loadi8 addr:$dst)), addr:$dst),
1352 (implicit EFLAGS)]>;
1353 def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), "neg{w}\t$dst",
1354 [(store (ineg (loadi16 addr:$dst)), addr:$dst),
1355 (implicit EFLAGS)]>, OpSize;
1356 def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), "neg{l}\t$dst",
1357 [(store (ineg (loadi32 addr:$dst)), addr:$dst),
1358 (implicit EFLAGS)]>;
1360 } // Defs = [EFLAGS]
1362 // Match xor -1 to not. Favors these over a move imm + xor to save code size.
1363 let AddedComplexity = 15 in {
1364 def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src), "not{b}\t$dst",
1365 [(set GR8:$dst, (not GR8:$src))]>;
1366 def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src), "not{w}\t$dst",
1367 [(set GR16:$dst, (not GR16:$src))]>, OpSize;
1368 def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src), "not{l}\t$dst",
1369 [(set GR32:$dst, (not GR32:$src))]>;
1371 let isTwoAddress = 0 in {
1372 def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), "not{b}\t$dst",
1373 [(store (not (loadi8 addr:$dst)), addr:$dst)]>;
1374 def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), "not{w}\t$dst",
1375 [(store (not (loadi16 addr:$dst)), addr:$dst)]>, OpSize;
1376 def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), "not{l}\t$dst",
1377 [(store (not (loadi32 addr:$dst)), addr:$dst)]>;
1381 // TODO: inc/dec is slow for P4, but fast for Pentium-M.
1382 let Defs = [EFLAGS] in {
1384 def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src), "inc{b}\t$dst",
1385 [(set GR8:$dst, (add GR8:$src, 1)),
1386 (implicit EFLAGS)]>;
1387 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1388 def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
1389 [(set GR16:$dst, (add GR16:$src, 1)),
1390 (implicit EFLAGS)]>,
1391 OpSize, Requires<[In32BitMode]>;
1392 def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
1393 [(set GR32:$dst, (add GR32:$src, 1)),
1394 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1396 let isTwoAddress = 0, CodeSize = 2 in {
1397 def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst",
1398 [(store (add (loadi8 addr:$dst), 1), addr:$dst),
1399 (implicit EFLAGS)]>;
1400 def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
1401 [(store (add (loadi16 addr:$dst), 1), addr:$dst),
1402 (implicit EFLAGS)]>,
1403 OpSize, Requires<[In32BitMode]>;
1404 def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
1405 [(store (add (loadi32 addr:$dst), 1), addr:$dst),
1406 (implicit EFLAGS)]>,
1407 Requires<[In32BitMode]>;
1411 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src), "dec{b}\t$dst",
1412 [(set GR8:$dst, (add GR8:$src, -1)),
1413 (implicit EFLAGS)]>;
1414 let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
1415 def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
1416 [(set GR16:$dst, (add GR16:$src, -1)),
1417 (implicit EFLAGS)]>,
1418 OpSize, Requires<[In32BitMode]>;
1419 def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
1420 [(set GR32:$dst, (add GR32:$src, -1)),
1421 (implicit EFLAGS)]>, Requires<[In32BitMode]>;
1424 let isTwoAddress = 0, CodeSize = 2 in {
1425 def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst",
1426 [(store (add (loadi8 addr:$dst), -1), addr:$dst),
1427 (implicit EFLAGS)]>;
1428 def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
1429 [(store (add (loadi16 addr:$dst), -1), addr:$dst),
1430 (implicit EFLAGS)]>,
1431 OpSize, Requires<[In32BitMode]>;
1432 def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
1433 [(store (add (loadi32 addr:$dst), -1), addr:$dst),
1434 (implicit EFLAGS)]>,
1435 Requires<[In32BitMode]>;
1437 } // Defs = [EFLAGS]
1439 // Logical operators...
1440 let Defs = [EFLAGS] in {
1441 let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y
1442 def AND8rr : I<0x20, MRMDestReg,
1443 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1444 "and{b}\t{$src2, $dst|$dst, $src2}",
1445 [(set GR8:$dst, (and GR8:$src1, GR8:$src2)),
1446 (implicit EFLAGS)]>;
1447 def AND16rr : I<0x21, MRMDestReg,
1448 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1449 "and{w}\t{$src2, $dst|$dst, $src2}",
1450 [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
1451 (implicit EFLAGS)]>, OpSize;
1452 def AND32rr : I<0x21, MRMDestReg,
1453 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1454 "and{l}\t{$src2, $dst|$dst, $src2}",
1455 [(set GR32:$dst, (and GR32:$src1, GR32:$src2)),
1456 (implicit EFLAGS)]>;
1459 def AND8rm : I<0x22, MRMSrcMem,
1460 (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1461 "and{b}\t{$src2, $dst|$dst, $src2}",
1462 [(set GR8:$dst, (and GR8:$src1, (loadi8 addr:$src2))),
1463 (implicit EFLAGS)]>;
1464 def AND16rm : I<0x23, MRMSrcMem,
1465 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1466 "and{w}\t{$src2, $dst|$dst, $src2}",
1467 [(set GR16:$dst, (and GR16:$src1, (loadi16 addr:$src2))),
1468 (implicit EFLAGS)]>, OpSize;
1469 def AND32rm : I<0x23, MRMSrcMem,
1470 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1471 "and{l}\t{$src2, $dst|$dst, $src2}",
1472 [(set GR32:$dst, (and GR32:$src1, (loadi32 addr:$src2))),
1473 (implicit EFLAGS)]>;
1475 def AND8ri : Ii8<0x80, MRM4r,
1476 (outs GR8 :$dst), (ins GR8 :$src1, i8imm :$src2),
1477 "and{b}\t{$src2, $dst|$dst, $src2}",
1478 [(set GR8:$dst, (and GR8:$src1, imm:$src2)),
1479 (implicit EFLAGS)]>;
1480 def AND16ri : Ii16<0x81, MRM4r,
1481 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1482 "and{w}\t{$src2, $dst|$dst, $src2}",
1483 [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
1484 (implicit EFLAGS)]>, OpSize;
1485 def AND32ri : Ii32<0x81, MRM4r,
1486 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1487 "and{l}\t{$src2, $dst|$dst, $src2}",
1488 [(set GR32:$dst, (and GR32:$src1, imm:$src2)),
1489 (implicit EFLAGS)]>;
1490 def AND16ri8 : Ii8<0x83, MRM4r,
1491 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1492 "and{w}\t{$src2, $dst|$dst, $src2}",
1493 [(set GR16:$dst, (and GR16:$src1, i16immSExt8:$src2)),
1494 (implicit EFLAGS)]>,
1496 def AND32ri8 : Ii8<0x83, MRM4r,
1497 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1498 "and{l}\t{$src2, $dst|$dst, $src2}",
1499 [(set GR32:$dst, (and GR32:$src1, i32immSExt8:$src2)),
1500 (implicit EFLAGS)]>;
1502 let isTwoAddress = 0 in {
1503 def AND8mr : I<0x20, MRMDestMem,
1504 (outs), (ins i8mem :$dst, GR8 :$src),
1505 "and{b}\t{$src, $dst|$dst, $src}",
1506 [(store (and (load addr:$dst), GR8:$src), addr:$dst),
1507 (implicit EFLAGS)]>;
1508 def AND16mr : I<0x21, MRMDestMem,
1509 (outs), (ins i16mem:$dst, GR16:$src),
1510 "and{w}\t{$src, $dst|$dst, $src}",
1511 [(store (and (load addr:$dst), GR16:$src), addr:$dst),
1512 (implicit EFLAGS)]>,
1514 def AND32mr : I<0x21, MRMDestMem,
1515 (outs), (ins i32mem:$dst, GR32:$src),
1516 "and{l}\t{$src, $dst|$dst, $src}",
1517 [(store (and (load addr:$dst), GR32:$src), addr:$dst),
1518 (implicit EFLAGS)]>;
1519 def AND8mi : Ii8<0x80, MRM4m,
1520 (outs), (ins i8mem :$dst, i8imm :$src),
1521 "and{b}\t{$src, $dst|$dst, $src}",
1522 [(store (and (loadi8 addr:$dst), imm:$src), addr:$dst),
1523 (implicit EFLAGS)]>;
1524 def AND16mi : Ii16<0x81, MRM4m,
1525 (outs), (ins i16mem:$dst, i16imm:$src),
1526 "and{w}\t{$src, $dst|$dst, $src}",
1527 [(store (and (loadi16 addr:$dst), imm:$src), addr:$dst),
1528 (implicit EFLAGS)]>,
1530 def AND32mi : Ii32<0x81, MRM4m,
1531 (outs), (ins i32mem:$dst, i32imm:$src),
1532 "and{l}\t{$src, $dst|$dst, $src}",
1533 [(store (and (loadi32 addr:$dst), imm:$src), addr:$dst),
1534 (implicit EFLAGS)]>;
1535 def AND16mi8 : Ii8<0x83, MRM4m,
1536 (outs), (ins i16mem:$dst, i16i8imm :$src),
1537 "and{w}\t{$src, $dst|$dst, $src}",
1538 [(store (and (load addr:$dst), i16immSExt8:$src), addr:$dst),
1539 (implicit EFLAGS)]>,
1541 def AND32mi8 : Ii8<0x83, MRM4m,
1542 (outs), (ins i32mem:$dst, i32i8imm :$src),
1543 "and{l}\t{$src, $dst|$dst, $src}",
1544 [(store (and (load addr:$dst), i32immSExt8:$src), addr:$dst),
1545 (implicit EFLAGS)]>;
1549 let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y
1550 def OR8rr : I<0x08, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1551 "or{b}\t{$src2, $dst|$dst, $src2}",
1552 [(set GR8:$dst, (or GR8:$src1, GR8:$src2)),
1553 (implicit EFLAGS)]>;
1554 def OR16rr : I<0x09, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1555 "or{w}\t{$src2, $dst|$dst, $src2}",
1556 [(set GR16:$dst, (or GR16:$src1, GR16:$src2)),
1557 (implicit EFLAGS)]>, OpSize;
1558 def OR32rr : I<0x09, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1559 "or{l}\t{$src2, $dst|$dst, $src2}",
1560 [(set GR32:$dst, (or GR32:$src1, GR32:$src2)),
1561 (implicit EFLAGS)]>;
1563 def OR8rm : I<0x0A, MRMSrcMem , (outs GR8 :$dst), (ins GR8 :$src1, i8mem :$src2),
1564 "or{b}\t{$src2, $dst|$dst, $src2}",
1565 [(set GR8:$dst, (or GR8:$src1, (load addr:$src2))),
1566 (implicit EFLAGS)]>;
1567 def OR16rm : I<0x0B, MRMSrcMem , (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1568 "or{w}\t{$src2, $dst|$dst, $src2}",
1569 [(set GR16:$dst, (or GR16:$src1, (load addr:$src2))),
1570 (implicit EFLAGS)]>, OpSize;
1571 def OR32rm : I<0x0B, MRMSrcMem , (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1572 "or{l}\t{$src2, $dst|$dst, $src2}",
1573 [(set GR32:$dst, (or GR32:$src1, (load addr:$src2))),
1574 (implicit EFLAGS)]>;
1576 def OR8ri : Ii8 <0x80, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1577 "or{b}\t{$src2, $dst|$dst, $src2}",
1578 [(set GR8:$dst, (or GR8:$src1, imm:$src2)),
1579 (implicit EFLAGS)]>;
1580 def OR16ri : Ii16<0x81, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1581 "or{w}\t{$src2, $dst|$dst, $src2}",
1582 [(set GR16:$dst, (or GR16:$src1, imm:$src2)),
1583 (implicit EFLAGS)]>, OpSize;
1584 def OR32ri : Ii32<0x81, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1585 "or{l}\t{$src2, $dst|$dst, $src2}",
1586 [(set GR32:$dst, (or GR32:$src1, imm:$src2)),
1587 (implicit EFLAGS)]>;
1589 def OR16ri8 : Ii8<0x83, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1590 "or{w}\t{$src2, $dst|$dst, $src2}",
1591 [(set GR16:$dst, (or GR16:$src1, i16immSExt8:$src2)),
1592 (implicit EFLAGS)]>, OpSize;
1593 def OR32ri8 : Ii8<0x83, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1594 "or{l}\t{$src2, $dst|$dst, $src2}",
1595 [(set GR32:$dst, (or GR32:$src1, i32immSExt8:$src2)),
1596 (implicit EFLAGS)]>;
1597 let isTwoAddress = 0 in {
1598 def OR8mr : I<0x08, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1599 "or{b}\t{$src, $dst|$dst, $src}",
1600 [(store (or (load addr:$dst), GR8:$src), addr:$dst),
1601 (implicit EFLAGS)]>;
1602 def OR16mr : I<0x09, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1603 "or{w}\t{$src, $dst|$dst, $src}",
1604 [(store (or (load addr:$dst), GR16:$src), addr:$dst),
1605 (implicit EFLAGS)]>, OpSize;
1606 def OR32mr : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1607 "or{l}\t{$src, $dst|$dst, $src}",
1608 [(store (or (load addr:$dst), GR32:$src), addr:$dst),
1609 (implicit EFLAGS)]>;
1610 def OR8mi : Ii8<0x80, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
1611 "or{b}\t{$src, $dst|$dst, $src}",
1612 [(store (or (loadi8 addr:$dst), imm:$src), addr:$dst),
1613 (implicit EFLAGS)]>;
1614 def OR16mi : Ii16<0x81, MRM1m, (outs), (ins i16mem:$dst, i16imm:$src),
1615 "or{w}\t{$src, $dst|$dst, $src}",
1616 [(store (or (loadi16 addr:$dst), imm:$src), addr:$dst),
1617 (implicit EFLAGS)]>,
1619 def OR32mi : Ii32<0x81, MRM1m, (outs), (ins i32mem:$dst, i32imm:$src),
1620 "or{l}\t{$src, $dst|$dst, $src}",
1621 [(store (or (loadi32 addr:$dst), imm:$src), addr:$dst),
1622 (implicit EFLAGS)]>;
1623 def OR16mi8 : Ii8<0x83, MRM1m, (outs), (ins i16mem:$dst, i16i8imm:$src),
1624 "or{w}\t{$src, $dst|$dst, $src}",
1625 [(store (or (load addr:$dst), i16immSExt8:$src), addr:$dst),
1626 (implicit EFLAGS)]>,
1628 def OR32mi8 : Ii8<0x83, MRM1m, (outs), (ins i32mem:$dst, i32i8imm:$src),
1629 "or{l}\t{$src, $dst|$dst, $src}",
1630 [(store (or (load addr:$dst), i32immSExt8:$src), addr:$dst),
1631 (implicit EFLAGS)]>;
1632 } // isTwoAddress = 0
1635 let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y
1636 def XOR8rr : I<0x30, MRMDestReg,
1637 (outs GR8 :$dst), (ins GR8 :$src1, GR8 :$src2),
1638 "xor{b}\t{$src2, $dst|$dst, $src2}",
1639 [(set GR8:$dst, (xor GR8:$src1, GR8:$src2)),
1640 (implicit EFLAGS)]>;
1641 def XOR16rr : I<0x31, MRMDestReg,
1642 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1643 "xor{w}\t{$src2, $dst|$dst, $src2}",
1644 [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
1645 (implicit EFLAGS)]>, OpSize;
1646 def XOR32rr : I<0x31, MRMDestReg,
1647 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1648 "xor{l}\t{$src2, $dst|$dst, $src2}",
1649 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2)),
1650 (implicit EFLAGS)]>;
1651 } // isCommutable = 1
1653 def XOR8rm : I<0x32, MRMSrcMem ,
1654 (outs GR8 :$dst), (ins GR8:$src1, i8mem :$src2),
1655 "xor{b}\t{$src2, $dst|$dst, $src2}",
1656 [(set GR8:$dst, (xor GR8:$src1, (load addr:$src2))),
1657 (implicit EFLAGS)]>;
1658 def XOR16rm : I<0x33, MRMSrcMem ,
1659 (outs GR16:$dst), (ins GR16:$src1, i16mem:$src2),
1660 "xor{w}\t{$src2, $dst|$dst, $src2}",
1661 [(set GR16:$dst, (xor GR16:$src1, (load addr:$src2))),
1662 (implicit EFLAGS)]>,
1664 def XOR32rm : I<0x33, MRMSrcMem ,
1665 (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
1666 "xor{l}\t{$src2, $dst|$dst, $src2}",
1667 [(set GR32:$dst, (xor GR32:$src1, (load addr:$src2))),
1668 (implicit EFLAGS)]>;
1670 def XOR8ri : Ii8<0x80, MRM6r,
1671 (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1672 "xor{b}\t{$src2, $dst|$dst, $src2}",
1673 [(set GR8:$dst, (xor GR8:$src1, imm:$src2)),
1674 (implicit EFLAGS)]>;
1675 def XOR16ri : Ii16<0x81, MRM6r,
1676 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1677 "xor{w}\t{$src2, $dst|$dst, $src2}",
1678 [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
1679 (implicit EFLAGS)]>, OpSize;
1680 def XOR32ri : Ii32<0x81, MRM6r,
1681 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1682 "xor{l}\t{$src2, $dst|$dst, $src2}",
1683 [(set GR32:$dst, (xor GR32:$src1, imm:$src2)),
1684 (implicit EFLAGS)]>;
1685 def XOR16ri8 : Ii8<0x83, MRM6r,
1686 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1687 "xor{w}\t{$src2, $dst|$dst, $src2}",
1688 [(set GR16:$dst, (xor GR16:$src1, i16immSExt8:$src2)),
1689 (implicit EFLAGS)]>,
1691 def XOR32ri8 : Ii8<0x83, MRM6r,
1692 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1693 "xor{l}\t{$src2, $dst|$dst, $src2}",
1694 [(set GR32:$dst, (xor GR32:$src1, i32immSExt8:$src2)),
1695 (implicit EFLAGS)]>;
1697 let isTwoAddress = 0 in {
1698 def XOR8mr : I<0x30, MRMDestMem,
1699 (outs), (ins i8mem :$dst, GR8 :$src),
1700 "xor{b}\t{$src, $dst|$dst, $src}",
1701 [(store (xor (load addr:$dst), GR8:$src), addr:$dst),
1702 (implicit EFLAGS)]>;
1703 def XOR16mr : I<0x31, MRMDestMem,
1704 (outs), (ins i16mem:$dst, GR16:$src),
1705 "xor{w}\t{$src, $dst|$dst, $src}",
1706 [(store (xor (load addr:$dst), GR16:$src), addr:$dst),
1707 (implicit EFLAGS)]>,
1709 def XOR32mr : I<0x31, MRMDestMem,
1710 (outs), (ins i32mem:$dst, GR32:$src),
1711 "xor{l}\t{$src, $dst|$dst, $src}",
1712 [(store (xor (load addr:$dst), GR32:$src), addr:$dst),
1713 (implicit EFLAGS)]>;
1714 def XOR8mi : Ii8<0x80, MRM6m,
1715 (outs), (ins i8mem :$dst, i8imm :$src),
1716 "xor{b}\t{$src, $dst|$dst, $src}",
1717 [(store (xor (loadi8 addr:$dst), imm:$src), addr:$dst),
1718 (implicit EFLAGS)]>;
1719 def XOR16mi : Ii16<0x81, MRM6m,
1720 (outs), (ins i16mem:$dst, i16imm:$src),
1721 "xor{w}\t{$src, $dst|$dst, $src}",
1722 [(store (xor (loadi16 addr:$dst), imm:$src), addr:$dst),
1723 (implicit EFLAGS)]>,
1725 def XOR32mi : Ii32<0x81, MRM6m,
1726 (outs), (ins i32mem:$dst, i32imm:$src),
1727 "xor{l}\t{$src, $dst|$dst, $src}",
1728 [(store (xor (loadi32 addr:$dst), imm:$src), addr:$dst),
1729 (implicit EFLAGS)]>;
1730 def XOR16mi8 : Ii8<0x83, MRM6m,
1731 (outs), (ins i16mem:$dst, i16i8imm :$src),
1732 "xor{w}\t{$src, $dst|$dst, $src}",
1733 [(store (xor (load addr:$dst), i16immSExt8:$src), addr:$dst),
1734 (implicit EFLAGS)]>,
1736 def XOR32mi8 : Ii8<0x83, MRM6m,
1737 (outs), (ins i32mem:$dst, i32i8imm :$src),
1738 "xor{l}\t{$src, $dst|$dst, $src}",
1739 [(store (xor (load addr:$dst), i32immSExt8:$src), addr:$dst),
1740 (implicit EFLAGS)]>;
1741 } // isTwoAddress = 0
1742 } // Defs = [EFLAGS]
1744 // Shift instructions
1745 let Defs = [EFLAGS] in {
1746 let Uses = [CL] in {
1747 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
1748 "shl{b}\t{%cl, $dst|$dst, CL}",
1749 [(set GR8:$dst, (shl GR8:$src, CL))]>;
1750 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
1751 "shl{w}\t{%cl, $dst|$dst, CL}",
1752 [(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
1753 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
1754 "shl{l}\t{%cl, $dst|$dst, CL}",
1755 [(set GR32:$dst, (shl GR32:$src, CL))]>;
1758 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1759 "shl{b}\t{$src2, $dst|$dst, $src2}",
1760 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
1761 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
1762 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1763 "shl{w}\t{$src2, $dst|$dst, $src2}",
1764 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1765 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1766 "shl{l}\t{$src2, $dst|$dst, $src2}",
1767 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>;
1768 // NOTE: We don't use shifts of a register by one, because 'add reg,reg' is
1770 } // isConvertibleToThreeAddress = 1
1772 let isTwoAddress = 0 in {
1773 let Uses = [CL] in {
1774 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
1775 "shl{b}\t{%cl, $dst|$dst, CL}",
1776 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
1777 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
1778 "shl{w}\t{%cl, $dst|$dst, CL}",
1779 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1780 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
1781 "shl{l}\t{%cl, $dst|$dst, CL}",
1782 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
1784 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
1785 "shl{b}\t{$src, $dst|$dst, $src}",
1786 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1787 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
1788 "shl{w}\t{$src, $dst|$dst, $src}",
1789 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1791 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
1792 "shl{l}\t{$src, $dst|$dst, $src}",
1793 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1796 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
1798 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1799 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
1801 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1803 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
1805 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1808 let Uses = [CL] in {
1809 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
1810 "shr{b}\t{%cl, $dst|$dst, CL}",
1811 [(set GR8:$dst, (srl GR8:$src, CL))]>;
1812 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
1813 "shr{w}\t{%cl, $dst|$dst, CL}",
1814 [(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
1815 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
1816 "shr{l}\t{%cl, $dst|$dst, CL}",
1817 [(set GR32:$dst, (srl GR32:$src, CL))]>;
1820 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
1821 "shr{b}\t{$src2, $dst|$dst, $src2}",
1822 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
1823 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1824 "shr{w}\t{$src2, $dst|$dst, $src2}",
1825 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1826 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1827 "shr{l}\t{$src2, $dst|$dst, $src2}",
1828 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>;
1831 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
1833 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
1834 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
1836 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
1837 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
1839 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>;
1841 let isTwoAddress = 0 in {
1842 let Uses = [CL] in {
1843 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
1844 "shr{b}\t{%cl, $dst|$dst, CL}",
1845 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
1846 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
1847 "shr{w}\t{%cl, $dst|$dst, CL}",
1848 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
1850 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
1851 "shr{l}\t{%cl, $dst|$dst, CL}",
1852 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
1854 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
1855 "shr{b}\t{$src, $dst|$dst, $src}",
1856 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1857 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
1858 "shr{w}\t{$src, $dst|$dst, $src}",
1859 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1861 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
1862 "shr{l}\t{$src, $dst|$dst, $src}",
1863 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1866 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
1868 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1869 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
1871 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,OpSize;
1872 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
1874 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1877 let Uses = [CL] in {
1878 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
1879 "sar{b}\t{%cl, $dst|$dst, CL}",
1880 [(set GR8:$dst, (sra GR8:$src, CL))]>;
1881 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
1882 "sar{w}\t{%cl, $dst|$dst, CL}",
1883 [(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
1884 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
1885 "sar{l}\t{%cl, $dst|$dst, CL}",
1886 [(set GR32:$dst, (sra GR32:$src, CL))]>;
1889 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1890 "sar{b}\t{$src2, $dst|$dst, $src2}",
1891 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
1892 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1893 "sar{w}\t{$src2, $dst|$dst, $src2}",
1894 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
1896 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1897 "sar{l}\t{$src2, $dst|$dst, $src2}",
1898 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>;
1901 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
1903 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
1904 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
1906 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize;
1907 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
1909 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>;
1911 let isTwoAddress = 0 in {
1912 let Uses = [CL] in {
1913 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
1914 "sar{b}\t{%cl, $dst|$dst, CL}",
1915 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
1916 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
1917 "sar{w}\t{%cl, $dst|$dst, CL}",
1918 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1919 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
1920 "sar{l}\t{%cl, $dst|$dst, CL}",
1921 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
1923 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
1924 "sar{b}\t{$src, $dst|$dst, $src}",
1925 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1926 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
1927 "sar{w}\t{$src, $dst|$dst, $src}",
1928 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
1930 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
1931 "sar{l}\t{$src, $dst|$dst, $src}",
1932 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1935 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
1937 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
1938 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
1940 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
1942 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
1944 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
1947 // Rotate instructions
1948 // FIXME: provide shorter instructions when imm8 == 1
1949 let Uses = [CL] in {
1950 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
1951 "rol{b}\t{%cl, $dst|$dst, CL}",
1952 [(set GR8:$dst, (rotl GR8:$src, CL))]>;
1953 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
1954 "rol{w}\t{%cl, $dst|$dst, CL}",
1955 [(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
1956 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
1957 "rol{l}\t{%cl, $dst|$dst, CL}",
1958 [(set GR32:$dst, (rotl GR32:$src, CL))]>;
1961 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
1962 "rol{b}\t{$src2, $dst|$dst, $src2}",
1963 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
1964 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
1965 "rol{w}\t{$src2, $dst|$dst, $src2}",
1966 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
1967 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
1968 "rol{l}\t{$src2, $dst|$dst, $src2}",
1969 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>;
1972 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
1974 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
1975 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
1977 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize;
1978 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
1980 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>;
1982 let isTwoAddress = 0 in {
1983 let Uses = [CL] in {
1984 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
1985 "rol{b}\t{%cl, $dst|$dst, CL}",
1986 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
1987 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
1988 "rol{w}\t{%cl, $dst|$dst, CL}",
1989 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
1990 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
1991 "rol{l}\t{%cl, $dst|$dst, CL}",
1992 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
1994 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
1995 "rol{b}\t{$src, $dst|$dst, $src}",
1996 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
1997 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src),
1998 "rol{w}\t{$src, $dst|$dst, $src}",
1999 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2001 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src),
2002 "rol{l}\t{$src, $dst|$dst, $src}",
2003 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2006 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
2008 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2009 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
2011 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2013 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
2015 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2018 let Uses = [CL] in {
2019 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
2020 "ror{b}\t{%cl, $dst|$dst, CL}",
2021 [(set GR8:$dst, (rotr GR8:$src, CL))]>;
2022 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
2023 "ror{w}\t{%cl, $dst|$dst, CL}",
2024 [(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
2025 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
2026 "ror{l}\t{%cl, $dst|$dst, CL}",
2027 [(set GR32:$dst, (rotr GR32:$src, CL))]>;
2030 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
2031 "ror{b}\t{$src2, $dst|$dst, $src2}",
2032 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
2033 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
2034 "ror{w}\t{$src2, $dst|$dst, $src2}",
2035 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>, OpSize;
2036 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
2037 "ror{l}\t{$src2, $dst|$dst, $src2}",
2038 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>;
2041 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
2043 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
2044 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
2046 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize;
2047 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
2049 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>;
2051 let isTwoAddress = 0 in {
2052 let Uses = [CL] in {
2053 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
2054 "ror{b}\t{%cl, $dst|$dst, CL}",
2055 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
2056 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
2057 "ror{w}\t{%cl, $dst|$dst, CL}",
2058 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
2059 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
2060 "ror{l}\t{%cl, $dst|$dst, CL}",
2061 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
2063 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
2064 "ror{b}\t{$src, $dst|$dst, $src}",
2065 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2066 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
2067 "ror{w}\t{$src, $dst|$dst, $src}",
2068 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)]>,
2070 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
2071 "ror{l}\t{$src, $dst|$dst, $src}",
2072 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
2075 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
2077 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)]>;
2078 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
2080 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)]>,
2082 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
2084 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)]>;
2089 // Double shift instructions (generalizations of rotate)
2090 let Uses = [CL] in {
2091 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2092 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2093 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
2094 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
2095 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2096 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
2097 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2098 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2099 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
2101 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
2102 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2103 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
2107 let isCommutable = 1 in { // These instructions commute to each other.
2108 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
2109 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2110 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2111 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
2114 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
2115 (outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$src3),
2116 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2117 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
2120 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
2121 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2122 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2123 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
2126 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
2127 (outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$src3),
2128 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2129 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
2134 let isTwoAddress = 0 in {
2135 let Uses = [CL] in {
2136 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2137 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2138 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
2140 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2141 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2142 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
2145 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
2146 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2147 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2148 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
2149 (i8 imm:$src3)), addr:$dst)]>,
2151 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
2152 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
2153 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2154 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
2155 (i8 imm:$src3)), addr:$dst)]>,
2158 let Uses = [CL] in {
2159 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2160 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2161 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
2162 addr:$dst)]>, TB, OpSize;
2163 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2164 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
2165 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
2166 addr:$dst)]>, TB, OpSize;
2168 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
2169 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2170 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2171 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
2172 (i8 imm:$src3)), addr:$dst)]>,
2174 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
2175 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
2176 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2177 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
2178 (i8 imm:$src3)), addr:$dst)]>,
2181 } // Defs = [EFLAGS]
2185 let Defs = [EFLAGS] in {
2186 let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y
2187 // Register-Register Addition
2188 def ADD8rr : I<0x00, MRMDestReg, (outs GR8 :$dst),
2189 (ins GR8 :$src1, GR8 :$src2),
2190 "add{b}\t{$src2, $dst|$dst, $src2}",
2191 [(set GR8:$dst, (add GR8:$src1, GR8:$src2)),
2192 (implicit EFLAGS)]>;
2194 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2195 // Register-Register Addition
2196 def ADD16rr : I<0x01, MRMDestReg, (outs GR16:$dst),
2197 (ins GR16:$src1, GR16:$src2),
2198 "add{w}\t{$src2, $dst|$dst, $src2}",
2199 [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
2200 (implicit EFLAGS)]>, OpSize;
2201 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),
2202 (ins GR32:$src1, GR32:$src2),
2203 "add{l}\t{$src2, $dst|$dst, $src2}",
2204 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
2205 (implicit EFLAGS)]>;
2206 } // end isConvertibleToThreeAddress
2207 } // end isCommutable
2209 // Register-Memory Addition
2210 def ADD8rm : I<0x02, MRMSrcMem, (outs GR8 :$dst),
2211 (ins GR8 :$src1, i8mem :$src2),
2212 "add{b}\t{$src2, $dst|$dst, $src2}",
2213 [(set GR8:$dst, (add GR8:$src1, (load addr:$src2))),
2214 (implicit EFLAGS)]>;
2215 def ADD16rm : I<0x03, MRMSrcMem, (outs GR16:$dst),
2216 (ins GR16:$src1, i16mem:$src2),
2217 "add{w}\t{$src2, $dst|$dst, $src2}",
2218 [(set GR16:$dst, (add GR16:$src1, (load addr:$src2))),
2219 (implicit EFLAGS)]>, OpSize;
2220 def ADD32rm : I<0x03, MRMSrcMem, (outs GR32:$dst),
2221 (ins GR32:$src1, i32mem:$src2),
2222 "add{l}\t{$src2, $dst|$dst, $src2}",
2223 [(set GR32:$dst, (add GR32:$src1, (load addr:$src2))),
2224 (implicit EFLAGS)]>;
2226 // Register-Integer Addition
2227 def ADD8ri : Ii8<0x80, MRM0r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2228 "add{b}\t{$src2, $dst|$dst, $src2}",
2229 [(set GR8:$dst, (add GR8:$src1, imm:$src2)),
2230 (implicit EFLAGS)]>;
2232 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
2233 // Register-Integer Addition
2234 def ADD16ri : Ii16<0x81, MRM0r, (outs GR16:$dst),
2235 (ins GR16:$src1, i16imm:$src2),
2236 "add{w}\t{$src2, $dst|$dst, $src2}",
2237 [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
2238 (implicit EFLAGS)]>, OpSize;
2239 def ADD32ri : Ii32<0x81, MRM0r, (outs GR32:$dst),
2240 (ins GR32:$src1, i32imm:$src2),
2241 "add{l}\t{$src2, $dst|$dst, $src2}",
2242 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
2243 (implicit EFLAGS)]>;
2244 def ADD16ri8 : Ii8<0x83, MRM0r, (outs GR16:$dst),
2245 (ins GR16:$src1, i16i8imm:$src2),
2246 "add{w}\t{$src2, $dst|$dst, $src2}",
2247 [(set GR16:$dst, (add GR16:$src1, i16immSExt8:$src2)),
2248 (implicit EFLAGS)]>, OpSize;
2249 def ADD32ri8 : Ii8<0x83, MRM0r, (outs GR32:$dst),
2250 (ins GR32:$src1, i32i8imm:$src2),
2251 "add{l}\t{$src2, $dst|$dst, $src2}",
2252 [(set GR32:$dst, (add GR32:$src1, i32immSExt8:$src2)),
2253 (implicit EFLAGS)]>;
2256 let isTwoAddress = 0 in {
2257 // Memory-Register Addition
2258 def ADD8mr : I<0x00, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2259 "add{b}\t{$src2, $dst|$dst, $src2}",
2260 [(store (add (load addr:$dst), GR8:$src2), addr:$dst),
2261 (implicit EFLAGS)]>;
2262 def ADD16mr : I<0x01, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2263 "add{w}\t{$src2, $dst|$dst, $src2}",
2264 [(store (add (load addr:$dst), GR16:$src2), addr:$dst),
2265 (implicit EFLAGS)]>, OpSize;
2266 def ADD32mr : I<0x01, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2267 "add{l}\t{$src2, $dst|$dst, $src2}",
2268 [(store (add (load addr:$dst), GR32:$src2), addr:$dst),
2269 (implicit EFLAGS)]>;
2270 def ADD8mi : Ii8<0x80, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src2),
2271 "add{b}\t{$src2, $dst|$dst, $src2}",
2272 [(store (add (loadi8 addr:$dst), imm:$src2), addr:$dst),
2273 (implicit EFLAGS)]>;
2274 def ADD16mi : Ii16<0x81, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src2),
2275 "add{w}\t{$src2, $dst|$dst, $src2}",
2276 [(store (add (loadi16 addr:$dst), imm:$src2), addr:$dst),
2277 (implicit EFLAGS)]>, OpSize;
2278 def ADD32mi : Ii32<0x81, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src2),
2279 "add{l}\t{$src2, $dst|$dst, $src2}",
2280 [(store (add (loadi32 addr:$dst), imm:$src2), addr:$dst),
2281 (implicit EFLAGS)]>;
2282 def ADD16mi8 : Ii8<0x83, MRM0m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2283 "add{w}\t{$src2, $dst|$dst, $src2}",
2284 [(store (add (load addr:$dst), i16immSExt8:$src2),
2286 (implicit EFLAGS)]>, OpSize;
2287 def ADD32mi8 : Ii8<0x83, MRM0m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2288 "add{l}\t{$src2, $dst|$dst, $src2}",
2289 [(store (add (load addr:$dst), i32immSExt8:$src2),
2291 (implicit EFLAGS)]>;
2294 let Uses = [EFLAGS] in {
2295 let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y
2296 def ADC8rr : I<0x10, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2297 "adc{b}\t{$src2, $dst|$dst, $src2}",
2298 [(set GR8:$dst, (adde GR8:$src1, GR8:$src2))]>;
2299 def ADC16rr : I<0x11, MRMDestReg, (outs GR16:$dst),
2300 (ins GR16:$src1, GR16:$src2),
2301 "adc{w}\t{$src2, $dst|$dst, $src2}",
2302 [(set GR16:$dst, (adde GR16:$src1, GR16:$src2))]>, OpSize;
2303 def ADC32rr : I<0x11, MRMDestReg, (outs GR32:$dst),
2304 (ins GR32:$src1, GR32:$src2),
2305 "adc{l}\t{$src2, $dst|$dst, $src2}",
2306 [(set GR32:$dst, (adde GR32:$src1, GR32:$src2))]>;
2308 def ADC8rm : I<0x12, MRMSrcMem , (outs GR8:$dst),
2309 (ins GR8:$src1, i8mem:$src2),
2310 "adc{b}\t{$src2, $dst|$dst, $src2}",
2311 [(set GR8:$dst, (adde GR8:$src1, (load addr:$src2)))]>;
2312 def ADC16rm : I<0x13, MRMSrcMem , (outs GR16:$dst),
2313 (ins GR16:$src1, i16mem:$src2),
2314 "adc{w}\t{$src2, $dst|$dst, $src2}",
2315 [(set GR16:$dst, (adde GR16:$src1, (load addr:$src2)))]>,
2317 def ADC32rm : I<0x13, MRMSrcMem , (outs GR32:$dst),
2318 (ins GR32:$src1, i32mem:$src2),
2319 "adc{l}\t{$src2, $dst|$dst, $src2}",
2320 [(set GR32:$dst, (adde GR32:$src1, (load addr:$src2)))]>;
2321 def ADC8ri : Ii8<0x80, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2322 "adc{b}\t{$src2, $dst|$dst, $src2}",
2323 [(set GR8:$dst, (adde GR8:$src1, imm:$src2))]>;
2324 def ADC16ri : Ii16<0x81, MRM2r, (outs GR16:$dst),
2325 (ins GR16:$src1, i16imm:$src2),
2326 "adc{w}\t{$src2, $dst|$dst, $src2}",
2327 [(set GR16:$dst, (adde GR16:$src1, imm:$src2))]>, OpSize;
2328 def ADC16ri8 : Ii8<0x83, MRM2r, (outs GR16:$dst),
2329 (ins GR16:$src1, i16i8imm:$src2),
2330 "adc{w}\t{$src2, $dst|$dst, $src2}",
2331 [(set GR16:$dst, (adde GR16:$src1, i16immSExt8:$src2))]>,
2333 def ADC32ri : Ii32<0x81, MRM2r, (outs GR32:$dst),
2334 (ins GR32:$src1, i32imm:$src2),
2335 "adc{l}\t{$src2, $dst|$dst, $src2}",
2336 [(set GR32:$dst, (adde GR32:$src1, imm:$src2))]>;
2337 def ADC32ri8 : Ii8<0x83, MRM2r, (outs GR32:$dst),
2338 (ins GR32:$src1, i32i8imm:$src2),
2339 "adc{l}\t{$src2, $dst|$dst, $src2}",
2340 [(set GR32:$dst, (adde GR32:$src1, i32immSExt8:$src2))]>;
2342 let isTwoAddress = 0 in {
2343 def ADC8mr : I<0x10, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2344 "adc{b}\t{$src2, $dst|$dst, $src2}",
2345 [(store (adde (load addr:$dst), GR8:$src2), addr:$dst)]>;
2346 def ADC16mr : I<0x11, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2347 "adc{w}\t{$src2, $dst|$dst, $src2}",
2348 [(store (adde (load addr:$dst), GR16:$src2), addr:$dst)]>,
2350 def ADC32mr : I<0x11, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2351 "adc{l}\t{$src2, $dst|$dst, $src2}",
2352 [(store (adde (load addr:$dst), GR32:$src2), addr:$dst)]>;
2353 def ADC8mi : Ii8<0x80, MRM2m, (outs), (ins i8mem:$dst, i8imm:$src2),
2354 "adc{b}\t{$src2, $dst|$dst, $src2}",
2355 [(store (adde (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2356 def ADC16mi : Ii16<0x81, MRM2m, (outs), (ins i16mem:$dst, i16imm:$src2),
2357 "adc{w}\t{$src2, $dst|$dst, $src2}",
2358 [(store (adde (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2360 def ADC16mi8 : Ii8<0x83, MRM2m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2361 "adc{w}\t{$src2, $dst|$dst, $src2}",
2362 [(store (adde (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2364 def ADC32mi : Ii32<0x81, MRM2m, (outs), (ins i32mem:$dst, i32imm:$src2),
2365 "adc{l}\t{$src2, $dst|$dst, $src2}",
2366 [(store (adde (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2367 def ADC32mi8 : Ii8<0x83, MRM2m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2368 "adc{l}\t{$src2, $dst|$dst, $src2}",
2369 [(store (adde (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2371 } // Uses = [EFLAGS]
2373 // Register-Register Subtraction
2374 def SUB8rr : I<0x28, MRMDestReg, (outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
2375 "sub{b}\t{$src2, $dst|$dst, $src2}",
2376 [(set GR8:$dst, (sub GR8:$src1, GR8:$src2)),
2377 (implicit EFLAGS)]>;
2378 def SUB16rr : I<0x29, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2379 "sub{w}\t{$src2, $dst|$dst, $src2}",
2380 [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
2381 (implicit EFLAGS)]>, OpSize;
2382 def SUB32rr : I<0x29, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2383 "sub{l}\t{$src2, $dst|$dst, $src2}",
2384 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2)),
2385 (implicit EFLAGS)]>;
2387 // Register-Memory Subtraction
2388 def SUB8rm : I<0x2A, MRMSrcMem, (outs GR8 :$dst),
2389 (ins GR8 :$src1, i8mem :$src2),
2390 "sub{b}\t{$src2, $dst|$dst, $src2}",
2391 [(set GR8:$dst, (sub GR8:$src1, (load addr:$src2))),
2392 (implicit EFLAGS)]>;
2393 def SUB16rm : I<0x2B, MRMSrcMem, (outs GR16:$dst),
2394 (ins GR16:$src1, i16mem:$src2),
2395 "sub{w}\t{$src2, $dst|$dst, $src2}",
2396 [(set GR16:$dst, (sub GR16:$src1, (load addr:$src2))),
2397 (implicit EFLAGS)]>, OpSize;
2398 def SUB32rm : I<0x2B, MRMSrcMem, (outs GR32:$dst),
2399 (ins GR32:$src1, i32mem:$src2),
2400 "sub{l}\t{$src2, $dst|$dst, $src2}",
2401 [(set GR32:$dst, (sub GR32:$src1, (load addr:$src2))),
2402 (implicit EFLAGS)]>;
2404 // Register-Integer Subtraction
2405 def SUB8ri : Ii8 <0x80, MRM5r, (outs GR8:$dst),
2406 (ins GR8:$src1, i8imm:$src2),
2407 "sub{b}\t{$src2, $dst|$dst, $src2}",
2408 [(set GR8:$dst, (sub GR8:$src1, imm:$src2)),
2409 (implicit EFLAGS)]>;
2410 def SUB16ri : Ii16<0x81, MRM5r, (outs GR16:$dst),
2411 (ins GR16:$src1, i16imm:$src2),
2412 "sub{w}\t{$src2, $dst|$dst, $src2}",
2413 [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
2414 (implicit EFLAGS)]>, OpSize;
2415 def SUB32ri : Ii32<0x81, MRM5r, (outs GR32:$dst),
2416 (ins GR32:$src1, i32imm:$src2),
2417 "sub{l}\t{$src2, $dst|$dst, $src2}",
2418 [(set GR32:$dst, (sub GR32:$src1, imm:$src2)),
2419 (implicit EFLAGS)]>;
2420 def SUB16ri8 : Ii8<0x83, MRM5r, (outs GR16:$dst),
2421 (ins GR16:$src1, i16i8imm:$src2),
2422 "sub{w}\t{$src2, $dst|$dst, $src2}",
2423 [(set GR16:$dst, (sub GR16:$src1, i16immSExt8:$src2)),
2424 (implicit EFLAGS)]>, OpSize;
2425 def SUB32ri8 : Ii8<0x83, MRM5r, (outs GR32:$dst),
2426 (ins GR32:$src1, i32i8imm:$src2),
2427 "sub{l}\t{$src2, $dst|$dst, $src2}",
2428 [(set GR32:$dst, (sub GR32:$src1, i32immSExt8:$src2)),
2429 (implicit EFLAGS)]>;
2431 let isTwoAddress = 0 in {
2432 // Memory-Register Subtraction
2433 def SUB8mr : I<0x28, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src2),
2434 "sub{b}\t{$src2, $dst|$dst, $src2}",
2435 [(store (sub (load addr:$dst), GR8:$src2), addr:$dst),
2436 (implicit EFLAGS)]>;
2437 def SUB16mr : I<0x29, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2438 "sub{w}\t{$src2, $dst|$dst, $src2}",
2439 [(store (sub (load addr:$dst), GR16:$src2), addr:$dst),
2440 (implicit EFLAGS)]>, OpSize;
2441 def SUB32mr : I<0x29, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2442 "sub{l}\t{$src2, $dst|$dst, $src2}",
2443 [(store (sub (load addr:$dst), GR32:$src2), addr:$dst),
2444 (implicit EFLAGS)]>;
2446 // Memory-Integer Subtraction
2447 def SUB8mi : Ii8<0x80, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src2),
2448 "sub{b}\t{$src2, $dst|$dst, $src2}",
2449 [(store (sub (loadi8 addr:$dst), imm:$src2), addr:$dst),
2450 (implicit EFLAGS)]>;
2451 def SUB16mi : Ii16<0x81, MRM5m, (outs), (ins i16mem:$dst, i16imm:$src2),
2452 "sub{w}\t{$src2, $dst|$dst, $src2}",
2453 [(store (sub (loadi16 addr:$dst), imm:$src2),addr:$dst),
2454 (implicit EFLAGS)]>, OpSize;
2455 def SUB32mi : Ii32<0x81, MRM5m, (outs), (ins i32mem:$dst, i32imm:$src2),
2456 "sub{l}\t{$src2, $dst|$dst, $src2}",
2457 [(store (sub (loadi32 addr:$dst), imm:$src2),addr:$dst),
2458 (implicit EFLAGS)]>;
2459 def SUB16mi8 : Ii8<0x83, MRM5m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2460 "sub{w}\t{$src2, $dst|$dst, $src2}",
2461 [(store (sub (load addr:$dst), i16immSExt8:$src2),
2463 (implicit EFLAGS)]>, OpSize;
2464 def SUB32mi8 : Ii8<0x83, MRM5m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2465 "sub{l}\t{$src2, $dst|$dst, $src2}",
2466 [(store (sub (load addr:$dst), i32immSExt8:$src2),
2468 (implicit EFLAGS)]>;
2471 let Uses = [EFLAGS] in {
2472 def SBB8rr : I<0x18, MRMDestReg, (outs GR8:$dst),
2473 (ins GR8:$src1, GR8:$src2),
2474 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2475 [(set GR8:$dst, (sube GR8:$src1, GR8:$src2))]>;
2476 def SBB16rr : I<0x19, MRMDestReg, (outs GR16:$dst),
2477 (ins GR16:$src1, GR16:$src2),
2478 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2479 [(set GR16:$dst, (sube GR16:$src1, GR16:$src2))]>, OpSize;
2480 def SBB32rr : I<0x19, MRMDestReg, (outs GR32:$dst),
2481 (ins GR32:$src1, GR32:$src2),
2482 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2483 [(set GR32:$dst, (sube GR32:$src1, GR32:$src2))]>;
2485 let isTwoAddress = 0 in {
2486 def SBB8mr : I<0x18, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
2487 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2488 [(store (sube (load addr:$dst), GR8:$src2), addr:$dst)]>;
2489 def SBB16mr : I<0x19, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
2490 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2491 [(store (sube (load addr:$dst), GR16:$src2), addr:$dst)]>,
2493 def SBB32mr : I<0x19, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
2494 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2495 [(store (sube (load addr:$dst), GR32:$src2), addr:$dst)]>;
2496 def SBB8mi : Ii32<0x80, MRM3m, (outs), (ins i8mem:$dst, i8imm:$src2),
2497 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2498 [(store (sube (loadi8 addr:$dst), imm:$src2), addr:$dst)]>;
2499 def SBB16mi : Ii16<0x81, MRM3m, (outs), (ins i16mem:$dst, i16imm:$src2),
2500 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2501 [(store (sube (loadi16 addr:$dst), imm:$src2), addr:$dst)]>,
2503 def SBB16mi8 : Ii8<0x83, MRM3m, (outs), (ins i16mem:$dst, i16i8imm :$src2),
2504 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2505 [(store (sube (load addr:$dst), i16immSExt8:$src2), addr:$dst)]>,
2507 def SBB32mi : Ii32<0x81, MRM3m, (outs), (ins i32mem:$dst, i32imm:$src2),
2508 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2509 [(store (sube (loadi32 addr:$dst), imm:$src2), addr:$dst)]>;
2510 def SBB32mi8 : Ii8<0x83, MRM3m, (outs), (ins i32mem:$dst, i32i8imm :$src2),
2511 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2512 [(store (sube (load addr:$dst), i32immSExt8:$src2), addr:$dst)]>;
2514 def SBB8rm : I<0x1A, MRMSrcMem, (outs GR8:$dst), (ins GR8:$src1, i8mem:$src2),
2515 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2516 [(set GR8:$dst, (sube GR8:$src1, (load addr:$src2)))]>;
2517 def SBB16rm : I<0x1B, MRMSrcMem, (outs GR16:$dst),
2518 (ins GR16:$src1, i16mem:$src2),
2519 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2520 [(set GR16:$dst, (sube GR16:$src1, (load addr:$src2)))]>,
2522 def SBB32rm : I<0x1B, MRMSrcMem, (outs GR32:$dst),
2523 (ins GR32:$src1, i32mem:$src2),
2524 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2525 [(set GR32:$dst, (sube GR32:$src1, (load addr:$src2)))]>;
2526 def SBB8ri : Ii8<0x80, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
2527 "sbb{b}\t{$src2, $dst|$dst, $src2}",
2528 [(set GR8:$dst, (sube GR8:$src1, imm:$src2))]>;
2529 def SBB16ri : Ii16<0x81, MRM3r, (outs GR16:$dst),
2530 (ins GR16:$src1, i16imm:$src2),
2531 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2532 [(set GR16:$dst, (sube GR16:$src1, imm:$src2))]>, OpSize;
2533 def SBB16ri8 : Ii8<0x83, MRM3r, (outs GR16:$dst),
2534 (ins GR16:$src1, i16i8imm:$src2),
2535 "sbb{w}\t{$src2, $dst|$dst, $src2}",
2536 [(set GR16:$dst, (sube GR16:$src1, i16immSExt8:$src2))]>,
2538 def SBB32ri : Ii32<0x81, MRM3r, (outs GR32:$dst),
2539 (ins GR32:$src1, i32imm:$src2),
2540 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2541 [(set GR32:$dst, (sube GR32:$src1, imm:$src2))]>;
2542 def SBB32ri8 : Ii8<0x83, MRM3r, (outs GR32:$dst),
2543 (ins GR32:$src1, i32i8imm:$src2),
2544 "sbb{l}\t{$src2, $dst|$dst, $src2}",
2545 [(set GR32:$dst, (sube GR32:$src1, i32immSExt8:$src2))]>;
2546 } // Uses = [EFLAGS]
2547 } // Defs = [EFLAGS]
2549 let Defs = [EFLAGS] in {
2550 let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y
2551 // Register-Register Signed Integer Multiply
2552 def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
2553 "imul{w}\t{$src2, $dst|$dst, $src2}",
2554 [(set GR16:$dst, (mul GR16:$src1, GR16:$src2)),
2555 (implicit EFLAGS)]>, TB, OpSize;
2556 def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
2557 "imul{l}\t{$src2, $dst|$dst, $src2}",
2558 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2)),
2559 (implicit EFLAGS)]>, TB;
2562 // Register-Memory Signed Integer Multiply
2563 def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
2564 (ins GR16:$src1, i16mem:$src2),
2565 "imul{w}\t{$src2, $dst|$dst, $src2}",
2566 [(set GR16:$dst, (mul GR16:$src1, (load addr:$src2))),
2567 (implicit EFLAGS)]>, TB, OpSize;
2568 def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
2569 "imul{l}\t{$src2, $dst|$dst, $src2}",
2570 [(set GR32:$dst, (mul GR32:$src1, (load addr:$src2))),
2571 (implicit EFLAGS)]>, TB;
2572 } // Defs = [EFLAGS]
2573 } // end Two Address instructions
2575 // Suprisingly enough, these are not two address instructions!
2576 let Defs = [EFLAGS] in {
2577 // Register-Integer Signed Integer Multiply
2578 def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
2579 (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
2580 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2581 [(set GR16:$dst, (mul GR16:$src1, imm:$src2)),
2582 (implicit EFLAGS)]>, OpSize;
2583 def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
2584 (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
2585 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2586 [(set GR32:$dst, (mul GR32:$src1, imm:$src2)),
2587 (implicit EFLAGS)]>;
2588 def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
2589 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
2590 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2591 [(set GR16:$dst, (mul GR16:$src1, i16immSExt8:$src2)),
2592 (implicit EFLAGS)]>, OpSize;
2593 def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
2594 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
2595 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2596 [(set GR32:$dst, (mul GR32:$src1, i32immSExt8:$src2)),
2597 (implicit EFLAGS)]>;
2599 // Memory-Integer Signed Integer Multiply
2600 def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
2601 (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2),
2602 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2603 [(set GR16:$dst, (mul (load addr:$src1), imm:$src2)),
2604 (implicit EFLAGS)]>, OpSize;
2605 def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
2606 (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
2607 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2608 [(set GR32:$dst, (mul (load addr:$src1), imm:$src2)),
2609 (implicit EFLAGS)]>;
2610 def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
2611 (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
2612 "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2613 [(set GR16:$dst, (mul (load addr:$src1),
2614 i16immSExt8:$src2)),
2615 (implicit EFLAGS)]>, OpSize;
2616 def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
2617 (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
2618 "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2619 [(set GR32:$dst, (mul (load addr:$src1),
2620 i32immSExt8:$src2)),
2621 (implicit EFLAGS)]>;
2622 } // Defs = [EFLAGS]
2624 //===----------------------------------------------------------------------===//
2625 // Test instructions are just like AND, except they don't generate a result.
2627 let Defs = [EFLAGS] in {
2628 let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
2629 def TEST8rr : I<0x84, MRMDestReg, (outs), (ins GR8:$src1, GR8:$src2),
2630 "test{b}\t{$src2, $src1|$src1, $src2}",
2631 [(X86cmp (and_su GR8:$src1, GR8:$src2), 0),
2632 (implicit EFLAGS)]>;
2633 def TEST16rr : I<0x85, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2634 "test{w}\t{$src2, $src1|$src1, $src2}",
2635 [(X86cmp (and_su GR16:$src1, GR16:$src2), 0),
2636 (implicit EFLAGS)]>,
2638 def TEST32rr : I<0x85, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2639 "test{l}\t{$src2, $src1|$src1, $src2}",
2640 [(X86cmp (and_su GR32:$src1, GR32:$src2), 0),
2641 (implicit EFLAGS)]>;
2644 def TEST8rm : I<0x84, MRMSrcMem, (outs), (ins GR8 :$src1, i8mem :$src2),
2645 "test{b}\t{$src2, $src1|$src1, $src2}",
2646 [(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0),
2647 (implicit EFLAGS)]>;
2648 def TEST16rm : I<0x85, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
2649 "test{w}\t{$src2, $src1|$src1, $src2}",
2650 [(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0),
2651 (implicit EFLAGS)]>, OpSize;
2652 def TEST32rm : I<0x85, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
2653 "test{l}\t{$src2, $src1|$src1, $src2}",
2654 [(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0),
2655 (implicit EFLAGS)]>;
2657 def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
2658 (outs), (ins GR8:$src1, i8imm:$src2),
2659 "test{b}\t{$src2, $src1|$src1, $src2}",
2660 [(X86cmp (and_su GR8:$src1, imm:$src2), 0),
2661 (implicit EFLAGS)]>;
2662 def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
2663 (outs), (ins GR16:$src1, i16imm:$src2),
2664 "test{w}\t{$src2, $src1|$src1, $src2}",
2665 [(X86cmp (and_su GR16:$src1, imm:$src2), 0),
2666 (implicit EFLAGS)]>, OpSize;
2667 def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
2668 (outs), (ins GR32:$src1, i32imm:$src2),
2669 "test{l}\t{$src2, $src1|$src1, $src2}",
2670 [(X86cmp (and_su GR32:$src1, imm:$src2), 0),
2671 (implicit EFLAGS)]>;
2673 def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
2674 (outs), (ins i8mem:$src1, i8imm:$src2),
2675 "test{b}\t{$src2, $src1|$src1, $src2}",
2676 [(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0),
2677 (implicit EFLAGS)]>;
2678 def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
2679 (outs), (ins i16mem:$src1, i16imm:$src2),
2680 "test{w}\t{$src2, $src1|$src1, $src2}",
2681 [(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0),
2682 (implicit EFLAGS)]>, OpSize;
2683 def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
2684 (outs), (ins i32mem:$src1, i32imm:$src2),
2685 "test{l}\t{$src2, $src1|$src1, $src2}",
2686 [(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0),
2687 (implicit EFLAGS)]>;
2688 } // Defs = [EFLAGS]
2691 // Condition code ops, incl. set if equal/not equal/...
2692 let Defs = [EFLAGS], Uses = [AH], neverHasSideEffects = 1 in
2693 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>; // flags = AH
2694 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
2695 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
2697 let Uses = [EFLAGS] in {
2698 def SETEr : I<0x94, MRM0r,
2699 (outs GR8 :$dst), (ins),
2701 [(set GR8:$dst, (X86setcc X86_COND_E, EFLAGS))]>,
2703 def SETEm : I<0x94, MRM0m,
2704 (outs), (ins i8mem:$dst),
2706 [(store (X86setcc X86_COND_E, EFLAGS), addr:$dst)]>,
2709 def SETNEr : I<0x95, MRM0r,
2710 (outs GR8 :$dst), (ins),
2712 [(set GR8:$dst, (X86setcc X86_COND_NE, EFLAGS))]>,
2714 def SETNEm : I<0x95, MRM0m,
2715 (outs), (ins i8mem:$dst),
2717 [(store (X86setcc X86_COND_NE, EFLAGS), addr:$dst)]>,
2720 def SETLr : I<0x9C, MRM0r,
2721 (outs GR8 :$dst), (ins),
2723 [(set GR8:$dst, (X86setcc X86_COND_L, EFLAGS))]>,
2724 TB; // GR8 = < signed
2725 def SETLm : I<0x9C, MRM0m,
2726 (outs), (ins i8mem:$dst),
2728 [(store (X86setcc X86_COND_L, EFLAGS), addr:$dst)]>,
2729 TB; // [mem8] = < signed
2731 def SETGEr : I<0x9D, MRM0r,
2732 (outs GR8 :$dst), (ins),
2734 [(set GR8:$dst, (X86setcc X86_COND_GE, EFLAGS))]>,
2735 TB; // GR8 = >= signed
2736 def SETGEm : I<0x9D, MRM0m,
2737 (outs), (ins i8mem:$dst),
2739 [(store (X86setcc X86_COND_GE, EFLAGS), addr:$dst)]>,
2740 TB; // [mem8] = >= signed
2742 def SETLEr : I<0x9E, MRM0r,
2743 (outs GR8 :$dst), (ins),
2745 [(set GR8:$dst, (X86setcc X86_COND_LE, EFLAGS))]>,
2746 TB; // GR8 = <= signed
2747 def SETLEm : I<0x9E, MRM0m,
2748 (outs), (ins i8mem:$dst),
2750 [(store (X86setcc X86_COND_LE, EFLAGS), addr:$dst)]>,
2751 TB; // [mem8] = <= signed
2753 def SETGr : I<0x9F, MRM0r,
2754 (outs GR8 :$dst), (ins),
2756 [(set GR8:$dst, (X86setcc X86_COND_G, EFLAGS))]>,
2757 TB; // GR8 = > signed
2758 def SETGm : I<0x9F, MRM0m,
2759 (outs), (ins i8mem:$dst),
2761 [(store (X86setcc X86_COND_G, EFLAGS), addr:$dst)]>,
2762 TB; // [mem8] = > signed
2764 def SETBr : I<0x92, MRM0r,
2765 (outs GR8 :$dst), (ins),
2767 [(set GR8:$dst, (X86setcc X86_COND_B, EFLAGS))]>,
2768 TB; // GR8 = < unsign
2769 def SETBm : I<0x92, MRM0m,
2770 (outs), (ins i8mem:$dst),
2772 [(store (X86setcc X86_COND_B, EFLAGS), addr:$dst)]>,
2773 TB; // [mem8] = < unsign
2775 def SETAEr : I<0x93, MRM0r,
2776 (outs GR8 :$dst), (ins),
2778 [(set GR8:$dst, (X86setcc X86_COND_AE, EFLAGS))]>,
2779 TB; // GR8 = >= unsign
2780 def SETAEm : I<0x93, MRM0m,
2781 (outs), (ins i8mem:$dst),
2783 [(store (X86setcc X86_COND_AE, EFLAGS), addr:$dst)]>,
2784 TB; // [mem8] = >= unsign
2786 def SETBEr : I<0x96, MRM0r,
2787 (outs GR8 :$dst), (ins),
2789 [(set GR8:$dst, (X86setcc X86_COND_BE, EFLAGS))]>,
2790 TB; // GR8 = <= unsign
2791 def SETBEm : I<0x96, MRM0m,
2792 (outs), (ins i8mem:$dst),
2794 [(store (X86setcc X86_COND_BE, EFLAGS), addr:$dst)]>,
2795 TB; // [mem8] = <= unsign
2797 def SETAr : I<0x97, MRM0r,
2798 (outs GR8 :$dst), (ins),
2800 [(set GR8:$dst, (X86setcc X86_COND_A, EFLAGS))]>,
2801 TB; // GR8 = > signed
2802 def SETAm : I<0x97, MRM0m,
2803 (outs), (ins i8mem:$dst),
2805 [(store (X86setcc X86_COND_A, EFLAGS), addr:$dst)]>,
2806 TB; // [mem8] = > signed
2808 def SETSr : I<0x98, MRM0r,
2809 (outs GR8 :$dst), (ins),
2811 [(set GR8:$dst, (X86setcc X86_COND_S, EFLAGS))]>,
2812 TB; // GR8 = <sign bit>
2813 def SETSm : I<0x98, MRM0m,
2814 (outs), (ins i8mem:$dst),
2816 [(store (X86setcc X86_COND_S, EFLAGS), addr:$dst)]>,
2817 TB; // [mem8] = <sign bit>
2818 def SETNSr : I<0x99, MRM0r,
2819 (outs GR8 :$dst), (ins),
2821 [(set GR8:$dst, (X86setcc X86_COND_NS, EFLAGS))]>,
2822 TB; // GR8 = !<sign bit>
2823 def SETNSm : I<0x99, MRM0m,
2824 (outs), (ins i8mem:$dst),
2826 [(store (X86setcc X86_COND_NS, EFLAGS), addr:$dst)]>,
2827 TB; // [mem8] = !<sign bit>
2829 def SETPr : I<0x9A, MRM0r,
2830 (outs GR8 :$dst), (ins),
2832 [(set GR8:$dst, (X86setcc X86_COND_P, EFLAGS))]>,
2834 def SETPm : I<0x9A, MRM0m,
2835 (outs), (ins i8mem:$dst),
2837 [(store (X86setcc X86_COND_P, EFLAGS), addr:$dst)]>,
2838 TB; // [mem8] = parity
2839 def SETNPr : I<0x9B, MRM0r,
2840 (outs GR8 :$dst), (ins),
2842 [(set GR8:$dst, (X86setcc X86_COND_NP, EFLAGS))]>,
2843 TB; // GR8 = not parity
2844 def SETNPm : I<0x9B, MRM0m,
2845 (outs), (ins i8mem:$dst),
2847 [(store (X86setcc X86_COND_NP, EFLAGS), addr:$dst)]>,
2848 TB; // [mem8] = not parity
2850 def SETOr : I<0x90, MRM0r,
2851 (outs GR8 :$dst), (ins),
2853 [(set GR8:$dst, (X86setcc X86_COND_O, EFLAGS))]>,
2854 TB; // GR8 = overflow
2855 def SETOm : I<0x90, MRM0m,
2856 (outs), (ins i8mem:$dst),
2858 [(store (X86setcc X86_COND_O, EFLAGS), addr:$dst)]>,
2859 TB; // [mem8] = overflow
2860 def SETNOr : I<0x91, MRM0r,
2861 (outs GR8 :$dst), (ins),
2863 [(set GR8:$dst, (X86setcc X86_COND_NO, EFLAGS))]>,
2864 TB; // GR8 = not overflow
2865 def SETNOm : I<0x91, MRM0m,
2866 (outs), (ins i8mem:$dst),
2868 [(store (X86setcc X86_COND_NO, EFLAGS), addr:$dst)]>,
2869 TB; // [mem8] = not overflow
2870 } // Uses = [EFLAGS]
2873 // Integer comparisons
2874 let Defs = [EFLAGS] in {
2875 def CMP8rr : I<0x38, MRMDestReg,
2876 (outs), (ins GR8 :$src1, GR8 :$src2),
2877 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2878 [(X86cmp GR8:$src1, GR8:$src2), (implicit EFLAGS)]>;
2879 def CMP16rr : I<0x39, MRMDestReg,
2880 (outs), (ins GR16:$src1, GR16:$src2),
2881 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2882 [(X86cmp GR16:$src1, GR16:$src2), (implicit EFLAGS)]>, OpSize;
2883 def CMP32rr : I<0x39, MRMDestReg,
2884 (outs), (ins GR32:$src1, GR32:$src2),
2885 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2886 [(X86cmp GR32:$src1, GR32:$src2), (implicit EFLAGS)]>;
2887 def CMP8mr : I<0x38, MRMDestMem,
2888 (outs), (ins i8mem :$src1, GR8 :$src2),
2889 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2890 [(X86cmp (loadi8 addr:$src1), GR8:$src2),
2891 (implicit EFLAGS)]>;
2892 def CMP16mr : I<0x39, MRMDestMem,
2893 (outs), (ins i16mem:$src1, GR16:$src2),
2894 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2895 [(X86cmp (loadi16 addr:$src1), GR16:$src2),
2896 (implicit EFLAGS)]>, OpSize;
2897 def CMP32mr : I<0x39, MRMDestMem,
2898 (outs), (ins i32mem:$src1, GR32:$src2),
2899 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2900 [(X86cmp (loadi32 addr:$src1), GR32:$src2),
2901 (implicit EFLAGS)]>;
2902 def CMP8rm : I<0x3A, MRMSrcMem,
2903 (outs), (ins GR8 :$src1, i8mem :$src2),
2904 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2905 [(X86cmp GR8:$src1, (loadi8 addr:$src2)),
2906 (implicit EFLAGS)]>;
2907 def CMP16rm : I<0x3B, MRMSrcMem,
2908 (outs), (ins GR16:$src1, i16mem:$src2),
2909 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2910 [(X86cmp GR16:$src1, (loadi16 addr:$src2)),
2911 (implicit EFLAGS)]>, OpSize;
2912 def CMP32rm : I<0x3B, MRMSrcMem,
2913 (outs), (ins GR32:$src1, i32mem:$src2),
2914 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2915 [(X86cmp GR32:$src1, (loadi32 addr:$src2)),
2916 (implicit EFLAGS)]>;
2917 def CMP8ri : Ii8<0x80, MRM7r,
2918 (outs), (ins GR8:$src1, i8imm:$src2),
2919 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2920 [(X86cmp GR8:$src1, imm:$src2), (implicit EFLAGS)]>;
2921 def CMP16ri : Ii16<0x81, MRM7r,
2922 (outs), (ins GR16:$src1, i16imm:$src2),
2923 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2924 [(X86cmp GR16:$src1, imm:$src2),
2925 (implicit EFLAGS)]>, OpSize;
2926 def CMP32ri : Ii32<0x81, MRM7r,
2927 (outs), (ins GR32:$src1, i32imm:$src2),
2928 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2929 [(X86cmp GR32:$src1, imm:$src2), (implicit EFLAGS)]>;
2930 def CMP8mi : Ii8 <0x80, MRM7m,
2931 (outs), (ins i8mem :$src1, i8imm :$src2),
2932 "cmp{b}\t{$src2, $src1|$src1, $src2}",
2933 [(X86cmp (loadi8 addr:$src1), imm:$src2),
2934 (implicit EFLAGS)]>;
2935 def CMP16mi : Ii16<0x81, MRM7m,
2936 (outs), (ins i16mem:$src1, i16imm:$src2),
2937 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2938 [(X86cmp (loadi16 addr:$src1), imm:$src2),
2939 (implicit EFLAGS)]>, OpSize;
2940 def CMP32mi : Ii32<0x81, MRM7m,
2941 (outs), (ins i32mem:$src1, i32imm:$src2),
2942 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2943 [(X86cmp (loadi32 addr:$src1), imm:$src2),
2944 (implicit EFLAGS)]>;
2945 def CMP16ri8 : Ii8<0x83, MRM7r,
2946 (outs), (ins GR16:$src1, i16i8imm:$src2),
2947 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2948 [(X86cmp GR16:$src1, i16immSExt8:$src2),
2949 (implicit EFLAGS)]>, OpSize;
2950 def CMP16mi8 : Ii8<0x83, MRM7m,
2951 (outs), (ins i16mem:$src1, i16i8imm:$src2),
2952 "cmp{w}\t{$src2, $src1|$src1, $src2}",
2953 [(X86cmp (loadi16 addr:$src1), i16immSExt8:$src2),
2954 (implicit EFLAGS)]>, OpSize;
2955 def CMP32mi8 : Ii8<0x83, MRM7m,
2956 (outs), (ins i32mem:$src1, i32i8imm:$src2),
2957 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2958 [(X86cmp (loadi32 addr:$src1), i32immSExt8:$src2),
2959 (implicit EFLAGS)]>;
2960 def CMP32ri8 : Ii8<0x83, MRM7r,
2961 (outs), (ins GR32:$src1, i32i8imm:$src2),
2962 "cmp{l}\t{$src2, $src1|$src1, $src2}",
2963 [(X86cmp GR32:$src1, i32immSExt8:$src2),
2964 (implicit EFLAGS)]>;
2965 } // Defs = [EFLAGS]
2968 // TODO: BTC, BTR, and BTS
2969 let Defs = [EFLAGS] in {
2970 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
2971 "bt{w}\t{$src2, $src1|$src1, $src2}",
2972 [(X86bt GR16:$src1, GR16:$src2),
2973 (implicit EFLAGS)]>, OpSize, TB;
2974 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
2975 "bt{l}\t{$src2, $src1|$src1, $src2}",
2976 [(X86bt GR32:$src1, GR32:$src2),
2977 (implicit EFLAGS)]>, TB;
2979 // Unlike with the register+register form, the memory+register form of the
2980 // bt instruction does not ignore the high bits of the index. From ISel's
2981 // perspective, this is pretty bizarre. Disable these instructions for now.
2982 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
2983 // "bt{w}\t{$src2, $src1|$src1, $src2}",
2984 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
2985 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
2986 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
2987 // "bt{l}\t{$src2, $src1|$src1, $src2}",
2988 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
2989 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
2991 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
2992 "bt{w}\t{$src2, $src1|$src1, $src2}",
2993 [(X86bt GR16:$src1, i16immSExt8:$src2),
2994 (implicit EFLAGS)]>, OpSize, TB;
2995 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
2996 "bt{l}\t{$src2, $src1|$src1, $src2}",
2997 [(X86bt GR32:$src1, i32immSExt8:$src2),
2998 (implicit EFLAGS)]>, TB;
2999 // Note that these instructions don't need FastBTMem because that
3000 // only applies when the other operand is in a register. When it's
3001 // an immediate, bt is still fast.
3002 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
3003 "bt{w}\t{$src2, $src1|$src1, $src2}",
3004 [(X86bt (loadi16 addr:$src1), i16immSExt8:$src2),
3005 (implicit EFLAGS)]>, OpSize, TB;
3006 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
3007 "bt{l}\t{$src2, $src1|$src1, $src2}",
3008 [(X86bt (loadi32 addr:$src1), i32immSExt8:$src2),
3009 (implicit EFLAGS)]>, TB;
3010 } // Defs = [EFLAGS]
3012 // Sign/Zero extenders
3013 // Use movsbl intead of movsbw; we don't care about the high 16 bits
3014 // of the register here. This has a smaller encoding and avoids a
3015 // partial-register update.
3016 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3017 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3018 [(set GR16:$dst, (sext GR8:$src))]>, TB;
3019 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3020 "movs{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3021 [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB;
3022 def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3023 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3024 [(set GR32:$dst, (sext GR8:$src))]>, TB;
3025 def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3026 "movs{bl|x}\t{$src, $dst|$dst, $src}",
3027 [(set GR32:$dst, (sextloadi32i8 addr:$src))]>, TB;
3028 def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3029 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3030 [(set GR32:$dst, (sext GR16:$src))]>, TB;
3031 def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3032 "movs{wl|x}\t{$src, $dst|$dst, $src}",
3033 [(set GR32:$dst, (sextloadi32i16 addr:$src))]>, TB;
3035 // Use movzbl intead of movzbw; we don't care about the high 16 bits
3036 // of the register here. This has a smaller encoding and avoids a
3037 // partial-register update.
3038 def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src),
3039 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3040 [(set GR16:$dst, (zext GR8:$src))]>, TB;
3041 def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src),
3042 "movz{bl|x}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
3043 [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB;
3044 def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
3045 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3046 [(set GR32:$dst, (zext GR8:$src))]>, TB;
3047 def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
3048 "movz{bl|x}\t{$src, $dst|$dst, $src}",
3049 [(set GR32:$dst, (zextloadi32i8 addr:$src))]>, TB;
3050 def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
3051 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3052 [(set GR32:$dst, (zext GR16:$src))]>, TB;
3053 def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
3054 "movz{wl|x}\t{$src, $dst|$dst, $src}",
3055 [(set GR32:$dst, (zextloadi32i16 addr:$src))]>, TB;
3057 // These are the same as the regular regular MOVZX32rr8 and MOVZX32rm8
3058 // except that they use GR32_NOREX for the output operand register class
3059 // instead of GR32. This allows them to operate on h registers on x86-64.
3060 def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg,
3061 (outs GR32_NOREX:$dst), (ins GR8:$src),
3062 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3065 def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
3066 (outs GR32_NOREX:$dst), (ins i8mem:$src),
3067 "movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
3070 let neverHasSideEffects = 1 in {
3071 let Defs = [AX], Uses = [AL] in
3072 def CBW : I<0x98, RawFrm, (outs), (ins),
3073 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
3074 let Defs = [EAX], Uses = [AX] in
3075 def CWDE : I<0x98, RawFrm, (outs), (ins),
3076 "{cwtl|cwde}", []>; // EAX = signext(AX)
3078 let Defs = [AX,DX], Uses = [AX] in
3079 def CWD : I<0x99, RawFrm, (outs), (ins),
3080 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
3081 let Defs = [EAX,EDX], Uses = [EAX] in
3082 def CDQ : I<0x99, RawFrm, (outs), (ins),
3083 "{cltd|cdq}", []>; // EDX:EAX = signext(EAX)
3086 //===----------------------------------------------------------------------===//
3087 // Alias Instructions
3088 //===----------------------------------------------------------------------===//
3090 // Alias instructions that map movr0 to xor.
3091 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
3092 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1 in {
3093 def MOV8r0 : I<0x30, MRMInitReg, (outs GR8 :$dst), (ins),
3094 "xor{b}\t$dst, $dst",
3095 [(set GR8:$dst, 0)]>;
3096 // Use xorl instead of xorw since we don't care about the high 16 bits,
3097 // it's smaller, and it avoids a partial-register update.
3098 def MOV16r0 : I<0x31, MRMInitReg, (outs GR16:$dst), (ins),
3099 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
3100 [(set GR16:$dst, 0)]>;
3101 def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins),
3102 "xor{l}\t$dst, $dst",
3103 [(set GR32:$dst, 0)]>;
3106 //===----------------------------------------------------------------------===//
3107 // Thread Local Storage Instructions
3110 // All calls clobber the non-callee saved registers. ESP is marked as
3111 // a use to prevent stack-pointer assignments that appear immediately
3112 // before calls from potentially appearing dead.
3113 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
3114 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
3115 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
3116 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
3118 def TLS_addr32 : I<0, Pseudo, (outs), (ins lea32mem:$sym),
3119 "leal\t$sym, %eax; "
3120 "call\t___tls_get_addr@PLT",
3121 [(X86tlsaddr tls32addr:$sym)]>,
3122 Requires<[In32BitMode]>;
3124 let AddedComplexity = 5 in
3125 def GS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3126 "movl\t%gs:$src, $dst",
3127 [(set GR32:$dst, (gsload addr:$src))]>, SegGS;
3129 let AddedComplexity = 5 in
3130 def FS_MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
3131 "movl\t%fs:$src, $dst",
3132 [(set GR32:$dst, (fsload addr:$src))]>, SegFS;
3134 //===----------------------------------------------------------------------===//
3135 // DWARF Pseudo Instructions
3138 def DWARF_LOC : I<0, Pseudo, (outs),
3139 (ins i32imm:$line, i32imm:$col, i32imm:$file),
3140 ".loc\t${file:debug} ${line:debug} ${col:debug}",
3141 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
3144 //===----------------------------------------------------------------------===//
3145 // EH Pseudo Instructions
3147 let isTerminator = 1, isReturn = 1, isBarrier = 1,
3149 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
3150 "ret\t#eh_return, addr: $addr",
3151 [(X86ehret GR32:$addr)]>;
3155 //===----------------------------------------------------------------------===//
3159 // Atomic swap. These are just normal xchg instructions. But since a memory
3160 // operand is referenced, the atomicity is ensured.
3161 let Constraints = "$val = $dst" in {
3162 def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3163 "xchg{l}\t{$val, $ptr|$ptr, $val}",
3164 [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))]>;
3165 def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3166 "xchg{w}\t{$val, $ptr|$ptr, $val}",
3167 [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))]>,
3169 def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3170 "xchg{b}\t{$val, $ptr|$ptr, $val}",
3171 [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))]>;
3174 // Atomic compare and swap.
3175 let Defs = [EAX, EFLAGS], Uses = [EAX] in {
3176 def LCMPXCHG32 : I<0xB1, MRMDestMem, (outs), (ins i32mem:$ptr, GR32:$swap),
3178 "cmpxchg{l}\t{$swap, $ptr|$ptr, $swap}",
3179 [(X86cas addr:$ptr, GR32:$swap, 4)]>, TB, LOCK;
3181 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in {
3182 def LCMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i32mem:$ptr),
3185 [(X86cas8 addr:$ptr)]>, TB, LOCK;
3188 let Defs = [AX, EFLAGS], Uses = [AX] in {
3189 def LCMPXCHG16 : I<0xB1, MRMDestMem, (outs), (ins i16mem:$ptr, GR16:$swap),
3191 "cmpxchg{w}\t{$swap, $ptr|$ptr, $swap}",
3192 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
3194 let Defs = [AL, EFLAGS], Uses = [AL] in {
3195 def LCMPXCHG8 : I<0xB0, MRMDestMem, (outs), (ins i8mem:$ptr, GR8:$swap),
3197 "cmpxchg{b}\t{$swap, $ptr|$ptr, $swap}",
3198 [(X86cas addr:$ptr, GR8:$swap, 1)]>, TB, LOCK;
3201 // Atomic exchange and add
3202 let Constraints = "$val = $dst", Defs = [EFLAGS] in {
3203 def LXADD32 : I<0xC1, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3205 "xadd{l}\t{$val, $ptr|$ptr, $val}",
3206 [(set GR32:$dst, (atomic_load_add_32 addr:$ptr, GR32:$val))]>,
3208 def LXADD16 : I<0xC1, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3210 "xadd{w}\t{$val, $ptr|$ptr, $val}",
3211 [(set GR16:$dst, (atomic_load_add_16 addr:$ptr, GR16:$val))]>,
3213 def LXADD8 : I<0xC0, MRMSrcMem, (outs GR8:$dst), (ins i8mem:$ptr, GR8:$val),
3215 "xadd{b}\t{$val, $ptr|$ptr, $val}",
3216 [(set GR8:$dst, (atomic_load_add_8 addr:$ptr, GR8:$val))]>,
3220 // Atomic exchange, and, or, xor
3221 let Constraints = "$val = $dst", Defs = [EFLAGS],
3222 usesCustomDAGSchedInserter = 1 in {
3223 def ATOMAND32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3224 "#ATOMAND32 PSEUDO!",
3225 [(set GR32:$dst, (atomic_load_and_32 addr:$ptr, GR32:$val))]>;
3226 def ATOMOR32 : I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3227 "#ATOMOR32 PSEUDO!",
3228 [(set GR32:$dst, (atomic_load_or_32 addr:$ptr, GR32:$val))]>;
3229 def ATOMXOR32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3230 "#ATOMXOR32 PSEUDO!",
3231 [(set GR32:$dst, (atomic_load_xor_32 addr:$ptr, GR32:$val))]>;
3232 def ATOMNAND32 : I<0, Pseudo,(outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3233 "#ATOMNAND32 PSEUDO!",
3234 [(set GR32:$dst, (atomic_load_nand_32 addr:$ptr, GR32:$val))]>;
3235 def ATOMMIN32: I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$ptr, GR32:$val),
3236 "#ATOMMIN32 PSEUDO!",
3237 [(set GR32:$dst, (atomic_load_min_32 addr:$ptr, GR32:$val))]>;
3238 def ATOMMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3239 "#ATOMMAX32 PSEUDO!",
3240 [(set GR32:$dst, (atomic_load_max_32 addr:$ptr, GR32:$val))]>;
3241 def ATOMUMIN32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3242 "#ATOMUMIN32 PSEUDO!",
3243 [(set GR32:$dst, (atomic_load_umin_32 addr:$ptr, GR32:$val))]>;
3244 def ATOMUMAX32: I<0, Pseudo, (outs GR32:$dst),(ins i32mem:$ptr, GR32:$val),
3245 "#ATOMUMAX32 PSEUDO!",
3246 [(set GR32:$dst, (atomic_load_umax_32 addr:$ptr, GR32:$val))]>;
3248 def ATOMAND16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3249 "#ATOMAND16 PSEUDO!",
3250 [(set GR16:$dst, (atomic_load_and_16 addr:$ptr, GR16:$val))]>;
3251 def ATOMOR16 : I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3252 "#ATOMOR16 PSEUDO!",
3253 [(set GR16:$dst, (atomic_load_or_16 addr:$ptr, GR16:$val))]>;
3254 def ATOMXOR16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3255 "#ATOMXOR16 PSEUDO!",
3256 [(set GR16:$dst, (atomic_load_xor_16 addr:$ptr, GR16:$val))]>;
3257 def ATOMNAND16 : I<0, Pseudo,(outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3258 "#ATOMNAND16 PSEUDO!",
3259 [(set GR16:$dst, (atomic_load_nand_16 addr:$ptr, GR16:$val))]>;
3260 def ATOMMIN16: I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$ptr, GR16:$val),
3261 "#ATOMMIN16 PSEUDO!",
3262 [(set GR16:$dst, (atomic_load_min_16 addr:$ptr, GR16:$val))]>;
3263 def ATOMMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3264 "#ATOMMAX16 PSEUDO!",
3265 [(set GR16:$dst, (atomic_load_max_16 addr:$ptr, GR16:$val))]>;
3266 def ATOMUMIN16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3267 "#ATOMUMIN16 PSEUDO!",
3268 [(set GR16:$dst, (atomic_load_umin_16 addr:$ptr, GR16:$val))]>;
3269 def ATOMUMAX16: I<0, Pseudo, (outs GR16:$dst),(ins i16mem:$ptr, GR16:$val),
3270 "#ATOMUMAX16 PSEUDO!",
3271 [(set GR16:$dst, (atomic_load_umax_16 addr:$ptr, GR16:$val))]>;
3273 def ATOMAND8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3274 "#ATOMAND8 PSEUDO!",
3275 [(set GR8:$dst, (atomic_load_and_8 addr:$ptr, GR8:$val))]>;
3276 def ATOMOR8 : I<0, Pseudo, (outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3278 [(set GR8:$dst, (atomic_load_or_8 addr:$ptr, GR8:$val))]>;
3279 def ATOMXOR8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3280 "#ATOMXOR8 PSEUDO!",
3281 [(set GR8:$dst, (atomic_load_xor_8 addr:$ptr, GR8:$val))]>;
3282 def ATOMNAND8 : I<0, Pseudo,(outs GR8:$dst),(ins i8mem:$ptr, GR8:$val),
3283 "#ATOMNAND8 PSEUDO!",
3284 [(set GR8:$dst, (atomic_load_nand_8 addr:$ptr, GR8:$val))]>;
3287 let Constraints = "$val1 = $dst1, $val2 = $dst2",
3288 Defs = [EFLAGS, EAX, EBX, ECX, EDX],
3289 Uses = [EAX, EBX, ECX, EDX],
3290 mayLoad = 1, mayStore = 1,
3291 usesCustomDAGSchedInserter = 1 in {
3292 def ATOMAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3293 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3294 "#ATOMAND6432 PSEUDO!", []>;
3295 def ATOMOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3296 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3297 "#ATOMOR6432 PSEUDO!", []>;
3298 def ATOMXOR6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3299 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3300 "#ATOMXOR6432 PSEUDO!", []>;
3301 def ATOMNAND6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3302 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3303 "#ATOMNAND6432 PSEUDO!", []>;
3304 def ATOMADD6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3305 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3306 "#ATOMADD6432 PSEUDO!", []>;
3307 def ATOMSUB6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3308 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3309 "#ATOMSUB6432 PSEUDO!", []>;
3310 def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
3311 (ins i64mem:$ptr, GR32:$val1, GR32:$val2),
3312 "#ATOMSWAP6432 PSEUDO!", []>;
3315 //===----------------------------------------------------------------------===//
3316 // Non-Instruction Patterns
3317 //===----------------------------------------------------------------------===//
3319 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
3320 def : Pat<(i32 (X86Wrapper tconstpool :$dst)), (MOV32ri tconstpool :$dst)>;
3321 def : Pat<(i32 (X86Wrapper tjumptable :$dst)), (MOV32ri tjumptable :$dst)>;
3322 def : Pat<(i32 (X86Wrapper tglobaltlsaddr:$dst)),(MOV32ri tglobaltlsaddr:$dst)>;
3323 def : Pat<(i32 (X86Wrapper tglobaladdr :$dst)), (MOV32ri tglobaladdr :$dst)>;
3324 def : Pat<(i32 (X86Wrapper texternalsym:$dst)), (MOV32ri texternalsym:$dst)>;
3326 def : Pat<(add GR32:$src1, (X86Wrapper tconstpool:$src2)),
3327 (ADD32ri GR32:$src1, tconstpool:$src2)>;
3328 def : Pat<(add GR32:$src1, (X86Wrapper tjumptable:$src2)),
3329 (ADD32ri GR32:$src1, tjumptable:$src2)>;
3330 def : Pat<(add GR32:$src1, (X86Wrapper tglobaladdr :$src2)),
3331 (ADD32ri GR32:$src1, tglobaladdr:$src2)>;
3332 def : Pat<(add GR32:$src1, (X86Wrapper texternalsym:$src2)),
3333 (ADD32ri GR32:$src1, texternalsym:$src2)>;
3335 def : Pat<(store (i32 (X86Wrapper tglobaladdr:$src)), addr:$dst),
3336 (MOV32mi addr:$dst, tglobaladdr:$src)>;
3337 def : Pat<(store (i32 (X86Wrapper texternalsym:$src)), addr:$dst),
3338 (MOV32mi addr:$dst, texternalsym:$src)>;
3342 def : Pat<(X86tailcall GR32:$dst),
3345 def : Pat<(X86tailcall (i32 tglobaladdr:$dst)),
3347 def : Pat<(X86tailcall (i32 texternalsym:$dst)),
3350 def : Pat<(X86tcret GR32:$dst, imm:$off),
3351 (TCRETURNri GR32:$dst, imm:$off)>;
3353 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
3354 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3356 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
3357 (TCRETURNdi texternalsym:$dst, imm:$off)>;
3359 def : Pat<(X86call (i32 tglobaladdr:$dst)),
3360 (CALLpcrel32 tglobaladdr:$dst)>;
3361 def : Pat<(X86call (i32 texternalsym:$dst)),
3362 (CALLpcrel32 texternalsym:$dst)>;
3363 def : Pat<(X86call (i32 imm:$dst)),
3364 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
3366 // X86 specific add which produces a flag.
3367 def : Pat<(addc GR32:$src1, GR32:$src2),
3368 (ADD32rr GR32:$src1, GR32:$src2)>;
3369 def : Pat<(addc GR32:$src1, (load addr:$src2)),
3370 (ADD32rm GR32:$src1, addr:$src2)>;
3371 def : Pat<(addc GR32:$src1, imm:$src2),
3372 (ADD32ri GR32:$src1, imm:$src2)>;
3373 def : Pat<(addc GR32:$src1, i32immSExt8:$src2),
3374 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3376 def : Pat<(subc GR32:$src1, GR32:$src2),
3377 (SUB32rr GR32:$src1, GR32:$src2)>;
3378 def : Pat<(subc GR32:$src1, (load addr:$src2)),
3379 (SUB32rm GR32:$src1, addr:$src2)>;
3380 def : Pat<(subc GR32:$src1, imm:$src2),
3381 (SUB32ri GR32:$src1, imm:$src2)>;
3382 def : Pat<(subc GR32:$src1, i32immSExt8:$src2),
3383 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3387 // TEST R,R is smaller than CMP R,0
3388 def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
3389 (TEST8rr GR8:$src1, GR8:$src1)>;
3390 def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)),
3391 (TEST16rr GR16:$src1, GR16:$src1)>;
3392 def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)),
3393 (TEST32rr GR32:$src1, GR32:$src1)>;
3395 // Conditional moves with folded loads with operands swapped and conditions
3397 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_B, EFLAGS),
3398 (CMOVAE16rm GR16:$src2, addr:$src1)>;
3399 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_B, EFLAGS),
3400 (CMOVAE32rm GR32:$src2, addr:$src1)>;
3401 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_AE, EFLAGS),
3402 (CMOVB16rm GR16:$src2, addr:$src1)>;
3403 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_AE, EFLAGS),
3404 (CMOVB32rm GR32:$src2, addr:$src1)>;
3405 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_E, EFLAGS),
3406 (CMOVNE16rm GR16:$src2, addr:$src1)>;
3407 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_E, EFLAGS),
3408 (CMOVNE32rm GR32:$src2, addr:$src1)>;
3409 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NE, EFLAGS),
3410 (CMOVE16rm GR16:$src2, addr:$src1)>;
3411 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NE, EFLAGS),
3412 (CMOVE32rm GR32:$src2, addr:$src1)>;
3413 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_BE, EFLAGS),
3414 (CMOVA16rm GR16:$src2, addr:$src1)>;
3415 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_BE, EFLAGS),
3416 (CMOVA32rm GR32:$src2, addr:$src1)>;
3417 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_A, EFLAGS),
3418 (CMOVBE16rm GR16:$src2, addr:$src1)>;
3419 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_A, EFLAGS),
3420 (CMOVBE32rm GR32:$src2, addr:$src1)>;
3421 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_L, EFLAGS),
3422 (CMOVGE16rm GR16:$src2, addr:$src1)>;
3423 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_L, EFLAGS),
3424 (CMOVGE32rm GR32:$src2, addr:$src1)>;
3425 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_GE, EFLAGS),
3426 (CMOVL16rm GR16:$src2, addr:$src1)>;
3427 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_GE, EFLAGS),
3428 (CMOVL32rm GR32:$src2, addr:$src1)>;
3429 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_LE, EFLAGS),
3430 (CMOVG16rm GR16:$src2, addr:$src1)>;
3431 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_LE, EFLAGS),
3432 (CMOVG32rm GR32:$src2, addr:$src1)>;
3433 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_G, EFLAGS),
3434 (CMOVLE16rm GR16:$src2, addr:$src1)>;
3435 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_G, EFLAGS),
3436 (CMOVLE32rm GR32:$src2, addr:$src1)>;
3437 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_P, EFLAGS),
3438 (CMOVNP16rm GR16:$src2, addr:$src1)>;
3439 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_P, EFLAGS),
3440 (CMOVNP32rm GR32:$src2, addr:$src1)>;
3441 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NP, EFLAGS),
3442 (CMOVP16rm GR16:$src2, addr:$src1)>;
3443 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NP, EFLAGS),
3444 (CMOVP32rm GR32:$src2, addr:$src1)>;
3445 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_S, EFLAGS),
3446 (CMOVNS16rm GR16:$src2, addr:$src1)>;
3447 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_S, EFLAGS),
3448 (CMOVNS32rm GR32:$src2, addr:$src1)>;
3449 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NS, EFLAGS),
3450 (CMOVS16rm GR16:$src2, addr:$src1)>;
3451 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NS, EFLAGS),
3452 (CMOVS32rm GR32:$src2, addr:$src1)>;
3453 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_O, EFLAGS),
3454 (CMOVNO16rm GR16:$src2, addr:$src1)>;
3455 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_O, EFLAGS),
3456 (CMOVNO32rm GR32:$src2, addr:$src1)>;
3457 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, X86_COND_NO, EFLAGS),
3458 (CMOVO16rm GR16:$src2, addr:$src1)>;
3459 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, X86_COND_NO, EFLAGS),
3460 (CMOVO32rm GR32:$src2, addr:$src1)>;
3462 // zextload bool -> zextload byte
3463 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3464 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
3465 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3467 // extload bool -> extload byte
3468 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
3469 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>,
3470 Requires<[In32BitMode]>;
3471 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
3472 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>,
3473 Requires<[In32BitMode]>;
3474 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
3475 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
3478 def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>,
3479 Requires<[In32BitMode]>;
3480 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>,
3481 Requires<[In32BitMode]>;
3482 def : Pat<(i32 (anyext GR16:$src)),
3483 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, x86_subreg_16bit)>;
3485 // (and (i32 load), 255) -> (zextload i8)
3486 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 255))),
3487 (MOVZX32rm8 addr:$src)>;
3488 def : Pat<(i32 (and (nvloadi32 addr:$src), (i32 65535))),
3489 (MOVZX32rm16 addr:$src)>;
3491 //===----------------------------------------------------------------------===//
3493 //===----------------------------------------------------------------------===//
3495 // Odd encoding trick: -128 fits into an 8-bit immediate field while
3496 // +128 doesn't, so in this special case use a sub instead of an add.
3497 def : Pat<(add GR16:$src1, 128),
3498 (SUB16ri8 GR16:$src1, -128)>;
3499 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
3500 (SUB16mi8 addr:$dst, -128)>;
3501 def : Pat<(add GR32:$src1, 128),
3502 (SUB32ri8 GR32:$src1, -128)>;
3503 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
3504 (SUB32mi8 addr:$dst, -128)>;
3506 // r & (2^16-1) ==> movz
3507 def : Pat<(and GR32:$src1, 0xffff),
3508 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
3509 // r & (2^8-1) ==> movz
3510 def : Pat<(and GR32:$src1, 0xff),
3511 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
3513 Requires<[In32BitMode]>;
3514 // r & (2^8-1) ==> movz
3515 def : Pat<(and GR16:$src1, 0xff),
3516 (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
3518 Requires<[In32BitMode]>;
3520 // sext_inreg patterns
3521 def : Pat<(sext_inreg GR32:$src, i16),
3522 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
3523 def : Pat<(sext_inreg GR32:$src, i8),
3524 (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3526 Requires<[In32BitMode]>;
3527 def : Pat<(sext_inreg GR16:$src, i8),
3528 (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3530 Requires<[In32BitMode]>;
3533 def : Pat<(i16 (trunc GR32:$src)),
3534 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
3535 def : Pat<(i8 (trunc GR32:$src)),
3536 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3538 Requires<[In32BitMode]>;
3539 def : Pat<(i8 (trunc GR16:$src)),
3540 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3542 Requires<[In32BitMode]>;
3544 // h-register tricks
3545 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
3546 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3547 x86_subreg_8bit_hi)>,
3548 Requires<[In32BitMode]>;
3549 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
3550 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3551 x86_subreg_8bit_hi)>,
3552 Requires<[In32BitMode]>;
3553 def : Pat<(srl_su GR16:$src, (i8 8)),
3556 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3557 x86_subreg_8bit_hi)),
3559 Requires<[In32BitMode]>;
3560 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
3561 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
3562 x86_subreg_8bit_hi))>,
3563 Requires<[In32BitMode]>;
3564 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
3565 (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
3566 x86_subreg_8bit_hi))>,
3567 Requires<[In32BitMode]>;
3569 // (shl x, 1) ==> (add x, x)
3570 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
3571 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
3572 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
3574 // (shl x (and y, 31)) ==> (shl x, y)
3575 def : Pat<(shl GR8:$src1, (and CL:$amt, 31)),
3576 (SHL8rCL GR8:$src1)>;
3577 def : Pat<(shl GR16:$src1, (and CL:$amt, 31)),
3578 (SHL16rCL GR16:$src1)>;
3579 def : Pat<(shl GR32:$src1, (and CL:$amt, 31)),
3580 (SHL32rCL GR32:$src1)>;
3581 def : Pat<(store (shl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3582 (SHL8mCL addr:$dst)>;
3583 def : Pat<(store (shl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3584 (SHL16mCL addr:$dst)>;
3585 def : Pat<(store (shl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3586 (SHL32mCL addr:$dst)>;
3588 def : Pat<(srl GR8:$src1, (and CL:$amt, 31)),
3589 (SHR8rCL GR8:$src1)>;
3590 def : Pat<(srl GR16:$src1, (and CL:$amt, 31)),
3591 (SHR16rCL GR16:$src1)>;
3592 def : Pat<(srl GR32:$src1, (and CL:$amt, 31)),
3593 (SHR32rCL GR32:$src1)>;
3594 def : Pat<(store (srl (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3595 (SHR8mCL addr:$dst)>;
3596 def : Pat<(store (srl (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3597 (SHR16mCL addr:$dst)>;
3598 def : Pat<(store (srl (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3599 (SHR32mCL addr:$dst)>;
3601 def : Pat<(sra GR8:$src1, (and CL:$amt, 31)),
3602 (SAR8rCL GR8:$src1)>;
3603 def : Pat<(sra GR16:$src1, (and CL:$amt, 31)),
3604 (SAR16rCL GR16:$src1)>;
3605 def : Pat<(sra GR32:$src1, (and CL:$amt, 31)),
3606 (SAR32rCL GR32:$src1)>;
3607 def : Pat<(store (sra (loadi8 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3608 (SAR8mCL addr:$dst)>;
3609 def : Pat<(store (sra (loadi16 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3610 (SAR16mCL addr:$dst)>;
3611 def : Pat<(store (sra (loadi32 addr:$dst), (and CL:$amt, 31)), addr:$dst),
3612 (SAR32mCL addr:$dst)>;
3614 // (or (x >> c) | (y << (32 - c))) ==> (shrd32 x, y, c)
3615 def : Pat<(or (srl GR32:$src1, CL:$amt),
3616 (shl GR32:$src2, (sub 32, CL:$amt))),
3617 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3619 def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt),
3620 (shl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3621 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3623 def : Pat<(or (srl GR32:$src1, (i8 (trunc ECX:$amt))),
3624 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3625 (SHRD32rrCL GR32:$src1, GR32:$src2)>;
3627 def : Pat<(store (or (srl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3628 (shl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3630 (SHRD32mrCL addr:$dst, GR32:$src2)>;
3632 def : Pat<(shrd GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3633 (SHRD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3635 def : Pat<(store (shrd (loadi32 addr:$dst), (i8 imm:$amt1),
3636 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3637 (SHRD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3639 // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c)
3640 def : Pat<(or (shl GR32:$src1, CL:$amt),
3641 (srl GR32:$src2, (sub 32, CL:$amt))),
3642 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3644 def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt),
3645 (srl GR32:$src2, (sub 32, CL:$amt))), addr:$dst),
3646 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3648 def : Pat<(or (shl GR32:$src1, (i8 (trunc ECX:$amt))),
3649 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3650 (SHLD32rrCL GR32:$src1, GR32:$src2)>;
3652 def : Pat<(store (or (shl (loadi32 addr:$dst), (i8 (trunc ECX:$amt))),
3653 (srl GR32:$src2, (i8 (trunc (sub 32, ECX:$amt))))),
3655 (SHLD32mrCL addr:$dst, GR32:$src2)>;
3657 def : Pat<(shld GR32:$src1, (i8 imm:$amt1), GR32:$src2, (i8 imm:$amt2)),
3658 (SHLD32rri8 GR32:$src1, GR32:$src2, (i8 imm:$amt1))>;
3660 def : Pat<(store (shld (loadi32 addr:$dst), (i8 imm:$amt1),
3661 GR32:$src2, (i8 imm:$amt2)), addr:$dst),
3662 (SHLD32mri8 addr:$dst, GR32:$src2, (i8 imm:$amt1))>;
3664 // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c)
3665 def : Pat<(or (srl GR16:$src1, CL:$amt),
3666 (shl GR16:$src2, (sub 16, CL:$amt))),
3667 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3669 def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt),
3670 (shl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3671 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3673 def : Pat<(or (srl GR16:$src1, (i8 (trunc CX:$amt))),
3674 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3675 (SHRD16rrCL GR16:$src1, GR16:$src2)>;
3677 def : Pat<(store (or (srl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3678 (shl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3680 (SHRD16mrCL addr:$dst, GR16:$src2)>;
3682 def : Pat<(shrd GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3683 (SHRD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3685 def : Pat<(store (shrd (loadi16 addr:$dst), (i8 imm:$amt1),
3686 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3687 (SHRD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3689 // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c)
3690 def : Pat<(or (shl GR16:$src1, CL:$amt),
3691 (srl GR16:$src2, (sub 16, CL:$amt))),
3692 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3694 def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt),
3695 (srl GR16:$src2, (sub 16, CL:$amt))), addr:$dst),
3696 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3698 def : Pat<(or (shl GR16:$src1, (i8 (trunc CX:$amt))),
3699 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3700 (SHLD16rrCL GR16:$src1, GR16:$src2)>;
3702 def : Pat<(store (or (shl (loadi16 addr:$dst), (i8 (trunc CX:$amt))),
3703 (srl GR16:$src2, (i8 (trunc (sub 16, CX:$amt))))),
3705 (SHLD16mrCL addr:$dst, GR16:$src2)>;
3707 def : Pat<(shld GR16:$src1, (i8 imm:$amt1), GR16:$src2, (i8 imm:$amt2)),
3708 (SHLD16rri8 GR16:$src1, GR16:$src2, (i8 imm:$amt1))>;
3710 def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
3711 GR16:$src2, (i8 imm:$amt2)), addr:$dst),
3712 (SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
3714 //===----------------------------------------------------------------------===//
3715 // EFLAGS-defining Patterns
3716 //===----------------------------------------------------------------------===//
3718 // Register-Register Addition with EFLAGS result
3719 def : Pat<(parallel (X86add_flag GR8:$src1, GR8:$src2),
3721 (ADD8rr GR8:$src1, GR8:$src2)>;
3722 def : Pat<(parallel (X86add_flag GR16:$src1, GR16:$src2),
3724 (ADD16rr GR16:$src1, GR16:$src2)>;
3725 def : Pat<(parallel (X86add_flag GR32:$src1, GR32:$src2),
3727 (ADD32rr GR32:$src1, GR32:$src2)>;
3729 // Register-Memory Addition with EFLAGS result
3730 def : Pat<(parallel (X86add_flag GR8:$src1, (loadi8 addr:$src2)),
3732 (ADD8rm GR8:$src1, addr:$src2)>;
3733 def : Pat<(parallel (X86add_flag GR16:$src1, (loadi16 addr:$src2)),
3735 (ADD16rm GR16:$src1, addr:$src2)>;
3736 def : Pat<(parallel (X86add_flag GR32:$src1, (loadi32 addr:$src2)),
3738 (ADD32rm GR32:$src1, addr:$src2)>;
3740 // Register-Integer Addition with EFLAGS result
3741 def : Pat<(parallel (X86add_flag GR8:$src1, imm:$src2),
3743 (ADD8ri GR8:$src1, imm:$src2)>;
3744 def : Pat<(parallel (X86add_flag GR16:$src1, imm:$src2),
3746 (ADD16ri GR16:$src1, imm:$src2)>;
3747 def : Pat<(parallel (X86add_flag GR32:$src1, imm:$src2),
3749 (ADD32ri GR32:$src1, imm:$src2)>;
3750 def : Pat<(parallel (X86add_flag GR16:$src1, i16immSExt8:$src2),
3752 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
3753 def : Pat<(parallel (X86add_flag GR32:$src1, i32immSExt8:$src2),
3755 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
3757 // Memory-Register Addition with EFLAGS result
3758 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), GR8:$src2),
3761 (ADD8mr addr:$dst, GR8:$src2)>;
3762 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), GR16:$src2),
3765 (ADD16mr addr:$dst, GR16:$src2)>;
3766 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), GR32:$src2),
3769 (ADD32mr addr:$dst, GR32:$src2)>;
3771 // Memory-Integer Addition with EFLAGS result
3772 def : Pat<(parallel (store (X86add_flag (loadi8 addr:$dst), imm:$src2),
3775 (ADD8mi addr:$dst, imm:$src2)>;
3776 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), imm:$src2),
3779 (ADD16mi addr:$dst, imm:$src2)>;
3780 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), imm:$src2),
3783 (ADD32mi addr:$dst, imm:$src2)>;
3784 def : Pat<(parallel (store (X86add_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3787 (ADD16mi8 addr:$dst, i16immSExt8:$src2)>;
3788 def : Pat<(parallel (store (X86add_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3791 (ADD32mi8 addr:$dst, i32immSExt8:$src2)>;
3793 // Register-Register Subtraction with EFLAGS result
3794 def : Pat<(parallel (X86sub_flag GR8:$src1, GR8:$src2),
3796 (SUB8rr GR8:$src1, GR8:$src2)>;
3797 def : Pat<(parallel (X86sub_flag GR16:$src1, GR16:$src2),
3799 (SUB16rr GR16:$src1, GR16:$src2)>;
3800 def : Pat<(parallel (X86sub_flag GR32:$src1, GR32:$src2),
3802 (SUB32rr GR32:$src1, GR32:$src2)>;
3804 // Register-Memory Subtraction with EFLAGS result
3805 def : Pat<(parallel (X86sub_flag GR8:$src1, (loadi8 addr:$src2)),
3807 (SUB8rm GR8:$src1, addr:$src2)>;
3808 def : Pat<(parallel (X86sub_flag GR16:$src1, (loadi16 addr:$src2)),
3810 (SUB16rm GR16:$src1, addr:$src2)>;
3811 def : Pat<(parallel (X86sub_flag GR32:$src1, (loadi32 addr:$src2)),
3813 (SUB32rm GR32:$src1, addr:$src2)>;
3815 // Register-Integer Subtraction with EFLAGS result
3816 def : Pat<(parallel (X86sub_flag GR8:$src1, imm:$src2),
3818 (SUB8ri GR8:$src1, imm:$src2)>;
3819 def : Pat<(parallel (X86sub_flag GR16:$src1, imm:$src2),
3821 (SUB16ri GR16:$src1, imm:$src2)>;
3822 def : Pat<(parallel (X86sub_flag GR32:$src1, imm:$src2),
3824 (SUB32ri GR32:$src1, imm:$src2)>;
3825 def : Pat<(parallel (X86sub_flag GR16:$src1, i16immSExt8:$src2),
3827 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
3828 def : Pat<(parallel (X86sub_flag GR32:$src1, i32immSExt8:$src2),
3830 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
3832 // Memory-Register Subtraction with EFLAGS result
3833 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), GR8:$src2),
3836 (SUB8mr addr:$dst, GR8:$src2)>;
3837 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), GR16:$src2),
3840 (SUB16mr addr:$dst, GR16:$src2)>;
3841 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), GR32:$src2),
3844 (SUB32mr addr:$dst, GR32:$src2)>;
3846 // Memory-Integer Subtraction with EFLAGS result
3847 def : Pat<(parallel (store (X86sub_flag (loadi8 addr:$dst), imm:$src2),
3850 (SUB8mi addr:$dst, imm:$src2)>;
3851 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), imm:$src2),
3854 (SUB16mi addr:$dst, imm:$src2)>;
3855 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), imm:$src2),
3858 (SUB32mi addr:$dst, imm:$src2)>;
3859 def : Pat<(parallel (store (X86sub_flag (loadi16 addr:$dst), i16immSExt8:$src2),
3862 (SUB16mi8 addr:$dst, i16immSExt8:$src2)>;
3863 def : Pat<(parallel (store (X86sub_flag (loadi32 addr:$dst), i32immSExt8:$src2),
3866 (SUB32mi8 addr:$dst, i32immSExt8:$src2)>;
3869 // Register-Register Signed Integer Multiply with EFLAGS result
3870 def : Pat<(parallel (X86smul_flag GR16:$src1, GR16:$src2),
3872 (IMUL16rr GR16:$src1, GR16:$src2)>;
3873 def : Pat<(parallel (X86smul_flag GR32:$src1, GR32:$src2),
3875 (IMUL32rr GR32:$src1, GR32:$src2)>;
3877 // Register-Memory Signed Integer Multiply with EFLAGS result
3878 def : Pat<(parallel (X86smul_flag GR16:$src1, (loadi16 addr:$src2)),
3880 (IMUL16rm GR16:$src1, addr:$src2)>;
3881 def : Pat<(parallel (X86smul_flag GR32:$src1, (loadi32 addr:$src2)),
3883 (IMUL32rm GR32:$src1, addr:$src2)>;
3885 // Register-Integer Signed Integer Multiply with EFLAGS result
3886 def : Pat<(parallel (X86smul_flag GR16:$src1, imm:$src2),
3888 (IMUL16rri GR16:$src1, imm:$src2)>;
3889 def : Pat<(parallel (X86smul_flag GR32:$src1, imm:$src2),
3891 (IMUL32rri GR32:$src1, imm:$src2)>;
3892 def : Pat<(parallel (X86smul_flag GR16:$src1, i16immSExt8:$src2),
3894 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
3895 def : Pat<(parallel (X86smul_flag GR32:$src1, i32immSExt8:$src2),
3897 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
3899 // Memory-Integer Signed Integer Multiply with EFLAGS result
3900 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), imm:$src2),
3902 (IMUL16rmi addr:$src1, imm:$src2)>;
3903 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), imm:$src2),
3905 (IMUL32rmi addr:$src1, imm:$src2)>;
3906 def : Pat<(parallel (X86smul_flag (loadi16 addr:$src1), i16immSExt8:$src2),
3908 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
3909 def : Pat<(parallel (X86smul_flag (loadi32 addr:$src1), i32immSExt8:$src2),
3911 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
3913 // Optimize multiply by 2 with EFLAGS result.
3914 let AddedComplexity = 2 in {
3915 def : Pat<(parallel (X86smul_flag GR16:$src1, 2),
3917 (ADD16rr GR16:$src1, GR16:$src1)>;
3919 def : Pat<(parallel (X86smul_flag GR32:$src1, 2),
3921 (ADD32rr GR32:$src1, GR32:$src1)>;
3924 // INC and DEC with EFLAGS result. Note that these do not set CF.
3925 def : Pat<(parallel (X86inc_flag GR8:$src), (implicit EFLAGS)),
3927 def : Pat<(parallel (store (i8 (X86inc_flag (loadi8 addr:$dst))), addr:$dst),
3930 def : Pat<(parallel (X86dec_flag GR8:$src), (implicit EFLAGS)),
3932 def : Pat<(parallel (store (i8 (X86dec_flag (loadi8 addr:$dst))), addr:$dst),
3936 def : Pat<(parallel (X86inc_flag GR16:$src), (implicit EFLAGS)),
3937 (INC16r GR16:$src)>, Requires<[In32BitMode]>;
3938 def : Pat<(parallel (store (i16 (X86inc_flag (loadi16 addr:$dst))), addr:$dst),
3940 (INC16m addr:$dst)>, Requires<[In32BitMode]>;
3941 def : Pat<(parallel (X86dec_flag GR16:$src), (implicit EFLAGS)),
3942 (DEC16r GR16:$src)>, Requires<[In32BitMode]>;
3943 def : Pat<(parallel (store (i16 (X86dec_flag (loadi16 addr:$dst))), addr:$dst),
3945 (DEC16m addr:$dst)>, Requires<[In32BitMode]>;
3947 def : Pat<(parallel (X86inc_flag GR32:$src), (implicit EFLAGS)),
3948 (INC32r GR32:$src)>, Requires<[In32BitMode]>;
3949 def : Pat<(parallel (store (i32 (X86inc_flag (loadi32 addr:$dst))), addr:$dst),
3951 (INC32m addr:$dst)>, Requires<[In32BitMode]>;
3952 def : Pat<(parallel (X86dec_flag GR32:$src), (implicit EFLAGS)),
3953 (DEC32r GR32:$src)>, Requires<[In32BitMode]>;
3954 def : Pat<(parallel (store (i32 (X86dec_flag (loadi32 addr:$dst))), addr:$dst),
3956 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
3958 //===----------------------------------------------------------------------===//
3959 // Floating Point Stack Support
3960 //===----------------------------------------------------------------------===//
3962 include "X86InstrFPStack.td"
3964 //===----------------------------------------------------------------------===//
3966 //===----------------------------------------------------------------------===//
3968 include "X86Instr64bit.td"
3970 //===----------------------------------------------------------------------===//
3971 // XMM Floating point support (requires SSE / SSE2)
3972 //===----------------------------------------------------------------------===//
3974 include "X86InstrSSE.td"
3976 //===----------------------------------------------------------------------===//
3977 // MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
3978 //===----------------------------------------------------------------------===//
3980 include "X86InstrMMX.td"