1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // X86 specific DAG Nodes.
20 def SDTIntShiftDOp: SDTypeProfile<1, 3,
21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
22 SDTCisInt<0>, SDTCisInt<3>]>;
24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>;
26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
29 def SDTX86Cmov : SDTypeProfile<1, 4,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>;
33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
35 [SDTCisInt<0>, SDTCisVT<1, i32>]>;
37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
40 SDTCisInt<0>, SDTCisVT<1, i32>]>;
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 // RES1, RES2, FLAGS = op LHS, RHS
50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2,
54 SDTCisInt<0>, SDTCisVT<1, i32>]>;
55 def SDTX86BrCond : SDTypeProfile<0, 3,
56 [SDTCisVT<0, OtherVT>,
57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
59 def SDTX86SetCC : SDTypeProfile<1, 2,
61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
62 def SDTX86SetCC_C : SDTypeProfile<1, 2,
64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>;
66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>;
68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>;
70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>,
72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>;
78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>,
88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>,
94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>;
96 def SDTX86Void : SDTypeProfile<0, 0, []>;
98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
117 [SDNPHasChain,SDNPSideEffect]>;
118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER,
122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER,
126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>;
127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>;
128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>;
132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>;
134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>;
140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>;
142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand,
143 [SDNPHasChain, SDNPSideEffect]>;
145 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand,
146 [SDNPHasChain, SDNPSideEffect]>;
148 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
150 SDNPMayLoad, SDNPMemOperand]>;
151 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair,
152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
153 SDNPMayLoad, SDNPMemOperand]>;
154 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair,
155 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
156 SDNPMayLoad, SDNPMemOperand]>;
158 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret,
159 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
161 def X86vastart_save_xmm_regs :
162 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS",
163 SDT_X86VASTART_SAVE_XMM_REGS,
164 [SDNPHasChain, SDNPVariadic]>;
166 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64,
167 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
169 def X86callseq_start :
170 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart,
171 [SDNPHasChain, SDNPOutGlue]>;
173 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd,
174 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
176 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call,
177 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
180 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr,
181 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>;
182 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr,
183 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore,
186 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void,
187 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
188 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void,
189 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
190 def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void,
191 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
193 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>;
194 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>;
196 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR,
197 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
199 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR,
200 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
202 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET,
205 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP",
206 SDTypeProfile<1, 1, [SDTCisInt<0>,
208 [SDNPHasChain, SDNPSideEffect]>;
209 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP",
210 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
211 [SDNPHasChain, SDNPSideEffect]>;
213 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET,
214 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
216 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags,
218 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>;
219 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
221 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags,
223 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
224 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
226 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
227 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
228 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
230 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags,
232 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags,
235 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>;
237 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
239 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void,
240 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
242 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
245 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
246 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
248 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL,
249 [SDNPHasChain, SDNPOutGlue]>;
251 //===----------------------------------------------------------------------===//
252 // X86 Operand Definitions.
255 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
256 // the index operand of an address, to conform to x86 encoding restrictions.
257 def ptr_rc_nosp : PointerLikeRegClass<1>;
259 // *mem - Operand definitions for the funky X86 addressing mode operands.
261 def X86MemAsmOperand : AsmOperandClass {
264 def X86Mem8AsmOperand : AsmOperandClass {
265 let Name = "Mem8"; let RenderMethod = "addMemOperands";
267 def X86Mem16AsmOperand : AsmOperandClass {
268 let Name = "Mem16"; let RenderMethod = "addMemOperands";
270 def X86Mem32AsmOperand : AsmOperandClass {
271 let Name = "Mem32"; let RenderMethod = "addMemOperands";
273 def X86Mem64AsmOperand : AsmOperandClass {
274 let Name = "Mem64"; let RenderMethod = "addMemOperands";
276 def X86Mem80AsmOperand : AsmOperandClass {
277 let Name = "Mem80"; let RenderMethod = "addMemOperands";
279 def X86Mem128AsmOperand : AsmOperandClass {
280 let Name = "Mem128"; let RenderMethod = "addMemOperands";
282 def X86Mem256AsmOperand : AsmOperandClass {
283 let Name = "Mem256"; let RenderMethod = "addMemOperands";
285 def X86Mem512AsmOperand : AsmOperandClass {
286 let Name = "Mem512"; let RenderMethod = "addMemOperands";
289 // Gather mem operands
290 def X86MemVX32Operand : AsmOperandClass {
291 let Name = "MemVX32"; let RenderMethod = "addMemOperands";
293 def X86MemVY32Operand : AsmOperandClass {
294 let Name = "MemVY32"; let RenderMethod = "addMemOperands";
296 def X86MemVZ32Operand : AsmOperandClass {
297 let Name = "MemVZ32"; let RenderMethod = "addMemOperands";
299 def X86MemVX64Operand : AsmOperandClass {
300 let Name = "MemVX64"; let RenderMethod = "addMemOperands";
302 def X86MemVY64Operand : AsmOperandClass {
303 let Name = "MemVY64"; let RenderMethod = "addMemOperands";
305 def X86MemVZ64Operand : AsmOperandClass {
306 let Name = "MemVZ64"; let RenderMethod = "addMemOperands";
309 def X86AbsMemAsmOperand : AsmOperandClass {
311 let SuperClasses = [X86MemAsmOperand];
313 class X86MemOperand<string printMethod> : Operand<iPTR> {
314 let PrintMethod = printMethod;
315 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
316 let ParserMatchClass = X86MemAsmOperand;
319 let OperandType = "OPERAND_MEMORY" in {
320 def opaque32mem : X86MemOperand<"printopaquemem">;
321 def opaque48mem : X86MemOperand<"printopaquemem">;
322 def opaque80mem : X86MemOperand<"printopaquemem">;
323 def opaque512mem : X86MemOperand<"printopaquemem">;
325 def i8mem : X86MemOperand<"printi8mem"> {
326 let ParserMatchClass = X86Mem8AsmOperand; }
327 def i16mem : X86MemOperand<"printi16mem"> {
328 let ParserMatchClass = X86Mem16AsmOperand; }
329 def i32mem : X86MemOperand<"printi32mem"> {
330 let ParserMatchClass = X86Mem32AsmOperand; }
331 def i64mem : X86MemOperand<"printi64mem"> {
332 let ParserMatchClass = X86Mem64AsmOperand; }
333 def i128mem : X86MemOperand<"printi128mem"> {
334 let ParserMatchClass = X86Mem128AsmOperand; }
335 def i256mem : X86MemOperand<"printi256mem"> {
336 let ParserMatchClass = X86Mem256AsmOperand; }
337 def i512mem : X86MemOperand<"printi512mem"> {
338 let ParserMatchClass = X86Mem512AsmOperand; }
339 def f32mem : X86MemOperand<"printf32mem"> {
340 let ParserMatchClass = X86Mem32AsmOperand; }
341 def f64mem : X86MemOperand<"printf64mem"> {
342 let ParserMatchClass = X86Mem64AsmOperand; }
343 def f80mem : X86MemOperand<"printf80mem"> {
344 let ParserMatchClass = X86Mem80AsmOperand; }
345 def f128mem : X86MemOperand<"printf128mem"> {
346 let ParserMatchClass = X86Mem128AsmOperand; }
347 def f256mem : X86MemOperand<"printf256mem">{
348 let ParserMatchClass = X86Mem256AsmOperand; }
349 def f512mem : X86MemOperand<"printf512mem">{
350 let ParserMatchClass = X86Mem512AsmOperand; }
351 def v512mem : Operand<iPTR> {
352 let PrintMethod = "printf512mem";
353 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
354 let ParserMatchClass = X86Mem512AsmOperand; }
356 // Gather mem operands
357 def vx32mem : X86MemOperand<"printi32mem">{
358 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
359 let ParserMatchClass = X86MemVX32Operand; }
360 def vy32mem : X86MemOperand<"printi32mem">{
361 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
362 let ParserMatchClass = X86MemVY32Operand; }
363 def vx64mem : X86MemOperand<"printi64mem">{
364 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm);
365 let ParserMatchClass = X86MemVX64Operand; }
366 def vy64mem : X86MemOperand<"printi64mem">{
367 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm);
368 let ParserMatchClass = X86MemVY64Operand; }
369 def vy64xmem : X86MemOperand<"printi64mem">{
370 let MIOperandInfo = (ops ptr_rc, i8imm, VR256X, i32imm, i8imm);
371 let ParserMatchClass = X86MemVY64Operand; }
372 def vz32mem : X86MemOperand<"printi32mem">{
373 let MIOperandInfo = (ops ptr_rc, i16imm, VR512, i32imm, i8imm);
374 let ParserMatchClass = X86MemVZ32Operand; }
375 def vz64mem : X86MemOperand<"printi64mem">{
376 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm);
377 let ParserMatchClass = X86MemVZ64Operand; }
380 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of
381 // plain GR64, so that it doesn't potentially require a REX prefix.
382 def i8mem_NOREX : Operand<i64> {
383 let PrintMethod = "printi8mem";
384 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm);
385 let ParserMatchClass = X86Mem8AsmOperand;
386 let OperandType = "OPERAND_MEMORY";
389 // GPRs available for tailcall.
390 // It represents GR32_TC, GR64_TC or GR64_TCW64.
391 def ptr_rc_tailcall : PointerLikeRegClass<2>;
393 // Special i32mem for addresses of load folding tail calls. These are not
394 // allowed to use callee-saved registers since they must be scheduled
395 // after callee-saved register are popped.
396 def i32mem_TC : Operand<i32> {
397 let PrintMethod = "printi32mem";
398 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall,
400 let ParserMatchClass = X86Mem32AsmOperand;
401 let OperandType = "OPERAND_MEMORY";
404 // Special i64mem for addresses of load folding tail calls. These are not
405 // allowed to use callee-saved registers since they must be scheduled
406 // after callee-saved register are popped.
407 def i64mem_TC : Operand<i64> {
408 let PrintMethod = "printi64mem";
409 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
410 ptr_rc_tailcall, i32imm, i8imm);
411 let ParserMatchClass = X86Mem64AsmOperand;
412 let OperandType = "OPERAND_MEMORY";
415 let OperandType = "OPERAND_PCREL",
416 ParserMatchClass = X86AbsMemAsmOperand,
417 PrintMethod = "printPCRelImm" in {
418 def i32imm_pcrel : Operand<i32>;
419 def i16imm_pcrel : Operand<i16>;
421 // Branch targets have OtherVT type and print as pc-relative values.
422 def brtarget : Operand<OtherVT>;
423 def brtarget8 : Operand<OtherVT>;
427 def X86SrcIdx8Operand : AsmOperandClass {
428 let Name = "SrcIdx8";
429 let RenderMethod = "addSrcIdxOperands";
430 let SuperClasses = [X86Mem8AsmOperand];
432 def X86SrcIdx16Operand : AsmOperandClass {
433 let Name = "SrcIdx16";
434 let RenderMethod = "addSrcIdxOperands";
435 let SuperClasses = [X86Mem16AsmOperand];
437 def X86SrcIdx32Operand : AsmOperandClass {
438 let Name = "SrcIdx32";
439 let RenderMethod = "addSrcIdxOperands";
440 let SuperClasses = [X86Mem32AsmOperand];
442 def X86SrcIdx64Operand : AsmOperandClass {
443 let Name = "SrcIdx64";
444 let RenderMethod = "addSrcIdxOperands";
445 let SuperClasses = [X86Mem64AsmOperand];
447 def X86DstIdx8Operand : AsmOperandClass {
448 let Name = "DstIdx8";
449 let RenderMethod = "addDstIdxOperands";
450 let SuperClasses = [X86Mem8AsmOperand];
452 def X86DstIdx16Operand : AsmOperandClass {
453 let Name = "DstIdx16";
454 let RenderMethod = "addDstIdxOperands";
455 let SuperClasses = [X86Mem16AsmOperand];
457 def X86DstIdx32Operand : AsmOperandClass {
458 let Name = "DstIdx32";
459 let RenderMethod = "addDstIdxOperands";
460 let SuperClasses = [X86Mem32AsmOperand];
462 def X86DstIdx64Operand : AsmOperandClass {
463 let Name = "DstIdx64";
464 let RenderMethod = "addDstIdxOperands";
465 let SuperClasses = [X86Mem64AsmOperand];
467 def X86MemOffs16_8AsmOperand : AsmOperandClass {
468 let Name = "MemOffs16_8";
469 let RenderMethod = "addMemOffsOperands";
470 let SuperClasses = [X86Mem8AsmOperand];
472 def X86MemOffs16_16AsmOperand : AsmOperandClass {
473 let Name = "MemOffs16_16";
474 let RenderMethod = "addMemOffsOperands";
475 let SuperClasses = [X86Mem16AsmOperand];
477 def X86MemOffs16_32AsmOperand : AsmOperandClass {
478 let Name = "MemOffs16_32";
479 let RenderMethod = "addMemOffsOperands";
480 let SuperClasses = [X86Mem32AsmOperand];
482 def X86MemOffs32_8AsmOperand : AsmOperandClass {
483 let Name = "MemOffs32_8";
484 let RenderMethod = "addMemOffsOperands";
485 let SuperClasses = [X86Mem8AsmOperand];
487 def X86MemOffs32_16AsmOperand : AsmOperandClass {
488 let Name = "MemOffs32_16";
489 let RenderMethod = "addMemOffsOperands";
490 let SuperClasses = [X86Mem16AsmOperand];
492 def X86MemOffs32_32AsmOperand : AsmOperandClass {
493 let Name = "MemOffs32_32";
494 let RenderMethod = "addMemOffsOperands";
495 let SuperClasses = [X86Mem32AsmOperand];
497 def X86MemOffs64_8AsmOperand : AsmOperandClass {
498 let Name = "MemOffs64_8";
499 let RenderMethod = "addMemOffsOperands";
500 let SuperClasses = [X86Mem8AsmOperand];
502 def X86MemOffs64_16AsmOperand : AsmOperandClass {
503 let Name = "MemOffs64_16";
504 let RenderMethod = "addMemOffsOperands";
505 let SuperClasses = [X86Mem16AsmOperand];
507 def X86MemOffs64_32AsmOperand : AsmOperandClass {
508 let Name = "MemOffs64_32";
509 let RenderMethod = "addMemOffsOperands";
510 let SuperClasses = [X86Mem32AsmOperand];
512 def X86MemOffs64_64AsmOperand : AsmOperandClass {
513 let Name = "MemOffs64_64";
514 let RenderMethod = "addMemOffsOperands";
515 let SuperClasses = [X86Mem64AsmOperand];
517 let OperandType = "OPERAND_MEMORY" in {
518 def srcidx8 : Operand<iPTR> {
519 let ParserMatchClass = X86SrcIdx8Operand;
520 let MIOperandInfo = (ops ptr_rc, i8imm);
521 let PrintMethod = "printSrcIdx8"; }
522 def srcidx16 : Operand<iPTR> {
523 let ParserMatchClass = X86SrcIdx16Operand;
524 let MIOperandInfo = (ops ptr_rc, i8imm);
525 let PrintMethod = "printSrcIdx16"; }
526 def srcidx32 : Operand<iPTR> {
527 let ParserMatchClass = X86SrcIdx32Operand;
528 let MIOperandInfo = (ops ptr_rc, i8imm);
529 let PrintMethod = "printSrcIdx32"; }
530 def srcidx64 : Operand<iPTR> {
531 let ParserMatchClass = X86SrcIdx64Operand;
532 let MIOperandInfo = (ops ptr_rc, i8imm);
533 let PrintMethod = "printSrcIdx64"; }
534 def dstidx8 : Operand<iPTR> {
535 let ParserMatchClass = X86DstIdx8Operand;
536 let MIOperandInfo = (ops ptr_rc);
537 let PrintMethod = "printDstIdx8"; }
538 def dstidx16 : Operand<iPTR> {
539 let ParserMatchClass = X86DstIdx16Operand;
540 let MIOperandInfo = (ops ptr_rc);
541 let PrintMethod = "printDstIdx16"; }
542 def dstidx32 : Operand<iPTR> {
543 let ParserMatchClass = X86DstIdx32Operand;
544 let MIOperandInfo = (ops ptr_rc);
545 let PrintMethod = "printDstIdx32"; }
546 def dstidx64 : Operand<iPTR> {
547 let ParserMatchClass = X86DstIdx64Operand;
548 let MIOperandInfo = (ops ptr_rc);
549 let PrintMethod = "printDstIdx64"; }
550 def offset16_8 : Operand<iPTR> {
551 let ParserMatchClass = X86MemOffs16_8AsmOperand;
552 let MIOperandInfo = (ops i64imm, i8imm);
553 let PrintMethod = "printMemOffs8"; }
554 def offset16_16 : Operand<iPTR> {
555 let ParserMatchClass = X86MemOffs16_16AsmOperand;
556 let MIOperandInfo = (ops i64imm, i8imm);
557 let PrintMethod = "printMemOffs16"; }
558 def offset16_32 : Operand<iPTR> {
559 let ParserMatchClass = X86MemOffs16_32AsmOperand;
560 let MIOperandInfo = (ops i64imm, i8imm);
561 let PrintMethod = "printMemOffs32"; }
562 def offset32_8 : Operand<iPTR> {
563 let ParserMatchClass = X86MemOffs32_8AsmOperand;
564 let MIOperandInfo = (ops i64imm, i8imm);
565 let PrintMethod = "printMemOffs8"; }
566 def offset32_16 : Operand<iPTR> {
567 let ParserMatchClass = X86MemOffs32_16AsmOperand;
568 let MIOperandInfo = (ops i64imm, i8imm);
569 let PrintMethod = "printMemOffs16"; }
570 def offset32_32 : Operand<iPTR> {
571 let ParserMatchClass = X86MemOffs32_32AsmOperand;
572 let MIOperandInfo = (ops i64imm, i8imm);
573 let PrintMethod = "printMemOffs32"; }
574 def offset64_8 : Operand<iPTR> {
575 let ParserMatchClass = X86MemOffs64_8AsmOperand;
576 let MIOperandInfo = (ops i64imm, i8imm);
577 let PrintMethod = "printMemOffs8"; }
578 def offset64_16 : Operand<iPTR> {
579 let ParserMatchClass = X86MemOffs64_16AsmOperand;
580 let MIOperandInfo = (ops i64imm, i8imm);
581 let PrintMethod = "printMemOffs16"; }
582 def offset64_32 : Operand<iPTR> {
583 let ParserMatchClass = X86MemOffs64_32AsmOperand;
584 let MIOperandInfo = (ops i64imm, i8imm);
585 let PrintMethod = "printMemOffs32"; }
586 def offset64_64 : Operand<iPTR> {
587 let ParserMatchClass = X86MemOffs64_64AsmOperand;
588 let MIOperandInfo = (ops i64imm, i8imm);
589 let PrintMethod = "printMemOffs64"; }
593 def SSECC : Operand<i8> {
594 let PrintMethod = "printSSECC";
595 let OperandType = "OPERAND_IMMEDIATE";
598 def i8immZExt3 : ImmLeaf<i8, [{
599 return Imm >= 0 && Imm < 8;
602 def AVXCC : Operand<i8> {
603 let PrintMethod = "printAVXCC";
604 let OperandType = "OPERAND_IMMEDIATE";
607 def i8immZExt5 : ImmLeaf<i8, [{
608 return Imm >= 0 && Imm < 32;
610 // AVX-512 uses a 32-bit immediate in their intrinsics
611 def i32immZExt5 : ImmLeaf<i32, [{
612 return Imm >= 0 && Imm < 32;
615 class ImmSExtAsmOperandClass : AsmOperandClass {
616 let SuperClasses = [ImmAsmOperand];
617 let RenderMethod = "addImmOperands";
620 def X86GR32orGR64AsmOperand : AsmOperandClass {
621 let Name = "GR32orGR64";
624 def GR32orGR64 : RegisterOperand<GR32> {
625 let ParserMatchClass = X86GR32orGR64AsmOperand;
628 def AVX512RC : Operand<i32> {
629 let PrintMethod = "printRoundingControl";
630 let OperandType = "OPERAND_IMMEDIATE";
633 // Sign-extended immediate classes. We don't need to define the full lattice
634 // here because there is no instruction with an ambiguity between ImmSExti64i32
637 // The strange ranges come from the fact that the assembler always works with
638 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1"
639 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits).
642 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF]
643 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass {
644 let Name = "ImmSExti64i32";
647 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] |
648 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
649 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass {
650 let Name = "ImmSExti16i8";
651 let SuperClasses = [ImmSExti64i32AsmOperand];
654 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] |
655 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
656 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass {
657 let Name = "ImmSExti32i8";
661 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]
662 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {
663 let Name = "ImmSExti64i8";
664 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand,
665 ImmSExti64i32AsmOperand];
668 // A couple of more descriptive operand definitions.
669 // 16-bits but only 8 bits are significant.
670 def i16i8imm : Operand<i16> {
671 let ParserMatchClass = ImmSExti16i8AsmOperand;
672 let OperandType = "OPERAND_IMMEDIATE";
674 // 32-bits but only 8 bits are significant.
675 def i32i8imm : Operand<i32> {
676 let ParserMatchClass = ImmSExti32i8AsmOperand;
677 let OperandType = "OPERAND_IMMEDIATE";
680 // 64-bits but only 32 bits are significant.
681 def i64i32imm : Operand<i64> {
682 let ParserMatchClass = ImmSExti64i32AsmOperand;
683 let OperandType = "OPERAND_IMMEDIATE";
686 // 64-bits but only 32 bits are significant, and those bits are treated as being
688 def i64i32imm_pcrel : Operand<i64> {
689 let PrintMethod = "printPCRelImm";
690 let ParserMatchClass = X86AbsMemAsmOperand;
691 let OperandType = "OPERAND_PCREL";
694 // 64-bits but only 8 bits are significant.
695 def i64i8imm : Operand<i64> {
696 let ParserMatchClass = ImmSExti64i8AsmOperand;
697 let OperandType = "OPERAND_IMMEDIATE";
700 def lea64_32mem : Operand<i32> {
701 let PrintMethod = "printi32mem";
702 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
703 let ParserMatchClass = X86MemAsmOperand;
706 // Memory operands that use 64-bit pointers in both ILP32 and LP64.
707 def lea64mem : Operand<i64> {
708 let PrintMethod = "printi64mem";
709 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm);
710 let ParserMatchClass = X86MemAsmOperand;
714 //===----------------------------------------------------------------------===//
715 // X86 Complex Pattern Definitions.
718 // Define X86 specific addressing mode.
719 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>;
720 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr",
721 [add, sub, mul, X86mul_imm, shl, or, frameindex],
723 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing.
724 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr",
725 [add, sub, mul, X86mul_imm, shl, or,
726 frameindex, X86WrapperRIP],
729 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
730 [tglobaltlsaddr], []>;
732 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr",
733 [tglobaltlsaddr], []>;
735 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr",
736 [add, sub, mul, X86mul_imm, shl, or, frameindex,
739 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
740 [tglobaltlsaddr], []>;
742 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr",
743 [tglobaltlsaddr], []>;
745 //===----------------------------------------------------------------------===//
746 // X86 Instruction Predicate Definitions.
747 def HasCMov : Predicate<"Subtarget->hasCMov()">;
748 def NoCMov : Predicate<"!Subtarget->hasCMov()">;
750 def HasMMX : Predicate<"Subtarget->hasMMX()">;
751 def Has3DNow : Predicate<"Subtarget->has3DNow()">;
752 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">;
753 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
754 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">;
755 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">;
756 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">;
757 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">;
758 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">;
759 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">;
760 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">;
761 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">;
762 def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">;
763 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">;
764 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">;
765 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">;
766 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">;
767 def HasAVX : Predicate<"Subtarget->hasAVX()">;
768 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">;
769 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">;
770 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">,
771 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">;
772 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">;
773 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">;
774 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">;
775 def HasCDI : Predicate<"Subtarget->hasCDI()">;
776 def HasPFI : Predicate<"Subtarget->hasPFI()">;
777 def HasERI : Predicate<"Subtarget->hasERI()">;
778 def HasDQI : Predicate<"Subtarget->hasDQI()">;
779 def NoDQI : Predicate<"!Subtarget->hasDQI()">;
780 def HasBWI : Predicate<"Subtarget->hasBWI()">;
781 def HasVLX : Predicate<"Subtarget->hasVLX()">,
782 AssemblerPredicate<"FeatureVLX", "AVX-512 VLX ISA">;
783 def NoVLX : Predicate<"!Subtarget->hasVLX()">;
785 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
786 def HasAES : Predicate<"Subtarget->hasAES()">;
787 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">;
788 def HasFMA : Predicate<"Subtarget->hasFMA()">;
789 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">;
790 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
791 def HasXOP : Predicate<"Subtarget->hasXOP()">;
792 def HasTBM : Predicate<"Subtarget->hasTBM()">;
793 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
794 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
795 def HasF16C : Predicate<"Subtarget->hasF16C()">;
796 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">;
797 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
798 def HasBMI : Predicate<"Subtarget->hasBMI()">;
799 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
800 def HasRTM : Predicate<"Subtarget->hasRTM()">;
801 def HasHLE : Predicate<"Subtarget->hasHLE()">;
802 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
803 def HasADX : Predicate<"Subtarget->hasADX()">;
804 def HasSHA : Predicate<"Subtarget->hasSHA()">;
805 def HasSGX : Predicate<"Subtarget->hasSGX()">;
806 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
807 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
808 def HasSMAP : Predicate<"Subtarget->hasSMAP()">;
809 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
810 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
811 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
812 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
813 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
814 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
815 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
816 AssemblerPredicate<"Mode64Bit", "64-bit mode">;
817 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
818 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
819 def In16BitMode : Predicate<"Subtarget->is16Bit()">,
820 AssemblerPredicate<"Mode16Bit", "16-bit mode">;
821 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">,
822 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">;
823 def In32BitMode : Predicate<"Subtarget->is32Bit()">,
824 AssemblerPredicate<"Mode32Bit", "32-bit mode">;
825 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">;
826 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
827 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
828 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">;
829 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">;
830 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&"
831 "TM.getCodeModel() != CodeModel::Kernel">;
832 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||"
833 "TM.getCodeModel() == CodeModel::Kernel">;
834 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
835 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">;
836 def OptForSize : Predicate<"OptForSize">;
837 def OptForSpeed : Predicate<"!OptForSize">;
838 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">;
839 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">;
840 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">;
841 def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">;
842 def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">;
844 //===----------------------------------------------------------------------===//
845 // X86 Instruction Format Definitions.
848 include "X86InstrFormats.td"
850 //===----------------------------------------------------------------------===//
851 // Pattern fragments.
854 // X86 specific condition code. These correspond to CondCode in
855 // X86InstrInfo.h. They must be kept in synch.
856 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE
857 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC
858 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C
859 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA
860 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z
861 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE
862 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL
863 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE
864 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG
865 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ
866 def X86_COND_NO : PatLeaf<(i8 10)>;
867 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO
868 def X86_COND_NS : PatLeaf<(i8 12)>;
869 def X86_COND_O : PatLeaf<(i8 13)>;
870 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
871 def X86_COND_S : PatLeaf<(i8 15)>;
873 // Predicate used to help when pattern matching LZCNT/TZCNT.
874 def X86_COND_E_OR_NE : ImmLeaf<i8, [{
875 return (Imm == X86::COND_E) || (Imm == X86::COND_NE);
878 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
879 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
880 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
881 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>;
884 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>;
887 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
889 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>;
891 def i64immZExt32SExt8 : ImmLeaf<i64, [{
892 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm;
895 // Helper fragments for loads.
896 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is
897 // known to be 32-bit aligned or better. Ditto for i8 to i16.
898 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{
899 LoadSDNode *LD = cast<LoadSDNode>(N);
900 ISD::LoadExtType ExtType = LD->getExtensionType();
901 if (ExtType == ISD::NON_EXTLOAD)
903 if (ExtType == ISD::EXTLOAD)
904 return LD->getAlignment() >= 2 && !LD->isVolatile();
908 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{
909 LoadSDNode *LD = cast<LoadSDNode>(N);
910 ISD::LoadExtType ExtType = LD->getExtensionType();
911 if (ExtType == ISD::EXTLOAD)
912 return LD->getAlignment() >= 2 && !LD->isVolatile();
916 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{
917 LoadSDNode *LD = cast<LoadSDNode>(N);
918 ISD::LoadExtType ExtType = LD->getExtensionType();
919 if (ExtType == ISD::NON_EXTLOAD)
921 if (ExtType == ISD::EXTLOAD)
922 return LD->getAlignment() >= 4 && !LD->isVolatile();
926 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>;
927 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>;
928 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>;
929 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>;
930 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>;
932 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>;
933 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>;
934 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
935 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
936 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
937 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
939 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>;
940 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>;
941 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>;
942 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
943 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>;
944 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
945 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
946 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
947 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
948 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
950 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>;
951 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>;
952 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>;
953 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>;
954 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>;
955 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
956 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
957 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
958 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
959 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
962 // An 'and' node with a single use.
963 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
964 return N->hasOneUse();
966 // An 'srl' node with a single use.
967 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{
968 return N->hasOneUse();
970 // An 'trunc' node with a single use.
971 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
972 return N->hasOneUse();
975 //===----------------------------------------------------------------------===//
980 let hasSideEffects = 0, SchedRW = [WriteZero] in {
981 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
982 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
983 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
984 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
985 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
989 // Constructing a stack frame.
990 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
991 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>;
993 let SchedRW = [WriteALU] in {
994 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
995 def LEAVE : I<0xC9, RawFrm,
996 (outs), (ins), "leave", [], IIC_LEAVE>,
997 Requires<[Not64BitMode]>;
999 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
1000 def LEAVE64 : I<0xC9, RawFrm,
1001 (outs), (ins), "leave", [], IIC_LEAVE>,
1002 Requires<[In64BitMode]>;
1005 //===----------------------------------------------------------------------===//
1006 // Miscellaneous Instructions.
1009 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
1010 let mayLoad = 1, SchedRW = [WriteLoad] in {
1011 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
1012 IIC_POP_REG16>, OpSize16;
1013 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1014 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1015 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
1016 IIC_POP_REG>, OpSize16;
1017 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
1018 IIC_POP_MEM>, OpSize16;
1019 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
1020 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
1021 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
1022 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>;
1023 } // mayLoad, SchedRW
1025 let mayStore = 1, SchedRW = [WriteStore] in {
1026 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1027 IIC_PUSH_REG>, OpSize16;
1028 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1029 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1030 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
1031 IIC_PUSH_REG>, OpSize16;
1032 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
1033 IIC_PUSH_MEM>, OpSize16;
1034 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
1035 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
1036 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
1037 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
1039 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
1040 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1041 Requires<[Not64BitMode]>;
1042 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
1043 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1044 Requires<[Not64BitMode]>;
1045 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1046 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1047 Requires<[Not64BitMode]>;
1048 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
1049 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1050 Requires<[Not64BitMode]>;
1051 } // mayStore, SchedRW
1054 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1055 SchedRW = [WriteLoad] in {
1056 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
1058 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
1059 OpSize32, Requires<[Not64BitMode]>;
1062 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1063 SchedRW = [WriteStore] in {
1064 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
1066 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
1067 OpSize32, Requires<[Not64BitMode]>;
1070 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
1071 let mayLoad = 1, SchedRW = [WriteLoad] in {
1072 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1073 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1074 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [],
1075 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>;
1076 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [],
1077 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>;
1078 } // mayLoad, SchedRW
1079 let mayStore = 1, SchedRW = [WriteStore] in {
1080 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1081 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1082 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [],
1083 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>;
1084 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [],
1085 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>;
1086 } // mayStore, SchedRW
1089 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1090 SchedRW = [WriteStore] in {
1091 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
1092 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
1093 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
1094 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
1095 Requires<[In64BitMode]>;
1096 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
1097 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
1098 Requires<[In64BitMode]>;
1101 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1102 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>,
1103 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>;
1104 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1105 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
1106 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1108 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
1109 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1110 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
1111 OpSize32, Requires<[Not64BitMode]>;
1112 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
1113 OpSize16, Requires<[Not64BitMode]>;
1115 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
1116 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1117 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
1118 OpSize32, Requires<[Not64BitMode]>;
1119 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
1120 OpSize16, Requires<[Not64BitMode]>;
1123 let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
1124 // GR32 = bswap GR32
1125 def BSWAP32r : I<0xC8, AddRegFrm,
1126 (outs GR32:$dst), (ins GR32:$src),
1128 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
1130 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
1132 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB;
1133 } // Constraints = "$src = $dst", SchedRW
1135 // Bit scan instructions.
1136 let Defs = [EFLAGS] in {
1137 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1138 "bsf{w}\t{$src, $dst|$dst, $src}",
1139 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1140 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1141 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1142 "bsf{w}\t{$src, $dst|$dst, $src}",
1143 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1144 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1145 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1146 "bsf{l}\t{$src, $dst|$dst, $src}",
1147 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1148 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1149 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1150 "bsf{l}\t{$src, $dst|$dst, $src}",
1151 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1152 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1153 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1154 "bsf{q}\t{$src, $dst|$dst, $src}",
1155 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1156 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1157 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1158 "bsf{q}\t{$src, $dst|$dst, $src}",
1159 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1160 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1162 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1163 "bsr{w}\t{$src, $dst|$dst, $src}",
1164 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1165 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1166 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1167 "bsr{w}\t{$src, $dst|$dst, $src}",
1168 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1169 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1170 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1171 "bsr{l}\t{$src, $dst|$dst, $src}",
1172 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1173 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1174 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1175 "bsr{l}\t{$src, $dst|$dst, $src}",
1176 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1177 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1178 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1179 "bsr{q}\t{$src, $dst|$dst, $src}",
1180 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1181 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1182 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1183 "bsr{q}\t{$src, $dst|$dst, $src}",
1184 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1185 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1186 } // Defs = [EFLAGS]
1188 let SchedRW = [WriteMicrocoded] in {
1189 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1190 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
1191 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
1192 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1193 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
1194 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
1195 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
1196 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
1197 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
1198 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
1201 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1202 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in
1203 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
1204 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
1205 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
1206 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
1207 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
1208 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
1209 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
1210 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
1211 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
1212 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
1213 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
1215 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1216 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in
1217 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
1218 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
1219 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in
1220 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
1221 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
1222 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in
1223 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
1224 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
1225 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in
1226 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
1227 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
1229 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1230 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in {
1231 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
1232 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1233 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
1234 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
1235 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
1236 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
1237 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
1238 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
1242 //===----------------------------------------------------------------------===//
1243 // Move Instructions.
1245 let SchedRW = [WriteMove] in {
1246 let hasSideEffects = 0 in {
1247 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1248 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1249 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1250 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1251 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1252 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1253 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1254 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1257 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1258 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
1259 "mov{b}\t{$src, $dst|$dst, $src}",
1260 [(set GR8:$dst, imm:$src)], IIC_MOV>;
1261 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
1262 "mov{w}\t{$src, $dst|$dst, $src}",
1263 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
1264 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
1265 "mov{l}\t{$src, $dst|$dst, $src}",
1266 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
1267 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
1268 "mov{q}\t{$src, $dst|$dst, $src}",
1269 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>;
1271 let isReMaterializable = 1 in {
1272 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1273 "movabs{q}\t{$src, $dst|$dst, $src}",
1274 [(set GR64:$dst, imm:$src)], IIC_MOV>;
1277 // Longer forms that use a ModR/M byte. Needed for disassembler
1278 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
1279 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src),
1280 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1281 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src),
1282 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1283 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src),
1284 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1288 let SchedRW = [WriteStore] in {
1289 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
1290 "mov{b}\t{$src, $dst|$dst, $src}",
1291 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
1292 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
1293 "mov{w}\t{$src, $dst|$dst, $src}",
1294 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
1295 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
1296 "mov{l}\t{$src, $dst|$dst, $src}",
1297 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
1298 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
1299 "mov{q}\t{$src, $dst|$dst, $src}",
1300 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
1303 let hasSideEffects = 0 in {
1305 /// Memory offset versions of moves. The immediate is an address mode sized
1306 /// offset from the segment base.
1307 let SchedRW = [WriteALU] in {
1308 let mayLoad = 1 in {
1310 def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src),
1311 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
1314 def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src),
1315 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1318 def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src),
1319 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1323 def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src),
1324 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16;
1326 def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src),
1327 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
1330 def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src),
1331 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
1334 let mayStore = 1 in {
1336 def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins),
1337 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32;
1339 def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins),
1340 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1343 def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins),
1344 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1348 def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins),
1349 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16;
1351 def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins),
1352 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
1355 def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins),
1356 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
1361 // These forms all have full 64-bit absolute addresses in their instructions
1362 // and use the movabs mnemonic to indicate this specific form.
1363 let mayLoad = 1 in {
1365 def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src),
1366 "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64;
1368 def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src),
1369 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64;
1371 def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src),
1372 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
1375 def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src),
1376 "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64;
1379 let mayStore = 1 in {
1381 def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins),
1382 "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64;
1384 def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins),
1385 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64;
1387 def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins),
1388 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
1391 def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins),
1392 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64;
1394 } // hasSideEffects = 0
1396 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1397 SchedRW = [WriteMove] in {
1398 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
1399 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1400 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
1401 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
1402 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
1403 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
1404 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
1405 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
1408 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1409 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
1410 "mov{b}\t{$src, $dst|$dst, $src}",
1411 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
1412 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1413 "mov{w}\t{$src, $dst|$dst, $src}",
1414 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
1415 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1416 "mov{l}\t{$src, $dst|$dst, $src}",
1417 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
1418 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1419 "mov{q}\t{$src, $dst|$dst, $src}",
1420 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
1423 let SchedRW = [WriteStore] in {
1424 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
1425 "mov{b}\t{$src, $dst|$dst, $src}",
1426 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
1427 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1428 "mov{w}\t{$src, $dst|$dst, $src}",
1429 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
1430 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1431 "mov{l}\t{$src, $dst|$dst, $src}",
1432 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
1433 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1434 "mov{q}\t{$src, $dst|$dst, $src}",
1435 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
1438 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
1439 // that they can be used for copying and storing h registers, which can't be
1440 // encoded when a REX prefix is present.
1441 let isCodeGenOnly = 1 in {
1442 let hasSideEffects = 0 in
1443 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1444 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
1445 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>,
1447 let mayStore = 1, hasSideEffects = 0 in
1448 def MOV8mr_NOREX : I<0x88, MRMDestMem,
1449 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
1450 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1451 IIC_MOV_MEM>, Sched<[WriteStore]>;
1452 let mayLoad = 1, hasSideEffects = 0,
1453 canFoldAsLoad = 1, isReMaterializable = 1 in
1454 def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
1455 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
1456 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [],
1457 IIC_MOV_MEM>, Sched<[WriteLoad]>;
1461 // Condition code ops, incl. set if equal/not equal/...
1462 let SchedRW = [WriteALU] in {
1463 let Defs = [EFLAGS], Uses = [AH] in
1464 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf",
1465 [(set EFLAGS, (X86sahf AH))], IIC_AHF>;
1466 let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in
1467 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
1468 IIC_AHF>; // AH = flags
1471 //===----------------------------------------------------------------------===//
1472 // Bit tests instructions: BT, BTS, BTR, BTC.
1474 let Defs = [EFLAGS] in {
1475 let SchedRW = [WriteALU] in {
1476 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1477 "bt{w}\t{$src2, $src1|$src1, $src2}",
1478 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
1480 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1481 "bt{l}\t{$src2, $src1|$src1, $src2}",
1482 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
1484 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1485 "bt{q}\t{$src2, $src1|$src1, $src2}",
1486 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
1489 // Unlike with the register+register form, the memory+register form of the
1490 // bt instruction does not ignore the high bits of the index. From ISel's
1491 // perspective, this is pretty bizarre. Make these instructions disassembly
1494 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
1495 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1496 "bt{w}\t{$src2, $src1|$src1, $src2}",
1497 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
1498 // (implicit EFLAGS)]
1500 >, OpSize16, TB, Requires<[FastBTMem]>;
1501 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1502 "bt{l}\t{$src2, $src1|$src1, $src2}",
1503 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
1504 // (implicit EFLAGS)]
1506 >, OpSize32, TB, Requires<[FastBTMem]>;
1507 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1508 "bt{q}\t{$src2, $src1|$src1, $src2}",
1509 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
1510 // (implicit EFLAGS)]
1515 let SchedRW = [WriteALU] in {
1516 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1517 "bt{w}\t{$src2, $src1|$src1, $src2}",
1518 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
1519 IIC_BT_RI>, OpSize16, TB;
1520 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1521 "bt{l}\t{$src2, $src1|$src1, $src2}",
1522 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
1523 IIC_BT_RI>, OpSize32, TB;
1524 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1525 "bt{q}\t{$src2, $src1|$src1, $src2}",
1526 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
1530 // Note that these instructions don't need FastBTMem because that
1531 // only applies when the other operand is in a register. When it's
1532 // an immediate, bt is still fast.
1533 let SchedRW = [WriteALU] in {
1534 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1535 "bt{w}\t{$src2, $src1|$src1, $src2}",
1536 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
1537 ], IIC_BT_MI>, OpSize16, TB;
1538 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1539 "bt{l}\t{$src2, $src1|$src1, $src2}",
1540 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
1541 ], IIC_BT_MI>, OpSize32, TB;
1542 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1543 "bt{q}\t{$src2, $src1|$src1, $src2}",
1544 [(set EFLAGS, (X86bt (loadi64 addr:$src1),
1545 i64immSExt8:$src2))], IIC_BT_MI>, TB;
1548 let hasSideEffects = 0 in {
1549 let SchedRW = [WriteALU] in {
1550 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1551 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1553 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1554 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1556 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1557 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1560 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1561 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1562 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1564 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1565 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1567 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1568 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1571 let SchedRW = [WriteALU] in {
1572 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1573 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1575 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1576 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1578 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1579 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1582 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1583 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1584 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1586 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1587 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1589 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1590 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1593 let SchedRW = [WriteALU] in {
1594 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1595 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1597 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1598 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1600 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1601 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
1604 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1605 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1606 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1608 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1609 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1611 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1612 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1615 let SchedRW = [WriteALU] in {
1616 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1617 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1619 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1620 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1622 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1623 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1626 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1627 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1628 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1630 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1631 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1633 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1634 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1637 let SchedRW = [WriteALU] in {
1638 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1639 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1641 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1642 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
1644 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1645 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
1648 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1649 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
1650 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1652 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
1653 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
1655 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
1656 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
1659 let SchedRW = [WriteALU] in {
1660 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1661 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1663 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1664 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
1666 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
1667 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
1670 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1671 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1672 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1674 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1675 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
1677 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
1678 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
1680 } // hasSideEffects = 0
1681 } // Defs = [EFLAGS]
1684 //===----------------------------------------------------------------------===//
1688 // Atomic swap. These are just normal xchg instructions. But since a memory
1689 // operand is referenced, the atomicity is ensured.
1690 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
1691 InstrItinClass itin> {
1692 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in {
1693 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst),
1694 (ins GR8:$val, i8mem:$ptr),
1695 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
1698 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
1700 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst),
1701 (ins GR16:$val, i16mem:$ptr),
1702 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
1705 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
1707 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
1708 (ins GR32:$val, i32mem:$ptr),
1709 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
1712 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
1714 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
1715 (ins GR64:$val, i64mem:$ptr),
1716 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
1719 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
1724 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>;
1726 // Swap between registers.
1727 let SchedRW = [WriteALU] in {
1728 let Constraints = "$val = $dst" in {
1729 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
1730 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1731 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
1732 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1734 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
1735 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
1737 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
1738 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
1741 // Swap between EAX and other registers.
1742 let Uses = [AX], Defs = [AX] in
1743 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
1744 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
1745 let Uses = [EAX], Defs = [EAX] in
1746 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
1747 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1748 OpSize32, Requires<[Not64BitMode]>;
1749 let Uses = [EAX], Defs = [EAX] in
1750 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
1751 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
1752 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
1753 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
1754 OpSize32, Requires<[In64BitMode]>;
1755 let Uses = [RAX], Defs = [RAX] in
1756 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
1757 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
1760 let SchedRW = [WriteALU] in {
1761 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1762 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1763 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1764 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1766 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1767 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
1769 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1770 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
1773 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
1774 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1775 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1776 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1777 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1779 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1780 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
1782 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1783 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
1787 let SchedRW = [WriteALU] in {
1788 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
1789 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1790 IIC_CMPXCHG_REG8>, TB;
1791 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1792 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1793 IIC_CMPXCHG_REG>, TB, OpSize16;
1794 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1795 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1796 IIC_CMPXCHG_REG>, TB, OpSize32;
1797 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1798 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1799 IIC_CMPXCHG_REG>, TB;
1802 let SchedRW = [WriteALULd, WriteRMW] in {
1803 let mayLoad = 1, mayStore = 1 in {
1804 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
1805 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [],
1806 IIC_CMPXCHG_MEM8>, TB;
1807 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1808 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
1809 IIC_CMPXCHG_MEM>, TB, OpSize16;
1810 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1811 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
1812 IIC_CMPXCHG_MEM>, TB, OpSize32;
1813 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1814 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
1815 IIC_CMPXCHG_MEM>, TB;
1818 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in
1819 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst),
1820 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB;
1822 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
1823 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst),
1824 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>,
1825 TB, Requires<[HasCmpxchg16b]>;
1829 // Lock instruction prefix
1830 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
1832 // Rex64 instruction prefix
1833 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>,
1834 Requires<[In64BitMode]>;
1836 // Data16 instruction prefix
1837 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>;
1839 // Repeat string operation instruction prefixes
1840 // These uses the DF flag in the EFLAGS register to inc or dec ECX
1841 let Defs = [ECX], Uses = [ECX,EFLAGS] in {
1842 // Repeat (used with INS, OUTS, MOVS, LODS and STOS)
1843 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
1844 // Repeat while not equal (used with CMPS and SCAS)
1845 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
1849 // String manipulation instructions
1850 let SchedRW = [WriteMicrocoded] in {
1851 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1852 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in
1853 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1854 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1855 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in
1856 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1857 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
1858 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in
1859 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1860 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
1861 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in
1862 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1863 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
1866 let SchedRW = [WriteSystem] in {
1867 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1868 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in {
1869 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
1870 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
1871 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
1872 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
1873 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
1874 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
1877 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI
1878 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in {
1879 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
1880 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
1881 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
1882 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
1883 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
1884 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
1888 // Flag instructions
1889 let SchedRW = [WriteALU] in {
1890 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>;
1891 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>;
1892 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>;
1893 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>;
1894 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>;
1895 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>;
1896 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>;
1898 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB;
1901 // Table lookup instructions
1902 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>,
1905 let SchedRW = [WriteMicrocoded] in {
1906 // ASCII Adjust After Addition
1907 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1908 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>,
1909 Requires<[Not64BitMode]>;
1911 // ASCII Adjust AX Before Division
1912 // sets AL, AH and EFLAGS and uses AL and AH
1913 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src),
1914 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>;
1916 // ASCII Adjust AX After Multiply
1917 // sets AL, AH and EFLAGS and uses AL
1918 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src),
1919 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>;
1921 // ASCII Adjust AL After Subtraction - sets
1922 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS
1923 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>,
1924 Requires<[Not64BitMode]>;
1926 // Decimal Adjust AL after Addition
1927 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1928 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>,
1929 Requires<[Not64BitMode]>;
1931 // Decimal Adjust AL after Subtraction
1932 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS
1933 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
1934 Requires<[Not64BitMode]>;
1937 let SchedRW = [WriteSystem] in {
1938 // Check Array Index Against Bounds
1939 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1940 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
1941 Requires<[Not64BitMode]>;
1942 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1943 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
1944 Requires<[Not64BitMode]>;
1946 // Adjust RPL Field of Segment Selector
1947 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1948 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>,
1949 Requires<[Not64BitMode]>;
1950 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1951 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>,
1952 Requires<[Not64BitMode]>;
1955 //===----------------------------------------------------------------------===//
1956 // MOVBE Instructions
1958 let Predicates = [HasMOVBE] in {
1959 let SchedRW = [WriteALULd] in {
1960 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
1961 "movbe{w}\t{$src, $dst|$dst, $src}",
1962 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1964 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
1965 "movbe{l}\t{$src, $dst|$dst, $src}",
1966 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1968 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
1969 "movbe{q}\t{$src, $dst|$dst, $src}",
1970 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1973 let SchedRW = [WriteStore] in {
1974 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
1975 "movbe{w}\t{$src, $dst|$dst, $src}",
1976 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1978 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1979 "movbe{l}\t{$src, $dst|$dst, $src}",
1980 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1982 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1983 "movbe{q}\t{$src, $dst|$dst, $src}",
1984 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1989 //===----------------------------------------------------------------------===//
1990 // RDRAND Instruction
1992 let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
1993 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
1995 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
1996 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
1998 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
1999 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
2001 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
2004 //===----------------------------------------------------------------------===//
2005 // RDSEED Instruction
2007 let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
2008 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
2010 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
2011 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
2013 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
2014 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
2016 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
2019 //===----------------------------------------------------------------------===//
2020 // LZCNT Instruction
2022 let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
2023 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2024 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2025 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
2027 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2028 "lzcnt{w}\t{$src, $dst|$dst, $src}",
2029 [(set GR16:$dst, (ctlz (loadi16 addr:$src))),
2030 (implicit EFLAGS)]>, XS, OpSize16;
2032 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2033 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2034 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
2036 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2037 "lzcnt{l}\t{$src, $dst|$dst, $src}",
2038 [(set GR32:$dst, (ctlz (loadi32 addr:$src))),
2039 (implicit EFLAGS)]>, XS, OpSize32;
2041 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2042 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2043 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>,
2045 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2046 "lzcnt{q}\t{$src, $dst|$dst, $src}",
2047 [(set GR64:$dst, (ctlz (loadi64 addr:$src))),
2048 (implicit EFLAGS)]>, XS;
2051 let Predicates = [HasLZCNT] in {
2052 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2053 (X86cmp GR16:$src, (i16 0))),
2054 (LZCNT16rr GR16:$src)>;
2055 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2056 (X86cmp GR32:$src, (i32 0))),
2057 (LZCNT32rr GR32:$src)>;
2058 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2059 (X86cmp GR64:$src, (i64 0))),
2060 (LZCNT64rr GR64:$src)>;
2061 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE),
2062 (X86cmp GR16:$src, (i16 0))),
2063 (LZCNT16rr GR16:$src)>;
2064 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE),
2065 (X86cmp GR32:$src, (i32 0))),
2066 (LZCNT32rr GR32:$src)>;
2067 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE),
2068 (X86cmp GR64:$src, (i64 0))),
2069 (LZCNT64rr GR64:$src)>;
2071 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2072 (X86cmp (loadi16 addr:$src), (i16 0))),
2073 (LZCNT16rm addr:$src)>;
2074 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2075 (X86cmp (loadi32 addr:$src), (i32 0))),
2076 (LZCNT32rm addr:$src)>;
2077 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2078 (X86cmp (loadi64 addr:$src), (i64 0))),
2079 (LZCNT64rm addr:$src)>;
2080 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2081 (X86cmp (loadi16 addr:$src), (i16 0))),
2082 (LZCNT16rm addr:$src)>;
2083 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2084 (X86cmp (loadi32 addr:$src), (i32 0))),
2085 (LZCNT32rm addr:$src)>;
2086 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2087 (X86cmp (loadi64 addr:$src), (i64 0))),
2088 (LZCNT64rm addr:$src)>;
2091 //===----------------------------------------------------------------------===//
2094 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2095 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
2096 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2097 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
2099 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
2100 "tzcnt{w}\t{$src, $dst|$dst, $src}",
2101 [(set GR16:$dst, (cttz (loadi16 addr:$src))),
2102 (implicit EFLAGS)]>, XS, OpSize16;
2104 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
2105 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2106 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
2108 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
2109 "tzcnt{l}\t{$src, $dst|$dst, $src}",
2110 [(set GR32:$dst, (cttz (loadi32 addr:$src))),
2111 (implicit EFLAGS)]>, XS, OpSize32;
2113 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
2114 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2115 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>,
2117 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
2118 "tzcnt{q}\t{$src, $dst|$dst, $src}",
2119 [(set GR64:$dst, (cttz (loadi64 addr:$src))),
2120 (implicit EFLAGS)]>, XS;
2123 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
2124 RegisterClass RC, X86MemOperand x86memop> {
2125 let hasSideEffects = 0 in {
2126 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
2127 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2130 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
2131 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
2136 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2137 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2138 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2139 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
2140 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
2141 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
2142 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
2145 //===----------------------------------------------------------------------===//
2146 // Pattern fragments to auto generate BMI instructions.
2147 //===----------------------------------------------------------------------===//
2149 let Predicates = [HasBMI] in {
2150 // FIXME: patterns for the load versions are not implemented
2151 def : Pat<(and GR32:$src, (add GR32:$src, -1)),
2152 (BLSR32rr GR32:$src)>;
2153 def : Pat<(and GR64:$src, (add GR64:$src, -1)),
2154 (BLSR64rr GR64:$src)>;
2156 def : Pat<(xor GR32:$src, (add GR32:$src, -1)),
2157 (BLSMSK32rr GR32:$src)>;
2158 def : Pat<(xor GR64:$src, (add GR64:$src, -1)),
2159 (BLSMSK64rr GR64:$src)>;
2161 def : Pat<(and GR32:$src, (ineg GR32:$src)),
2162 (BLSI32rr GR32:$src)>;
2163 def : Pat<(and GR64:$src, (ineg GR64:$src)),
2164 (BLSI64rr GR64:$src)>;
2167 let Predicates = [HasBMI] in {
2168 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
2169 (X86cmp GR16:$src, (i16 0))),
2170 (TZCNT16rr GR16:$src)>;
2171 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
2172 (X86cmp GR32:$src, (i32 0))),
2173 (TZCNT32rr GR32:$src)>;
2174 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
2175 (X86cmp GR64:$src, (i64 0))),
2176 (TZCNT64rr GR64:$src)>;
2177 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE),
2178 (X86cmp GR16:$src, (i16 0))),
2179 (TZCNT16rr GR16:$src)>;
2180 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE),
2181 (X86cmp GR32:$src, (i32 0))),
2182 (TZCNT32rr GR32:$src)>;
2183 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE),
2184 (X86cmp GR64:$src, (i64 0))),
2185 (TZCNT64rr GR64:$src)>;
2187 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
2188 (X86cmp (loadi16 addr:$src), (i16 0))),
2189 (TZCNT16rm addr:$src)>;
2190 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
2191 (X86cmp (loadi32 addr:$src), (i32 0))),
2192 (TZCNT32rm addr:$src)>;
2193 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
2194 (X86cmp (loadi64 addr:$src), (i64 0))),
2195 (TZCNT64rm addr:$src)>;
2196 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
2197 (X86cmp (loadi16 addr:$src), (i16 0))),
2198 (TZCNT16rm addr:$src)>;
2199 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
2200 (X86cmp (loadi32 addr:$src), (i32 0))),
2201 (TZCNT32rm addr:$src)>;
2202 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
2203 (X86cmp (loadi64 addr:$src), (i64 0))),
2204 (TZCNT64rm addr:$src)>;
2208 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
2209 X86MemOperand x86memop, Intrinsic Int,
2211 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2212 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2213 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2215 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
2216 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2217 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2218 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
2221 let Predicates = [HasBMI], Defs = [EFLAGS] in {
2222 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
2223 int_x86_bmi_bextr_32, loadi32>;
2224 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
2225 int_x86_bmi_bextr_64, loadi64>, VEX_W;
2228 let Predicates = [HasBMI2], Defs = [EFLAGS] in {
2229 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
2230 int_x86_bmi_bzhi_32, loadi32>;
2231 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
2232 int_x86_bmi_bzhi_64, loadi64>, VEX_W;
2236 def CountTrailingOnes : SDNodeXForm<imm, [{
2237 // Count the trailing ones in the immediate.
2238 return getI8Imm(CountTrailingOnes_64(N->getZExtValue()));
2241 def BZHIMask : ImmLeaf<i64, [{
2242 return isMask_64(Imm) && (CountTrailingOnes_64(Imm) > 32);
2245 let Predicates = [HasBMI2] in {
2246 def : Pat<(and GR64:$src, BZHIMask:$mask),
2247 (BZHI64rr GR64:$src,
2248 (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
2249 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>;
2251 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)),
2252 (BZHI32rr GR32:$src,
2253 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2255 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)),
2256 (BZHI32rm addr:$src,
2257 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2259 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)),
2260 (BZHI64rr GR64:$src,
2261 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2263 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)),
2264 (BZHI64rm addr:$src,
2265 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>;
2268 let Predicates = [HasBMI] in {
2269 def : Pat<(X86bextr GR32:$src1, GR32:$src2),
2270 (BEXTR32rr GR32:$src1, GR32:$src2)>;
2271 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
2272 (BEXTR32rm addr:$src1, GR32:$src2)>;
2273 def : Pat<(X86bextr GR64:$src1, GR64:$src2),
2274 (BEXTR64rr GR64:$src1, GR64:$src2)>;
2275 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
2276 (BEXTR64rm addr:$src1, GR64:$src2)>;
2279 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
2280 X86MemOperand x86memop, Intrinsic Int,
2282 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
2283 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2284 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
2286 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2287 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2288 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
2291 let Predicates = [HasBMI2] in {
2292 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
2293 int_x86_bmi_pdep_32, loadi32>, T8XD;
2294 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
2295 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
2296 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
2297 int_x86_bmi_pext_32, loadi32>, T8XS;
2298 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
2299 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
2302 //===----------------------------------------------------------------------===//
2305 let Predicates = [HasTBM], Defs = [EFLAGS] in {
2307 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
2308 X86MemOperand x86memop, PatFrag ld_frag,
2309 Intrinsic Int, Operand immtype,
2310 SDPatternOperator immoperator> {
2311 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
2312 !strconcat(OpcodeStr,
2313 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2314 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
2316 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
2317 (ins x86memop:$src1, immtype:$cntl),
2318 !strconcat(OpcodeStr,
2319 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
2320 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
2324 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32,
2325 int_x86_tbm_bextri_u32, i32imm, imm>;
2326 let ImmT = Imm32S in
2327 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64,
2328 int_x86_tbm_bextri_u64, i64i32imm,
2329 i64immSExt32>, VEX_W;
2331 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
2332 RegisterClass RC, string OpcodeStr,
2333 X86MemOperand x86memop, PatFrag ld_frag> {
2334 let hasSideEffects = 0 in {
2335 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
2336 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2339 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
2340 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
2345 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
2346 Format FormReg, Format FormMem> {
2347 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem,
2349 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem,
2353 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2354 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
2355 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
2356 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
2357 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
2358 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
2359 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
2360 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2361 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
2364 //===----------------------------------------------------------------------===//
2365 // Pattern fragments to auto generate TBM instructions.
2366 //===----------------------------------------------------------------------===//
2368 let Predicates = [HasTBM] in {
2369 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)),
2370 (BEXTRI32ri GR32:$src1, imm:$src2)>;
2371 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
2372 (BEXTRI32mi addr:$src1, imm:$src2)>;
2373 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2),
2374 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>;
2375 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2),
2376 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>;
2378 // FIXME: patterns for the load versions are not implemented
2379 def : Pat<(and GR32:$src, (add GR32:$src, 1)),
2380 (BLCFILL32rr GR32:$src)>;
2381 def : Pat<(and GR64:$src, (add GR64:$src, 1)),
2382 (BLCFILL64rr GR64:$src)>;
2384 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
2385 (BLCI32rr GR32:$src)>;
2386 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
2387 (BLCI64rr GR64:$src)>;
2389 // Extra patterns because opt can optimize the above patterns to this.
2390 def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
2391 (BLCI32rr GR32:$src)>;
2392 def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
2393 (BLCI64rr GR64:$src)>;
2395 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
2396 (BLCIC32rr GR32:$src)>;
2397 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
2398 (BLCIC64rr GR64:$src)>;
2400 def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
2401 (BLCMSK32rr GR32:$src)>;
2402 def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
2403 (BLCMSK64rr GR64:$src)>;
2405 def : Pat<(or GR32:$src, (add GR32:$src, 1)),
2406 (BLCS32rr GR32:$src)>;
2407 def : Pat<(or GR64:$src, (add GR64:$src, 1)),
2408 (BLCS64rr GR64:$src)>;
2410 def : Pat<(or GR32:$src, (add GR32:$src, -1)),
2411 (BLSFILL32rr GR32:$src)>;
2412 def : Pat<(or GR64:$src, (add GR64:$src, -1)),
2413 (BLSFILL64rr GR64:$src)>;
2415 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
2416 (BLSIC32rr GR32:$src)>;
2417 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
2418 (BLSIC64rr GR64:$src)>;
2420 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
2421 (T1MSKC32rr GR32:$src)>;
2422 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
2423 (T1MSKC64rr GR64:$src)>;
2425 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
2426 (TZMSK32rr GR32:$src)>;
2427 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
2428 (TZMSK64rr GR64:$src)>;
2431 //===----------------------------------------------------------------------===//
2433 //===----------------------------------------------------------------------===//
2435 include "X86InstrArithmetic.td"
2436 include "X86InstrCMovSetCC.td"
2437 include "X86InstrExtension.td"
2438 include "X86InstrControl.td"
2439 include "X86InstrShiftRotate.td"
2441 // X87 Floating Point Stack.
2442 include "X86InstrFPStack.td"
2444 // SIMD support (SSE, MMX and AVX)
2445 include "X86InstrFragmentsSIMD.td"
2447 // FMA - Fused Multiply-Add support (requires FMA)
2448 include "X86InstrFMA.td"
2451 include "X86InstrXOP.td"
2453 // SSE, MMX and 3DNow! vector support.
2454 include "X86InstrSSE.td"
2455 include "X86InstrAVX512.td"
2456 include "X86InstrMMX.td"
2457 include "X86Instr3DNow.td"
2459 include "X86InstrVMX.td"
2460 include "X86InstrSVM.td"
2462 include "X86InstrTSX.td"
2463 include "X86InstrSGX.td"
2465 // System instructions.
2466 include "X86InstrSystem.td"
2468 // Compiler Pseudo Instructions and Pat Patterns
2469 include "X86InstrCompiler.td"
2471 //===----------------------------------------------------------------------===//
2472 // Assembler Mnemonic Aliases
2473 //===----------------------------------------------------------------------===//
2475 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>;
2476 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>;
2477 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>;
2479 def : MnemonicAlias<"cbw", "cbtw", "att">;
2480 def : MnemonicAlias<"cwde", "cwtl", "att">;
2481 def : MnemonicAlias<"cwd", "cwtd", "att">;
2482 def : MnemonicAlias<"cdq", "cltd", "att">;
2483 def : MnemonicAlias<"cdqe", "cltq", "att">;
2484 def : MnemonicAlias<"cqo", "cqto", "att">;
2486 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq.
2487 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>;
2488 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>;
2490 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>;
2491 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>;
2493 def : MnemonicAlias<"loopz", "loope", "att">;
2494 def : MnemonicAlias<"loopnz", "loopne", "att">;
2496 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>;
2497 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>;
2498 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>;
2499 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>;
2500 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>;
2501 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>;
2502 def : MnemonicAlias<"popfd", "popfl", "att">;
2504 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in
2505 // all modes. However: "push (addr)" and "push $42" should default to
2506 // pushl/pushq depending on the current mode. Similar for "pop %bx"
2507 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>;
2508 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>;
2509 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>;
2510 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>;
2511 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>;
2512 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
2513 def : MnemonicAlias<"pushfd", "pushfl", "att">;
2515 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>;
2516 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>;
2517 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>;
2518 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>;
2519 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>;
2520 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>;
2522 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>;
2523 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>;
2524 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>;
2525 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>;
2527 def : MnemonicAlias<"repe", "rep", "att">;
2528 def : MnemonicAlias<"repz", "rep", "att">;
2529 def : MnemonicAlias<"repnz", "repne", "att">;
2531 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>;
2532 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>;
2533 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>;
2535 def : MnemonicAlias<"salb", "shlb", "att">;
2536 def : MnemonicAlias<"salw", "shlw", "att">;
2537 def : MnemonicAlias<"sall", "shll", "att">;
2538 def : MnemonicAlias<"salq", "shlq", "att">;
2540 def : MnemonicAlias<"smovb", "movsb", "att">;
2541 def : MnemonicAlias<"smovw", "movsw", "att">;
2542 def : MnemonicAlias<"smovl", "movsl", "att">;
2543 def : MnemonicAlias<"smovq", "movsq", "att">;
2545 def : MnemonicAlias<"ud2a", "ud2", "att">;
2546 def : MnemonicAlias<"verrw", "verr", "att">;
2548 // System instruction aliases.
2549 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>;
2550 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>;
2551 def : MnemonicAlias<"sysret", "sysretl", "att">;
2552 def : MnemonicAlias<"sysexit", "sysexitl", "att">;
2554 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>;
2555 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>;
2556 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>;
2557 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>;
2558 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>;
2559 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>;
2560 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>;
2561 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>;
2562 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>;
2563 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>;
2564 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>;
2565 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>;
2568 // Floating point stack aliases.
2569 def : MnemonicAlias<"fcmovz", "fcmove", "att">;
2570 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">;
2571 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">;
2572 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">;
2573 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">;
2574 def : MnemonicAlias<"fcomip", "fcompi", "att">;
2575 def : MnemonicAlias<"fildq", "fildll", "att">;
2576 def : MnemonicAlias<"fistpq", "fistpll", "att">;
2577 def : MnemonicAlias<"fisttpq", "fisttpll", "att">;
2578 def : MnemonicAlias<"fldcww", "fldcw", "att">;
2579 def : MnemonicAlias<"fnstcww", "fnstcw", "att">;
2580 def : MnemonicAlias<"fnstsww", "fnstsw", "att">;
2581 def : MnemonicAlias<"fucomip", "fucompi", "att">;
2582 def : MnemonicAlias<"fwait", "wait">;
2585 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond,
2587 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix),
2588 !strconcat(Prefix, NewCond, Suffix), VariantName>;
2590 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of
2591 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for
2592 /// example "setz" -> "sete".
2593 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix,
2595 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb
2596 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete
2597 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe
2598 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae
2599 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae
2600 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle
2601 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge
2602 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne
2603 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp
2604 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp
2606 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb
2607 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta
2608 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl
2609 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg
2612 // Aliases for set<CC>
2613 defm : IntegerCondCodeMnemonicAlias<"set", "">;
2614 // Aliases for j<CC>
2615 defm : IntegerCondCodeMnemonicAlias<"j", "">;
2616 // Aliases for cmov<CC>{w,l,q}
2617 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">;
2618 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">;
2619 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">;
2620 // No size suffix for intel-style asm.
2621 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">;
2624 //===----------------------------------------------------------------------===//
2625 // Assembler Instruction Aliases
2626 //===----------------------------------------------------------------------===//
2628 // aad/aam default to base 10 if no operand is specified.
2629 def : InstAlias<"aad", (AAD8i8 10)>;
2630 def : InstAlias<"aam", (AAM8i8 10)>;
2632 // Disambiguate the mem/imm form of bt-without-a-suffix as btl.
2633 // Likewise for btc/btr/bts.
2634 def : InstAlias<"bt {$imm, $mem|$mem, $imm}",
2635 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2636 def : InstAlias<"btc {$imm, $mem|$mem, $imm}",
2637 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2638 def : InstAlias<"btr {$imm, $mem|$mem, $imm}",
2639 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2640 def : InstAlias<"bts {$imm, $mem|$mem, $imm}",
2641 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>;
2644 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>;
2645 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>;
2646 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
2647 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
2649 // lods aliases. Accept the destination being omitted because it's implicit
2650 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2651 // in the destination.
2652 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2653 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2654 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2655 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2656 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2657 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2658 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2659 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2661 // stos aliases. Accept the source being omitted because it's implicit in
2662 // the mnemonic, or the mnemonic suffix being omitted because it's implicit
2664 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>;
2665 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>;
2666 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>;
2667 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2668 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>;
2669 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
2670 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
2671 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2673 // scas aliases. Accept the destination being omitted because it's implicit
2674 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2675 // in the destination.
2676 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>;
2677 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>;
2678 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>;
2679 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2680 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>;
2681 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>;
2682 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>;
2683 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
2685 // div and idiv aliases for explicit A register.
2686 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
2687 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
2688 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>;
2689 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>;
2690 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>;
2691 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>;
2692 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>;
2693 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>;
2694 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>;
2695 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>;
2696 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>;
2697 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>;
2698 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>;
2699 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>;
2700 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
2701 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
2705 // Various unary fpstack operations default to operating on on ST1.
2706 // For example, "fxch" -> "fxch %st(1)"
2707 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>;
2708 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>;
2709 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>;
2710 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>;
2711 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>;
2712 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>;
2713 def : InstAlias<"fxch", (XCH_F ST1), 0>;
2714 def : InstAlias<"fcom", (COM_FST0r ST1), 0>;
2715 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>;
2716 def : InstAlias<"fcomi", (COM_FIr ST1), 0>;
2717 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>;
2718 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>;
2719 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>;
2720 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>;
2721 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>;
2723 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op.
2724 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate
2725 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with
2727 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> {
2728 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"),
2729 (Inst RST:$op), EmitAlias>;
2730 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"),
2731 (Inst ST0), EmitAlias>;
2734 defm : FpUnaryAlias<"fadd", ADD_FST0r>;
2735 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>;
2736 defm : FpUnaryAlias<"fsub", SUB_FST0r>;
2737 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>;
2738 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>;
2739 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>;
2740 defm : FpUnaryAlias<"fmul", MUL_FST0r>;
2741 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>;
2742 defm : FpUnaryAlias<"fdiv", DIV_FST0r>;
2743 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>;
2744 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>;
2745 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>;
2746 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>;
2747 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>;
2748 defm : FpUnaryAlias<"fcompi", COM_FIPr>;
2749 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>;
2752 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they
2753 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute,
2754 // solely because gas supports it.
2755 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>;
2756 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>;
2757 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>;
2758 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>;
2759 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>;
2760 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>;
2762 // We accept "fnstsw %eax" even though it only writes %ax.
2763 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>;
2764 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>;
2765 def : InstAlias<"fnstsw" , (FNSTSW16r)>;
2767 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but
2768 // this is compatible with what GAS does.
2769 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2770 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>;
2771 def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2772 def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>;
2773 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2774 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>;
2775 def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2776 def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>;
2778 def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2779 def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>;
2780 def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2781 def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>;
2782 def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2783 def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>;
2786 // "imul <imm>, B" is an alias for "imul <imm>, B, B".
2787 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>;
2788 def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>;
2789 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>;
2790 def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>;
2791 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>;
2792 def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>;
2794 // inb %dx -> inb %al, %dx
2795 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>;
2796 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>;
2797 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>;
2798 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
2799 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
2800 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
2803 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
2804 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2805 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>;
2806 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2807 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>;
2808 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>;
2809 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>;
2810 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>;
2811 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>;
2813 // Force mov without a suffix with a segment and mem to prefer the 'l' form of
2814 // the move. All segment/mem forms are equivalent, this has the shortest
2816 def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>;
2817 def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>;
2819 // Match 'movq <largeimm>, <reg>' as an alias for movabsq.
2820 def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
2822 // Match 'movq GR64, MMX' as an alias for movd.
2823 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2824 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>;
2825 def : InstAlias<"movq {$src, $dst|$dst, $src}",
2826 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>;
2829 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>;
2830 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>;
2831 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>;
2832 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>;
2833 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>;
2834 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>;
2835 def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>;
2838 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>;
2839 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>;
2840 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>;
2841 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>;
2842 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>;
2843 def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
2844 // Note: No GR32->GR64 movzx form.
2846 // outb %dx -> outb %al, %dx
2847 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>;
2848 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>;
2849 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>;
2850 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
2851 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
2852 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
2854 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
2855 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
2856 // errors, since its encoding is the most compact.
2857 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>;
2859 // shld/shrd op,op -> shld op, op, CL
2860 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>;
2861 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>;
2862 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>;
2863 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>;
2864 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>;
2865 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>;
2867 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>;
2868 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>;
2869 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>;
2870 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>;
2871 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>;
2872 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>;
2874 /* FIXME: This is disabled because the asm matcher is currently incapable of
2875 * matching a fixed immediate like $1.
2876 // "shl X, $1" is an alias for "shl X".
2877 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> {
2878 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2879 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>;
2880 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2881 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>;
2882 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2883 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>;
2884 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2885 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>;
2886 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"),
2887 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>;
2888 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"),
2889 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>;
2890 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"),
2891 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>;
2892 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"),
2893 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>;
2896 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
2897 defm : ShiftRotateByOneAlias<"rcr", "RCR">;
2898 defm : ShiftRotateByOneAlias<"rol", "ROL">;
2899 defm : ShiftRotateByOneAlias<"ror", "ROR">;
2902 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms.
2903 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}",
2904 (TEST8rm GR8 :$val, i8mem :$mem), 0>;
2905 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}",
2906 (TEST16rm GR16:$val, i16mem:$mem), 0>;
2907 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}",
2908 (TEST32rm GR32:$val, i32mem:$mem), 0>;
2909 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}",
2910 (TEST64rm GR64:$val, i64mem:$mem), 0>;
2912 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms.
2913 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}",
2914 (XCHG8rm GR8 :$val, i8mem :$mem), 0>;
2915 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}",
2916 (XCHG16rm GR16:$val, i16mem:$mem), 0>;
2917 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}",
2918 (XCHG32rm GR32:$val, i32mem:$mem), 0>;
2919 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}",
2920 (XCHG64rm GR64:$val, i64mem:$mem), 0>;
2922 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
2923 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>;
2924 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2925 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>;
2926 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}",
2927 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>;
2928 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>;