1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
15 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
17 #include "MCTargetDesc/X86BaseInfo.h"
18 #include "X86RegisterInfo.h"
19 #include "llvm/ADT/DenseMap.h"
20 #include "llvm/Target/TargetInstrInfo.h"
22 #define GET_INSTRINFO_HEADER
23 #include "X86GenInstrInfo.inc"
26 class X86RegisterInfo;
29 namespace MachineCombinerPattern {
30 enum MC_PATTERN : int {
31 // These are commutative variants for reassociating a computation chain
40 } // end namespace MachineCombinerPattern
43 // X86 specific condition code. These correspond to X86_*_COND in
44 // X86InstrInfo.td. They must be kept in synch.
62 LAST_VALID_COND = COND_S,
64 // Artificial condition codes. These are used by AnalyzeBranch
65 // to indicate a block terminated with two conditional branches to
66 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
67 // which can't be represented on x86 with a single condition. These
68 // are never used in MachineInstrs.
75 // Turn condition code into conditional branch opcode.
76 unsigned GetCondBranchFromCond(CondCode CC);
78 /// \brief Return a set opcode for the given condition and whether it has
80 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
82 /// \brief Return a cmov opcode for the given condition, register size in
83 /// bytes, and operand type.
84 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
85 bool HasMemoryOperand = false);
87 // Turn CMov opcode into condition code.
88 CondCode getCondFromCMovOpc(unsigned Opc);
90 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
91 /// e.g. turning COND_E to COND_NE.
92 CondCode GetOppositeBranchCondition(CondCode CC);
93 } // end namespace X86;
96 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
97 /// a reference to a stub for a global, not the global itself.
98 inline static bool isGlobalStubReference(unsigned char TargetFlag) {
100 case X86II::MO_DLLIMPORT: // dllimport stub.
101 case X86II::MO_GOTPCREL: // rip-relative GOT reference.
102 case X86II::MO_GOT: // normal GOT reference.
103 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
104 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
105 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
112 /// isGlobalRelativeToPICBase - Return true if the specified global value
113 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
114 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
115 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
116 switch (TargetFlag) {
117 case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
118 case X86II::MO_GOT: // isPICStyleGOT: other global.
119 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
120 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
121 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
122 case X86II::MO_TLVP: // ??? Pretty sure..
129 inline static bool isScale(const MachineOperand &MO) {
131 (MO.getImm() == 1 || MO.getImm() == 2 ||
132 MO.getImm() == 4 || MO.getImm() == 8);
135 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
136 if (MI->getOperand(Op).isFI()) return true;
137 return Op+X86::AddrSegmentReg <= MI->getNumOperands() &&
138 MI->getOperand(Op+X86::AddrBaseReg).isReg() &&
139 isScale(MI->getOperand(Op+X86::AddrScaleAmt)) &&
140 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
141 (MI->getOperand(Op+X86::AddrDisp).isImm() ||
142 MI->getOperand(Op+X86::AddrDisp).isGlobal() ||
143 MI->getOperand(Op+X86::AddrDisp).isCPI() ||
144 MI->getOperand(Op+X86::AddrDisp).isJTI());
147 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
148 if (MI->getOperand(Op).isFI()) return true;
149 return Op+X86::AddrNumOperands <= MI->getNumOperands() &&
150 MI->getOperand(Op+X86::AddrSegmentReg).isReg() &&
154 class X86InstrInfo final : public X86GenInstrInfo {
155 X86Subtarget &Subtarget;
156 const X86RegisterInfo RI;
158 /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
159 /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps.
161 typedef DenseMap<unsigned,
162 std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
163 RegOp2MemOpTableType RegOp2MemOpTable2Addr;
164 RegOp2MemOpTableType RegOp2MemOpTable0;
165 RegOp2MemOpTableType RegOp2MemOpTable1;
166 RegOp2MemOpTableType RegOp2MemOpTable2;
167 RegOp2MemOpTableType RegOp2MemOpTable3;
168 RegOp2MemOpTableType RegOp2MemOpTable4;
170 /// MemOp2RegOpTable - Load / store unfolding opcode map.
172 typedef DenseMap<unsigned,
173 std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
174 MemOp2RegOpTableType MemOp2RegOpTable;
176 static void AddTableEntry(RegOp2MemOpTableType &R2MTable,
177 MemOp2RegOpTableType &M2RTable,
178 unsigned RegOp, unsigned MemOp, unsigned Flags);
180 virtual void anchor();
183 explicit X86InstrInfo(X86Subtarget &STI);
185 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
186 /// such, whenever a client has an instance of instruction info, it should
187 /// always be able to get register info as well (through this method).
189 const X86RegisterInfo &getRegisterInfo() const { return RI; }
191 /// getSPAdjust - This returns the stack pointer adjustment made by
192 /// this instruction. For x86, we need to handle more complex call
193 /// sequences involving PUSHes.
194 int getSPAdjust(const MachineInstr *MI) const override;
196 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
197 /// extension instruction. That is, it's like a copy where it's legal for the
198 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
199 /// true, then it's expected the pre-extension value is available as a subreg
200 /// of the result register. This also returns the sub-register index in
202 bool isCoalescableExtInstr(const MachineInstr &MI,
203 unsigned &SrcReg, unsigned &DstReg,
204 unsigned &SubIdx) const override;
206 unsigned isLoadFromStackSlot(const MachineInstr *MI,
207 int &FrameIndex) const override;
208 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
209 /// stack locations as well. This uses a heuristic so it isn't
210 /// reliable for correctness.
211 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
212 int &FrameIndex) const override;
214 unsigned isStoreToStackSlot(const MachineInstr *MI,
215 int &FrameIndex) const override;
216 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
217 /// stack locations as well. This uses a heuristic so it isn't
218 /// reliable for correctness.
219 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
220 int &FrameIndex) const override;
222 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
223 AliasAnalysis *AA) const override;
224 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
225 unsigned DestReg, unsigned SubIdx,
226 const MachineInstr *Orig,
227 const TargetRegisterInfo &TRI) const override;
229 /// Given an operand within a MachineInstr, insert preceding code to put it
230 /// into the right format for a particular kind of LEA instruction. This may
231 /// involve using an appropriate super-register instead (with an implicit use
232 /// of the original) or creating a new virtual register and inserting COPY
233 /// instructions to get the data into the right class.
235 /// Reference parameters are set to indicate how caller should add this
236 /// operand to the LEA instruction.
237 bool classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
238 unsigned LEAOpcode, bool AllowSP,
239 unsigned &NewSrc, bool &isKill,
240 bool &isUndef, MachineOperand &ImplicitOp) const;
242 /// convertToThreeAddress - This method must be implemented by targets that
243 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
244 /// may be able to convert a two-address instruction into a true
245 /// three-address instruction on demand. This allows the X86 target (for
246 /// example) to convert ADD and SHL instructions into LEA instructions if they
247 /// would require register copies due to two-addressness.
249 /// This method returns a null pointer if the transformation cannot be
250 /// performed, otherwise it returns the new instruction.
252 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
253 MachineBasicBlock::iterator &MBBI,
254 LiveVariables *LV) const override;
256 /// commuteInstruction - We have a few instructions that must be hacked on to
259 MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
261 bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
262 unsigned &SrcOpIdx2) const override;
265 bool isUnpredicatedTerminator(const MachineInstr* MI) const override;
266 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
267 MachineBasicBlock *&FBB,
268 SmallVectorImpl<MachineOperand> &Cond,
269 bool AllowModify) const override;
270 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
271 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
272 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
273 DebugLoc DL) const override;
274 bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond,
275 unsigned, unsigned, int&, int&, int&) const override;
276 void insertSelect(MachineBasicBlock &MBB,
277 MachineBasicBlock::iterator MI, DebugLoc DL,
278 unsigned DstReg, ArrayRef<MachineOperand> Cond,
279 unsigned TrueReg, unsigned FalseReg) const override;
280 void copyPhysReg(MachineBasicBlock &MBB,
281 MachineBasicBlock::iterator MI, DebugLoc DL,
282 unsigned DestReg, unsigned SrcReg,
283 bool KillSrc) const override;
284 void storeRegToStackSlot(MachineBasicBlock &MBB,
285 MachineBasicBlock::iterator MI,
286 unsigned SrcReg, bool isKill, int FrameIndex,
287 const TargetRegisterClass *RC,
288 const TargetRegisterInfo *TRI) const override;
290 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
291 SmallVectorImpl<MachineOperand> &Addr,
292 const TargetRegisterClass *RC,
293 MachineInstr::mmo_iterator MMOBegin,
294 MachineInstr::mmo_iterator MMOEnd,
295 SmallVectorImpl<MachineInstr*> &NewMIs) const;
297 void loadRegFromStackSlot(MachineBasicBlock &MBB,
298 MachineBasicBlock::iterator MI,
299 unsigned DestReg, int FrameIndex,
300 const TargetRegisterClass *RC,
301 const TargetRegisterInfo *TRI) const override;
303 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
304 SmallVectorImpl<MachineOperand> &Addr,
305 const TargetRegisterClass *RC,
306 MachineInstr::mmo_iterator MMOBegin,
307 MachineInstr::mmo_iterator MMOEnd,
308 SmallVectorImpl<MachineInstr*> &NewMIs) const;
310 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
312 /// foldMemoryOperand - If this target supports it, fold a load or store of
313 /// the specified stack slot into the specified machine instruction for the
314 /// specified operand(s). If this is possible, the target should perform the
315 /// folding and return true, otherwise it should return false. If it folds
316 /// the instruction, it is likely that the MachineInstruction the iterator
317 /// references has been changed.
318 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
319 ArrayRef<unsigned> Ops,
320 MachineBasicBlock::iterator InsertPt,
321 int FrameIndex) const override;
323 /// foldMemoryOperand - Same as the previous version except it allows folding
324 /// of any load and store from / to any address, not just from a specific
326 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
327 ArrayRef<unsigned> Ops,
328 MachineBasicBlock::iterator InsertPt,
329 MachineInstr *LoadMI) const override;
331 /// canFoldMemoryOperand - Returns true if the specified load / store is
332 /// folding is possible.
333 bool canFoldMemoryOperand(const MachineInstr *,
334 ArrayRef<unsigned>) const override;
336 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
337 /// a store or a load and a store into two or more instruction. If this is
338 /// possible, returns true as well as the new instructions by reference.
339 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
340 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
341 SmallVectorImpl<MachineInstr*> &NewMIs) const override;
343 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
344 SmallVectorImpl<SDNode*> &NewNodes) const override;
346 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
347 /// instruction after load / store are unfolded from an instruction of the
348 /// specified opcode. It returns zero if the specified unfolding is not
349 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
350 /// index of the operand which will hold the register holding the loaded
352 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
353 bool UnfoldLoad, bool UnfoldStore,
354 unsigned *LoadRegIndex = nullptr) const override;
356 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
357 /// to determine if two loads are loading from the same base address. It
358 /// should only return true if the base pointers are the same and the
359 /// only differences between the two addresses are the offset. It also returns
360 /// the offsets by reference.
361 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
362 int64_t &Offset2) const override;
364 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
365 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
366 /// be scheduled togther. On some targets if two loads are loading from
367 /// addresses in the same cache line, it's better if they are scheduled
368 /// together. This function takes two integers that represent the load offsets
369 /// from the common base address. It returns true if it decides it's desirable
370 /// to schedule the two loads together. "NumLoads" is the number of loads that
371 /// have already been scheduled after Load1.
372 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
373 int64_t Offset1, int64_t Offset2,
374 unsigned NumLoads) const override;
376 bool shouldScheduleAdjacent(MachineInstr* First,
377 MachineInstr *Second) const override;
379 void getNoopForMachoTarget(MCInst &NopInst) const override;
382 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
384 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
385 /// instruction that defines the specified register class.
386 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
388 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
389 /// would clobber the EFLAGS condition register. Note the result may be
390 /// conservative. If it cannot definitely determine the safety after visiting
391 /// a few instructions in each direction it assumes it's not safe.
392 bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
393 MachineBasicBlock::iterator I) const;
395 static bool isX86_64ExtendedReg(const MachineOperand &MO) {
396 if (!MO.isReg()) return false;
397 return X86II::isX86_64ExtendedReg(MO.getReg());
400 /// getGlobalBaseReg - Return a virtual register initialized with the
401 /// the global base register value. Output instructions required to
402 /// initialize the register in the function entry block, if necessary.
404 unsigned getGlobalBaseReg(MachineFunction *MF) const;
406 std::pair<uint16_t, uint16_t>
407 getExecutionDomain(const MachineInstr *MI) const override;
409 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
412 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
413 const TargetRegisterInfo *TRI) const override;
414 unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
415 const TargetRegisterInfo *TRI) const override;
416 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
417 const TargetRegisterInfo *TRI) const override;
419 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
421 ArrayRef<MachineOperand> MOs,
422 MachineBasicBlock::iterator InsertPt,
423 unsigned Size, unsigned Alignment,
424 bool AllowCommute) const;
427 getUnconditionalBranch(MCInst &Branch,
428 const MCSymbolRefExpr *BranchTarget) const override;
430 void getTrap(MCInst &MI) const override;
432 unsigned getJumpInstrTableEntryBound() const override;
434 bool isHighLatencyDef(int opc) const override;
436 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
437 const MachineRegisterInfo *MRI,
438 const MachineInstr *DefMI, unsigned DefIdx,
439 const MachineInstr *UseMI,
440 unsigned UseIdx) const override;
443 bool useMachineCombiner() const override {
447 /// Return true when there is potentially a faster code sequence
448 /// for an instruction chain ending in <Root>. All potential patterns are
449 /// output in the <Pattern> array.
452 SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &P) const override;
454 /// When hasPattern() finds a pattern, this function generates the
455 /// instructions that could replace the original code sequence.
456 void genAlternativeCodeSequence(
457 MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
458 SmallVectorImpl<MachineInstr *> &InsInstrs,
459 SmallVectorImpl<MachineInstr *> &DelInstrs,
460 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
462 /// analyzeCompare - For a comparison instruction, return the source registers
463 /// in SrcReg and SrcReg2 if having two register operands, and the value it
464 /// compares against in CmpValue. Return true if the comparison instruction
466 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
467 unsigned &SrcReg2, int &CmpMask,
468 int &CmpValue) const override;
470 /// optimizeCompareInstr - Check if there exists an earlier instruction that
471 /// operates on the same source operands and sets flags in the same way as
472 /// Compare; remove Compare if possible.
473 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
474 unsigned SrcReg2, int CmpMask, int CmpValue,
475 const MachineRegisterInfo *MRI) const override;
477 /// optimizeLoadInstr - Try to remove the load by folding it to a register
478 /// operand at the use. We fold the load instructions if and only if the
479 /// def and use are in the same BB. We only look at one load and see
480 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
481 /// defined by the load we are trying to fold. DefMI returns the machine
482 /// instruction that defines FoldAsLoadDefReg, and the function returns
483 /// the machine instruction generated due to folding.
484 MachineInstr* optimizeLoadInstr(MachineInstr *MI,
485 const MachineRegisterInfo *MRI,
486 unsigned &FoldAsLoadDefReg,
487 MachineInstr *&DefMI) const override;
490 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
491 MachineFunction::iterator &MFI,
492 MachineBasicBlock::iterator &MBBI,
493 LiveVariables *LV) const;
495 /// isFrameOperand - Return true and the FrameIndex if the specified
496 /// operand and follow operands form a reference to the stack frame.
497 bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
498 int &FrameIndex) const;
501 } // End llvm namespace